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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id m64sm10052931wmm.41.2021.08.01.16.42.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Aug 2021 16:42:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nF2CPaID+VIHHyjgrg/yG4IgKh5kbi2GWmyHFcP4Gh4=; b=NyS1QGTbvNT1A496xSOlAv7v5TyTHcuKQEWXPuT5KDkTsVMg1iuVFs0eMa4nRkQ8nf L3iKqS/WLujpUC6V3fC7VPTOlFSbFtFTjjYahQretqjiPMBUAIy9gkZvz39bfdQkkauO IVZU/H749ZKAqGJwfFtbRgO2rliS4hyJMa2WbDP/Lh5UAYNGr0/5Lk1Ibab61H10ils/ 9slzpA1TWT3BdLJPg8Akaf0xFup93whqBwLveFM8NlishOrzJz3EJvl0h9wMXGfzdDMO QnMewp2TjN1YOLU9SkT5mFYBBrlUxYTrHO3w092CglKIwcqKKR0TSZ0Pt6SE1W1wWWUZ QARw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=nF2CPaID+VIHHyjgrg/yG4IgKh5kbi2GWmyHFcP4Gh4=; b=qOAV9m2joADaAqe916zbA3+7jFOq6DUn6JOJzqFLlFp1BTcFXKdxLggZe2A7eoinBQ EkfKEYJ02jatnNQXQxsrAn0cX8Jrh6ooJrRh8BVrhBIBpqQjVBlv3TRuZdBbZW4phjBB +HpWRtD2cft6+1VEzpvn/oyva5FwezICJKSF1pB42a8yFFMYYaOJ5g9j6vmF9RpA/c2P jlVgHrUomPJmsHrjOviRPpFuuVvwWLXUHw7HJ8Nt+nwjaJLLimbxhD/CW1PS3zYce+lO LS9BRa4qo4I0+305yXuaiOZbhYXBi6BB8Y7ohLDWcN+rTpsMMQUbh/vyCJtYoGSXSfDk U2GA== X-Gm-Message-State: AOAM531Tnu8RumSpoNBVEjef8JZlK038fH8bGWaHAMhgEK5m+9xHLU3o oc91fnDGjf8H9wIYsYxNqK0= X-Google-Smtp-Source: ABdhPJxkS0gW73A5jvBmWmcVYCgTOH9/iIoiHGHioWrmRKPSzUZdpw87WBXNowYrRTtZHbEmY4K6YQ== X-Received: by 2002:adf:db85:: with SMTP id u5mr14538829wri.167.1627861328964; Sun, 01 Aug 2021 16:42:08 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-6.2 1/4] target/mips: Simpify PREF opcode Date: Mon, 2 Aug 2021 01:41:59 +0200 Message-Id: <20210801234202.3167676-2-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210801234202.3167676-1-f4bug@amsat.org> References: <20210801234202.3167676-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1627861332410100001 check_insn() checks for any bit in the set, and INSN_R5900 is just another bit added to the set. No need to special-case it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tcg/translate.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 34a96159d15..05efd25e29d 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15738,12 +15738,8 @@ static bool decode_opc_legacy(CPUMIPSState *env, D= isasContext *ctx) /* Treat as NOP. */ break; case OPC_PREF: - if (ctx->insn_flags & INSN_R5900) { - /* Treat as NOP. */ - } else { - check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1); - /* Treat as NOP. */ - } + check_insn(ctx, ISA_MIPS4 | ISA_MIPS_R1 | INSN_R5900); + /* Treat as NOP. */ break; =20 /* Floating point (COP1). */ --=20 2.31.1 From nobody Fri May 17 11:05:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1627861335; cv=none; d=zohomail.com; s=zohoarc; b=G+ZTX17tYhlWwwHEtRhid1btnTfaRpqbpwR7Fj7o0w8UAyZBgjh0lfkbNlubpgHLEZyGJrEzOG8BFEIQpzLMSI6HyBPflJWFQop8HlndCzt83Ru+TAH5nkCDnAzmTaX8wZdq6s2wnh//rpoCbhLLLbt2vnKil3k+TbV0RvxqbEE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1627861335; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2Ht5ISZ2OXCCd1H3XZUszoZrx9DeFBjuRyEDw8rJrxw=; b=PFMFLhnbCJnQWzkWerPH6Ul/8uBnabQQog7AcO0f+HEih7nnrbcYKZxo79l98jwARF9H/Fv2by3OcET3WW7QRetzEly5ytChUFvOOyVDKqxh1TdP24KmufCj95IhtUf3Z3MmM9horHKDySw1zUYw2kEBIktYpCofuj3mgyLgKGY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) by mx.zohomail.com with SMTPS id 1627861335405252.7261229894532; Sun, 1 Aug 2021 16:42:15 -0700 (PDT) Received: by mail-wr1-f44.google.com with SMTP id z4so19322643wrv.11 for ; Sun, 01 Aug 2021 16:42:14 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id q14sm9231252wrs.8.2021.08.01.16.42.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Aug 2021 16:42:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2Ht5ISZ2OXCCd1H3XZUszoZrx9DeFBjuRyEDw8rJrxw=; b=jykHNSz8UFH0PNEe19lGaiItMn/DT/Bdiyp3H7TorlSFFghnJ3Es3EqeYloZcKx4e/ jOJ7UJ6i/hUYckC/v7RiSQPcFNNZC6zGTIBbjgS3vkQU2jp1xeMSswPo6PRU5QZ9/+5q Xlzw0uJ5Z52mBUlWviPdKDoOLerV0nRAhT6koe0ApLBDKre+yrDBtgpYhYl4uiydVvHq ux6kjLHJRo42tzylPvPORwa4a6205Dhs3Xv2GDohXF8udztCW28/XWHlhKIHv1epN6dy ODxtDNpAebXb7v6tYwUEme8CLKNLcah3ogmarWw1EL+aBhIYLumhE4dSXCxRlg95UkXm dVNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=2Ht5ISZ2OXCCd1H3XZUszoZrx9DeFBjuRyEDw8rJrxw=; b=G5Ds0B0ZLLi6s9DqZK+r6XScdPHQuZ24ZfqGncVQG4TVjqgx5NdD7UGtUhbkB1+J/6 abJjfdtbsDvVqy8tKAXsbhSrvUYChvlJbsT44W0wlHRE8O+HW5u9la7gR9DWqRZ8sX7+ bVmsgbUVi6mbawCC01/p/HhzUbSaZ078+P/Ju9+X/vSZH5nOwT+sFpRPzot0GFKwtO6t dDnsUyXgLv69/JfbaQOnv115GMWe73Vo5Y28lRfG0SWtpdRsqonh+fgETERqmYBCtdVY 1yMA7ksmQc61uEfh04O11f4kzARmpaIix1P39w6SWXmdlT1hgXKX5qe4EXUitsJg/HBh AsSw== X-Gm-Message-State: AOAM533Ak+waGJozmn7SvfpnZcAnIRoEXPGSHbIa2FyAs2nHUdI0l+9f LHNeBJGkEv0F8i7thpQrLW4= X-Google-Smtp-Source: ABdhPJwYRzFXh64lBOmR9+Ni1v7rRcBcO5TD9OinftcFpCV+xmy1noOipyf54AnphZVFpS7mWVUPgg== X-Received: by 2002:a5d:5650:: with SMTP id j16mr14388125wrw.46.1627861333590; Sun, 01 Aug 2021 16:42:13 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-6.2 2/4] target/mips: Decode vendor extensions before MIPS ISAs Date: Mon, 2 Aug 2021 01:42:00 +0200 Message-Id: <20210801234202.3167676-3-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210801234202.3167676-1-f4bug@amsat.org> References: <20210801234202.3167676-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1627861336868100001 In commit ffc672aa977 ("target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree") we misplaced the decoder call. Move it to the correct place. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tcg/translate.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 05efd25e29d..9572cc56947 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -16093,6 +16093,11 @@ static void decode_opc(CPUMIPSState *env, DisasCon= text *ctx) =20 /* Transition to the auto-generated decoder. */ =20 + /* Vendor extensions */ + if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opc= ode)) { + return; + } + /* ISA extensions */ if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) { return; @@ -16102,9 +16107,6 @@ static void decode_opc(CPUMIPSState *env, DisasCont= ext *ctx) if (cpu_supports_isa(env, ISA_MIPS_R6) && decode_isa_rel6(ctx, ctx->op= code)) { return; } - if (cpu_supports_isa(env, INSN_R5900) && decode_ext_txx9(ctx, ctx->opc= ode)) { - return; - } =20 if (decode_opc_legacy(env, ctx)) { return; --=20 2.31.1 From nobody Fri May 17 11:05:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) client-ip=209.85.128.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1627861340; cv=none; d=zohomail.com; s=zohoarc; b=kOTj5s5qq7OItR8MdTTafo16HsPz6OTwewwkS5oI4rHBM3J1LlbqPvNk8mHI5L98AYDU4pexQazkuk3u6b1Su96pdpG6T+9L9fxdANQdXE21+JK0MSiNzzKaNAwykoXmCQWQfp1BVPrmCYW3tHT5K7f7XxzxSqjnadf3zD8ZR50= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1627861340; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MEexVZpOmMQGQKbdMdmdE8d8zbgl8YhKPkuKPBINUxU=; b=e/maaIO1RhxAhxnry6E+/JHe7HBnwD2hB/kSLrDW14MwLY1Vg90S1ikknVhJRNP0EE6xVBWsVuLUZ6MX5gqUYH/oQHT6m3oO78LueDIwrnBRGCwprYTuDs5BIfpJcb1SqNOvTdbibG20gob37PXLfFbgTqN/yAIdS3LWV9YssSY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) by mx.zohomail.com with SMTPS id 1627861340145607.4864112214694; Sun, 1 Aug 2021 16:42:20 -0700 (PDT) Received: by mail-wm1-f42.google.com with SMTP id n28-20020a05600c3b9cb02902552e60df56so9910184wms.0 for ; Sun, 01 Aug 2021 16:42:19 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.. 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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id t8sm9755115wmj.5.2021.08.01.16.42.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Aug 2021 16:42:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MEexVZpOmMQGQKbdMdmdE8d8zbgl8YhKPkuKPBINUxU=; b=XKBjKUtJ9i1o6TdDS1uCHWl49NustW8bcFRQ1Pt1Pkmbv2e8TsAe9IbadtHSn78DbS V+RzLczrrmyJLwlwQGmCwS0mU21wUgTkawA+K5u8UUOFKBWGLp6V35HaPCt5pNrOr/up jM4lvsLPZxDf7CK0vus6cGOgdOLGSeBFGbg+cv2v3vwOmR4cc31agmdMfsjnMbU5beze a/+HNLuahczJ6QP6z9+X/rKOusDrit8c3u3EO/VI9uxpUCWD6GTaBi9ij/YlawGK+k8q gYGAFe1yik4f7QK7HlD9j+RowDAdhMwIOZLR3V+RPD5ZFcHej/djxy/Ed/XcPU0Keq3h riCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=MEexVZpOmMQGQKbdMdmdE8d8zbgl8YhKPkuKPBINUxU=; b=C21gYPXlNuX/A54pB1mkDaKySWd/xS2Y3a+R7UaifUwq/0a4T/CZ+Ode1HANTEp8fi +nGqh5UEhagrA87qIkDc/foZmSvj+CgTLhPsA+ZPM4936diuzuOF2DgV/ekzkGXS0QYG KAVnNTdaK71ypLoqXtJjOdO6Z4Ygx2j9faUDOy4EYmATKox9/tvWHgrNmmfBYTk47wm/ GFpHURca3oVMlRE7UnW2wDfGLLBI/qfE3fpWmYVovCPE/A3ACM5vJcQUGW+lPdvQUJSk pIWrXrcGWFrXylCkZ7Zv1Q+DbBG66/Wq8BIlG2Qu+2YRgbMV8RwFLYgpx7rgDVQUmK2/ ZiCQ== X-Gm-Message-State: AOAM5321UG7MgfuyljWoNKF+UP4eojJW1OjVicqYk43LwKzqnS4j9PKa 0TYEq7TVtl2CWvkorG5cgL4= X-Google-Smtp-Source: ABdhPJwLAt2ETijowAWtJpYpX9m4hUeDpTFfJi8C4bh7yT00oJioRIjQ1xHFEUykPMP/eS/J1wtPrA== X-Received: by 2002:a1c:5449:: with SMTP id p9mr13920931wmi.101.1627861338260; Sun, 01 Aug 2021 16:42:18 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-6.2 3/4] target/mips: Merge 32-bit/64-bit release6 decodetree definitions Date: Mon, 2 Aug 2021 01:42:01 +0200 Message-Id: <20210801234202.3167676-4-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210801234202.3167676-1-f4bug@amsat.org> References: <20210801234202.3167676-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1627861340675100001 We don't need to maintain 2 sets of decodetree definitions. Merge them into a single file. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tcg/mips64r6.decode | 27 ------------------- .../mips/tcg/{mips32r6.decode =3D> rel6.decode} | 13 +++++++++ target/mips/tcg/rel6_translate.c | 16 ++++------- target/mips/tcg/meson.build | 3 +-- 4 files changed, 19 insertions(+), 40 deletions(-) delete mode 100644 target/mips/tcg/mips64r6.decode rename target/mips/tcg/{mips32r6.decode =3D> rel6.decode} (69%) diff --git a/target/mips/tcg/mips64r6.decode b/target/mips/tcg/mips64r6.dec= ode deleted file mode 100644 index b58d8009ccd..00000000000 --- a/target/mips/tcg/mips64r6.decode +++ /dev/null @@ -1,27 +0,0 @@ -# MIPS64 Release 6 instruction set -# -# Copyright (C) 2020 Philippe Mathieu-Daud=C3=A9 -# -# SPDX-License-Identifier: LGPL-2.1-or-later -# -# Reference: -# MIPS Architecture for Programmers Volume II-A -# The MIPS64 Instruction Set Reference Manual, Revision 6.06 -# (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06) -# - -&rtype rs rt rd sa !extern - -&REMOVED !extern - -@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype - -DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa - -REMOVED 011010 ----- ----- ---------------- # LDL -REMOVED 011011 ----- ----- ---------------- # LDR -REMOVED 101100 ----- ----- ---------------- # SDL -REMOVED 101101 ----- ----- ---------------- # SDR - -REMOVED 110100 ----- ----- ---------------- # LLD -REMOVED 111100 ----- ----- ---------------- # SCD diff --git a/target/mips/tcg/mips32r6.decode b/target/mips/tcg/rel6.decode similarity index 69% rename from target/mips/tcg/mips32r6.decode rename to target/mips/tcg/rel6.decode index 837c991edc5..ed069c51662 100644 --- a/target/mips/tcg/mips32r6.decode +++ b/target/mips/tcg/rel6.decode @@ -5,21 +5,29 @@ # SPDX-License-Identifier: LGPL-2.1-or-later # # Reference: +# # MIPS Architecture for Programmers Volume II-A # The MIPS32 Instruction Set Reference Manual, Revision 6.06 # (Document Number: MD00086-2B-MIPS32BIS-AFP-06.06) # +# MIPS Architecture for Programmers Volume II-A +# The MIPS64 Instruction Set Reference Manual, Revision 6.06 +# (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06) =20 &rtype rs rt rd sa =20 @lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype =20 LSA 000000 ..... ..... ..... 000 .. 000101 @lsa +DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa =20 REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3) =20 REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2 =20 +REMOVED 011010 ----- ----- ---------------- # LDL +REMOVED 011011 ----- ----- ---------------- # LDR + REMOVED 011111 ----- ----- ---------- 011001 # LWLE REMOVED 011111 ----- ----- ---------- 011010 # LWRE REMOVED 011111 ----- ----- ---------- 100001 # SWLE @@ -28,9 +36,14 @@ REMOVED 011111 ----- ----- ---------- 10001= 0 # SWRE REMOVED 100010 ----- ----- ---------------- # LWL REMOVED 100110 ----- ----- ---------------- # LWR REMOVED 101010 ----- ----- ---------------- # SWL +REMOVED 101100 ----- ----- ---------------- # SDL +REMOVED 101101 ----- ----- ---------------- # SDR REMOVED 101110 ----- ----- ---------------- # SWR =20 REMOVED 101111 ----- ----- ---------------- # CACHE + REMOVED 110000 ----- ----- ---------------- # LL REMOVED 110011 ----- ----- ---------------- # PREF +REMOVED 110100 ----- ----- ---------------- # LLD REMOVED 111000 ----- ----- ---------------- # SC +REMOVED 111100 ----- ----- ---------------- # SCD diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_transl= ate.c index 0354370927d..ae2e023a817 100644 --- a/target/mips/tcg/rel6_translate.c +++ b/target/mips/tcg/rel6_translate.c @@ -13,9 +13,8 @@ #include "exec/helper-gen.h" #include "translate.h" =20 -/* Include the auto-generated decoder. */ -#include "decode-mips32r6.c.inc" -#include "decode-mips64r6.c.inc" +/* Include the auto-generated decoders. */ +#include "decode-rel6.c.inc" =20 bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a) { @@ -31,13 +30,8 @@ static bool trans_LSA(DisasContext *ctx, arg_rtype *a) =20 static bool trans_DLSA(DisasContext *ctx, arg_rtype *a) { + if (TARGET_LONG_BITS !=3D 64) { + return false; + } return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa); } - -bool decode_isa_rel6(DisasContext *ctx, uint32_t insn) -{ - if (TARGET_LONG_BITS =3D=3D 64 && decode_mips64r6(ctx, insn)) { - return true; - } - return decode_mips32r6(ctx, insn); -} diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build index bf4001e5741..70fa3dd57df 100644 --- a/target/mips/tcg/meson.build +++ b/target/mips/tcg/meson.build @@ -1,6 +1,5 @@ gen =3D [ - decodetree.process('mips32r6.decode', extra_args: '--static-decode=3Ddec= ode_mips32r6'), - decodetree.process('mips64r6.decode', extra_args: '--static-decode=3Ddec= ode_mips64r6'), + decodetree.process('rel6.decode', extra_args: ['--decode=3Ddecode_isa_re= l6']), decodetree.process('msa.decode', extra_args: '--decode=3Ddecode_ase_msa'= ), decodetree.process('tx79.decode', extra_args: '--static-decode=3Ddecode_= tx79'), ] --=20 2.31.1 From nobody Fri May 17 11:05:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.43 as permitted sender) client-ip=209.85.128.43; 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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id v12sm9261748wrq.59.2021.08.01.16.42.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Aug 2021 16:42:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uT/G/TGwLnMu4sg8giZ2uNGklRryTJ16DUSDHo2QPeA=; b=S8ABpkbQ/VQN8+oNZgUjXBYQ5yj//CeCo4+GqWdYX7+8ojdAIc4AAHaO9gaDjlJcxX kXAdZpY4O5axPFpEJU0g4ap9r/rQ+eKhL0twPQGublUrxF/LvDbaTKhpnbEwxc3gVCGU +PNfLtUdPFeBXa6YDq3C1S6pfjLbfK/xTCqc+QlEhQ5fgRy3RT/IfELZgNYQR1n528gF /N7NIJm0VArQzfyD8A8qS0AS14+WQyrnjmcBoXHDEGDDenM6HokHO8MkPeovKIQIpGmE AHPYUm0Xo/5BbxUAYtriW44QfxEoe0VZxcWTh1WjCXhAzh1mgqwZGYDdSJU2TJkn/Vsp XV/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=uT/G/TGwLnMu4sg8giZ2uNGklRryTJ16DUSDHo2QPeA=; b=kz4mN6/pvdnJRttuDwXDHk1FSvJu8m2cqk6Pd4ww6CvnHvLtYB3G//GI7ZH44NKJaD qx8lJA5Rqm+HQXSyclJvaxTj/mQ3/SRDb49qz6Iomiuoxt2veNEKMiOh8Rcg/ck/C2kt L31RWEaimu5uGeTEe+nYQYS6f/4IkfQB185j6X39xHbR2hbkW08smnwNKeJtomjVbbR/ ajgHZI4zZ60ZAVVa0G5MP+dtD+KOhsCYyXd3+7JKZ/KYVsyBuubQR/JgoWSxuKnvb5Es LsH8AHBCey4GewaZLhcJ+FGce21hRu/y5/AIyAdBN8LskXydPQPzRrC4ipn6sd2my+sM NZjA== X-Gm-Message-State: AOAM533AN+ylNoufX3rpBNB/kZQW+xVxVJqWUk3CWZ9MgBDvH/yaHon4 cBZUDl9/LEq5j+/DketVdjs= X-Google-Smtp-Source: ABdhPJyjFwkRCV1BKFgWl/JPp8iS7px4ltxtLOEbvSNwqCRhixDFHyI9jtNJk2kr5ldvfzp+emXPcQ== X-Received: by 2002:a1c:3b07:: with SMTP id i7mr14164358wma.7.1627861343034; Sun, 01 Aug 2021 16:42:23 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aurelien Jarno , Aleksandar Rikalo , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH-for-6.2 4/4] target/mips: Rename 'rtype' as 'r' Date: Mon, 2 Aug 2021 01:42:02 +0200 Message-Id: <20210801234202.3167676-5-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210801234202.3167676-1-f4bug@amsat.org> References: <20210801234202.3167676-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1627861346842100001 We'll soon have more opcode and decoded arguments, and 'rtype' is not very helpful. Naming it simply 'r' ease reviewing the .decode files when we have many opcodes. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tcg/msa.decode | 4 +-- target/mips/tcg/rel6.decode | 4 +-- target/mips/tcg/tx79.decode | 14 ++++---- target/mips/tcg/msa_translate.c | 4 +-- target/mips/tcg/rel6_translate.c | 4 +-- target/mips/tcg/tx79_translate.c | 62 ++++++++++++++++---------------- 6 files changed, 46 insertions(+), 46 deletions(-) diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index bf132e36b9b..74d99f6862c 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -11,11 +11,11 @@ # - The MIPS64 SIMD Architecture Module, Revision 1.12 # (Document Number: MD00868-1D-MSA64-AFP-01.12) =20 -&rtype rs rt rd sa +&r rs rt rd sa =20 &msa_bz df wt s16 =20 -@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r @bz ...... ... .. wt:5 s16:16 &msa_bz df=3D3 @bz_df ...... ... df:2 wt:5 s16:16 &msa_bz =20 diff --git a/target/mips/tcg/rel6.decode b/target/mips/tcg/rel6.decode index ed069c51662..d6989cf56e8 100644 --- a/target/mips/tcg/rel6.decode +++ b/target/mips/tcg/rel6.decode @@ -14,9 +14,9 @@ # The MIPS64 Instruction Set Reference Manual, Revision 6.06 # (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06) =20 -&rtype rs rt rd sa +&r rs rt rd sa =20 -@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &rtype +@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r =20 LSA 000000 ..... ..... ..... 000 .. 000101 @lsa DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa diff --git a/target/mips/tcg/tx79.decode b/target/mips/tcg/tx79.decode index 03a25a5096d..57d87a2076a 100644 --- a/target/mips/tcg/tx79.decode +++ b/target/mips/tcg/tx79.decode @@ -11,20 +11,20 @@ # when creating helpers common to those for the individual # instruction patterns. =20 -&rtype rs rt rd sa +&r rs rt rd sa =20 -&itype base rt offset +&i base rt offset =20 ########################################################################### # Named instruction formats. These are generally used to # reduce the amount of duplication between instruction patterns. =20 -@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &rtype sa=3D0 -@rt_rd ...... ..... rt:5 rd:5 ..... ...... &rtype rs=3D0 sa= =3D0 -@rs ...... rs:5 ..... .......... ...... &rtype rt=3D0 rd= =3D0 sa=3D0 -@rd ...... .......... rd:5 ..... ...... &rtype rs=3D0 rt= =3D0 sa=3D0 +@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &r sa=3D0 +@rt_rd ...... ..... rt:5 rd:5 ..... ...... &r sa=3D0 rs=3D0 +@rs ...... rs:5 ..... .......... ...... &r sa=3D0 rt= =3D0 rd=3D0 +@rd ...... .......... rd:5 ..... ...... &r sa=3D0 rs=3D0 r= t=3D0 =20 -@ldst ...... base:5 rt:5 offset:16 &itype +@ldst ...... base:5 rt:5 offset:16 &i =20 ########################################################################### =20 diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translat= e.c index eed2eca6c92..8170a8df26b 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -2261,12 +2261,12 @@ static bool trans_MSA(DisasContext *ctx, arg_MSA *a) return true; } =20 -static bool trans_LSA(DisasContext *ctx, arg_rtype *a) +static bool trans_LSA(DisasContext *ctx, arg_r *a) { return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); } =20 -static bool trans_DLSA(DisasContext *ctx, arg_rtype *a) +static bool trans_DLSA(DisasContext *ctx, arg_r *a) { if (TARGET_LONG_BITS !=3D 64) { return false; diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_transl= ate.c index ae2e023a817..d631851258a 100644 --- a/target/mips/tcg/rel6_translate.c +++ b/target/mips/tcg/rel6_translate.c @@ -23,12 +23,12 @@ bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a) return true; } =20 -static bool trans_LSA(DisasContext *ctx, arg_rtype *a) +static bool trans_LSA(DisasContext *ctx, arg_r *a) { return gen_lsa(ctx, a->rd, a->rt, a->rs, a->sa); } =20 -static bool trans_DLSA(DisasContext *ctx, arg_rtype *a) +static bool trans_DLSA(DisasContext *ctx, arg_r *a) { if (TARGET_LONG_BITS !=3D 64) { return false; diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_transl= ate.c index 395d6afa1f1..6d51fe17c1a 100644 --- a/target/mips/tcg/tx79_translate.c +++ b/target/mips/tcg/tx79_translate.c @@ -64,28 +64,28 @@ bool decode_ext_tx79(DisasContext *ctx, uint32_t insn) * MTLO1 rs Move To LO1 Register */ =20 -static bool trans_MFHI1(DisasContext *ctx, arg_rtype *a) +static bool trans_MFHI1(DisasContext *ctx, arg_r *a) { gen_store_gpr(cpu_HI[1], a->rd); =20 return true; } =20 -static bool trans_MFLO1(DisasContext *ctx, arg_rtype *a) +static bool trans_MFLO1(DisasContext *ctx, arg_r *a) { gen_store_gpr(cpu_LO[1], a->rd); =20 return true; } =20 -static bool trans_MTHI1(DisasContext *ctx, arg_rtype *a) +static bool trans_MTHI1(DisasContext *ctx, arg_r *a) { gen_load_gpr(cpu_HI[1], a->rs); =20 return true; } =20 -static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) +static bool trans_MTLO1(DisasContext *ctx, arg_r *a) { gen_load_gpr(cpu_LO[1], a->rs); =20 @@ -116,7 +116,7 @@ static bool trans_MTLO1(DisasContext *ctx, arg_rtype *a) * PSUBUW rd, rs, rt Parallel Subtract with Unsigned saturation Wo= rd */ =20 -static bool trans_parallel_arith(DisasContext *ctx, arg_rtype *a, +static bool trans_parallel_arith(DisasContext *ctx, arg_r *a, void (*gen_logic_i64)(TCGv_i64, TCGv_i64,= TCGv_i64)) { TCGv_i64 ax, bx; @@ -146,19 +146,19 @@ static bool trans_parallel_arith(DisasContext *ctx, a= rg_rtype *a, } =20 /* Parallel Subtract Byte */ -static bool trans_PSUBB(DisasContext *ctx, arg_rtype *a) +static bool trans_PSUBB(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_vec_sub8_i64); } =20 /* Parallel Subtract Halfword */ -static bool trans_PSUBH(DisasContext *ctx, arg_rtype *a) +static bool trans_PSUBH(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_vec_sub16_i64); } =20 /* Parallel Subtract Word */ -static bool trans_PSUBW(DisasContext *ctx, arg_rtype *a) +static bool trans_PSUBW(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_vec_sub32_i64); } @@ -189,25 +189,25 @@ static bool trans_PSUBW(DisasContext *ctx, arg_rtype = *a) */ =20 /* Parallel And */ -static bool trans_PAND(DisasContext *ctx, arg_rtype *a) +static bool trans_PAND(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_and_i64); } =20 /* Parallel Or */ -static bool trans_POR(DisasContext *ctx, arg_rtype *a) +static bool trans_POR(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_or_i64); } =20 /* Parallel Exclusive Or */ -static bool trans_PXOR(DisasContext *ctx, arg_rtype *a) +static bool trans_PXOR(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_xor_i64); } =20 /* Parallel Not Or */ -static bool trans_PNOR(DisasContext *ctx, arg_rtype *a) +static bool trans_PNOR(DisasContext *ctx, arg_r *a) { return trans_parallel_arith(ctx, a, tcg_gen_nor_i64); } @@ -237,7 +237,7 @@ static bool trans_PNOR(DisasContext *ctx, arg_rtype *a) * PCEQW rd, rs, rt Parallel Compare for Equal Word */ =20 -static bool trans_parallel_compare(DisasContext *ctx, arg_rtype *a, +static bool trans_parallel_compare(DisasContext *ctx, arg_r *a, TCGCond cond, unsigned wlen) { TCGv_i64 c0, c1, ax, bx, t0, t1, t2; @@ -286,37 +286,37 @@ static bool trans_parallel_compare(DisasContext *ctx,= arg_rtype *a, } =20 /* Parallel Compare for Greater Than Byte */ -static bool trans_PCGTB(DisasContext *ctx, arg_rtype *a) +static bool trans_PCGTB(DisasContext *ctx, arg_r *a) { return trans_parallel_compare(ctx, a, TCG_COND_GE, 8); } =20 /* Parallel Compare for Equal Byte */ -static bool trans_PCEQB(DisasContext *ctx, arg_rtype *a) +static bool trans_PCEQB(DisasContext *ctx, arg_r *a) { return trans_parallel_compare(ctx, a, TCG_COND_EQ, 8); } =20 /* Parallel Compare for Greater Than Halfword */ -static bool trans_PCGTH(DisasContext *ctx, arg_rtype *a) +static bool trans_PCGTH(DisasContext *ctx, arg_r *a) { return trans_parallel_compare(ctx, a, TCG_COND_GE, 16); } =20 /* Parallel Compare for Equal Halfword */ -static bool trans_PCEQH(DisasContext *ctx, arg_rtype *a) +static bool trans_PCEQH(DisasContext *ctx, arg_r *a) { return trans_parallel_compare(ctx, a, TCG_COND_EQ, 16); } =20 /* Parallel Compare for Greater Than Word */ -static bool trans_PCGTW(DisasContext *ctx, arg_rtype *a) +static bool trans_PCGTW(DisasContext *ctx, arg_r *a) { return trans_parallel_compare(ctx, a, TCG_COND_GE, 32); } =20 /* Parallel Compare for Equal Word */ -static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a) +static bool trans_PCEQW(DisasContext *ctx, arg_r *a) { return trans_parallel_compare(ctx, a, TCG_COND_EQ, 32); } @@ -334,7 +334,7 @@ static bool trans_PCEQW(DisasContext *ctx, arg_rtype *a) * SQ rt, offset(base) Store Quadword */ =20 -static bool trans_LQ(DisasContext *ctx, arg_itype *a) +static bool trans_LQ(DisasContext *ctx, arg_i *a) { TCGv_i64 t0; TCGv addr; @@ -369,7 +369,7 @@ static bool trans_LQ(DisasContext *ctx, arg_itype *a) return true; } =20 -static bool trans_SQ(DisasContext *ctx, arg_itype *a) +static bool trans_SQ(DisasContext *ctx, arg_i *a) { TCGv_i64 t0 =3D tcg_temp_new_i64(); TCGv addr =3D tcg_temp_new(); @@ -437,7 +437,7 @@ static bool trans_SQ(DisasContext *ctx, arg_itype *a) */ =20 /* Parallel Pack to Word */ -static bool trans_PPACW(DisasContext *ctx, arg_rtype *a) +static bool trans_PPACW(DisasContext *ctx, arg_r *a) { TCGv_i64 a0, b0, t0; =20 @@ -473,7 +473,7 @@ static void gen_pextw(TCGv_i64 dl, TCGv_i64 dh, TCGv_i6= 4 a, TCGv_i64 b) tcg_gen_deposit_i64(dh, a, b, 0, 32); } =20 -static bool trans_PEXTLx(DisasContext *ctx, arg_rtype *a, unsigned wlen) +static bool trans_PEXTLx(DisasContext *ctx, arg_r *a, unsigned wlen) { TCGv_i64 ax, bx; =20 @@ -514,19 +514,19 @@ static bool trans_PEXTLx(DisasContext *ctx, arg_rtype= *a, unsigned wlen) } =20 /* Parallel Extend Lower from Byte */ -static bool trans_PEXTLB(DisasContext *ctx, arg_rtype *a) +static bool trans_PEXTLB(DisasContext *ctx, arg_r *a) { return trans_PEXTLx(ctx, a, 8); } =20 /* Parallel Extend Lower from Halfword */ -static bool trans_PEXTLH(DisasContext *ctx, arg_rtype *a) +static bool trans_PEXTLH(DisasContext *ctx, arg_r *a) { return trans_PEXTLx(ctx, a, 16); } =20 /* Parallel Extend Lower from Word */ -static bool trans_PEXTLW(DisasContext *ctx, arg_rtype *a) +static bool trans_PEXTLW(DisasContext *ctx, arg_r *a) { TCGv_i64 ax, bx; =20 @@ -549,7 +549,7 @@ static bool trans_PEXTLW(DisasContext *ctx, arg_rtype *= a) } =20 /* Parallel Extend Upper from Word */ -static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *a) +static bool trans_PEXTUW(DisasContext *ctx, arg_r *a) { TCGv_i64 ax, bx; =20 @@ -593,7 +593,7 @@ static bool trans_PEXTUW(DisasContext *ctx, arg_rtype *= a) */ =20 /* Parallel Copy Halfword */ -static bool trans_PCPYH(DisasContext *s, arg_rtype *a) +static bool trans_PCPYH(DisasContext *s, arg_r *a) { if (a->rd =3D=3D 0) { /* nop */ @@ -615,7 +615,7 @@ static bool trans_PCPYH(DisasContext *s, arg_rtype *a) } =20 /* Parallel Copy Lower Doubleword */ -static bool trans_PCPYLD(DisasContext *s, arg_rtype *a) +static bool trans_PCPYLD(DisasContext *s, arg_r *a) { if (a->rd =3D=3D 0) { /* nop */ @@ -638,7 +638,7 @@ static bool trans_PCPYLD(DisasContext *s, arg_rtype *a) } =20 /* Parallel Copy Upper Doubleword */ -static bool trans_PCPYUD(DisasContext *s, arg_rtype *a) +static bool trans_PCPYUD(DisasContext *s, arg_r *a) { if (a->rd =3D=3D 0) { /* nop */ @@ -657,7 +657,7 @@ static bool trans_PCPYUD(DisasContext *s, arg_rtype *a) } =20 /* Parallel Rotate 3 Words Left */ -static bool trans_PROT3W(DisasContext *ctx, arg_rtype *a) +static bool trans_PROT3W(DisasContext *ctx, arg_r *a) { TCGv_i64 ax; =20 --=20 2.31.1