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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1627520027912100001 Content-Type: text/plain; charset="utf-8" Cc: qemu-arm@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/aarch64/cpu_loop.c | 4 ++++ linux-user/arm/cpu_loop.c | 43 +++++++++++++++++++++++++++-------- target/arm/cpu.c | 2 +- target/arm/cpu_tcg.c | 2 +- 4 files changed, 40 insertions(+), 11 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index ee72a1c20f..998831f87f 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -137,6 +137,10 @@ void cpu_loop(CPUARMState *env) case 0x11: /* Synchronous Tag Check Fault */ info.si_code =3D TARGET_SEGV_MTESERR; break; + case 0x21: /* Alignment fault */ + info.si_signo =3D TARGET_SIGBUS; + info.si_code =3D TARGET_BUS_ADRALN; + break; default: g_assert_not_reached(); } diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 69632d15be..da7da6a0c1 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -23,6 +23,7 @@ #include "elf.h" #include "cpu_loop-common.h" #include "semihosting/common-semi.h" +#include "target/arm/syndrome.h" =20 #define get_user_code_u32(x, gaddr, env) \ ({ abi_long __r =3D get_user_u32((x), (gaddr)); \ @@ -286,9 +287,8 @@ void cpu_loop(CPUARMState *env) { CPUState *cs =3D env_cpu(env); int trapnr; - unsigned int n, insn; + unsigned int n, insn, ec, fsc; target_siginfo_t info; - uint32_t addr; abi_ulong ret; =20 for(;;) { @@ -437,15 +437,40 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - addr =3D env->exception.vaddress; - { - info.si_signo =3D TARGET_SIGSEGV; - info.si_errno =3D 0; - /* XXX: check env->error_code */ + info.si_signo =3D TARGET_SIGSEGV; + info.si_errno =3D 0; + info._sifields._sigfault._addr =3D env->exception.vaddress; + /* + * We should only arrive here with EC in {DATAABORT, INSNABORT= }, + * and short-form FSC, which then tells us to look at the FSR. + * ??? arm_cpu_reset never sets TTBCR_EAE, so we always get + * short-form FSC. + */ + ec =3D syn_get_ec(env->exception.syndrome); + assert(ec =3D=3D EC_DATAABORT || ec =3D=3D EC_INSNABORT); + fsc =3D extract32(env->exception.syndrome, 0, 6); + assert(fsc =3D=3D 0x3f); + switch (env->exception.fsr & 0x1f) { + case 0x1: /* Alignment */ + info.si_signo =3D TARGET_SIGBUS; + info.si_code =3D TARGET_BUS_ADRALN; + break; + case 0x3: /* Access flag fault, level 1 */ + case 0x6: /* Access flag fault, level 2 */ + case 0x9: /* Domain fault, level 1 */ + case 0xb: /* Domain fault, level 2 */ + case 0xd: /* Permision fault, level 1 */ + case 0xf: /* Permision fault, level 2 */ + info.si_code =3D TARGET_SEGV_ACCERR; + break; + case 0x5: /* Translation fault, level 1 */ + case 0x7: /* Translation fault, level 2 */ info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D addr; - queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; + default: + g_assert_not_reached(); } + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case EXCP_DEBUG: case EXCP_BKPT: diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2866dd7658..de0d968d76 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1987,11 +1987,11 @@ static const struct TCGCPUOps arm_tcg_ops =3D { .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, .tlb_fill =3D arm_cpu_tlb_fill, .debug_excp_handler =3D arm_debug_excp_handler, + .do_unaligned_access =3D arm_cpu_do_unaligned_access, =20 #if !defined(CONFIG_USER_ONLY) .do_interrupt =3D arm_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, - .do_unaligned_access =3D arm_cpu_do_unaligned_access, .adjust_watchpoint_address =3D arm_adjust_watchpoint_address, .debug_check_watchpoint =3D arm_debug_check_watchpoint, .debug_check_breakpoint =3D arm_debug_check_breakpoint, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index ed444bf436..1b91fdc890 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -904,11 +904,11 @@ static const struct TCGCPUOps arm_v7m_tcg_ops =3D { .cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt, .tlb_fill =3D arm_cpu_tlb_fill, .debug_excp_handler =3D arm_debug_excp_handler, + .do_unaligned_access =3D arm_cpu_do_unaligned_access, =20 #if !defined(CONFIG_USER_ONLY) .do_interrupt =3D arm_v7m_cpu_do_interrupt, .do_transaction_failed =3D arm_cpu_do_transaction_failed, - .do_unaligned_access =3D arm_cpu_do_unaligned_access, .adjust_watchpoint_address =3D arm_adjust_watchpoint_address, .debug_check_watchpoint =3D arm_debug_check_watchpoint, .debug_check_breakpoint =3D arm_debug_check_breakpoint, --=20 2.25.1