From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626897733155752.9402696633305; Wed, 21 Jul 2021 13:02:13 -0700 (PDT) Received: from localhost ([::1]:53436 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6IQ0-0005KE-0A for importer@patchew.org; Wed, 21 Jul 2021 16:02:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36466) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6INu-0002LO-DV for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:02 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]:33598) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6INs-0005Zf-3V for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:02 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d1so1664045plg.0 for ; Wed, 21 Jul 2021 12:59:59 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.12.59.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 12:59:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tGWi1/p5kH4vSWuQiEwMVtQM3xzILn4TEfNFXETr+/s=; b=EK44EOprzAhgmXmsvs9nJ3GKkJS/pI3r7n7/Bxu/VKC81SuFnij7GgLUENICf+tWJV kY5PyRktzfJBdLwOaFL0lM3utS+ijZ1uSTtv/GrAJokdzIHd+UFMFEEuR1JfvvxRxcyL JWziVCw5xovSTHnnATLiCgaSLqFxK7zqiBgiq2BLVX+IpOwpzIjovKjcRZsFhiGh7Em7 w9SYIG5rBY6yJrH54OlsvqUt3QuksfTk/GCeHcPOekmKrT18a3KPrcYf16sYrda8mtrS 0EWa/IQUw/dsqzXPcCPDQo1TFz7TviyuJ0MryzWoYB/eU7SxdTQ5pwLCwz12esHGRvsW 8w4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tGWi1/p5kH4vSWuQiEwMVtQM3xzILn4TEfNFXETr+/s=; b=qYpIaYAQbaRO3FinMr8iHJtXVaw7g0XY+rHiwvSU3ke7fgQ+SBP3PcKckQrZNuIKXn sa7L9AsSs5Ai/4Lcnr3JHlYh6VqEskPqg6aC9jRJ8rOp7v3KZQZTPyTtA6Rm0RcaiSjZ GESSBMQGylQblhVwgULWmQE8irTkJ81KJJC0BNVesXbq2XmlWauRNkksj/yyMrEhO4lS s+TbyyAQYTLaa0ELIxUmQzlkS9OlJUfwP+dsuiIWeafYXTE/6wJsplegSRRJVQ0jKDD3 VtVq37EvGKntINqwAx9vYr1SWnkq5u97Njwtjy7J2B9QpPVi5t9z9oyybghQnqTxjS7f YhdA== X-Gm-Message-State: AOAM533XWFnhbJ/Bjz06G7Leja1conNvHU2AgAOKemCRaUPXaaacO7BS 3KEy3vOPRIOhPyMHzxwxanPGGJeQLC6Lvw== X-Google-Smtp-Source: ABdhPJzGcsVy0N3pQ8ysPWz5BKy5TLy3ywwFUsXwEe18dfYGXUQTse5KF6fCe1QiySJYb4ZUGK9F1g== X-Received: by 2002:a62:dd83:0:b029:2e8:e511:c32f with SMTP id w125-20020a62dd830000b02902e8e511c32fmr37914367pff.49.1626897598652; Wed, 21 Jul 2021 12:59:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 01/27] qemu/atomic: Use macros for CONFIG_ATOMIC64 Date: Wed, 21 Jul 2021 09:59:28 -1000 Message-Id: <20210721195954.879535-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Cole Robinson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626897734184100003 Clang warnings about questionable atomic usage get localized to the inline function in atomic.h. By using a macro, we get the full traceback to the original use that caused the warning. Tested-by: Cole Robinson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/qemu/atomic.h | 29 +++++++++-------------------- 1 file changed, 9 insertions(+), 20 deletions(-) diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h index 3ccf84fd46..a7654d2a33 100644 --- a/include/qemu/atomic.h +++ b/include/qemu/atomic.h @@ -457,26 +457,15 @@ =20 /* Abstractions to access atomically (i.e. "once") i64/u64 variables */ #ifdef CONFIG_ATOMIC64 -static inline int64_t qatomic_read_i64(const int64_t *ptr) -{ - /* use __nocheck because sizeof(void *) might be < sizeof(u64) */ - return qatomic_read__nocheck(ptr); -} - -static inline uint64_t qatomic_read_u64(const uint64_t *ptr) -{ - return qatomic_read__nocheck(ptr); -} - -static inline void qatomic_set_i64(int64_t *ptr, int64_t val) -{ - qatomic_set__nocheck(ptr, val); -} - -static inline void qatomic_set_u64(uint64_t *ptr, uint64_t val) -{ - qatomic_set__nocheck(ptr, val); -} +/* Use __nocheck because sizeof(void *) might be < sizeof(u64) */ +#define qatomic_read_i64(P) \ + _Generic(*(P), int64_t: qatomic_read__nocheck(P)) +#define qatomic_read_u64(P) \ + _Generic(*(P), uint64_t: qatomic_read__nocheck(P)) +#define qatomic_set_i64(P, V) \ + _Generic(*(P), int64_t: qatomic_set__nocheck(P, V)) +#define qatomic_set_u64(P, V) \ + _Generic(*(P), uint64_t: qatomic_set__nocheck(P, V)) =20 static inline void qatomic64_init(void) { --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626897733220882.5415015573572; Wed, 21 Jul 2021 13:02:13 -0700 (PDT) Received: from localhost ([::1]:53414 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6IQ0-0005Jc-1b for importer@patchew.org; Wed, 21 Jul 2021 16:02:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36488) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6INw-0002OX-4o for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:04 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:36816) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6INt-0005av-G9 for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:03 -0400 Received: by mail-pl1-x630.google.com with SMTP id x16so1650052plg.3 for ; Wed, 21 Jul 2021 13:00:01 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.12.59.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 12:59:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Qsy1TulgZgPi35LzO24guGsv4onLBv9K5/zzVnSrTIU=; b=QRByAOkkN+6TUvyldPDTtYpInxWSRayy9aBteaLzDRUBNO3TIH56SDNlXkr8MA6rFj T8T84jGKQYaGvn+dx3y9fToPR/5kyIkhgH3ZD0jXdtDgTK7kLXTh0aSnHGpeBFFkjIfO zVLB3eIHCVX7Sd4LyP5UOVZe9BQOX6HR+IDT9l0qLNhU/gatARy7KtiIVWzBm+tcgSXe bUNR/a0BqyAtUXXtKdNt/C+Ow/YhuTVNOmVe5txQ+EzVsV2ydpUuXETfIYgdSAJ059Kw dJdvTrDCinj407WGDBeJ0s/5AkWZQ0WhSskgWlGJ7xY17Xgq+4lJrhHohat48wsSZuKI kOvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Qsy1TulgZgPi35LzO24guGsv4onLBv9K5/zzVnSrTIU=; b=LPv/yHkPqx0HWtGDUTEktVbsFcu0gQHtp7iD8nryxt57GZ4fPX//AbedWCaMdbx6EX 7p8k9tkkngYEOyNNvppA1FTBKzYOBIuhAJG4oJ3UxfS1wO6K8uzAyxlg+japMetHASNk 07i87sJdPjpT6H6oObSprFUgPndnILH2ROS+Bl5rXyxRnIqM8VzHuMVNPaMWcEMfSRK9 luZGVBQCjJaj3L+MlHWoHtUAJicvadNtAiQJ15PSCwVEIlpeMgRRrT8CxkeLla3Y6PSw 1o0mpdhRK5ROnZq2uIgJHmxMcLk+cc6UcIhvLdo+RH3m69STnmIhCMpgJsctW8ilsO2Z 1CoQ== X-Gm-Message-State: AOAM530xt4noCfsZ/OqbawztZ7Zqtuy8c4RiJ2StUPak+4nOMMz6wLFi 193ec4X4nB3otNcpHgKZSWSJAofEr8Yu8w== X-Google-Smtp-Source: ABdhPJy2A1pK/jEwdW2GdQsRxUeLdk0XD7fg6bv+xxbfJpKHhC6PMViNwzUHZ4ySML5QmoPHlDgfbg== X-Received: by 2002:a05:6a00:189e:b029:32b:9f66:dcbb with SMTP id x30-20020a056a00189eb029032b9f66dcbbmr38263852pfh.72.1626897600003; Wed, 21 Jul 2021 13:00:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 02/27] qemu/atomic: Remove pre-C11 atomic fallbacks Date: Wed, 21 Jul 2021 09:59:29 -1000 Message-Id: <20210721195954.879535-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Cole Robinson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626898636916100002 We now require c11, so the fallbacks are now dead code Tested-by: Cole Robinson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- configure | 7 -- include/qemu/atomic.h | 204 +++--------------------------------------- 2 files changed, 10 insertions(+), 201 deletions(-) diff --git a/configure b/configure index 232c54dcc1..b5965b159f 100755 --- a/configure +++ b/configure @@ -3991,18 +3991,11 @@ cat > $TMPC << EOF int main(void) { uint64_t x =3D 0, y =3D 0; -#ifdef __ATOMIC_RELAXED y =3D __atomic_load_n(&x, __ATOMIC_RELAXED); __atomic_store_n(&x, y, __ATOMIC_RELAXED); __atomic_compare_exchange_n(&x, &y, x, 0, __ATOMIC_RELAXED, __ATOMIC_REL= AXED); __atomic_exchange_n(&x, y, __ATOMIC_RELAXED); __atomic_fetch_add(&x, y, __ATOMIC_RELAXED); -#else - typedef char is_host64[sizeof(void *) >=3D sizeof(uint64_t) ? 1 : -1]; - __sync_lock_test_and_set(&x, y); - __sync_val_compare_and_swap(&x, y, 0); - __sync_fetch_and_add(&x, y); -#endif return 0; } EOF diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h index a7654d2a33..fe5467d193 100644 --- a/include/qemu/atomic.h +++ b/include/qemu/atomic.h @@ -60,8 +60,9 @@ (unsigned short)1, = \ (expr)+0)))))) =20 -#ifdef __ATOMIC_RELAXED -/* For C11 atomic ops */ +#ifndef __ATOMIC_RELAXED +#error "Expecting C11 atomic ops" +#endif =20 /* Manual memory barriers * @@ -239,193 +240,8 @@ #define qatomic_xor(ptr, n) \ ((void) __atomic_fetch_xor(ptr, n, __ATOMIC_SEQ_CST)) =20 -#else /* __ATOMIC_RELAXED */ - -#ifdef __alpha__ -#define smp_read_barrier_depends() asm volatile("mb":::"memory") -#endif - -#if defined(__i386__) || defined(__x86_64__) || defined(__s390x__) - -/* - * Because of the strongly ordered storage model, wmb() and rmb() are nops - * here (a compiler barrier only). QEMU doesn't do accesses to write-comb= ining - * qemu memory or non-temporal load/stores from C code. - */ -#define smp_mb_release() barrier() -#define smp_mb_acquire() barrier() - -/* - * __sync_lock_test_and_set() is documented to be an acquire barrier only, - * but it is a full barrier at the hardware level. Add a compiler barrier - * to make it a full barrier also at the compiler level. - */ -#define qatomic_xchg(ptr, i) (barrier(), __sync_lock_test_and_set(ptr, = i)) - -#elif defined(_ARCH_PPC) - -/* - * We use an eieio() for wmb() on powerpc. This assumes we don't - * need to order cacheable and non-cacheable stores with respect to - * each other. - * - * smp_mb has the same problem as on x86 for not-very-new GCC - * (http://patchwork.ozlabs.org/patch/126184/, Nov 2011). - */ -#define smp_wmb() ({ asm volatile("eieio" ::: "memory"); (void)0;= }) -#if defined(__powerpc64__) -#define smp_mb_release() ({ asm volatile("lwsync" ::: "memory"); (void)0= ; }) -#define smp_mb_acquire() ({ asm volatile("lwsync" ::: "memory"); (void)0= ; }) -#else -#define smp_mb_release() ({ asm volatile("sync" ::: "memory"); (void)0; = }) -#define smp_mb_acquire() ({ asm volatile("sync" ::: "memory"); (void)0; = }) -#endif -#define smp_mb() ({ asm volatile("sync" ::: "memory"); (void)0; = }) - -#endif /* _ARCH_PPC */ - -/* - * For (host) platforms we don't have explicit barrier definitions - * for, we use the gcc __sync_synchronize() primitive to generate a - * full barrier. This should be safe on all platforms, though it may - * be overkill for smp_mb_acquire() and smp_mb_release(). - */ -#ifndef smp_mb -#define smp_mb() __sync_synchronize() -#endif - -#ifndef smp_mb_acquire -#define smp_mb_acquire() __sync_synchronize() -#endif - -#ifndef smp_mb_release -#define smp_mb_release() __sync_synchronize() -#endif - -#ifndef smp_read_barrier_depends -#define smp_read_barrier_depends() barrier() -#endif - -#ifndef signal_barrier -#define signal_barrier() barrier() -#endif - -/* These will only be atomic if the processor does the fetch or store - * in a single issue memory operation - */ -#define qatomic_read__nocheck(p) (*(__typeof__(*(p)) volatile*) (p)) -#define qatomic_set__nocheck(p, i) ((*(__typeof__(*(p)) volatile*) (p)) = =3D (i)) - -#define qatomic_read(ptr) qatomic_read__nocheck(ptr) -#define qatomic_set(ptr, i) qatomic_set__nocheck(ptr,i) - -/** - * qatomic_rcu_read - reads a RCU-protected pointer to a local variable - * into a RCU read-side critical section. The pointer can later be safely - * dereferenced within the critical section. - * - * This ensures that the pointer copy is invariant thorough the whole crit= ical - * section. - * - * Inserts memory barriers on architectures that require them (currently o= nly - * Alpha) and documents which pointers are protected by RCU. - * - * qatomic_rcu_read also includes a compiler barrier to ensure that - * value-speculative optimizations (e.g. VSS: Value Speculation - * Scheduling) does not perform the data read before the pointer read - * by speculating the value of the pointer. - * - * Should match qatomic_rcu_set(), qatomic_xchg(), qatomic_cmpxchg(). - */ -#define qatomic_rcu_read(ptr) ({ \ - typeof(*ptr) _val =3D qatomic_read(ptr); \ - smp_read_barrier_depends(); \ - _val; \ -}) - -/** - * qatomic_rcu_set - assigns (publicizes) a pointer to a new data structure - * meant to be read by RCU read-side critical sections. - * - * Documents which pointers will be dereferenced by RCU read-side critical - * sections and adds the required memory barriers on architectures requiri= ng - * them. It also makes sure the compiler does not reorder code initializin= g the - * data structure before its publication. - * - * Should match qatomic_rcu_read(). - */ -#define qatomic_rcu_set(ptr, i) do { \ - smp_wmb(); \ - qatomic_set(ptr, i); \ -} while (0) - -#define qatomic_load_acquire(ptr) ({ \ - typeof(*ptr) _val =3D qatomic_read(ptr); \ - smp_mb_acquire(); \ - _val; \ -}) - -#define qatomic_store_release(ptr, i) do { \ - smp_mb_release(); \ - qatomic_set(ptr, i); \ -} while (0) - -#ifndef qatomic_xchg -#if defined(__clang__) -#define qatomic_xchg(ptr, i) __sync_swap(ptr, i) -#else -/* __sync_lock_test_and_set() is documented to be an acquire barrier only.= */ -#define qatomic_xchg(ptr, i) (smp_mb(), __sync_lock_test_and_set(ptr, i= )) -#endif -#endif -#define qatomic_xchg__nocheck qatomic_xchg - -/* Provide shorter names for GCC atomic builtins. */ -#define qatomic_fetch_inc(ptr) __sync_fetch_and_add(ptr, 1) -#define qatomic_fetch_dec(ptr) __sync_fetch_and_add(ptr, -1) - -#define qatomic_fetch_add(ptr, n) __sync_fetch_and_add(ptr, n) -#define qatomic_fetch_sub(ptr, n) __sync_fetch_and_sub(ptr, n) -#define qatomic_fetch_and(ptr, n) __sync_fetch_and_and(ptr, n) -#define qatomic_fetch_or(ptr, n) __sync_fetch_and_or(ptr, n) -#define qatomic_fetch_xor(ptr, n) __sync_fetch_and_xor(ptr, n) - -#define qatomic_inc_fetch(ptr) __sync_add_and_fetch(ptr, 1) -#define qatomic_dec_fetch(ptr) __sync_add_and_fetch(ptr, -1) -#define qatomic_add_fetch(ptr, n) __sync_add_and_fetch(ptr, n) -#define qatomic_sub_fetch(ptr, n) __sync_sub_and_fetch(ptr, n) -#define qatomic_and_fetch(ptr, n) __sync_and_and_fetch(ptr, n) -#define qatomic_or_fetch(ptr, n) __sync_or_and_fetch(ptr, n) -#define qatomic_xor_fetch(ptr, n) __sync_xor_and_fetch(ptr, n) - -#define qatomic_cmpxchg(ptr, old, new) \ - __sync_val_compare_and_swap(ptr, old, new) -#define qatomic_cmpxchg__nocheck(ptr, old, new) qatomic_cmpxchg(ptr, old,= new) - -/* And even shorter names that return void. */ -#define qatomic_inc(ptr) ((void) __sync_fetch_and_add(ptr, 1)) -#define qatomic_dec(ptr) ((void) __sync_fetch_and_add(ptr, -1)) -#define qatomic_add(ptr, n) ((void) __sync_fetch_and_add(ptr, n)) -#define qatomic_sub(ptr, n) ((void) __sync_fetch_and_sub(ptr, n)) -#define qatomic_and(ptr, n) ((void) __sync_fetch_and_and(ptr, n)) -#define qatomic_or(ptr, n) ((void) __sync_fetch_and_or(ptr, n)) -#define qatomic_xor(ptr, n) ((void) __sync_fetch_and_xor(ptr, n)) - -#endif /* __ATOMIC_RELAXED */ - -#ifndef smp_wmb #define smp_wmb() smp_mb_release() -#endif -#ifndef smp_rmb #define smp_rmb() smp_mb_acquire() -#endif - -/* This is more efficient than a store plus a fence. */ -#if !defined(__SANITIZE_THREAD__) -#if defined(__i386__) || defined(__x86_64__) || defined(__s390x__) -#define qatomic_mb_set(ptr, i) ((void)qatomic_xchg(ptr, i)) -#endif -#endif =20 /* qatomic_mb_read/set semantics map Java volatile variables. They are * less expensive on some platforms (notably POWER) than fully @@ -435,16 +251,16 @@ * use. See docs/devel/atomics.rst for more discussion. */ =20 -#ifndef qatomic_mb_read #define qatomic_mb_read(ptr) \ qatomic_load_acquire(ptr) -#endif =20 -#ifndef qatomic_mb_set -#define qatomic_mb_set(ptr, i) do { \ - qatomic_store_release(ptr, i); \ - smp_mb(); \ -} while(0) +#if !defined(__SANITIZE_THREAD__) && \ + (defined(__i386__) || defined(__x86_64__) || defined(__s390x__)) +/* This is more efficient than a store plus a fence. */ +# define qatomic_mb_set(ptr, i) ((void)qatomic_xchg(ptr, i)) +#else +# define qatomic_mb_set(ptr, i) \ + ({ qatomic_store_release(ptr, i); smp_mb(); }) #endif =20 #define qatomic_fetch_inc_nonzero(ptr) ({ \ --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626897732904180.47137140899508; Wed, 21 Jul 2021 13:02:12 -0700 (PDT) Received: from localhost ([::1]:53428 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6IPz-0005Ju-Jq for importer@patchew.org; Wed, 21 Jul 2021 16:02:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36494) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6INw-0002P4-IV for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:04 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:33605) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6INu-0005bu-Mq for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:04 -0400 Received: by mail-pl1-x633.google.com with SMTP id d1so1664195plg.0 for ; Wed, 21 Jul 2021 13:00:02 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gByINc+ktkYg8pbHnFAwT6K5mm8lqzrOGXD9r55vivo=; b=AkVocfRZiKZhd73C+a0h/ZY5HZSViAcZN26dlO7Ff+KDG+mP2MifHJyPex/FLzdpFU tOmc4o5a9SfEPrzgP5vybbhVd1UOjTkz9bbIofxCErZiv/eZEkhOsBJx1iwe7OeppJn0 zK+U9mTGNS0tYKsKpie25sVCLwpHeSXU7lBxbPNXuHFhQiaruNAM4DEDA99aXDd7mudV XR2kEIgOdGDjkECZiIrlhnjLpBqagLNSQ2HCAQaGgnOI/0Y53aQdv6bDydHu8dmNt+15 xSjrKDV1KZBqam4nwv3eYfuG6GVk8wG+FJGcyllOFYbJ/ifGKnutJHjLtzdfk04ceJWU 343g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gByINc+ktkYg8pbHnFAwT6K5mm8lqzrOGXD9r55vivo=; b=YIZMyvA/llDTBFxsJk791gxipITOfakgfK+dOiwIZ/fWyP5hxzPIxfU3K/qf/Ca1Rx 5E74Bslmi6EryXT0f818/ZMS4y2bGysk/xez0Pz+0xAGdNO2KAma0RoFkwCH8Zu+R/u1 cxb0s025qVXF3ybYjxcyl4roNIKXKIvfANz6LJZgN65AaFXnqhxQ2IrSj386WYcmNpNM FUMLpDhgeNIrs097XMeFOKz9Iul/g9nedTdQG91wBah+SyZ1BhB/Uwl2kFg332rdNW8B 7j7m8uk6xU7e8o1KUiq06wJj4eCzWgTEhktnXIKO7KRBRAwFJthK+uWeYrYNINeso03K mCyw== X-Gm-Message-State: AOAM531pYxmKt/++yjnzfOw0/fFdPUFEgTbZfohFihNKwnqZowHzQtZ6 9bNlnmWtTjFaN9fo7p/L863ctstp1lclTQ== X-Google-Smtp-Source: ABdhPJza7rSDz8t1oOTVx9qHQMTyTBmSrUPTak0CIoGWbzjgDoY7ap16Cv6w9sqWsQByFj/MDRDFYg== X-Received: by 2002:a65:64cf:: with SMTP id t15mr37296068pgv.131.1626897601346; Wed, 21 Jul 2021 13:00:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 03/27] qemu/atomic: Add aligned_{int64,uint64}_t types Date: Wed, 21 Jul 2021 09:59:30 -1000 Message-Id: <20210721195954.879535-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Cole Robinson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626898636886100001 Use it to avoid some clang-12 -Watomic-alignment errors, forcing some structures to be aligned and as a pointer when we have ensured that the address is aligned. Tested-by: Cole Robinson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 4 ++-- include/qemu/atomic.h | 14 +++++++++++++- include/qemu/stats64.h | 2 +- softmmu/timers-state.h | 2 +- linux-user/hppa/cpu_loop.c | 2 +- util/qsp.c | 4 ++-- 6 files changed, 20 insertions(+), 8 deletions(-) diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index afa8a9daf3..d347462af5 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -28,8 +28,8 @@ # define SHIFT 4 #elif DATA_SIZE =3D=3D 8 # define SUFFIX q -# define DATA_TYPE uint64_t -# define SDATA_TYPE int64_t +# define DATA_TYPE aligned_uint64_t +# define SDATA_TYPE aligned_int64_t # define BSWAP bswap64 # define SHIFT 3 #elif DATA_SIZE =3D=3D 4 diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h index fe5467d193..112a29910b 100644 --- a/include/qemu/atomic.h +++ b/include/qemu/atomic.h @@ -271,7 +271,19 @@ _oldn; \ }) =20 -/* Abstractions to access atomically (i.e. "once") i64/u64 variables */ +/* + * Abstractions to access atomically (i.e. "once") i64/u64 variables. + * + * The i386 abi is odd in that by default members are only aligned to + * 4 bytes, which means that 8-byte types can wind up mis-aligned. + * Clang will then warn about this, and emit a call into libatomic. + * + * Use of these types in structures when they will be used with atomic + * operations can avoid this. + */ +typedef int64_t aligned_int64_t __attribute__((aligned(8))); +typedef uint64_t aligned_uint64_t __attribute__((aligned(8))); + #ifdef CONFIG_ATOMIC64 /* Use __nocheck because sizeof(void *) might be < sizeof(u64) */ #define qatomic_read_i64(P) \ diff --git a/include/qemu/stats64.h b/include/qemu/stats64.h index fdd3d1b8f9..802402254b 100644 --- a/include/qemu/stats64.h +++ b/include/qemu/stats64.h @@ -21,7 +21,7 @@ =20 typedef struct Stat64 { #ifdef CONFIG_ATOMIC64 - uint64_t value; + aligned_uint64_t value; #else uint32_t low, high; uint32_t lock; diff --git a/softmmu/timers-state.h b/softmmu/timers-state.h index 8c262ce139..94bb7394c5 100644 --- a/softmmu/timers-state.h +++ b/softmmu/timers-state.h @@ -47,7 +47,7 @@ typedef struct TimersState { int64_t last_delta; =20 /* Compensate for varying guest execution speed. */ - int64_t qemu_icount_bias; + aligned_int64_t qemu_icount_bias; =20 int64_t vm_clock_warp_start; int64_t cpu_clock_offset; diff --git a/linux-user/hppa/cpu_loop.c b/linux-user/hppa/cpu_loop.c index 3aaaf3337c..82d8183821 100644 --- a/linux-user/hppa/cpu_loop.c +++ b/linux-user/hppa/cpu_loop.c @@ -82,7 +82,7 @@ static abi_ulong hppa_lws(CPUHPPAState *env) o64 =3D *(uint64_t *)g2h(cs, old); n64 =3D *(uint64_t *)g2h(cs, new); #ifdef CONFIG_ATOMIC64 - r64 =3D qatomic_cmpxchg__nocheck((uint64_t *)g2h(cs, addr), + r64 =3D qatomic_cmpxchg__nocheck((aligned_uint64_t *)g2h(c= s, addr), o64, n64); ret =3D r64 !=3D o64; #else diff --git a/util/qsp.c b/util/qsp.c index bacc5fa2f6..8562b14a87 100644 --- a/util/qsp.c +++ b/util/qsp.c @@ -83,8 +83,8 @@ typedef struct QSPCallSite QSPCallSite; struct QSPEntry { void *thread_ptr; const QSPCallSite *callsite; - uint64_t n_acqs; - uint64_t ns; + aligned_uint64_t n_acqs; + aligned_uint64_t ns; unsigned int n_objs; /* count of coalesced objs; only used for reporti= ng */ }; typedef struct QSPEntry QSPEntry; --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1626897914; cv=none; d=zohomail.com; s=zohoarc; b=JO81uAz5qyYc6Lx3zfwCWPhK/dOZgFdJc1tE69rwd3mLMncRgXaDtA8VEYGX5U5XNRAG30Fxz7hM21UceyUPeAlcFMwCbgrYdMYHqd+H1opx9hliTzLMN10KXKJ4HqZ5Rc7/tY+tArmKXNgtTj1unuYPc/mo+SMBULN6ORPcsHU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626897914; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yFBmZYnlqnGmH22vv1l18Boh2+T/swIBlrsgKz43rXg=; b=hyqxBXKUfE/apiLFauNT0gAzxcIObUHxCDdplchN4KbWHDfJ2jcK26ZSxcY6VFmUb8eagQnVEeDR2BqTjzVoWrhkqSqqWId7WY0JH7WLKrl8c8RECE72DRO+UMjZdB53VynYLF35E4F2+w/pD45sU836uvKQNURi1BVd8hzQXWI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626897914158277.93667354026013; Wed, 21 Jul 2021 13:05:14 -0700 (PDT) Received: from localhost ([::1]:33940 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6ISv-00033v-2T for importer@patchew.org; Wed, 21 Jul 2021 16:05:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36522) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IO0-0002YE-40 for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:08 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:35676) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6INw-0005dm-7v for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:07 -0400 Received: by mail-pl1-x62b.google.com with SMTP id n11so1650140plc.2 for ; Wed, 21 Jul 2021 13:00:03 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yFBmZYnlqnGmH22vv1l18Boh2+T/swIBlrsgKz43rXg=; b=v+KtpDpJhttTaCgv9zf3hNuk/HX212dqf1NVAnlqtBhLgpZqv0hJTEumqGGaEPs7hQ 6Kv7+RVJQmxDvgl7WVwlBWefaTxttdDqg0JYzUckd0FYYRr3+3oqs9/BlKTqGkbjnPoZ H8csv1qsSH/d6/h94hnKxXpzUeBHgzNiwiie00Or+ZPMhqfGxGCiSZSkslTqzsvQDz1a EDrHY4Z3yAWKuVDKZIMUx2RfKzQ9Inild/YxE8Lm4HTFD+nJgrzrOH+/7S88ExhfZIP+ HR1auL0khzQiI6en+mH7dF7T9YjZFrKoMlIQwtsjDfpMMzMRDQImIf+tMkMML3KEdv0x /o9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yFBmZYnlqnGmH22vv1l18Boh2+T/swIBlrsgKz43rXg=; b=cdJ/SJJ2wrEmSWuUKI0dh1hvIQCDuCLnjZN689Q22NOQTtFaoOuVLnIFq8nPcqfz7y RuZ+im5hrnWlGPhQv01uc7OhILKyyvV4Oa3Pm+Tec4xBlmHKdAbtgR03u2PhEXEicpid ztk9+hUKfgUo+OfzWaAUDdv8wMB5TCjnyXF/XLlejNCFV0EJIejfS0pVQzAnyjvEWCfW u6COJPBW1w4sHL3ASLhnHwfFnNk17tZ/zlPUSnMk8n1Ne3Wa8VWydko+g1wc1UVRNI34 NqeXMfQv6EqtaIMbgb8djnIDdj+cGxI8elQcINp/zik4bb7RdhBMKehWQh+5R800z8xG X9bA== X-Gm-Message-State: AOAM532NKAhvVIU02ovLBiQ2om9hpe+0n7+o8Xq27n4P7jBzUp4nc1U5 lg1wahISdhwQpi0xCuqZVZB5QmjOpLKDXA== X-Google-Smtp-Source: ABdhPJy9NgXkxAlEUJc9a7fCM8bDRJPAY0WTrL+j4v4AaOnmcvX77MY6GXDt/lVWy2Vcbaj9LSt2NQ== X-Received: by 2002:a62:2bc6:0:b029:2cc:242f:ab69 with SMTP id r189-20020a622bc60000b02902cc242fab69mr38376250pfr.16.1626897602715; Wed, 21 Jul 2021 13:00:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 04/27] tcg: Rename helper_atomic_*_mmu and provide for user-only Date: Wed, 21 Jul 2021 09:59:31 -1000 Message-Id: <20210721195954.879535-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Cole Robinson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1626897915105100005 Content-Type: text/plain; charset="utf-8" Always provide the atomic interface using TCGMemOpIdx oi and uintptr_t retaddr. Rename from helper_* to cpu_* so as to (mostly) match the exec/cpu_ldst.h functions, and to emphasize that they are not callable from TCG directly. Tested-by: Cole Robinson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 78 ++++++++++++++++------------------- accel/tcg/cputlb.c | 8 ++-- accel/tcg/user-exec.c | 59 ++++++++++++++++---------- target/arm/helper-a64.c | 8 ++-- target/i386/tcg/mem_helper.c | 15 +------ target/m68k/op_helper.c | 19 +++------ target/ppc/mem_helper.c | 16 +++---- target/s390x/tcg/mem_helper.c | 19 ++++----- 8 files changed, 104 insertions(+), 118 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 25dd19d6e1..44ccd86f3e 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -1341,31 +1341,32 @@ void helper_be_stq_mmu(CPUArchState *env, target_ul= ong addr, uint64_t val, # define helper_ret_stl_mmu helper_le_stl_mmu # define helper_ret_stq_mmu helper_le_stq_mmu #endif +#endif /* CONFIG_SOFTMMU */ =20 -uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, +uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, + uint32_t cmpv, uint32_t newv, + TCGMemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr, uint32_t cmpv, uint32_t newv, TCGMemOpIdx oi, uintptr_t retaddr); -uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong add= r, - uint32_t cmpv, uint32_t newv, - TCGMemOpIdx oi, uintptr_t retaddr); -uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong add= r, - uint32_t cmpv, uint32_t newv, - TCGMemOpIdx oi, uintptr_t retaddr); -uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong add= r, - uint64_t cmpv, uint64_t newv, - TCGMemOpIdx oi, uintptr_t retaddr); -uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong add= r, - uint32_t cmpv, uint32_t newv, - TCGMemOpIdx oi, uintptr_t retaddr); -uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong add= r, - uint32_t cmpv, uint32_t newv, - TCGMemOpIdx oi, uintptr_t retaddr); -uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong add= r, - uint64_t cmpv, uint64_t newv, - TCGMemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr, + uint32_t cmpv, uint32_t newv, + TCGMemOpIdx oi, uintptr_t retaddr); +uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr, + uint64_t cmpv, uint64_t newv, + TCGMemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr, + uint32_t cmpv, uint32_t newv, + TCGMemOpIdx oi, uintptr_t retaddr); +uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr, + uint32_t cmpv, uint32_t newv, + TCGMemOpIdx oi, uintptr_t retaddr); +uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr, + uint64_t cmpv, uint64_t newv, + TCGMemOpIdx oi, uintptr_t retaddr); =20 #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ -TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu \ +TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \ (CPUArchState *env, target_ulong addr, TYPE val, \ TCGMemOpIdx oi, uintptr_t retaddr); =20 @@ -1411,31 +1412,22 @@ GEN_ATOMIC_HELPER_ALL(xchg) =20 #undef GEN_ATOMIC_HELPER_ALL #undef GEN_ATOMIC_HELPER -#endif /* CONFIG_SOFTMMU */ =20 -/* - * These aren't really a "proper" helpers because TCG cannot manage Int128. - * However, use the same format as the others, for use by the backends. - * - * The cmpxchg functions are only defined if HAVE_CMPXCHG128; - * the ld/st functions are only defined if HAVE_ATOMIC128, - * as defined by . - */ -Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr, - Int128 cmpv, Int128 newv, - TCGMemOpIdx oi, uintptr_t retaddr); -Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr, - Int128 cmpv, Int128 newv, - TCGMemOpIdx oi, uintptr_t retaddr); +Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr, + Int128 cmpv, Int128 newv, + TCGMemOpIdx oi, uintptr_t retaddr); +Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr, + Int128 cmpv, Int128 newv, + TCGMemOpIdx oi, uintptr_t retaddr); =20 -Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr, - TCGMemOpIdx oi, uintptr_t retaddr); -void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128= val, - TCGMemOpIdx oi, uintptr_t retaddr); -void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128= val, - TCGMemOpIdx oi, uintptr_t retaddr); +Int128 cpu_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr); +Int128 cpu_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr); +void cpu_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 va= l, + TCGMemOpIdx oi, uintptr_t retaddr); +void cpu_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 va= l, + TCGMemOpIdx oi, uintptr_t retaddr); =20 #ifdef CONFIG_DEBUG_TCG void tcg_assert_listed_vecop(TCGOpcode); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b4e15b6aad..63da1cc96f 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2686,12 +2686,14 @@ void cpu_stq_le_data(CPUArchState *env, target_ulon= g ptr, uint64_t val) cpu_stq_le_data_ra(env, ptr, val, 0); } =20 -/* First set of helpers allows passing in of OI and RETADDR. This makes - them callable from other helpers. */ +/* + * First set of functions passes in OI and RETADDR. + * This makes them callable from other helpers. + */ =20 #define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr #define ATOMIC_NAME(X) \ - HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu)) + glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu) #define ATOMIC_MMU_DECLS #define ATOMIC_MMU_LOOKUP_RW \ atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ | PAGE_WRITE, re= taddr) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index ba09fd0413..82dbe06f08 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1234,19 +1234,23 @@ static void *atomic_mmu_lookup(CPUArchState *env, t= arget_ulong addr, return ret; } =20 -/* Macro to call the above, with local variables from the use context. */ -#define ATOMIC_MMU_DECLS do {} while (0) -#define ATOMIC_MMU_LOOKUP_RW atomic_mmu_lookup(env, addr, DATA_SIZE, GETP= C()) +#include "atomic_common.c.inc" + +/* + * First set of functions passes in OI and RETADDR. + * This makes them callable from other helpers. + */ + +#define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr +#define ATOMIC_NAME(X) \ + glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu) +#define ATOMIC_MMU_DECLS +#define ATOMIC_MMU_LOOKUP_RW atomic_mmu_lookup(env, addr, DATA_SIZE, reta= ddr) #define ATOMIC_MMU_LOOKUP_R ATOMIC_MMU_LOOKUP_RW #define ATOMIC_MMU_LOOKUP_W ATOMIC_MMU_LOOKUP_RW #define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0) #define ATOMIC_MMU_IDX MMU_USER_IDX =20 -#define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) -#define EXTRA_ARGS - -#include "atomic_common.c.inc" - #define DATA_SIZE 1 #include "atomic_template.h" =20 @@ -1261,20 +1265,33 @@ static void *atomic_mmu_lookup(CPUArchState *env, t= arget_ulong addr, #include "atomic_template.h" #endif =20 -/* The following is only callable from other helpers, and matches up - with the softmmu version. */ - #if HAVE_ATOMIC128 || HAVE_CMPXCHG128 - -#undef EXTRA_ARGS -#undef ATOMIC_NAME -#undef ATOMIC_MMU_LOOKUP_RW - -#define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr -#define ATOMIC_NAME(X) \ - HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu)) -#define ATOMIC_MMU_LOOKUP_RW atomic_mmu_lookup(env, addr, DATA_SIZE, reta= ddr) - #define DATA_SIZE 16 #include "atomic_template.h" #endif + +/* + * Second set of functions is directly callable from TCG. + */ + +#undef EXTRA_ARGS +#undef ATOMIC_NAME +#undef ATOMIC_MMU_DECLS + +#define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) +#define EXTRA_ARGS +#define ATOMIC_MMU_DECLS uintptr_t retaddr =3D GETPC() + +#define DATA_SIZE 1 +#include "atomic_template.h" + +#define DATA_SIZE 2 +#include "atomic_template.h" + +#define DATA_SIZE 4 +#include "atomic_template.h" + +#ifdef CONFIG_ATOMIC64 +#define DATA_SIZE 8 +#include "atomic_template.h" +#endif diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index ac5c4452d5..26f79f9141 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -564,7 +564,7 @@ uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMSta= te *env, uint64_t addr, =20 cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); newv =3D int128_make128(new_lo, new_hi); - oldv =3D helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra); + oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra); =20 success =3D int128_eq(oldv, cmpv); return !success; @@ -638,7 +638,7 @@ uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMSta= te *env, uint64_t addr, */ cmpv =3D int128_make128(env->exclusive_high, env->exclusive_val); newv =3D int128_make128(new_hi, new_lo); - oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); + oldv =3D cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); =20 success =3D int128_eq(oldv, cmpv); return !success; @@ -660,7 +660,7 @@ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_= t rs, uint64_t addr, =20 cmpv =3D int128_make128(env->xregs[rs], env->xregs[rs + 1]); newv =3D int128_make128(new_lo, new_hi); - oldv =3D helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra); + oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra); =20 env->xregs[rs] =3D int128_getlo(oldv); env->xregs[rs + 1] =3D int128_gethi(oldv); @@ -681,7 +681,7 @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_= t rs, uint64_t addr, =20 cmpv =3D int128_make128(env->xregs[rs + 1], env->xregs[rs]); newv =3D int128_make128(new_lo, new_hi); - oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); + oldv =3D cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); =20 env->xregs[rs + 1] =3D int128_getlo(oldv); env->xregs[rs] =3D int128_gethi(oldv); diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 591f512bff..2da3cd14b6 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -64,22 +64,12 @@ void helper_cmpxchg8b(CPUX86State *env, target_ulong a0) cmpv =3D deposit64(env->regs[R_EAX], 32, 32, env->regs[R_EDX]); newv =3D deposit64(env->regs[R_EBX], 32, 32, env->regs[R_ECX]); =20 -#ifdef CONFIG_USER_ONLY - { - uint64_t *haddr =3D g2h(env_cpu(env), a0); - cmpv =3D cpu_to_le64(cmpv); - newv =3D cpu_to_le64(newv); - oldv =3D qatomic_cmpxchg__nocheck(haddr, cmpv, newv); - oldv =3D le64_to_cpu(oldv); - } -#else { uintptr_t ra =3D GETPC(); int mem_idx =3D cpu_mmu_index(env, false); TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ, mem_idx); - oldv =3D helper_atomic_cmpxchgq_le_mmu(env, a0, cmpv, newv, oi, ra= ); + oldv =3D cpu_atomic_cmpxchgq_le_mmu(env, a0, cmpv, newv, oi, ra); } -#endif =20 if (oldv =3D=3D cmpv) { eflags |=3D CC_Z; @@ -147,8 +137,7 @@ void helper_cmpxchg16b(CPUX86State *env, target_ulong a= 0) =20 int mem_idx =3D cpu_mmu_index(env, false); TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); - Int128 oldv =3D helper_atomic_cmpxchgo_le_mmu(env, a0, cmpv, - newv, oi, ra); + Int128 oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, a0, cmpv, newv, oi= , ra); =20 if (int128_eq(oldv, cmpv)) { eflags |=3D CC_Z; diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index ae1ba4b437..d006d1cb3e 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -22,6 +22,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "semihosting/semihost.h" +#include "tcg/tcg.h" =20 #if defined(CONFIG_USER_ONLY) =20 @@ -782,9 +783,9 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs, = uint32_t a1, uint32_t a2, uint32_t u2 =3D env->dregs[Du2]; uint32_t l1, l2; uintptr_t ra =3D GETPC(); -#if defined(CONFIG_ATOMIC64) && !defined(CONFIG_USER_ONLY) +#if defined(CONFIG_ATOMIC64) int mmu_idx =3D cpu_mmu_index(env, 0); - TCGMemOpIdx oi; + TCGMemOpIdx oi =3D make_memop_idx(MO_BEQ, mmu_idx); #endif =20 if (parallel) { @@ -794,23 +795,13 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs= , uint32_t a1, uint32_t a2, if ((a1 & 7) =3D=3D 0 && a2 =3D=3D a1 + 4) { c =3D deposit64(c2, 32, 32, c1); u =3D deposit64(u2, 32, 32, u1); -#ifdef CONFIG_USER_ONLY - l =3D helper_atomic_cmpxchgq_be(env, a1, c, u); -#else - oi =3D make_memop_idx(MO_BEQ, mmu_idx); - l =3D helper_atomic_cmpxchgq_be_mmu(env, a1, c, u, oi, ra); -#endif + l =3D cpu_atomic_cmpxchgq_be_mmu(env, a1, c, u, oi, ra); l1 =3D l >> 32; l2 =3D l; } else if ((a2 & 7) =3D=3D 0 && a1 =3D=3D a2 + 4) { c =3D deposit64(c1, 32, 32, c2); u =3D deposit64(u1, 32, 32, u2); -#ifdef CONFIG_USER_ONLY - l =3D helper_atomic_cmpxchgq_be(env, a2, c, u); -#else - oi =3D make_memop_idx(MO_BEQ, mmu_idx); - l =3D helper_atomic_cmpxchgq_be_mmu(env, a2, c, u, oi, ra); -#endif + l =3D cpu_atomic_cmpxchgq_be_mmu(env, a2, c, u, oi, ra); l2 =3D l >> 32; l1 =3D l; } else diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 444b2a30ef..e2282baa8d 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -376,7 +376,7 @@ uint64_t helper_lq_le_parallel(CPUPPCState *env, target= _ulong addr, =20 /* We will have raised EXCP_ATOMIC from the translator. */ assert(HAVE_ATOMIC128); - ret =3D helper_atomic_ldo_le_mmu(env, addr, opidx, GETPC()); + ret =3D cpu_atomic_ldo_le_mmu(env, addr, opidx, GETPC()); env->retxh =3D int128_gethi(ret); return int128_getlo(ret); } @@ -388,7 +388,7 @@ uint64_t helper_lq_be_parallel(CPUPPCState *env, target= _ulong addr, =20 /* We will have raised EXCP_ATOMIC from the translator. */ assert(HAVE_ATOMIC128); - ret =3D helper_atomic_ldo_be_mmu(env, addr, opidx, GETPC()); + ret =3D cpu_atomic_ldo_be_mmu(env, addr, opidx, GETPC()); env->retxh =3D int128_gethi(ret); return int128_getlo(ret); } @@ -401,7 +401,7 @@ void helper_stq_le_parallel(CPUPPCState *env, target_ul= ong addr, /* We will have raised EXCP_ATOMIC from the translator. */ assert(HAVE_ATOMIC128); val =3D int128_make128(lo, hi); - helper_atomic_sto_le_mmu(env, addr, val, opidx, GETPC()); + cpu_atomic_sto_le_mmu(env, addr, val, opidx, GETPC()); } =20 void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr, @@ -412,7 +412,7 @@ void helper_stq_be_parallel(CPUPPCState *env, target_ul= ong addr, /* We will have raised EXCP_ATOMIC from the translator. */ assert(HAVE_ATOMIC128); val =3D int128_make128(lo, hi); - helper_atomic_sto_be_mmu(env, addr, val, opidx, GETPC()); + cpu_atomic_sto_be_mmu(env, addr, val, opidx, GETPC()); } =20 uint32_t helper_stqcx_le_parallel(CPUPPCState *env, target_ulong addr, @@ -429,8 +429,8 @@ uint32_t helper_stqcx_le_parallel(CPUPPCState *env, tar= get_ulong addr, =20 cmpv =3D int128_make128(env->reserve_val2, env->reserve_val); newv =3D int128_make128(new_lo, new_hi); - oldv =3D helper_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, - opidx, GETPC()); + oldv =3D cpu_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, + opidx, GETPC()); success =3D int128_eq(oldv, cmpv); } env->reserve_addr =3D -1; @@ -451,8 +451,8 @@ uint32_t helper_stqcx_be_parallel(CPUPPCState *env, tar= get_ulong addr, =20 cmpv =3D int128_make128(env->reserve_val2, env->reserve_val); newv =3D int128_make128(new_lo, new_hi); - oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, - opidx, GETPC()); + oldv =3D cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, + opidx, GETPC()); success =3D int128_eq(oldv, cmpv); } env->reserve_addr =3D -1; diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 9bae13ecf0..21a4de4067 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1811,7 +1811,7 @@ void HELPER(cdsg_parallel)(CPUS390XState *env, uint64= _t addr, =20 mem_idx =3D cpu_mmu_index(env, false); oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); - oldv =3D helper_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); + oldv =3D cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); fail =3D !int128_eq(oldv, cmpv); =20 env->cc_op =3D fail; @@ -1884,7 +1884,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, ov =3D qatomic_cmpxchg__nocheck(haddr, cv, nv); #else TCGMemOpIdx oi =3D make_memop_idx(MO_TEUL | MO_ALIGN, mem_= idx); - ov =3D helper_atomic_cmpxchgl_be_mmu(env, a1, cv, nv, oi, = ra); + ov =3D cpu_atomic_cmpxchgl_be_mmu(env, a1, cv, nv, oi, ra); #endif } else { ov =3D cpu_ldl_data_ra(env, a1, ra); @@ -1903,13 +1903,8 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t= r3, uint64_t a1, =20 if (parallel) { #ifdef CONFIG_ATOMIC64 -# ifdef CONFIG_USER_ONLY - uint64_t *haddr =3D g2h(env_cpu(env), a1); - ov =3D qatomic_cmpxchg__nocheck(haddr, cv, nv); -# else TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN, mem_i= dx); - ov =3D helper_atomic_cmpxchgq_be_mmu(env, a1, cv, nv, oi, = ra); -# endif + ov =3D cpu_atomic_cmpxchgq_be_mmu(env, a1, cv, nv, oi, ra); #else /* Note that we asserted !parallel above. */ g_assert_not_reached(); @@ -1945,7 +1940,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, cpu_stq_data_ra(env, a1 + 8, int128_getlo(nv), ra); } else if (HAVE_CMPXCHG128) { TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, me= m_idx); - ov =3D helper_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, = ra); + ov =3D cpu_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi, ra); cc =3D !int128_eq(ov, cv); } else { /* Note that we asserted !parallel above. */ @@ -1985,7 +1980,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, } else if (HAVE_ATOMIC128) { TCGMemOpIdx oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, me= m_idx); Int128 sv =3D int128_make128(svl, svh); - helper_atomic_sto_be_mmu(env, a2, sv, oi, ra); + cpu_atomic_sto_be_mmu(env, a2, sv, oi, ra); } else { /* Note that we asserted !parallel above. */ g_assert_not_reached(); @@ -2486,7 +2481,7 @@ uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uin= t64_t addr) =20 mem_idx =3D cpu_mmu_index(env, false); oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); - v =3D helper_atomic_ldo_be_mmu(env, addr, oi, ra); + v =3D cpu_atomic_ldo_be_mmu(env, addr, oi, ra); hi =3D int128_gethi(v); lo =3D int128_getlo(v); =20 @@ -2518,7 +2513,7 @@ void HELPER(stpq_parallel)(CPUS390XState *env, uint64= _t addr, mem_idx =3D cpu_mmu_index(env, false); oi =3D make_memop_idx(MO_TEQ | MO_ALIGN_16, mem_idx); v =3D int128_make128(low, high); - helper_atomic_sto_be_mmu(env, addr, v, oi, ra); + cpu_atomic_sto_be_mmu(env, addr, v, oi, ra); } =20 /* Execute instruction. This instruction executes an insn modified with --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1626897912; cv=none; d=zohomail.com; s=zohoarc; b=jGsCiH8aR/oHMfoc60RA83UmiID6dpsYV0EG2q5qGgcUURRuMfkoouW0WKU3+Bg9HR2c5A6g2BOH/W9kqySLHkUeYEg955BVr9TPmVA0Mn/O9f+MlsD+k9wF+DatXCC4oG2yGtALqdv/Cs3EteC5VsaziD0ZHcO67WjhiQ3yvGM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626897912; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=E44AAclzpTIljt+uwc9zjVKN1U0J8m7T2mfXeYGPYLM=; b=emJvjDZq9l4DbCDyTkRLXw9g5oR9ZUB15Fbuw3rzZEj6KUfxFLWAXPCmULKmfZOm6c8TmgBHVmVwdqeF5XZU2eKZF/hLjuMkrMezziusYFe1w1UxQeda5k75JeoTPi6vmu9KGkKWXVANwrqp3o4LAhNAMBu/oXbhBmR5tD8wf/I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626897912501370.4331485594315; Wed, 21 Jul 2021 13:05:12 -0700 (PDT) Received: from localhost ([::1]:33768 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6ISt-0002xM-Ds for importer@patchew.org; Wed, 21 Jul 2021 16:05:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36524) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IO0-0002Z0-Bc for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:08 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:53972) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6INx-0005fT-Gh for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:07 -0400 Received: by mail-pj1-x1030.google.com with SMTP id p9so2550389pjl.3 for ; Wed, 21 Jul 2021 13:00:05 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=E44AAclzpTIljt+uwc9zjVKN1U0J8m7T2mfXeYGPYLM=; b=TzFeEwyx3u6GxJQa5CiOOU1R5caZaJ/bM85/ASHlss241T2AZVLee7l3yu5Ltrx8gY 6Cmb5R1kTcIYeG9yt2/U9IpSibQtPvRgBr0Kr2XekWyEl3StJbSL9bLfHFZEFgT4IIBT w620Pdx277QD+xcoeaicEBEzTvuBDVEf48qtQ50SZT9Z5uhfFrwr1jE6EhP6PuRlaLEw e26WJeg1ssq3axfKshTHIYYMH6Ur8tb6lnXPQibEcrw+pZeky+bgettaO4qoc9MACqHS j+Uq/3kSI0S11BqjECJMeZN3/8NY54BlWcOB0vqIhPHt6AhZQm8jI157c0C0DMQmGgsd fnCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E44AAclzpTIljt+uwc9zjVKN1U0J8m7T2mfXeYGPYLM=; b=sb0bUq0AqQpTTF+/E1qlEuNPAlx/b9JsjwOrEGJ+cE2jh8/X9w4O5iBu/IRAGxznNE FNbYpzVLaUfl6w4lpB5nIE6maHug/qy+ZBsfOKvKiuEEuTSYRTlhIQsvtdsFIqdyyHWB WZT82kY+7qXIOCfXipYMERmxAx3U9vKk29yh+rCOKA4KU9eh9/ps3yMJI7BZRYh51tim FdvoIxuhuE7FFEuYAzckCm/kn+2nSLV/jXy7MM9XATzTWbPBpV0hfawxjfJrvjQpDwVt hrmQ74a+kEGPJwmlIcmSPBelmwc+XHeQ/aw6LSPVOE0aarKTlc5v2Cpl8nsfQsCb4n8Z iI0A== X-Gm-Message-State: AOAM5332AURtGIaf1sv7EevR7aNEApS/KxNUYkqirQbTk/CgHUWQdcbC 3zicAsPW+IpYPzBL+xNxAVEkl76PRm/LMg== X-Google-Smtp-Source: ABdhPJxA9RIq5b3QMQ67GAIfrtohO3BGZ5QBAdGN2iFlHxP37QTSRNg72/Nm6w2yvwuJejOxEBFa/g== X-Received: by 2002:a63:5963:: with SMTP id j35mr37300073pgm.341.1626897604124; Wed, 21 Jul 2021 13:00:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 05/27] accel/tcg: Standardize atomic helpers on softmmu api Date: Wed, 21 Jul 2021 09:59:32 -1000 Message-Id: <20210721195954.879535-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Cole Robinson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1626897913169100001 Content-Type: text/plain; charset="utf-8" Reduce the amount of code duplication by always passing the TCGMemOpIdx argument to helper_atomic_*. This is not currently used for user-only, but it's easy to ignore. Tested-by: Cole Robinson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 46 ----------------------- accel/tcg/cputlb.c | 32 ---------------- accel/tcg/user-exec.c | 26 ------------- tcg/tcg-op.c | 51 ++++++------------------- accel/tcg/atomic_common.c.inc | 70 +++++++++++++++++++++++++++++++++++ 5 files changed, 82 insertions(+), 143 deletions(-) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index 91a5b7e85f..37cbd722bf 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -39,8 +39,6 @@ DEF_HELPER_FLAGS_1(exit_atomic, TCG_CALL_NO_WG, noreturn,= env) DEF_HELPER_FLAGS_3(memset, TCG_CALL_NO_RWG, ptr, ptr, int, ptr) #endif /* IN_HELPER_PROTO */ =20 -#ifdef CONFIG_SOFTMMU - DEF_HELPER_FLAGS_5(atomic_cmpxchgb, TCG_CALL_NO_WG, i32, env, tl, i32, i32, i32) DEF_HELPER_FLAGS_5(atomic_cmpxchgw_be, TCG_CALL_NO_WG, @@ -88,50 +86,6 @@ DEF_HELPER_FLAGS_5(atomic_cmpxchgq_le, TCG_CALL_NO_WG, TCG_CALL_NO_WG, i32, env, tl, i32, i32) #endif /* CONFIG_ATOMIC64 */ =20 -#else - -DEF_HELPER_FLAGS_4(atomic_cmpxchgb, TCG_CALL_NO_WG, i32, env, tl, i32, i32) -DEF_HELPER_FLAGS_4(atomic_cmpxchgw_be, TCG_CALL_NO_WG, i32, env, tl, i32, = i32) -DEF_HELPER_FLAGS_4(atomic_cmpxchgw_le, TCG_CALL_NO_WG, i32, env, tl, i32, = i32) -DEF_HELPER_FLAGS_4(atomic_cmpxchgl_be, TCG_CALL_NO_WG, i32, env, tl, i32, = i32) -DEF_HELPER_FLAGS_4(atomic_cmpxchgl_le, TCG_CALL_NO_WG, i32, env, tl, i32, = i32) -#ifdef CONFIG_ATOMIC64 -DEF_HELPER_FLAGS_4(atomic_cmpxchgq_be, TCG_CALL_NO_WG, i64, env, tl, i64, = i64) -DEF_HELPER_FLAGS_4(atomic_cmpxchgq_le, TCG_CALL_NO_WG, i64, env, tl, i64, = i64) -#endif - -#ifdef CONFIG_ATOMIC64 -#define GEN_ATOMIC_HELPERS(NAME) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), b), \ - TCG_CALL_NO_WG, i32, env, tl, i32) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_le), \ - TCG_CALL_NO_WG, i32, env, tl, i32) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_be), \ - TCG_CALL_NO_WG, i32, env, tl, i32) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_le), \ - TCG_CALL_NO_WG, i32, env, tl, i32) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_be), \ - TCG_CALL_NO_WG, i32, env, tl, i32) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), q_le), \ - TCG_CALL_NO_WG, i64, env, tl, i64) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), q_be), \ - TCG_CALL_NO_WG, i64, env, tl, i64) -#else -#define GEN_ATOMIC_HELPERS(NAME) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), b), \ - TCG_CALL_NO_WG, i32, env, tl, i32) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_le), \ - TCG_CALL_NO_WG, i32, env, tl, i32) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_be), \ - TCG_CALL_NO_WG, i32, env, tl, i32) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_le), \ - TCG_CALL_NO_WG, i32, env, tl, i32) \ - DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_be), \ - TCG_CALL_NO_WG, i32, env, tl, i32) -#endif /* CONFIG_ATOMIC64 */ - -#endif /* CONFIG_SOFTMMU */ - GEN_ATOMIC_HELPERS(fetch_add) GEN_ATOMIC_HELPERS(fetch_and) GEN_ATOMIC_HELPERS(fetch_or) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 63da1cc96f..842cf4b572 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2725,38 +2725,6 @@ void cpu_stq_le_data(CPUArchState *env, target_ulong= ptr, uint64_t val) #include "atomic_template.h" #endif =20 -/* Second set of helpers are directly callable from TCG as helpers. */ - -#undef EXTRA_ARGS -#undef ATOMIC_NAME -#undef ATOMIC_MMU_LOOKUP_RW -#undef ATOMIC_MMU_LOOKUP_R -#undef ATOMIC_MMU_LOOKUP_W - -#define EXTRA_ARGS , TCGMemOpIdx oi -#define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) -#define ATOMIC_MMU_LOOKUP_RW \ - atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ | PAGE_WRITE, GE= TPC()) -#define ATOMIC_MMU_LOOKUP_R \ - atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ, GETPC()) -#define ATOMIC_MMU_LOOKUP_W \ - atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_WRITE, GETPC()) - -#define DATA_SIZE 1 -#include "atomic_template.h" - -#define DATA_SIZE 2 -#include "atomic_template.h" - -#define DATA_SIZE 4 -#include "atomic_template.h" - -#ifdef CONFIG_ATOMIC64 -#define DATA_SIZE 8 -#include "atomic_template.h" -#endif -#undef ATOMIC_MMU_IDX - /* Code access functions. */ =20 static uint64_t full_ldub_code(CPUArchState *env, target_ulong addr, diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 82dbe06f08..7e92d6b875 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1269,29 +1269,3 @@ static void *atomic_mmu_lookup(CPUArchState *env, ta= rget_ulong addr, #define DATA_SIZE 16 #include "atomic_template.h" #endif - -/* - * Second set of functions is directly callable from TCG. - */ - -#undef EXTRA_ARGS -#undef ATOMIC_NAME -#undef ATOMIC_MMU_DECLS - -#define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END)) -#define EXTRA_ARGS -#define ATOMIC_MMU_DECLS uintptr_t retaddr =3D GETPC() - -#define DATA_SIZE 1 -#include "atomic_template.h" - -#define DATA_SIZE 2 -#include "atomic_template.h" - -#define DATA_SIZE 4 -#include "atomic_template.h" - -#ifdef CONFIG_ATOMIC64 -#define DATA_SIZE 8 -#include "atomic_template.h" -#endif diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 0c561fb253..75eaa910c9 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -3084,7 +3084,6 @@ static void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 va= l, MemOp opc) } } =20 -#ifdef CONFIG_SOFTMMU typedef void (*gen_atomic_cx_i32)(TCGv_i32, TCGv_env, TCGv, TCGv_i32, TCGv_i32, TCGv_i32); typedef void (*gen_atomic_cx_i64)(TCGv_i64, TCGv_env, TCGv, @@ -3093,12 +3092,6 @@ typedef void (*gen_atomic_op_i32)(TCGv_i32, TCGv_env= , TCGv, TCGv_i32, TCGv_i32); typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv, TCGv_i64, TCGv_i32); -#else -typedef void (*gen_atomic_cx_i32)(TCGv_i32, TCGv_env, TCGv, TCGv_i32, TCGv= _i32); -typedef void (*gen_atomic_cx_i64)(TCGv_i64, TCGv_env, TCGv, TCGv_i64, TCGv= _i64); -typedef void (*gen_atomic_op_i32)(TCGv_i32, TCGv_env, TCGv, TCGv_i32); -typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv, TCGv_i64); -#endif =20 #ifdef CONFIG_ATOMIC64 # define WITH_ATOMIC64(X) X, @@ -3140,18 +3133,13 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv= addr, TCGv_i32 cmpv, tcg_temp_free_i32(t1); } else { gen_atomic_cx_i32 gen; + TCGMemOpIdx oi; =20 gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; tcg_debug_assert(gen !=3D NULL); =20 -#ifdef CONFIG_SOFTMMU - { - TCGMemOpIdx oi =3D make_memop_idx(memop & ~MO_SIGN, idx); - gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); - } -#else - gen(retv, cpu_env, addr, cmpv, newv); -#endif + oi =3D make_memop_idx(memop & ~MO_SIGN, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); =20 if (memop & MO_SIGN) { tcg_gen_ext_i32(retv, retv, memop); @@ -3184,18 +3172,13 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv= addr, TCGv_i64 cmpv, } else if ((memop & MO_SIZE) =3D=3D MO_64) { #ifdef CONFIG_ATOMIC64 gen_atomic_cx_i64 gen; + TCGMemOpIdx oi; =20 gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; tcg_debug_assert(gen !=3D NULL); =20 -#ifdef CONFIG_SOFTMMU - { - TCGMemOpIdx oi =3D make_memop_idx(memop, idx); - gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); - } -#else - gen(retv, cpu_env, addr, cmpv, newv); -#endif + oi =3D make_memop_idx(memop, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); #else gen_helper_exit_atomic(cpu_env); /* Produce a result, so that we have a well-formed opcode stream @@ -3245,20 +3228,15 @@ static void do_atomic_op_i32(TCGv_i32 ret, TCGv add= r, TCGv_i32 val, TCGArg idx, MemOp memop, void * const table[]) { gen_atomic_op_i32 gen; + TCGMemOpIdx oi; =20 memop =3D tcg_canonicalize_memop(memop, 0, 0); =20 gen =3D table[memop & (MO_SIZE | MO_BSWAP)]; tcg_debug_assert(gen !=3D NULL); =20 -#ifdef CONFIG_SOFTMMU - { - TCGMemOpIdx oi =3D make_memop_idx(memop & ~MO_SIGN, idx); - gen(ret, cpu_env, addr, val, tcg_constant_i32(oi)); - } -#else - gen(ret, cpu_env, addr, val); -#endif + oi =3D make_memop_idx(memop & ~MO_SIGN, idx); + gen(ret, cpu_env, addr, val, tcg_constant_i32(oi)); =20 if (memop & MO_SIGN) { tcg_gen_ext_i32(ret, ret, memop); @@ -3292,18 +3270,13 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv add= r, TCGv_i64 val, if ((memop & MO_SIZE) =3D=3D MO_64) { #ifdef CONFIG_ATOMIC64 gen_atomic_op_i64 gen; + TCGMemOpIdx oi; =20 gen =3D table[memop & (MO_SIZE | MO_BSWAP)]; tcg_debug_assert(gen !=3D NULL); =20 -#ifdef CONFIG_SOFTMMU - { - TCGMemOpIdx oi =3D make_memop_idx(memop & ~MO_SIGN, idx); - gen(ret, cpu_env, addr, val, tcg_constant_i32(oi)); - } -#else - gen(ret, cpu_env, addr, val); -#endif + oi =3D make_memop_idx(memop & ~MO_SIGN, idx); + gen(ret, cpu_env, addr, val, tcg_constant_i32(oi)); #else gen_helper_exit_atomic(cpu_env); /* Produce a result, so that we have a well-formed opcode stream diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc index 344525b0bb..a668cf0d6f 100644 --- a/accel/tcg/atomic_common.c.inc +++ b/accel/tcg/atomic_common.c.inc @@ -52,3 +52,73 @@ void atomic_trace_st_post(CPUArchState *env, target_ulon= g addr, uint16_t info) { qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info); } + +/* + * Atomic helpers callable from TCG. + * These have a common interface and all defer to cpu_atomic_* + * using the host return address from GETPC(). + */ + +#define CMPXCHG_HELPER(OP, TYPE) \ + TYPE HELPER(atomic_##OP)(CPUArchState *env, target_ulong addr, \ + TYPE oldv, TYPE newv, uint32_t oi) \ + { return cpu_atomic_##OP##_mmu(env, addr, oldv, newv, oi, GETPC()); } + +CMPXCHG_HELPER(cmpxchgb, uint32_t) +CMPXCHG_HELPER(cmpxchgw_be, uint32_t) +CMPXCHG_HELPER(cmpxchgw_le, uint32_t) +CMPXCHG_HELPER(cmpxchgl_be, uint32_t) +CMPXCHG_HELPER(cmpxchgl_le, uint32_t) + +#ifdef CONFIG_ATOMIC64 +CMPXCHG_HELPER(cmpxchgq_be, uint64_t) +CMPXCHG_HELPER(cmpxchgq_le, uint64_t) +#endif + +#undef CMPXCHG_HELPER + +#define ATOMIC_HELPER(OP, TYPE) \ + TYPE HELPER(glue(atomic_,OP))(CPUArchState *env, target_ulong addr, \ + TYPE val, uint32_t oi) \ + { return glue(glue(cpu_atomic_,OP),_mmu)(env, addr, val, oi, GETPC());= } + +#ifdef CONFIG_ATOMIC64 +#define GEN_ATOMIC_HELPERS(OP) \ + ATOMIC_HELPER(glue(OP,b), uint32_t) \ + ATOMIC_HELPER(glue(OP,w_be), uint32_t) \ + ATOMIC_HELPER(glue(OP,w_le), uint32_t) \ + ATOMIC_HELPER(glue(OP,l_be), uint32_t) \ + ATOMIC_HELPER(glue(OP,l_le), uint32_t) \ + ATOMIC_HELPER(glue(OP,q_be), uint64_t) \ + ATOMIC_HELPER(glue(OP,q_le), uint64_t) +#else +#define GEN_ATOMIC_HELPERS(OP) \ + ATOMIC_HELPER(glue(OP,b), uint32_t) \ + ATOMIC_HELPER(glue(OP,w_be), uint32_t) \ + ATOMIC_HELPER(glue(OP,w_le), uint32_t) \ + ATOMIC_HELPER(glue(OP,l_be), uint32_t) \ + ATOMIC_HELPER(glue(OP,l_le), uint32_t) +#endif + +GEN_ATOMIC_HELPERS(fetch_add) +GEN_ATOMIC_HELPERS(fetch_and) +GEN_ATOMIC_HELPERS(fetch_or) +GEN_ATOMIC_HELPERS(fetch_xor) +GEN_ATOMIC_HELPERS(fetch_smin) +GEN_ATOMIC_HELPERS(fetch_umin) +GEN_ATOMIC_HELPERS(fetch_smax) +GEN_ATOMIC_HELPERS(fetch_umax) + +GEN_ATOMIC_HELPERS(add_fetch) +GEN_ATOMIC_HELPERS(and_fetch) +GEN_ATOMIC_HELPERS(or_fetch) +GEN_ATOMIC_HELPERS(xor_fetch) +GEN_ATOMIC_HELPERS(smin_fetch) +GEN_ATOMIC_HELPERS(umin_fetch) +GEN_ATOMIC_HELPERS(smax_fetch) +GEN_ATOMIC_HELPERS(umax_fetch) + +GEN_ATOMIC_HELPERS(xchg) + +#undef ATOMIC_HELPER +#undef GEN_ATOMIC_HELPERS --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626898041531158.21107501495646; Wed, 21 Jul 2021 13:07:21 -0700 (PDT) Received: from localhost ([::1]:42356 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6IUy-0000Pz-9R for importer@patchew.org; Wed, 21 Jul 2021 16:07:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36538) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IO1-0002cn-Ha for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:09 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:36815) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6INz-0005gB-3x for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:09 -0400 Received: by mail-pl1-x62e.google.com with SMTP id x16so1650385plg.3 for ; Wed, 21 Jul 2021 13:00:06 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AJc0gflkXzJ2IW/hPKxX146OQW57gZ0MjkK6XwFBGFA=; b=QAL7QgX5y8OHHVPMIz+YgvbIATzL2jhYuGOO4NwT5iveWmP74n84LUmpgYgJcfByIp 9ol2rbVnzZ6FGfEny6UaW332N/XQNOzoaO3G8hFj9nJGf/kGM1PuV6imOfxLyGsf7yxC MqgSKDAtGN02U0yw6h+Cqty3FtfAt1olqP3kHUqpdlzuhMKxnyTkFbD9OYKMDabTiWg+ VSUjZ/SzvkIf0YeWT1JUPIOcUd7UmewK3XM3VEjo2EobQw1qCeyhnII5PCdtjPCzO9JL JocEFRH7e5NAlMJrk/XWlSqbWdgrTB75c15UPIzfwFOFEG9KD33ZNIFoOlC7gj3EURpP dJOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AJc0gflkXzJ2IW/hPKxX146OQW57gZ0MjkK6XwFBGFA=; b=jrwLK7WPaJ973SK47mUbMitmhs4QlQf4w2EJOR+iE0To9GTvymYUh2Gs8AW5tBgeFm FT1zcpx0Lbu+eZsNzCQh+CC1jUSvmJrbfv6Lbl6/xvkY1+1jF7z7TraP1fFCwOxxJNju QLIDLgLgoEshuthm0b99tuaAp3mK9ebcScdwgR/OhfKlTOb8EpOr4yxsjGyQdS4cyvHp yUMDIrf580BAqIuCreJ3qSPFl0ZLfYnHYvHXnliTUhyhBtDXbfsxO56BkLgULTKcw393 DgLeeiSsKlvV+K3HBiy/OWfUfwl3/OH2EV+m5dfRa49d50Vf6ubJVdAWxS+KY2X1QHxT EKQg== X-Gm-Message-State: AOAM532o4/WHX9bRlXeD+Ar1rDWV4lmrYitlv5vwNKtD2XOsl/rUFr3h YpzSi2mlRnsQf98pfh67UTrS6o+nZ2w= X-Google-Smtp-Source: ABdhPJxAy7tHEcp3fKPyFgTRyIF8dW3dnJhvH7bx4K2/WfvRZKhdK0VVl40ly1mKK4wipYH9N/YjMA== X-Received: by 2002:a17:90a:ea12:: with SMTP id w18mr37392396pjy.103.1626897605588; Wed, 21 Jul 2021 13:00:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 06/27] accel/tcg: Fold EXTRA_ARGS into atomic_template.h Date: Wed, 21 Jul 2021 09:59:33 -1000 Message-Id: <20210721195954.879535-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Cole Robinson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626898042832100002 All instances of EXTRA_ARGS are now identical. Tested-by: Cole Robinson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 36 ++++++++++++++++++++---------------- accel/tcg/cputlb.c | 1 - accel/tcg/user-exec.c | 1 - 3 files changed, 20 insertions(+), 18 deletions(-) diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index d347462af5..52fb26a274 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -71,7 +71,8 @@ #endif =20 ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr, - ABI_TYPE cmpv, ABI_TYPE newv EXTRA_ARGS) + ABI_TYPE cmpv, ABI_TYPE newv, + TCGMemOpIdx oi, uintptr_t retaddr) { ATOMIC_MMU_DECLS; DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; @@ -92,7 +93,8 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_u= long addr, =20 #if DATA_SIZE >=3D 16 #if HAVE_ATOMIC128 -ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr EXTRA_ARGS) +ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { ATOMIC_MMU_DECLS; DATA_TYPE val, *haddr =3D ATOMIC_MMU_LOOKUP_R; @@ -106,8 +108,8 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulon= g addr EXTRA_ARGS) return val; } =20 -void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, - ABI_TYPE val EXTRA_ARGS) +void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val, + TCGMemOpIdx oi, uintptr_t retaddr) { ATOMIC_MMU_DECLS; DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_W; @@ -121,8 +123,8 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong ad= dr, } #endif #else -ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, - ABI_TYPE val EXTRA_ARGS) +ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE = val, + TCGMemOpIdx oi, uintptr_t retaddr) { ATOMIC_MMU_DECLS; DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; @@ -139,7 +141,7 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ul= ong addr, =20 #define GEN_ATOMIC_HELPER(X) \ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ - ABI_TYPE val EXTRA_ARGS) \ + ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) \ { \ ATOMIC_MMU_DECLS; \ DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; \ @@ -173,7 +175,7 @@ GEN_ATOMIC_HELPER(xor_fetch) */ #define GEN_ATOMIC_HELPER_FN(X, FN, XDATA_TYPE, RET) \ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ - ABI_TYPE xval EXTRA_ARGS) \ + ABI_TYPE xval, TCGMemOpIdx oi, uintptr_t retaddr) \ { \ ATOMIC_MMU_DECLS; \ XDATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; \ @@ -218,7 +220,8 @@ GEN_ATOMIC_HELPER_FN(umax_fetch, MAX, DATA_TYPE, new) #endif =20 ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr, - ABI_TYPE cmpv, ABI_TYPE newv EXTRA_ARGS) + ABI_TYPE cmpv, ABI_TYPE newv, + TCGMemOpIdx oi, uintptr_t retaddr) { ATOMIC_MMU_DECLS; DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; @@ -239,7 +242,8 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target= _ulong addr, =20 #if DATA_SIZE >=3D 16 #if HAVE_ATOMIC128 -ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr EXTRA_ARGS) +ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi, uintptr_t retaddr) { ATOMIC_MMU_DECLS; DATA_TYPE val, *haddr =3D ATOMIC_MMU_LOOKUP_R; @@ -253,8 +257,8 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulon= g addr EXTRA_ARGS) return BSWAP(val); } =20 -void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, - ABI_TYPE val EXTRA_ARGS) +void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val, + TCGMemOpIdx oi, uintptr_t retaddr) { ATOMIC_MMU_DECLS; DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_W; @@ -270,8 +274,8 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong ad= dr, } #endif #else -ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, - ABI_TYPE val EXTRA_ARGS) +ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE = val, + TCGMemOpIdx oi, uintptr_t retaddr) { ATOMIC_MMU_DECLS; DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; @@ -288,7 +292,7 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ul= ong addr, =20 #define GEN_ATOMIC_HELPER(X) \ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ - ABI_TYPE val EXTRA_ARGS) \ + ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) \ { \ ATOMIC_MMU_DECLS; \ DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; \ @@ -320,7 +324,7 @@ GEN_ATOMIC_HELPER(xor_fetch) */ #define GEN_ATOMIC_HELPER_FN(X, FN, XDATA_TYPE, RET) \ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ - ABI_TYPE xval EXTRA_ARGS) \ + ABI_TYPE xval, TCGMemOpIdx oi, uintptr_t retaddr) \ { \ ATOMIC_MMU_DECLS; \ XDATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 842cf4b572..cc0e673222 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2691,7 +2691,6 @@ void cpu_stq_le_data(CPUArchState *env, target_ulong = ptr, uint64_t val) * This makes them callable from other helpers. */ =20 -#define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr #define ATOMIC_NAME(X) \ glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu) #define ATOMIC_MMU_DECLS diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 7e92d6b875..f6f8ddeb60 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1241,7 +1241,6 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, * This makes them callable from other helpers. */ =20 -#define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr #define ATOMIC_NAME(X) \ glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu) #define ATOMIC_MMU_DECLS --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626897912493483.5290903949501; Wed, 21 Jul 2021 13:05:12 -0700 (PDT) Received: from localhost ([::1]:33816 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6ISt-0002zI-7X for importer@patchew.org; Wed, 21 Jul 2021 16:05:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36554) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IO2-0002gP-Qd for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:10 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:40840) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IO0-0005gt-Nq for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:10 -0400 Received: by mail-pl1-x62a.google.com with SMTP id q13so720167plx.7 for ; Wed, 21 Jul 2021 13:00:08 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IYPOS53QXxnMU3psldAYFVGdynnCru1uw1bavCP9XhE=; b=Jb/pOYJjDz/q09sYg7foqBuen31cwzHeKkb0makL6SnZsnkMHuSyp4b5ctq0DsBU7B 4xGRQDy5VvcZrg8sVXj6nCJJp/ufrhn8ZnxA6n3lDdw6BW6UBXa13VJ5jzmrUaX8krz/ wYojUTmLzv6PYYD0klYz9RZlo26ZMnspsu7w2QAnHAFY5QaVr0eOkLoH6+H8Nr9j+MCH ZRZD5+mLA6IpX3AT3gYQQ0CUE5JKuwfV8vHjt8kg4TehnjBqP5em2Z0UpwCCZAyomvQe Xm9p0hDtzy2EPb6TrDecve6cw8Yy4/37Vwal5MECk6SqHOStxnibKiMA+WIgiqtOlZzV YSZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IYPOS53QXxnMU3psldAYFVGdynnCru1uw1bavCP9XhE=; b=Lv6N/15eXPEWZiEdkaYr9MOercdNBRC+ELisqjpOEx6G+Ey/pCbFCFPz+5HeoE0El9 Pk0XOKHwt5KHvcOnmpZLflzimC1W3zzjDNhYf1dhmTrrnB7Le1LjXWroUfY70TIT+1ye GqdgN566uTnzdAVnxJWg/6undwkziSXCNCN9nf4V0CVxnM4uRFJROOyO2HRnxaaN+rfr cF1aoB+hREBMepSkVhbNG2R1u57Ck1vlWJXmRfLHP6hEU9eYdrfeE976okb+gfN9w7HX HCHmM/l0/N+nG0GVA3MUxv6K6e9WOxqXxGLSQzQf63ZMQbO1YR6WZN17U4+cALdx5IaK 7KKw== X-Gm-Message-State: AOAM533f7vMNQd7G+sLzRYzOYzTDHEv3BI6vPFv9FYJTw+2S2Sp/NYjq dMvnWmCeLx0oww58QNMJ+BrBv/YheCev9A== X-Google-Smtp-Source: ABdhPJzoaI0S04QwpWsW+0NPBemJ0Kx/J2TSyMnLze9C9sSXrA3mX3r15I1mjJ5cE+ABfxm9Kk35tQ== X-Received: by 2002:a17:90a:4481:: with SMTP id t1mr37103995pjg.232.1626897607039; Wed, 21 Jul 2021 13:00:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 07/27] accel/tcg: Remove ATOMIC_MMU_DECLS Date: Wed, 21 Jul 2021 09:59:34 -1000 Message-Id: <20210721195954.879535-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Cole Robinson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626897913189100002 All definitions are now empty. Tested-by: Cole Robinson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 12 ------------ accel/tcg/cputlb.c | 1 - accel/tcg/user-exec.c | 1 - 3 files changed, 14 deletions(-) diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index 52fb26a274..ae6b6a03be 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -74,7 +74,6 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_u= long addr, ABI_TYPE cmpv, ABI_TYPE newv, TCGMemOpIdx oi, uintptr_t retaddr) { - ATOMIC_MMU_DECLS; DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; DATA_TYPE ret; uint16_t info =3D trace_mem_build_info(SHIFT, false, 0, false, @@ -96,7 +95,6 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_u= long addr, ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - ATOMIC_MMU_DECLS; DATA_TYPE val, *haddr =3D ATOMIC_MMU_LOOKUP_R; uint16_t info =3D trace_mem_build_info(SHIFT, false, 0, false, ATOMIC_MMU_IDX); @@ -111,7 +109,6 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulon= g addr, void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) { - ATOMIC_MMU_DECLS; DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_W; uint16_t info =3D trace_mem_build_info(SHIFT, false, 0, true, ATOMIC_MMU_IDX); @@ -126,7 +123,6 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong ad= dr, ABI_TYPE val, ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE = val, TCGMemOpIdx oi, uintptr_t retaddr) { - ATOMIC_MMU_DECLS; DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; DATA_TYPE ret; uint16_t info =3D trace_mem_build_info(SHIFT, false, 0, false, @@ -143,7 +139,6 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ul= ong addr, ABI_TYPE val, ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) \ { \ - ATOMIC_MMU_DECLS; \ DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; \ DATA_TYPE ret; \ uint16_t info =3D trace_mem_build_info(SHIFT, false, 0, false, \ @@ -177,7 +172,6 @@ GEN_ATOMIC_HELPER(xor_fetch) ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ ABI_TYPE xval, TCGMemOpIdx oi, uintptr_t retaddr) \ { \ - ATOMIC_MMU_DECLS; \ XDATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; \ XDATA_TYPE cmp, old, new, val =3D xval; \ uint16_t info =3D trace_mem_build_info(SHIFT, false, 0, false, \ @@ -223,7 +217,6 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target= _ulong addr, ABI_TYPE cmpv, ABI_TYPE newv, TCGMemOpIdx oi, uintptr_t retaddr) { - ATOMIC_MMU_DECLS; DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; DATA_TYPE ret; uint16_t info =3D trace_mem_build_info(SHIFT, false, MO_BSWAP, false, @@ -245,7 +238,6 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target= _ulong addr, ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - ATOMIC_MMU_DECLS; DATA_TYPE val, *haddr =3D ATOMIC_MMU_LOOKUP_R; uint16_t info =3D trace_mem_build_info(SHIFT, false, MO_BSWAP, false, ATOMIC_MMU_IDX); @@ -260,7 +252,6 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulon= g addr, void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) { - ATOMIC_MMU_DECLS; DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_W; uint16_t info =3D trace_mem_build_info(SHIFT, false, MO_BSWAP, true, ATOMIC_MMU_IDX); @@ -277,7 +268,6 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong ad= dr, ABI_TYPE val, ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE = val, TCGMemOpIdx oi, uintptr_t retaddr) { - ATOMIC_MMU_DECLS; DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; ABI_TYPE ret; uint16_t info =3D trace_mem_build_info(SHIFT, false, MO_BSWAP, false, @@ -294,7 +284,6 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ul= ong addr, ABI_TYPE val, ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) \ { \ - ATOMIC_MMU_DECLS; \ DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; \ DATA_TYPE ret; \ uint16_t info =3D trace_mem_build_info(SHIFT, false, MO_BSWAP, \ @@ -326,7 +315,6 @@ GEN_ATOMIC_HELPER(xor_fetch) ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ ABI_TYPE xval, TCGMemOpIdx oi, uintptr_t retaddr) \ { \ - ATOMIC_MMU_DECLS; \ XDATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; \ XDATA_TYPE ldo, ldn, old, new, val =3D xval; \ uint16_t info =3D trace_mem_build_info(SHIFT, false, MO_BSWAP, \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index cc0e673222..dc646e964a 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2693,7 +2693,6 @@ void cpu_stq_le_data(CPUArchState *env, target_ulong = ptr, uint64_t val) =20 #define ATOMIC_NAME(X) \ glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu) -#define ATOMIC_MMU_DECLS #define ATOMIC_MMU_LOOKUP_RW \ atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ | PAGE_WRITE, re= taddr) #define ATOMIC_MMU_LOOKUP_R \ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index f6f8ddeb60..bc4a38b4df 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1243,7 +1243,6 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, =20 #define ATOMIC_NAME(X) \ glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu) -#define ATOMIC_MMU_DECLS #define ATOMIC_MMU_LOOKUP_RW atomic_mmu_lookup(env, addr, DATA_SIZE, reta= ddr) #define ATOMIC_MMU_LOOKUP_R ATOMIC_MMU_LOOKUP_RW #define ATOMIC_MMU_LOOKUP_W ATOMIC_MMU_LOOKUP_RW --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1626897977; cv=none; d=zohomail.com; s=zohoarc; b=isIQc2dyc8rma2iOyUfwaJidHXmPXHH82BLLTLzrHRV/JoT99gEj38Cmn2D69Q7th2V34hlXZ4+7+0tG+WOwNAGW35gswZP4LfBoHojpB5HTvHcv9T7Nnk3hcIKbIxWidCk/yINyBIqm0m69Q4/J++cE7k5ZgLlHGQ1P8Mf8ziw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626897977; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yXkWA0eZbeR3PWDmUYnZO8DFWV5ZMhdaTqrtSIzDRQk=; b=cWzSk4dtA854FkW00cC5zjrRZ2Bmy/e3v3/8qp36cXsAKCeH+micuw+kr/r4fwldjDd71KRWk2bk+4tJi0H4eaVj5rckSHONMByBcHljpjUQQwqrIKRRTSqguc77DcSOULaJ9VGWFSml7AklzuCG6xnu2CJhNRA+Tn9h0JgbZLk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626897977472240.07298010897864; Wed, 21 Jul 2021 13:06:17 -0700 (PDT) Received: from localhost ([::1]:36798 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6ITw-000589-2b for importer@patchew.org; Wed, 21 Jul 2021 16:06:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36572) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IO3-0002iv-TT for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:11 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:37782) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IO1-0005hi-RY for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:11 -0400 Received: by mail-pj1-x102a.google.com with SMTP id a17-20020a17090abe11b0290173ce472b8aso532213pjs.2 for ; Wed, 21 Jul 2021 13:00:09 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yXkWA0eZbeR3PWDmUYnZO8DFWV5ZMhdaTqrtSIzDRQk=; b=nAJVf4/w6mcR8riLMZ2Efsoa0ZuX88jpobolEhJe9e175P24AEubhSDqGxdWmg5Od1 VDq/UNN/aGjACBYFbwAqAaR1zBTK5qr37E85buSiVIdujs2LzQ1GNuu3jJNLNkSU7TDL j6btUS+AMR25WAI+DL96KgF6D3kYeMoAi0YqQx+xItItXUaOemrpDMnm+xZDNPb+lDMo 3zruxBqndiQ8NhKhV/JZt+R3uMjMVRTsusP+sOn9c0Gws4qTMesdmssNEfk6fqD08LgG 52Ti10vos54jDxrxcuQMrbDrQrHbjAEl3Jp68oCr93zsqzFSsutpuGUVs7HPSO75APWe eDNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yXkWA0eZbeR3PWDmUYnZO8DFWV5ZMhdaTqrtSIzDRQk=; b=LQkxtLxbJE3SgKYmJkAl6jlSggcJ5WphtXD5me4xlIjjSqB/TDH1XKmqJbKIiUQT1j 8zipujJ4+n1nS2UjLyJLcx1u8gQ/Cv9KQ8R46iIcwHsYBTu4FfKvi/iHpG3vaED1bWCT sWrKCQjyZVDHqtKck+TyWBSCBwW9nX2d3CjIrEggOQX90vaDTPnpp07MGhlE16RV6JMM Cr19OMEcKd41LC1rjdPvIdqnr4ozCrio/7x1YzgbQ/eRedc49UkQmJru2HszMhaGiqzO e0LqCoiGUHXLBBVH/E3MGa5yFKQDqLzSf3K7GxdtEjaPilXNGM5+/EiLLe/R7NmdEswS hUnQ== X-Gm-Message-State: AOAM530assu1xPsu4Npylg3ISxFaxvlLpkWWFOeYNpzxLIyHf2ty9sf8 JuM9xal/p65FmWTg4sFM5buQlvFgqwUNwQ== X-Google-Smtp-Source: ABdhPJy182H6nmaCf4C8TFbDJeoxJ7zh8/cmmmopq8M9Sagc2Oq1AZiDcDiPVFbBGx71C7QI3SyUfQ== X-Received: by 2002:a63:1621:: with SMTP id w33mr12475716pgl.291.1626897608493; Wed, 21 Jul 2021 13:00:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 08/27] accel/tcg: Expand ATOMIC_MMU_LOOKUP_* Date: Wed, 21 Jul 2021 09:59:35 -1000 Message-Id: <20210721195954.879535-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Cole Robinson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1626897980242100001 Content-Type: text/plain; charset="utf-8" Unify the parameters of atomic_mmu_lookup between cputlb.c and user-exec.c. Call the function directly, and remove the macros. Tested-by: Cole Robinson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 41 +++++++++++++++++++++++++------------ accel/tcg/cputlb.c | 7 +------ accel/tcg/user-exec.c | 12 ++++++----- 3 files changed, 36 insertions(+), 24 deletions(-) diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index ae6b6a03be..6ee0158c5f 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -74,7 +74,8 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_u= long addr, ABI_TYPE cmpv, ABI_TYPE newv, TCGMemOpIdx oi, uintptr_t retaddr) { - DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; + DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, + PAGE_READ | PAGE_WRITE, retaddr); DATA_TYPE ret; uint16_t info =3D trace_mem_build_info(SHIFT, false, 0, false, ATOMIC_MMU_IDX); @@ -95,7 +96,9 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_u= long addr, ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - DATA_TYPE val, *haddr =3D ATOMIC_MMU_LOOKUP_R; + DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, + PAGE_READ, retaddr); + DATA_TYPE val; uint16_t info =3D trace_mem_build_info(SHIFT, false, 0, false, ATOMIC_MMU_IDX); =20 @@ -109,7 +112,8 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulon= g addr, void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) { - DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_W; + DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, + PAGE_WRITE, retaddr); uint16_t info =3D trace_mem_build_info(SHIFT, false, 0, true, ATOMIC_MMU_IDX); =20 @@ -123,7 +127,8 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong ad= dr, ABI_TYPE val, ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE = val, TCGMemOpIdx oi, uintptr_t retaddr) { - DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; + DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, + PAGE_READ | PAGE_WRITE, retaddr); DATA_TYPE ret; uint16_t info =3D trace_mem_build_info(SHIFT, false, 0, false, ATOMIC_MMU_IDX); @@ -139,7 +144,8 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ul= ong addr, ABI_TYPE val, ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) \ { \ - DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; \ + DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ + PAGE_READ | PAGE_WRITE, retaddr);= \ DATA_TYPE ret; \ uint16_t info =3D trace_mem_build_info(SHIFT, false, 0, false, \ ATOMIC_MMU_IDX); \ @@ -161,7 +167,8 @@ GEN_ATOMIC_HELPER(xor_fetch) =20 #undef GEN_ATOMIC_HELPER =20 -/* These helpers are, as a whole, full barriers. Within the helper, +/* + * These helpers are, as a whole, full barriers. Within the helper, * the leading barrier is explicit and the trailing barrier is within * cmpxchg primitive. * @@ -172,7 +179,8 @@ GEN_ATOMIC_HELPER(xor_fetch) ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ ABI_TYPE xval, TCGMemOpIdx oi, uintptr_t retaddr) \ { \ - XDATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; \ + XDATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ + PAGE_READ | PAGE_WRITE, retaddr)= ; \ XDATA_TYPE cmp, old, new, val =3D xval; \ uint16_t info =3D trace_mem_build_info(SHIFT, false, 0, false, \ ATOMIC_MMU_IDX); \ @@ -217,7 +225,8 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target= _ulong addr, ABI_TYPE cmpv, ABI_TYPE newv, TCGMemOpIdx oi, uintptr_t retaddr) { - DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; + DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, + PAGE_READ | PAGE_WRITE, retaddr); DATA_TYPE ret; uint16_t info =3D trace_mem_build_info(SHIFT, false, MO_BSWAP, false, ATOMIC_MMU_IDX); @@ -238,7 +247,9 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target= _ulong addr, ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi, uintptr_t retaddr) { - DATA_TYPE val, *haddr =3D ATOMIC_MMU_LOOKUP_R; + DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, + PAGE_READ, retaddr); + DATA_TYPE val; uint16_t info =3D trace_mem_build_info(SHIFT, false, MO_BSWAP, false, ATOMIC_MMU_IDX); =20 @@ -252,7 +263,8 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulon= g addr, void ATOMIC_NAME(st)(CPUArchState *env, target_ulong addr, ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) { - DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_W; + DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, + PAGE_WRITE, retaddr); uint16_t info =3D trace_mem_build_info(SHIFT, false, MO_BSWAP, true, ATOMIC_MMU_IDX); =20 @@ -268,7 +280,8 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong ad= dr, ABI_TYPE val, ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE = val, TCGMemOpIdx oi, uintptr_t retaddr) { - DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; + DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, + PAGE_READ | PAGE_WRITE, retaddr); ABI_TYPE ret; uint16_t info =3D trace_mem_build_info(SHIFT, false, MO_BSWAP, false, ATOMIC_MMU_IDX); @@ -284,7 +297,8 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ul= ong addr, ABI_TYPE val, ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ ABI_TYPE val, TCGMemOpIdx oi, uintptr_t retaddr) \ { \ - DATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; \ + DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ + PAGE_READ | PAGE_WRITE, retaddr);= \ DATA_TYPE ret; \ uint16_t info =3D trace_mem_build_info(SHIFT, false, MO_BSWAP, \ false, ATOMIC_MMU_IDX); \ @@ -315,7 +329,8 @@ GEN_ATOMIC_HELPER(xor_fetch) ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ ABI_TYPE xval, TCGMemOpIdx oi, uintptr_t retaddr) \ { \ - XDATA_TYPE *haddr =3D ATOMIC_MMU_LOOKUP_RW; \ + XDATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ + PAGE_READ | PAGE_WRITE, retaddr)= ; \ XDATA_TYPE ldo, ldn, old, new, val =3D xval; \ uint16_t info =3D trace_mem_build_info(SHIFT, false, MO_BSWAP, \ false, ATOMIC_MMU_IDX); \ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index dc646e964a..b1e5471f94 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2693,12 +2693,7 @@ void cpu_stq_le_data(CPUArchState *env, target_ulong= ptr, uint64_t val) =20 #define ATOMIC_NAME(X) \ glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu) -#define ATOMIC_MMU_LOOKUP_RW \ - atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ | PAGE_WRITE, re= taddr) -#define ATOMIC_MMU_LOOKUP_R \ - atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ, retaddr) -#define ATOMIC_MMU_LOOKUP_W \ - atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_WRITE, retaddr) + #define ATOMIC_MMU_CLEANUP #define ATOMIC_MMU_IDX get_mmuidx(oi) =20 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index bc4a38b4df..90d1a2d327 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1221,9 +1221,14 @@ uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr ptr) return ret; } =20 -/* Do not allow unaligned operations to proceed. Return the host address.= */ +/* + * Do not allow unaligned operations to proceed. Return the host address. + * + * @prot may be PAGE_READ, PAGE_WRITE, or PAGE_READ|PAGE_WRITE. + */ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, - int size, uintptr_t retaddr) + TCGMemOpIdx oi, int size, int prot, + uintptr_t retaddr) { /* Enforce qemu required alignment. */ if (unlikely(addr & (size - 1))) { @@ -1243,9 +1248,6 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, =20 #define ATOMIC_NAME(X) \ glue(glue(glue(cpu_atomic_ ## X, SUFFIX), END), _mmu) -#define ATOMIC_MMU_LOOKUP_RW atomic_mmu_lookup(env, addr, DATA_SIZE, reta= ddr) -#define ATOMIC_MMU_LOOKUP_R ATOMIC_MMU_LOOKUP_RW -#define ATOMIC_MMU_LOOKUP_W ATOMIC_MMU_LOOKUP_RW #define ATOMIC_MMU_CLEANUP do { clear_helper_retaddr(); } while (0) #define ATOMIC_MMU_IDX MMU_USER_IDX =20 --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162689804114798.44168398998215; Wed, 21 Jul 2021 13:07:21 -0700 (PDT) Received: from localhost ([::1]:42276 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6IUy-0000MI-0S for importer@patchew.org; Wed, 21 Jul 2021 16:07:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36588) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IO4-0002kT-QM for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:12 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:37812) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IO3-0005ik-3J for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:12 -0400 Received: by mail-pl1-x62d.google.com with SMTP id y3so1646956plp.4 for ; Wed, 21 Jul 2021 13:00:10 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lxWc/RvP2HP3ROUQi7CWrSdIRxEa6wVjFG+/s3ElqKw=; b=JFfR/aftAGjAQ0wcUTUf2A3PuXn/DyS1H5IjkntwDDTy4XuaRrgQMpRFE/3rlg284H 7V0lrHNsLb+eAn8pM1T9GcuPq9NKgTejICrPnLZzjgZD9asFj7fhdgNgxfT0We0TX0ut TsZpVnZGlTb/jiVBe7iGlHa/ieSzCNAPT8Z8F80vPgYgtfq/RGwz68mI628PUV/C0W2w gAMIMYanLJHGG3rpiiFHSRuxUS73Lkr6K7pSAWYvvHc164KXoQJiso9o6FqRnFBjhg2e SWLqoH+TUArWnvcG5d0C8hUqkb7HapdeWgPLG8eugI+wzYTaVVUuBTjDV2fccSLLpIq4 I+gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lxWc/RvP2HP3ROUQi7CWrSdIRxEa6wVjFG+/s3ElqKw=; b=A3vfl9XtaNmwBSgJtqTa0xUwMgrHLpSE1oyROW7XBiN6CzYCxvo2HMkLwnIqWsyA+e iEs0evpfn2RWARC0cJvcxbo9T4lqPSr7Vmt0H314fnd06eakw9jh9KwC/hKws4EJJLQQ 4cN6C4vxsP+MpzRNSUzR/buujGYJjAVT6NAL2/x522KD/4PnH3K9aUq3EEPiV6LKhQ54 uFcrdMD2KI03wUclJYJ2c4wqHNdYMq8RXiDvKPFx+mw7X2Xt8yzPO82XAEqGU+Kwb8L7 UWWAo+FUtzfxOE0eWrat5LvZDGqb4a6+CBSW29OFXVRGnS5hC3DrCejHFz7l1qDKkCZ7 zZ0A== X-Gm-Message-State: AOAM533MgSEp7zVWBK1K5haDcmRnWwLy770tZCdNV00Y+N7rVpUvzVPf 0hWJZvB08HcD8BY5y961fCicFgayINtThA== X-Google-Smtp-Source: ABdhPJwcsUYEwglax+iQ/ioK1HsTcYgFTqHmcMqFZHGQxKC4nm0aDRDL1kvzUhJ+5yKnRBfml/SjKQ== X-Received: by 2002:a17:90a:e453:: with SMTP id jp19mr5486083pjb.19.1626897609728; Wed, 21 Jul 2021 13:00:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 09/27] trace: Fold mem-internal.h into mem.h Date: Wed, 21 Jul 2021 09:59:36 -1000 Message-Id: <20210721195954.879535-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Cole Robinson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626898042806100001 Since the last thing that mem.h does is include mem-internal.h, the symbols are not actually private. Tested-by: Cole Robinson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- trace/mem-internal.h | 50 -------------------------------------------- trace/mem.h | 50 ++++++++++++++++++++++++++++++++++---------- plugins/core.c | 2 +- 3 files changed, 40 insertions(+), 62 deletions(-) delete mode 100644 trace/mem-internal.h diff --git a/trace/mem-internal.h b/trace/mem-internal.h deleted file mode 100644 index 8b72b678fa..0000000000 --- a/trace/mem-internal.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Helper functions for guest memory tracing - * - * Copyright (C) 2016 Llu=C3=ADs Vilanova - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - */ - -#ifndef TRACE__MEM_INTERNAL_H -#define TRACE__MEM_INTERNAL_H - -#define TRACE_MEM_SZ_SHIFT_MASK 0xf /* size shift mask */ -#define TRACE_MEM_SE (1ULL << 4) /* sign extended (y/n) */ -#define TRACE_MEM_BE (1ULL << 5) /* big endian (y/n) */ -#define TRACE_MEM_ST (1ULL << 6) /* store (y/n) */ -#define TRACE_MEM_MMU_SHIFT 8 /* mmu idx */ - -static inline uint16_t trace_mem_build_info( - int size_shift, bool sign_extend, MemOp endianness, - bool store, unsigned int mmu_idx) -{ - uint16_t res; - - res =3D size_shift & TRACE_MEM_SZ_SHIFT_MASK; - if (sign_extend) { - res |=3D TRACE_MEM_SE; - } - if (endianness =3D=3D MO_BE) { - res |=3D TRACE_MEM_BE; - } - if (store) { - res |=3D TRACE_MEM_ST; - } -#ifdef CONFIG_SOFTMMU - res |=3D mmu_idx << TRACE_MEM_MMU_SHIFT; -#endif - return res; -} - -static inline uint16_t trace_mem_get_info(MemOp op, - unsigned int mmu_idx, - bool store) -{ - return trace_mem_build_info(op & MO_SIZE, !!(op & MO_SIGN), - op & MO_BSWAP, store, - mmu_idx); -} - -#endif /* TRACE__MEM_INTERNAL_H */ diff --git a/trace/mem.h b/trace/mem.h index 9644f592b4..2f27e7bdf0 100644 --- a/trace/mem.h +++ b/trace/mem.h @@ -12,24 +12,52 @@ =20 #include "tcg/tcg.h" =20 - -/** - * trace_mem_get_info: - * - * Return a value for the 'info' argument in guest memory access traces. - */ -static uint16_t trace_mem_get_info(MemOp op, unsigned int mmu_idx, bool st= ore); +#define TRACE_MEM_SZ_SHIFT_MASK 0xf /* size shift mask */ +#define TRACE_MEM_SE (1ULL << 4) /* sign extended (y/n) */ +#define TRACE_MEM_BE (1ULL << 5) /* big endian (y/n) */ +#define TRACE_MEM_ST (1ULL << 6) /* store (y/n) */ +#define TRACE_MEM_MMU_SHIFT 8 /* mmu idx */ =20 /** * trace_mem_build_info: * * Return a value for the 'info' argument in guest memory access traces. */ -static uint16_t trace_mem_build_info(int size_shift, bool sign_extend, - MemOp endianness, bool store, - unsigned int mmuidx); +static inline uint16_t trace_mem_build_info(int size_shift, bool sign_exte= nd, + MemOp endianness, bool store, + unsigned int mmu_idx) +{ + uint16_t res; + + res =3D size_shift & TRACE_MEM_SZ_SHIFT_MASK; + if (sign_extend) { + res |=3D TRACE_MEM_SE; + } + if (endianness =3D=3D MO_BE) { + res |=3D TRACE_MEM_BE; + } + if (store) { + res |=3D TRACE_MEM_ST; + } +#ifdef CONFIG_SOFTMMU + res |=3D mmu_idx << TRACE_MEM_MMU_SHIFT; +#endif + return res; +} =20 =20 -#include "trace/mem-internal.h" +/** + * trace_mem_get_info: + * + * Return a value for the 'info' argument in guest memory access traces. + */ +static inline uint16_t trace_mem_get_info(MemOp op, + unsigned int mmu_idx, + bool store) +{ + return trace_mem_build_info(op & MO_SIZE, !!(op & MO_SIGN), + op & MO_BSWAP, store, + mmu_idx); +} =20 #endif /* TRACE__MEM_H */ diff --git a/plugins/core.c b/plugins/core.c index e1bcdb570d..474db287cb 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -27,7 +27,7 @@ #include "exec/helper-proto.h" #include "tcg/tcg.h" #include "tcg/tcg-op.h" -#include "trace/mem-internal.h" /* mem_info macros */ +#include "trace/mem.h" /* mem_info macros */ #include "plugin.h" #include "qemu/compiler.h" =20 --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1626898099; cv=none; d=zohomail.com; s=zohoarc; b=Hhbg5SpCL/Dl/vJFmkmskQHBgaGyFFX5iijifdylQF60U9wwkmiWrttJ7dhlUFpG1fPCdfNwIl/6zhbvkXhmcrcyDw7bbfmnjudxXiI0rhOiUY1FqNwFCeto5wgY34O2yVTcc80PhXEhB4G7JGd8iyT6BY1uy+pHfG526r/PZwc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626898099; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2lpkYejps8WW7OyPV4Frr6HZRCmemCrR97xZ2v/S9G4=; b=XLvyz1bmTN2d8aH1GYrWjAyI3vO9T3lO3JSnwztIyKnUtb2aWDjCnZlGq6y3o35UJpdye5AKy8tIi9G1BssWypquhapCtQHOFFiVpgyvo2GwVh7FLqtvVdfJsbRfFr8fpWcVT6Verd63cNIFvokz7QoXKguw8RRP9aI0YplWk5k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626898099641321.5049138128719; Wed, 21 Jul 2021 13:08:19 -0700 (PDT) Received: from localhost ([::1]:45388 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6IVu-0002QM-Hs for importer@patchew.org; Wed, 21 Jul 2021 16:08:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36626) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IO6-0002oX-Jz for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:14 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:38493) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IO4-0005jF-6b for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:14 -0400 Received: by mail-pl1-x62a.google.com with SMTP id u3so1643230plf.5 for ; Wed, 21 Jul 2021 13:00:11 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2lpkYejps8WW7OyPV4Frr6HZRCmemCrR97xZ2v/S9G4=; b=PYxgg2UPZFdy/frwaVRYUo8Yw7x3XZx3QATn2I9nvDCB/41dxFXVPndOId6WJlZm6P vy4w37Pz1E/ycEEL6wwb9pIFoS6L27WQN26pF3AVb5gEA/FAX1+wrVINavlFLL9pSauf YRG9SVTiqL25+kLw2ZZ/qO5FpN7a2KxUBFHX1T66Gz4X58RDEIeNIfZYv5hmfJB9LOK5 YnGYs4tlfskfIL2wHArjVSvMuu+rpFldpmhNQsntVZAXrSGIENBF+mBU+jP2WfpYMPXO VnT1if3UI6OmBwMXOmNs61GktbDvECWldx49W6aY0yQgbrW5HsgwH+Si4jLF/HaH+F+f m4Zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2lpkYejps8WW7OyPV4Frr6HZRCmemCrR97xZ2v/S9G4=; b=TicEQykB+MUn6tLmeFY5eUO0U/VLaETtkanV6y91w5yayuq3ygb13iDYOgeM37QtOl AAWR3g1gCto2sRuESS7Plfr72/JDcvEhk6AybyiP6Iria/iLMr5ZFGEXo/CJHiHVmHMp 0L9X8AwEyBFy5HTwMsKNUtk8GfHxqVGLCseI1/jUxP852Pw99Qnbrs1bIMEC+qXlfJQ3 o1U2/lgFz3JFEvU6mXH56ssAuht7Iqxk06JDfHrBA2FxPPCozGepOsjfdIf63fpZzxy8 fuagUtYhP9o994ngpfStJ9lfNO5DtcQOKMXnPhsbSH/Q/JfUw3VzrSGYXvYDslyooS6q y0Pw== X-Gm-Message-State: AOAM533G8VPXC4Zx3c2bOUVdVEWgzBnfQ0n9nGl1vyy6rx2+ld/pjOhP cVopEDlK4NoIRa2GPfELa+HaIx9BfYonqw== X-Google-Smtp-Source: ABdhPJz7CTeZHp1zGKvDc0ZbueLd2pDvmA1IPE7NmJHTqr1WiImyFaOtJsv0eGuJzYyGFuAXNagGag== X-Received: by 2002:a63:1551:: with SMTP id 17mr27908982pgv.76.1626897610954; Wed, 21 Jul 2021 13:00:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 10/27] accel/tcg: Push trace info building into atomic_common.c.inc Date: Wed, 21 Jul 2021 09:59:37 -1000 Message-Id: <20210721195954.879535-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Cole Robinson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1626898100508100001 Content-Type: text/plain; charset="utf-8" Use trace_mem_get_info instead of trace_mem_build_info, using the TCGMemOpIdx that we already have. Do this in the atomic_trace_*_pre function as common subroutines. Tested-by: Cole Robinson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- accel/tcg/atomic_template.h | 48 +++++++++-------------------------- accel/tcg/atomic_common.c.inc | 37 ++++++++++++++++++--------- 2 files changed, 37 insertions(+), 48 deletions(-) diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index 6ee0158c5f..d89af4cc1e 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -77,10 +77,8 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_= ulong addr, DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ | PAGE_WRITE, retaddr); DATA_TYPE ret; - uint16_t info =3D trace_mem_build_info(SHIFT, false, 0, false, - ATOMIC_MMU_IDX); + uint16_t info =3D atomic_trace_rmw_pre(env, addr, oi); =20 - atomic_trace_rmw_pre(env, addr, info); #if DATA_SIZE =3D=3D 16 ret =3D atomic16_cmpxchg(haddr, cmpv, newv); #else @@ -99,10 +97,8 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulong= addr, DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ, retaddr); DATA_TYPE val; - uint16_t info =3D trace_mem_build_info(SHIFT, false, 0, false, - ATOMIC_MMU_IDX); + uint16_t info =3D atomic_trace_ld_pre(env, addr, oi); =20 - atomic_trace_ld_pre(env, addr, info); val =3D atomic16_read(haddr); ATOMIC_MMU_CLEANUP; atomic_trace_ld_post(env, addr, info); @@ -114,10 +110,8 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong a= ddr, ABI_TYPE val, { DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_WRITE, retaddr); - uint16_t info =3D trace_mem_build_info(SHIFT, false, 0, true, - ATOMIC_MMU_IDX); + uint16_t info =3D atomic_trace_st_pre(env, addr, oi); =20 - atomic_trace_st_pre(env, addr, info); atomic16_set(haddr, val); ATOMIC_MMU_CLEANUP; atomic_trace_st_post(env, addr, info); @@ -130,10 +124,8 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_u= long addr, ABI_TYPE val, DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ | PAGE_WRITE, retaddr); DATA_TYPE ret; - uint16_t info =3D trace_mem_build_info(SHIFT, false, 0, false, - ATOMIC_MMU_IDX); + uint16_t info =3D atomic_trace_rmw_pre(env, addr, oi); =20 - atomic_trace_rmw_pre(env, addr, info); ret =3D qatomic_xchg__nocheck(haddr, val); ATOMIC_MMU_CLEANUP; atomic_trace_rmw_post(env, addr, info); @@ -147,9 +139,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong= addr, \ DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ PAGE_READ | PAGE_WRITE, retaddr);= \ DATA_TYPE ret; \ - uint16_t info =3D trace_mem_build_info(SHIFT, false, 0, false, \ - ATOMIC_MMU_IDX); \ - atomic_trace_rmw_pre(env, addr, info); \ + uint16_t info =3D atomic_trace_rmw_pre(env, addr, oi); \ ret =3D qatomic_##X(haddr, val); \ ATOMIC_MMU_CLEANUP; \ atomic_trace_rmw_post(env, addr, info); \ @@ -182,9 +172,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong= addr, \ XDATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ PAGE_READ | PAGE_WRITE, retaddr)= ; \ XDATA_TYPE cmp, old, new, val =3D xval; \ - uint16_t info =3D trace_mem_build_info(SHIFT, false, 0, false, \ - ATOMIC_MMU_IDX); \ - atomic_trace_rmw_pre(env, addr, info); \ + uint16_t info =3D atomic_trace_rmw_pre(env, addr, oi); \ smp_mb(); \ cmp =3D qatomic_read__nocheck(haddr); \ do { \ @@ -228,10 +216,8 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, targe= t_ulong addr, DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ | PAGE_WRITE, retaddr); DATA_TYPE ret; - uint16_t info =3D trace_mem_build_info(SHIFT, false, MO_BSWAP, false, - ATOMIC_MMU_IDX); + uint16_t info =3D atomic_trace_rmw_pre(env, addr, oi); =20 - atomic_trace_rmw_pre(env, addr, info); #if DATA_SIZE =3D=3D 16 ret =3D atomic16_cmpxchg(haddr, BSWAP(cmpv), BSWAP(newv)); #else @@ -250,10 +236,8 @@ ABI_TYPE ATOMIC_NAME(ld)(CPUArchState *env, target_ulo= ng addr, DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ, retaddr); DATA_TYPE val; - uint16_t info =3D trace_mem_build_info(SHIFT, false, MO_BSWAP, false, - ATOMIC_MMU_IDX); + uint16_t info =3D atomic_trace_ld_pre(env, addr, oi); =20 - atomic_trace_ld_pre(env, addr, info); val =3D atomic16_read(haddr); ATOMIC_MMU_CLEANUP; atomic_trace_ld_post(env, addr, info); @@ -265,11 +249,9 @@ void ATOMIC_NAME(st)(CPUArchState *env, target_ulong a= ddr, ABI_TYPE val, { DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_WRITE, retaddr); - uint16_t info =3D trace_mem_build_info(SHIFT, false, MO_BSWAP, true, - ATOMIC_MMU_IDX); + uint16_t info =3D atomic_trace_st_pre(env, addr, oi); =20 val =3D BSWAP(val); - atomic_trace_st_pre(env, addr, info); val =3D BSWAP(val); atomic16_set(haddr, val); ATOMIC_MMU_CLEANUP; @@ -283,10 +265,8 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_u= long addr, ABI_TYPE val, DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, PAGE_READ | PAGE_WRITE, retaddr); ABI_TYPE ret; - uint16_t info =3D trace_mem_build_info(SHIFT, false, MO_BSWAP, false, - ATOMIC_MMU_IDX); + uint16_t info =3D atomic_trace_rmw_pre(env, addr, oi); =20 - atomic_trace_rmw_pre(env, addr, info); ret =3D qatomic_xchg__nocheck(haddr, BSWAP(val)); ATOMIC_MMU_CLEANUP; atomic_trace_rmw_post(env, addr, info); @@ -300,9 +280,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong= addr, \ DATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ PAGE_READ | PAGE_WRITE, retaddr);= \ DATA_TYPE ret; \ - uint16_t info =3D trace_mem_build_info(SHIFT, false, MO_BSWAP, \ - false, ATOMIC_MMU_IDX); \ - atomic_trace_rmw_pre(env, addr, info); \ + uint16_t info =3D atomic_trace_rmw_pre(env, addr, oi); \ ret =3D qatomic_##X(haddr, BSWAP(val)); \ ATOMIC_MMU_CLEANUP; \ atomic_trace_rmw_post(env, addr, info); \ @@ -332,9 +310,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong= addr, \ XDATA_TYPE *haddr =3D atomic_mmu_lookup(env, addr, oi, DATA_SIZE, \ PAGE_READ | PAGE_WRITE, retaddr)= ; \ XDATA_TYPE ldo, ldn, old, new, val =3D xval; \ - uint16_t info =3D trace_mem_build_info(SHIFT, false, MO_BSWAP, \ - false, ATOMIC_MMU_IDX); \ - atomic_trace_rmw_pre(env, addr, info); \ + uint16_t info =3D atomic_trace_rmw_pre(env, addr, oi); \ smp_mb(); \ ldn =3D qatomic_read__nocheck(haddr); \ do { \ diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc index a668cf0d6f..6c0339f610 100644 --- a/accel/tcg/atomic_common.c.inc +++ b/accel/tcg/atomic_common.c.inc @@ -13,45 +13,58 @@ * See the COPYING file in the top-level directory. */ =20 -static inline -void atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr, uint16_t i= nfo) +static uint16_t atomic_trace_rmw_pre(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi) { CPUState *cpu =3D env_cpu(env); + uint16_t info =3D trace_mem_get_info(get_memop(oi), get_mmuidx(oi), fa= lse); =20 trace_guest_mem_before_exec(cpu, addr, info); trace_guest_mem_before_exec(cpu, addr, info | TRACE_MEM_ST); + + return info; } =20 -static inline void -atomic_trace_rmw_post(CPUArchState *env, target_ulong addr, uint16_t info) +static void atomic_trace_rmw_post(CPUArchState *env, target_ulong addr, + uint16_t info) { qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info); qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info | TRACE_MEM_ST); } =20 -static inline -void atomic_trace_ld_pre(CPUArchState *env, target_ulong addr, uint16_t in= fo) +#if HAVE_ATOMIC128 +static uint16_t atomic_trace_ld_pre(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi) { + uint16_t info =3D trace_mem_get_info(get_memop(oi), get_mmuidx(oi), fa= lse); + trace_guest_mem_before_exec(env_cpu(env), addr, info); + + return info; } =20 -static inline -void atomic_trace_ld_post(CPUArchState *env, target_ulong addr, uint16_t i= nfo) +static void atomic_trace_ld_post(CPUArchState *env, target_ulong addr, + uint16_t info) { qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info); } =20 -static inline -void atomic_trace_st_pre(CPUArchState *env, target_ulong addr, uint16_t in= fo) +static uint16_t atomic_trace_st_pre(CPUArchState *env, target_ulong addr, + TCGMemOpIdx oi) { + uint16_t info =3D trace_mem_get_info(get_memop(oi), get_mmuidx(oi), tr= ue); + trace_guest_mem_before_exec(env_cpu(env), addr, info); + + return info; } =20 -static inline -void atomic_trace_st_post(CPUArchState *env, target_ulong addr, uint16_t i= nfo) +static void atomic_trace_st_post(CPUArchState *env, target_ulong addr, + uint16_t info) { qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, info); } +#endif =20 /* * Atomic helpers callable from TCG. --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626898247682104.41778443769999; Wed, 21 Jul 2021 13:10:47 -0700 (PDT) Received: from localhost ([::1]:50778 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6IYI-00061m-H2 for importer@patchew.org; Wed, 21 Jul 2021 16:10:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36638) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IO7-0002pR-Ow for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:15 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:40840) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IO5-0005kH-Iv for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:15 -0400 Received: by mail-pl1-x629.google.com with SMTP id q13so720489plx.7 for ; Wed, 21 Jul 2021 13:00:13 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fPhqaj8tr3Rp4GKzrSeMc4wSTZdCBtqiRU4Qe7xA0xQ=; b=GsWCS5Ey8oX6PwrtDW7FeE57J9sPyPO9921ADoP2TNjJ5Y8VkRWeW52TvdAqm5/hwx XusKeF0BvK0FPmyUIluTgGWReoJ7YyYZYSrKDY7afdkGlH9NTleamX87v1aczuJXD5a1 dc+IxnwhESTpCF8podZe7OYQl/ursUeJIY/muq2orJm5wHNTBPejONKhYzcCXUMDvBsK 33Vty/HPgOmzlF3O4C6COuqm1PDEHkhz2zxotlFuGknufk4kVpmaHWkyxwnWFsnXaIjB bp/tNVDLJD0P19sGlKhXJZJDxGjDxEyFYChN1BSf7EysIc99iZ6PX3RgV0hAPcC4Z06b EIVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fPhqaj8tr3Rp4GKzrSeMc4wSTZdCBtqiRU4Qe7xA0xQ=; b=QcTqamNU0cQYtpGRWE4Nzvk7S76THEnbpouOQNgbkzSgjAQDpbOTMp+V2JetvX09XE 3RfXifC3eRAZjAOt8QSiRkb21nC/zKF42MWOrnvQrc2nu2Rttf7nhAOIwk1FRZkSJDJF vFP8SlnszpmrqLNVBD8GXpTUHyYDLyHRyDqquw1vtQRHxpFSdht/IFmeKlc65CJkkuIR IPPp/tm6JIX2G8BrnVXumcA/Fb62LvGFLMQTuDVtv/w6RL4CfOjASTbzSU1V5WOiXepw 3OOMe3fZgDPUaIkuI3icsOojm9KN2nqAzypc1givBCxYessmQhhpPzrO0JGCvZb7Gc9Y zYlw== X-Gm-Message-State: AOAM533CjE6fj8WmQJYhvDIL9qXHOeooCHoZKSJ2ktbdoBbCvqSKuoU2 LuqFcTTLBheLl2nTn2VnsdTEMqtYuq0k0g== X-Google-Smtp-Source: ABdhPJx37j0Fts8kp8zpRk/wmbrsFp2KdLDCsfpVDhUz65TSaB5HboS72qQ/wR+rUltvSDJI8qDXlQ== X-Received: by 2002:a62:36c5:0:b029:32b:83fa:3a3e with SMTP id d188-20020a6236c50000b029032b83fa3a3emr38553781pfa.52.1626897612273; Wed, 21 Jul 2021 13:00:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 11/27] accel/tcg: Reduce CF_COUNT_MASK to match TCG_MAX_INSNS Date: Wed, 21 Jul 2021 09:59:38 -1000 Message-Id: <20210721195954.879535-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , peter.maydell@linaro.org, Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626898249971100002 The space reserved for CF_COUNT_MASK was overly large. Reduce to free up cflags bits and eliminate an extra test. Tested-by: Mark Cave-Ayland Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Message-Id: <20210717221851.2124573-2-richard.henderson@linaro.org> --- include/exec/exec-all.h | 4 +++- accel/tcg/translate-all.c | 5 ++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 754f4130c9..dfe82ed19c 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -492,7 +492,9 @@ struct TranslationBlock { target_ulong cs_base; /* CS base for this block */ uint32_t flags; /* flags defining in which context the code was genera= ted */ uint32_t cflags; /* compile flags */ -#define CF_COUNT_MASK 0x00007fff + +/* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */ +#define CF_COUNT_MASK 0x000001ff #define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ #define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ #define CF_USE_ICOUNT 0x00020000 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 4df26de858..5cc01d693b 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1428,11 +1428,10 @@ TranslationBlock *tb_gen_code(CPUState *cpu, =20 max_insns =3D cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { max_insns =3D TCG_MAX_INSNS; } + QEMU_BUILD_BUG_ON(CF_COUNT_MASK + 1 !=3D TCG_MAX_INSNS); + if (cpu->singlestep_enabled || singlestep) { max_insns =3D 1; } --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626898420293936.3050242069347; Wed, 21 Jul 2021 13:13:40 -0700 (PDT) Received: from localhost ([::1]:59008 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6Ib5-0003GA-6y for importer@patchew.org; Wed, 21 Jul 2021 16:13:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36648) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IO8-0002rB-KF for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:16 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:41977) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IO6-0005lR-TE for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:16 -0400 Received: by mail-pj1-x1029.google.com with SMTP id jx7-20020a17090b46c7b02901757deaf2c8so1965379pjb.0 for ; Wed, 21 Jul 2021 13:00:14 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ehY8U09jBm9UvNr8BfCejix3nlnXxTqyEmybvBBu+AM=; b=dqqQrwrNBYZEdU1t/HtQLpyePhi2gq0lKHjw/cV9aTWfDckCmpSM1erCzDK6hYLQoG IK/eqMGNayfVzBRzqRLP5zz1z3M3svIv0GNpS8uRt0sN83okO5VeYcLpi+FQ2JYksxR4 DeaAsvI5sSN4FSk2zVtvNBd6om2R09doXv2h/N90L5A76fxR26K2rB9zSlXqmp8Azd85 J6hGzB59DJ+Ue4QwWJ6TvYjet2d9C7bqpW1pzBUdQ9Lq0mJ3KMbsaIf0lISx7ixQplag lKrJqykpN2CcM5OHCZhYNPCybmOBI43MHiII1MbQLa+M2Fr7bJAORaUR1hs0dj52WIht xNHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ehY8U09jBm9UvNr8BfCejix3nlnXxTqyEmybvBBu+AM=; b=GyIk3lLkiC8t2oQR8oiKCITK+kXCc6A1Rv8V5o/xif7njKkJLnB6ylJ9S8QP6/o6z7 LEP98eRAjucXtnj5hw9jx6V5qyWBX2PmY6JnBZhFg4RHPoPsXRxjYdSKL7gvIKvG/xUn cDdZhg3vx6Y5rmADR7+o6PlyenrQtMX36RVAqglFBR3WoxSQ0aXdsyCns6ODXsu6C6Ps N1ens7L73Z+GaDphBRVQ8hqERI9lBIn+JGp+/4bfY0/hjA1NLMpQVsqxPFqw9EFvPHpK yLsVD5yKV9ygp20vkNFNHZuwpdiAeFCLQZ3NQRC1jBB6VcVPLO7xPjGZS7K5pbr18hCh +Hqg== X-Gm-Message-State: AOAM531kED9h2JWXuYSTj9I9QHolrsxXNQ4XU56h//awALqb2KQ82rpl KgxGCUavynCH7duin9eXPKWYrWcoPlJvDw== X-Google-Smtp-Source: ABdhPJyI+cEb5fn1FCvVra4j9CzJ3uVSexEWtOGkkj52b9HIBiuov6P4Ls6S295IL7tykRZJIhE+PA== X-Received: by 2002:a65:5c01:: with SMTP id u1mr37993214pgr.181.1626897613723; Wed, 21 Jul 2021 13:00:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 12/27] accel/tcg: Move curr_cflags into cpu-exec.c Date: Wed, 21 Jul 2021 09:59:39 -1000 Message-Id: <20210721195954.879535-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , peter.maydell@linaro.org, Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626898422203100003 We will shortly have more than a simple member read here, with stuff not necessarily exposed to exec/exec-all.h. Tested-by: Mark Cave-Ayland Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210717221851.2124573-3-richard.henderson@linaro.org> --- include/exec/exec-all.h | 5 +---- accel/tcg/cpu-exec.c | 5 +++++ 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index dfe82ed19c..ae7603ca75 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -565,10 +565,7 @@ static inline uint32_t tb_cflags(const TranslationBloc= k *tb) } =20 /* current cflags for hashing/comparison */ -static inline uint32_t curr_cflags(CPUState *cpu) -{ - return cpu->tcg_cflags; -} +uint32_t curr_cflags(CPUState *cpu); =20 /* TranslationBlock invalidate API */ #if defined(CONFIG_USER_ONLY) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index e22bcb99f7..ef4214d893 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -145,6 +145,11 @@ static void init_delay_params(SyncClocks *sc, const CP= UState *cpu) } #endif /* CONFIG USER ONLY */ =20 +uint32_t curr_cflags(CPUState *cpu) +{ + return cpu->tcg_cflags; +} + /* Might cause an exception, so have a longjmp destination ready */ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc, target_ulong cs_base, --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1626898304; cv=none; d=zohomail.com; s=zohoarc; b=Y+Y664BKR7vAhCpnAOBumgcn/qQegPBBi3dyqedY5rv7aJvRIa2XO1jT+pW9zHHIRTfTaDm4W2Ty2EsXJ3mAspnoyZD/dM+FaOChubCpmlKB+TwwgT+trI3NvQAE6lH6wUlcrhIPc6yELSQmOUcblguyB4hJeJpm/1sgyQTgzWE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626898304; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5munM6eZd/uk4n4hD7SHb+ixOouAZHeY9ReXlmZhFgI=; b=LnYSGfpJMO0ve5GmG46Q227rQIskpyW5y2J4D3c6xqkTJKpN3hqMZwo7tQNsTW5wKngeh0ddJu9j+Y5e+cWjezURqAgAPPUhRtXPu0J65U7mdzChscnBeo5D60begqf7CpWGIWzzUIpOKADQXtWPBuWPRVoZNNhs0TUebjauZHU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626898304227359.03541681969887; Wed, 21 Jul 2021 13:11:44 -0700 (PDT) Received: from localhost ([::1]:53820 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6IZD-00086F-5y for importer@patchew.org; Wed, 21 Jul 2021 16:11:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36660) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IOA-0002sn-5M for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:18 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:43523) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IO8-0005mC-CC for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:17 -0400 Received: by mail-pl1-x62e.google.com with SMTP id b12so1631148plh.10 for ; Wed, 21 Jul 2021 13:00:15 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5munM6eZd/uk4n4hD7SHb+ixOouAZHeY9ReXlmZhFgI=; b=viTLpVQEsZL+8QAxFbaPI6rVcRXgOVtwgaOYJDgajeXL453XnRJRNAKo2v3TynVoBH uAXZQiiUcrosc5Yht8YK8ThnOnaqfk5FjQPp4Ok7qjia+TkSDr7pKhHJCYUjxVLXWOe7 /gu4J8JQP6SxbEJAOLDO/UwNBdKCwy+XKclLniQ36P/zlYmd7j27c3ENcF7A7HzrVDag IXJk+iNe1bK/5MKJGdwV60XJtxnMV+XIzm8xfKKi0ib2CSiX5TPWsPEub6m+cOXAdumz daawhG3uTBJMghfBE3+l3VPWS2GIrwel3zgBYhMvxL7x0vx8PdyjRXhNgLh4byB3YtVM O50A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5munM6eZd/uk4n4hD7SHb+ixOouAZHeY9ReXlmZhFgI=; b=PkktjTtMjMv06iknfrs7udRTja1vD21JhGQrJtIyuGKBwkIWn7cwMQsg+KsyjnFTD7 epUCze8JGHGv0c4k3RDiK203awSOfzNhgkrFt47KYxxyn/MZUsqCyjRaKxudvv84aONQ t9X5rK4F6NWatWZxVP9l8VbgpK6oXLCE8G6A7bybXP0mmUqEEE5a2GOz6QG1QRmoUjvl rkxj1hzyTpQnSHp1Ab68pWtw/ncNs/HiF2aaHjE+HVsWl9GZEt1yyHFSkKoXoOpObNDs WtRdHK6hVmhmCOqTRqG+eQrg8oXfpKdxnacWNIQOgefN2t7NmYL+fOz43J58ieianqid IAnw== X-Gm-Message-State: AOAM530Z11AqU3oeQdf+3GPwoUYHDd7pRKnTb3uROZNxBSWcUGJKHWZG ufkXojT5Up+17binq0ItPbUdBFztxT6gnw== X-Google-Smtp-Source: ABdhPJxvN3Iq6b/nAdD5bMIBqG92ImXpF00oV5dl3uF9edSAP7rtA36mmcnELDCN8mVuOBXOfDxFTg== X-Received: by 2002:a63:9d46:: with SMTP id i67mr37992809pgd.225.1626897615033; Wed, 21 Jul 2021 13:00:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 13/27] target/alpha: Drop goto_tb path in gen_call_pal Date: Wed, 21 Jul 2021 09:59:40 -1000 Message-Id: <20210721195954.879535-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1626898306036100001 We are certain of a page crossing here, entering the PALcode image, so the call to use_goto_tb that should have been here will never succeed. We are shortly going to add an assert to tcg_gen_goto_tb that would trigger for this case. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/alpha/translate.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 103c6326a2..949ba6ffde 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -1207,19 +1207,8 @@ static DisasJumpType gen_call_pal(DisasContext *ctx,= int palcode) ? 0x2000 + (palcode - 0x80) * 64 : 0x1000 + palcode * 64); =20 - /* Since the destination is running in PALmode, we don't really - need the page permissions check. We'll see the existence of - the page when we create the TB, and we'll flush all TBs if - we change the PAL base register. */ - if (!ctx->base.singlestep_enabled) { - tcg_gen_goto_tb(0); - tcg_gen_movi_i64(cpu_pc, entry); - tcg_gen_exit_tb(ctx->base.tb, 0); - return DISAS_NORETURN; - } else { - tcg_gen_movi_i64(cpu_pc, entry); - return DISAS_PC_UPDATED; - } + tcg_gen_movi_i64(cpu_pc, entry); + return DISAS_PC_UPDATED; } #endif } --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626898647976737.513320409731; Wed, 21 Jul 2021 13:17:27 -0700 (PDT) Received: from localhost ([::1]:38886 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6Iek-0000R8-B7 for importer@patchew.org; Wed, 21 Jul 2021 16:17:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36708) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IOF-0002uX-Vw for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:24 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:40845) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IO9-0005nd-Uv for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:22 -0400 Received: by mail-pl1-x62e.google.com with SMTP id q13so720759plx.7 for ; Wed, 21 Jul 2021 13:00:17 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qpFwoKbq+TluVfp0et24W5UD/m+YrCl4U/myz3fWvpI=; b=mYqVBJrwBAbnZk0USsdPBlGRHPBJeKe2+OYpaZzN2zLQUUvRWklhpYwfhcS4OdWJqS oe+hfU9JTpUSSDnvjrQOa8RV2NLRvjNB09ey9couUpICgbx2v/zOSdOFQb7OMMYUDXlo rvkx+qvDvDQZ6ux7Va29kFvn10x6Daq6MXwqY33F3w5FhobnDhOStwIf5IxKJC2PS69q HQiJZ8d4jVECAwvwx28QdSNNjDGIJT3TpQBdWOafMBc9v7EVA05It7kAUBGzKvGUe+qG nCke4QdRUiL24SZkgq5vBYcdFs3OyWue5TzQPC7Yjhc3wc435ul4ExpmoxuMIvvh24Vf SJdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qpFwoKbq+TluVfp0et24W5UD/m+YrCl4U/myz3fWvpI=; b=SKzXyuZJVXqrBbKY8tg/rde9BfCKBbt6YNbSyiX/Mi55VwiUoFiODDBlbsXzWN037i WCw2ES81EAlZseqOr4M/vyA+k5hQJVE+vxvqqVv6JvA/fB0XY+Zx4bK5dKLSOLGPLTpH sj8mAXDKK8VwNh2Mzg8Ix4Vau48d2NLVoYR/2LRhILoVMjTJ8+wy5fyjOlR0XR+AHJT/ kRHGUnmypRh1GpNrlLPl7BYxy7FvOgT1BMJb1aSxebcrNUsWzTJNePSQcfpnEKR1GORR 4BAE8KNEGp18qlwHZyPfSrAWrJMbYihlerK3Eq5R9xFxh6qfjm4xvaP7aHRhPj38P6KO mRJQ== X-Gm-Message-State: AOAM531n4zDdCsLsZD580SavOD0twIAsECZZ8bmgjrrvhGB93UvnZMcH V1czKdX4S1JBysnmLkcKkzlMxmYCYmEWyw== X-Google-Smtp-Source: ABdhPJzXhF0SxNwff+/1BmaAfaZyZbD9aBKlMViCOUO1FL1oyN9g5GBXwSMGX+VlbqKy9/OL8ouLwg== X-Received: by 2002:a65:62da:: with SMTP id m26mr37518325pgv.370.1626897616412; Wed, 21 Jul 2021 13:00:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 14/27] accel/tcg: Add CF_NO_GOTO_TB and CF_NO_GOTO_PTR Date: Wed, 21 Jul 2021 09:59:41 -1000 Message-Id: <20210721195954.879535-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , peter.maydell@linaro.org, Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626898649308100001 Move the -d nochain check to bits on tb->cflags. These will be used for more than -d nochain shortly. Set bits during curr_cflags, test them in translator_use_goto_tb, assert we're not doing anything odd in tcg_gen_goto_tb. The test in tcg_gen_exit_tb is redundant with the assert for goto_tb_issue_mask. Tested-by: Mark Cave-Ayland Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Message-Id: <20210717221851.2124573-4-richard.henderson@linaro.org> --- include/exec/exec-all.h | 16 +++++++++------- accel/tcg/cpu-exec.c | 8 +++++++- accel/tcg/translator.c | 5 +++++ tcg/tcg-op.c | 28 ++++++++++++---------------- 4 files changed, 33 insertions(+), 24 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index ae7603ca75..6873cce8df 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -494,13 +494,15 @@ struct TranslationBlock { uint32_t cflags; /* compile flags */ =20 /* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */ -#define CF_COUNT_MASK 0x000001ff -#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ -#define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ -#define CF_USE_ICOUNT 0x00020000 -#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held = */ -#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context = */ -#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ +#define CF_COUNT_MASK 0x000001ff +#define CF_NO_GOTO_TB 0x00000200 /* Do not chain with goto_tb */ +#define CF_NO_GOTO_PTR 0x00000400 /* Do not chain with goto_ptr */ +#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ +#define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ +#define CF_USE_ICOUNT 0x00020000 +#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock hel= d */ +#define CF_PARALLEL 0x00080000 /* Generate code for a parallel contex= t */ +#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ #define CF_CLUSTER_SHIFT 24 =20 /* Per-vCPU dynamic tracing state used to generate this TB */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ef4214d893..d3232d5764 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -147,7 +147,13 @@ static void init_delay_params(SyncClocks *sc, const CP= UState *cpu) =20 uint32_t curr_cflags(CPUState *cpu) { - return cpu->tcg_cflags; + uint32_t cflags =3D cpu->tcg_cflags; + + if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { + cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR; + } + + return cflags; } =20 /* Might cause an exception, so have a longjmp destination ready */ diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 59804af37b..2ea5a74f30 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -33,6 +33,11 @@ void translator_loop_temp_check(DisasContextBase *db) =20 bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest) { + /* Suppress goto_tb if requested. */ + if (tb_cflags(db->tb) & CF_NO_GOTO_TB) { + return false; + } + /* Suppress goto_tb in the case of single-steping. */ if (db->singlestep_enabled || singlestep) { return false; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 75eaa910c9..c754396575 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2723,10 +2723,6 @@ void tcg_gen_exit_tb(const TranslationBlock *tb, uns= igned idx) seen this numbered exit before, via tcg_gen_goto_tb. */ tcg_debug_assert(tcg_ctx->goto_tb_issue_mask & (1 << idx)); #endif - /* When not chaining, exit without indicating a link. */ - if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - val =3D 0; - } } else { /* This is an exit via the exitreq label. */ tcg_debug_assert(idx =3D=3D TB_EXIT_REQUESTED); @@ -2738,6 +2734,8 @@ void tcg_gen_exit_tb(const TranslationBlock *tb, unsi= gned idx) =20 void tcg_gen_goto_tb(unsigned idx) { + /* We tested CF_NO_GOTO_TB in translator_use_goto_tb. */ + tcg_debug_assert(!(tcg_ctx->tb_cflags & CF_NO_GOTO_TB)); /* We only support two chained exits. */ tcg_debug_assert(idx <=3D TB_EXIT_IDXMAX); #ifdef CONFIG_DEBUG_TCG @@ -2746,25 +2744,23 @@ void tcg_gen_goto_tb(unsigned idx) tcg_ctx->goto_tb_issue_mask |=3D 1 << idx; #endif plugin_gen_disable_mem_helpers(); - /* When not chaining, we simply fall through to the "fallback" exit. = */ - if (!qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - tcg_gen_op1i(INDEX_op_goto_tb, idx); - } + tcg_gen_op1i(INDEX_op_goto_tb, idx); } =20 void tcg_gen_lookup_and_goto_ptr(void) { - if (!qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - TCGv_ptr ptr; + TCGv_ptr ptr; =20 - plugin_gen_disable_mem_helpers(); - ptr =3D tcg_temp_new_ptr(); - gen_helper_lookup_tb_ptr(ptr, cpu_env); - tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr)); - tcg_temp_free_ptr(ptr); - } else { + if (tcg_ctx->tb_cflags & CF_NO_GOTO_PTR) { tcg_gen_exit_tb(NULL, 0); + return; } + + plugin_gen_disable_mem_helpers(); + ptr =3D tcg_temp_new_ptr(); + gen_helper_lookup_tb_ptr(ptr, cpu_env); + tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr)); + tcg_temp_free_ptr(ptr); } =20 static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st) --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1626898248; cv=none; d=zohomail.com; s=zohoarc; b=Z/7z2BL+1yNqmppgdXVXZE7hY1ww2/SRjkzqYShClmIj/SzVG7oqQd7v+lkWg1oMn/PaRpmAYmpuV6XNJVSvf1Ho4EWv4BbabBeRX5UHA+bhaX6h2GLABwH1T98DUb7DQU0XV94xkn30ODs+tp58lbwcx+oB5bUsIxiztWFnHtQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626898248; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AQ5Q3JNtN/mbypwUzDSRUQzn9dP3F0xe81U/358f3Jc=; b=Ee7Ki/QfApFRe2IEBKSsohe7obxf18pCYW65ePbVuNAXtRlCYfuveQv2jGNyjoYqJ/Ks5C/KZBPPQF7XpNXfTUK2UK+jvmMCZn+n2HyqTSKNEr0NXKyKnKfzPfQ6682aH8wtt4iN2cMPWfaFuLdjBv1p8oEEk0I1z1wwGkfBJ9A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626898248421126.88222813280083; Wed, 21 Jul 2021 13:10:48 -0700 (PDT) Received: from localhost ([::1]:50762 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6IYJ-00061H-7g for importer@patchew.org; Wed, 21 Jul 2021 16:10:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36742) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IOH-0002xl-Qz for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:29 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:53979) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IOC-0005o5-If for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:23 -0400 Received: by mail-pj1-x1035.google.com with SMTP id p9so2551378pjl.3 for ; Wed, 21 Jul 2021 13:00:18 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AQ5Q3JNtN/mbypwUzDSRUQzn9dP3F0xe81U/358f3Jc=; b=ZieUyDGcXrZ/ZD+pERJLO5zrBPrviZeSrak3MiFPWIlqHLHFlBBjHMtARtGBvIXViF INwA5NUo+zllvsjdBEc7uQNYwUcLDLIwugdNz9VfMSpyVE2Z1dPggURlo5GTkL+jP7iu vNmeQYm8fud1QX4VlVTqecw4a/6beMTuj9iftFzpP5MCKsfV9zztJSVQr5QKlU55YUtM Vn9RanVWNNTafEdmMGk3A7ElDZCpHuQ/WB8wYdg6uqvJfj5bINWpbGv3Ko8woWxmMV9t D8dh6k2VNcwdt8ClRzUHaym3RFlQGldn83kPxsSzeM1f6KVGCxQPc56EfDsA9bw+KBxS NECw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AQ5Q3JNtN/mbypwUzDSRUQzn9dP3F0xe81U/358f3Jc=; b=c03VOo4IjcprYBdgESBlYv1krcFrEQGqQgF2zwEe6SRe5lNPbaPtTmjTeq7p9uaRRq nFZfS7J2w/qyDPufO2UCOWXMunzlRFHTABPAvdGSM2ymsfl3GH426IGK2D10QvZX3v8a iMoB86GcOBUadw0FUDDORuYXSt4bkT0O7ZhAnGh+SKasDBYqSl9j+gwYS4PKy39n6kRu 0rDf37zm0guT3UoMXB2MP7atjgsQvO0knctfv5k2TNnh6bo/nz7NkSFmMv98nvllgU3y 0HsO+YKAZuu/eQGyKBCjymv6Un7Al56PPKdFLqbFsaCYTv7G6+Krpkr0rxAYXDva4D+H Z+sg== X-Gm-Message-State: AOAM533GeAP/nlOyAEV+bEAXTLvscOGbZG5B3CsSjT02OmzfYeu7owHq OZR57hIKwFzUypeGQ7ABJSCnErpFSfmRQQ== X-Google-Smtp-Source: ABdhPJynmWfmLWZTy2Vqs2PnxKcQSE0s3hGNQydV0tvwkSrooYS2JbygL1yDQCSlGspHJ+wIKobi7g== X-Received: by 2002:a63:fe51:: with SMTP id x17mr37341434pgj.58.1626897617759; Wed, 21 Jul 2021 13:00:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 15/27] accel/tcg: Drop CF_NO_GOTO_PTR from -d nochain Date: Wed, 21 Jul 2021 09:59:42 -1000 Message-Id: <20210721195954.879535-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1626898249966100001 Content-Type: text/plain; charset="utf-8" The purpose of suppressing goto_ptr from -d nochain had been to return to the main loop so that -d cpu would be recognized. But we now include -d cpu logging in helper_lookup_tb_ptr so there is no need to exclude goto_ptr. Tested-by: Mark Cave-Ayland Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20210717221851.2124573-5-richard.henderson@linaro.org> --- accel/tcg/cpu-exec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index d3232d5764..70ea3c7d68 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -150,7 +150,7 @@ uint32_t curr_cflags(CPUState *cpu) uint32_t cflags =3D cpu->tcg_cflags; =20 if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR; + cflags |=3D CF_NO_GOTO_TB; } =20 return cflags; --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1626898799; cv=none; d=zohomail.com; s=zohoarc; b=bYuvjYvhBWe/0we9aE22XnjsO0z9Ttw0bQPB2/RMbxDuQtgNOxFiJRjbkubNVz5LLTBTU9whx1FBCmMKhQmAaheumDrsCjFDBJ0vI/NvZC2kxJ8oV/uxTdeHktoL2j/sV5lYxjop6bvHokVfy8F/SXMUlj1IW8dp6rIusVcdbYM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626898799; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kjlCqgWH6pPgYrklOenIkvHWm64/nMaB86DSmeNcAlg=; b=VjZtljsmc7QWxAr9gZlyNAtu2W86YS/+g2l9f7Iznaotd8xtzZNZpHzweBCXdPhKNuFDF7bzEnlcqRTIiVDzTEZwhBF9gnHSnAKx6u0eOIyOI7bME2ThVg9oRz9eYlZ08Xj7dNFsB2Ostm7moBAsgAEJ5E2NH0Gev6i+rnyVFZ4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626898799855340.4148666180605; Wed, 21 Jul 2021 13:19:59 -0700 (PDT) Received: from localhost ([::1]:47014 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6IhC-0005zQ-PU for importer@patchew.org; Wed, 21 Jul 2021 16:19:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36744) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IOH-0002xn-SS for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:29 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:40584) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IOC-0005or-JJ for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:24 -0400 Received: by mail-pj1-x1031.google.com with SMTP id u9-20020a17090a1f09b029017554809f35so503632pja.5 for ; Wed, 21 Jul 2021 13:00:19 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kjlCqgWH6pPgYrklOenIkvHWm64/nMaB86DSmeNcAlg=; b=YGjJCsV4jW3tfALyF3pFrO4wnjAdq1xYzoYsQxpjmx398WULiH+gT3FaDttA+vGNq8 1X6BJdmTvO3k4bSMLEXD6B0clRfAdPfm4ac4WssAbkyTEjmU3XPiTg+eFs0ZoKxEjszY XcjI7z2JNGlDd875wY8SsET9imM5qm/8s1b1Ik6Px5BOIC596zbsB1ppP/vZGG1mWamm luy0DUIfZQBSEyMiWOUSqSdNTfKzTNB+3bCy90U4+1Y5RW36AyIBEvIwvjkL63WxSunE D2jKZFz5aHo9e8HOUIwMa/pp2gWo5HqpxKvoVrUDvUOFRgQ94Hmf/dWUJgPJjoAtEVSr qkug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kjlCqgWH6pPgYrklOenIkvHWm64/nMaB86DSmeNcAlg=; b=mFHbLMre5BcGv4g3owRVyZ7gLX+tgGgWlutNxn/5CbzgJWH8jCxSJvcefaf4Ly0Cac PXP/JWWVlb5JMUpFumAaWx4IjGt5olo6RCLMLT4PUPhRJ08c9ckwKAlvStKhiI1nFt5n D7bdyKVZY2Xk66w7dsCr+WIrqZtLlvKHKtVgguCMgoWj4I1Iax12m6C0n8x4kZTRo26g d5+dt803QQwdjYgg/QAU3BYIRe/JDvmulkqbBVx1dlOaaQSHAhxpa258vdCOsoFsx5dK /oxgR/w3+DcHaN8yT3l+rflqtZw/0Ucvtx6Na5eSmra0iPxiPuCzweYTqk9dplN9ofFD sfIw== X-Gm-Message-State: AOAM532oTP1kVBj171jfGDdgl3rtqm9eyodXR6fFxWa0WXO6FmQ4fz3t J4+ShX4+oCy5oS4NiHcDKYh0cRe3psliOw== X-Google-Smtp-Source: ABdhPJyGIiczQOFB/6wC1A303j0MwIT+/iPhB29S68vtD0CmUetmYU0lNeaxPwVZDZSwxFsMbsh83w== X-Received: by 2002:aa7:8b56:0:b029:2b9:77be:d305 with SMTP id i22-20020aa78b560000b02902b977bed305mr38364016pfd.61.1626897619053; Wed, 21 Jul 2021 13:00:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 16/27] accel/tcg: Handle -singlestep in curr_cflags Date: Wed, 21 Jul 2021 09:59:43 -1000 Message-Id: <20210721195954.879535-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1626898801578100001 Content-Type: text/plain; charset="utf-8" Exchange the test in translator_use_goto_tb for CF_NO_GOTO_TB, and the test in tb_gen_code for setting CF_COUNT_MASK to 1. Tested-by: Mark Cave-Ayland Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20210717221851.2124573-6-richard.henderson@linaro.org> --- accel/tcg/cpu-exec.c | 8 +++++++- accel/tcg/translate-all.c | 2 +- accel/tcg/translator.c | 2 +- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 70ea3c7d68..2206c463f5 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -149,7 +149,13 @@ uint32_t curr_cflags(CPUState *cpu) { uint32_t cflags =3D cpu->tcg_cflags; =20 - if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { + /* + * For singlestep and -d nochain, suppress goto_tb so that + * we can log -d cpu,exec after every TB. + */ + if (singlestep) { + cflags |=3D CF_NO_GOTO_TB | 1; + } else if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { cflags |=3D CF_NO_GOTO_TB; } =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 5cc01d693b..bf82c15aab 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1432,7 +1432,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } QEMU_BUILD_BUG_ON(CF_COUNT_MASK + 1 !=3D TCG_MAX_INSNS); =20 - if (cpu->singlestep_enabled || singlestep) { + if (cpu->singlestep_enabled) { max_insns =3D 1; } =20 diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 2ea5a74f30..a59eb7c11b 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -39,7 +39,7 @@ bool translator_use_goto_tb(DisasContextBase *db, target_= ulong dest) } =20 /* Suppress goto_tb in the case of single-steping. */ - if (db->singlestep_enabled || singlestep) { + if (db->singlestep_enabled) { return false; } =20 --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626898419948856.7165857488212; Wed, 21 Jul 2021 13:13:39 -0700 (PDT) Received: from localhost ([::1]:58992 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6Ib4-0003Fh-P3 for importer@patchew.org; Wed, 21 Jul 2021 16:13:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36786) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IOK-0002xw-Pf for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:30 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:44777) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IOF-0005pG-PI for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:27 -0400 Received: by mail-pj1-x1032.google.com with SMTP id p4-20020a17090a9304b029016f3020d867so1946840pjo.3 for ; Wed, 21 Jul 2021 13:00:21 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DTRTI80fORwFOs4KxX5hNUbj/Raa40Oboxi0GCzL6jg=; b=HRGQvmYb2ufbGkQNPGQcalNkkVMKGqcVe7qJfMeWegTcJi7pcGrUd5ifY8nXRQ+kM+ E+3mBDI13njMlKWXGFJcDgRykTDCSk0O4ADn1n+4oKQrt+TBNL5j4Z/+1mcjQeb5vQht L6S/5WcibK0aJ4esHcY1HvXToFnX6rp7Ce2paIyA+DFgRPlBu0OMDZ7mfpipE7nKQGek K807GdEqDNN6Chq4bDVwpx8oTzQLysMgLFD4etIE5zaPLWqV0yf6WllHPo/BgOJQ9RKH /nhzdJ8aQMSSCaDqphc/WI2nRi4Xu50YoDUrxw7b2HtdoPoTN3ahil48rUGAKWYcJl0X IJHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DTRTI80fORwFOs4KxX5hNUbj/Raa40Oboxi0GCzL6jg=; b=jYandqUvoPFm51C4GPbtjkWwV24vq+XGtIA9Y5vzdEbtKDsqLE9GXd0vvkqdkd/Ltu g4aBy3LPf0qG5YR+nif8QdOmA+B1DXttIP7Q7HV7HasAaAmKjy7kZLwvmppRkyL3EEXk WrY7MCLG9HGWzy9xFn3eshSnjqdag49/g+Vj+VRK2/sov+wm+C1BTpcgauixyAmdi7gm B9QIT+ovjT2Q7QGsphpeJQ/5SVqqeaDEn1OuSRw5SUt8XVjwWDx8ouzOAmx4KxN+1hiD 5wGef81OyuO7s9hZxPqOK+txZtUkMvVcW2bM0AeXTw0+QwaFIgIPpbdUbHINej78NWB0 lh1Q== X-Gm-Message-State: AOAM533xkGNC/Qrr6MyZr2yWoFY09l0niR1HYTV7R0lQD5V0wxIYfPmC rrHHhCN1VLdDCOOC3f9PonnkneeJEKoYYA== X-Google-Smtp-Source: ABdhPJwNg1OOk/ATI8p3esO9A+ruM8SmouoFyqqUbOl/7gxS1IgTHhrmhPzN/oQrz4QTLkzIl+CSxw== X-Received: by 2002:a62:1c14:0:b029:34a:70f5:40da with SMTP id c20-20020a621c140000b029034a70f540damr16118993pfc.37.1626897620403; Wed, 21 Jul 2021 13:00:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 17/27] accel/tcg: Use CF_NO_GOTO_{TB, PTR} in cpu_exec_step_atomic Date: Wed, 21 Jul 2021 09:59:44 -1000 Message-Id: <20210721195954.879535-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , peter.maydell@linaro.org, Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626898420527100001 Request that the one TB returns immediately, so that we release the exclusive lock as soon as possible. Tested-by: Mark Cave-Ayland Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Message-Id: <20210717221851.2124573-7-richard.henderson@linaro.org> --- accel/tcg/cpu-exec.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 2206c463f5..5bb099174f 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -330,8 +330,7 @@ void cpu_exec_step_atomic(CPUState *cpu) CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; target_ulong cs_base, pc; - uint32_t flags; - uint32_t cflags =3D (curr_cflags(cpu) & ~CF_PARALLEL) | 1; + uint32_t flags, cflags; int tb_exit; =20 if (sigsetjmp(cpu->jmp_env, 0) =3D=3D 0) { @@ -341,8 +340,14 @@ void cpu_exec_step_atomic(CPUState *cpu) cpu->running =3D true; =20 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); =20 + cflags =3D curr_cflags(cpu); + /* Execute in a serial context. */ + cflags &=3D ~CF_PARALLEL; + /* After 1 insn, return and release the exclusive lock. */ + cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1; + + tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb =3D=3D NULL) { mmap_lock(); tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1626898488; cv=none; d=zohomail.com; s=zohoarc; b=Xpt3Cm2Szcr5vgEN0FDlVJKR6szz4qlFYRgsQ1SXjvVJkZ8t/Hc0ITpbu+DXH8KcsAwBZ8LbgWnUPNgw8ZloTQmZNjNVTgpd5wvonkZOHM/mlQ/KxaZh6w6AwxvIg1CyAXLiSYuvbOm7DC2W5NZA7BXdtUOmxsHfb8cXtyzLE+g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626898488; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=M1PZQ2MSvFDbXrpGppYIv2PQlYkQHkfO64Ue3b3IUQo=; b=esydkjjcX6JqclYvbz6Ifi0EPovWhjtIOJx/6ofCVGbpMAG+ggUiBB00Ca26GvjGhBihT0Pb3eqAyYO5wQLbLcdtjMBX4bEERdHdjMvfzowzwTA/FNqamBwHXN/giHU+l3VLab+kMGFQP73SUBzzpV2J6qhG9O0bP9H7mM3RAmU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626898488752357.51836476313986; Wed, 21 Jul 2021 13:14:48 -0700 (PDT) Received: from localhost ([::1]:33758 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6IcB-0005Hg-PY for importer@patchew.org; Wed, 21 Jul 2021 16:14:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36848) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IOP-00031Z-7E for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:37 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:43844) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IOF-0005pw-ON for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:31 -0400 Received: by mail-pj1-x102a.google.com with SMTP id x13-20020a17090a46cdb0290175cf22899cso1948644pjg.2 for ; Wed, 21 Jul 2021 13:00:22 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M1PZQ2MSvFDbXrpGppYIv2PQlYkQHkfO64Ue3b3IUQo=; b=p3BSvv9xlmaKy9mMqgf7c3I4fhv9lcpaokkFfOGnLWZPQoiKCB1hGcZpa9/AB1ieEd 53Mq+oNDy6NKaDm+cnqnQLyK4/7ASgK774fVXBALJAblogPxuWF/xC/eEr/12x41eJZ9 K2bmNNGAqcRBn53kpDglWmy//SxMqAPBVT7+nl22we1v0QXJ4cI6a1Ylf1WMCWcEeV61 SEu7AqukTKAoPrulK0VZPmxqdBuL6vovf//UMWqT7UTdDdZIs95VaeAsnrBqPi0Bw6gW QMqiMUINL1azw02BPBB73EP3MpDKRqyKs6vvuib26l0wY7SW9vo97zi3N935wElB0qtT qB3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M1PZQ2MSvFDbXrpGppYIv2PQlYkQHkfO64Ue3b3IUQo=; b=R8slD4E3aEN2rArsd/Jk8vBtCiZ0dWuo5WSOZ0mXa0NsMZuTiW7d6OfKjbWZIpMdsZ RI7UKsdl9OMveVnUCkcIksnpknBX6bf1hny6loL5LtZRATN6cMLtEEiaKZ7zhBmQIMas qRCSSnaAmMRDb2NYACSahXwaAXglgRmv5w+OHHk7V6DomckcAauyYAbRuz6zctNLYQe2 kdUG69ULvHUq4Si2f/0JvflcxAdWTSt97okLf47jGQ+jYZCDyeZ13otB5lpZ1UzKlLMu l1awHT3kEFEQN72VVKhl4+UJ+X7RqBPQGYeFof/kojiDv4jab64gcX2Q9I2xr1G6FQdG pOrw== X-Gm-Message-State: AOAM532pKIeYjSgg9hGskF167xB+UQqdELr+2HxVJcESx9jyZ6ZduG9K OaYR4CZjRDVMW2JQhl+mY2JHkTExdcvOgQ== X-Google-Smtp-Source: ABdhPJyCY0/NPNDuL0IY7jZpHidnuQpijwmlbDVeGJfNPf6w6sIETMgL+I9vZxsFU5gDuiO8zdnqFg== X-Received: by 2002:a05:6a00:1582:b029:332:67bf:c196 with SMTP id u2-20020a056a001582b029033267bfc196mr38765876pfk.52.1626897621765; Wed, 21 Jul 2021 13:00:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 18/27] hw/core: Introduce TCGCPUOps.debug_check_breakpoint Date: Wed, 21 Jul 2021 09:59:45 -1000 Message-Id: <20210721195954.879535-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1626898489155100001 New hook to return true when an architectural breakpoint is to be recognized and false when it should be suppressed. First use must wait until other pieces are in place. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 72d791438c..eab27d0c03 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -88,6 +88,12 @@ struct TCGCPUOps { */ bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); =20 + /** + * @debug_check_breakpoint: return true if the architectural + * breakpoint whose PC has matched should really fire. + */ + bool (*debug_check_breakpoint)(CPUState *cpu); + /** * @io_recompile_replay_branch: Callback for cpu_io_recompile. * --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1626898044; cv=none; d=zohomail.com; s=zohoarc; b=hWdqwe624S9i7P0ISJunlFWz+tkbhGi0YSFqCT+tuWxeneByW6u+nVeZG9HnLsrINCDMWOXnPq9OkAH5gnXYCn5LoP6EJEgG70qME5t3VFBGXOeIVtEvbeas2p2yX2nZne82juesKNDIs3f6h9a1MwqCPzBmRPY12gF8RCbR1wc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626898044; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dJN2k5SJVEq9tPKHGr6/aHWCsTEx2Fk2u0dskQ4Nk1Y=; b=P+Cyup+ozRacj6dFI7KS8RhHgif0HJs0dknoPavoYgKB70U/7/YbHWoApvTrKOLHqE/ovzzdvNImCxvGYPvYe9PpcNriUQubufGEQ2ZBS9jL3L4MpC7z1/ZbGY0TTPzrwu4EmG0zdqegdjEtL5vrPzztoBmxfEjJrxtZGs2M8Fw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626898044681868.3256006118496; Wed, 21 Jul 2021 13:07:24 -0700 (PDT) Received: from localhost ([::1]:42590 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6IV1-0000ZB-Ia for importer@patchew.org; Wed, 21 Jul 2021 16:07:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36794) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IOK-0002xx-W4 for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:31 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:37786) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IOH-0005qk-Jv for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:28 -0400 Received: by mail-pj1-x102b.google.com with SMTP id a17-20020a17090abe11b0290173ce472b8aso533557pjs.2 for ; Wed, 21 Jul 2021 13:00:23 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dJN2k5SJVEq9tPKHGr6/aHWCsTEx2Fk2u0dskQ4Nk1Y=; b=CKZc+AERNhFDelEz+YIZ8FT6VBQlFzwBReeyHf0pn44hKCtsLiYQGcY7Z62vNC8lL9 mc/zNXW9Ydz3ClUMfHUGyksHx5tBaQszzTQ8IFPCsP0mQxj2Xnc+/4FkBpsWZ+G8WglL rziuHqlIugPFHzqe5H2tRwUElfcSsXElrYjcXPTT729x/1f1yiAvx0gvsCafI5VMliaK 6AYFVCc4N4mQj69Q+SBKItH364U9/40Et9uAjQ9DHrEfVUwQOn/qWpvFm6PrjuclI/U5 UuCNqh8962cgEohsR1nTvCA5q5ie9EXws5KkK4ZBOsmrnLN3Lm4Xd4ao28lo1X3sJYt8 DU0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dJN2k5SJVEq9tPKHGr6/aHWCsTEx2Fk2u0dskQ4Nk1Y=; b=S+05t+JV9RmT4S49b0Xz23EBS67fMETogQk4bjvP/M8YogzHD5oShunnKjQc5HzUB8 +Ren9W6iyM/2K3Z6TgvzatQcr+mh7i5BzwIAu8dJsUYIFaiOGcjEhg5wvP207sebzm6Y k4Ia9dlwtCJK9Ce4jiyhgaH0SkN1OZisEOGC1QbRUVuKNLLJkdxA4Lsh7SJ+9UW8gG+U G/gEbevaGbYLoVta7nvaNr5F4mGZPg30jtEJf/zAAHs3uTSLXVLXXdl0cQoAvhzHAc1l HhuLgUvmDYomFgmZAOEsK/T5lwBME/Gi1ZKALJ/xglOxG55aZxbAXEqmTSPlgkm9qIzQ lLbQ== X-Gm-Message-State: AOAM530+9gB/dLY5Sg1U8LBx0YF8vhfPnD5CAnvfYonRG05Gq5068wQW dTpeFPlT1nPxFMuxHe5IgV2saEEhWRxRqQ== X-Google-Smtp-Source: ABdhPJxWyRun/y/ri+jY+tZgM3kk6Dy1TW9aUGkSFTmmWJClT37YItTkzoHuQvpJ5RHqlWXS+mj71w== X-Received: by 2002:aa7:8c47:0:b029:340:aa57:f65 with SMTP id e7-20020aa78c470000b0290340aa570f65mr22899786pfd.56.1626897623005; Wed, 21 Jul 2021 13:00:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 19/27] target/arm: Implement debug_check_breakpoint Date: Wed, 21 Jul 2021 09:59:46 -1000 Message-Id: <20210721195954.879535-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1626898044922100001 Reuse the code at the bottom of helper_check_breakpoints, which is what we currently call from *_tr_breakpoint_check. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/internals.h | 3 +++ target/arm/cpu.c | 1 + target/arm/cpu_tcg.c | 1 + target/arm/debug_helper.c | 7 +++---- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 3ba86e8af8..11a72013f5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -282,6 +282,9 @@ void hw_breakpoint_update(ARMCPU *cpu, int n); */ void hw_breakpoint_update_all(ARMCPU *cpu); =20 +/* Callback function for checking if a breakpoint should trigger. */ +bool arm_debug_check_breakpoint(CPUState *cs); + /* Callback function for checking if a watchpoint should trigger. */ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9cddfd6a44..752b15bb79 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1984,6 +1984,7 @@ static const struct TCGCPUOps arm_tcg_ops =3D { .do_unaligned_access =3D arm_cpu_do_unaligned_access, .adjust_watchpoint_address =3D arm_adjust_watchpoint_address, .debug_check_watchpoint =3D arm_debug_check_watchpoint, + .debug_check_breakpoint =3D arm_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ }; #endif /* CONFIG_TCG */ diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index d2d97115ea..ed444bf436 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -911,6 +911,7 @@ static const struct TCGCPUOps arm_v7m_tcg_ops =3D { .do_unaligned_access =3D arm_cpu_do_unaligned_access, .adjust_watchpoint_address =3D arm_adjust_watchpoint_address, .debug_check_watchpoint =3D arm_debug_check_watchpoint, + .debug_check_breakpoint =3D arm_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ }; #endif /* CONFIG_TCG */ diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 2ff72d47d1..4a0c479527 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -216,8 +216,9 @@ static bool check_watchpoints(ARMCPU *cpu) return false; } =20 -static bool check_breakpoints(ARMCPU *cpu) +bool arm_debug_check_breakpoint(CPUState *cs) { + ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; int n; =20 @@ -240,9 +241,7 @@ static bool check_breakpoints(ARMCPU *cpu) =20 void HELPER(check_breakpoints)(CPUARMState *env) { - ARMCPU *cpu =3D env_archcpu(env); - - if (check_breakpoints(cpu)) { + if (arm_debug_check_breakpoint(env_cpu(env))) { HELPER(exception_internal(env, EXCP_DEBUG)); } } --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1626898994; cv=none; d=zohomail.com; s=zohoarc; b=Ia2x394edLLFJ2hCyl6jENEa7eVABzcHeJJFUqspjwQupxfcPullMFJsxT3/lmY0Pvu7t7jcL4m9wU3jqW+tpizSf/1NnNDCd7H2ZfHDYdG/D2A3K6tWY7eAA6Ov+vxU9EN68cWHwTiQ6cleKBigxiTxJnAj5NDwoTvziPtt068= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626898994; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=P7/BMHsXFM5u+/5zB8fL6SRcNTVkT9GgtafQt9Cnl+M=; b=dYdLUQtBwGwEbFEny61F2NakR1fRsEmr+u8DEkHM6hynrWZmFXAc+EKrLOPIt9m2ro2+Ic5Q1V5zK4kFZUFqg7cNawpH7TF7DJkSlwkmqySN9BNkJC9qCf15itHSQXtiBFtSlgzDUHk+n5cXD19QCKkZd2DyJu10zlwBVpze2l4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626898994444448.3493163827908; Wed, 21 Jul 2021 13:23:14 -0700 (PDT) Received: from localhost ([::1]:55388 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6IkK-0003IW-U3 for importer@patchew.org; Wed, 21 Jul 2021 16:23:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36812) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IOL-0002xz-Ci for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:31 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:36815) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IOH-0005sm-LJ for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:28 -0400 Received: by mail-pl1-x62b.google.com with SMTP id x16so1651501plg.3 for ; Wed, 21 Jul 2021 13:00:25 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P7/BMHsXFM5u+/5zB8fL6SRcNTVkT9GgtafQt9Cnl+M=; b=H/hwpR0Nxbawf4a3cwXFxOUcA4/77o3fk6OaNHlX0rjoXkxJX1kDO+1p4wZSpCND3q Dy4IKl9OH71OcGREgk3TRS7hHkd1ZwOOPP0ZddJVwBQLBoT6cWthRQ7qy+qO1aUUH+RT NjWX4nhK8YfqqxnbHXA/W5AUDcH7pbRFhjqxS1Jq6OFfAMrTZ8PJCqA3hni9EVYP7VJf 52sDr5YXkMzJ+dWRZQ+31Jr09/3st6Ulo3rH0zn4a3pluPGmvwnWfGQIXsYZENI8fU8k d6hrtv6u4ufSxqMNYzck7/j2O9xht7AalHJMn0unje8lpzzhIlYVSd4vsi5abxsYqELl 7VAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P7/BMHsXFM5u+/5zB8fL6SRcNTVkT9GgtafQt9Cnl+M=; b=dbVQPZCiTbjedN3W9Xpx2OCXCb7oydYsnUosxmIaLyhdBXpJWPE+uJCGSk/ulS6z0c sIyc7JFeAxQD/Dq6Zg9iBBo1Gn8XszNpk1RJalmbZgkWPCh9aU2T4t7RidEo7OLrNu6r eUhKPlYkUZGHgBxxapxpaBdzrL3N5MLlIADHrQEauuFcoDRKQZA/8NDo0sgXRZN4NYRp crmiIHinuv0srv+uRs45+1tsIbAvhQq6cJqbCWbSE6k/Ct1qpdqHlj8DDW2q9m5qS7wd rqG9rmxasbuWNb9qb0NkRmezcmEwwCS+kMd7cxeAvtXUy7hXT9MVQpLWvWnx9G45lYJU gKTA== X-Gm-Message-State: AOAM531E8ztxLbFz0faBy7ynBzslF/aK4RBNyug+iQt71IJUpkbnNFRu 3Nxm9A9B2y+2Zgh04CtSXPrF1XZmIXazZg== X-Google-Smtp-Source: ABdhPJwYenygV08xgyeEah4Va2HTMZ+2UcnujqshVEcCxjOxU6APCyD2u2IxKC/a5gJtb1/f733FNQ== X-Received: by 2002:a17:902:9004:b029:f0:b40d:38d with SMTP id a4-20020a1709029004b02900f0b40d038dmr29068905plp.85.1626897624239; Wed, 21 Jul 2021 13:00:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 20/27] target/i386: Implement debug_check_breakpoint Date: Wed, 21 Jul 2021 09:59:47 -1000 Message-Id: <20210721195954.879535-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1626898995809100001 Return false for RF set, as we do in i386_tr_breakpoint_check. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/i386/tcg/tcg-cpu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index e96ec9bbcc..238e3a9395 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -54,6 +54,17 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, cpu->env.eip =3D tb->pc - tb->cs_base; } =20 +#ifndef CONFIG_USER_ONLY +static bool x86_debug_check_breakpoint(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + /* RF disables all architectural breakpoints. */ + return !(env->eflags & RF_MASK); +} +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static const struct TCGCPUOps x86_tcg_ops =3D { @@ -66,6 +77,7 @@ static const struct TCGCPUOps x86_tcg_ops =3D { .tlb_fill =3D x86_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY .debug_excp_handler =3D breakpoint_handler, + .debug_check_breakpoint =3D x86_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ }; =20 --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1626898250; cv=none; d=zohomail.com; s=zohoarc; b=mMNiHqd9mmT8DlXy71nPh/DXPjXxKhsZTB8T/MRSFVIxXNrMdKi+5tJvJK0VTx2ooQdn0stMRV3gvpn+fDJNxNd/iw+6c8CU3lr9rWi47LD7kd18MRhEyo4tSFXXb1Ss3QPWlXroorDrBAhwbLMV/5NlqJHova9lEgROPygEnGQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626898250; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qdFshZ1JFzbGAkyd3/YVEXhZvgnahsLT3Wd/z86Gd8Y=; b=hQHgdILsrHtCaT9TzRHl3bYoXUR5u9yzuHpGSn0KCUJrbuXXInCSYoG83p6vwcWANGNx/NM5yhasduxOkkrI6CHspfFk3z9AHEEZm+Emj8WDV72runbBJCdLk1DaHVupDqhBhuRxqRlsgpLp5VNUrgJoqnnQG3sbDNic5fPI2Q0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626898250211710.5047619831822; Wed, 21 Jul 2021 13:10:50 -0700 (PDT) Received: from localhost ([::1]:51006 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6IYL-0006B3-63 for importer@patchew.org; Wed, 21 Jul 2021 16:10:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36818) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IOL-0002yI-Hd for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:31 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:56309) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IOJ-0005uC-H8 for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:28 -0400 Received: by mail-pj1-x1031.google.com with SMTP id gx2so2541150pjb.5 for ; Wed, 21 Jul 2021 13:00:26 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qdFshZ1JFzbGAkyd3/YVEXhZvgnahsLT3Wd/z86Gd8Y=; b=r+Iv1GLvGF/M7czzJNI1zBqFmlfzBqu1lU0dvN6NDxAIfCHhQFemq5mTxtDmkNO2YS VAu4Yj3gCKc+BrebPo/kVjRFIoJ3KNeMNSXAKSTJj3r8+u/NJjpjNpH7B4Iq5zRydahD JQFmkQ3XAGuBai2cwLPKUpG7NaRxaLq3F1dExBo4NKPrxL/j1NZv0JgQcaGvmaFjOw0L CIVMWOOI3mx5PoClatJ3A5sbCFXrRvbAy61f/8QP0OhtkLTVfmv7qarx/5fEmUZC/7w2 FAc9XOZuqB7cxuG3tBiq4jpR+sa934qcrh2Qybyf+HdDo6rCQbX78UitGzanBst1z0a5 xreA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qdFshZ1JFzbGAkyd3/YVEXhZvgnahsLT3Wd/z86Gd8Y=; b=ZyvE21UdOJSdO/ryW3ZgcDsKqkCPd3QFhdV8cZGRen+y3HOmLxHxguMs73gWOElAoY +//TjEgyQqzPLpjeKLyUwSmMXUEtYaEwWfomv9DpZgXGM579BqQ8wF0p8ra5j/yRdCA9 o+0CHnxwtiiAEeD/+M6gK2wdIfCwv6vg0roo8YtpJ6QxZPP0B34uKeGrr45/EwUv/lKd vDyUmODJgci0FLWA4c2qB4YG39fp+rjtEoLYP06vAXXYVlDe3qIhuOUXnD9Xcjo0hZDb ndApmSZo1jiBPpCZP8nHB4f1j27CeoAykBxvx7lcj+76B0sgKXS19xSMb8Z9+5zgVb1h Qsew== X-Gm-Message-State: AOAM533CymuVImwTPMuNMaTqFmzCd7kbWyuucHxiKevM1T6xFB3PZ7Fn BSA0WB3dESsX3Z+wMznvBL6kLTpbWlCrLA== X-Google-Smtp-Source: ABdhPJw5f1ZFDHb1IVLGcAE9TPtukCRUw5og3/6XV1uUX78os62SYqBTPo7Z16bno98orRQbs8GXtg== X-Received: by 2002:a17:90b:110c:: with SMTP id gi12mr37030792pjb.163.1626897625689; Wed, 21 Jul 2021 13:00:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 21/27] hw/core: Introduce CPUClass.gdb_adjust_breakpoint Date: Wed, 21 Jul 2021 09:59:48 -1000 Message-Id: <20210721195954.879535-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1626898252068100001 This will allow a breakpoint hack to move out of AVR's translator. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 4 ++++ cpu.c | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 4e0ea68efc..bc864564ce 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -103,6 +103,9 @@ struct SysemuCPUOps; * also implement the synchronize_from_tb hook. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. + * @gdb_adjust_breakpoint: Callback for adjusting the address of a + * breakpoint. Used by AVR to handle a gdb mis-feature with + * its Harvard architecture split code and data. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to s= top @@ -137,6 +140,7 @@ struct CPUClass { void (*set_pc)(CPUState *cpu, vaddr value); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); + vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr); =20 const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); diff --git a/cpu.c b/cpu.c index 83059537d7..91d9e38acb 100644 --- a/cpu.c +++ b/cpu.c @@ -267,8 +267,13 @@ static void breakpoint_invalidate(CPUState *cpu, targe= t_ulong pc) int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, CPUBreakpoint **breakpoint) { + CPUClass *cc =3D CPU_GET_CLASS(cpu); CPUBreakpoint *bp; =20 + if (cc->gdb_adjust_breakpoint) { + pc =3D cc->gdb_adjust_breakpoint(cpu, pc); + } + bp =3D g_malloc(sizeof(*bp)); =20 bp->pc =3D pc; @@ -294,8 +299,13 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int= flags, /* Remove a specific breakpoint. */ int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags) { + CPUClass *cc =3D CPU_GET_CLASS(cpu); CPUBreakpoint *bp; =20 + if (cc->gdb_adjust_breakpoint) { + pc =3D cc->gdb_adjust_breakpoint(cpu, pc); + } + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { if (bp->pc =3D=3D pc && bp->flags =3D=3D flags) { cpu_breakpoint_remove_by_ref(cpu, bp); --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1626899348; cv=none; d=zohomail.com; s=zohoarc; b=MXG8Inf8WHhXihahD+B5yrJaITWOUqDuXuiJRSQ2AbsxeNgb4BYG/2h6YUKg4jdYQ8r79KbeSxJptugEBOf2/Tj35nz5qSqNg6gLYHQizp0Zt607dD6fxdApNAxnt4pClu2v7A7ccWdEuMVCxho/GaW3q8czbBY2pl9z3TRlnNE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626899348; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lKfL9kcE9bZaAS1wP7b8UNPiK9t3sVn3RcrRasY3aLw=; b=ft8TzZBtKwozXfDx3aXePatDbO8Yx6EmjWt9S8xPPMioAVH4hTFrNPviFXURsC47C+cGqCFQFYAMEpR11RAx4DGwI54r+Pqca/x4jhd6zf39/7bwP8EvLnG53R8NfJNwL/olElmhBvV1FjXrSggnAPswUximIZsFlZ08ViZmQD4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626899348382706.8128054739423; Wed, 21 Jul 2021 13:29:08 -0700 (PDT) Received: from localhost ([::1]:42992 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6Iq3-0005rd-CJ for importer@patchew.org; Wed, 21 Jul 2021 16:29:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36858) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IOP-00031a-CN for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:37 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:40846) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IOK-0005vE-CR for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:33 -0400 Received: by mail-pl1-x62e.google.com with SMTP id q13so721318plx.7 for ; Wed, 21 Jul 2021 13:00:27 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lKfL9kcE9bZaAS1wP7b8UNPiK9t3sVn3RcrRasY3aLw=; b=hvhnNmV4+jjMyuhtuHvPUAq25townmD4SgweCj20USzmdwXqEg4FhhBFKXlU8vcn7p fMgPk09SE51Lzacoc/vgYMHCg+5imEnnHxKcesTklka3smzScSQXY7btbCp2mRpxZa2l RA41KNViCcWqWkWizJtOc6BaElMcmMFY4yZOHr8//5bpokuc4ay32aZ2wjigrehMpLWt JE2fzMOzldckv805G8ty644Wk84+YwA9RDagOCMXtHjG/gngvoUICAI6CEeaMzoYP7Xm 7WMe7KZBCe1o13ACz5P94SLmbJUl4YVGiGussYQA6niBvfuuuE5DIi+mOkpqkMuVEiNC /mPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lKfL9kcE9bZaAS1wP7b8UNPiK9t3sVn3RcrRasY3aLw=; b=Vi2zFuTAs4kgTeWMgUPI+ZIn7R2N8X37605PRIKjUy7zfTrH6a2/d3BJ0r08M4m4fF pR2JQ3tbRccVWKNS43kSboL+2Z1Nb0KXt27SnAKznVdID3fc2bo0HNxRQFkaW/xxtDT2 ydXtL8LHcRsBFw0gF91aA3ELCfOJZFG80Z60bTtNEuMHf0FwAfoUmUaewdFKSjNbO+tc UZKG21zi2pyiwHaeo0eMGzPNrfg8KHtoZMCw55vc59bqGCv1e69zA83CT52nVNgQlWZb jh59iqp97pqxVJRoBx2u2MvJaZmnK1xFdDh0ScKI8zbmXcvadJVbG+mv4/Wv9PSSVyv0 +xag== X-Gm-Message-State: AOAM530TS5yqUxI56a/KMv4VKDx1Eiq69DETYJQ9f2ReCyMCo5EKAmJn ewL+sQEPPXMm2owrL7sRIXZd7wUE65BYAg== X-Google-Smtp-Source: ABdhPJzrhLsotIvFCBSFxbQmJ4TKGK1cCwr7xpOCiNHEd8jqJvZu69PNIdZfAkhZEsUnyX9BKMmz2A== X-Received: by 2002:aa7:980d:0:b029:32e:2373:cd63 with SMTP id e13-20020aa7980d0000b029032e2373cd63mr38092358pfl.51.1626897626849; Wed, 21 Jul 2021 13:00:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 22/27] target/avr: Implement gdb_adjust_breakpoint Date: Wed, 21 Jul 2021 09:59:49 -1000 Message-Id: <20210721195954.879535-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1626899349919100001 Ensure at registration that all breakpoints are in code space, not data space. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/avr/cpu.h | 1 + target/avr/cpu.c | 1 + target/avr/gdbstub.c | 13 +++++++++++++ target/avr/translate.c | 14 -------------- 4 files changed, 15 insertions(+), 14 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index d148e8c75a..93e3faa0a9 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -162,6 +162,7 @@ hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr= addr); int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int avr_print_insn(bfd_vma addr, disassemble_info *info); +vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr); =20 static inline int avr_feature(CPUAVRState *env, AVRFeature feature) { diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 57e3fab4a0..ea14175ca5 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -223,6 +223,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; + cc->gdb_adjust_breakpoint =3D avr_cpu_gdb_adjust_breakpoint; cc->gdb_num_core_regs =3D 35; cc->gdb_core_xml_file =3D "avr-cpu.xml"; cc->tcg_ops =3D &avr_tcg_ops; diff --git a/target/avr/gdbstub.c b/target/avr/gdbstub.c index c28ed67efe..1c1b908c92 100644 --- a/target/avr/gdbstub.c +++ b/target/avr/gdbstub.c @@ -82,3 +82,16 @@ int avr_cpu_gdb_write_register(CPUState *cs, uint8_t *me= m_buf, int n) =20 return 0; } + +vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr) +{ + /* + * This is due to some strange GDB behavior + * Let's assume main has address 0x100: + * b main - sets breakpoint at address 0x00000100 (code) + * b *0x100 - sets breakpoint at address 0x00800100 (data) + * + * Force all breakpoints into code space. + */ + return addr % OFFSET_DATA; +} diff --git a/target/avr/translate.c b/target/avr/translate.c index 8237a03c23..f7202a646b 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2958,20 +2958,6 @@ static void avr_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) DisasContext *ctx =3D container_of(dcbase, DisasContext, base); TCGLabel *skip_label =3D NULL; =20 - /* - * This is due to some strange GDB behavior - * Let's assume main has address 0x100: - * b main - sets breakpoint at address 0x00000100 (code) - * b *0x100 - sets breakpoint at address 0x00800100 (data) - * - * The translator driver has already taken care of the code pointer. - */ - if (!ctx->base.singlestep_enabled && - cpu_breakpoint_test(cs, OFFSET_DATA + ctx->base.pc_next, BP_ANY)) { - gen_breakpoint(ctx); - return; - } - /* Conditionally skip the next instruction, if indicated. */ if (ctx->skip_cond !=3D TCG_COND_NEVER) { skip_label =3D gen_new_label(); --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626899171398666.9279487978625; Wed, 21 Jul 2021 13:26:11 -0700 (PDT) Received: from localhost ([::1]:35414 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6InB-0000Wp-71 for importer@patchew.org; Wed, 21 Jul 2021 16:26:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IOP-00031c-V2 for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:38 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:44771) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IOL-0005wr-J7 for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:33 -0400 Received: by mail-pj1-x102a.google.com with SMTP id p4-20020a17090a9304b029016f3020d867so1947481pjo.3 for ; Wed, 21 Jul 2021 13:00:29 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DXOXSEfLZBNIVX60+JbD+azd+XSC/P1pd7+HVk2RYSk=; b=JZlvrbtv17tMQNoo6DyuqjZlN5d6ilPvNVtxWVrsFoJkauAbBY+b8CCSvAYBlZ7DqR yWBojgR+fbX/953xDHhxXNF1NK17teA1B3CpT4IOWdIH0iYkbCfYVazso+78JxT9niJd jio/QHe3mCOODYXGXvmw8hy5eDoNbtGi4MTseCP/FpcTbZ35uPQywiBnf20HhxP9bHY6 geHfqxY0TDVDVLSoI2Gyw2rbmdAsfmzfXUlesbfEmeMrLpTrgpqwnbjOPLG8SpJlh84A Qo/OUdNKd+UVuArNzeqqO6QBDjNJokmq0/1hk84bCjT8U02Kqewg4Zqbk6JjzCLKxAwf Rfhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DXOXSEfLZBNIVX60+JbD+azd+XSC/P1pd7+HVk2RYSk=; b=TZJRTcC2dSSF0VHRMqJlSaR+PJMahr4SwdXKlz80Ltz2du0NIFxSB1sVkJa9V4bnql NrqvEH3HeplEWR1u/OewGrD/biwQH930Cd0biY+w1vdVXQnHGBqe5J/8Ti0Yi8kSCZWj QcXcYy8WDEq1Fb4OPwS0ZPBJSzrysJzVtms6VcC6WIKgbzg8U1RHgV0lXgEYTpBFXuI5 RrSxbpl4Iib8TiDDyUYtKB+075oI+69ULAgmZzvB0bJDPZrTLqlo44asEySRa7ABotU/ Eh7f2XbYEyfNkzBKPhQfN666Xarzar1SS53bJedS3clbhlQ2tDbBh558SxZPwvg5oAp7 Ea7A== X-Gm-Message-State: AOAM530A5Tlh6M3JzUt7NJAC7/lbNqF87OC5IyK+/fsSecnlrusIPk7m wR1DRDmk/cP9C/PQHZ46M5n3t9C/ckLihA== X-Google-Smtp-Source: ABdhPJxk84Y8Av7q/iJQHY1EN12ogYpBEYAs6ZrnIVJGrgbllK8aodHc2ETR3h2XkWbRWVy9xdYsNw== X-Received: by 2002:a17:903:4101:b029:12b:8d5a:f883 with SMTP id r1-20020a1709034101b029012b8d5af883mr12847936pld.39.1626897628280; Wed, 21 Jul 2021 13:00:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 23/27] accel/tcg: Merge tb_find into its only caller Date: Wed, 21 Jul 2021 09:59:50 -1000 Message-Id: <20210721195954.879535-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , peter.maydell@linaro.org, Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626899173042100002 We are going to want two things: (1) check for breakpoints will want to break out of the loop here, (2) cflags can only be calculated with pc in hand. Tested-by: Mark Cave-Ayland Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 83 ++++++++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 42 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5bb099174f..cde7069eb7 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -500,41 +500,6 @@ static inline void tb_add_jump(TranslationBlock *tb, i= nt n, return; } =20 -static inline TranslationBlock *tb_find(CPUState *cpu, - TranslationBlock *last_tb, - int tb_exit, uint32_t cflags) -{ - CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; - TranslationBlock *tb; - target_ulong cs_base, pc; - uint32_t flags; - - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - - tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); - if (tb =3D=3D NULL) { - mmap_lock(); - tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); - mmap_unlock(); - /* We add the TB in the virtual pc hash table for the fast lookup = */ - qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb); - } -#ifndef CONFIG_USER_ONLY - /* We don't take care of direct jumps when address mapping changes in - * system emulation. So it's not safe to make a direct jump to a TB - * spanning two pages because the mapping for the second page can chan= ge. - */ - if (tb->page_addr[1] !=3D -1) { - last_tb =3D NULL; - } -#endif - /* See if we can patch the calling TB. */ - if (last_tb) { - tb_add_jump(last_tb, tb_exit, tb); - } - return tb; -} - static inline bool cpu_handle_halt(CPUState *cpu) { if (cpu->halted) { @@ -868,22 +833,56 @@ int cpu_exec(CPUState *cpu) int tb_exit =3D 0; =20 while (!cpu_handle_interrupt(cpu, &last_tb)) { - uint32_t cflags =3D cpu->cflags_next_tb; TranslationBlock *tb; + target_ulong cs_base, pc; + uint32_t flags, cflags; =20 - /* When requested, use an exact setting for cflags for the next - execution. This is used for icount, precise smc, and stop- - after-access watchpoints. Since this request should never - have CF_INVALID set, -1 is a convenient invalid value that - does not require tcg headers for cpu_common_reset. */ + /* + * When requested, use an exact setting for cflags for the next + * execution. This is used for icount, precise smc, and stop- + * after-access watchpoints. Since this request should never + * have CF_INVALID set, -1 is a convenient invalid value that + * does not require tcg headers for cpu_common_reset. + */ + cflags =3D cpu->cflags_next_tb; if (cflags =3D=3D -1) { cflags =3D curr_cflags(cpu); } else { cpu->cflags_next_tb =3D -1; } =20 - tb =3D tb_find(cpu, last_tb, tb_exit, cflags); + cpu_get_tb_cpu_state(cpu->env_ptr, &pc, &cs_base, &flags); + + tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); + if (tb =3D=3D NULL) { + mmap_lock(); + tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + mmap_unlock(); + /* + * We add the TB in the virtual pc hash table + * for the fast lookup + */ + qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]= , tb); + } + +#ifndef CONFIG_USER_ONLY + /* + * We don't take care of direct jumps when address mapping + * changes in system emulation. So it's not safe to make a + * direct jump to a TB spanning two pages because the mapping + * for the second page can change. + */ + if (tb->page_addr[1] !=3D -1) { + last_tb =3D NULL; + } +#endif + /* See if we can patch the calling TB. */ + if (last_tb) { + tb_add_jump(last_tb, tb_exit, tb); + } + cpu_loop_exec_tb(cpu, tb, &last_tb, &tb_exit); + /* Try to align the host and virtual clocks if the guest is in advance */ align_clocks(&sc, cpu); --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626898853291324.77827372683123; Wed, 21 Jul 2021 13:20:53 -0700 (PDT) Received: from localhost ([::1]:49996 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6Ii4-0007zk-45 for importer@patchew.org; Wed, 21 Jul 2021 16:20:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36882) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IOR-00031g-96 for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:38 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:39773) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IOP-0005yq-0F for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:35 -0400 Received: by mail-pj1-x1035.google.com with SMTP id k4-20020a17090a5144b02901731c776526so511324pjm.4 for ; Wed, 21 Jul 2021 13:00:30 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9GWkaKyRsG77alB6vA/2Z/4XpERa6jrLA8YHoeRukk0=; b=g0o6AtAON5ZZ3g/uJciZbtP5yf/rRKkIxLQFryEXVCuGXPFoDM/rAhtKg3+Tm0TjHo TLUn/d1GGY0fc0E98grVyjNTaPLU3guQ5RNIaAOK4EDlRIk0vnFRjIE5bcV7Vecj2CZ6 Pf+y6i2Qjl6Ixr5Dg+WNrHWKDomHGreGBT3sd8cgPMdaNBmppu2WaB9eolFdvUmhc3RQ Sh6LDU8GyXJtNFyECAkNzLXGQaK+7Yvz3qFxM6HAfSJwgNRwEKWh12nGoVuSX0SIRvUP kF5wgRVlIpED5wgEVuP0rHCvBc7lepZS4sDO9s22myznjuW7cr8XqCbLA4GYbg9RhJm0 1S3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9GWkaKyRsG77alB6vA/2Z/4XpERa6jrLA8YHoeRukk0=; b=mnHJXvWwmfoqooDZM6zkuqGRsVPpJWBxhLlD2bSn5m2CfhHbaqD+I0E8nlUG57mvtG 3xSuEcC2N/jKnh0S98yqX3MqmGnFKGa4NP1YiS13RrABaElXq0UqRmvN6jV3P4xC++j9 1zX/eJUeqUOVJGGpqF5op2bZ0zQE9fJohUYqzC7O43ibYtSGdKEWdA23ZedBdGpGxSar 1JMgT8uCkc3SXVCAjTE30O+SjQqVFZTJNnC7HSQyym/b3NiNoNNxhiDsDxiCFlhX7HGe kmNeKItTjLbXIthF+K9lct+awUV2A5sANE7dz+x1GPY9fcMMj71g997FEGVmF28h0CB3 L7Eg== X-Gm-Message-State: AOAM533tqO1pksV8nkcBMQ1Ro2synzCuNLX0Qwxhdu2UxnvhSdHmcztx 8R8TXrWrZcLAZHIc2OVygOEydK/wX5u4ug== X-Google-Smtp-Source: ABdhPJxbXSn63Qws8znP/pTsyvxr0txO2nrojjwXYBgW++sAIIxf8d41YZOHsnC7rB61qB7ZrRdprg== X-Received: by 2002:a17:902:e04e:b029:10f:133f:87c8 with SMTP id x14-20020a170902e04eb029010f133f87c8mr28962199plx.70.1626897629593; Wed, 21 Jul 2021 13:00:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 24/27] accel/tcg: Move breakpoint recognition outside translation Date: Wed, 21 Jul 2021 09:59:51 -1000 Message-Id: <20210721195954.879535-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , peter.maydell@linaro.org, Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626898854802100001 Trigger breakpoints before beginning translation of a TB that would begin with a BP. Thus we never generate code for the BP at all. Single-step instructions within a page containing a BP so that we are sure to check each insn for the BP as above. We no longer need to flush any TBs when changing BPs. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/286 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/404 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/489 Tested-by: Mark Cave-Ayland Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 91 ++++++++++++++++++++++++++++++++++++++++-- accel/tcg/translator.c | 24 +---------- cpu.c | 20 ---------- 3 files changed, 89 insertions(+), 46 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index cde7069eb7..5cc6363f4c 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -222,6 +222,76 @@ static inline void log_cpu_exec(target_ulong pc, CPUSt= ate *cpu, } } =20 +static bool check_for_breakpoints(CPUState *cpu, target_ulong pc, + uint32_t *cflags) +{ + CPUBreakpoint *bp; + bool match_page =3D false; + + if (likely(QTAILQ_EMPTY(&cpu->breakpoints))) { + return false; + } + + /* + * Singlestep overrides breakpoints. + * This requirement is visible in the record-replay tests, where + * we would fail to make forward progress in reverse-continue. + * + * TODO: gdb singlestep should only override gdb breakpoints, + * so that one could (gdb) singlestep into the guest kernel's + * architectural breakpoint handler. + */ + if (cpu->singlestep_enabled) { + return false; + } + + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + /* + * If we have an exact pc match, trigger the breakpoint. + * Otherwise, note matches within the page. + */ + if (pc =3D=3D bp->pc) { + bool match_bp =3D false; + + if (bp->flags & BP_GDB) { + match_bp =3D true; + } else if (bp->flags & BP_CPU) { +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + CPUClass *cc =3D CPU_GET_CLASS(cpu); + assert(cc->tcg_ops->debug_check_breakpoint); + match_bp =3D cc->tcg_ops->debug_check_breakpoint(cpu); +#endif + } + + if (match_bp) { + cpu->exception_index =3D EXCP_DEBUG; + return true; + } + } else if (((pc ^ bp->pc) & TARGET_PAGE_MASK) =3D=3D 0) { + match_page =3D true; + } + } + + /* + * Within the same page as a breakpoint, single-step, + * returning to helper_lookup_tb_ptr after each insn looking + * for the actual breakpoint. + * + * TODO: Perhaps better to record all of the TBs associated + * with a given virtual page that contains a breakpoint, and + * then invalidate them when a new overlapping breakpoint is + * set on the page. Non-overlapping TBs would not be + * invalidated, nor would any TB need to be invalidated as + * breakpoints are removed. + */ + if (match_page) { + *cflags =3D (*cflags & ~CF_COUNT_MASK) | CF_NO_GOTO_TB | 1; + } + return false; +} + /** * helper_lookup_tb_ptr: quick check for next tb * @env: current cpu state @@ -235,11 +305,16 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) CPUState *cpu =3D env_cpu(env); TranslationBlock *tb; target_ulong cs_base, pc; - uint32_t flags; + uint32_t flags, cflags; =20 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); =20 - tb =3D tb_lookup(cpu, pc, cs_base, flags, curr_cflags(cpu)); + cflags =3D curr_cflags(cpu); + if (check_for_breakpoints(cpu, pc, &cflags)) { + cpu_loop_exit(cpu); + } + + tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb =3D=3D NULL) { return tcg_code_gen_epilogue; } @@ -346,6 +421,12 @@ void cpu_exec_step_atomic(CPUState *cpu) cflags &=3D ~CF_PARALLEL; /* After 1 insn, return and release the exclusive lock. */ cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1; + /* + * No need to check_for_breakpoints here. + * We only arrive in cpu_exec_step_atomic after beginning execution + * of an insn that includes an atomic operation we can't handle. + * Any breakpoint for this insn will have been recognized earlier. + */ =20 tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb =3D=3D NULL) { @@ -837,6 +918,8 @@ int cpu_exec(CPUState *cpu) target_ulong cs_base, pc; uint32_t flags, cflags; =20 + cpu_get_tb_cpu_state(cpu->env_ptr, &pc, &cs_base, &flags); + /* * When requested, use an exact setting for cflags for the next * execution. This is used for icount, precise smc, and stop- @@ -851,7 +934,9 @@ int cpu_exec(CPUState *cpu) cpu->cflags_next_tb =3D -1; } =20 - cpu_get_tb_cpu_state(cpu->env_ptr, &pc, &cs_base, &flags); + if (check_for_breakpoints(cpu, pc, &cflags)) { + break; + } =20 tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb =3D=3D NULL) { diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index a59eb7c11b..4f3728c278 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -50,7 +50,6 @@ bool translator_use_goto_tb(DisasContextBase *db, target_= ulong dest) void translator_loop(const TranslatorOps *ops, DisasContextBase *db, CPUState *cpu, TranslationBlock *tb, int max_insns) { - int bp_insn =3D 0; bool plugin_enabled; =20 /* Initialize DisasContext */ @@ -85,27 +84,6 @@ void translator_loop(const TranslatorOps *ops, DisasCont= extBase *db, plugin_gen_insn_start(cpu, db); } =20 - /* Pass breakpoint hits to target for further processing */ - if (!db->singlestep_enabled - && unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - if (bp->pc =3D=3D db->pc_next) { - if (ops->breakpoint_check(db, cpu, bp)) { - bp_insn =3D 1; - break; - } - } - } - /* The breakpoint_check hook may use DISAS_TOO_MANY to indicate - that only one more instruction is to be executed. Otherwise - it should use DISAS_NORETURN when generating an exception, - but may use a DISAS_TARGET_* value for Something Else. */ - if (db->is_jmp > DISAS_TOO_MANY) { - break; - } - } - /* Disassemble one instruction. The translate_insn hook should update db->pc_next and db->is_jmp to indicate what should be done next -- either exiting this loop or locate the start of @@ -144,7 +122,7 @@ void translator_loop(const TranslatorOps *ops, DisasCon= textBase *db, =20 /* Emit code to exit the TB, as indicated by db->is_jmp. */ ops->tb_stop(db, cpu); - gen_tb_end(db->tb, db->num_insns - bp_insn); + gen_tb_end(db->tb, db->num_insns); =20 if (plugin_enabled) { plugin_gen_tb_end(cpu); diff --git a/cpu.c b/cpu.c index 91d9e38acb..d6ae5ae581 100644 --- a/cpu.c +++ b/cpu.c @@ -225,11 +225,6 @@ void tb_invalidate_phys_addr(target_ulong addr) tb_invalidate_phys_page_range(addr, addr + 1); mmap_unlock(); } - -static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) -{ - tb_invalidate_phys_addr(pc); -} #else void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs att= rs) { @@ -250,17 +245,6 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr = addr, MemTxAttrs attrs) ram_addr =3D memory_region_get_ram_addr(mr) + addr; tb_invalidate_phys_page_range(ram_addr, ram_addr + 1); } - -static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) -{ - /* - * There may not be a virtual to physical translation for the pc - * right now, but there may exist cached TB for this pc. - * Flush the whole TB cache to force re-translation of such TBs. - * This is heavyweight, but we're debugging anyway. - */ - tb_flush(cpu); -} #endif =20 /* Add a breakpoint. */ @@ -286,8 +270,6 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int = flags, QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry); } =20 - breakpoint_invalidate(cpu, pc); - if (breakpoint) { *breakpoint =3D bp; } @@ -320,8 +302,6 @@ void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBre= akpoint *bp) { QTAILQ_REMOVE(&cpu->breakpoints, bp, entry); =20 - breakpoint_invalidate(cpu, bp->pc); - trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags); g_free(bp); } --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1626898656; cv=none; d=zohomail.com; s=zohoarc; b=g9WC3E1LM25L4lfpE/RO5hodEHu+WxucyyImTv63zpKRM5TU+nAOiAFp7QwfYFa5etIe00L/Pin524KcAO3p2xp7LIrl2Ezpfk7CM2x9nBqjF6RMrQPH8LtXaRa1rvVzaxd2cMoQb2H+kbk2e3//3EwlLWtDwomNGGj8u2vpk+Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626898656; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WLlNOYb7V1szy63ymfXSKL8yHvS0NPcKsC3nVJw2dt4=; b=itoWu0GYIddQkn2Ng8ajEq/m9zFgSSPxbMoq2E9OmYPXzmgh8si2QRjf+8MuofMyenZr+YFvHVN8bHIoRXiVUGY+atMWjNzukuLDWoAZXyD5QjYcYf2J12yDzTHn3zdkKwovRLawPksNFZEkh506zGJBtUwtExKydCEyI5nzdBw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626898656475895.1017858664077; Wed, 21 Jul 2021 13:17:36 -0700 (PDT) Received: from localhost ([::1]:39082 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6Iet-0000ZU-8j for importer@patchew.org; Wed, 21 Jul 2021 16:17:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36906) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IOT-00031m-9f for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:38 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:47080) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IOP-00061F-09 for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:37 -0400 Received: by mail-pj1-x102a.google.com with SMTP id nt18-20020a17090b2492b02901765d605e14so972372pjb.5 for ; Wed, 21 Jul 2021 13:00:32 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WLlNOYb7V1szy63ymfXSKL8yHvS0NPcKsC3nVJw2dt4=; b=D9jPMEp1XjKm8nv0Y+A6UHZvKqtfRyoReYF1FbW7cX/ygVJoaDsQVq5ub8VYMtcrkF 76dxIbJHZlHQPyKyf6XMvobA9Qn/2w/Hak9huxAIwkobJaqOESrBqLe29nUwpwvfstmY xSSGAJMYyZqm6SlLmcV9yWU1OIR73y2p1Gnyoho3/rVwnD4FeOIR0jRf0la9g1cgu0FW WdJj9ZUGrzGN5GKj1U7qBzS6e0n37nU2ZUMyQSJPwhkbzcFbTYpXCCyreQA+9yMEb1br SZ0UTbbe64cnPa+peJ62/sq3bG0Xm8Zsopxkm1wwrDsZNX4wGhERiY1Yn5RRFIuA0J/B cf/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WLlNOYb7V1szy63ymfXSKL8yHvS0NPcKsC3nVJw2dt4=; b=aR8wgokI6g17gHXFywTXn1OfLgQmSrZbY7HdyZNLbtoaMILYgKF+cRjbzMCi2pgcpp oLDCU65vqG4XL4TbTnazrEwMqkk89EnSwwRXgmuSZZ15cCAn/RaNWFvSPSjqu4hzhyTN 2cJyDrZusURmXPs0ZiUuvkOmhDpLZ79UIyN1KF3KrGyYEQefNtY8PIoiessUwVdvmiZj VbgNHu6Ay7iOFvFkIHImL9wk0sgd7sPinzkhTAjgjKSabRJj2PmPOmcqDB6TjeSww84Q UaMTWB27RPP9chI+KRV4hV9wpJEFOuMzNIb+mUMzgKBJitFRskLG0IKyoqpioCRctbzY EMAQ== X-Gm-Message-State: AOAM531aROsvkdKe0xt7y8qGRBHRVzCSvHBcD30V86b0gp49fQIhiyyF JcPYfH5xEcjuEIl3MoQI91N8nI5JmNdyeg== X-Google-Smtp-Source: ABdhPJygSrqr6d+8DU3P2eCphnEKWV66IxLyhMd2zN3DsLk/MY2lBN/EtzNn2GWcdPleUMAhY9tDoA== X-Received: by 2002:a17:902:6b82:b029:120:3404:ce99 with SMTP id p2-20020a1709026b82b02901203404ce99mr28608151plk.49.1626897630999; Wed, 21 Jul 2021 13:00:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 25/27] accel/tcg: Remove TranslatorOps.breakpoint_check Date: Wed, 21 Jul 2021 09:59:52 -1000 Message-Id: <20210721195954.879535-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1626898658311100001 The hook is now unused, with breakpoints checked outside translation. Tested-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/translator.h | 11 ----------- target/arm/helper.h | 2 -- target/alpha/translate.c | 16 ---------------- target/arm/debug_helper.c | 7 ------- target/arm/translate-a64.c | 25 ------------------------- target/arm/translate.c | 29 ----------------------------- target/avr/translate.c | 18 ------------------ target/cris/translate.c | 20 -------------------- target/hexagon/translate.c | 17 ----------------- target/hppa/translate.c | 11 ----------- target/i386/tcg/translate.c | 28 ---------------------------- target/m68k/translate.c | 18 ------------------ target/microblaze/translate.c | 18 ------------------ target/mips/tcg/translate.c | 19 ------------------- target/nios2/translate.c | 27 --------------------------- target/openrisc/translate.c | 17 ----------------- target/ppc/translate.c | 18 ------------------ target/riscv/translate.c | 17 ----------------- target/rx/translate.c | 14 -------------- target/s390x/tcg/translate.c | 24 ------------------------ target/sh4/translate.c | 18 ------------------ target/sparc/translate.c | 17 ----------------- target/tricore/translate.c | 16 ---------------- target/xtensa/translate.c | 17 ----------------- 24 files changed, 424 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index dd9c06d40d..d318803267 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -89,15 +89,6 @@ typedef struct DisasContextBase { * @insn_start: * Emit the tcg_gen_insn_start opcode. * - * @breakpoint_check: - * When called, the breakpoint has already been checked to match the = PC, - * but the target may decide the breakpoint missed the address - * (e.g., due to conditions encoded in their flags). Return true to - * indicate that the breakpoint did hit, in which case no more breakp= oints - * are checked. If the breakpoint did hit, emit any code required to - * signal the exception, and set db->is_jmp as necessary to terminate - * the main loop. - * * @translate_insn: * Disassemble one instruction and set db->pc_next for the start * of the following instruction. Set db->is_jmp as necessary to @@ -113,8 +104,6 @@ typedef struct TranslatorOps { void (*init_disas_context)(DisasContextBase *db, CPUState *cpu); void (*tb_start)(DisasContextBase *db, CPUState *cpu); void (*insn_start)(DisasContextBase *db, CPUState *cpu); - bool (*breakpoint_check)(DisasContextBase *db, CPUState *cpu, - const CPUBreakpoint *bp); void (*translate_insn)(DisasContextBase *db, CPUState *cpu); void (*tb_stop)(DisasContextBase *db, CPUState *cpu); void (*disas_log)(const DisasContextBase *db, CPUState *cpu); diff --git a/target/arm/helper.h b/target/arm/helper.h index db87d7d537..248569b0cd 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -54,8 +54,6 @@ DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) DEF_HELPER_2(pre_smc, void, env, i32) =20 -DEF_HELPER_1(check_breakpoints, void, env) - DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_2(cpsr_write_eret, void, env, i32) DEF_HELPER_1(cpsr_read, i32, env) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 949ba6ffde..de6c0a8439 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2967,21 +2967,6 @@ static void alpha_tr_insn_start(DisasContextBase *dc= base, CPUState *cpu) tcg_gen_insn_start(dcbase->pc_next); } =20 -static bool alpha_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *= cpu, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - ctx->base.is_jmp =3D gen_excp(ctx, EXCP_DEBUG, 0); - - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx->base.pc_next +=3D 4; - return true; -} - static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); @@ -3040,7 +3025,6 @@ static const TranslatorOps alpha_tr_ops =3D { .init_disas_context =3D alpha_tr_init_disas_context, .tb_start =3D alpha_tr_tb_start, .insn_start =3D alpha_tr_insn_start, - .breakpoint_check =3D alpha_tr_breakpoint_check, .translate_insn =3D alpha_tr_translate_insn, .tb_stop =3D alpha_tr_tb_stop, .disas_log =3D alpha_tr_disas_log, diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 4a0c479527..2983e36dd3 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -239,13 +239,6 @@ bool arm_debug_check_breakpoint(CPUState *cs) return false; } =20 -void HELPER(check_breakpoints)(CPUARMState *env) -{ - if (arm_debug_check_breakpoint(env_cpu(env))) { - HELPER(exception_internal(env, EXCP_DEBUG)); - } -} - bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) { /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ca11a5fecd..422e2ac0c9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14844,30 +14844,6 @@ static void aarch64_tr_insn_start(DisasContextBase= *dcbase, CPUState *cpu) dc->insn_start =3D tcg_last_op(); } =20 -static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState= *cpu, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - if (bp->flags & BP_CPU) { - gen_a64_set_pc_im(dc->base.pc_next); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it likely won't be executed */ - dc->base.is_jmp =3D DISAS_TOO_MANY; - } else { - gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - dc->base.pc_next +=3D 4; - dc->base.is_jmp =3D DISAS_NORETURN; - } - - return true; -} - static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *= cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -14982,7 +14958,6 @@ const TranslatorOps aarch64_translator_ops =3D { .init_disas_context =3D aarch64_tr_init_disas_context, .tb_start =3D aarch64_tr_tb_start, .insn_start =3D aarch64_tr_insn_start, - .breakpoint_check =3D aarch64_tr_breakpoint_check, .translate_insn =3D aarch64_tr_translate_insn, .tb_stop =3D aarch64_tr_tb_stop, .disas_log =3D aarch64_tr_disas_log, diff --git a/target/arm/translate.c b/target/arm/translate.c index e1a8152598..351afa43a2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9438,33 +9438,6 @@ static void arm_tr_insn_start(DisasContextBase *dcba= se, CPUState *cpu) dc->insn_start =3D tcg_last_op(); } =20 -static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cp= u, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - if (bp->flags & BP_CPU) { - gen_set_condexec(dc); - gen_set_pc_im(dc, dc->base.pc_next); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it's likely not going to be executed */ - dc->base.is_jmp =3D DISAS_TOO_MANY; - } else { - gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - /* TODO: Advance PC by correct instruction length to - * avoid disassembler error messages */ - dc->base.pc_next +=3D 2; - dc->base.is_jmp =3D DISAS_NORETURN; - } - - return true; -} - static bool arm_pre_translate_insn(DisasContext *dc) { #ifdef CONFIG_USER_ONLY @@ -9827,7 +9800,6 @@ static const TranslatorOps arm_translator_ops =3D { .init_disas_context =3D arm_tr_init_disas_context, .tb_start =3D arm_tr_tb_start, .insn_start =3D arm_tr_insn_start, - .breakpoint_check =3D arm_tr_breakpoint_check, .translate_insn =3D arm_tr_translate_insn, .tb_stop =3D arm_tr_tb_stop, .disas_log =3D arm_tr_disas_log, @@ -9837,7 +9809,6 @@ static const TranslatorOps thumb_translator_ops =3D { .init_disas_context =3D arm_tr_init_disas_context, .tb_start =3D arm_tr_tb_start, .insn_start =3D arm_tr_insn_start, - .breakpoint_check =3D arm_tr_breakpoint_check, .translate_insn =3D thumb_tr_translate_insn, .tb_stop =3D arm_tr_tb_stop, .disas_log =3D arm_tr_disas_log, diff --git a/target/avr/translate.c b/target/avr/translate.c index f7202a646b..1111e08b83 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2900,14 +2900,6 @@ static bool canonicalize_skip(DisasContext *ctx) return true; } =20 -static void gen_breakpoint(DisasContext *ctx) -{ - canonicalize_skip(ctx); - tcg_gen_movi_tl(cpu_pc, ctx->npc); - gen_helper_debug(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; -} - static void avr_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); @@ -2944,15 +2936,6 @@ static void avr_tr_insn_start(DisasContextBase *dcba= se, CPUState *cs) tcg_gen_insn_start(ctx->npc); } =20 -static bool avr_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - gen_breakpoint(ctx); - return true; -} - static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); @@ -3055,7 +3038,6 @@ static const TranslatorOps avr_tr_ops =3D { .init_disas_context =3D avr_tr_init_disas_context, .tb_start =3D avr_tr_tb_start, .insn_start =3D avr_tr_insn_start, - .breakpoint_check =3D avr_tr_breakpoint_check, .translate_insn =3D avr_tr_translate_insn, .tb_stop =3D avr_tr_tb_stop, .disas_log =3D avr_tr_disas_log, diff --git a/target/cris/translate.c b/target/cris/translate.c index 9258c13e9f..a84b753349 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3118,25 +3118,6 @@ static void cris_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) tcg_gen_insn_start(dc->delayed_branch =3D=3D 1 ? dc->ppc | 1 : dc->pc); } =20 -static bool cris_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= pu, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - cris_evaluate_flags(dc); - tcg_gen_movi_tl(env_pc, dc->pc); - t_gen_raise_exception(EXCP_DEBUG); - dc->base.is_jmp =3D DISAS_NORETURN; - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - dc->pc +=3D 2; - return true; -} - static void cris_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -3315,7 +3296,6 @@ static const TranslatorOps cris_tr_ops =3D { .init_disas_context =3D cris_tr_init_disas_context, .tb_start =3D cris_tr_tb_start, .insn_start =3D cris_tr_insn_start, - .breakpoint_check =3D cris_tr_breakpoint_check, .translate_insn =3D cris_tr_translate_insn, .tb_stop =3D cris_tr_tb_stop, .disas_log =3D cris_tr_disas_log, diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index b23d36adf5..54fdcaa5e8 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -540,22 +540,6 @@ static void hexagon_tr_insn_start(DisasContextBase *dc= base, CPUState *cpu) tcg_gen_insn_start(ctx->base.pc_next); } =20 -static bool hexagon_tr_breakpoint_check(DisasContextBase *dcbase, CPUState= *cpu, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - gen_exception_end_tb(ctx, EXCP_DEBUG); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - ctx->base.pc_next +=3D 4; - return true; -} - static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx) { target_ulong page_start =3D ctx->base.pc_first & TARGET_PAGE_MASK; @@ -631,7 +615,6 @@ static const TranslatorOps hexagon_tr_ops =3D { .init_disas_context =3D hexagon_tr_init_disas_context, .tb_start =3D hexagon_tr_tb_start, .insn_start =3D hexagon_tr_insn_start, - .breakpoint_check =3D hexagon_tr_breakpoint_check, .translate_insn =3D hexagon_tr_translate_packet, .tb_stop =3D hexagon_tr_tb_stop, .disas_log =3D hexagon_tr_disas_log, diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 2552747138..b18150ef8d 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4159,16 +4159,6 @@ static void hppa_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cs) tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b); } =20 -static bool hppa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= s, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - gen_excp(ctx, EXCP_DEBUG); - ctx->base.pc_next +=3D 4; - return true; -} - static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); @@ -4330,7 +4320,6 @@ static const TranslatorOps hppa_tr_ops =3D { .init_disas_context =3D hppa_tr_init_disas_context, .tb_start =3D hppa_tr_tb_start, .insn_start =3D hppa_tr_insn_start, - .breakpoint_check =3D hppa_tr_breakpoint_check, .translate_insn =3D hppa_tr_translate_insn, .tb_stop =3D hppa_tr_tb_stop, .disas_log =3D hppa_tr_disas_log, diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 8520d5a1e2..aacb605eee 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2604,14 +2604,6 @@ static void gen_interrupt(DisasContext *s, int intno, s->base.is_jmp =3D DISAS_NORETURN; } =20 -static void gen_debug(DisasContext *s) -{ - gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); - gen_helper_debug(cpu_env); - s->base.is_jmp =3D DISAS_NORETURN; -} - static void gen_set_hflag(DisasContext *s, uint32_t mask) { if ((s->flags & mask) =3D=3D 0) { @@ -8635,25 +8627,6 @@ static void i386_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); } =20 -static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= pu, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - /* If RF is set, suppress an internally generated breakpoint. */ - int flags =3D dc->base.tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY; - if (bp->flags & flags) { - gen_debug(dc); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the generic logic setting tb->size later does the right thing. = */ - dc->base.pc_next +=3D 1; - return true; - } else { - return false; - } -} - static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -8721,7 +8694,6 @@ static const TranslatorOps i386_tr_ops =3D { .init_disas_context =3D i386_tr_init_disas_context, .tb_start =3D i386_tr_tb_start, .insn_start =3D i386_tr_insn_start, - .breakpoint_check =3D i386_tr_breakpoint_check, .translate_insn =3D i386_tr_translate_insn, .tb_stop =3D i386_tr_tb_stop, .disas_log =3D i386_tr_disas_log, diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 1fee04b8dd..c34d9aed61 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -6208,23 +6208,6 @@ static void m68k_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); } =20 -static bool m68k_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= pu, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - gen_exception(dc, dc->base.pc_next, EXCP_DEBUG); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - dc->base.pc_next +=3D 2; - - return true; -} - static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -6310,7 +6293,6 @@ static const TranslatorOps m68k_tr_ops =3D { .init_disas_context =3D m68k_tr_init_disas_context, .tb_start =3D m68k_tr_tb_start, .insn_start =3D m68k_tr_insn_start, - .breakpoint_check =3D m68k_tr_breakpoint_check, .translate_insn =3D m68k_tr_translate_insn, .tb_stop =3D m68k_tr_tb_stop, .disas_log =3D m68k_tr_disas_log, diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index c68a84a219..a14ffed784 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1673,23 +1673,6 @@ static void mb_tr_insn_start(DisasContextBase *dcb, = CPUState *cs) dc->insn_start =3D tcg_last_op(); } =20 -static bool mb_tr_breakpoint_check(DisasContextBase *dcb, CPUState *cs, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcb, DisasContext, base); - - gen_raise_exception_sync(dc, EXCP_DEBUG); - - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - dc->base.pc_next +=3D 4; - return true; -} - static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) { DisasContext *dc =3D container_of(dcb, DisasContext, base); @@ -1854,7 +1837,6 @@ static const TranslatorOps mb_tr_ops =3D { .init_disas_context =3D mb_tr_init_disas_context, .tb_start =3D mb_tr_tb_start, .insn_start =3D mb_tr_insn_start, - .breakpoint_check =3D mb_tr_breakpoint_check, .translate_insn =3D mb_tr_translate_insn, .tb_stop =3D mb_tr_tb_stop, .disas_log =3D mb_tr_disas_log, diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index fd980ea966..5b03545f09 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -16178,24 +16178,6 @@ static void mips_tr_insn_start(DisasContextBase *d= cbase, CPUState *cs) ctx->btarget); } =20 -static bool mips_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= s, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - save_cpu_state(ctx, 1); - ctx->base.is_jmp =3D DISAS_NORETURN; - gen_helper_raise_exception_debug(cpu_env); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - ctx->base.pc_next +=3D 4; - return true; -} - static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { CPUMIPSState *env =3D cs->env_ptr; @@ -16303,7 +16285,6 @@ static const TranslatorOps mips_tr_ops =3D { .init_disas_context =3D mips_tr_init_disas_context, .tb_start =3D mips_tr_tb_start, .insn_start =3D mips_tr_insn_start, - .breakpoint_check =3D mips_tr_breakpoint_check, .translate_insn =3D mips_tr_translate_insn, .tb_stop =3D mips_tr_tb_stop, .disas_log =3D mips_tr_disas_log, diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 17742cebc7..08d7ac5398 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -744,16 +744,6 @@ static const char * const regnames[] =3D { =20 #include "exec/gen-icount.h" =20 -static void gen_exception(DisasContext *dc, uint32_t excp) -{ - TCGv_i32 tmp =3D tcg_const_i32(excp); - - tcg_gen_movi_tl(cpu_R[R_PC], dc->pc); - gen_helper_raise_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); - dc->base.is_jmp =3D DISAS_NORETURN; -} - /* generate intermediate code for basic block 'tb'. */ static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) { @@ -777,22 +767,6 @@ static void nios2_tr_insn_start(DisasContextBase *dcba= se, CPUState *cs) tcg_gen_insn_start(dcbase->pc_next); } =20 -static bool nios2_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *= cs, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - gen_exception(dc, EXCP_DEBUG); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - dc->base.pc_next +=3D 4; - return true; -} - static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -870,7 +844,6 @@ static const TranslatorOps nios2_tr_ops =3D { .init_disas_context =3D nios2_tr_init_disas_context, .tb_start =3D nios2_tr_tb_start, .insn_start =3D nios2_tr_insn_start, - .breakpoint_check =3D nios2_tr_breakpoint_check, .translate_insn =3D nios2_tr_translate_insn, .tb_stop =3D nios2_tr_tb_stop, .disas_log =3D nios2_tr_disas_log, diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 059da48475..d6ea536744 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1609,22 +1609,6 @@ static void openrisc_tr_insn_start(DisasContextBase = *dcbase, CPUState *cs) | (dc->base.num_insns > 1 ? 2 : 0)); } =20 -static bool openrisc_tr_breakpoint_check(DisasContextBase *dcbase, CPUStat= e *cs, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); - gen_exception(dc, EXCP_DEBUG); - dc->base.is_jmp =3D DISAS_NORETURN; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next +=3D 4; - return true; -} - static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState = *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -1727,7 +1711,6 @@ static const TranslatorOps openrisc_tr_ops =3D { .init_disas_context =3D openrisc_tr_init_disas_context, .tb_start =3D openrisc_tr_tb_start, .insn_start =3D openrisc_tr_insn_start, - .breakpoint_check =3D openrisc_tr_breakpoint_check, .translate_insn =3D openrisc_tr_translate_insn, .tb_stop =3D openrisc_tr_tb_stop, .disas_log =3D openrisc_tr_disas_log, diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0a55cb7181..171b216e17 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -8565,23 +8565,6 @@ static void ppc_tr_insn_start(DisasContextBase *dcba= se, CPUState *cs) tcg_gen_insn_start(dcbase->pc_next); } =20 -static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - gen_update_nip(ctx, ctx->base.pc_next); - gen_debug_exception(ctx); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be properly - * cleared -- thus we increment the PC here so that the logic - * setting tb->size below does the right thing. - */ - ctx->base.pc_next +=3D 4; - return true; -} - static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) { REQUIRE_INSNS_FLAGS2(ctx, ISA310); @@ -8710,7 +8693,6 @@ static const TranslatorOps ppc_tr_ops =3D { .init_disas_context =3D ppc_tr_init_disas_context, .tb_start =3D ppc_tr_tb_start, .insn_start =3D ppc_tr_insn_start, - .breakpoint_check =3D ppc_tr_breakpoint_check, .translate_insn =3D ppc_tr_translate_insn, .tb_stop =3D ppc_tr_tb_stop, .disas_log =3D ppc_tr_disas_log, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index deda0c8a44..6983be5723 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -961,22 +961,6 @@ static void riscv_tr_insn_start(DisasContextBase *dcba= se, CPUState *cpu) tcg_gen_insn_start(ctx->base.pc_next); } =20 -static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *= cpu, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - ctx->base.is_jmp =3D DISAS_NORETURN; - gen_exception_debug(); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx->base.pc_next +=3D 4; - return true; -} - static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); @@ -1029,7 +1013,6 @@ static const TranslatorOps riscv_tr_ops =3D { .init_disas_context =3D riscv_tr_init_disas_context, .tb_start =3D riscv_tr_tb_start, .insn_start =3D riscv_tr_insn_start, - .breakpoint_check =3D riscv_tr_breakpoint_check, .translate_insn =3D riscv_tr_translate_insn, .tb_stop =3D riscv_tr_tb_stop, .disas_log =3D riscv_tr_disas_log, diff --git a/target/rx/translate.c b/target/rx/translate.c index 23a626438a..a3cf720455 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2309,19 +2309,6 @@ static void rx_tr_insn_start(DisasContextBase *dcbas= e, CPUState *cs) tcg_gen_insn_start(ctx->base.pc_next); } =20 -static bool rx_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - /* We have hit a breakpoint - make sure PC is up-to-date */ - tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); - gen_helper_debug(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - ctx->base.pc_next +=3D 1; - return true; -} - static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); @@ -2373,7 +2360,6 @@ static const TranslatorOps rx_tr_ops =3D { .init_disas_context =3D rx_tr_init_disas_context, .tb_start =3D rx_tr_tb_start, .insn_start =3D rx_tr_insn_start, - .breakpoint_check =3D rx_tr_breakpoint_check, .translate_insn =3D rx_tr_translate_insn, .tb_stop =3D rx_tr_tb_stop, .disas_log =3D rx_tr_disas_log, diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 92fa7656c2..0632b0374b 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6552,29 +6552,6 @@ static void s390x_tr_insn_start(DisasContextBase *dc= base, CPUState *cs) { } =20 -static bool s390x_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *= cs, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - /* - * Emit an insn_start to accompany the breakpoint exception. - * The ILEN value is a dummy, since this does not result in - * an s390x exception, but an internal qemu exception which - * brings us back to interact with the gdbstub. - */ - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 2); - - dc->base.is_jmp =3D DISAS_PC_STALE; - dc->do_debug =3D true; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size does the right thing. */ - dc->base.pc_next +=3D 2; - return true; -} - static void s390x_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { CPUS390XState *env =3D cs->env_ptr; @@ -6642,7 +6619,6 @@ static const TranslatorOps s390x_tr_ops =3D { .init_disas_context =3D s390x_tr_init_disas_context, .tb_start =3D s390x_tr_tb_start, .insn_start =3D s390x_tr_insn_start, - .breakpoint_check =3D s390x_tr_breakpoint_check, .translate_insn =3D s390x_tr_translate_insn, .tb_stop =3D s390x_tr_tb_stop, .disas_log =3D s390x_tr_disas_log, diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 40898e2393..8704fea1ca 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2289,23 +2289,6 @@ static void sh4_tr_insn_start(DisasContextBase *dcba= se, CPUState *cs) tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags); } =20 -static bool sh4_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - /* We have hit a breakpoint - make sure PC is up-to-date */ - gen_save_cpu_state(ctx, true); - gen_helper_debug(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx->base.pc_next +=3D 2; - return true; -} - static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { CPUSH4State *env =3D cs->env_ptr; @@ -2369,7 +2352,6 @@ static const TranslatorOps sh4_tr_ops =3D { .init_disas_context =3D sh4_tr_init_disas_context, .tb_start =3D sh4_tr_tb_start, .insn_start =3D sh4_tr_insn_start, - .breakpoint_check =3D sh4_tr_breakpoint_check, .translate_insn =3D sh4_tr_translate_insn, .tb_stop =3D sh4_tr_tb_stop, .disas_log =3D sh4_tr_disas_log, diff --git a/target/sparc/translate.c b/target/sparc/translate.c index e530cb4aa8..11de5a4963 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5854,22 +5854,6 @@ static void sparc_tr_insn_start(DisasContextBase *dc= base, CPUState *cs) } } =20 -static bool sparc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *= cs, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - if (dc->pc !=3D dc->base.pc_first) { - save_state(dc); - } - gen_helper_debug(cpu_env); - tcg_gen_exit_tb(NULL, 0); - dc->base.is_jmp =3D DISAS_NORETURN; - /* update pc_next so that the current instruction is included in tb->s= ize */ - dc->base.pc_next +=3D 4; - return true; -} - static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -5932,7 +5916,6 @@ static const TranslatorOps sparc_tr_ops =3D { .init_disas_context =3D sparc_tr_init_disas_context, .tb_start =3D sparc_tr_tb_start, .insn_start =3D sparc_tr_insn_start, - .breakpoint_check =3D sparc_tr_breakpoint_check, .translate_insn =3D sparc_tr_translate_insn, .tb_stop =3D sparc_tr_tb_stop, .disas_log =3D sparc_tr_disas_log, diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 865020754d..a0cc0f1cb3 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8810,21 +8810,6 @@ static void tricore_tr_insn_start(DisasContextBase *= dcbase, CPUState *cpu) tcg_gen_insn_start(ctx->base.pc_next); } =20 -static bool tricore_tr_breakpoint_check(DisasContextBase *dcbase, CPUState= *cpu, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - generate_qemu_excp(ctx, EXCP_DEBUG); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - ctx->base.pc_next +=3D 4; - return true; -} - static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx) { /* @@ -8898,7 +8883,6 @@ static const TranslatorOps tricore_tr_ops =3D { .init_disas_context =3D tricore_tr_init_disas_context, .tb_start =3D tricore_tr_tb_start, .insn_start =3D tricore_tr_insn_start, - .breakpoint_check =3D tricore_tr_breakpoint_check, .translate_insn =3D tricore_tr_translate_insn, .tb_stop =3D tricore_tr_tb_stop, .disas_log =3D tricore_tr_disas_log, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 7094cfcf1d..20399d6a04 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1232,22 +1232,6 @@ static void xtensa_tr_insn_start(DisasContextBase *d= cbase, CPUState *cpu) tcg_gen_insn_start(dcbase->pc_next); } =20 -static bool xtensa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState = *cpu, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); - gen_exception(dc, EXCP_DEBUG); - dc->base.is_jmp =3D DISAS_NORETURN; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next +=3D 2; - return true; -} - static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *c= pu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -1330,7 +1314,6 @@ static const TranslatorOps xtensa_translator_ops =3D { .init_disas_context =3D xtensa_tr_init_disas_context, .tb_start =3D xtensa_tr_tb_start, .insn_start =3D xtensa_tr_insn_start, - .breakpoint_check =3D xtensa_tr_breakpoint_check, .translate_insn =3D xtensa_tr_translate_insn, .tb_stop =3D xtensa_tr_tb_stop, .disas_log =3D xtensa_tr_disas_log, --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626898715090667.1279461521026; Wed, 21 Jul 2021 13:18:35 -0700 (PDT) Received: from localhost ([::1]:41872 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6Ifq-0002Um-1W for importer@patchew.org; Wed, 21 Jul 2021 16:18:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36904) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IOT-00031l-29 for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:38 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:43531) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IOP-00063H-Te for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:36 -0400 Received: by mail-pl1-x634.google.com with SMTP id b12so1632118plh.10 for ; Wed, 21 Jul 2021 13:00:33 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uv4KyE46xKGLObtihhZF89wcjkrGbag40+YXKQhFASw=; b=BIMXz1jcOrQdmm20Z+9NcGCm1SFpdh7U9wkW2CnrQqbc78BmY9FG3wBhOEkRhJGgT6 9MjLZB71afSqzl4D8Hufbfq3Av9WV7R7ilWicDrKNJXiJ6cJW5yhSLL45FYq/oO+Sxm3 vwagNiWMLicR4cfg3rHeLido0HKzRi+z1Dx/bbo7SjFCE7Yj5kEz+31fc/EgZRf05Gv4 oh0lMOknlu+0H2DaefTLwnIDLs2F8oNWcHuIRyWlXnRCzwucW7Iz86kHmQVUTopA+Tkt rdAIxHYt4nAtMnN3LjsF9kj5G86pGlZ4lohsLz7SlYBdBoIasmBNmKhv8KsVKEzwphFB O1Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uv4KyE46xKGLObtihhZF89wcjkrGbag40+YXKQhFASw=; b=JdxvxI5QPtIycFXDh5sC7Zd1iFzJ71z+SXXnxEQidxMUGFvhMjItSbAsK+OhKHrNhS gB7txJ+Ci/zWON+eS2iQcOU6toPq1jlCYk20CY5T/ePObdzbZQvOgtMato3VeB7HCzou V+4zHKbv7sIToX8Bx09gu3WcDuMzgsLWCCCxzFd6s6BEGAc3sJC5z7JU4jEjHJgg2ZHJ iBUIWVSg69QXuDeAUGh84vHU3sFoIOEQ2A697Hz0WUH0ZUzkKRi/Zo/Oirwyep3kzTJB o/vLmmPYkuSdedBEgAkbNtkHjz5axAmfgpNZwAbRM0tQfi2bc+MFsK8OhD67IcYSDVML Hkpw== X-Gm-Message-State: AOAM533qW8fwo20vbTGsg5HCK/mvj/DUiKOpMLr8xEXCmyTKSEIe+sZ8 c6EzOTkhFuUtoBK52vg2lpOhGK9LpIGJRw== X-Google-Smtp-Source: ABdhPJxTPjEqg9yJZXijPcq654r0jv5ndtg2PNpBgEVHnXc97nWNUW898X95Y2RfD0W+zYST4v09Ow== X-Received: by 2002:a17:902:c215:b029:12b:25f7:9b11 with SMTP id 21-20020a170902c215b029012b25f79b11mr28920379pll.82.1626897632527; Wed, 21 Jul 2021 13:00:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 26/27] accel/tcg: Hoist tb_cflags to a local in translator_loop Date: Wed, 21 Jul 2021 09:59:53 -1000 Message-Id: <20210721195954.879535-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , peter.maydell@linaro.org, Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626898715585100001 The access internal to tb_cflags() is atomic. Avoid re-reading it as such for the multiple uses. Tested-by: Mark Cave-Ayland Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- accel/tcg/translator.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 4f3728c278..b45337f3ba 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -50,6 +50,7 @@ bool translator_use_goto_tb(DisasContextBase *db, target_= ulong dest) void translator_loop(const TranslatorOps *ops, DisasContextBase *db, CPUState *cpu, TranslationBlock *tb, int max_insns) { + uint32_t cflags =3D tb_cflags(tb); bool plugin_enabled; =20 /* Initialize DisasContext */ @@ -72,8 +73,7 @@ void translator_loop(const TranslatorOps *ops, DisasConte= xtBase *db, ops->tb_start(db, cpu); tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ =20 - plugin_enabled =3D plugin_gen_tb_start(cpu, tb, - tb_cflags(db->tb) & CF_MEMI_ONLY); + plugin_enabled =3D plugin_gen_tb_start(cpu, tb, cflags & CF_MEMI_ONLY); =20 while (true) { db->num_insns++; @@ -88,14 +88,13 @@ void translator_loop(const TranslatorOps *ops, DisasCon= textBase *db, update db->pc_next and db->is_jmp to indicate what should be done next -- either exiting this loop or locate the start of the next instruction. */ - if (db->num_insns =3D=3D db->max_insns - && (tb_cflags(db->tb) & CF_LAST_IO)) { + if (db->num_insns =3D=3D db->max_insns && (cflags & CF_LAST_IO)) { /* Accept I/O on the last instruction. */ gen_io_start(); ops->translate_insn(db, cpu); } else { /* we should only see CF_MEMI_ONLY for io_recompile */ - tcg_debug_assert(!(tb_cflags(db->tb) & CF_MEMI_ONLY)); + tcg_debug_assert(!(cflags & CF_MEMI_ONLY)); ops->translate_insn(db, cpu); } =20 --=20 2.25.1 From nobody Sat May 18 21:00:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626899041638347.1169562066011; Wed, 21 Jul 2021 13:24:01 -0700 (PDT) Received: from localhost ([::1]:58514 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m6Il6-0005Uz-Ie for importer@patchew.org; Wed, 21 Jul 2021 16:24:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36916) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m6IOU-00032K-VJ for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:38 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:39773) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m6IOS-00064W-PR for qemu-devel@nongnu.org; Wed, 21 Jul 2021 16:00:38 -0400 Received: by mail-pj1-x1034.google.com with SMTP id k4-20020a17090a5144b02901731c776526so511643pjm.4 for ; Wed, 21 Jul 2021 13:00:34 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id w3sm706028pjq.12.2021.07.21.13.00.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jul 2021 13:00:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zLV+SXNQp2xsmnQvSIHnLL5fnwmzEtBufgQQMvoXHhI=; b=MKR0GHW3cCfINzRj//sWpgHum4HwVXclWQJmeP10RFM0vTbyTDsWTqui44YMIToM61 ZOp+z1yiGGVzXp4tLNv3cBUhNGYBjTvT7CkI5cp/+g55/JTpXS4EFXCoEIkeSImQskmw qI7FTzk6VGK26B64kDmqNzvXPPa00cUXMdmyW0dEo9YBBtWss+DM8LMrQob2VMw6n/v/ ajKSOO5wNo4wdjpjwQg0H02qL7l5ThTApSeuFLbJeQ1uX9iWOZ4netKTqB/IR84xp1xw AHAkEiaL3rKXJPQCE8GkaxZUcUGN3vbXdgNJoZr91/XXUrESqpb8sVBq/ujXjlxVr+sx cbUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zLV+SXNQp2xsmnQvSIHnLL5fnwmzEtBufgQQMvoXHhI=; b=Ok1qWb7CB5BYI3ZsCo37yo6TSYc3rdGc6RBSz6McIjeDrKXBLlXdINByccqfRekwhS ZofmCi47dCEzQz2k3VABzVXB7WIsQEA3Y7PDWpKPl41fpElhgQKil0IRvCD2NxlcR2u5 A1tf6Rj/UjcJO7FiJhRBBMLXxsJYf8dMj4bat7rh1MGgukWt655l7Dyu+DZaCOTO8X4p Goe0XFRswHLp1HjrPvxPTt/R1uKTZCOyL0iF2JE6wwunZO8sU7Pjnzluxcm7txjSzPjG CsJepL5HJ0f30F2mQ5GXlB4hsK7OkHASAIgyNVxwqf9MNe24by28Gsd98/ltReAwudKo OL/Q== X-Gm-Message-State: AOAM5334ZnMvYzEQQ1Nm7ULzYlqVp6JS6lcR4E/xU2tMCI4sE35C6T2C Rzk2p426DzJ3rslQt0FbTk/KMSDY3d3Peg== X-Google-Smtp-Source: ABdhPJxUu8wpe6VSQwPQMdt7/LqO2o0XwyzgKEUFIMSAxu5zhYr/q99y9BBiiSnuUw9B6QrYVJZw0g== X-Received: by 2002:a63:cf0a:: with SMTP id j10mr2819695pgg.4.1626897633994; Wed, 21 Jul 2021 13:00:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 27/27] accel/tcg: Record singlestep_enabled in tb->cflags Date: Wed, 21 Jul 2021 09:59:54 -1000 Message-Id: <20210721195954.879535-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210721195954.879535-1-richard.henderson@linaro.org> References: <20210721195954.879535-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , peter.maydell@linaro.org, Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626899043407100001 Set CF_SINGLE_STEP when single-stepping is enabled. This avoids the need to flush all tb's when turning single-stepping on or off. Tested-by: Mark Cave-Ayland Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 1 + accel/tcg/cpu-exec.c | 7 ++++++- accel/tcg/translate-all.c | 4 ---- accel/tcg/translator.c | 7 +------ cpu.c | 4 ---- 5 files changed, 8 insertions(+), 15 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 6873cce8df..5d1b6d80fb 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -497,6 +497,7 @@ struct TranslationBlock { #define CF_COUNT_MASK 0x000001ff #define CF_NO_GOTO_TB 0x00000200 /* Do not chain with goto_tb */ #define CF_NO_GOTO_PTR 0x00000400 /* Do not chain with goto_ptr */ +#define CF_SINGLE_STEP 0x00000800 /* gdbstub single-step in effect */ #define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ #define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ #define CF_USE_ICOUNT 0x00020000 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5cc6363f4c..fc895cf51e 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -150,10 +150,15 @@ uint32_t curr_cflags(CPUState *cpu) uint32_t cflags =3D cpu->tcg_cflags; =20 /* + * Record gdb single-step. We should be exiting the TB by raising + * EXCP_DEBUG, but to simplify other tests, disable chaining too. + * * For singlestep and -d nochain, suppress goto_tb so that * we can log -d cpu,exec after every TB. */ - if (singlestep) { + if (unlikely(cpu->singlestep_enabled)) { + cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR | CF_SINGLE_STEP | 1; + } else if (singlestep) { cflags |=3D CF_NO_GOTO_TB | 1; } else if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { cflags |=3D CF_NO_GOTO_TB; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bf82c15aab..bbfcfb698c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1432,10 +1432,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } QEMU_BUILD_BUG_ON(CF_COUNT_MASK + 1 !=3D TCG_MAX_INSNS); =20 - if (cpu->singlestep_enabled) { - max_insns =3D 1; - } - buffer_overflow: tb =3D tcg_tb_alloc(tcg_ctx); if (unlikely(!tb)) { diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index b45337f3ba..c53a7f8e44 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -38,11 +38,6 @@ bool translator_use_goto_tb(DisasContextBase *db, target= _ulong dest) return false; } =20 - /* Suppress goto_tb in the case of single-steping. */ - if (db->singlestep_enabled) { - return false; - } - /* Check for the dest on the same page as the start of the TB. */ return ((db->pc_first ^ dest) & TARGET_PAGE_MASK) =3D=3D 0; } @@ -60,7 +55,7 @@ void translator_loop(const TranslatorOps *ops, DisasConte= xtBase *db, db->is_jmp =3D DISAS_NEXT; db->num_insns =3D 0; db->max_insns =3D max_insns; - db->singlestep_enabled =3D cpu->singlestep_enabled; + db->singlestep_enabled =3D cflags & CF_SINGLE_STEP; =20 ops->init_disas_context(db, cpu); tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ diff --git a/cpu.c b/cpu.c index d6ae5ae581..e1799a15bc 100644 --- a/cpu.c +++ b/cpu.c @@ -326,10 +326,6 @@ void cpu_single_step(CPUState *cpu, int enabled) cpu->singlestep_enabled =3D enabled; if (kvm_enabled()) { kvm_update_guest_debug(cpu, 0); - } else { - /* must flush all the translated code to avoid inconsistencies= */ - /* XXX: only flush what is necessary */ - tb_flush(cpu); } trace_breakpoint_singlestep(cpu->cpu_index, enabled); } --=20 2.25.1