From nobody Mon Feb 9 03:12:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626854073154680.7782859637557; Wed, 21 Jul 2021 00:54:33 -0700 (PDT) Received: from localhost ([::1]:37678 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m673n-0001ew-OA for importer@patchew.org; Wed, 21 Jul 2021 03:54:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52996) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m66yM-0006qJ-EW; Wed, 21 Jul 2021 03:48:54 -0400 Received: from new2-smtp.messagingengine.com ([66.111.4.224]:58385) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m66yK-0002QZ-KS; Wed, 21 Jul 2021 03:48:54 -0400 Received: from compute2.internal (compute2.nyi.internal [10.202.2.42]) by mailnew.nyi.internal (Postfix) with ESMTP id DE6515816F0; Wed, 21 Jul 2021 03:48:51 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute2.internal (MEProxy); Wed, 21 Jul 2021 03:48:51 -0400 Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 21 Jul 2021 03:48:49 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irrelevant.dk; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=fm3; bh= 69JPLYSnFZhAufymlT12ftm0OEpfY9b/EpDsh51XTk0=; b=jmwQP/QZFs0lJrrz +4b0QkdSEjC4Qf8Dj9C8TvTa9jjrlOxT6EgEuuhhHekOR/QShOJltaG+I7gKDcqQ fM44Fw7NatJXJqqNeswngxDEWpGG7qhmP5YhT35ncwjyQvPWXUL1v5vv130j/M/q ZXGTNe5ALuDblwreXGS/BCq90GmGyNgEG8CfKuwF3IRTgkSDFtYmDbOeFi2Ysdf2 GS9Nv+qaoK1JkRzG8MxUqkRIDpEja7onMDqdL5qlNx2lJ/MvktywDMwD5dhi8qbL vz8FlW/EO3N2vy+V9E7euM32O4hueIQmSWrzOtPtpDUfDKrHLgUwlAP0pWBhAeB+ vt4HYA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm3; bh=69JPLYSnFZhAufymlT12ftm0OEpfY9b/EpDsh51XT k0=; b=iah0JV3auNlDh1lfdwQ1+xWzJZh5id09QzKXTNc9piORhaqfN4VdGZgcw vQdtBH4hyIeWi6uDcEXBAScRUaB2oUqQL+EtD/4Mj6opPaXgJH13gVqVSwwjL8/t +WTvNQLPpStxi578Rc2DvDTtHWSxGioxM+okb2C+t7nry/iop2ZGpV8OS7gFomkv R/zjHb0s9H3kkoaRy/zQJQxucveLrrAcKfYGllQOKTg8Z0+LOsv5ee4212/V0igp faADnHSJBt3FgrCLmoSIkIii48yGNHbvVMO63V2+IuWwzMiqCanRs2EiJY6AI9H/ A61iySOVQsTbmLSqFIWkBaIZUgb6A== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrfeefgdduudegucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepmfhlrghu shculfgvnhhsvghnuceoihhtshesihhrrhgvlhgvvhgrnhhtrdgukheqnecuggftrfgrth htvghrnhepteevuedugeevieehgeeileeufeetvddtkeetfeelgeehudfhjeeuledvhfff tdegnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomhepih htshesihhrrhgvlhgvvhgrnhhtrdgukh X-ME-Proxy: From: Klaus Jensen To: qemu-devel@nongnu.org Subject: [PATCH v6 2/5] hw/nvme: use symbolic names for registers Date: Wed, 21 Jul 2021 09:48:33 +0200 Message-Id: <20210721074836.110232-3-its@irrelevant.dk> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210721074836.110232-1-its@irrelevant.dk> References: <20210721074836.110232-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=66.111.4.224; envelope-from=its@irrelevant.dk; helo=new2-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Thomas Huth , qemu-block@nongnu.org, Klaus Jensen , Gollu Appalanaidu , Max Reitz , Klaus Jensen , Stefan Hajnoczi , Keith Busch , Paolo Bonzini , Fam Zheng , Kevin Wolf , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1626854075169100001 From: Klaus Jensen Add the NvmeBarRegs enum and use these instead of explicit register offsets. Signed-off-by: Klaus Jensen Reviewed-by: Gollu Appalanaidu Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Keith Busch --- include/block/nvme.h | 29 ++++++++++++++++++++++++++++- hw/nvme/ctrl.c | 44 ++++++++++++++++++++++---------------------- 2 files changed, 50 insertions(+), 23 deletions(-) diff --git a/include/block/nvme.h b/include/block/nvme.h index 84053b68b987..77aae0117494 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -9,7 +9,7 @@ typedef struct QEMU_PACKED NvmeBar { uint32_t cc; uint8_t rsvd24[4]; uint32_t csts; - uint32_t nssrc; + uint32_t nssr; uint32_t aqa; uint64_t asq; uint64_t acq; @@ -31,6 +31,33 @@ typedef struct QEMU_PACKED NvmeBar { uint8_t css[484]; } NvmeBar; =20 +enum NvmeBarRegs { + NVME_REG_CAP =3D offsetof(NvmeBar, cap), + NVME_REG_VS =3D offsetof(NvmeBar, vs), + NVME_REG_INTMS =3D offsetof(NvmeBar, intms), + NVME_REG_INTMC =3D offsetof(NvmeBar, intmc), + NVME_REG_CC =3D offsetof(NvmeBar, cc), + NVME_REG_CSTS =3D offsetof(NvmeBar, csts), + NVME_REG_NSSR =3D offsetof(NvmeBar, nssr), + NVME_REG_AQA =3D offsetof(NvmeBar, aqa), + NVME_REG_ASQ =3D offsetof(NvmeBar, asq), + NVME_REG_ACQ =3D offsetof(NvmeBar, acq), + NVME_REG_CMBLOC =3D offsetof(NvmeBar, cmbloc), + NVME_REG_CMBSZ =3D offsetof(NvmeBar, cmbsz), + NVME_REG_BPINFO =3D offsetof(NvmeBar, bpinfo), + NVME_REG_BPRSEL =3D offsetof(NvmeBar, bprsel), + NVME_REG_BPMBL =3D offsetof(NvmeBar, bpmbl), + NVME_REG_CMBMSC =3D offsetof(NvmeBar, cmbmsc), + NVME_REG_CMBSTS =3D offsetof(NvmeBar, cmbsts), + NVME_REG_PMRCAP =3D offsetof(NvmeBar, pmrcap), + NVME_REG_PMRCTL =3D offsetof(NvmeBar, pmrctl), + NVME_REG_PMRSTS =3D offsetof(NvmeBar, pmrsts), + NVME_REG_PMREBS =3D offsetof(NvmeBar, pmrebs), + NVME_REG_PMRSWTP =3D offsetof(NvmeBar, pmrswtp), + NVME_REG_PMRMSCL =3D offsetof(NvmeBar, pmrmscl), + NVME_REG_PMRMSCU =3D offsetof(NvmeBar, pmrmscu), +}; + enum NvmeCapShift { CAP_MQES_SHIFT =3D 0, CAP_CQR_SHIFT =3D 16, diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 070d9f6a962d..23ff71f65c0e 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -5740,7 +5740,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset= , uint64_t data, } =20 switch (offset) { - case 0xc: /* INTMS */ + case NVME_REG_INTMS: if (unlikely(msix_enabled(&(n->parent_obj)))) { NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix, "undefined access to interrupt mask set" @@ -5752,7 +5752,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset= , uint64_t data, trace_pci_nvme_mmio_intm_set(data & 0xffffffff, n->bar.intmc); nvme_irq_check(n); break; - case 0x10: /* INTMC */ + case NVME_REG_INTMC: if (unlikely(msix_enabled(&(n->parent_obj)))) { NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix, "undefined access to interrupt mask clr" @@ -5764,7 +5764,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset= , uint64_t data, trace_pci_nvme_mmio_intm_clr(data & 0xffffffff, n->bar.intmc); nvme_irq_check(n); break; - case 0x14: /* CC */ + case NVME_REG_CC: trace_pci_nvme_mmio_cfg(data & 0xffffffff); /* Windows first sends data, then sends enable bit */ if (!NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc) && @@ -5798,7 +5798,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset= , uint64_t data, n->bar.cc =3D data; } break; - case 0x1c: /* CSTS */ + case NVME_REG_CSTS: if (data & (1 << 4)) { NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ssreset_w1c_unsupported, "attempted to W1C CSTS.NSSRO" @@ -5809,7 +5809,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset= , uint64_t data, " of controller status"); } break; - case 0x20: /* NSSR */ + case NVME_REG_NSSR: if (data =3D=3D 0x4e564d65) { trace_pci_nvme_ub_mmiowr_ssreset_unsupported(); } else { @@ -5817,38 +5817,38 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offs= et, uint64_t data, return; } break; - case 0x24: /* AQA */ + case NVME_REG_AQA: n->bar.aqa =3D data & 0xffffffff; trace_pci_nvme_mmio_aqattr(data & 0xffffffff); break; - case 0x28: /* ASQ */ + case NVME_REG_ASQ: n->bar.asq =3D size =3D=3D 8 ? data : (n->bar.asq & ~0xffffffffULL) | (data & 0xffffffff); trace_pci_nvme_mmio_asqaddr(data); break; - case 0x2c: /* ASQ hi */ + case NVME_REG_ASQ + 4: n->bar.asq =3D (n->bar.asq & 0xffffffff) | (data << 32); trace_pci_nvme_mmio_asqaddr_hi(data, n->bar.asq); break; - case 0x30: /* ACQ */ + case NVME_REG_ACQ: trace_pci_nvme_mmio_acqaddr(data); n->bar.acq =3D size =3D=3D 8 ? data : (n->bar.acq & ~0xffffffffULL) | (data & 0xffffffff); break; - case 0x34: /* ACQ hi */ + case NVME_REG_ACQ + 4: n->bar.acq =3D (n->bar.acq & 0xffffffff) | (data << 32); trace_pci_nvme_mmio_acqaddr_hi(data, n->bar.acq); break; - case 0x38: /* CMBLOC */ + case NVME_REG_CMBLOC: NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbloc_reserved, "invalid write to reserved CMBLOC" " when CMBSZ is zero, ignored"); return; - case 0x3C: /* CMBSZ */ + case NVME_REG_CMBSZ: NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbsz_readonly, "invalid write to read only CMBSZ, ignored"); return; - case 0x50: /* CMBMSC */ + case NVME_REG_CMBMSC: if (!NVME_CAP_CMBS(n->bar.cap)) { return; } @@ -5876,15 +5876,15 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offs= et, uint64_t data, } =20 return; - case 0x54: /* CMBMSC hi */ + case NVME_REG_CMBMSC + 4: n->bar.cmbmsc =3D (n->bar.cmbmsc & 0xffffffff) | (data << 32); return; =20 - case 0xe00: /* PMRCAP */ + case NVME_REG_PMRCAP: NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrcap_readonly, "invalid write to PMRCAP register, ignored"); return; - case 0xe04: /* PMRCTL */ + case NVME_REG_PMRCTL: if (!NVME_CAP_PMRS(n->bar.cap)) { return; } @@ -5899,19 +5899,19 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offs= et, uint64_t data, n->pmr.cmse =3D false; } return; - case 0xe08: /* PMRSTS */ + case NVME_REG_PMRSTS: NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrsts_readonly, "invalid write to PMRSTS register, ignored"); return; - case 0xe0C: /* PMREBS */ + case NVME_REG_PMREBS: NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrebs_readonly, "invalid write to PMREBS register, ignored"); return; - case 0xe10: /* PMRSWTP */ + case NVME_REG_PMRSWTP: NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrswtp_readonly, "invalid write to PMRSWTP register, ignored"); return; - case 0xe14: /* PMRMSCL */ + case NVME_REG_PMRMSCL: if (!NVME_CAP_PMRS(n->bar.cap)) { return; } @@ -5933,7 +5933,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset= , uint64_t data, } =20 return; - case 0xe18: /* PMRMSCU */ + case NVME_REG_PMRMSCU: if (!NVME_CAP_PMRS(n->bar.cap)) { return; } @@ -5975,7 +5975,7 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr a= ddr, unsigned size) * from PMRSTS should ensure prior writes * made it to persistent media */ - if (addr =3D=3D 0xe08 && + if (addr =3D=3D NVME_REG_PMRSTS && (NVME_PMRCAP_PMRWBM(n->bar.pmrcap) & 0x02)) { memory_region_msync(&n->pmr.dev->mr, 0, n->pmr.dev->size); } --=20 2.32.0