From nobody Mon May 13 10:52:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626811038144555.876016226563; Tue, 20 Jul 2021 12:57:18 -0700 (PDT) Received: from localhost ([::1]:48302 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5vrg-0001h9-Aw for importer@patchew.org; Tue, 20 Jul 2021 15:57:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55594) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5vpH-00072I-AZ for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:47 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:39446) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5vpF-0007xA-MT for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:47 -0400 Received: by mail-pl1-x629.google.com with SMTP id h1so11953623plf.6 for ; Tue, 20 Jul 2021 12:54:44 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id j25sm15422179pfh.77.2021.07.20.12.54.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 12:54:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bSI7+FYoYzIRMvsyeEg3j2XXfVWM2GYuNosumX6OIpk=; b=xH8KvVM4SBzXIQA64VMFTBGTkxp3niF5ZYMSbHc6OWQakMGCcvh75plVLvGyImSIWJ QRyWL6hDEfFKYg7kUuKGgXXJNjseDms19D4+LZHp8/GRrn7r/auNMddBxmAM3WyZWwb8 L0qX+rq71k+DDM5DiphHrQFbHtGMv/X5bcUfK1KWSk/EQkxF/KsQw5MXnqn5iGJ6sOog YQAS2Lb1Gr+bUu5ndNInP21G3qyZaGIb8YrWRjiM0NONMK87bsYwAk0EzN43RCkFDwJu e113bZjZ6qKR7taU49aXIginKHylF6Y41fv/0RWnl3XnF9gBzGfK8/6+CUY+rroN9EK/ d4Wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bSI7+FYoYzIRMvsyeEg3j2XXfVWM2GYuNosumX6OIpk=; b=A8oqBk6U4YoC36SC1Q5CA4kSB10w5canFh1U3edbqtBvjj95R2jikKoLLp5dYlZ1/x MlGxVQz4G3qA80S420xPj8BiCZqSWfxoClDD8ltAe8yBTFaaXnYvgPb8KDDvPsfxv3T3 3JTRKNfxQpTiqZaPP9RYKXGCBWAeY2kesY9cKux8AymhAskgokx9qnRdjKIYuCr4m07R XMREr1hqLAVZ+EdU5k8amb5rETg1JlgoXR1526jCVFshSM0nUYnnk/2ZqotERU6s0FlP 2KiFUOMsySiOXTQhppWhGE1sdNvzGxueMvFKQJXR9mcELKy1RCpFEZ9PdhU+F2aWYLxM yh5w== X-Gm-Message-State: AOAM5306KBMqdZdMm50eGd+qa36/WL54nCBhPNDQn2Brqg3rwm1Lpm3w LnPcvmHqKgaNvSUerWTz/SJ0rJuHaF9XUw== X-Google-Smtp-Source: ABdhPJwPEkpRcM8XVRuviuVeNXKLNQgl/Z4nq8sLXmXiRzzIRuYua91fKL6L2GA/QbngIun74VsNeQ== X-Received: by 2002:a17:903:186:b029:12b:8d80:5d78 with SMTP id z6-20020a1709030186b029012b8d805d78mr8386833plg.17.1626810883985; Tue, 20 Jul 2021 12:54:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v6 01/17] accel/tcg: Reduce CF_COUNT_MASK to match TCG_MAX_INSNS Date: Tue, 20 Jul 2021 09:54:23 -1000 Message-Id: <20210720195439.626594-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720195439.626594-1-richard.henderson@linaro.org> References: <20210720195439.626594-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626811038979100001 The space reserved for CF_COUNT_MASK was overly large. Reduce to free up cflags bits and eliminate an extra test. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Message-Id: <20210717221851.2124573-2-richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland --- include/exec/exec-all.h | 4 +++- accel/tcg/translate-all.c | 5 ++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 754f4130c9..dfe82ed19c 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -492,7 +492,9 @@ struct TranslationBlock { target_ulong cs_base; /* CS base for this block */ uint32_t flags; /* flags defining in which context the code was genera= ted */ uint32_t cflags; /* compile flags */ -#define CF_COUNT_MASK 0x00007fff + +/* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */ +#define CF_COUNT_MASK 0x000001ff #define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ #define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ #define CF_USE_ICOUNT 0x00020000 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 4df26de858..5cc01d693b 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1428,11 +1428,10 @@ TranslationBlock *tb_gen_code(CPUState *cpu, =20 max_insns =3D cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { max_insns =3D TCG_MAX_INSNS; } + QEMU_BUILD_BUG_ON(CF_COUNT_MASK + 1 !=3D TCG_MAX_INSNS); + if (cpu->singlestep_enabled || singlestep) { max_insns =3D 1; } --=20 2.25.1 From nobody Mon May 13 10:52:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626811305226779.6492483993894; Tue, 20 Jul 2021 13:01:45 -0700 (PDT) Received: from localhost ([::1]:59872 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5vw0-0001Kb-44 for importer@patchew.org; Tue, 20 Jul 2021 16:01:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55622) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5vpI-00074e-Gh for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:48 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:33589) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5vpG-0007xI-Ke for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:48 -0400 Received: by mail-pj1-x1034.google.com with SMTP id v18-20020a17090ac912b0290173b9578f1cso2428215pjt.0 for ; Tue, 20 Jul 2021 12:54:46 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id j25sm15422179pfh.77.2021.07.20.12.54.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 12:54:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f8NOqQ/0TvCdkNluzWUj4pUQUbt/7JktmnpikxlNXDw=; b=M8E/XhGGriSeEIT9gObm3UvaTPMbnwEQ6dT02NqBIcA5GWt3fDamkWTkKkgB4njD9V VQlVQelzb4Pr09bFZRjHiW0T8/gwEsPGinj9LNUMz/WeqFmTvmjRmdOVuPNAdx2gBOuD Eay4Vd9QoaZSm7Lsk+9BsJ3sexxw3Xod3hQW567UgtIAIzd3kptEy4icKW3Q1r4v1Vz0 Q7yj/ARfimZINaQJ9JhW5RH4x80wkuq8Q4ExEr+mN+jX1I+0a+MH6yxKgQPRPiIPM0/Q 3kb8h+XIV7KfF6jpPxbjAkFqknxlmIXMzfnR1gdX438gplHkghbqcDo6F9zJySHoplgx zemA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f8NOqQ/0TvCdkNluzWUj4pUQUbt/7JktmnpikxlNXDw=; b=tJ0zii+qnqPG9cWTECM6EAKO4SoYRLHKhCOG5rBz/9YEHuZsThu9i6uV9VTksdhfjs U3INpBk3KhYWwB5LaU/sdxplDyeEcBuAaFR9XANhmjw9OdgEFSZUpRxQSmJaOg3yNCpu fM0Rq+QXK5NLlP92UC14ArvVLFPcDjcewY5IzDzDeImnykh/VTq90iEI7nIf64jttGUw 90p3/Gdx7xDT5tiWPOO5thIkI2pXdRZ5ri+GG4/Ht0W/5rCf93+51qHCdGvm9S9E7R+p Y3wPZeZcMWRRLuYs8c+1HXd82grq8TF9YTCpjdJYMNIygMb6PvlvaOcDDBBL3aHc5iTG Pr6w== X-Gm-Message-State: AOAM532fH1tl6Wh/bizrR0zvmZKFGk91RtSZ8rZHwJOFfWWwhmBWuwhT 7/zSSNhFVqxENW3UIwXBV4smNu4qzS0Bgw== X-Google-Smtp-Source: ABdhPJxOSSULQxJ2pGv3521iqHwL/d0ZjKryzwqcgVgbbfUSFmqHuOb/wBudUbzBztOEC1nvyus3tg== X-Received: by 2002:a17:90a:9b03:: with SMTP id f3mr30158335pjp.184.1626810885286; Tue, 20 Jul 2021 12:54:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v6 02/17] accel/tcg: Move curr_cflags into cpu-exec.c Date: Tue, 20 Jul 2021 09:54:24 -1000 Message-Id: <20210720195439.626594-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720195439.626594-1-richard.henderson@linaro.org> References: <20210720195439.626594-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626811307310100001 We will shortly have more than a simple member read here, with stuff not necessarily exposed to exec/exec-all.h. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210717221851.2124573-3-richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland --- include/exec/exec-all.h | 5 +---- accel/tcg/cpu-exec.c | 5 +++++ 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index dfe82ed19c..ae7603ca75 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -565,10 +565,7 @@ static inline uint32_t tb_cflags(const TranslationBloc= k *tb) } =20 /* current cflags for hashing/comparison */ -static inline uint32_t curr_cflags(CPUState *cpu) -{ - return cpu->tcg_cflags; -} +uint32_t curr_cflags(CPUState *cpu); =20 /* TranslationBlock invalidate API */ #if defined(CONFIG_USER_ONLY) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index e22bcb99f7..ef4214d893 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -145,6 +145,11 @@ static void init_delay_params(SyncClocks *sc, const CP= UState *cpu) } #endif /* CONFIG USER ONLY */ =20 +uint32_t curr_cflags(CPUState *cpu) +{ + return cpu->tcg_cflags; +} + /* Might cause an exception, so have a longjmp destination ready */ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc, target_ulong cs_base, --=20 2.25.1 From nobody Mon May 13 10:52:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626811196581301.47751146085886; Tue, 20 Jul 2021 12:59:56 -0700 (PDT) Received: from localhost ([::1]:56734 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5vuF-0007Vx-Im for importer@patchew.org; Tue, 20 Jul 2021 15:59:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55644) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5vpK-00079T-8w for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:51 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:37691) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5vpH-0007zA-Ru for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:50 -0400 Received: by mail-pl1-x631.google.com with SMTP id y3so7567761plp.4 for ; Tue, 20 Jul 2021 12:54:47 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id j25sm15422179pfh.77.2021.07.20.12.54.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 12:54:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5munM6eZd/uk4n4hD7SHb+ixOouAZHeY9ReXlmZhFgI=; b=gDX6ehLRIo3QZFClUPXppf32wbMUb6HT7Mf0RaYLAgrHkUq/p60ghOWZ2WwY3yUIt+ DO0iBd3ipsxne5JUMpfZORaW0pKKmXVNjJWUFOmrqqKlPkwby7fzTb7xl9F21q51vCQq GL2SBw4TQbbq0JrjVLZRMiGH/qfi84iytCyRcMWPegLOLqwQ7l46hMLkOLqrSs6Q1Aa5 Bqma2g3nW7fERtYjtz3NKpu4Kcl4vwJBdDDZLWGm48iq+GYYqxkS/x/s/pn7CrygkdNj eahS0cOIQ0PBAXGEq4/lAPZrY0UiGyLcw42jn0JjHsYg/43dAVDYu1/SGwEsd0JqjJcP uvpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5munM6eZd/uk4n4hD7SHb+ixOouAZHeY9ReXlmZhFgI=; b=T1T+NJ5WRkDg/PNy9O6IAG4BS5lj4rfV9ZqDUcm2cMsz1xWSG64aDCAshI1R0cdkyQ 3EDvRyBli0tFZ7Wm/wa9Ax87QTzgZ2FNCRcT7jmmNper4TGs5ECfAQR+C5LyIaHc1p4o bubISeInJb9m1AkUah5sjhjzTQSiEDNizv3UEPVlz2TRhFNWdz/U9rhcd7CqKmiJGAVl EdfZeRbEmNzuUuavYcE0x6a7hYS4gelOokSnHRx1Zsng/LY5iADz4nVfEUO/CHsnCQU5 2ZihIqiACG/5hiIQYLo0svxzDQ57BD3aPK7xC7arvZdLUkxEQ98jFy9NHBmoLtI+wA7o bt9A== X-Gm-Message-State: AOAM532JUIO3BDAwLcGIuzAlLBOpY0ef11Z1hgVCYcy1vWInJ1tAPGxS 84ytdLnmqDC7+G8TLqhO9HVtmCuQxvQiGg== X-Google-Smtp-Source: ABdhPJwlNNZ/eNISC4ms7tMU4vhsbPRtVxA4IAO8YkSehlXsv8kZD5/NqsiyZ6x0L1xlY/JoilJZbg== X-Received: by 2002:a17:902:ecce:b029:12b:374:c15f with SMTP id a14-20020a170902ecceb029012b0374c15fmr24812552plh.22.1626810886600; Tue, 20 Jul 2021 12:54:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v6 03/17] target/alpha: Drop goto_tb path in gen_call_pal Date: Tue, 20 Jul 2021 09:54:25 -1000 Message-Id: <20210720195439.626594-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720195439.626594-1-richard.henderson@linaro.org> References: <20210720195439.626594-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626811197354100001 We are certain of a page crossing here, entering the PALcode image, so the call to use_goto_tb that should have been here will never succeed. We are shortly going to add an assert to tcg_gen_goto_tb that would trigger for this case. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/alpha/translate.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 103c6326a2..949ba6ffde 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -1207,19 +1207,8 @@ static DisasJumpType gen_call_pal(DisasContext *ctx,= int palcode) ? 0x2000 + (palcode - 0x80) * 64 : 0x1000 + palcode * 64); =20 - /* Since the destination is running in PALmode, we don't really - need the page permissions check. We'll see the existence of - the page when we create the TB, and we'll flush all TBs if - we change the PAL base register. */ - if (!ctx->base.singlestep_enabled) { - tcg_gen_goto_tb(0); - tcg_gen_movi_i64(cpu_pc, entry); - tcg_gen_exit_tb(ctx->base.tb, 0); - return DISAS_NORETURN; - } else { - tcg_gen_movi_i64(cpu_pc, entry); - return DISAS_PC_UPDATED; - } + tcg_gen_movi_i64(cpu_pc, entry); + return DISAS_PC_UPDATED; } #endif } --=20 2.25.1 From nobody Mon May 13 10:52:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626811526165907.2335882265335; Tue, 20 Jul 2021 13:05:26 -0700 (PDT) Received: from localhost ([::1]:40190 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5vzZ-0006zE-4e for importer@patchew.org; Tue, 20 Jul 2021 16:05:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55662) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5vpL-00079p-J5 for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:53 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]:36446) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5vpJ-0007zo-8S for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:50 -0400 Received: by mail-pl1-x630.google.com with SMTP id x16so11958675plg.3 for ; Tue, 20 Jul 2021 12:54:48 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id j25sm15422179pfh.77.2021.07.20.12.54.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 12:54:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gKHnw/iTk1V/eUPCZhivd0JB3zDH6dBk+qd11N8EyNM=; b=UYrxUe+nJHTTjqpsYDSnEbAij9ZroSv3izsPCJN8kj0DW9QUfTh7wgikphzauIqjb3 iQ6kAW8+kG0ykSt1/Oq5fTmG0wCq7flFHElUUCeLCqOYZAih0vVz2U6909CRGv3BQCQw j8UQ5NVpQismEzrD/B+7K9eWvZVMzr/0+83vdw3wBJ1QEkmZOQAU3a9snxCwJLCe+twX wme8jw7nCNTYAqE8uY3K9zsjt6RRWHOnoWF6/M9HHC/iG0+RGcDdSQL4F6kTiL1VKezy K5vb24FIJAtjwNU1Tpr/OMhdGS2Kx8Ec6iu2an9/eEVdkhjh/V5cDrS831W3HJOoVEOX 5q/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gKHnw/iTk1V/eUPCZhivd0JB3zDH6dBk+qd11N8EyNM=; b=hzgmVdIMKFTZ6LlebEWEVvP1PYZHgX51jdHUkWVDRJjNKk+xQau9me0bF2yFhYt4Q3 ASNPff7AM9TItv/Qs06zcGPQD2SuxXlWXTwn8CxxLxVyVvOwAN8o57YWQQNXp+fhidTV E+lqZyYkTF/6etzHqhZWgkmwCjnxQWtkVR0Ql+VjHK2Lho6WUHZ1eMGR03M5asGjNlMK G3NPCko8mGmNUGVhT3vqXCJ7PBD+UMar9kmH7cgY/7zjyNVIovASozmmzZ6gBWgHh3OZ leoifhRCmggDog1AQbpS8jnwYVZFlwX3wCYEktPZrmmHKFovwkG/nzSfzRuEo8z8vvw6 2obw== X-Gm-Message-State: AOAM530L1Wk5eGPJWFe9FdZLR+gLGyIf5Najm3kQQjsfrE0NDThTgjcK FuyQw7ARI6WVWBp5S5q+IaZsLx4vVx62Zg== X-Google-Smtp-Source: ABdhPJyCNbGa5nFV8Db/L18WI1CFlqZi4Wftg9A0d/H6tVuRgsiBjZ+yc9Fa2oDX0kfxnDUKxUZH+Q== X-Received: by 2002:a17:902:be17:b029:12b:9b9f:c38d with SMTP id r23-20020a170902be17b029012b9b9fc38dmr3321469pls.41.1626810887921; Tue, 20 Jul 2021 12:54:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v6 04/17] accel/tcg: Add CF_NO_GOTO_TB and CF_NO_GOTO_PTR Date: Tue, 20 Jul 2021 09:54:26 -1000 Message-Id: <20210720195439.626594-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720195439.626594-1-richard.henderson@linaro.org> References: <20210720195439.626594-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626811527711100001 Move the -d nochain check to bits on tb->cflags. These will be used for more than -d nochain shortly. Set bits during curr_cflags, test them in translator_use_goto_tb, assert we're not doing anything odd in tcg_gen_goto_tb. The test in tcg_gen_exit_tb is redundant with the assert for goto_tb_issue_mask. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Message-Id: <20210717221851.2124573-4-richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland --- include/exec/exec-all.h | 16 +++++++++------- accel/tcg/cpu-exec.c | 8 +++++++- accel/tcg/translator.c | 5 +++++ tcg/tcg-op.c | 28 ++++++++++++---------------- 4 files changed, 33 insertions(+), 24 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index ae7603ca75..6873cce8df 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -494,13 +494,15 @@ struct TranslationBlock { uint32_t cflags; /* compile flags */ =20 /* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */ -#define CF_COUNT_MASK 0x000001ff -#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ -#define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ -#define CF_USE_ICOUNT 0x00020000 -#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held = */ -#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context = */ -#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ +#define CF_COUNT_MASK 0x000001ff +#define CF_NO_GOTO_TB 0x00000200 /* Do not chain with goto_tb */ +#define CF_NO_GOTO_PTR 0x00000400 /* Do not chain with goto_ptr */ +#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ +#define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ +#define CF_USE_ICOUNT 0x00020000 +#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock hel= d */ +#define CF_PARALLEL 0x00080000 /* Generate code for a parallel contex= t */ +#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ #define CF_CLUSTER_SHIFT 24 =20 /* Per-vCPU dynamic tracing state used to generate this TB */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ef4214d893..d3232d5764 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -147,7 +147,13 @@ static void init_delay_params(SyncClocks *sc, const CP= UState *cpu) =20 uint32_t curr_cflags(CPUState *cpu) { - return cpu->tcg_cflags; + uint32_t cflags =3D cpu->tcg_cflags; + + if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { + cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR; + } + + return cflags; } =20 /* Might cause an exception, so have a longjmp destination ready */ diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 59804af37b..2ea5a74f30 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -33,6 +33,11 @@ void translator_loop_temp_check(DisasContextBase *db) =20 bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest) { + /* Suppress goto_tb if requested. */ + if (tb_cflags(db->tb) & CF_NO_GOTO_TB) { + return false; + } + /* Suppress goto_tb in the case of single-steping. */ if (db->singlestep_enabled || singlestep) { return false; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 0c561fb253..e0d54d537f 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2723,10 +2723,6 @@ void tcg_gen_exit_tb(const TranslationBlock *tb, uns= igned idx) seen this numbered exit before, via tcg_gen_goto_tb. */ tcg_debug_assert(tcg_ctx->goto_tb_issue_mask & (1 << idx)); #endif - /* When not chaining, exit without indicating a link. */ - if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - val =3D 0; - } } else { /* This is an exit via the exitreq label. */ tcg_debug_assert(idx =3D=3D TB_EXIT_REQUESTED); @@ -2738,6 +2734,8 @@ void tcg_gen_exit_tb(const TranslationBlock *tb, unsi= gned idx) =20 void tcg_gen_goto_tb(unsigned idx) { + /* We tested CF_NO_GOTO_TB in translator_use_goto_tb. */ + tcg_debug_assert(!(tcg_ctx->tb_cflags & CF_NO_GOTO_TB)); /* We only support two chained exits. */ tcg_debug_assert(idx <=3D TB_EXIT_IDXMAX); #ifdef CONFIG_DEBUG_TCG @@ -2746,25 +2744,23 @@ void tcg_gen_goto_tb(unsigned idx) tcg_ctx->goto_tb_issue_mask |=3D 1 << idx; #endif plugin_gen_disable_mem_helpers(); - /* When not chaining, we simply fall through to the "fallback" exit. = */ - if (!qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - tcg_gen_op1i(INDEX_op_goto_tb, idx); - } + tcg_gen_op1i(INDEX_op_goto_tb, idx); } =20 void tcg_gen_lookup_and_goto_ptr(void) { - if (!qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - TCGv_ptr ptr; + TCGv_ptr ptr; =20 - plugin_gen_disable_mem_helpers(); - ptr =3D tcg_temp_new_ptr(); - gen_helper_lookup_tb_ptr(ptr, cpu_env); - tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr)); - tcg_temp_free_ptr(ptr); - } else { + if (tcg_ctx->tb_cflags & CF_NO_GOTO_PTR) { tcg_gen_exit_tb(NULL, 0); + return; } + + plugin_gen_disable_mem_helpers(); + ptr =3D tcg_temp_new_ptr(); + gen_helper_lookup_tb_ptr(ptr, cpu_env); + tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr)); + tcg_temp_free_ptr(ptr); } =20 static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st) --=20 2.25.1 From nobody Mon May 13 10:52:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626811053027311.23896829116893; Tue, 20 Jul 2021 12:57:33 -0700 (PDT) Received: from localhost ([::1]:49610 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5vrw-0002Xy-03 for importer@patchew.org; Tue, 20 Jul 2021 15:57:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55668) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5vpL-0007Af-Ue for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:53 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:44590) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5vpK-00080i-I3 for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:51 -0400 Received: by mail-pf1-x42f.google.com with SMTP id p36so404579pfw.11 for ; Tue, 20 Jul 2021 12:54:50 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id j25sm15422179pfh.77.2021.07.20.12.54.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 12:54:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9B/gmUM+QUz3bpCH+D2gMCTlPL+YqDM4DQGjYBG4u2w=; b=Dg6wlJZXVd2Rij+nGrvg34DUpOEIffGb2a6MJAgNAjeITKaAa1QIqutNGV5IfrnA05 yKb+ohVo8C29jOFE3dXa5BKRRoFyknH5O91PvCdsgBCpY4qK2gQOGGl6nHLRuQPgPQp9 Ye7fzx+0jCnK0+nJ5hDMdrSrviI+CDujJh2kj+anA4l9Z2GwgFOf/n69UzhdWud46oLw gBUdshKO+nKvNsgDYbEei3Ljg/7dAAaXrG5hd6++J9fBiWgVm/NHdLK5hcCkEogonWp9 9BWTMoAm4wyBTt1ALgXOIiCKIlKOKl8I0Ezx+/cxr/8hKS/sTGQAnpwg4xwUaLN4kiL5 AhRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9B/gmUM+QUz3bpCH+D2gMCTlPL+YqDM4DQGjYBG4u2w=; b=huYlaF7pGaVTLia6dt59lBqYlzHJMTySksOdPhWf8ZMJQJ2Uw7zPGQWifr3o0A9/hs 7KnMjKCHu4MdN4xUrAbsv/ntbT5VaAc3ggH4SYDDrBKLsSdn3njxVKatZhrq81ugmDx3 n30fETS9gM/qoa34NmtVs2pTO/ke3bwDTmsWoilmjZ6lXNmmWiLsskTIF4TUFx1GYf2K S9hdQBlc84sBXRoNw+6E2edd6/Xpn+exY45vPHjQDF0GzmGrLzJMFd8L94UOJkCLB9hH HZAiVxXpBmBWwRRo9HykN6GbByRM4nmSVryKO2Kj5KZNKU1o5dmc3f3dT5rvphkZq3vH mEjg== X-Gm-Message-State: AOAM531L1PSBy51bA5ePfjXdfZ1uQl+oTbc/UoWz03/4qZsnd8NxoTaa 9RVNpxTmMzYHYCn7/b/DNXT3Nxxpp+OiyA== X-Google-Smtp-Source: ABdhPJyrRFLA1DhiNKnIr8eQWtRH8F9fY4ryhsVKv6Y5g7MZBlqGEtuIrPAm6GlQPpMjDV+AQ4jF7g== X-Received: by 2002:a63:e947:: with SMTP id q7mr13992826pgj.324.1626810889267; Tue, 20 Jul 2021 12:54:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v6 05/17] accel/tcg: Drop CF_NO_GOTO_PTR from -d nochain Date: Tue, 20 Jul 2021 09:54:27 -1000 Message-Id: <20210720195439.626594-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720195439.626594-1-richard.henderson@linaro.org> References: <20210720195439.626594-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626811053729100001 Content-Type: text/plain; charset="utf-8" The purpose of suppressing goto_ptr from -d nochain had been to return to the main loop so that -d cpu would be recognized. But we now include -d cpu logging in helper_lookup_tb_ptr so there is no need to exclude goto_ptr. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20210717221851.2124573-5-richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland --- accel/tcg/cpu-exec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index d3232d5764..70ea3c7d68 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -150,7 +150,7 @@ uint32_t curr_cflags(CPUState *cpu) uint32_t cflags =3D cpu->tcg_cflags; =20 if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR; + cflags |=3D CF_NO_GOTO_TB; } =20 return cflags; --=20 2.25.1 From nobody Mon May 13 10:52:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626811042393178.5694819385509; Tue, 20 Jul 2021 12:57:22 -0700 (PDT) Received: from localhost ([::1]:48608 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5vrk-0001uR-NP for importer@patchew.org; Tue, 20 Jul 2021 15:57:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55684) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5vpN-0007Am-8s for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:53 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:39790) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5vpL-00082G-QX for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:53 -0400 Received: by mail-pf1-x431.google.com with SMTP id b12so428562pfv.6 for ; Tue, 20 Jul 2021 12:54:51 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id j25sm15422179pfh.77.2021.07.20.12.54.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 12:54:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jXNdPSSG3EvHjS1ff9yaYX7BJ5tWCVTACEwi3klwS+c=; b=d81CIYkGmpm6ZkjDzFpOZdrYgeXv+Hn6nw+iMcB/63XeZ5crb7UM7fzRGNVSd66gK8 1g1rmsIzePVxTCwOHFzkSck6rfaH8Aw0VQafJGKxyYAkCxYt4TMhBNoVqPZeOHNpH0kV BndRDBnCsWoSp7zZ8f4x7RyCHEUOU/ulHjlFsmZAD2eqvgr9sOzvfAtQn2Q7VJTx5XD7 q1KHyFcdAtcwXPHOzHfi+alxk0RulegW16lqhRLnCZ8riFIiXhjlwrCDODUDvJ6bv4W6 A0/3Y+r3ffzqaCsaj/Nq4riDzVxoKGITnC/c85vqZxrlR9pR3ev3rb+PvpeIdn9GerfL XZTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jXNdPSSG3EvHjS1ff9yaYX7BJ5tWCVTACEwi3klwS+c=; b=LgDD7Gz6nhuuuSNJRzNsjP2Sj+UGq7pvKI4E0iqMXhomCqGbnHpJBZ0PwmptikrYfG CQmqfzQmMiCfCg5ZavTdrO2C0L1LI5bt6JNRCahaW2eVKWYVh3AYMUvMFuBI73E35xEk p75nSCcs0IscS7LdNxniaAc/dhHXCHDdTW+o5c12p3ePqEuLXGGSjSa9EtDTjYHfg15F f7M74aSkTzF7g+alJBY0kP9Wtx6o1bcYQF3S7y/wInDaUCwNvF0wvGP55LvpCJZU12Lz gpwIMxgfDRJErtrb0uIjcnGcn2cPtiIKBbSxwaV+M8luTlAxUdZq9Ndg3ZTTjEFUvcvY dMOQ== X-Gm-Message-State: AOAM530ydc+d5L/L4tyw2IV/oXvm7k0XgpEk8TAfo7rQJOQqV/bzm/Uc Pzur68stMiAnRqr2iOvTd9eIbbmQ5YlLmQ== X-Google-Smtp-Source: ABdhPJzFdoaSTAa26tAaQX/53UGfFk8aw8R8nnnr8uCP5Hwn8oxbrnOlDK8KnOpOkftjdln1JFV1CQ== X-Received: by 2002:a63:1126:: with SMTP id g38mr32111677pgl.452.1626810890546; Tue, 20 Jul 2021 12:54:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v6 06/17] accel/tcg: Handle -singlestep in curr_cflags Date: Tue, 20 Jul 2021 09:54:28 -1000 Message-Id: <20210720195439.626594-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720195439.626594-1-richard.henderson@linaro.org> References: <20210720195439.626594-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626811043011100001 Content-Type: text/plain; charset="utf-8" Exchange the test in translator_use_goto_tb for CF_NO_GOTO_TB, and the test in tb_gen_code for setting CF_COUNT_MASK to 1. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20210717221851.2124573-6-richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland --- accel/tcg/cpu-exec.c | 8 +++++++- accel/tcg/translate-all.c | 2 +- accel/tcg/translator.c | 2 +- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 70ea3c7d68..2206c463f5 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -149,7 +149,13 @@ uint32_t curr_cflags(CPUState *cpu) { uint32_t cflags =3D cpu->tcg_cflags; =20 - if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { + /* + * For singlestep and -d nochain, suppress goto_tb so that + * we can log -d cpu,exec after every TB. + */ + if (singlestep) { + cflags |=3D CF_NO_GOTO_TB | 1; + } else if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { cflags |=3D CF_NO_GOTO_TB; } =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 5cc01d693b..bf82c15aab 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1432,7 +1432,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } QEMU_BUILD_BUG_ON(CF_COUNT_MASK + 1 !=3D TCG_MAX_INSNS); =20 - if (cpu->singlestep_enabled || singlestep) { + if (cpu->singlestep_enabled) { max_insns =3D 1; } =20 diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 2ea5a74f30..a59eb7c11b 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -39,7 +39,7 @@ bool translator_use_goto_tb(DisasContextBase *db, target_= ulong dest) } =20 /* Suppress goto_tb in the case of single-steping. */ - if (db->singlestep_enabled || singlestep) { + if (db->singlestep_enabled) { return false; } =20 --=20 2.25.1 From nobody Mon May 13 10:52:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626811201194826.5648776342935; Tue, 20 Jul 2021 13:00:01 -0700 (PDT) Received: from localhost ([::1]:57162 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5vuK-0007nk-3d for importer@patchew.org; Tue, 20 Jul 2021 16:00:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55694) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5vpO-0007BP-Gm for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:55 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:41679) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5vpN-00082U-2g for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:54 -0400 Received: by mail-pg1-x532.google.com with SMTP id s18so23523199pgg.8 for ; Tue, 20 Jul 2021 12:54:52 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id j25sm15422179pfh.77.2021.07.20.12.54.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 12:54:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UqlmS05MkTOxmP5dwcL3fhQ/lw1WJjbK9e+xb00mPGM=; b=g1DwIPjM1AyjdKeChOvkz8D1AaXFZZDAjBVjt7O9oN2pibMyXXjHXLUBGTfVKsCTLF x8VEpLSFAgedtyVQAhTgCqiTAVT4jYvYBslHHOTC0N82nUhN1TpsyNSA8Gxvz9Zr36lr 2CXLA962CTaM29a7BFQ/351QE+OBhAtNAH7K26WhLTGozu0OSwlLFs00l29n5NZUnP/o fEy4gCFYZboRi42YeeMj2Or4dKbaLE9cTt5F17XvywLg+9yguAdwh5t9i6knjyhSUXpd dRkHwaBVWWg8oWCT4g6xry9KdI+9ZXhnvuetmtZywiULfQvvFkugbzKFSPaxRA/PQT/5 +Rlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UqlmS05MkTOxmP5dwcL3fhQ/lw1WJjbK9e+xb00mPGM=; b=a3l8MS1/DkJenqV8pDL3Jg1eMKKp6gLTUAoVMtMSqVfo82F2kAOOP8PZYCw2eH51ck EDW+i2I9x6iLheLqapMdi9IqkS7MLA/q9tYApIlB1MCa/UcnoWMH7KORbRGN52wBN7mD Uec78rkUItIgfE4N696Kb56s8JZmPhv8FCnRi3f617i8VJi6IUGGJcrHy+wwB4X3hYZz Yis6uItIXcqzGDCj8753XpeS5ECygBLK2gNroPrajGIkQ/UuI23blTgLkQKsYlnYTfIk RhL+wFdywcEiCfinlecws0MfGmEPH6L4FLRSnh+PJVJeqZmpC1Uj9K5D9TZXxEmncfoV O8aw== X-Gm-Message-State: AOAM53207/ucgharUNLCY6dmuVQWgLCzqkyOmanmOO+viKyqCsQRPQSV SeKPZt0TL9NUOSv4f7fUUb3jQEFbLF2xAQ== X-Google-Smtp-Source: ABdhPJzm8M6f2ufGaXj9jJY0RdN4mP7mRAkEN1cgqgBrZMjIsRyVJ+o3Z8tBWICSGVtfiZNomQ/O6w== X-Received: by 2002:a65:6111:: with SMTP id z17mr1873612pgu.335.1626810891853; Tue, 20 Jul 2021 12:54:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v6 07/17] accel/tcg: Use CF_NO_GOTO_{TB, PTR} in cpu_exec_step_atomic Date: Tue, 20 Jul 2021 09:54:29 -1000 Message-Id: <20210720195439.626594-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720195439.626594-1-richard.henderson@linaro.org> References: <20210720195439.626594-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626811201717100001 Request that the one TB returns immediately, so that we release the exclusive lock as soon as possible. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Message-Id: <20210717221851.2124573-7-richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland --- accel/tcg/cpu-exec.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 2206c463f5..5bb099174f 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -330,8 +330,7 @@ void cpu_exec_step_atomic(CPUState *cpu) CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; target_ulong cs_base, pc; - uint32_t flags; - uint32_t cflags =3D (curr_cflags(cpu) & ~CF_PARALLEL) | 1; + uint32_t flags, cflags; int tb_exit; =20 if (sigsetjmp(cpu->jmp_env, 0) =3D=3D 0) { @@ -341,8 +340,14 @@ void cpu_exec_step_atomic(CPUState *cpu) cpu->running =3D true; =20 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); =20 + cflags =3D curr_cflags(cpu); + /* Execute in a serial context. */ + cflags &=3D ~CF_PARALLEL; + /* After 1 insn, return and release the exclusive lock. */ + cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1; + + tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb =3D=3D NULL) { mmap_lock(); tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); --=20 2.25.1 From nobody Mon May 13 10:52:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626811450856597.9357445345863; Tue, 20 Jul 2021 13:04:10 -0700 (PDT) Received: from localhost ([::1]:37394 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5vyL-000583-Nc for importer@patchew.org; Tue, 20 Jul 2021 16:04:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55712) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5vpQ-0007Er-7b for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:57 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:43753) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5vpO-00084S-Cd for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:55 -0400 Received: by mail-pj1-x102f.google.com with SMTP id x13-20020a17090a46cdb0290175cf22899cso261465pjg.2 for ; Tue, 20 Jul 2021 12:54:54 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id j25sm15422179pfh.77.2021.07.20.12.54.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 12:54:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5o3EFC0L+7Y5ve+aUtFOWA7OByelfTkc7/2t+/SWZ0s=; b=UzLF8E/ns0aR317t3hwcURMkOanbYuSfmGoiu90EWOCIbRvj6CnJc9lH6QtHJwP863 isFv+sn18otKxpQwD51o9AAKUFzProvqe5BAX8xXXtPv6tgROvs3mAT4b9o5/hUu/Di6 sHG1bytKucdM2kzuvgGPwytUVVRGrsLBDszB3S2Snbqw+GW9la0VzCbfXONCRTsOW0Ih cRBgUvHVKbMSusHZxXPIw0bY9HdRLDzULNFE7yP3LKlT0uZhyI3Ub8F6R9x5s8pdSi8O 9LZMCyPU1Jb1C03LkP5CVxcUzUtmj9EfPfghZ2p+zXxCbT7EakfqhTNLrv2IhncrM97w M0CA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5o3EFC0L+7Y5ve+aUtFOWA7OByelfTkc7/2t+/SWZ0s=; b=bfHn5WK+LznNXlmNSJfYxgmupPuOHjqXrbMDHm6LSUuPq5GGt4BjeAe91BR/Xd178F izMQ9UE5zVKh93DVWrq68NHVUF3foHEsa3UTOvN1DXzox1RKifZ9fOJQR8xsVBT/g65h rBkU54j5HgaFGRCI4MMVoZrkkWm46brl6ng/uTFlzUdjP/Fzczt/7WU3iL3ciwJ8yZYv JQpTAguQHbE+o5fM7C8ah+2JrcvrXg1GrRWiDzmY5QOn7jjwH11QmcIq9afAkTABF+zG DzwHlx7sbKWYJvYrHS92IH0vznHFXRQ8wb8Jta9mxdwIQK+8cKiwiJejLX7WVRYMhsYq 2u/g== X-Gm-Message-State: AOAM531OUuLQ7R9xFqw14sRhPmdkuXIiolPdkoF4xvIfLS2N2L1fRykr bYa1NNjr3KuqwO48QGTxIo3GI6UkYy78Cg== X-Google-Smtp-Source: ABdhPJxvKqHDiemHu0DuyK4Tyh+OndL7FLd434woHpYPEKl7yBrsmO+Be8GaEmvDVUs2OwLyZeM88g== X-Received: by 2002:a17:902:bc82:b029:12b:a074:1fae with SMTP id bb2-20020a170902bc82b029012ba0741faemr2070744plb.29.1626810893183; Tue, 20 Jul 2021 12:54:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v6 08/17] hw/core: Introduce TCGCPUOps.debug_check_breakpoint Date: Tue, 20 Jul 2021 09:54:30 -1000 Message-Id: <20210720195439.626594-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720195439.626594-1-richard.henderson@linaro.org> References: <20210720195439.626594-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626811452900100001 New hook to return true when an architectural breakpoint is to be recognized and false when it should be suppressed. First use must wait until other pieces are in place. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Mark Cave-Ayland --- include/hw/core/tcg-cpu-ops.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 72d791438c..eab27d0c03 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -88,6 +88,12 @@ struct TCGCPUOps { */ bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); =20 + /** + * @debug_check_breakpoint: return true if the architectural + * breakpoint whose PC has matched should really fire. + */ + bool (*debug_check_breakpoint)(CPUState *cpu); + /** * @io_recompile_replay_branch: Callback for cpu_io_recompile. * --=20 2.25.1 From nobody Mon May 13 10:52:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626811445209239.71041835026313; Tue, 20 Jul 2021 13:04:05 -0700 (PDT) Received: from localhost ([::1]:37020 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5vyG-0004tV-25 for importer@patchew.org; Tue, 20 Jul 2021 16:04:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55734) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5vpR-0007FG-CV for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:59 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:41745) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5vpP-00084e-P4 for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:57 -0400 Received: by mail-pj1-x102b.google.com with SMTP id jx7-20020a17090b46c7b02901757deaf2c8so285486pjb.0 for ; Tue, 20 Jul 2021 12:54:55 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id j25sm15422179pfh.77.2021.07.20.12.54.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 12:54:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2J5gDf0ll8w4iTuhpRWpeMysVEVXrcPOLSCqyOf7Eh4=; b=GPVel5q8TCBUHoWHM2IVfBvuo0gEY5g+zTRz6U1/tRiMQ/JARUxUalmmo3C8UcEnJI SUi6d9iE1v8U/jXrHaIEAEk+sxtjd7EIvLAZzatrFGyebEaqEJybAbgijcnyZW4nVb2k 7tBY39H4cxkDDcFuQfoHv+sDNCKafNfPyp6jbxq1OL7yNIoxXi4qr32T/Vnz7h8Fdfsa 9ZsCk1g5wS3TakhrW5/yVn+fCUTvxRgAal3RC0oqgYY4B2Xfe7wAunO8MTn51YZ3XLQd jVLKycMqmbW1ft4T9g9B85SOydVQ+/D8fbj5jMIP+in1J/I2rExwuPdjFD4ICz+JahRz HAzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2J5gDf0ll8w4iTuhpRWpeMysVEVXrcPOLSCqyOf7Eh4=; b=qIg/DH+qcfhAPst+S0sI7i/nJxT/zMRfj+3wynydRgLeI9F6vmydXYspEVuoOOL9pD 9vC5+bOcKiveDXjpDLH94Ro9jdMF4D+YfHQ/AroPVsLd6PES9IXXg4eM2rJqMwoN1Muv v+jeH9mceYTNWG3bFrv4HF+5DhwBDkweO4pjIzYjOsprqWj7rMRb0nmGEK97lmmyhB5U lIdRYxifmJsYReKOfC5B05gLiHIHZyAc2j9jvuyMW/BZh7ewbi6VCnAXEN4GpGKCka/+ Glo+JYBujSdEGsG8xCL0H9H5NS7KG/MJbGhJK+kOBw1BSzOHxkajfVKiKju4kqzn3j7o Yn6g== X-Gm-Message-State: AOAM5300nS6BKGnBRHoWbIrE8BVQlWqk7F2Xr3ydLa1TMh+w6areHnSh jhwpecPJa5KFa9txrpFLswR4+AvyjnzehQ== X-Google-Smtp-Source: ABdhPJzwFVzots9e0WlLePEqaxWquqk/igchYvOgXC06a7O4vUY3+/RZnsUc9Y5VFcDpkuVlqsCZmg== X-Received: by 2002:a17:90a:590d:: with SMTP id k13mr31695632pji.56.1626810894485; Tue, 20 Jul 2021 12:54:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v6 09/17] target/arm: Implement debug_check_breakpoint Date: Tue, 20 Jul 2021 09:54:31 -1000 Message-Id: <20210720195439.626594-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720195439.626594-1-richard.henderson@linaro.org> References: <20210720195439.626594-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626811445938100001 Reuse the code at the bottom of helper_check_breakpoints, which is what we currently call from *_tr_breakpoint_check. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Mark Cave-Ayland --- target/arm/internals.h | 3 +++ target/arm/cpu.c | 1 + target/arm/cpu_tcg.c | 1 + target/arm/debug_helper.c | 7 +++---- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 3ba86e8af8..11a72013f5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -282,6 +282,9 @@ void hw_breakpoint_update(ARMCPU *cpu, int n); */ void hw_breakpoint_update_all(ARMCPU *cpu); =20 +/* Callback function for checking if a breakpoint should trigger. */ +bool arm_debug_check_breakpoint(CPUState *cs); + /* Callback function for checking if a watchpoint should trigger. */ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9cddfd6a44..752b15bb79 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1984,6 +1984,7 @@ static const struct TCGCPUOps arm_tcg_ops =3D { .do_unaligned_access =3D arm_cpu_do_unaligned_access, .adjust_watchpoint_address =3D arm_adjust_watchpoint_address, .debug_check_watchpoint =3D arm_debug_check_watchpoint, + .debug_check_breakpoint =3D arm_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ }; #endif /* CONFIG_TCG */ diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index d2d97115ea..ed444bf436 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -911,6 +911,7 @@ static const struct TCGCPUOps arm_v7m_tcg_ops =3D { .do_unaligned_access =3D arm_cpu_do_unaligned_access, .adjust_watchpoint_address =3D arm_adjust_watchpoint_address, .debug_check_watchpoint =3D arm_debug_check_watchpoint, + .debug_check_breakpoint =3D arm_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ }; #endif /* CONFIG_TCG */ diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 2ff72d47d1..4a0c479527 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -216,8 +216,9 @@ static bool check_watchpoints(ARMCPU *cpu) return false; } =20 -static bool check_breakpoints(ARMCPU *cpu) +bool arm_debug_check_breakpoint(CPUState *cs) { + ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; int n; =20 @@ -240,9 +241,7 @@ static bool check_breakpoints(ARMCPU *cpu) =20 void HELPER(check_breakpoints)(CPUARMState *env) { - ARMCPU *cpu =3D env_archcpu(env); - - if (check_breakpoints(cpu)) { + if (arm_debug_check_breakpoint(env_cpu(env))) { HELPER(exception_internal(env, EXCP_DEBUG)); } } --=20 2.25.1 From nobody Mon May 13 10:52:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626811256957598.0482802762151; Tue, 20 Jul 2021 13:00:56 -0700 (PDT) Received: from localhost ([::1]:58046 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5vvD-0008PQ-VE for importer@patchew.org; Tue, 20 Jul 2021 16:00:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55762) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5vpT-0007G6-Hr for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:59 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:55910) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5vpR-00085h-44 for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:59 -0400 Received: by mail-pj1-x102f.google.com with SMTP id gx2so305867pjb.5 for ; Tue, 20 Jul 2021 12:54:56 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id j25sm15422179pfh.77.2021.07.20.12.54.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 12:54:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P7/BMHsXFM5u+/5zB8fL6SRcNTVkT9GgtafQt9Cnl+M=; b=WtI7UFlqddpgzW2NCnXw6PoKts83f4wKociSZm7AKqCGbQgFUBuL703TsocVjPLVq9 2RTRSEV4mX/xHNr/LUEPVErtHAJN6ztN5y5CLZZnkhQAvd4gnl6ShCJyD21iXLZD1ra7 tM7EDKI5OZJHxFA1AZ6z6El6Ntzk+8qYyDD0X/ey10Hz6ZVczL3wD3qqM2KZEBBGAnnn LpJ237P1/lITC5wDLaRdM2W+N5LoapF0uUMgTPHdOZtNa2pIjzh6YkCIwtINT76Pe8ge K3ssmpysS7R16Ev7sXuE2E8WcnJXd3CxlVG1Z33YjqcIRP6kJDjyOxRu9Kl/a6JrRCWb MAZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P7/BMHsXFM5u+/5zB8fL6SRcNTVkT9GgtafQt9Cnl+M=; b=dvpo9jjGv7E+V7cFvVlalk5X/rGp0jPpUp1Oj5PKFkAflpRo39M+rhMX/MkxNjdePB CAyokRAxuLsWrFu7Qy+WyHyO7OfvsiOQNoDHBm5D3JOx8qRNCiqU6sLSxMcX00IYLD1u gEjtOXnaPqa5n4FY7GrpEYxj397hb1+UDSW7Ywp65iowfP3x3pSCf1MiR9uIENkrx/Lk bKqw+sC7ZtibDuaTt2Q0d7UZ07bkpk2etKme9IJii7WlCxH5/njhT+wchXXai3s2ntRa ryDnPoAi/M47hVhMvSq+b2u4WPFYI5veYanNcqaKTwKRUlBu/TNppNWrPsPTmvarmbb8 riYA== X-Gm-Message-State: AOAM533Eox+gyMQehTwIaxCif8+PeX3M+b9dceeYMiugk9leAx7fTgmo wUsgplpx6ljHn6nODLv6LWmoy1OedW8RFw== X-Google-Smtp-Source: ABdhPJxPaJn5pnNWgTBHTtsdHXeAW3zwYbsZW6xXx7vGYYBs80Hnr00ugdWhQHVOI6aOwchoFgfI8w== X-Received: by 2002:a17:90a:bd94:: with SMTP id z20mr32430995pjr.214.1626810895884; Tue, 20 Jul 2021 12:54:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v6 10/17] target/i386: Implement debug_check_breakpoint Date: Tue, 20 Jul 2021 09:54:32 -1000 Message-Id: <20210720195439.626594-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720195439.626594-1-richard.henderson@linaro.org> References: <20210720195439.626594-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626811259285100001 Return false for RF set, as we do in i386_tr_breakpoint_check. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- target/i386/tcg/tcg-cpu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index e96ec9bbcc..238e3a9395 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -54,6 +54,17 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, cpu->env.eip =3D tb->pc - tb->cs_base; } =20 +#ifndef CONFIG_USER_ONLY +static bool x86_debug_check_breakpoint(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + /* RF disables all architectural breakpoints. */ + return !(env->eflags & RF_MASK); +} +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static const struct TCGCPUOps x86_tcg_ops =3D { @@ -66,6 +77,7 @@ static const struct TCGCPUOps x86_tcg_ops =3D { .tlb_fill =3D x86_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY .debug_excp_handler =3D breakpoint_handler, + .debug_check_breakpoint =3D x86_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ }; =20 --=20 2.25.1 From nobody Mon May 13 10:52:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626811679363373.057084326702; Tue, 20 Jul 2021 13:07:59 -0700 (PDT) Received: from localhost ([::1]:48740 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5w22-0004KS-6h for importer@patchew.org; Tue, 20 Jul 2021 16:07:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55768) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5vpU-0007Hc-IK for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:55:00 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:34815) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5vpS-00086Q-GX for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:54:59 -0400 Received: by mail-pf1-x42e.google.com with SMTP id o201so448036pfd.1 for ; Tue, 20 Jul 2021 12:54:58 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id j25sm15422179pfh.77.2021.07.20.12.54.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 12:54:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FG3q2edYS6Fvc6gJJ5V0CeBI+/JUHyKtgs7Bx29llms=; b=gGX9/e668+itBWM5nokIqsa2CxH4RDX8pKM7uuMeNQpmwavbNk3E5F4Zct86TKz+/d IorPiTyHotxyNvuxY8eElpaNG5RZ0paRseoEQhw0Fgx5uJw/EKdhrcWSLyYifHLDgTgr eosY4kC6ONBX3Mfg4Mn4MAURzrFnkWTHAaIL4HTHxtgMTDpGsBtpFcgxIOcRqinVIi69 Ph1YQMpx35uM/CZ/2xEkAZ380JMcqP7v8LEE6GHj62xqQ/0QAZWISXrHbgaVBHBfPJE7 nB4uwhGSY/+Oex0mwU4NamawoiHDLVlVmKtOKGznhY6ON5cMEVa4bX2c72B9C00nrGoE iXgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FG3q2edYS6Fvc6gJJ5V0CeBI+/JUHyKtgs7Bx29llms=; b=Sa/024JxczRcP7D0a645S8yppRU1Vsi4BL/A17oAtAEq1zQUrf4lMBzfB5dOkK87/k o9+/tKz2ChyPKOwZPVEGHA9OtJRXACS3v/pnJvNZTPurlwWsXJo5xSdRP6G2Gi5I/z5V JhoQuknvyMF8SwP1T11lOdNUtIEEPSfLX7/MkehAN3cdo6hqQ6JqwRrzOd0VKLfxzQVG H7HLxpmvs4cKgJKVs6AEMa1cPKVpfBPqfCzoXlAp7YEhc2okiMAuHw7QUerdueqKTK88 xsglZVRGX0T0aVsrMQFharfaLJmNxEAEexS/CYAr07266Cn9pHfHlrjRu1szZhvfem1d h3aA== X-Gm-Message-State: AOAM5303zyBglATke4046kjprhcwtCiBfB6vrZtFYU+NQNH2vaYGhuwi AMKa3fFNQugNPsUOrGYVViPSg8bCim2U2g== X-Google-Smtp-Source: ABdhPJwWX8lsn9W1UiMG5kLAcOWSdcfp9oaO9pRJMxC5bQcK4NIWCi4M8YMtxd0ifpKhihKpNd8utw== X-Received: by 2002:a05:6a00:a86:b029:328:566c:d4e5 with SMTP id b6-20020a056a000a86b0290328566cd4e5mr33686483pfl.19.1626810897280; Tue, 20 Jul 2021 12:54:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v6 11/17] hw/core: Introduce CPUClass.gdb_adjust_breakpoint Date: Tue, 20 Jul 2021 09:54:33 -1000 Message-Id: <20210720195439.626594-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720195439.626594-1-richard.henderson@linaro.org> References: <20210720195439.626594-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626811680187100001 Content-Type: text/plain; charset="utf-8" This will allow a breakpoint hack to move out of AVR's translator. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- include/hw/core/cpu.h | 4 ++++ cpu.c | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 4e0ea68efc..bc864564ce 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -103,6 +103,9 @@ struct SysemuCPUOps; * also implement the synchronize_from_tb hook. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. + * @gdb_adjust_breakpoint: Callback for adjusting the address of a + * breakpoint. Used by AVR to handle a gdb mis-feature with + * its Harvard architecture split code and data. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to s= top @@ -137,6 +140,7 @@ struct CPUClass { void (*set_pc)(CPUState *cpu, vaddr value); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); + vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr); =20 const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); diff --git a/cpu.c b/cpu.c index 83059537d7..91d9e38acb 100644 --- a/cpu.c +++ b/cpu.c @@ -267,8 +267,13 @@ static void breakpoint_invalidate(CPUState *cpu, targe= t_ulong pc) int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, CPUBreakpoint **breakpoint) { + CPUClass *cc =3D CPU_GET_CLASS(cpu); CPUBreakpoint *bp; =20 + if (cc->gdb_adjust_breakpoint) { + pc =3D cc->gdb_adjust_breakpoint(cpu, pc); + } + bp =3D g_malloc(sizeof(*bp)); =20 bp->pc =3D pc; @@ -294,8 +299,13 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int= flags, /* Remove a specific breakpoint. */ int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags) { + CPUClass *cc =3D CPU_GET_CLASS(cpu); CPUBreakpoint *bp; =20 + if (cc->gdb_adjust_breakpoint) { + pc =3D cc->gdb_adjust_breakpoint(cpu, pc); + } + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { if (bp->pc =3D=3D pc && bp->flags =3D=3D flags) { cpu_breakpoint_remove_by_ref(cpu, bp); --=20 2.25.1 From nobody Mon May 13 10:52:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626811615472731.8558717146622; Tue, 20 Jul 2021 13:06:55 -0700 (PDT) Received: from localhost ([::1]:45512 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5w10-0002Ae-8i for importer@patchew.org; Tue, 20 Jul 2021 16:06:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55786) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5vpW-0007Jh-1s for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:55:02 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:46658) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5vpU-00087Y-B5 for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:55:01 -0400 Received: by mail-pl1-x62d.google.com with SMTP id c15so11944729pls.13 for ; Tue, 20 Jul 2021 12:54:59 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id j25sm15422179pfh.77.2021.07.20.12.54.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 12:54:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P3LffqvNinoZOAp9QjnMZFhnvMGiYvkKM9rqwGaZZAo=; b=gIJdBLu1v+m0e/ELQ+bky6yFBhRDSJXKETDvVjOaT3N8Q9xQNPFIEouMmqG5rZIdO8 /bIrcwZUbI/SBrWlNb1FDzrd3oSwNP9QdEIvQ3KMDFcImu6QMGeIWTcekHdJ0qb2SzET ZEbET6yq6IPnJJTLI9qtXErUg9xWHC/ojInphQt2jIQ5aWeJMeDKqsg0iwcXeliVEHk6 1+5/I1MsLYPXaxF542NvXQ4GD+Lh7ITrA7513fYScFPHmVqlebZPZEJFqA8kvKvWki48 61CIMVXm9C+5IucB+virUpMtc+R7pbO3RmZglD5LfMXydy20XTfXtb428XH4YHhYi/v/ 0V4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P3LffqvNinoZOAp9QjnMZFhnvMGiYvkKM9rqwGaZZAo=; b=f0PmgYLfAw5XXAoQmH4xI1lNFP5F64wqyaUKubNEXAdxaEmXXFpw+ADrPNt4XahvUT rzcyz2SsNB1jxhwpe2BUcBFcd+tJGZzBSudmfAoJbOhcbnDhFTDmTqOjCCGfSG4UpdAC eJgANhetmdvkXa3VV1qOPrfMvAhs8ISbCaoaw2VPbDwTLOPb3dg31maE+HRXdigy1Tk2 HefUSSCzDrIkz4q6lkUlILFkP7Uwzs/+oogIgp2P6IITid1pAetJyOLUWI+KT2/AII3u 0tIuwct10vgz48nUQGFUwzTTZs4wGvLlfsa4/u5g8wojru9OuIK79RoRBYJD8sXGFlQu G7kg== X-Gm-Message-State: AOAM532axEQEoJMtuPtiZ3v81DSSKXtwyxG+WeZ8LOqT9FoBPjBFN+BE FnLQDh2nlzrt2WZGsiBT/C9ZV2g1od0MFQ== X-Google-Smtp-Source: ABdhPJynl8Od31bLxex8houqF1q0nV0TUwcYHSQuLtaqWtdcHLIiWr9C3hbskxddYt0V3R/AF0tEkg== X-Received: by 2002:a17:90b:1484:: with SMTP id js4mr31554311pjb.155.1626810898537; Tue, 20 Jul 2021 12:54:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v6 12/17] target/avr: Implement gdb_adjust_breakpoint Date: Tue, 20 Jul 2021 09:54:34 -1000 Message-Id: <20210720195439.626594-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720195439.626594-1-richard.henderson@linaro.org> References: <20210720195439.626594-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626811616173100001 Content-Type: text/plain; charset="utf-8" Ensure at registration that all breakpoints are in code space, not data space. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- target/avr/cpu.h | 1 + target/avr/cpu.c | 1 + target/avr/gdbstub.c | 13 +++++++++++++ target/avr/translate.c | 14 -------------- 4 files changed, 15 insertions(+), 14 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index d148e8c75a..93e3faa0a9 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -162,6 +162,7 @@ hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr= addr); int avr_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int avr_print_insn(bfd_vma addr, disassemble_info *info); +vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr); =20 static inline int avr_feature(CPUAVRState *env, AVRFeature feature) { diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 57e3fab4a0..ea14175ca5 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -223,6 +223,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; + cc->gdb_adjust_breakpoint =3D avr_cpu_gdb_adjust_breakpoint; cc->gdb_num_core_regs =3D 35; cc->gdb_core_xml_file =3D "avr-cpu.xml"; cc->tcg_ops =3D &avr_tcg_ops; diff --git a/target/avr/gdbstub.c b/target/avr/gdbstub.c index c28ed67efe..1c1b908c92 100644 --- a/target/avr/gdbstub.c +++ b/target/avr/gdbstub.c @@ -82,3 +82,16 @@ int avr_cpu_gdb_write_register(CPUState *cs, uint8_t *me= m_buf, int n) =20 return 0; } + +vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr) +{ + /* + * This is due to some strange GDB behavior + * Let's assume main has address 0x100: + * b main - sets breakpoint at address 0x00000100 (code) + * b *0x100 - sets breakpoint at address 0x00800100 (data) + * + * Force all breakpoints into code space. + */ + return addr % OFFSET_DATA; +} diff --git a/target/avr/translate.c b/target/avr/translate.c index 8237a03c23..f7202a646b 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2958,20 +2958,6 @@ static void avr_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) DisasContext *ctx =3D container_of(dcbase, DisasContext, base); TCGLabel *skip_label =3D NULL; =20 - /* - * This is due to some strange GDB behavior - * Let's assume main has address 0x100: - * b main - sets breakpoint at address 0x00000100 (code) - * b *0x100 - sets breakpoint at address 0x00800100 (data) - * - * The translator driver has already taken care of the code pointer. - */ - if (!ctx->base.singlestep_enabled && - cpu_breakpoint_test(cs, OFFSET_DATA + ctx->base.pc_next, BP_ANY)) { - gen_breakpoint(ctx); - return; - } - /* Conditionally skip the next instruction, if indicated. */ if (ctx->skip_cond !=3D TCG_COND_NEVER) { skip_label =3D gen_new_label(); --=20 2.25.1 From nobody Mon May 13 10:52:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16268117791001019.136959258925; Tue, 20 Jul 2021 13:09:39 -0700 (PDT) Received: from localhost ([::1]:53852 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5w3e-0007gj-41 for importer@patchew.org; Tue, 20 Jul 2021 16:09:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55810) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5vpX-0007MK-1n for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:55:03 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:46960) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5vpV-00088O-58 for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:55:02 -0400 Received: by mail-pg1-x533.google.com with SMTP id r21so5347399pgv.13 for ; Tue, 20 Jul 2021 12:55:00 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id j25sm15422179pfh.77.2021.07.20.12.54.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 12:54:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ii+bv9Rk/DIfrNA6Uf1YrDYjps9D/8ScD8K+6wC+mQk=; b=vGfKQNK/o1HO/PP7SEsGdc5pHtI8kB8b1qzxDut0ooinv38eNmEK5a60zIErD2COVu JoXhsbCehN5KRdTReadNBJXnNkxmOCzcTXlM7VgShY5WgHC+QLBlbr/aBjY0c13KH/Ve ZQpFR7WJYzdvPkt+/fuF8hJivAEAEe0Z86dP7D5ubxir4HzJ/uEUgcRWz2r8BICdK8dK CdiSFfcW9s9DM7O9ixt1+bgiE2QAOizNMwxHOWv3/2f2nUhHEdUUktuNRLpJyIGx/TW5 vFGvpq3eBlfHsEpo3VWjd1+5rXyxjhew2/e8nCYQ8GCQrB95PfUDj0zeVv+r/LkT+GSd LwJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ii+bv9Rk/DIfrNA6Uf1YrDYjps9D/8ScD8K+6wC+mQk=; b=GOS7Hgo+EcFdQdgUhpoW08ol4Es7AEtPBM9Kr/A37N6op2/x56AsnhrAN0mLKg8XdT 0DDZGDiayN6sERyTy78yFfkxaqfH1eOOc1JlZBjHqjopoi/GJ7jL1sJyOeopw5NiiB/c yKsQ2TPgvyFr0YVoVIU28p9UzP6XYIC5IaX8zRYkxwSV1mBFlP4bM0y1axqvW2KmH+qy 7m+/e7vSM84/eYk9D9tc1++6FgVqYFaO70DXI1wFrz20YZUW/uJQzRt1cQrC2raXO/SI xPUMiCAmtz7IOkrO1F6wAc1LtwtpV6pmBC608WhvFI/Se/AD/6Hm/jsMcyV+TJqC0S7z wthg== X-Gm-Message-State: AOAM532ucSSl+aZqvrZzbzoRn69ntqwfUadr67lUMyrbOamJRC39TqtG UtJlCUmHtPMK2W4XGXmgSkMV3Ml0Wv+qTg== X-Google-Smtp-Source: ABdhPJxmgYwShXOY5g66StCOPhzih7yrThM9YLsSr/ZRZl2Qxy7iOS53wfLofod2mKPUoA41g/IPjg== X-Received: by 2002:a63:d84b:: with SMTP id k11mr32391176pgj.372.1626810899941; Tue, 20 Jul 2021 12:54:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v6 13/17] accel/tcg: Merge tb_find into its only caller Date: Tue, 20 Jul 2021 09:54:35 -1000 Message-Id: <20210720195439.626594-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720195439.626594-1-richard.henderson@linaro.org> References: <20210720195439.626594-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626811779470100001 We are going to want two things: (1) check for breakpoints will want to break out of the loop here, (2) cflags can only be calculated with pc in hand. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- accel/tcg/cpu-exec.c | 83 ++++++++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 42 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5bb099174f..cde7069eb7 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -500,41 +500,6 @@ static inline void tb_add_jump(TranslationBlock *tb, i= nt n, return; } =20 -static inline TranslationBlock *tb_find(CPUState *cpu, - TranslationBlock *last_tb, - int tb_exit, uint32_t cflags) -{ - CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; - TranslationBlock *tb; - target_ulong cs_base, pc; - uint32_t flags; - - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - - tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); - if (tb =3D=3D NULL) { - mmap_lock(); - tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); - mmap_unlock(); - /* We add the TB in the virtual pc hash table for the fast lookup = */ - qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb); - } -#ifndef CONFIG_USER_ONLY - /* We don't take care of direct jumps when address mapping changes in - * system emulation. So it's not safe to make a direct jump to a TB - * spanning two pages because the mapping for the second page can chan= ge. - */ - if (tb->page_addr[1] !=3D -1) { - last_tb =3D NULL; - } -#endif - /* See if we can patch the calling TB. */ - if (last_tb) { - tb_add_jump(last_tb, tb_exit, tb); - } - return tb; -} - static inline bool cpu_handle_halt(CPUState *cpu) { if (cpu->halted) { @@ -868,22 +833,56 @@ int cpu_exec(CPUState *cpu) int tb_exit =3D 0; =20 while (!cpu_handle_interrupt(cpu, &last_tb)) { - uint32_t cflags =3D cpu->cflags_next_tb; TranslationBlock *tb; + target_ulong cs_base, pc; + uint32_t flags, cflags; =20 - /* When requested, use an exact setting for cflags for the next - execution. This is used for icount, precise smc, and stop- - after-access watchpoints. Since this request should never - have CF_INVALID set, -1 is a convenient invalid value that - does not require tcg headers for cpu_common_reset. */ + /* + * When requested, use an exact setting for cflags for the next + * execution. This is used for icount, precise smc, and stop- + * after-access watchpoints. Since this request should never + * have CF_INVALID set, -1 is a convenient invalid value that + * does not require tcg headers for cpu_common_reset. + */ + cflags =3D cpu->cflags_next_tb; if (cflags =3D=3D -1) { cflags =3D curr_cflags(cpu); } else { cpu->cflags_next_tb =3D -1; } =20 - tb =3D tb_find(cpu, last_tb, tb_exit, cflags); + cpu_get_tb_cpu_state(cpu->env_ptr, &pc, &cs_base, &flags); + + tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); + if (tb =3D=3D NULL) { + mmap_lock(); + tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + mmap_unlock(); + /* + * We add the TB in the virtual pc hash table + * for the fast lookup + */ + qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]= , tb); + } + +#ifndef CONFIG_USER_ONLY + /* + * We don't take care of direct jumps when address mapping + * changes in system emulation. So it's not safe to make a + * direct jump to a TB spanning two pages because the mapping + * for the second page can change. + */ + if (tb->page_addr[1] !=3D -1) { + last_tb =3D NULL; + } +#endif + /* See if we can patch the calling TB. */ + if (last_tb) { + tb_add_jump(last_tb, tb_exit, tb); + } + cpu_loop_exec_tb(cpu, tb, &last_tb, &tb_exit); + /* Try to align the host and virtual clocks if the guest is in advance */ align_clocks(&sc, cpu); --=20 2.25.1 From nobody Mon May 13 10:52:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626811622594845.0712955550807; Tue, 20 Jul 2021 13:07:02 -0700 (PDT) Received: from localhost ([::1]:46136 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5w17-0002bA-C4 for importer@patchew.org; Tue, 20 Jul 2021 16:07:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55852) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5vpZ-0007Nz-3D for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:55:05 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:38630) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5vpW-00089a-Og for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:55:04 -0400 Received: by mail-pg1-x52d.google.com with SMTP id j4so6859115pgk.5 for ; Tue, 20 Jul 2021 12:55:02 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id j25sm15422179pfh.77.2021.07.20.12.55.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 12:55:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kYUWH5JWsqhdeJXf91tUX3RNEBHiSpWCpHdo9G1cD6M=; b=u2aRJkSa/Ci7Lv+9Y2viy3Tfbhpsgo+EppyuKjQvsF4VzUDAyK/C+XzJJrIwICsP0P yml1xlO9n//jq9cfPJdLW3mVRWQ6vuBHxWoQY5nVdJCk13btOuLfF9xRuh4v6X/s2PCS uXZYo4FxGb33HXXksWDJHcZhU516XwjshmW4zzxna4yY3SYY5zLuA5YsCse3B5cVIVLa 4Nx+6NrF9Vn8gZ2GtF3F3IGJv1ydKgHesSgCeP/Vu2JSlxq0RSMxgbgzqG3bh1ckRVQq QnYtrM7z6sJ/kb2gRY69ziFIq/QYcxKIzxtOmd36HHOlE0EU45Bl94MrAVWbMk18pP1W kcdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kYUWH5JWsqhdeJXf91tUX3RNEBHiSpWCpHdo9G1cD6M=; b=EdWNJfgviCwA6sf7uitVtLs9L9nPInb5bWHKgMyDhu4wRHnTVmp+O8p3RUjkyy1iUn g18hE5Ff035hgeyhNx02C5VhJOCpO+zMEWKnS82xN6XWzi0mf3YktxZ2fkRe17IZI8hJ CEEJN60Wn2u6pHcMzQHRVN3ayALzwJBNQ9hL6aVXxWeixfs5jsBo+zM5scIHvukaBwrE s+HlauCXLs0OrgbDS7f8TAAotccSqUB8bsfYOsYpQjOPMyDGgRoekMQzY3ot3/wE1cNX MQc8Mt7OJj0m2FVRYal9Mz5Qb5rCaMmbzBwggpjvOms7RvOqu8UD7T7v75yqK67AiffZ huBQ== X-Gm-Message-State: AOAM533MM3MZwVJufD1mCJgd+HUcU5HqfeXSYlLEHyT3o2xHyf0HEN3p f0l+FG/adbYcIS+Y1B/ZfK1An3Euxt61lQ== X-Google-Smtp-Source: ABdhPJw+L7Zapt+YhIUCUXOPiK6vCu6hid8TiGwkXz2qK4SawnDcmHDuQIRhXNEEVd22NEeEZiltFQ== X-Received: by 2002:a63:ed0a:: with SMTP id d10mr32605946pgi.82.1626810901306; Tue, 20 Jul 2021 12:55:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v6 14/17] accel/tcg: Move breakpoint recognition outside translation Date: Tue, 20 Jul 2021 09:54:36 -1000 Message-Id: <20210720195439.626594-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720195439.626594-1-richard.henderson@linaro.org> References: <20210720195439.626594-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626811623139100001 Trigger breakpoints before beginning translation of a TB that would begin with a BP. Thus we never generate code for the BP at all. Single-step instructions within a page containing a BP so that we are sure to check each insn for the BP as above. We no longer need to flush any TBs when changing BPs. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/286 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/404 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/489 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- accel/tcg/cpu-exec.c | 91 ++++++++++++++++++++++++++++++++++++++++-- accel/tcg/translator.c | 24 +---------- cpu.c | 20 ---------- 3 files changed, 89 insertions(+), 46 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index cde7069eb7..5cc6363f4c 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -222,6 +222,76 @@ static inline void log_cpu_exec(target_ulong pc, CPUSt= ate *cpu, } } =20 +static bool check_for_breakpoints(CPUState *cpu, target_ulong pc, + uint32_t *cflags) +{ + CPUBreakpoint *bp; + bool match_page =3D false; + + if (likely(QTAILQ_EMPTY(&cpu->breakpoints))) { + return false; + } + + /* + * Singlestep overrides breakpoints. + * This requirement is visible in the record-replay tests, where + * we would fail to make forward progress in reverse-continue. + * + * TODO: gdb singlestep should only override gdb breakpoints, + * so that one could (gdb) singlestep into the guest kernel's + * architectural breakpoint handler. + */ + if (cpu->singlestep_enabled) { + return false; + } + + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + /* + * If we have an exact pc match, trigger the breakpoint. + * Otherwise, note matches within the page. + */ + if (pc =3D=3D bp->pc) { + bool match_bp =3D false; + + if (bp->flags & BP_GDB) { + match_bp =3D true; + } else if (bp->flags & BP_CPU) { +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + CPUClass *cc =3D CPU_GET_CLASS(cpu); + assert(cc->tcg_ops->debug_check_breakpoint); + match_bp =3D cc->tcg_ops->debug_check_breakpoint(cpu); +#endif + } + + if (match_bp) { + cpu->exception_index =3D EXCP_DEBUG; + return true; + } + } else if (((pc ^ bp->pc) & TARGET_PAGE_MASK) =3D=3D 0) { + match_page =3D true; + } + } + + /* + * Within the same page as a breakpoint, single-step, + * returning to helper_lookup_tb_ptr after each insn looking + * for the actual breakpoint. + * + * TODO: Perhaps better to record all of the TBs associated + * with a given virtual page that contains a breakpoint, and + * then invalidate them when a new overlapping breakpoint is + * set on the page. Non-overlapping TBs would not be + * invalidated, nor would any TB need to be invalidated as + * breakpoints are removed. + */ + if (match_page) { + *cflags =3D (*cflags & ~CF_COUNT_MASK) | CF_NO_GOTO_TB | 1; + } + return false; +} + /** * helper_lookup_tb_ptr: quick check for next tb * @env: current cpu state @@ -235,11 +305,16 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) CPUState *cpu =3D env_cpu(env); TranslationBlock *tb; target_ulong cs_base, pc; - uint32_t flags; + uint32_t flags, cflags; =20 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); =20 - tb =3D tb_lookup(cpu, pc, cs_base, flags, curr_cflags(cpu)); + cflags =3D curr_cflags(cpu); + if (check_for_breakpoints(cpu, pc, &cflags)) { + cpu_loop_exit(cpu); + } + + tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb =3D=3D NULL) { return tcg_code_gen_epilogue; } @@ -346,6 +421,12 @@ void cpu_exec_step_atomic(CPUState *cpu) cflags &=3D ~CF_PARALLEL; /* After 1 insn, return and release the exclusive lock. */ cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1; + /* + * No need to check_for_breakpoints here. + * We only arrive in cpu_exec_step_atomic after beginning execution + * of an insn that includes an atomic operation we can't handle. + * Any breakpoint for this insn will have been recognized earlier. + */ =20 tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb =3D=3D NULL) { @@ -837,6 +918,8 @@ int cpu_exec(CPUState *cpu) target_ulong cs_base, pc; uint32_t flags, cflags; =20 + cpu_get_tb_cpu_state(cpu->env_ptr, &pc, &cs_base, &flags); + /* * When requested, use an exact setting for cflags for the next * execution. This is used for icount, precise smc, and stop- @@ -851,7 +934,9 @@ int cpu_exec(CPUState *cpu) cpu->cflags_next_tb =3D -1; } =20 - cpu_get_tb_cpu_state(cpu->env_ptr, &pc, &cs_base, &flags); + if (check_for_breakpoints(cpu, pc, &cflags)) { + break; + } =20 tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb =3D=3D NULL) { diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index a59eb7c11b..4f3728c278 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -50,7 +50,6 @@ bool translator_use_goto_tb(DisasContextBase *db, target_= ulong dest) void translator_loop(const TranslatorOps *ops, DisasContextBase *db, CPUState *cpu, TranslationBlock *tb, int max_insns) { - int bp_insn =3D 0; bool plugin_enabled; =20 /* Initialize DisasContext */ @@ -85,27 +84,6 @@ void translator_loop(const TranslatorOps *ops, DisasCont= extBase *db, plugin_gen_insn_start(cpu, db); } =20 - /* Pass breakpoint hits to target for further processing */ - if (!db->singlestep_enabled - && unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - if (bp->pc =3D=3D db->pc_next) { - if (ops->breakpoint_check(db, cpu, bp)) { - bp_insn =3D 1; - break; - } - } - } - /* The breakpoint_check hook may use DISAS_TOO_MANY to indicate - that only one more instruction is to be executed. Otherwise - it should use DISAS_NORETURN when generating an exception, - but may use a DISAS_TARGET_* value for Something Else. */ - if (db->is_jmp > DISAS_TOO_MANY) { - break; - } - } - /* Disassemble one instruction. The translate_insn hook should update db->pc_next and db->is_jmp to indicate what should be done next -- either exiting this loop or locate the start of @@ -144,7 +122,7 @@ void translator_loop(const TranslatorOps *ops, DisasCon= textBase *db, =20 /* Emit code to exit the TB, as indicated by db->is_jmp. */ ops->tb_stop(db, cpu); - gen_tb_end(db->tb, db->num_insns - bp_insn); + gen_tb_end(db->tb, db->num_insns); =20 if (plugin_enabled) { plugin_gen_tb_end(cpu); diff --git a/cpu.c b/cpu.c index 91d9e38acb..d6ae5ae581 100644 --- a/cpu.c +++ b/cpu.c @@ -225,11 +225,6 @@ void tb_invalidate_phys_addr(target_ulong addr) tb_invalidate_phys_page_range(addr, addr + 1); mmap_unlock(); } - -static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) -{ - tb_invalidate_phys_addr(pc); -} #else void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs att= rs) { @@ -250,17 +245,6 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr = addr, MemTxAttrs attrs) ram_addr =3D memory_region_get_ram_addr(mr) + addr; tb_invalidate_phys_page_range(ram_addr, ram_addr + 1); } - -static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) -{ - /* - * There may not be a virtual to physical translation for the pc - * right now, but there may exist cached TB for this pc. - * Flush the whole TB cache to force re-translation of such TBs. - * This is heavyweight, but we're debugging anyway. - */ - tb_flush(cpu); -} #endif =20 /* Add a breakpoint. */ @@ -286,8 +270,6 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int = flags, QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry); } =20 - breakpoint_invalidate(cpu, pc); - if (breakpoint) { *breakpoint =3D bp; } @@ -320,8 +302,6 @@ void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBre= akpoint *bp) { QTAILQ_REMOVE(&cpu->breakpoints, bp, entry); =20 - breakpoint_invalidate(cpu, bp->pc); - trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags); g_free(bp); } --=20 2.25.1 From nobody Mon May 13 10:52:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626812011669834.5216397269397; Tue, 20 Jul 2021 13:13:31 -0700 (PDT) Received: from localhost ([::1]:34312 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5w7O-00058V-Fl for importer@patchew.org; Tue, 20 Jul 2021 16:13:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55890) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5vpc-0007UF-22 for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:55:08 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]:45695) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5vpY-0008BD-82 for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:55:07 -0400 Received: by mail-pg1-x529.google.com with SMTP id y17so23488609pgf.12 for ; Tue, 20 Jul 2021 12:55:03 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id j25sm15422179pfh.77.2021.07.20.12.55.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 12:55:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=37d/ijQ1t48RUVhImmXHVIknSAC+2fwX9wc5yM63/5g=; b=RrIcItM7iGpoJLqncjMX6umDaRyUYqdvWPTmryKIkz0ek/6H4I4TCDpEVRWSYLC+Tx QfzTv/9xeNAYUZB7FRVed3tLWrJlJqjfAeoHFW2Ke0ObvnaBC2zljLwrjdTlUcEv3hN4 cQqzLxd+UM/VFJiFI/igYvuvqIZ3s7Xkhr10siZEbZgqzTHggly0+avU2HlZiq/rtUna dbwUbsCChEnXIkPsmE+gUp6KVxAzChyEbOrbrSYJr3izmBq75B8qY/EtXBRkyv7m94Wc 0x8yyP8JwDPzxG7+fx+Eq+aSqp4g02My5bhqsSXQ1qaPRoQCARs76KaebDhlc/lYxg+u 7ucQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=37d/ijQ1t48RUVhImmXHVIknSAC+2fwX9wc5yM63/5g=; b=SP6ukxBk+iozdy8XhyKsPOeVK9vMtJiyXv6BAkPQk/aREBFIxYWEO9g8FKHXjvfBSg +EFtHUNJUqw1j8nCHLXbpBLLlSfYPj8Z/oz5OFWz6gBHHj1sf5coczz3DaI+uQ5sNp8b Ha6NVsGlsG3IqLjNvBQinkB0pmrm6Ql4GemrS4q1GieKWZhEI7RjIoYWeT/4p8d1fPGz s4TB75ulssLqWrf4QSEJHtK6iyiY6UE7rraDac/gODiSPzhGRaZtigEUpX01HkMzTmIS dijk0aOZUIYdi8oQmgiopDWAIATUS1gVA3heFyvD/83tLOTK+EhpugBW5QmE7bgkXnkh dBoA== X-Gm-Message-State: AOAM530KgHbuPifOGpxFUr82XLoifnsXXuLhUhEAhLqbmVtaTEApGIZV 1Lf0ct92aXaiOMQSF7y+C3eN0DPmwEgnjw== X-Google-Smtp-Source: ABdhPJz5B15D38UZOkL/JMa1JEGh8UaKgCLGrzQFj6KEEnVezR7zE4IDIPo07uiYkYZWbVVP3IdYVA== X-Received: by 2002:a62:c501:0:b029:32a:dfe9:8648 with SMTP id j1-20020a62c5010000b029032adfe98648mr33514718pfg.28.1626810902676; Tue, 20 Jul 2021 12:55:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v6 15/17] accel/tcg: Remove TranslatorOps.breakpoint_check Date: Tue, 20 Jul 2021 09:54:37 -1000 Message-Id: <20210720195439.626594-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720195439.626594-1-richard.henderson@linaro.org> References: <20210720195439.626594-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626812012523100001 Content-Type: text/plain; charset="utf-8" The hook is now unused, with breakpoints checked outside translation. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Mark Cave-Ayland --- include/exec/translator.h | 11 ----------- target/arm/helper.h | 2 -- target/alpha/translate.c | 16 ---------------- target/arm/debug_helper.c | 7 ------- target/arm/translate-a64.c | 25 ------------------------- target/arm/translate.c | 29 ----------------------------- target/avr/translate.c | 18 ------------------ target/cris/translate.c | 20 -------------------- target/hexagon/translate.c | 17 ----------------- target/hppa/translate.c | 11 ----------- target/i386/tcg/translate.c | 28 ---------------------------- target/m68k/translate.c | 18 ------------------ target/microblaze/translate.c | 18 ------------------ target/mips/tcg/translate.c | 19 ------------------- target/nios2/translate.c | 27 --------------------------- target/openrisc/translate.c | 17 ----------------- target/ppc/translate.c | 18 ------------------ target/riscv/translate.c | 17 ----------------- target/rx/translate.c | 14 -------------- target/s390x/tcg/translate.c | 24 ------------------------ target/sh4/translate.c | 18 ------------------ target/sparc/translate.c | 17 ----------------- target/tricore/translate.c | 16 ---------------- target/xtensa/translate.c | 17 ----------------- 24 files changed, 424 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index dd9c06d40d..d318803267 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -89,15 +89,6 @@ typedef struct DisasContextBase { * @insn_start: * Emit the tcg_gen_insn_start opcode. * - * @breakpoint_check: - * When called, the breakpoint has already been checked to match the = PC, - * but the target may decide the breakpoint missed the address - * (e.g., due to conditions encoded in their flags). Return true to - * indicate that the breakpoint did hit, in which case no more breakp= oints - * are checked. If the breakpoint did hit, emit any code required to - * signal the exception, and set db->is_jmp as necessary to terminate - * the main loop. - * * @translate_insn: * Disassemble one instruction and set db->pc_next for the start * of the following instruction. Set db->is_jmp as necessary to @@ -113,8 +104,6 @@ typedef struct TranslatorOps { void (*init_disas_context)(DisasContextBase *db, CPUState *cpu); void (*tb_start)(DisasContextBase *db, CPUState *cpu); void (*insn_start)(DisasContextBase *db, CPUState *cpu); - bool (*breakpoint_check)(DisasContextBase *db, CPUState *cpu, - const CPUBreakpoint *bp); void (*translate_insn)(DisasContextBase *db, CPUState *cpu); void (*tb_stop)(DisasContextBase *db, CPUState *cpu); void (*disas_log)(const DisasContextBase *db, CPUState *cpu); diff --git a/target/arm/helper.h b/target/arm/helper.h index db87d7d537..248569b0cd 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -54,8 +54,6 @@ DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) DEF_HELPER_2(pre_smc, void, env, i32) =20 -DEF_HELPER_1(check_breakpoints, void, env) - DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_2(cpsr_write_eret, void, env, i32) DEF_HELPER_1(cpsr_read, i32, env) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 949ba6ffde..de6c0a8439 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2967,21 +2967,6 @@ static void alpha_tr_insn_start(DisasContextBase *dc= base, CPUState *cpu) tcg_gen_insn_start(dcbase->pc_next); } =20 -static bool alpha_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *= cpu, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - ctx->base.is_jmp =3D gen_excp(ctx, EXCP_DEBUG, 0); - - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx->base.pc_next +=3D 4; - return true; -} - static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); @@ -3040,7 +3025,6 @@ static const TranslatorOps alpha_tr_ops =3D { .init_disas_context =3D alpha_tr_init_disas_context, .tb_start =3D alpha_tr_tb_start, .insn_start =3D alpha_tr_insn_start, - .breakpoint_check =3D alpha_tr_breakpoint_check, .translate_insn =3D alpha_tr_translate_insn, .tb_stop =3D alpha_tr_tb_stop, .disas_log =3D alpha_tr_disas_log, diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 4a0c479527..2983e36dd3 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -239,13 +239,6 @@ bool arm_debug_check_breakpoint(CPUState *cs) return false; } =20 -void HELPER(check_breakpoints)(CPUARMState *env) -{ - if (arm_debug_check_breakpoint(env_cpu(env))) { - HELPER(exception_internal(env, EXCP_DEBUG)); - } -} - bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) { /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ca11a5fecd..422e2ac0c9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14844,30 +14844,6 @@ static void aarch64_tr_insn_start(DisasContextBase= *dcbase, CPUState *cpu) dc->insn_start =3D tcg_last_op(); } =20 -static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState= *cpu, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - if (bp->flags & BP_CPU) { - gen_a64_set_pc_im(dc->base.pc_next); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it likely won't be executed */ - dc->base.is_jmp =3D DISAS_TOO_MANY; - } else { - gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - dc->base.pc_next +=3D 4; - dc->base.is_jmp =3D DISAS_NORETURN; - } - - return true; -} - static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *= cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -14982,7 +14958,6 @@ const TranslatorOps aarch64_translator_ops =3D { .init_disas_context =3D aarch64_tr_init_disas_context, .tb_start =3D aarch64_tr_tb_start, .insn_start =3D aarch64_tr_insn_start, - .breakpoint_check =3D aarch64_tr_breakpoint_check, .translate_insn =3D aarch64_tr_translate_insn, .tb_stop =3D aarch64_tr_tb_stop, .disas_log =3D aarch64_tr_disas_log, diff --git a/target/arm/translate.c b/target/arm/translate.c index e1a8152598..351afa43a2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9438,33 +9438,6 @@ static void arm_tr_insn_start(DisasContextBase *dcba= se, CPUState *cpu) dc->insn_start =3D tcg_last_op(); } =20 -static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cp= u, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - if (bp->flags & BP_CPU) { - gen_set_condexec(dc); - gen_set_pc_im(dc, dc->base.pc_next); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it's likely not going to be executed */ - dc->base.is_jmp =3D DISAS_TOO_MANY; - } else { - gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - /* TODO: Advance PC by correct instruction length to - * avoid disassembler error messages */ - dc->base.pc_next +=3D 2; - dc->base.is_jmp =3D DISAS_NORETURN; - } - - return true; -} - static bool arm_pre_translate_insn(DisasContext *dc) { #ifdef CONFIG_USER_ONLY @@ -9827,7 +9800,6 @@ static const TranslatorOps arm_translator_ops =3D { .init_disas_context =3D arm_tr_init_disas_context, .tb_start =3D arm_tr_tb_start, .insn_start =3D arm_tr_insn_start, - .breakpoint_check =3D arm_tr_breakpoint_check, .translate_insn =3D arm_tr_translate_insn, .tb_stop =3D arm_tr_tb_stop, .disas_log =3D arm_tr_disas_log, @@ -9837,7 +9809,6 @@ static const TranslatorOps thumb_translator_ops =3D { .init_disas_context =3D arm_tr_init_disas_context, .tb_start =3D arm_tr_tb_start, .insn_start =3D arm_tr_insn_start, - .breakpoint_check =3D arm_tr_breakpoint_check, .translate_insn =3D thumb_tr_translate_insn, .tb_stop =3D arm_tr_tb_stop, .disas_log =3D arm_tr_disas_log, diff --git a/target/avr/translate.c b/target/avr/translate.c index f7202a646b..1111e08b83 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2900,14 +2900,6 @@ static bool canonicalize_skip(DisasContext *ctx) return true; } =20 -static void gen_breakpoint(DisasContext *ctx) -{ - canonicalize_skip(ctx); - tcg_gen_movi_tl(cpu_pc, ctx->npc); - gen_helper_debug(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; -} - static void avr_tr_init_disas_context(DisasContextBase *dcbase, CPUState *= cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); @@ -2944,15 +2936,6 @@ static void avr_tr_insn_start(DisasContextBase *dcba= se, CPUState *cs) tcg_gen_insn_start(ctx->npc); } =20 -static bool avr_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - gen_breakpoint(ctx); - return true; -} - static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); @@ -3055,7 +3038,6 @@ static const TranslatorOps avr_tr_ops =3D { .init_disas_context =3D avr_tr_init_disas_context, .tb_start =3D avr_tr_tb_start, .insn_start =3D avr_tr_insn_start, - .breakpoint_check =3D avr_tr_breakpoint_check, .translate_insn =3D avr_tr_translate_insn, .tb_stop =3D avr_tr_tb_stop, .disas_log =3D avr_tr_disas_log, diff --git a/target/cris/translate.c b/target/cris/translate.c index 9258c13e9f..a84b753349 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3118,25 +3118,6 @@ static void cris_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) tcg_gen_insn_start(dc->delayed_branch =3D=3D 1 ? dc->ppc | 1 : dc->pc); } =20 -static bool cris_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= pu, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - cris_evaluate_flags(dc); - tcg_gen_movi_tl(env_pc, dc->pc); - t_gen_raise_exception(EXCP_DEBUG); - dc->base.is_jmp =3D DISAS_NORETURN; - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - dc->pc +=3D 2; - return true; -} - static void cris_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -3315,7 +3296,6 @@ static const TranslatorOps cris_tr_ops =3D { .init_disas_context =3D cris_tr_init_disas_context, .tb_start =3D cris_tr_tb_start, .insn_start =3D cris_tr_insn_start, - .breakpoint_check =3D cris_tr_breakpoint_check, .translate_insn =3D cris_tr_translate_insn, .tb_stop =3D cris_tr_tb_stop, .disas_log =3D cris_tr_disas_log, diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index b23d36adf5..54fdcaa5e8 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -540,22 +540,6 @@ static void hexagon_tr_insn_start(DisasContextBase *dc= base, CPUState *cpu) tcg_gen_insn_start(ctx->base.pc_next); } =20 -static bool hexagon_tr_breakpoint_check(DisasContextBase *dcbase, CPUState= *cpu, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - gen_exception_end_tb(ctx, EXCP_DEBUG); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - ctx->base.pc_next +=3D 4; - return true; -} - static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx) { target_ulong page_start =3D ctx->base.pc_first & TARGET_PAGE_MASK; @@ -631,7 +615,6 @@ static const TranslatorOps hexagon_tr_ops =3D { .init_disas_context =3D hexagon_tr_init_disas_context, .tb_start =3D hexagon_tr_tb_start, .insn_start =3D hexagon_tr_insn_start, - .breakpoint_check =3D hexagon_tr_breakpoint_check, .translate_insn =3D hexagon_tr_translate_packet, .tb_stop =3D hexagon_tr_tb_stop, .disas_log =3D hexagon_tr_disas_log, diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 2552747138..b18150ef8d 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4159,16 +4159,6 @@ static void hppa_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cs) tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b); } =20 -static bool hppa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= s, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - gen_excp(ctx, EXCP_DEBUG); - ctx->base.pc_next +=3D 4; - return true; -} - static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); @@ -4330,7 +4320,6 @@ static const TranslatorOps hppa_tr_ops =3D { .init_disas_context =3D hppa_tr_init_disas_context, .tb_start =3D hppa_tr_tb_start, .insn_start =3D hppa_tr_insn_start, - .breakpoint_check =3D hppa_tr_breakpoint_check, .translate_insn =3D hppa_tr_translate_insn, .tb_stop =3D hppa_tr_tb_stop, .disas_log =3D hppa_tr_disas_log, diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 8520d5a1e2..aacb605eee 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2604,14 +2604,6 @@ static void gen_interrupt(DisasContext *s, int intno, s->base.is_jmp =3D DISAS_NORETURN; } =20 -static void gen_debug(DisasContext *s) -{ - gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); - gen_helper_debug(cpu_env); - s->base.is_jmp =3D DISAS_NORETURN; -} - static void gen_set_hflag(DisasContext *s, uint32_t mask) { if ((s->flags & mask) =3D=3D 0) { @@ -8635,25 +8627,6 @@ static void i386_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); } =20 -static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= pu, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - /* If RF is set, suppress an internally generated breakpoint. */ - int flags =3D dc->base.tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY; - if (bp->flags & flags) { - gen_debug(dc); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the generic logic setting tb->size later does the right thing. = */ - dc->base.pc_next +=3D 1; - return true; - } else { - return false; - } -} - static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -8721,7 +8694,6 @@ static const TranslatorOps i386_tr_ops =3D { .init_disas_context =3D i386_tr_init_disas_context, .tb_start =3D i386_tr_tb_start, .insn_start =3D i386_tr_insn_start, - .breakpoint_check =3D i386_tr_breakpoint_check, .translate_insn =3D i386_tr_translate_insn, .tb_stop =3D i386_tr_tb_stop, .disas_log =3D i386_tr_disas_log, diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 1fee04b8dd..c34d9aed61 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -6208,23 +6208,6 @@ static void m68k_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); } =20 -static bool m68k_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= pu, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - gen_exception(dc, dc->base.pc_next, EXCP_DEBUG); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - dc->base.pc_next +=3D 2; - - return true; -} - static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -6310,7 +6293,6 @@ static const TranslatorOps m68k_tr_ops =3D { .init_disas_context =3D m68k_tr_init_disas_context, .tb_start =3D m68k_tr_tb_start, .insn_start =3D m68k_tr_insn_start, - .breakpoint_check =3D m68k_tr_breakpoint_check, .translate_insn =3D m68k_tr_translate_insn, .tb_stop =3D m68k_tr_tb_stop, .disas_log =3D m68k_tr_disas_log, diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index c68a84a219..a14ffed784 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1673,23 +1673,6 @@ static void mb_tr_insn_start(DisasContextBase *dcb, = CPUState *cs) dc->insn_start =3D tcg_last_op(); } =20 -static bool mb_tr_breakpoint_check(DisasContextBase *dcb, CPUState *cs, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcb, DisasContext, base); - - gen_raise_exception_sync(dc, EXCP_DEBUG); - - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - dc->base.pc_next +=3D 4; - return true; -} - static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) { DisasContext *dc =3D container_of(dcb, DisasContext, base); @@ -1854,7 +1837,6 @@ static const TranslatorOps mb_tr_ops =3D { .init_disas_context =3D mb_tr_init_disas_context, .tb_start =3D mb_tr_tb_start, .insn_start =3D mb_tr_insn_start, - .breakpoint_check =3D mb_tr_breakpoint_check, .translate_insn =3D mb_tr_translate_insn, .tb_stop =3D mb_tr_tb_stop, .disas_log =3D mb_tr_disas_log, diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index fd980ea966..5b03545f09 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -16178,24 +16178,6 @@ static void mips_tr_insn_start(DisasContextBase *d= cbase, CPUState *cs) ctx->btarget); } =20 -static bool mips_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= s, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - save_cpu_state(ctx, 1); - ctx->base.is_jmp =3D DISAS_NORETURN; - gen_helper_raise_exception_debug(cpu_env); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - ctx->base.pc_next +=3D 4; - return true; -} - static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { CPUMIPSState *env =3D cs->env_ptr; @@ -16303,7 +16285,6 @@ static const TranslatorOps mips_tr_ops =3D { .init_disas_context =3D mips_tr_init_disas_context, .tb_start =3D mips_tr_tb_start, .insn_start =3D mips_tr_insn_start, - .breakpoint_check =3D mips_tr_breakpoint_check, .translate_insn =3D mips_tr_translate_insn, .tb_stop =3D mips_tr_tb_stop, .disas_log =3D mips_tr_disas_log, diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 17742cebc7..08d7ac5398 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -744,16 +744,6 @@ static const char * const regnames[] =3D { =20 #include "exec/gen-icount.h" =20 -static void gen_exception(DisasContext *dc, uint32_t excp) -{ - TCGv_i32 tmp =3D tcg_const_i32(excp); - - tcg_gen_movi_tl(cpu_R[R_PC], dc->pc); - gen_helper_raise_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); - dc->base.is_jmp =3D DISAS_NORETURN; -} - /* generate intermediate code for basic block 'tb'. */ static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) { @@ -777,22 +767,6 @@ static void nios2_tr_insn_start(DisasContextBase *dcba= se, CPUState *cs) tcg_gen_insn_start(dcbase->pc_next); } =20 -static bool nios2_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *= cs, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - gen_exception(dc, EXCP_DEBUG); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - dc->base.pc_next +=3D 4; - return true; -} - static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -870,7 +844,6 @@ static const TranslatorOps nios2_tr_ops =3D { .init_disas_context =3D nios2_tr_init_disas_context, .tb_start =3D nios2_tr_tb_start, .insn_start =3D nios2_tr_insn_start, - .breakpoint_check =3D nios2_tr_breakpoint_check, .translate_insn =3D nios2_tr_translate_insn, .tb_stop =3D nios2_tr_tb_stop, .disas_log =3D nios2_tr_disas_log, diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 059da48475..d6ea536744 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1609,22 +1609,6 @@ static void openrisc_tr_insn_start(DisasContextBase = *dcbase, CPUState *cs) | (dc->base.num_insns > 1 ? 2 : 0)); } =20 -static bool openrisc_tr_breakpoint_check(DisasContextBase *dcbase, CPUStat= e *cs, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); - gen_exception(dc, EXCP_DEBUG); - dc->base.is_jmp =3D DISAS_NORETURN; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next +=3D 4; - return true; -} - static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState = *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -1727,7 +1711,6 @@ static const TranslatorOps openrisc_tr_ops =3D { .init_disas_context =3D openrisc_tr_init_disas_context, .tb_start =3D openrisc_tr_tb_start, .insn_start =3D openrisc_tr_insn_start, - .breakpoint_check =3D openrisc_tr_breakpoint_check, .translate_insn =3D openrisc_tr_translate_insn, .tb_stop =3D openrisc_tr_tb_stop, .disas_log =3D openrisc_tr_disas_log, diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0a55cb7181..171b216e17 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -8565,23 +8565,6 @@ static void ppc_tr_insn_start(DisasContextBase *dcba= se, CPUState *cs) tcg_gen_insn_start(dcbase->pc_next); } =20 -static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - gen_update_nip(ctx, ctx->base.pc_next); - gen_debug_exception(ctx); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be properly - * cleared -- thus we increment the PC here so that the logic - * setting tb->size below does the right thing. - */ - ctx->base.pc_next +=3D 4; - return true; -} - static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) { REQUIRE_INSNS_FLAGS2(ctx, ISA310); @@ -8710,7 +8693,6 @@ static const TranslatorOps ppc_tr_ops =3D { .init_disas_context =3D ppc_tr_init_disas_context, .tb_start =3D ppc_tr_tb_start, .insn_start =3D ppc_tr_insn_start, - .breakpoint_check =3D ppc_tr_breakpoint_check, .translate_insn =3D ppc_tr_translate_insn, .tb_stop =3D ppc_tr_tb_stop, .disas_log =3D ppc_tr_disas_log, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index deda0c8a44..6983be5723 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -961,22 +961,6 @@ static void riscv_tr_insn_start(DisasContextBase *dcba= se, CPUState *cpu) tcg_gen_insn_start(ctx->base.pc_next); } =20 -static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *= cpu, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - ctx->base.is_jmp =3D DISAS_NORETURN; - gen_exception_debug(); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx->base.pc_next +=3D 4; - return true; -} - static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); @@ -1029,7 +1013,6 @@ static const TranslatorOps riscv_tr_ops =3D { .init_disas_context =3D riscv_tr_init_disas_context, .tb_start =3D riscv_tr_tb_start, .insn_start =3D riscv_tr_insn_start, - .breakpoint_check =3D riscv_tr_breakpoint_check, .translate_insn =3D riscv_tr_translate_insn, .tb_stop =3D riscv_tr_tb_stop, .disas_log =3D riscv_tr_disas_log, diff --git a/target/rx/translate.c b/target/rx/translate.c index 23a626438a..a3cf720455 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2309,19 +2309,6 @@ static void rx_tr_insn_start(DisasContextBase *dcbas= e, CPUState *cs) tcg_gen_insn_start(ctx->base.pc_next); } =20 -static bool rx_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - /* We have hit a breakpoint - make sure PC is up-to-date */ - tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); - gen_helper_debug(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - ctx->base.pc_next +=3D 1; - return true; -} - static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); @@ -2373,7 +2360,6 @@ static const TranslatorOps rx_tr_ops =3D { .init_disas_context =3D rx_tr_init_disas_context, .tb_start =3D rx_tr_tb_start, .insn_start =3D rx_tr_insn_start, - .breakpoint_check =3D rx_tr_breakpoint_check, .translate_insn =3D rx_tr_translate_insn, .tb_stop =3D rx_tr_tb_stop, .disas_log =3D rx_tr_disas_log, diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 92fa7656c2..0632b0374b 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6552,29 +6552,6 @@ static void s390x_tr_insn_start(DisasContextBase *dc= base, CPUState *cs) { } =20 -static bool s390x_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *= cs, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - /* - * Emit an insn_start to accompany the breakpoint exception. - * The ILEN value is a dummy, since this does not result in - * an s390x exception, but an internal qemu exception which - * brings us back to interact with the gdbstub. - */ - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 2); - - dc->base.is_jmp =3D DISAS_PC_STALE; - dc->do_debug =3D true; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size does the right thing. */ - dc->base.pc_next +=3D 2; - return true; -} - static void s390x_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { CPUS390XState *env =3D cs->env_ptr; @@ -6642,7 +6619,6 @@ static const TranslatorOps s390x_tr_ops =3D { .init_disas_context =3D s390x_tr_init_disas_context, .tb_start =3D s390x_tr_tb_start, .insn_start =3D s390x_tr_insn_start, - .breakpoint_check =3D s390x_tr_breakpoint_check, .translate_insn =3D s390x_tr_translate_insn, .tb_stop =3D s390x_tr_tb_stop, .disas_log =3D s390x_tr_disas_log, diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 40898e2393..8704fea1ca 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2289,23 +2289,6 @@ static void sh4_tr_insn_start(DisasContextBase *dcba= se, CPUState *cs) tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags); } =20 -static bool sh4_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - /* We have hit a breakpoint - make sure PC is up-to-date */ - gen_save_cpu_state(ctx, true); - gen_helper_debug(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx->base.pc_next +=3D 2; - return true; -} - static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { CPUSH4State *env =3D cs->env_ptr; @@ -2369,7 +2352,6 @@ static const TranslatorOps sh4_tr_ops =3D { .init_disas_context =3D sh4_tr_init_disas_context, .tb_start =3D sh4_tr_tb_start, .insn_start =3D sh4_tr_insn_start, - .breakpoint_check =3D sh4_tr_breakpoint_check, .translate_insn =3D sh4_tr_translate_insn, .tb_stop =3D sh4_tr_tb_stop, .disas_log =3D sh4_tr_disas_log, diff --git a/target/sparc/translate.c b/target/sparc/translate.c index e530cb4aa8..11de5a4963 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5854,22 +5854,6 @@ static void sparc_tr_insn_start(DisasContextBase *dc= base, CPUState *cs) } } =20 -static bool sparc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *= cs, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - if (dc->pc !=3D dc->base.pc_first) { - save_state(dc); - } - gen_helper_debug(cpu_env); - tcg_gen_exit_tb(NULL, 0); - dc->base.is_jmp =3D DISAS_NORETURN; - /* update pc_next so that the current instruction is included in tb->s= ize */ - dc->base.pc_next +=3D 4; - return true; -} - static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -5932,7 +5916,6 @@ static const TranslatorOps sparc_tr_ops =3D { .init_disas_context =3D sparc_tr_init_disas_context, .tb_start =3D sparc_tr_tb_start, .insn_start =3D sparc_tr_insn_start, - .breakpoint_check =3D sparc_tr_breakpoint_check, .translate_insn =3D sparc_tr_translate_insn, .tb_stop =3D sparc_tr_tb_stop, .disas_log =3D sparc_tr_disas_log, diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 865020754d..a0cc0f1cb3 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8810,21 +8810,6 @@ static void tricore_tr_insn_start(DisasContextBase *= dcbase, CPUState *cpu) tcg_gen_insn_start(ctx->base.pc_next); } =20 -static bool tricore_tr_breakpoint_check(DisasContextBase *dcbase, CPUState= *cpu, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - generate_qemu_excp(ctx, EXCP_DEBUG); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - ctx->base.pc_next +=3D 4; - return true; -} - static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx) { /* @@ -8898,7 +8883,6 @@ static const TranslatorOps tricore_tr_ops =3D { .init_disas_context =3D tricore_tr_init_disas_context, .tb_start =3D tricore_tr_tb_start, .insn_start =3D tricore_tr_insn_start, - .breakpoint_check =3D tricore_tr_breakpoint_check, .translate_insn =3D tricore_tr_translate_insn, .tb_stop =3D tricore_tr_tb_stop, .disas_log =3D tricore_tr_disas_log, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 7094cfcf1d..20399d6a04 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1232,22 +1232,6 @@ static void xtensa_tr_insn_start(DisasContextBase *d= cbase, CPUState *cpu) tcg_gen_insn_start(dcbase->pc_next); } =20 -static bool xtensa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState = *cpu, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); - gen_exception(dc, EXCP_DEBUG); - dc->base.is_jmp =3D DISAS_NORETURN; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next +=3D 2; - return true; -} - static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *c= pu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -1330,7 +1314,6 @@ static const TranslatorOps xtensa_translator_ops =3D { .init_disas_context =3D xtensa_tr_init_disas_context, .tb_start =3D xtensa_tr_tb_start, .insn_start =3D xtensa_tr_insn_start, - .breakpoint_check =3D xtensa_tr_breakpoint_check, .translate_insn =3D xtensa_tr_translate_insn, .tb_stop =3D xtensa_tr_tb_stop, .disas_log =3D xtensa_tr_disas_log, --=20 2.25.1 From nobody Mon May 13 10:52:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626811837450212.7242571881643; Tue, 20 Jul 2021 13:10:37 -0700 (PDT) Received: from localhost ([::1]:54714 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5w4a-0008GY-EE for importer@patchew.org; Tue, 20 Jul 2021 16:10:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55878) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5vpb-0007Qw-59 for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:55:07 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:39856) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5vpZ-0008Bz-ID for qemu-devel@nongnu.org; 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[204.210.126.223]) by smtp.gmail.com with ESMTPSA id j25sm15422179pfh.77.2021.07.20.12.55.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 12:55:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AZ4MKQyFA9AM/nKrT7V33vlow5VjeOIvrBUMrcM4oVg=; b=zlHXvJmPMsx7hwbF/dmrgYNfD1/aZBIKdRmIzugkkXXie5quda3BoPHvjqShArxea0 qPjmOJ0MB3Cyl3NBDXGuYsFrPsv2i6Yr+SuWwEYJYbpaqQJt+XhQVkPjBMtyqSQ4ecZs /uzUtxG5MARpZnVy7KkdITOWMZZvQy5Den511HUvSjMU5iNJibJo47jdt7hFG5nUzYU2 Wky6rgYQaq8lOYBnEhyoWwwPz0B5I7CNVGgSwcSsHErUfiNf9VLpz3XXgzWZKiZFun2C 6IBbJwdc7H4gwqpnOCLjKlIXUrO5s0ymyrNi1J8qQiCCTvvwcoFK5I1yaIlBgDdVGa5Z d92g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AZ4MKQyFA9AM/nKrT7V33vlow5VjeOIvrBUMrcM4oVg=; b=PfPsmNbtHQTlp0hamWVDd4JqULLnm5kYP7jsGwRvh067FfhGltDCXC5BlJAZosKihj TYMi8vQQZBA9MEVfg66cVQu2FVMV/mzwlplkORezhe2iAylqClA/NPZ534sFr4k1924T BfAzlFAnJNMqMM1jMRup1fqetqTKBx6UuPzN/fJZMoVgW+jE+bsj4cH9EQYywxQVavDU CB0g26M9oDdPGSSCWhcjxBHN+VkWNQG/df8aAfjHXMtQW2JohfKQ+kDRfolAPzhBbr0O g4C4C3kpyh/lJzd88OG16ZvsD4/LslNnr6n+/FYoaVJVccKM+u0LJN6aFT1tETjpurWn pwtA== X-Gm-Message-State: AOAM5322manT4Zgs/med7nFHGF55tJssfKWAafC/s5w9yuis9NWKKSFy YZ42FpccGtLYBeKs9xaQXqJThLEMWzMwwA== X-Google-Smtp-Source: ABdhPJwIJ7+Gi++UkKhrhDO74IsG8M6cVVAauI3zwmeWcSCST4h2UfFvTnkLBT53W1J9amEwHgY6Ow== X-Received: by 2002:aa7:90c9:0:b029:307:49ca:dedd with SMTP id k9-20020aa790c90000b029030749cadeddmr33477869pfk.9.1626810904116; Tue, 20 Jul 2021 12:55:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v6 16/17] accel/tcg: Hoist tb_cflags to a local in translator_loop Date: Tue, 20 Jul 2021 09:54:38 -1000 Message-Id: <20210720195439.626594-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720195439.626594-1-richard.henderson@linaro.org> References: <20210720195439.626594-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626811838219100001 The access internal to tb_cflags() is atomic. Avoid re-reading it as such for the multiple uses. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Tested-by: Mark Cave-Ayland --- accel/tcg/translator.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 4f3728c278..b45337f3ba 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -50,6 +50,7 @@ bool translator_use_goto_tb(DisasContextBase *db, target_= ulong dest) void translator_loop(const TranslatorOps *ops, DisasContextBase *db, CPUState *cpu, TranslationBlock *tb, int max_insns) { + uint32_t cflags =3D tb_cflags(tb); bool plugin_enabled; =20 /* Initialize DisasContext */ @@ -72,8 +73,7 @@ void translator_loop(const TranslatorOps *ops, DisasConte= xtBase *db, ops->tb_start(db, cpu); tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ =20 - plugin_enabled =3D plugin_gen_tb_start(cpu, tb, - tb_cflags(db->tb) & CF_MEMI_ONLY); + plugin_enabled =3D plugin_gen_tb_start(cpu, tb, cflags & CF_MEMI_ONLY); =20 while (true) { db->num_insns++; @@ -88,14 +88,13 @@ void translator_loop(const TranslatorOps *ops, DisasCon= textBase *db, update db->pc_next and db->is_jmp to indicate what should be done next -- either exiting this loop or locate the start of the next instruction. */ - if (db->num_insns =3D=3D db->max_insns - && (tb_cflags(db->tb) & CF_LAST_IO)) { + if (db->num_insns =3D=3D db->max_insns && (cflags & CF_LAST_IO)) { /* Accept I/O on the last instruction. */ gen_io_start(); ops->translate_insn(db, cpu); } else { /* we should only see CF_MEMI_ONLY for io_recompile */ - tcg_debug_assert(!(tb_cflags(db->tb) & CF_MEMI_ONLY)); + tcg_debug_assert(!(cflags & CF_MEMI_ONLY)); ops->translate_insn(db, cpu); } =20 --=20 2.25.1 From nobody Mon May 13 10:52:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626812029902207.1798821897961; Tue, 20 Jul 2021 13:13:49 -0700 (PDT) Received: from localhost ([::1]:34930 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5w7g-0005YC-OD for importer@patchew.org; Tue, 20 Jul 2021 16:13:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55892) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5vpc-0007Wb-Kr for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:55:08 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]:46663) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5vpa-0008Ck-P9 for qemu-devel@nongnu.org; Tue, 20 Jul 2021 15:55:08 -0400 Received: by mail-pl1-x632.google.com with SMTP id c15so11944877pls.13 for ; Tue, 20 Jul 2021 12:55:06 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id j25sm15422179pfh.77.2021.07.20.12.55.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jul 2021 12:55:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wpCm80kgLZbyypXRy+NSC5PGXOWFkDjMVeqOCfwZ1jY=; b=PDLSAOq6BrH4dwJDPkmiZUDimJ3aCYprwGmV5fNoxjHgGw+C5NYwlpDTQJCC9h1u5X q05jtFa+Ar8iubci3Nt4WPJ5J/TnmMqpUiKXXhlJP7YODPx8/syL/+dFyox282l9geVV wTKOvzSxpmctmFsT/VbN3KKL6OuTE0TBLG8Wg3X1hH8xKFNI5VoJbbhoT3qltiaWHEL6 zCNPuoHgEMNZH7ykbW31xip6iKLAcBi6eVkjTLJk+JnTwF4aw7+FfS0MobLuYxG2++it h4fUZDn7V03dgGX87oVJSuQD+dVHe4l3z/uNqGywYwgsEetS+c4Un1UOTrJQOSuhg2c0 1EHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wpCm80kgLZbyypXRy+NSC5PGXOWFkDjMVeqOCfwZ1jY=; b=aC5hmvv8m5FFgvn8z6qk6d71c79tNlgK74O1kyZoET9uEy1caRyByAch+/nvL+JuIc KlBzTZ03WoRqCnZTwofx7AhkWEITahc47MmUwqxYSjb4wKeG5sHIgzhi0N3zVD1VO2QP hSDZjiFvHmOM+aaeuU/vZAhZ9cOfYW8+gCHrpWq9+UYKyD1JCswRfVRVUl1O5814m7e7 x0oWo+66jMkAS7QdjowIisFahRSU5uGO0reiWIZCNftfBb6/xysXcVZ3+alP0D++Qssw YnuXlkm8/eAEoCmNzUSA9T5SEzr2TxTCpWCy3BbCMSyCdYe9cr31zQnFwJ3/UeSclQqY dBAw== X-Gm-Message-State: AOAM5319wLNy7TI8zr0YEAK12rdNNutr1cHdmTFitqPBnJBFr0euhjVs wsdoR4xmzC+BEhj9+LehrnUNJIOikFFwLg== X-Google-Smtp-Source: ABdhPJxwMiPkCqxZeThhF5tUCqCXPH2RgbSMDRpWEX3DA+UJdiH9oif1Qh9HmhQ9O3rj8do8q9Xwog== X-Received: by 2002:a17:90a:b63:: with SMTP id 90mr31397749pjq.58.1626810905510; Tue, 20 Jul 2021 12:55:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v6 17/17] accel/tcg: Record singlestep_enabled in tb->cflags Date: Tue, 20 Jul 2021 09:54:39 -1000 Message-Id: <20210720195439.626594-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720195439.626594-1-richard.henderson@linaro.org> References: <20210720195439.626594-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626812031796100001 Content-Type: text/plain; charset="utf-8" Set CF_SINGLE_STEP when single-stepping is enabled. This avoids the need to flush all tb's when turning single-stepping on or off. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Tested-by: Mark Cave-Ayland --- include/exec/exec-all.h | 1 + accel/tcg/cpu-exec.c | 7 ++++++- accel/tcg/translate-all.c | 4 ---- accel/tcg/translator.c | 7 +------ cpu.c | 4 ---- 5 files changed, 8 insertions(+), 15 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 6873cce8df..5d1b6d80fb 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -497,6 +497,7 @@ struct TranslationBlock { #define CF_COUNT_MASK 0x000001ff #define CF_NO_GOTO_TB 0x00000200 /* Do not chain with goto_tb */ #define CF_NO_GOTO_PTR 0x00000400 /* Do not chain with goto_ptr */ +#define CF_SINGLE_STEP 0x00000800 /* gdbstub single-step in effect */ #define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ #define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ #define CF_USE_ICOUNT 0x00020000 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5cc6363f4c..fc895cf51e 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -150,10 +150,15 @@ uint32_t curr_cflags(CPUState *cpu) uint32_t cflags =3D cpu->tcg_cflags; =20 /* + * Record gdb single-step. We should be exiting the TB by raising + * EXCP_DEBUG, but to simplify other tests, disable chaining too. + * * For singlestep and -d nochain, suppress goto_tb so that * we can log -d cpu,exec after every TB. */ - if (singlestep) { + if (unlikely(cpu->singlestep_enabled)) { + cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR | CF_SINGLE_STEP | 1; + } else if (singlestep) { cflags |=3D CF_NO_GOTO_TB | 1; } else if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { cflags |=3D CF_NO_GOTO_TB; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bf82c15aab..bbfcfb698c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1432,10 +1432,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } QEMU_BUILD_BUG_ON(CF_COUNT_MASK + 1 !=3D TCG_MAX_INSNS); =20 - if (cpu->singlestep_enabled) { - max_insns =3D 1; - } - buffer_overflow: tb =3D tcg_tb_alloc(tcg_ctx); if (unlikely(!tb)) { diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index b45337f3ba..c53a7f8e44 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -38,11 +38,6 @@ bool translator_use_goto_tb(DisasContextBase *db, target= _ulong dest) return false; } =20 - /* Suppress goto_tb in the case of single-steping. */ - if (db->singlestep_enabled) { - return false; - } - /* Check for the dest on the same page as the start of the TB. */ return ((db->pc_first ^ dest) & TARGET_PAGE_MASK) =3D=3D 0; } @@ -60,7 +55,7 @@ void translator_loop(const TranslatorOps *ops, DisasConte= xtBase *db, db->is_jmp =3D DISAS_NEXT; db->num_insns =3D 0; db->max_insns =3D max_insns; - db->singlestep_enabled =3D cpu->singlestep_enabled; + db->singlestep_enabled =3D cflags & CF_SINGLE_STEP; =20 ops->init_disas_context(db, cpu); tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ diff --git a/cpu.c b/cpu.c index d6ae5ae581..e1799a15bc 100644 --- a/cpu.c +++ b/cpu.c @@ -326,10 +326,6 @@ void cpu_single_step(CPUState *cpu, int enabled) cpu->singlestep_enabled =3D enabled; if (kvm_enabled()) { kvm_update_guest_debug(cpu, 0); - } else { - /* must flush all the translated code to avoid inconsistencies= */ - /* XXX: only flush what is necessary */ - tb_flush(cpu); } trace_breakpoint_singlestep(cpu->cpu_index, enabled); } --=20 2.25.1