From nobody Tue Feb 10 00:59:43 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1626784584; cv=none; d=zohomail.com; s=zohoarc; b=dXgwmWPiwIBEj9o6Fnbfc/2+Fdbn7vIG/6dyMsRwmbd7YwwyiaEQ+S9Swcuf8nLxlFEyrpTMlPmJ0BLH7h03IY9nGCRYV+o3LX6YK4CI5DiCuBTxvSKFNncy4OxHJ9tVktcKH426s9uJ6//X2fg9V9DeR9iJ5+U9561KRFozrM8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626784584; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=oZJDtPPnQgkRRLJKi58MD/EsmW1gPlLMEVQEbaQvZbA=; b=nwQkdwoQ2InEJNSmkjgxJRoIyAMw31/7Se+liHI3i9XsW5XOhGrU2fTmNll2EmreoRfA/Wt3RbKBj3yOUZmVIpIA3SyMeoeyiziBYkAA2oXeaeoPgG1bk63U0hgXUfa190YnUhVgTufWBRs7DgOZ0/ThpXT8n3xt5cT8E5G766E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626784584165391.61528560254135; Tue, 20 Jul 2021 05:36:24 -0700 (PDT) Received: from localhost ([::1]:36050 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5oz1-0004RO-35 for importer@patchew.org; Tue, 20 Jul 2021 08:36:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46288) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5otj-0004Tk-Sw for qemu-devel@nongnu.org; Tue, 20 Jul 2021 08:30:55 -0400 Received: from rev.ng ([5.9.113.41]:47295) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5oth-0004en-84 for qemu-devel@nongnu.org; Tue, 20 Jul 2021 08:30:55 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:Content-Type:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive; bh=oZJDtPPnQgkRRLJKi58MD/EsmW1gPlLMEVQEbaQvZbA=; b=Xt9td+cPw9dFL6ci9nqKJUhx+8 J4/Nmd6srmjVpt8SVBeOGTFLlfcxSYoba6dNKTRaeoube4hr51vN/EUY4xC7+qCTSHbVozQsXfvfr Zv7+WZaPsB/m63HY+DE664eWBx0h9z6V2iQRNwO/SxJ5LmhEj8M1U5ojz2WPsqKWREak=; To: qemu-devel@nongnu.org Cc: tsimpson@quicinc.com, bcain@quicinc.com, babush@rev.ng, nizzo@rev.ng, richard.henderson@linaro.org, Alessandro Di Federico Subject: [PATCH v6 04/12] target/hexagon: make helper functions non-static Date: Tue, 20 Jul 2021 14:30:23 +0200 Message-Id: <20210720123031.1101682-5-ale.qemu@rev.ng> In-Reply-To: <20210720123031.1101682-1-ale.qemu@rev.ng> References: <20210720123031.1101682-1-ale.qemu@rev.ng> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.9.113.41; envelope-from=ale@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Alessandro Di Federico From: Alessandro Di Federico via X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626784585370100001 Content-Type: text/plain; charset="utf-8" From: Paolo Montesel Make certain helper functions non-static, making them available outside genptr.c. These functions are required by code generated by the idef-parser. This commit also makes some op_helper.c non-static in order to avoid having them marked as unused when using the idef-parser generated code. Signed-off-by: Alessandro Di Federico Signed-off-by: Paolo Montesel Reviewed-by: Richard Henderson Reviewed-by: Taylor Simpson --- target/hexagon/genptr.h | 30 +++++++++++++++++++ target/hexagon/op_helper.h | 37 ++++++++++++++++++++++++ target/hexagon/genptr.c | 59 +++++++++++++++++++++----------------- target/hexagon/op_helper.c | 29 +++++++++---------- 4 files changed, 113 insertions(+), 42 deletions(-) create mode 100644 target/hexagon/op_helper.h diff --git a/target/hexagon/genptr.h b/target/hexagon/genptr.h index c158005d2a..d71dd7e1ce 100644 --- a/target/hexagon/genptr.h +++ b/target/hexagon/genptr.h @@ -19,7 +19,37 @@ #define HEXAGON_GENPTR_H =20 #include "insn.h" +#include "tcg/tcg.h" +#include "translate.h" =20 extern const SemanticInsn opcode_genptr[]; =20 +void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot); +void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + uint32_t slot); +void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + uint32_t slot); +void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + uint32_t slot); +void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, DisasContext *= ctx, + uint32_t slot); +void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *= ctx, + uint32_t slot); +void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *= ctx, + uint32_t slot); +void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *= ctx, + uint32_t slot); +void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, DisasContext *= ctx, + uint32_t slot); +TCGv gen_read_preg(TCGv pred, uint8_t num); +void gen_log_reg_write(int rnum, TCGv val); +void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val); +TCGv gen_8bitsof(TCGv result, TCGv value); +void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src); +TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign); +TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign); +TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign); +void gen_set_half(int N, TCGv result, TCGv src); +void gen_set_half_i64(int N, TCGv_i64 result, TCGv src); + #endif diff --git a/target/hexagon/op_helper.h b/target/hexagon/op_helper.h new file mode 100644 index 0000000000..2d39637b8f --- /dev/null +++ b/target/hexagon/op_helper.h @@ -0,0 +1,37 @@ +/* + * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_OP_HELPER_H +#define HEXAGON_OP_HELPER_H + +/* Misc functions */ +void cancel_slot(CPUHexagonState *env, uint32_t slot); +void write_new_pc(CPUHexagonState *env, target_ulong addr); + +uint8_t mem_load1(CPUHexagonState *env, uint32_t slot, target_ulong vaddr); +uint16_t mem_load2(CPUHexagonState *env, uint32_t slot, target_ulong vaddr= ); +uint32_t mem_load4(CPUHexagonState *env, uint32_t slot, target_ulong vaddr= ); +uint64_t mem_load8(CPUHexagonState *env, uint32_t slot, target_ulong vaddr= ); + +void log_reg_write(CPUHexagonState *env, int rnum, target_ulong val, + uint32_t slot); +void log_store64(CPUHexagonState *env, target_ulong addr, int64_t val, + int width, int slot); +void log_store32(CPUHexagonState *env, target_ulong addr, target_ulong val, + int width, int slot); + +#endif diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 2c7f4136b5..5e7f446657 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -26,6 +26,13 @@ #include "macros.h" #undef QEMU_GENERATE #include "gen_tcg.h" +#include "genptr.h" + +TCGv gen_read_preg(TCGv pred, uint8_t num) +{ + tcg_gen_mov_tl(pred, hex_pred[num]); + return pred; +} =20 static inline void gen_log_predicated_reg_write(int rnum, TCGv val, uint32_t slot) @@ -52,7 +59,7 @@ static inline void gen_log_predicated_reg_write(int rnum,= TCGv val, tcg_temp_free(slot_mask); } =20 -static inline void gen_log_reg_write(int rnum, TCGv val) +void gen_log_reg_write(int rnum, TCGv val) { tcg_gen_mov_tl(hex_new_value[rnum], val); if (HEX_DEBUG) { @@ -115,7 +122,7 @@ static void gen_log_reg_write_pair(int rnum, TCGv_i64 v= al) } } =20 -static inline void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv va= l) +void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val) { TCGv base_val =3D tcg_temp_new(); =20 @@ -255,7 +262,7 @@ static inline void gen_write_ctrl_reg_pair(DisasContext= *ctx, int reg_num, } } =20 -static TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign) +TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign) { if (sign) { tcg_gen_sextract_tl(result, src, N * 8, 8); @@ -265,7 +272,7 @@ static TCGv gen_get_byte(TCGv result, int N, TCGv src, = bool sign) return result; } =20 -static TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign) +TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign) { TCGv_i64 res64 =3D tcg_temp_new_i64(); if (sign) { @@ -279,7 +286,7 @@ static TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i= 64 src, bool sign) return result; } =20 -static inline TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign) +TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign) { if (sign) { tcg_gen_sextract_tl(result, src, N * 16, 16); @@ -289,12 +296,12 @@ static inline TCGv gen_get_half(TCGv result, int N, T= CGv src, bool sign) return result; } =20 -static inline void gen_set_half(int N, TCGv result, TCGv src) +void gen_set_half(int N, TCGv result, TCGv src) { tcg_gen_deposit_tl(result, result, src, N * 16, 16); } =20 -static inline void gen_set_half_i64(int N, TCGv_i64 result, TCGv src) +void gen_set_half_i64(int N, TCGv_i64 result, TCGv src) { TCGv_i64 src64 =3D tcg_temp_new_i64(); tcg_gen_extu_i32_i64(src64, src); @@ -302,7 +309,7 @@ static inline void gen_set_half_i64(int N, TCGv_i64 res= ult, TCGv src) tcg_temp_free_i64(src64); } =20 -static void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src) +void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src) { TCGv_i64 src64 =3D tcg_temp_new_i64(); tcg_gen_extu_i32_i64(src64, src); @@ -381,60 +388,60 @@ static inline void gen_store_conditional8(DisasContex= t *ctx, tcg_gen_movi_tl(hex_llsc_addr, ~0); } =20 -static inline void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t s= lot) +void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot) { tcg_gen_mov_tl(hex_store_addr[slot], vaddr); tcg_gen_movi_tl(hex_store_width[slot], width); tcg_gen_mov_tl(hex_store_val32[slot], src); } =20 -static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, - DisasContext *ctx, uint32_t slot) +void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + uint32_t slot) { gen_store32(vaddr, src, 1, slot); ctx->store_width[slot] =3D 1; } =20 -static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, - DisasContext *ctx, uint32_t slot) +void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *= ctx, + uint32_t slot) { TCGv tmp =3D tcg_const_tl(src); gen_store1(cpu_env, vaddr, tmp, ctx, slot); tcg_temp_free(tmp); } =20 -static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, - DisasContext *ctx, uint32_t slot) +void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + uint32_t slot) { gen_store32(vaddr, src, 2, slot); ctx->store_width[slot] =3D 2; } =20 -static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, - DisasContext *ctx, uint32_t slot) +void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *= ctx, + uint32_t slot) { TCGv tmp =3D tcg_const_tl(src); gen_store2(cpu_env, vaddr, tmp, ctx, slot); tcg_temp_free(tmp); } =20 -static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, - DisasContext *ctx, uint32_t slot) +void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, DisasContext *ctx, + uint32_t slot) { gen_store32(vaddr, src, 4, slot); ctx->store_width[slot] =3D 4; } =20 -static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, - DisasContext *ctx, uint32_t slot) +void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, DisasContext *= ctx, + uint32_t slot) { TCGv tmp =3D tcg_const_tl(src); gen_store4(cpu_env, vaddr, tmp, ctx, slot); tcg_temp_free(tmp); } =20 -static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, - DisasContext *ctx, uint32_t slot) +void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, DisasContext *= ctx, + uint32_t slot) { tcg_gen_mov_tl(hex_store_addr[slot], vaddr); tcg_gen_movi_tl(hex_store_width[slot], 8); @@ -442,15 +449,15 @@ static inline void gen_store8(TCGv_env cpu_env, TCGv = vaddr, TCGv_i64 src, ctx->store_width[slot] =3D 8; } =20 -static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, - DisasContext *ctx, uint32_t slot) +void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, DisasContext *= ctx, + uint32_t slot) { TCGv_i64 tmp =3D tcg_const_i64(src); gen_store8(cpu_env, vaddr, tmp, ctx, slot); tcg_temp_free_i64(tmp); } =20 -static TCGv gen_8bitsof(TCGv result, TCGv value) +TCGv gen_8bitsof(TCGv result, TCGv value) { TCGv zero =3D tcg_const_tl(0); TCGv ones =3D tcg_const_tl(0xff); diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 459555966d..a864e68837 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -25,6 +25,7 @@ #include "arch.h" #include "hex_arch_types.h" #include "fma_emu.h" +#include "op_helper.h" =20 #define SF_BIAS 127 #define SF_MANTBITS 23 @@ -45,8 +46,8 @@ void QEMU_NORETURN HELPER(raise_exception)(CPUHexagonStat= e *env, uint32_t excp) do_raise_exception_err(env, excp, 0); } =20 -static void log_reg_write(CPUHexagonState *env, int rnum, - target_ulong val, uint32_t slot) +void log_reg_write(CPUHexagonState *env, int rnum, target_ulong val, + uint32_t slot) { HEX_DEBUG_LOG("log_reg_write[%d] =3D " TARGET_FMT_ld " (0x" TARGET_FMT= _lx ")", rnum, val, val); @@ -77,8 +78,8 @@ static void log_pred_write(CPUHexagonState *env, int pnum= , target_ulong val) } } =20 -static void log_store32(CPUHexagonState *env, target_ulong addr, - target_ulong val, int width, int slot) +void log_store32(CPUHexagonState *env, target_ulong addr, target_ulong val, + int width, int slot) { HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx ", %" PRId32 " [0x08%" PRIx32 "])\n", @@ -88,8 +89,8 @@ static void log_store32(CPUHexagonState *env, target_ulon= g addr, env->mem_log_stores[slot].data32 =3D val; } =20 -static void log_store64(CPUHexagonState *env, target_ulong addr, - int64_t val, int width, int slot) +void log_store64(CPUHexagonState *env, target_ulong addr, int64_t val, + int width, int slot) { HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx ", %" PRId64 " [0x016%" PRIx64 "])\n", @@ -99,7 +100,7 @@ static void log_store64(CPUHexagonState *env, target_ulo= ng addr, env->mem_log_stores[slot].data64 =3D val; } =20 -static void write_new_pc(CPUHexagonState *env, target_ulong addr) +void write_new_pc(CPUHexagonState *env, target_ulong addr) { HEX_DEBUG_LOG("write_new_pc(0x" TARGET_FMT_lx ")\n", addr); =20 @@ -390,8 +391,7 @@ static void check_noshuf(CPUHexagonState *env, uint32_t= slot) } } =20 -static uint8_t mem_load1(CPUHexagonState *env, uint32_t slot, - target_ulong vaddr) +uint8_t mem_load1(CPUHexagonState *env, uint32_t slot, target_ulong vaddr) { uint8_t retval; check_noshuf(env, slot); @@ -399,8 +399,7 @@ static uint8_t mem_load1(CPUHexagonState *env, uint32_t= slot, return retval; } =20 -static uint16_t mem_load2(CPUHexagonState *env, uint32_t slot, - target_ulong vaddr) +uint16_t mem_load2(CPUHexagonState *env, uint32_t slot, target_ulong vaddr) { uint16_t retval; check_noshuf(env, slot); @@ -408,8 +407,7 @@ static uint16_t mem_load2(CPUHexagonState *env, uint32_= t slot, return retval; } =20 -static uint32_t mem_load4(CPUHexagonState *env, uint32_t slot, - target_ulong vaddr) +uint32_t mem_load4(CPUHexagonState *env, uint32_t slot, target_ulong vaddr) { uint32_t retval; check_noshuf(env, slot); @@ -417,8 +415,7 @@ static uint32_t mem_load4(CPUHexagonState *env, uint32_= t slot, return retval; } =20 -static uint64_t mem_load8(CPUHexagonState *env, uint32_t slot, - target_ulong vaddr) +uint64_t mem_load8(CPUHexagonState *env, uint32_t slot, target_ulong vaddr) { uint64_t retval; check_noshuf(env, slot); @@ -1167,7 +1164,7 @@ float64 HELPER(dfmpyhh)(CPUHexagonState *env, float64= RxxV, return RxxV; } =20 -static void cancel_slot(CPUHexagonState *env, uint32_t slot) +void cancel_slot(CPUHexagonState *env, uint32_t slot) { HEX_DEBUG_LOG("Slot %d cancelled\n", slot); env->slot_cancelled |=3D (1 << slot); --=20 2.32.0