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[204.210.126.223]) by smtp.gmail.com with ESMTPSA id e4sm25378054pgi.94.2021.07.19.18.18.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 18:18:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bSI7+FYoYzIRMvsyeEg3j2XXfVWM2GYuNosumX6OIpk=; b=IorIqQce8w2QvTZ0VE+saSKT0qw5MjLBregE6KjiXPXcgknzF0GN+z5amHHr2DRN+c ucKtqfjjtLPYSNSvf67820Dh6P9ZDReEyeaLKivzjepdeBy+YW8y3UND5fDB1x5fxNVu Kv4XL9/yj472iE/qfB/1mxyr1pZd/QzHD2jHL1ihG5ScV1DnsQd5fyzjLH97npJD8LbK seolqJLucKlGndiXCvq+jAECreRyXaFexkgSWReYt9HTqdOqD4s6JqZB0g/kv2UWj7oQ eBWAJeSYomyAOnF4pLbxYt/A4GplHW93Q3cFuTnXHzEeNvZJpyDfs6TnWArdschDjc7r Dzdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bSI7+FYoYzIRMvsyeEg3j2XXfVWM2GYuNosumX6OIpk=; b=uNb3P749VjZfE/JzSJ0kXBph+z87i3KMcMkgtlu6cmJn3CaBH0B4GSN7ijrZ0kZMmE lwpcQjubGYfJHVdTRPKUfdp2rbFKjEhcE+aT5oxhi2zOxjcibkRh1Sm8Sj18OuuC9E/h SOHW1fsbG7+dqbQXzHd2s3StyHHPcULVb0JBN4wSo+q5VQMcUf5Lse43I1bU+FJtiUEu E//3qRpPfZ/fG6/btvAvY1yAhULqidixbrWi9VypCcbOp15Rkr/RqfETHz7h7h921vE8 jFL682kM4cmZsVDYV/LIYTj9hD0dP3wUSn+b8O2zaR6kF62C98vTd671EUWhWCsYUCNI KOVg== X-Gm-Message-State: AOAM530RfvwrVzNRnlEE7vmxxy2EO+3c+AQ1zOvm+5imROhJVR1qKhsk mxeuDRj7m91dj8Y90HVC5xBtqBCPvAfB1g== X-Google-Smtp-Source: ABdhPJxzyHSytu4nOyapG/sF9psfMrxThXpbAJoogCUrkkKjOIWuN9S1AeWDPABzTLqUGqVbGblJDg== X-Received: by 2002:a17:90a:8:: with SMTP id 8mr27566137pja.102.1626743885335; Mon, 19 Jul 2021 18:18:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v5 01/15] accel/tcg: Reduce CF_COUNT_MASK to match TCG_MAX_INSNS Date: Mon, 19 Jul 2021 15:17:46 -1000 Message-Id: <20210720011800.483966-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720011800.483966-1-richard.henderson@linaro.org> References: <20210720011800.483966-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626743983630100001 The space reserved for CF_COUNT_MASK was overly large. Reduce to free up cflags bits and eliminate an extra test. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Message-Id: <20210717221851.2124573-2-richard.henderson@linaro.org> --- include/exec/exec-all.h | 4 +++- accel/tcg/translate-all.c | 5 ++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 754f4130c9..dfe82ed19c 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -492,7 +492,9 @@ struct TranslationBlock { target_ulong cs_base; /* CS base for this block */ uint32_t flags; /* flags defining in which context the code was genera= ted */ uint32_t cflags; /* compile flags */ -#define CF_COUNT_MASK 0x00007fff + +/* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */ +#define CF_COUNT_MASK 0x000001ff #define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ #define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ #define CF_USE_ICOUNT 0x00020000 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 4df26de858..5cc01d693b 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1428,11 +1428,10 @@ TranslationBlock *tb_gen_code(CPUState *cpu, =20 max_insns =3D cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { max_insns =3D TCG_MAX_INSNS; } + QEMU_BUILD_BUG_ON(CF_COUNT_MASK + 1 !=3D TCG_MAX_INSNS); + if (cpu->singlestep_enabled || singlestep) { max_insns =3D 1; } --=20 2.25.1 From nobody Sat May 18 04:13:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626744115107317.72592194693414; Mon, 19 Jul 2021 18:21:55 -0700 (PDT) Received: from localhost ([::1]:38494 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5eSH-0006FA-PJ for importer@patchew.org; Mon, 19 Jul 2021 21:21:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60970) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5eOf-0006Pz-HC for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:09 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:53053) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5eOd-0003Kr-Uj for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:09 -0400 Received: by mail-pj1-x1029.google.com with SMTP id bt15so12768583pjb.2 for ; Mon, 19 Jul 2021 18:18:07 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id e4sm25378054pgi.94.2021.07.19.18.18.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 18:18:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f8NOqQ/0TvCdkNluzWUj4pUQUbt/7JktmnpikxlNXDw=; b=ANKr35ZZgq9L7ePZbC78F5MX69Lu4G3cxTc4WoL/46Df2rREz/SkWckkdXrtSU1u97 wYeZ5cyidOEotNWNbysXwiBMa6gDrs2imn8tP3gZgO9TE8FQA3H/Q1ACLSlGyIJOtcEY C1XAqcIXOItan/6iJc82gk8R2jaWBAlZXG2lAo7ACltwLOKWbG1XEHolrnwsFd5ETrUk VEdfPH0ypcZwY0LcQBqSk+aWDNXSEVcnN3GlvAfnLGZ5qOVTowopo2nLZaO8UPgO20VW LypF7znDKLZpr5NwQRASdEP7dCm5ZPesO2sFZ7zjRtnNLhoKLRUZtmtUQzfIh/ALI+61 uWRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f8NOqQ/0TvCdkNluzWUj4pUQUbt/7JktmnpikxlNXDw=; b=PQZaj8pOd6cZ4eaXn0Vg/JjgxRq1r4Xe9I3WQJaMhBqnE96ZgQzkQNKao67FNs1B6f GDy8NF3w274KRVZOCz6YZ0BCR91ZejF0upxoQdoPPtHlRFPzoWVFCBr40y43kVazipY5 d+wXubfKfWpqggB/NgkgRTrUWZk8dFB187xbry/Eq4QezceMgW7hdrZmO7Dz/zhDf9Ym G7FSryogrEvJGpTYoOhfgDAFJyHvawMubsB5op83621VQa7zFKdbOG/Pj8CGkjQZsU1+ AJ0Vfattz6UWWSCEhfPJEIEC4P0jOolmPGkBJWTtrJ9snu2wxgHehhCxdvkpXgBmEhRt e9uA== X-Gm-Message-State: AOAM530aWqUimWj2Yp9Rx7CSc0H8IZe4PLj4lhj9m3fZ6LmtFI5mh1XN xEAMYlg7DSQRQ6lYZ+DWuYfFO9+/UIlPnw== X-Google-Smtp-Source: ABdhPJxGyNdvEXdYbmGy7RangO2NFqdxjg2a0t0t4pnm0HqB7XIuOIYcZhXmF1tIpxEcSbw/MKVhcw== X-Received: by 2002:a17:90a:b78d:: with SMTP id m13mr22013576pjr.60.1626743886715; Mon, 19 Jul 2021 18:18:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v5 02/15] accel/tcg: Move curr_cflags into cpu-exec.c Date: Mon, 19 Jul 2021 15:17:47 -1000 Message-Id: <20210720011800.483966-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720011800.483966-1-richard.henderson@linaro.org> References: <20210720011800.483966-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626744116276100003 We will shortly have more than a simple member read here, with stuff not necessarily exposed to exec/exec-all.h. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210717221851.2124573-3-richard.henderson@linaro.org> --- include/exec/exec-all.h | 5 +---- accel/tcg/cpu-exec.c | 5 +++++ 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index dfe82ed19c..ae7603ca75 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -565,10 +565,7 @@ static inline uint32_t tb_cflags(const TranslationBloc= k *tb) } =20 /* current cflags for hashing/comparison */ -static inline uint32_t curr_cflags(CPUState *cpu) -{ - return cpu->tcg_cflags; -} +uint32_t curr_cflags(CPUState *cpu); =20 /* TranslationBlock invalidate API */ #if defined(CONFIG_USER_ONLY) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index e22bcb99f7..ef4214d893 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -145,6 +145,11 @@ static void init_delay_params(SyncClocks *sc, const CP= UState *cpu) } #endif /* CONFIG USER ONLY */ =20 +uint32_t curr_cflags(CPUState *cpu) +{ + return cpu->tcg_cflags; +} + /* Might cause an exception, so have a longjmp destination ready */ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc, target_ulong cs_base, --=20 2.25.1 From nobody Sat May 18 04:13:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626744221445957.3453956881787; Mon, 19 Jul 2021 18:23:41 -0700 (PDT) Received: from localhost ([::1]:46432 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5eU0-0002zr-AF for importer@patchew.org; Mon, 19 Jul 2021 21:23:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60980) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5eOg-0006TE-OW for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:10 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:33345) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5eOf-0003MY-Am for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:10 -0400 Received: by mail-pl1-x631.google.com with SMTP id d1so10676222plg.0 for ; Mon, 19 Jul 2021 18:18:08 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id e4sm25378054pgi.94.2021.07.19.18.18.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 18:18:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yz3cpE1v3usKVqxRjbCaLbAnRr3RaTGtZYXFSmK7X+Q=; b=AjOiiVboOU3r3ddghrq9H/7I5Zz2qy4CBJq9fdFUf1S9dE//G6B9E0Hxxm0mp00J5W OaF7DNPLvp+RAnGGbSitErrteZgsDyaBPzcvdvduWPZ2Ay5yGyRcB46WkYIzjsB+BoSV oIWvzXSrlUHm7FWmVpJrfPReL6PLYfdFpu7yGu0OyjvwnpNKcWMHh+WIwxaKGvX1w++T 4cpuMQOY0ubJwD0kqdTK/flX4/zExhubKV4T+WySDH68wWO6THSYZm1Vq0wUI+cdZPRD +7ovze7dPGEtdjGrcSXmUd+865i/9j4SEwd8YYqtLvsb2Q1QGBmlKyz2dkTmI+4aACrS fIXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yz3cpE1v3usKVqxRjbCaLbAnRr3RaTGtZYXFSmK7X+Q=; b=DHSrPMKDVHi6Eb9eaypjMfleiK9aM2TV7xZg9IxZMVkmzSoNwGp+zc292Svof3hIfR WpUXFCd1JbjhzDy2eUC704ow6D9Z885QJSs+95aRnChmEgwALRTtZTjeU4SNOerq1Rtv DC+A7L2izzHucd0ehBDl7eS0uz08WWRPsiubN4fRfSG0JQSfnWR9WNsvZUbU69lOfHTA t8n3ASGxEv3Ov5ErRGj2g1eWcGcGdozn93+C9CgZokDXyJEW8DTPKZ1xQ2cU+oEXIiJ/ mmYKwSb+F0s/9mu+LYy5yfC2ZA0I6/KZ2TfRZAjoYW95jwmhWaclD15pG0yZdfH8UzxZ LTjg== X-Gm-Message-State: AOAM5321/P+bnnZ8mI0QRvdvksayBP56VnADRvW8gEhrYAMcklgwbpWc kC30Ywo8gKc8nskQ5WppBo0p6jtW1cuHaw== X-Google-Smtp-Source: ABdhPJwydmyJW9paoDray5/pPhlpoWPBXNJ+JH399RCY19drPMGLo9jVw9dJO55/abnVrMpynBFwZQ== X-Received: by 2002:a17:90a:f198:: with SMTP id bv24mr27235803pjb.171.1626743888096; Mon, 19 Jul 2021 18:18:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v5 03/15] target/alpha: Drop goto_tb path in gen_call_pal Date: Mon, 19 Jul 2021 15:17:48 -1000 Message-Id: <20210720011800.483966-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720011800.483966-1-richard.henderson@linaro.org> References: <20210720011800.483966-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626744223024100001 Content-Type: text/plain; charset="utf-8" We are certain of a page crossing here, entering the PALcode image, so the call to use_goto_tb that should have been here will never succeed. We are shortly going to add an assert to tcg_gen_goto_tb that would trigger for this case. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/alpha/translate.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 103c6326a2..949ba6ffde 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -1207,19 +1207,8 @@ static DisasJumpType gen_call_pal(DisasContext *ctx,= int palcode) ? 0x2000 + (palcode - 0x80) * 64 : 0x1000 + palcode * 64); =20 - /* Since the destination is running in PALmode, we don't really - need the page permissions check. We'll see the existence of - the page when we create the TB, and we'll flush all TBs if - we change the PAL base register. */ - if (!ctx->base.singlestep_enabled) { - tcg_gen_goto_tb(0); - tcg_gen_movi_i64(cpu_pc, entry); - tcg_gen_exit_tb(ctx->base.tb, 0); - return DISAS_NORETURN; - } else { - tcg_gen_movi_i64(cpu_pc, entry); - return DISAS_PC_UPDATED; - } + tcg_gen_movi_i64(cpu_pc, entry); + return DISAS_PC_UPDATED; } #endif } --=20 2.25.1 From nobody Sat May 18 04:13:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626743991690266.10335028692816; Mon, 19 Jul 2021 18:19:51 -0700 (PDT) Received: from localhost ([::1]:58874 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5eQI-0000w0-MP for importer@patchew.org; Mon, 19 Jul 2021 21:19:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60998) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5eOi-0006Y5-Ib for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:12 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:53801) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5eOg-0003NP-Q8 for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:12 -0400 Received: by mail-pj1-x102a.google.com with SMTP id p9so12760714pjl.3 for ; Mon, 19 Jul 2021 18:18:10 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id e4sm25378054pgi.94.2021.07.19.18.18.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 18:18:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gKHnw/iTk1V/eUPCZhivd0JB3zDH6dBk+qd11N8EyNM=; b=VTa0pCZH6lOuQ7IKI6QTML2s2V0TiYnK7i0tRqtZ7CqR0d/oPIYwpqgdRbOkTtRU0I Eh1IXnh76FLfUD3IM4fkKjjmipNoPs9D28dcQ2VaW8fFQMRq/SK1RKSP4WmZ9OwDt70z X7P1OBmbxIbox7xPMu37bvVdqI51vfR3exqXTdTWK9QE1T6HvVAA1+OX+ikOIY0kqqH6 GM5CpbvqCakZa7Em9AzrRC67xKI1X2SxerevJIOf5V6DmxhYRtGbxAiqrtlLjiIhgkVi MbCGScibBdNvWy9oPqSk+eEHr/SaX2MHbqb4HCpELyUl5XwkRJusPm2vtxpco/AC39Ex qalw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gKHnw/iTk1V/eUPCZhivd0JB3zDH6dBk+qd11N8EyNM=; b=ZvEMpK7eyXcAPnfMMq+N4oS5Ystwz9Q/9nnSRbgwwmG6ClosKjVX36iiPL98sWxAlP jEq/yGDYIB7uCoCm3AXYPN4hBF7timHkDPXK8Gl139AvPnsLF49O87jHJtfouv83TVdM 2abkGLZk6/QfL/lVpqB8EfJp47U8g/mwTgyAm+cSFT+raHrK7O51ZyAlbox/CBcsC3Az hMuaalkFKNJkkjkPHH1weuRR46jkgkss6K0ED5zG8vgyClPPkblD3vat0hKq+ojZdhDV Py+sd66i9JUpJsFMNxUibcAc0OH/gSKAp2SrYDZp7z07y1B44LYrTlK8Ky6SIbYn5ez4 erIw== X-Gm-Message-State: AOAM530fu0h4raLJ4VAKC+EK4W91v2aKd6R/+BEVFWufMQsfprHLN7Ct XlNVwai9DQt0KSD1Y0D6JaMu16nsE2h2Pg== X-Google-Smtp-Source: ABdhPJxQfXdUOyu78iHKfAV1asb6aAVxOJ7j8MouuJkRW+lVUmRTTNAsT1zm7IyRZAMyOyEiUlRh+g== X-Received: by 2002:a17:90a:db52:: with SMTP id u18mr33527378pjx.56.1626743889513; Mon, 19 Jul 2021 18:18:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v5 04/15] accel/tcg: Add CF_NO_GOTO_TB and CF_NO_GOTO_PTR Date: Mon, 19 Jul 2021 15:17:49 -1000 Message-Id: <20210720011800.483966-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720011800.483966-1-richard.henderson@linaro.org> References: <20210720011800.483966-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626744895248100001 Move the -d nochain check to bits on tb->cflags. These will be used for more than -d nochain shortly. Set bits during curr_cflags, test them in translator_use_goto_tb, assert we're not doing anything odd in tcg_gen_goto_tb. The test in tcg_gen_exit_tb is redundant with the assert for goto_tb_issue_mask. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Message-Id: <20210717221851.2124573-4-richard.henderson@linaro.org> --- include/exec/exec-all.h | 16 +++++++++------- accel/tcg/cpu-exec.c | 8 +++++++- accel/tcg/translator.c | 5 +++++ tcg/tcg-op.c | 28 ++++++++++++---------------- 4 files changed, 33 insertions(+), 24 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index ae7603ca75..6873cce8df 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -494,13 +494,15 @@ struct TranslationBlock { uint32_t cflags; /* compile flags */ =20 /* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */ -#define CF_COUNT_MASK 0x000001ff -#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ -#define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ -#define CF_USE_ICOUNT 0x00020000 -#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held = */ -#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context = */ -#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ +#define CF_COUNT_MASK 0x000001ff +#define CF_NO_GOTO_TB 0x00000200 /* Do not chain with goto_tb */ +#define CF_NO_GOTO_PTR 0x00000400 /* Do not chain with goto_ptr */ +#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ +#define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ +#define CF_USE_ICOUNT 0x00020000 +#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock hel= d */ +#define CF_PARALLEL 0x00080000 /* Generate code for a parallel contex= t */ +#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ #define CF_CLUSTER_SHIFT 24 =20 /* Per-vCPU dynamic tracing state used to generate this TB */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index ef4214d893..d3232d5764 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -147,7 +147,13 @@ static void init_delay_params(SyncClocks *sc, const CP= UState *cpu) =20 uint32_t curr_cflags(CPUState *cpu) { - return cpu->tcg_cflags; + uint32_t cflags =3D cpu->tcg_cflags; + + if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { + cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR; + } + + return cflags; } =20 /* Might cause an exception, so have a longjmp destination ready */ diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 59804af37b..2ea5a74f30 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -33,6 +33,11 @@ void translator_loop_temp_check(DisasContextBase *db) =20 bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest) { + /* Suppress goto_tb if requested. */ + if (tb_cflags(db->tb) & CF_NO_GOTO_TB) { + return false; + } + /* Suppress goto_tb in the case of single-steping. */ if (db->singlestep_enabled || singlestep) { return false; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 0c561fb253..e0d54d537f 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2723,10 +2723,6 @@ void tcg_gen_exit_tb(const TranslationBlock *tb, uns= igned idx) seen this numbered exit before, via tcg_gen_goto_tb. */ tcg_debug_assert(tcg_ctx->goto_tb_issue_mask & (1 << idx)); #endif - /* When not chaining, exit without indicating a link. */ - if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - val =3D 0; - } } else { /* This is an exit via the exitreq label. */ tcg_debug_assert(idx =3D=3D TB_EXIT_REQUESTED); @@ -2738,6 +2734,8 @@ void tcg_gen_exit_tb(const TranslationBlock *tb, unsi= gned idx) =20 void tcg_gen_goto_tb(unsigned idx) { + /* We tested CF_NO_GOTO_TB in translator_use_goto_tb. */ + tcg_debug_assert(!(tcg_ctx->tb_cflags & CF_NO_GOTO_TB)); /* We only support two chained exits. */ tcg_debug_assert(idx <=3D TB_EXIT_IDXMAX); #ifdef CONFIG_DEBUG_TCG @@ -2746,25 +2744,23 @@ void tcg_gen_goto_tb(unsigned idx) tcg_ctx->goto_tb_issue_mask |=3D 1 << idx; #endif plugin_gen_disable_mem_helpers(); - /* When not chaining, we simply fall through to the "fallback" exit. = */ - if (!qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - tcg_gen_op1i(INDEX_op_goto_tb, idx); - } + tcg_gen_op1i(INDEX_op_goto_tb, idx); } =20 void tcg_gen_lookup_and_goto_ptr(void) { - if (!qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - TCGv_ptr ptr; + TCGv_ptr ptr; =20 - plugin_gen_disable_mem_helpers(); - ptr =3D tcg_temp_new_ptr(); - gen_helper_lookup_tb_ptr(ptr, cpu_env); - tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr)); - tcg_temp_free_ptr(ptr); - } else { + if (tcg_ctx->tb_cflags & CF_NO_GOTO_PTR) { tcg_gen_exit_tb(NULL, 0); + return; } + + plugin_gen_disable_mem_helpers(); + ptr =3D tcg_temp_new_ptr(); + gen_helper_lookup_tb_ptr(ptr, cpu_env); + tcg_gen_op1i(INDEX_op_goto_ptr, tcgv_ptr_arg(ptr)); + tcg_temp_free_ptr(ptr); } =20 static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st) --=20 2.25.1 From nobody Sat May 18 04:13:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626743991795350.42390158109504; Mon, 19 Jul 2021 18:19:51 -0700 (PDT) Received: from localhost ([::1]:58822 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5eQI-0000tp-Mk for importer@patchew.org; Mon, 19 Jul 2021 21:19:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32776) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5eOj-0006aQ-GB for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:14 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:46776) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5eOi-0003OS-5L for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:13 -0400 Received: by mail-pg1-x52b.google.com with SMTP id r21so2852835pgv.13 for ; Mon, 19 Jul 2021 18:18:11 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id e4sm25378054pgi.94.2021.07.19.18.18.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 18:18:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9B/gmUM+QUz3bpCH+D2gMCTlPL+YqDM4DQGjYBG4u2w=; b=NhdB/zzX6mDFjrjH1iM0YPwvjxswVTIJuu+MDmfEoddHffyqa/2j2UsfRHskFzHgHf 96OBigqIgY/G673cG+GVh0U/1Tp2RWrbDilOd/vGHPCSOG8VSMfhUK9Anj56scdF7KHM /wxTobJLD0p7rTBNgGMlTq2ufzYiBdu/JlCLFjKOdVc2Lg+aM9ReG4NJNM0RpkaikDMq JN8uDzTd6EB/vfNNHjL/50Oh7YPwVeOMzAZ+bjUoQQcAStCd6o37xbz8H0RPK6Gkcqoz GRqwC31qltNlx5IrT/32w/jnPOFCd0jX7AFL9seGrHWsH+fEqL3ZMeJZhq+CFqARxmqn 6Rgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9B/gmUM+QUz3bpCH+D2gMCTlPL+YqDM4DQGjYBG4u2w=; b=lNTnuRmS2NbDa4Kbhc5DxYD9dZv/GrQjGJq91gAWDUwURm1RIleC0iYzcR/eMk5pu7 luE15WOuHucIMmhzYm6aOG3tJ0Uc5FzQ8j5y9jRr72kFE0Gss8ePVxSdYZnZ4yRzZ5Dh 9EWiTHJV3dpADCbGHbQrz9raFArl/J0+6rFXCVbYpqpEZ3t/aIahbRFZ8GlBVw/USwkm Dcf9EGXtInbO/JzNYYnlucDwkcxYFqW2RhZoeO0G7xxY3HGCvvQ3iMuH2upDzvgc8MO3 O2f1QTFQe8GNx5xSvqlxHkveZl2wfzGfJyiLfI5q8AEDMc3jaIg9Q0HQoV7MYvl1eSwo PT6g== X-Gm-Message-State: AOAM531QEy80qbjDPlq87+nLdwb/V+toeH5loa63EOnXhMU8MGFVu9Nx If72GRnQB4OZjuKjxbm9/34+MhxZbiLttg== X-Google-Smtp-Source: ABdhPJzslWkt+0D1wN7wzUp679Xv+Z3RwOKtcPWNkSYpuVoRkmAFr5O3z2+v/Hm8zKpPnl4GshmKbg== X-Received: by 2002:a62:bd15:0:b029:31c:a584:5f97 with SMTP id a21-20020a62bd150000b029031ca5845f97mr28289884pff.33.1626743890850; Mon, 19 Jul 2021 18:18:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v5 05/15] accel/tcg: Drop CF_NO_GOTO_PTR from -d nochain Date: Mon, 19 Jul 2021 15:17:50 -1000 Message-Id: <20210720011800.483966-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720011800.483966-1-richard.henderson@linaro.org> References: <20210720011800.483966-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626743993620100001 Content-Type: text/plain; charset="utf-8" The purpose of suppressing goto_ptr from -d nochain had been to return to the main loop so that -d cpu would be recognized. But we now include -d cpu logging in helper_lookup_tb_ptr so there is no need to exclude goto_ptr. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20210717221851.2124573-5-richard.henderson@linaro.org> --- accel/tcg/cpu-exec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index d3232d5764..70ea3c7d68 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -150,7 +150,7 @@ uint32_t curr_cflags(CPUState *cpu) uint32_t cflags =3D cpu->tcg_cflags; =20 if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { - cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR; + cflags |=3D CF_NO_GOTO_TB; } =20 return cflags; --=20 2.25.1 From nobody Sat May 18 04:13:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626744120070253.87071139160184; Mon, 19 Jul 2021 18:22:00 -0700 (PDT) Received: from localhost ([::1]:39102 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5eSN-0006ct-31 for importer@patchew.org; Mon, 19 Jul 2021 21:21:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32802) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5eOm-0006cw-1a for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:16 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:41492) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5eOj-0003PS-Hy for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:15 -0400 Received: by mail-pg1-x534.google.com with SMTP id s18so21032745pgg.8 for ; Mon, 19 Jul 2021 18:18:13 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id e4sm25378054pgi.94.2021.07.19.18.18.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 18:18:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jXNdPSSG3EvHjS1ff9yaYX7BJ5tWCVTACEwi3klwS+c=; b=Hid4Fp4nMuKIlmpGzx86gzKiXOtYTKA6YSR5z87gZOA2WyYQTMwP0DYy4rYl8P4v36 51oaPMwBT3GA0a4mAcpHS8Jfzd2dUO35UOBF0w8/POmIcQTzLcxNUcdpTy51J5Zzpnli f+4J+gmwZm/mKLwb9AQ/07e/swy+uYx4xbMebCHxOkfU05BKZZy+BHvpSuQlE0e4GCML BEBbJI9R7ggrGY8UjykxNRmI5nqD8uW2ftkXREE56gAbMEabRjeiN8N3ej11Tx/MTzwb PyvqHx54ZxB5RU82eNrjxjFFJtbHAmDgf/Zkao7xdOhHpinElfycOZVBb0Tn3+ELZv2q KYjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jXNdPSSG3EvHjS1ff9yaYX7BJ5tWCVTACEwi3klwS+c=; b=LHaC0HQonIXg1j5Idq69iHEceS/i0nAkgnCQZ0RE4JVEbGIcO7krFda5Lz+yj5/2BQ 0Vv3i9EQjmucWV88K7DlcPrZe0qkOaH0OAIr7pmW57PmL+HUK7YtpCJVTlEp0xDSNo1F GQ8sXpRjNEAc/OIi5RWd5AuQL3onMJjdErYdLK1oD7/NZYIPz54HbgDslxxIRTUGgUGK cLmuPji8Dd7AMouNttx4XhTs8qLZ9kNswKEDgxwy/5k+WI+SS4/SEYX24xL02HtuVMYw McmvleXD6wMGzhjXBp0QRDYz4VuYTHrP6E9Jj3kwcIWGR4JsiIZZWM5WhebcRSB3Uvrg kvvg== X-Gm-Message-State: AOAM532JL113i0Q3uH3faQf+XgDRRHGZkkZusqGcbk40+14P1cjbJq/i sKtklNv2CG7FWG0hpCNGPo50bYxW0Ls5ug== X-Google-Smtp-Source: ABdhPJz/npaJQ1JHlzuV3A+WvLeFyHrck9bzfEY4+YvXXLbomaU1GL/EJ81t2HOX3h3KjbveHdtz/A== X-Received: by 2002:a65:41c6:: with SMTP id b6mr28243478pgq.206.1626743892270; Mon, 19 Jul 2021 18:18:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v5 06/15] accel/tcg: Handle -singlestep in curr_cflags Date: Mon, 19 Jul 2021 15:17:51 -1000 Message-Id: <20210720011800.483966-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720011800.483966-1-richard.henderson@linaro.org> References: <20210720011800.483966-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626744120665100001 Content-Type: text/plain; charset="utf-8" Exchange the test in translator_use_goto_tb for CF_NO_GOTO_TB, and the test in tb_gen_code for setting CF_COUNT_MASK to 1. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20210717221851.2124573-6-richard.henderson@linaro.org> --- accel/tcg/cpu-exec.c | 8 +++++++- accel/tcg/translate-all.c | 2 +- accel/tcg/translator.c | 2 +- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 70ea3c7d68..2206c463f5 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -149,7 +149,13 @@ uint32_t curr_cflags(CPUState *cpu) { uint32_t cflags =3D cpu->tcg_cflags; =20 - if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { + /* + * For singlestep and -d nochain, suppress goto_tb so that + * we can log -d cpu,exec after every TB. + */ + if (singlestep) { + cflags |=3D CF_NO_GOTO_TB | 1; + } else if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { cflags |=3D CF_NO_GOTO_TB; } =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 5cc01d693b..bf82c15aab 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1432,7 +1432,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } QEMU_BUILD_BUG_ON(CF_COUNT_MASK + 1 !=3D TCG_MAX_INSNS); =20 - if (cpu->singlestep_enabled || singlestep) { + if (cpu->singlestep_enabled) { max_insns =3D 1; } =20 diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 2ea5a74f30..a59eb7c11b 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -39,7 +39,7 @@ bool translator_use_goto_tb(DisasContextBase *db, target_= ulong dest) } =20 /* Suppress goto_tb in the case of single-steping. */ - if (db->singlestep_enabled || singlestep) { + if (db->singlestep_enabled) { return false; } =20 --=20 2.25.1 From nobody Sat May 18 04:13:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626744230267703.4064243528958; Mon, 19 Jul 2021 18:23:50 -0700 (PDT) Received: from localhost ([::1]:46944 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5eU9-0003Kv-7W for importer@patchew.org; Mon, 19 Jul 2021 21:23:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32808) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5eOm-0006dI-Ga for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:16 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]:40603) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5eOk-0003Q0-Ss for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:16 -0400 Received: by mail-pf1-x42d.google.com with SMTP id j199so18226921pfd.7 for ; Mon, 19 Jul 2021 18:18:14 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id e4sm25378054pgi.94.2021.07.19.18.18.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 18:18:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UqlmS05MkTOxmP5dwcL3fhQ/lw1WJjbK9e+xb00mPGM=; b=WUYLnFs7YwhGC8JpEA0t8lM+sAD0t3fWym8kdexgJm4KwhD1+kVMq+YkQEK9znQz2l /qhAoOOkiKdi7HJI/AYReryvkCbxL0yTAD6UdTwADzd8xmPq3v1Z9ocvlDJMBGHL1DDb dPU1mzwR7dsgg+36nPgavzUgTpRXQ42OODs3O7uzqznwnu3WoXzy0QA6Y7gDlUvMth91 KBUivPlxdctzA5XfBv7VJkL37IhM6Sv962cMdbWp5C1ksoZIc6gS31dJNxPbsVf8IBYH ynmuDJ5BQWUPAjHN17iYjfqfoUijtCaCOk9nv5LX69fnhwbUqZpsRT/Vx8NyLYqFFgQI oIxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UqlmS05MkTOxmP5dwcL3fhQ/lw1WJjbK9e+xb00mPGM=; b=lATFuGVws/crEZs3iauwNk4+7J5P5Y9JmmC0ZrR4g3L313yd6OCeG1rFhMAO2F3BjX 3TaccVHkD5SMT2hySiq4GbTfINwrHbPxQahlZrKU7UFNcIUrGf2zE6Q4jtD7WYaiZoX0 o3ZdSfItEv6mek3BuOLKI79E6r6gzzHH2X7w17LTZqmgraalqVqV5RWQ21YiG5VPAEO+ 76iH54m5zoci+CrnNj0oh7apKQ1FoxPZGiJZPRM+YwxFL4OFOyXLqMW/JmH974iu51Zb bmS+HsoZD7eQ1SrPAAxGwQfm/3mg6wGbf7nX2kmzUiywrsiir5V83SVzulgzuSK624ii EzQA== X-Gm-Message-State: AOAM533Kh/dXAcre7sY/lm0etjHRhYSW7o4SkGA5QM+BcDknOSMd1B65 5Jop7tcVPRGSU/U1380Tec6kqDFWz1CRDA== X-Google-Smtp-Source: ABdhPJx129NORmENz5PmOVSLJAZY70oXGdCTFRo6outWrXprXhi1azKTtymwwC7isNeCvQzFnN6MnA== X-Received: by 2002:aa7:87cd:0:b029:32e:7954:2872 with SMTP id i13-20020aa787cd0000b029032e79542872mr29176705pfo.0.1626743893671; Mon, 19 Jul 2021 18:18:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v5 07/15] accel/tcg: Use CF_NO_GOTO_{TB, PTR} in cpu_exec_step_atomic Date: Mon, 19 Jul 2021 15:17:52 -1000 Message-Id: <20210720011800.483966-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720011800.483966-1-richard.henderson@linaro.org> References: <20210720011800.483966-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626744231362100001 Request that the one TB returns immediately, so that we release the exclusive lock as soon as possible. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Reviewed-by: Alex Benn=C3=A9e Message-Id: <20210717221851.2124573-7-richard.henderson@linaro.org> --- accel/tcg/cpu-exec.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 2206c463f5..5bb099174f 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -330,8 +330,7 @@ void cpu_exec_step_atomic(CPUState *cpu) CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; TranslationBlock *tb; target_ulong cs_base, pc; - uint32_t flags; - uint32_t cflags =3D (curr_cflags(cpu) & ~CF_PARALLEL) | 1; + uint32_t flags, cflags; int tb_exit; =20 if (sigsetjmp(cpu->jmp_env, 0) =3D=3D 0) { @@ -341,8 +340,14 @@ void cpu_exec_step_atomic(CPUState *cpu) cpu->running =3D true; =20 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); =20 + cflags =3D curr_cflags(cpu); + /* Execute in a serial context. */ + cflags &=3D ~CF_PARALLEL; + /* After 1 insn, return and release the exclusive lock. */ + cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1; + + tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb =3D=3D NULL) { mmap_lock(); tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); --=20 2.25.1 From nobody Sat May 18 04:13:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626744115344889.8498022123733; Mon, 19 Jul 2021 18:21:55 -0700 (PDT) Received: from localhost ([::1]:38514 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5eSI-0006Fk-Aq for importer@patchew.org; Mon, 19 Jul 2021 21:21:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32818) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5eOn-0006eN-My for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:18 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]:45718) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5eOm-0003RT-AQ for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:17 -0400 Received: by mail-pf1-x435.google.com with SMTP id q10so18213761pfj.12 for ; Mon, 19 Jul 2021 18:18:15 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id e4sm25378054pgi.94.2021.07.19.18.18.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 18:18:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+p6ro6D5KFq3icWk04aTft7NAAiKyhL4s7d6P84Hy6s=; b=IBBYKQktOIqbOtC6pKwZ93dSuTM4bFrE5U1rJ7h23gCF50tWbPLmm1GN13v5K22aCQ +/IbJ26BzcEol3LdPFx4yP2Tp46l3z5Fosus/5FABgiRRaXFCVvQHpAGKXvcj37VoOKz dc2Ard4UYgbWylhqXaIyZmhl7QjKoj52Xmb8JogiTHjVAP/S2DEyDjdGgn5LEdw1ufRP bn9eOq92UzzUSM4D41cVPgxq7DWIZedeRlgDdAD+h4rM24wUwi7RDVAPIlI6F4ks7Lav mr2+PW+YkBOdjv6F49L7fGfLOEHuf/WM/vZ+OGAHAL1doh+xo55/LOvjnTOcgrB60293 Ut9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+p6ro6D5KFq3icWk04aTft7NAAiKyhL4s7d6P84Hy6s=; b=BWMn4gBqqnSmJpYAburjgp8p7tr8IorrpTV90nLe7iGNOTmixd9fuLeo1Q3xsjogyR fn0WXmgu0VvL56nXQUngBnmHvEi4hhD3lgbiHn89OoRctnfOnbsVcsM9TOYuqHWqQsXG vXZtK6tv5zTBsceev2M1pWc5Sf80TLLLBbJkEYFdGKu75cO7jCltKRpjvsilZds5Ee46 ATzi/6zEfKIiSQUiAg5V/AT9AZvkxWM8nVNL9o65zjZplnqjOF/kAxdqPZABQwqCf4y5 xHHQpmOX3IJfOpFgzKUABDPMsHqTRVY/4/oAl1fFEHoptd/ImJIGiC6Cv0LMKvF9ujln p8bw== X-Gm-Message-State: AOAM533Gz2TJPAahGHD8J9mSUgQDXJgmYNptTau5advhQPXFWVklgWiv TYZu5i0kQ100NCfkV7riZ8H4AhpW/6h/Ew== X-Google-Smtp-Source: ABdhPJwGjdlLLsP04qyvimXwfzkLWrzsg25LmBlthpxK5EP/dWWUbbbDyomgaYZ6Fl44kIPAihUCoQ== X-Received: by 2002:aa7:81d8:0:b029:308:1d33:a5fa with SMTP id c24-20020aa781d80000b02903081d33a5famr28108509pfn.55.1626743895043; Mon, 19 Jul 2021 18:18:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v5 08/15] hw/core: Introduce TCGCPUOps.debug_check_breakpoint Date: Mon, 19 Jul 2021 15:17:53 -1000 Message-Id: <20210720011800.483966-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720011800.483966-1-richard.henderson@linaro.org> References: <20210720011800.483966-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626744116287100004 Content-Type: text/plain; charset="utf-8" New hook to return true when an architectural breakpoint is to be recognized and false when it should be suppressed. First use must wait until other pieces are in place. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/tcg-cpu-ops.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 72d791438c..eab27d0c03 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -88,6 +88,12 @@ struct TCGCPUOps { */ bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); =20 + /** + * @debug_check_breakpoint: return true if the architectural + * breakpoint whose PC has matched should really fire. + */ + bool (*debug_check_breakpoint)(CPUState *cpu); + /** * @io_recompile_replay_branch: Callback for cpu_io_recompile. * --=20 2.25.1 From nobody Sat May 18 04:13:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162674412027240.10066001312748; Mon, 19 Jul 2021 18:22:00 -0700 (PDT) Received: from localhost ([::1]:39118 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5eSN-0006dO-4e for importer@patchew.org; Mon, 19 Jul 2021 21:21:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32840) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5eOp-0006gL-WE for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:20 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:40607) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5eOo-0003SN-Dz for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:19 -0400 Received: by mail-pf1-x431.google.com with SMTP id j199so18226987pfd.7 for ; Mon, 19 Jul 2021 18:18:17 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id e4sm25378054pgi.94.2021.07.19.18.18.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 18:18:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Og5qRofVVysqqx/NRwWHk/rtIdv4ghjwZRwj/LrGEQk=; b=XmTzgQSzJGGRw6+WmGCjh6tsUBfAb1o+qTMRtLN8EyThxhBohfMgCBvQSIyfhUi9jb fpZSh/Rhzs6l/OoxBT5aJ64lB4sf0PrWSm8JYDQ7dIgCVW1D0cVDV+UZbZulEKyCwNCi YhrGoDWYWoypsdp9kGGD1qsOxf3dUmrR2BVf1afqjjIRJq8HKnDzp/dPIFhfhl6VnSwh vsGDu4kAzW9197aMIEq10+22+Eov78wAxQ9OowHY/CuvBGPrbOdmgrtFwpioX047Mf0X 6CJa7HOur0Wrs41oaHSfG9KlqX+uWuyLb4kDtjXToWXmOjaosXA5PKOGoc9IEPDfmpDJ d4mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Og5qRofVVysqqx/NRwWHk/rtIdv4ghjwZRwj/LrGEQk=; b=l3KnQ1JyOFI5u7qbJCb8jrvpl9X7P43tO7mzpsUdIuW63E7StrPEpv36rBpc+JJZvM qAhAimMPmJkv0n58j3j33uL95hSkEydVuhRyMN3FP14QUJEBEbXu7Pt8RhGmV3CzPSp/ geE38FgdMw8099rZ74x9IYPIl528sUa8GnWH+OVpX9WRM9oyHQkuG0zNPtMon4+AP8uX 3FfmA+fGdW8+U7SSownvXp8DKaAUB8nFmQaXiOhKa1I2Xj4PC+glCyLC1x0VpsoiUaEd i0/3OIJais0DBf6cAmOXkIgMlaBa0aV4SoMCCWjHvzfbZSRQDaWo7XN5GEYcQRK4Y1aT MvRg== X-Gm-Message-State: AOAM531eBswI7uc7o6ySKdXSBBNEinnFOLFpAoeauEjdALQSSi2HGD9p DcVAoTIbhz930JEJuDQ9FKwlkubp+tFLAw== X-Google-Smtp-Source: ABdhPJzrR0rLaplNh4pZhI0oBm13V4LQ6xHyWypEPGUdpxn1bI0OpqZDcOVzhFfQYxD09A5aKehI2w== X-Received: by 2002:a62:3852:0:b029:32e:50d4:6ee5 with SMTP id f79-20020a6238520000b029032e50d46ee5mr28419145pfa.3.1626743896438; Mon, 19 Jul 2021 18:18:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v5 09/15] target/arm: Implement debug_check_breakpoint Date: Mon, 19 Jul 2021 15:17:54 -1000 Message-Id: <20210720011800.483966-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720011800.483966-1-richard.henderson@linaro.org> References: <20210720011800.483966-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626744120734100003 Content-Type: text/plain; charset="utf-8" Reuse the code at the bottom of helper_check_breakpoints, which is what we currently call from *_tr_breakpoint_check. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/internals.h | 3 +++ target/arm/cpu.c | 1 + target/arm/cpu_tcg.c | 1 + target/arm/debug_helper.c | 7 +++---- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 3ba86e8af8..11a72013f5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -282,6 +282,9 @@ void hw_breakpoint_update(ARMCPU *cpu, int n); */ void hw_breakpoint_update_all(ARMCPU *cpu); =20 +/* Callback function for checking if a breakpoint should trigger. */ +bool arm_debug_check_breakpoint(CPUState *cs); + /* Callback function for checking if a watchpoint should trigger. */ bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9cddfd6a44..752b15bb79 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1984,6 +1984,7 @@ static const struct TCGCPUOps arm_tcg_ops =3D { .do_unaligned_access =3D arm_cpu_do_unaligned_access, .adjust_watchpoint_address =3D arm_adjust_watchpoint_address, .debug_check_watchpoint =3D arm_debug_check_watchpoint, + .debug_check_breakpoint =3D arm_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ }; #endif /* CONFIG_TCG */ diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index d2d97115ea..ed444bf436 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -911,6 +911,7 @@ static const struct TCGCPUOps arm_v7m_tcg_ops =3D { .do_unaligned_access =3D arm_cpu_do_unaligned_access, .adjust_watchpoint_address =3D arm_adjust_watchpoint_address, .debug_check_watchpoint =3D arm_debug_check_watchpoint, + .debug_check_breakpoint =3D arm_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ }; #endif /* CONFIG_TCG */ diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 2ff72d47d1..4a0c479527 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -216,8 +216,9 @@ static bool check_watchpoints(ARMCPU *cpu) return false; } =20 -static bool check_breakpoints(ARMCPU *cpu) +bool arm_debug_check_breakpoint(CPUState *cs) { + ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; int n; =20 @@ -240,9 +241,7 @@ static bool check_breakpoints(ARMCPU *cpu) =20 void HELPER(check_breakpoints)(CPUARMState *env) { - ARMCPU *cpu =3D env_archcpu(env); - - if (check_breakpoints(cpu)) { + if (arm_debug_check_breakpoint(env_cpu(env))) { HELPER(exception_internal(env, EXCP_DEBUG)); } } --=20 2.25.1 From nobody Sat May 18 04:13:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626744361829696.8442699825218; Mon, 19 Jul 2021 18:26:01 -0700 (PDT) Received: from localhost ([::1]:53188 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5eWG-0007cJ-Ok for importer@patchew.org; Mon, 19 Jul 2021 21:26:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32846) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5eOq-0006gx-Ml for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:22 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]:33437) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5eOp-0003Tf-Ah for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:20 -0400 Received: by mail-pf1-x42e.google.com with SMTP id m83so18271910pfd.0 for ; Mon, 19 Jul 2021 18:18:18 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id e4sm25378054pgi.94.2021.07.19.18.18.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 18:18:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1SYl6z4JM6oqxGI/nixKvmomGJ8etB/EcKsdFgvob4o=; b=Ds91u9k9HXaMQ2DDALQDns/BuOqFDcOqUkFHTY6ls7uOCsi06glnOqZVcfr+Ggu7hF slhyAntwAVHcTipKTc4LLVaZf2yZaqWZ4BRPpaKLqWgT6mIRKfPQiVouCmoJvu/wFPpI Rqkw2K5oPvJaTipSZcbrm6auscu+0eZIawabvED5QnCcYgR1hCR+jdThOKgi8wuGwBXd vnb3Lg5/uoOxNfoncqJMoRVxZWN9WjYpCNU1bCicfFSOTkKvbzV7pxJzZ0k0l0TBTGpX Vanq/M42I6b9jFFto8nvJZePpmvonWImRckPXvnI2klKY/5qIFlakFFbAJuh/7B9pB1x 5jfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1SYl6z4JM6oqxGI/nixKvmomGJ8etB/EcKsdFgvob4o=; b=C+DFIW4l/n3S0CvDCDH63fcWaGjGm2MXRm4zxdGMgAKE56JOZnmG+gIWMmoB2Jlc1D oppi5I5OeOveB4HzQtxn/u2QRDxyt6MZV5xrFqtt2VOHPJkkRyLxDwLBpU5cqsstrwKL ZCJ/h8ZiNafAgEn2NjTArldrFM0QOuCZxYlnx0xqNqqmA3Z2srvX9Ox2f1TA43oQRrIz QXyMJzXQUxlNjmbgXLcNqiy6yCdATAqjokMc5DGl8T3lwdH+jiwCu7tcpTSzbdMrUGh6 C5dOEsAjd1HcCq4wL8KhYjiVvF8vUfz5BA4atotcdHE6szbzxJ2QCYT2UV36y/X0ueqZ zHNw== X-Gm-Message-State: AOAM530cd8lqDk3pxgSbN4fSiex1QflW2rKgl2pmdcYsqZHJdo+FYNzC EGr6PFM3wsapQkRLr2ZdE2twzMpKlowOMQ== X-Google-Smtp-Source: ABdhPJx3Al/lJr2+zmcSrN8/YStaieVJTIxoDr90uQwvTcP6iGPQJu0+JW3iwVpFkJjDZxZ9JzjjjQ== X-Received: by 2002:a63:d709:: with SMTP id d9mr28350581pgg.337.1626743898080; Mon, 19 Jul 2021 18:18:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v5 10/15] target/i386: Implement debug_check_breakpoint Date: Mon, 19 Jul 2021 15:17:55 -1000 Message-Id: <20210720011800.483966-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720011800.483966-1-richard.henderson@linaro.org> References: <20210720011800.483966-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626744362482100001 Content-Type: text/plain; charset="utf-8" Return false for RF set, as we do in i386_tr_breakpoint_check. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/i386/tcg/tcg-cpu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index e96ec9bbcc..238e3a9395 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -54,6 +54,17 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, cpu->env.eip =3D tb->pc - tb->cs_base; } =20 +#ifndef CONFIG_USER_ONLY +static bool x86_debug_check_breakpoint(CPUState *cs) +{ + X86CPU *cpu =3D X86_CPU(cs); + CPUX86State *env =3D &cpu->env; + + /* RF disables all architectural breakpoints. */ + return !(env->eflags & RF_MASK); +} +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static const struct TCGCPUOps x86_tcg_ops =3D { @@ -66,6 +77,7 @@ static const struct TCGCPUOps x86_tcg_ops =3D { .tlb_fill =3D x86_cpu_tlb_fill, #ifndef CONFIG_USER_ONLY .debug_excp_handler =3D breakpoint_handler, + .debug_check_breakpoint =3D x86_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ }; =20 --=20 2.25.1 From nobody Sat May 18 04:13:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626744448556331.44244590559083; Mon, 19 Jul 2021 18:27:28 -0700 (PDT) Received: from localhost ([::1]:58586 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5eXf-0002jp-Jv for importer@patchew.org; Mon, 19 Jul 2021 21:27:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32864) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5eOs-0006hc-4d for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:22 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:38908) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5eOq-0003U3-JT for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:21 -0400 Received: by mail-pg1-x535.google.com with SMTP id j4so4364930pgk.5 for ; Mon, 19 Jul 2021 18:18:20 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id e4sm25378054pgi.94.2021.07.19.18.18.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 18:18:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PHrvozsxOuSVOdMrHpVZufZjeOyEcT2c7pJZ5VYPbLQ=; b=LqcLCGC/iSpJhqSymm6FsT2nMAYWGbh3DA3hh7GUU2r8bESyyT6easxU6T6tWZH4DY 0VY3EurKgJ4gQ8nDb0tAVCXiWrbFcrUNoPMGouvMGoxUFI8y107Skx+aA9HODHlO4fi1 zPXNJaQl5DC2j6hyc/Dkd8FfW77azMxWCwwtvj0E434sIL3L/Zw1plrEpJhEQ3E99ywp 4513cRD1GK1Uds0yWtutcGu/5Dn1X6G6Vlrve4h94Ov4FDHOf7dIupHYfKIU3W+e2Ya7 hHy39A8FofkZehKfO4wWE5JiDurGdyTEbeyT7p4OENAsdFTG/FNOXoDTQPFjA+KNpF8m 8qMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PHrvozsxOuSVOdMrHpVZufZjeOyEcT2c7pJZ5VYPbLQ=; b=fPdYWfhFYPepDcIM4OENDbWUOFB4BPnj0YBeSmBUjL7MZeBFS105HV/OB2zG2UaSoM AsVyCw4CdD5gJDEWi1GRrEoDZXvPirHwHffRfBEfxSJhlSJUzHhn1o0KfH6STE8wdRS4 6l5NvhPeFBbIz08SGim5moBVNZz/L9xmGa4jXwQfBGZzYC+c5RUx0zBRzWozyo+gbN0o WUk3Y4KmXi2dstGW7GJq5eSLs+IJe0JSpaeT+qOImqjOUSJSNiKCoSOZ8JEzbZNrTU0r 2hd6BhxsJ6C8xQuFERjt0Ma4aRKarVFUn/8Z+VwQiLDhsyKx5r+CAL7qq1sAw99Zwgx4 MNfA== X-Gm-Message-State: AOAM532W5cpjOwJetmLwcxf2KMt0CzLp4kekX45al7HAh4dbXWk3qmd7 j20p0FkbrhbPWthD6Q3hJ7b3PhbQvdLfPg== X-Google-Smtp-Source: ABdhPJwpCPuBDWiVEWXTSyDbdGOFgEs4mqk4lfCtvRe0vX95//mugNQN5Mle3CIYV+XOUO2EHCLrUA== X-Received: by 2002:a63:4761:: with SMTP id w33mr28069071pgk.195.1626743899332; Mon, 19 Jul 2021 18:18:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v5 11/15] accel/tcg: Merge tb_find into its only caller Date: Mon, 19 Jul 2021 15:17:56 -1000 Message-Id: <20210720011800.483966-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720011800.483966-1-richard.henderson@linaro.org> References: <20210720011800.483966-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626744450602100001 Content-Type: text/plain; charset="utf-8" We are going to want two things: (1) check for breakpoints will want to break out of the loop here, (2) cflags can only be calculated with pc in hand. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- accel/tcg/cpu-exec.c | 83 ++++++++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 42 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5bb099174f..cde7069eb7 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -500,41 +500,6 @@ static inline void tb_add_jump(TranslationBlock *tb, i= nt n, return; } =20 -static inline TranslationBlock *tb_find(CPUState *cpu, - TranslationBlock *last_tb, - int tb_exit, uint32_t cflags) -{ - CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; - TranslationBlock *tb; - target_ulong cs_base, pc; - uint32_t flags; - - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); - - tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); - if (tb =3D=3D NULL) { - mmap_lock(); - tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); - mmap_unlock(); - /* We add the TB in the virtual pc hash table for the fast lookup = */ - qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb); - } -#ifndef CONFIG_USER_ONLY - /* We don't take care of direct jumps when address mapping changes in - * system emulation. So it's not safe to make a direct jump to a TB - * spanning two pages because the mapping for the second page can chan= ge. - */ - if (tb->page_addr[1] !=3D -1) { - last_tb =3D NULL; - } -#endif - /* See if we can patch the calling TB. */ - if (last_tb) { - tb_add_jump(last_tb, tb_exit, tb); - } - return tb; -} - static inline bool cpu_handle_halt(CPUState *cpu) { if (cpu->halted) { @@ -868,22 +833,56 @@ int cpu_exec(CPUState *cpu) int tb_exit =3D 0; =20 while (!cpu_handle_interrupt(cpu, &last_tb)) { - uint32_t cflags =3D cpu->cflags_next_tb; TranslationBlock *tb; + target_ulong cs_base, pc; + uint32_t flags, cflags; =20 - /* When requested, use an exact setting for cflags for the next - execution. This is used for icount, precise smc, and stop- - after-access watchpoints. Since this request should never - have CF_INVALID set, -1 is a convenient invalid value that - does not require tcg headers for cpu_common_reset. */ + /* + * When requested, use an exact setting for cflags for the next + * execution. This is used for icount, precise smc, and stop- + * after-access watchpoints. Since this request should never + * have CF_INVALID set, -1 is a convenient invalid value that + * does not require tcg headers for cpu_common_reset. + */ + cflags =3D cpu->cflags_next_tb; if (cflags =3D=3D -1) { cflags =3D curr_cflags(cpu); } else { cpu->cflags_next_tb =3D -1; } =20 - tb =3D tb_find(cpu, last_tb, tb_exit, cflags); + cpu_get_tb_cpu_state(cpu->env_ptr, &pc, &cs_base, &flags); + + tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); + if (tb =3D=3D NULL) { + mmap_lock(); + tb =3D tb_gen_code(cpu, pc, cs_base, flags, cflags); + mmap_unlock(); + /* + * We add the TB in the virtual pc hash table + * for the fast lookup + */ + qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)]= , tb); + } + +#ifndef CONFIG_USER_ONLY + /* + * We don't take care of direct jumps when address mapping + * changes in system emulation. So it's not safe to make a + * direct jump to a TB spanning two pages because the mapping + * for the second page can change. + */ + if (tb->page_addr[1] !=3D -1) { + last_tb =3D NULL; + } +#endif + /* See if we can patch the calling TB. */ + if (last_tb) { + tb_add_jump(last_tb, tb_exit, tb); + } + cpu_loop_exec_tb(cpu, tb, &last_tb, &tb_exit); + /* Try to align the host and virtual clocks if the guest is in advance */ align_clocks(&sc, cpu); --=20 2.25.1 From nobody Sat May 18 04:13:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626744527486951.2792390145615; Mon, 19 Jul 2021 18:28:47 -0700 (PDT) Received: from localhost ([::1]:35456 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5eYw-00067H-EU for importer@patchew.org; Mon, 19 Jul 2021 21:28:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32878) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5eOu-0006l4-2B for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:24 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:43845) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5eOr-0003Vf-VB for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:23 -0400 Received: by mail-pj1-x102d.google.com with SMTP id x13-20020a17090a46cdb0290175cf22899cso1521166pjg.2 for ; Mon, 19 Jul 2021 18:18:21 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id e4sm25378054pgi.94.2021.07.19.18.18.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 18:18:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sktB4eiY9I4bWXSFU/pRtO5O5p+Es9NUgFHwnuAPhsQ=; b=VWW6NZ6a6qqAG15XDt/xw0Z6GgxTzwiUAVBVdXwC1PKZm1SFM3eo8QF/RgYTjhU3ez LCdMYKALLs+yfZPEsopxo7qGQY5IqIhs/bHnFTvZX8QsFIbtFNbl1e4U3mR+O71zNhYT prTbSt22xDN8T+gwES2m4oXOgdN5m1qkhUWyQzG1xocC+3vdvKHn6DyJGB5lt865x3U9 QhlK0//J1A6Ew3W+dMVY2F114whZEJiFm6Lchzk2w2Kzx1FKEPtcL9W4lzAa86Yu9fln RVypLQUNIrpYFMXIkUt0T90nMkJ7gbJzTuYdRwcDph277Pw2MC+xHITD4I0m7+oWzqGt gCKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sktB4eiY9I4bWXSFU/pRtO5O5p+Es9NUgFHwnuAPhsQ=; b=CM9Bp672KoAB6F3I/WNZqOoJTvIqhpAFCM3obL1rRuFvH9ujrjRAgYyFuoXbcw2mMb 3Qo3XgZFmYwFjlh7gh6PDOeWGYScb2sfgMZFlUcQd2My6QHUJ9aI6ddfkW5vFjl0ILeb uneJkBgjtPsTVncw2lO5i4oYz1xZplpkCjZYJDc62Z2A3VSWjDiUYe4rGB27ta5qrco8 tuDMDQd9+z1FWbi1KYxY9nGWK38PhTPHddFVUEIZ667nyaxbGsVp3srxlR52tFtm6yAg lXs9QCY4HJxSsuXjnGxxY0U7/xVsKPcNMcAiMubKxPFF7+VXIslCGxrkqZa5xo++Fbk4 3A6g== X-Gm-Message-State: AOAM5337wr4mtOadlKef7JrTdAzOz5VKjADchS+GEG84Hl2MUQAOZ0M3 q7zCRAt+p8uazDA9B8Nq+EM82rZv6zdD2g== X-Google-Smtp-Source: ABdhPJzZ3fjdXV+cIm464V5HZK/J0nA/E2q/4fjhzyTG9g/Q2uOSuZgm1dQeoKLV/QPWrIF8TsBRpw== X-Received: by 2002:a17:90a:474f:: with SMTP id y15mr27749108pjg.2.1626743900712; Mon, 19 Jul 2021 18:18:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v5 12/15] accel/tcg: Move breakpoint recognition outside translation Date: Mon, 19 Jul 2021 15:17:57 -1000 Message-Id: <20210720011800.483966-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720011800.483966-1-richard.henderson@linaro.org> References: <20210720011800.483966-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626744527933100001 Content-Type: text/plain; charset="utf-8" Trigger breakpoints before beginning translation of a TB that would begin with a BP. Thus we never generate code for the BP at all. Single-step instructions within a page containing a BP so that we are sure to check each insn for the BP as above. We no longer need to flush any TBs when changing BPs. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/286 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/404 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/489 Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- accel/tcg/cpu-exec.c | 78 ++++++++++++++++++++++++++++++++++++++++-- accel/tcg/translator.c | 24 +------------ cpu.c | 20 ----------- 3 files changed, 76 insertions(+), 46 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index cde7069eb7..f5371e03d4 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -222,6 +222,63 @@ static inline void log_cpu_exec(target_ulong pc, CPUSt= ate *cpu, } } =20 +static bool check_for_breakpoints(CPUState *cpu, target_ulong pc, + uint32_t *cflags) +{ + CPUBreakpoint *bp; + bool match_page =3D false; + + if (likely(QTAILQ_EMPTY(&cpu->breakpoints))) { + return false; + } + + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { + /* + * If we have an exact pc match, trigger the breakpoint. + * Otherwise, note matches within the page. + */ + if (pc =3D=3D bp->pc) { + bool match_bp =3D false; + + if (bp->flags & BP_GDB) { + match_bp =3D true; + } else if (bp->flags & BP_CPU) { +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + CPUClass *cc =3D CPU_GET_CLASS(cpu); + assert(cc->tcg_ops->debug_check_breakpoint); + match_bp =3D cc->tcg_ops->debug_check_breakpoint(cpu); +#endif + } + + if (match_bp) { + cpu->exception_index =3D EXCP_DEBUG; + return true; + } + } else if (((pc ^ bp->pc) & TARGET_PAGE_MASK) =3D=3D 0) { + match_page =3D true; + } + } + + /* + * Within the same page as a breakpoint, single-step, + * returning to helper_lookup_tb_ptr after each looking + * for the actual breakpoint. + * + * TODO: Perhaps better to record all of the TBs associated + * with a given virtual page that contains a breakpoint, and + * then invalidate them when a new overlapping breakpoint is + * set on the page. Non-overlapping TBs would not be + * invalidated, nor would any TB need to be invalidated as + * breakpoints are removed. + */ + if (match_page) { + *cflags =3D (*cflags & ~CF_COUNT_MASK) | CF_NO_GOTO_TB | 1; + } + return false; +} + /** * helper_lookup_tb_ptr: quick check for next tb * @env: current cpu state @@ -235,11 +292,16 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) CPUState *cpu =3D env_cpu(env); TranslationBlock *tb; target_ulong cs_base, pc; - uint32_t flags; + uint32_t flags, cflags; =20 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); =20 - tb =3D tb_lookup(cpu, pc, cs_base, flags, curr_cflags(cpu)); + cflags =3D curr_cflags(cpu); + if (check_for_breakpoints(cpu, pc, &cflags)) { + cpu_loop_exit(cpu); + } + + tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb =3D=3D NULL) { return tcg_code_gen_epilogue; } @@ -346,6 +408,12 @@ void cpu_exec_step_atomic(CPUState *cpu) cflags &=3D ~CF_PARALLEL; /* After 1 insn, return and release the exclusive lock. */ cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1; + /* + * No need to check_for_breakpoints here. + * We only arrive in cpu_exec_step_atomic after beginning execution + * of an insn that includes an atomic operation we can't handle. + * Any breakpoint for this insn will have been recognized earlier. + */ =20 tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb =3D=3D NULL) { @@ -837,6 +905,8 @@ int cpu_exec(CPUState *cpu) target_ulong cs_base, pc; uint32_t flags, cflags; =20 + cpu_get_tb_cpu_state(cpu->env_ptr, &pc, &cs_base, &flags); + /* * When requested, use an exact setting for cflags for the next * execution. This is used for icount, precise smc, and stop- @@ -851,7 +921,9 @@ int cpu_exec(CPUState *cpu) cpu->cflags_next_tb =3D -1; } =20 - cpu_get_tb_cpu_state(cpu->env_ptr, &pc, &cs_base, &flags); + if (check_for_breakpoints(cpu, pc, &cflags)) { + break; + } =20 tb =3D tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb =3D=3D NULL) { diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index a59eb7c11b..4f3728c278 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -50,7 +50,6 @@ bool translator_use_goto_tb(DisasContextBase *db, target_= ulong dest) void translator_loop(const TranslatorOps *ops, DisasContextBase *db, CPUState *cpu, TranslationBlock *tb, int max_insns) { - int bp_insn =3D 0; bool plugin_enabled; =20 /* Initialize DisasContext */ @@ -85,27 +84,6 @@ void translator_loop(const TranslatorOps *ops, DisasCont= extBase *db, plugin_gen_insn_start(cpu, db); } =20 - /* Pass breakpoint hits to target for further processing */ - if (!db->singlestep_enabled - && unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { - if (bp->pc =3D=3D db->pc_next) { - if (ops->breakpoint_check(db, cpu, bp)) { - bp_insn =3D 1; - break; - } - } - } - /* The breakpoint_check hook may use DISAS_TOO_MANY to indicate - that only one more instruction is to be executed. Otherwise - it should use DISAS_NORETURN when generating an exception, - but may use a DISAS_TARGET_* value for Something Else. */ - if (db->is_jmp > DISAS_TOO_MANY) { - break; - } - } - /* Disassemble one instruction. The translate_insn hook should update db->pc_next and db->is_jmp to indicate what should be done next -- either exiting this loop or locate the start of @@ -144,7 +122,7 @@ void translator_loop(const TranslatorOps *ops, DisasCon= textBase *db, =20 /* Emit code to exit the TB, as indicated by db->is_jmp. */ ops->tb_stop(db, cpu); - gen_tb_end(db->tb, db->num_insns - bp_insn); + gen_tb_end(db->tb, db->num_insns); =20 if (plugin_enabled) { plugin_gen_tb_end(cpu); diff --git a/cpu.c b/cpu.c index 83059537d7..660b56f431 100644 --- a/cpu.c +++ b/cpu.c @@ -225,11 +225,6 @@ void tb_invalidate_phys_addr(target_ulong addr) tb_invalidate_phys_page_range(addr, addr + 1); mmap_unlock(); } - -static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) -{ - tb_invalidate_phys_addr(pc); -} #else void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs att= rs) { @@ -250,17 +245,6 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr = addr, MemTxAttrs attrs) ram_addr =3D memory_region_get_ram_addr(mr) + addr; tb_invalidate_phys_page_range(ram_addr, ram_addr + 1); } - -static void breakpoint_invalidate(CPUState *cpu, target_ulong pc) -{ - /* - * There may not be a virtual to physical translation for the pc - * right now, but there may exist cached TB for this pc. - * Flush the whole TB cache to force re-translation of such TBs. - * This is heavyweight, but we're debugging anyway. - */ - tb_flush(cpu); -} #endif =20 /* Add a breakpoint. */ @@ -281,8 +265,6 @@ int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int = flags, QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry); } =20 - breakpoint_invalidate(cpu, pc); - if (breakpoint) { *breakpoint =3D bp; } @@ -310,8 +292,6 @@ void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBre= akpoint *bp) { QTAILQ_REMOVE(&cpu->breakpoints, bp, entry); =20 - breakpoint_invalidate(cpu, bp->pc); - trace_breakpoint_remove(cpu->cpu_index, bp->pc, bp->flags); g_free(bp); } --=20 2.25.1 From nobody Sat May 18 04:13:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626744295532309.8852608409867; Mon, 19 Jul 2021 18:24:55 -0700 (PDT) Received: from localhost ([::1]:49284 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5eVC-0004ti-1H for importer@patchew.org; Mon, 19 Jul 2021 21:24:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32928) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5eOx-0006tk-U4 for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:28 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:45024) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5eOt-0003WQ-La for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:27 -0400 Received: by mail-pf1-x431.google.com with SMTP id p36so18212856pfw.11 for ; Mon, 19 Jul 2021 18:18:23 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id e4sm25378054pgi.94.2021.07.19.18.18.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 18:18:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Gz86JWdD8mgz58o/NdTo+ANYhFvpOsAkurqAws9uKcg=; b=BXhmdRYp5MyU2pXir1GM7wR3GlKyVtOAe7HeLteY/o+I3CzSFSIVNhWglzsU3AOhgy 4wm3Vei63UEPzwdB/JqL8g8rTBU1b/ZwiMx3pcBDR4MIFC7a+VQqkVNvdSqEdypYdgx3 1iUUaJ/yUJfanHG0SAeFw4uZUjKKXcGD3ItYFLc8qusszatv5Wr2O6oMxjm+hqbpwom8 qBVzZXUav+bXwjBRLet6nJ1aIZngBTJDXHAviFklbqs7QYD76In18u4upYEWlKEHTfTO GadsZWpwjCeWQ+tBLDatqBh382Edtsgtl6XhegrDMn9Ybvy1caNkly2PgnZYMjSRNtOl eeHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Gz86JWdD8mgz58o/NdTo+ANYhFvpOsAkurqAws9uKcg=; b=FJQE9VQY4CTTKx5fjN9z9WvpWIUqSipB2YftCVooUjAXeiCmGmwUwmebs5u2D+cJoY 36lOdNl6bFmHe/+8Y/drgEvjDwEUHGkAaK3neoVp2A6f0h6ms4vb0hiHz6dqcHUtV1P1 zkhegKDhEA2IwEdik2fdPLlESqWkqc+YWPSmYylB2qn9a5OwtlJn3RZoJwFEBMe97NF4 ezrQeYiv84CwSWUjyo5R574GLqJlShsDtjnQoAY6N8Qlfhi7EMZuUlGw1kKUAvTtmUie unO/eX3AY+/ad6erC9TkjRy9DCPGJYTwGXTsNRXc6dBBhqK3AuMLpnaHE415xOzxn8BA YDKQ== X-Gm-Message-State: AOAM533kjhgwz3pyVLQuKhOeGS6BTw52iAGvUAbIojVGWT8lmpbVQU5P hKDTa1xLtrO7hllh8/4b9yewMMyBrPeeaA== X-Google-Smtp-Source: ABdhPJyaZMr5lhYlVMyxNDbL1UocLkzoMPFnkpm+dp5EaEF9mgRE1RoAlLmjVDUv+Uy7KI+UQFwm7A== X-Received: by 2002:a63:5b02:: with SMTP id p2mr28213314pgb.161.1626743902208; Mon, 19 Jul 2021 18:18:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v5 13/15] accel/tcg: Remove TranslatorOps.breakpoint_check Date: Mon, 19 Jul 2021 15:17:58 -1000 Message-Id: <20210720011800.483966-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720011800.483966-1-richard.henderson@linaro.org> References: <20210720011800.483966-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626744296883100001 Content-Type: text/plain; charset="utf-8" The hook is now unused, with breakpoints checked outside translation. Signed-off-by: Richard Henderson --- include/exec/translator.h | 11 ----------- target/arm/helper.h | 2 -- target/alpha/translate.c | 16 ---------------- target/arm/debug_helper.c | 7 ------- target/arm/translate-a64.c | 25 ------------------------- target/arm/translate.c | 29 ----------------------------- target/avr/translate.c | 10 ---------- target/cris/translate.c | 20 -------------------- target/hexagon/translate.c | 17 ----------------- target/hppa/translate.c | 11 ----------- target/i386/tcg/translate.c | 28 ---------------------------- target/m68k/translate.c | 18 ------------------ target/microblaze/translate.c | 18 ------------------ target/mips/tcg/translate.c | 19 ------------------- target/nios2/translate.c | 27 --------------------------- target/openrisc/translate.c | 17 ----------------- target/ppc/translate.c | 18 ------------------ target/riscv/translate.c | 17 ----------------- target/rx/translate.c | 14 -------------- target/s390x/tcg/translate.c | 24 ------------------------ target/sh4/translate.c | 18 ------------------ target/sparc/translate.c | 17 ----------------- target/tricore/translate.c | 16 ---------------- target/xtensa/translate.c | 17 ----------------- 24 files changed, 416 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index dd9c06d40d..d318803267 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -89,15 +89,6 @@ typedef struct DisasContextBase { * @insn_start: * Emit the tcg_gen_insn_start opcode. * - * @breakpoint_check: - * When called, the breakpoint has already been checked to match the = PC, - * but the target may decide the breakpoint missed the address - * (e.g., due to conditions encoded in their flags). Return true to - * indicate that the breakpoint did hit, in which case no more breakp= oints - * are checked. If the breakpoint did hit, emit any code required to - * signal the exception, and set db->is_jmp as necessary to terminate - * the main loop. - * * @translate_insn: * Disassemble one instruction and set db->pc_next for the start * of the following instruction. Set db->is_jmp as necessary to @@ -113,8 +104,6 @@ typedef struct TranslatorOps { void (*init_disas_context)(DisasContextBase *db, CPUState *cpu); void (*tb_start)(DisasContextBase *db, CPUState *cpu); void (*insn_start)(DisasContextBase *db, CPUState *cpu); - bool (*breakpoint_check)(DisasContextBase *db, CPUState *cpu, - const CPUBreakpoint *bp); void (*translate_insn)(DisasContextBase *db, CPUState *cpu); void (*tb_stop)(DisasContextBase *db, CPUState *cpu); void (*disas_log)(const DisasContextBase *db, CPUState *cpu); diff --git a/target/arm/helper.h b/target/arm/helper.h index db87d7d537..248569b0cd 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -54,8 +54,6 @@ DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) DEF_HELPER_2(pre_smc, void, env, i32) =20 -DEF_HELPER_1(check_breakpoints, void, env) - DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_2(cpsr_write_eret, void, env, i32) DEF_HELPER_1(cpsr_read, i32, env) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 949ba6ffde..de6c0a8439 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2967,21 +2967,6 @@ static void alpha_tr_insn_start(DisasContextBase *dc= base, CPUState *cpu) tcg_gen_insn_start(dcbase->pc_next); } =20 -static bool alpha_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *= cpu, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - ctx->base.is_jmp =3D gen_excp(ctx, EXCP_DEBUG, 0); - - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx->base.pc_next +=3D 4; - return true; -} - static void alpha_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); @@ -3040,7 +3025,6 @@ static const TranslatorOps alpha_tr_ops =3D { .init_disas_context =3D alpha_tr_init_disas_context, .tb_start =3D alpha_tr_tb_start, .insn_start =3D alpha_tr_insn_start, - .breakpoint_check =3D alpha_tr_breakpoint_check, .translate_insn =3D alpha_tr_translate_insn, .tb_stop =3D alpha_tr_tb_stop, .disas_log =3D alpha_tr_disas_log, diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 4a0c479527..2983e36dd3 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -239,13 +239,6 @@ bool arm_debug_check_breakpoint(CPUState *cs) return false; } =20 -void HELPER(check_breakpoints)(CPUARMState *env) -{ - if (arm_debug_check_breakpoint(env_cpu(env))) { - HELPER(exception_internal(env, EXCP_DEBUG)); - } -} - bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) { /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ca11a5fecd..422e2ac0c9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14844,30 +14844,6 @@ static void aarch64_tr_insn_start(DisasContextBase= *dcbase, CPUState *cpu) dc->insn_start =3D tcg_last_op(); } =20 -static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState= *cpu, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - if (bp->flags & BP_CPU) { - gen_a64_set_pc_im(dc->base.pc_next); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it likely won't be executed */ - dc->base.is_jmp =3D DISAS_TOO_MANY; - } else { - gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - dc->base.pc_next +=3D 4; - dc->base.is_jmp =3D DISAS_NORETURN; - } - - return true; -} - static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *= cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -14982,7 +14958,6 @@ const TranslatorOps aarch64_translator_ops =3D { .init_disas_context =3D aarch64_tr_init_disas_context, .tb_start =3D aarch64_tr_tb_start, .insn_start =3D aarch64_tr_insn_start, - .breakpoint_check =3D aarch64_tr_breakpoint_check, .translate_insn =3D aarch64_tr_translate_insn, .tb_stop =3D aarch64_tr_tb_stop, .disas_log =3D aarch64_tr_disas_log, diff --git a/target/arm/translate.c b/target/arm/translate.c index e1a8152598..351afa43a2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9438,33 +9438,6 @@ static void arm_tr_insn_start(DisasContextBase *dcba= se, CPUState *cpu) dc->insn_start =3D tcg_last_op(); } =20 -static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cp= u, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - if (bp->flags & BP_CPU) { - gen_set_condexec(dc); - gen_set_pc_im(dc, dc->base.pc_next); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it's likely not going to be executed */ - dc->base.is_jmp =3D DISAS_TOO_MANY; - } else { - gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - /* TODO: Advance PC by correct instruction length to - * avoid disassembler error messages */ - dc->base.pc_next +=3D 2; - dc->base.is_jmp =3D DISAS_NORETURN; - } - - return true; -} - static bool arm_pre_translate_insn(DisasContext *dc) { #ifdef CONFIG_USER_ONLY @@ -9827,7 +9800,6 @@ static const TranslatorOps arm_translator_ops =3D { .init_disas_context =3D arm_tr_init_disas_context, .tb_start =3D arm_tr_tb_start, .insn_start =3D arm_tr_insn_start, - .breakpoint_check =3D arm_tr_breakpoint_check, .translate_insn =3D arm_tr_translate_insn, .tb_stop =3D arm_tr_tb_stop, .disas_log =3D arm_tr_disas_log, @@ -9837,7 +9809,6 @@ static const TranslatorOps thumb_translator_ops =3D { .init_disas_context =3D arm_tr_init_disas_context, .tb_start =3D arm_tr_tb_start, .insn_start =3D arm_tr_insn_start, - .breakpoint_check =3D arm_tr_breakpoint_check, .translate_insn =3D thumb_tr_translate_insn, .tb_stop =3D arm_tr_tb_stop, .disas_log =3D arm_tr_disas_log, diff --git a/target/avr/translate.c b/target/avr/translate.c index 8237a03c23..3055e84483 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2944,15 +2944,6 @@ static void avr_tr_insn_start(DisasContextBase *dcba= se, CPUState *cs) tcg_gen_insn_start(ctx->npc); } =20 -static bool avr_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - gen_breakpoint(ctx); - return true; -} - static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); @@ -3069,7 +3060,6 @@ static const TranslatorOps avr_tr_ops =3D { .init_disas_context =3D avr_tr_init_disas_context, .tb_start =3D avr_tr_tb_start, .insn_start =3D avr_tr_insn_start, - .breakpoint_check =3D avr_tr_breakpoint_check, .translate_insn =3D avr_tr_translate_insn, .tb_stop =3D avr_tr_tb_stop, .disas_log =3D avr_tr_disas_log, diff --git a/target/cris/translate.c b/target/cris/translate.c index 9258c13e9f..a84b753349 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3118,25 +3118,6 @@ static void cris_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) tcg_gen_insn_start(dc->delayed_branch =3D=3D 1 ? dc->ppc | 1 : dc->pc); } =20 -static bool cris_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= pu, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - cris_evaluate_flags(dc); - tcg_gen_movi_tl(env_pc, dc->pc); - t_gen_raise_exception(EXCP_DEBUG); - dc->base.is_jmp =3D DISAS_NORETURN; - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - dc->pc +=3D 2; - return true; -} - static void cris_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -3315,7 +3296,6 @@ static const TranslatorOps cris_tr_ops =3D { .init_disas_context =3D cris_tr_init_disas_context, .tb_start =3D cris_tr_tb_start, .insn_start =3D cris_tr_insn_start, - .breakpoint_check =3D cris_tr_breakpoint_check, .translate_insn =3D cris_tr_translate_insn, .tb_stop =3D cris_tr_tb_stop, .disas_log =3D cris_tr_disas_log, diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index b23d36adf5..54fdcaa5e8 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -540,22 +540,6 @@ static void hexagon_tr_insn_start(DisasContextBase *dc= base, CPUState *cpu) tcg_gen_insn_start(ctx->base.pc_next); } =20 -static bool hexagon_tr_breakpoint_check(DisasContextBase *dcbase, CPUState= *cpu, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - gen_exception_end_tb(ctx, EXCP_DEBUG); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - ctx->base.pc_next +=3D 4; - return true; -} - static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx) { target_ulong page_start =3D ctx->base.pc_first & TARGET_PAGE_MASK; @@ -631,7 +615,6 @@ static const TranslatorOps hexagon_tr_ops =3D { .init_disas_context =3D hexagon_tr_init_disas_context, .tb_start =3D hexagon_tr_tb_start, .insn_start =3D hexagon_tr_insn_start, - .breakpoint_check =3D hexagon_tr_breakpoint_check, .translate_insn =3D hexagon_tr_translate_packet, .tb_stop =3D hexagon_tr_tb_stop, .disas_log =3D hexagon_tr_disas_log, diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 2552747138..b18150ef8d 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4159,16 +4159,6 @@ static void hppa_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cs) tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b); } =20 -static bool hppa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= s, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - gen_excp(ctx, EXCP_DEBUG); - ctx->base.pc_next +=3D 4; - return true; -} - static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); @@ -4330,7 +4320,6 @@ static const TranslatorOps hppa_tr_ops =3D { .init_disas_context =3D hppa_tr_init_disas_context, .tb_start =3D hppa_tr_tb_start, .insn_start =3D hppa_tr_insn_start, - .breakpoint_check =3D hppa_tr_breakpoint_check, .translate_insn =3D hppa_tr_translate_insn, .tb_stop =3D hppa_tr_tb_stop, .disas_log =3D hppa_tr_disas_log, diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 8520d5a1e2..aacb605eee 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2604,14 +2604,6 @@ static void gen_interrupt(DisasContext *s, int intno, s->base.is_jmp =3D DISAS_NORETURN; } =20 -static void gen_debug(DisasContext *s) -{ - gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); - gen_helper_debug(cpu_env); - s->base.is_jmp =3D DISAS_NORETURN; -} - static void gen_set_hflag(DisasContext *s, uint32_t mask) { if ((s->flags & mask) =3D=3D 0) { @@ -8635,25 +8627,6 @@ static void i386_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); } =20 -static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= pu, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - /* If RF is set, suppress an internally generated breakpoint. */ - int flags =3D dc->base.tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY; - if (bp->flags & flags) { - gen_debug(dc); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the generic logic setting tb->size later does the right thing. = */ - dc->base.pc_next +=3D 1; - return true; - } else { - return false; - } -} - static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -8721,7 +8694,6 @@ static const TranslatorOps i386_tr_ops =3D { .init_disas_context =3D i386_tr_init_disas_context, .tb_start =3D i386_tr_tb_start, .insn_start =3D i386_tr_insn_start, - .breakpoint_check =3D i386_tr_breakpoint_check, .translate_insn =3D i386_tr_translate_insn, .tb_stop =3D i386_tr_tb_stop, .disas_log =3D i386_tr_disas_log, diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 1fee04b8dd..c34d9aed61 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -6208,23 +6208,6 @@ static void m68k_tr_insn_start(DisasContextBase *dcb= ase, CPUState *cpu) tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); } =20 -static bool m68k_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= pu, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - gen_exception(dc, dc->base.pc_next, EXCP_DEBUG); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - dc->base.pc_next +=3D 2; - - return true; -} - static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -6310,7 +6293,6 @@ static const TranslatorOps m68k_tr_ops =3D { .init_disas_context =3D m68k_tr_init_disas_context, .tb_start =3D m68k_tr_tb_start, .insn_start =3D m68k_tr_insn_start, - .breakpoint_check =3D m68k_tr_breakpoint_check, .translate_insn =3D m68k_tr_translate_insn, .tb_stop =3D m68k_tr_tb_stop, .disas_log =3D m68k_tr_disas_log, diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index c68a84a219..a14ffed784 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1673,23 +1673,6 @@ static void mb_tr_insn_start(DisasContextBase *dcb, = CPUState *cs) dc->insn_start =3D tcg_last_op(); } =20 -static bool mb_tr_breakpoint_check(DisasContextBase *dcb, CPUState *cs, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcb, DisasContext, base); - - gen_raise_exception_sync(dc, EXCP_DEBUG); - - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - dc->base.pc_next +=3D 4; - return true; -} - static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) { DisasContext *dc =3D container_of(dcb, DisasContext, base); @@ -1854,7 +1837,6 @@ static const TranslatorOps mb_tr_ops =3D { .init_disas_context =3D mb_tr_init_disas_context, .tb_start =3D mb_tr_tb_start, .insn_start =3D mb_tr_insn_start, - .breakpoint_check =3D mb_tr_breakpoint_check, .translate_insn =3D mb_tr_translate_insn, .tb_stop =3D mb_tr_tb_stop, .disas_log =3D mb_tr_disas_log, diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index fd980ea966..5b03545f09 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -16178,24 +16178,6 @@ static void mips_tr_insn_start(DisasContextBase *d= cbase, CPUState *cs) ctx->btarget); } =20 -static bool mips_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *c= s, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - save_cpu_state(ctx, 1); - ctx->base.is_jmp =3D DISAS_NORETURN; - gen_helper_raise_exception_debug(cpu_env); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - ctx->base.pc_next +=3D 4; - return true; -} - static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { CPUMIPSState *env =3D cs->env_ptr; @@ -16303,7 +16285,6 @@ static const TranslatorOps mips_tr_ops =3D { .init_disas_context =3D mips_tr_init_disas_context, .tb_start =3D mips_tr_tb_start, .insn_start =3D mips_tr_insn_start, - .breakpoint_check =3D mips_tr_breakpoint_check, .translate_insn =3D mips_tr_translate_insn, .tb_stop =3D mips_tr_tb_stop, .disas_log =3D mips_tr_disas_log, diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 17742cebc7..08d7ac5398 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -744,16 +744,6 @@ static const char * const regnames[] =3D { =20 #include "exec/gen-icount.h" =20 -static void gen_exception(DisasContext *dc, uint32_t excp) -{ - TCGv_i32 tmp =3D tcg_const_i32(excp); - - tcg_gen_movi_tl(cpu_R[R_PC], dc->pc); - gen_helper_raise_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); - dc->base.is_jmp =3D DISAS_NORETURN; -} - /* generate intermediate code for basic block 'tb'. */ static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState= *cs) { @@ -777,22 +767,6 @@ static void nios2_tr_insn_start(DisasContextBase *dcba= se, CPUState *cs) tcg_gen_insn_start(dcbase->pc_next); } =20 -static bool nios2_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *= cs, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - gen_exception(dc, EXCP_DEBUG); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - dc->base.pc_next +=3D 4; - return true; -} - static void nios2_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -870,7 +844,6 @@ static const TranslatorOps nios2_tr_ops =3D { .init_disas_context =3D nios2_tr_init_disas_context, .tb_start =3D nios2_tr_tb_start, .insn_start =3D nios2_tr_insn_start, - .breakpoint_check =3D nios2_tr_breakpoint_check, .translate_insn =3D nios2_tr_translate_insn, .tb_stop =3D nios2_tr_tb_stop, .disas_log =3D nios2_tr_disas_log, diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 059da48475..d6ea536744 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1609,22 +1609,6 @@ static void openrisc_tr_insn_start(DisasContextBase = *dcbase, CPUState *cs) | (dc->base.num_insns > 1 ? 2 : 0)); } =20 -static bool openrisc_tr_breakpoint_check(DisasContextBase *dcbase, CPUStat= e *cs, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); - gen_exception(dc, EXCP_DEBUG); - dc->base.is_jmp =3D DISAS_NORETURN; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next +=3D 4; - return true; -} - static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState = *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -1727,7 +1711,6 @@ static const TranslatorOps openrisc_tr_ops =3D { .init_disas_context =3D openrisc_tr_init_disas_context, .tb_start =3D openrisc_tr_tb_start, .insn_start =3D openrisc_tr_insn_start, - .breakpoint_check =3D openrisc_tr_breakpoint_check, .translate_insn =3D openrisc_tr_translate_insn, .tb_stop =3D openrisc_tr_tb_stop, .disas_log =3D openrisc_tr_disas_log, diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 0a55cb7181..171b216e17 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -8565,23 +8565,6 @@ static void ppc_tr_insn_start(DisasContextBase *dcba= se, CPUState *cs) tcg_gen_insn_start(dcbase->pc_next); } =20 -static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - gen_update_nip(ctx, ctx->base.pc_next); - gen_debug_exception(ctx); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be properly - * cleared -- thus we increment the PC here so that the logic - * setting tb->size below does the right thing. - */ - ctx->base.pc_next +=3D 4; - return true; -} - static bool is_prefix_insn(DisasContext *ctx, uint32_t insn) { REQUIRE_INSNS_FLAGS2(ctx, ISA310); @@ -8710,7 +8693,6 @@ static const TranslatorOps ppc_tr_ops =3D { .init_disas_context =3D ppc_tr_init_disas_context, .tb_start =3D ppc_tr_tb_start, .insn_start =3D ppc_tr_insn_start, - .breakpoint_check =3D ppc_tr_breakpoint_check, .translate_insn =3D ppc_tr_translate_insn, .tb_stop =3D ppc_tr_tb_stop, .disas_log =3D ppc_tr_disas_log, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index deda0c8a44..6983be5723 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -961,22 +961,6 @@ static void riscv_tr_insn_start(DisasContextBase *dcba= se, CPUState *cpu) tcg_gen_insn_start(ctx->base.pc_next); } =20 -static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *= cpu, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); - ctx->base.is_jmp =3D DISAS_NORETURN; - gen_exception_debug(); - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx->base.pc_next +=3D 4; - return true; -} - static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); @@ -1029,7 +1013,6 @@ static const TranslatorOps riscv_tr_ops =3D { .init_disas_context =3D riscv_tr_init_disas_context, .tb_start =3D riscv_tr_tb_start, .insn_start =3D riscv_tr_insn_start, - .breakpoint_check =3D riscv_tr_breakpoint_check, .translate_insn =3D riscv_tr_translate_insn, .tb_stop =3D riscv_tr_tb_stop, .disas_log =3D riscv_tr_disas_log, diff --git a/target/rx/translate.c b/target/rx/translate.c index 23a626438a..a3cf720455 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2309,19 +2309,6 @@ static void rx_tr_insn_start(DisasContextBase *dcbas= e, CPUState *cs) tcg_gen_insn_start(ctx->base.pc_next); } =20 -static bool rx_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - /* We have hit a breakpoint - make sure PC is up-to-date */ - tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); - gen_helper_debug(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - ctx->base.pc_next +=3D 1; - return true; -} - static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); @@ -2373,7 +2360,6 @@ static const TranslatorOps rx_tr_ops =3D { .init_disas_context =3D rx_tr_init_disas_context, .tb_start =3D rx_tr_tb_start, .insn_start =3D rx_tr_insn_start, - .breakpoint_check =3D rx_tr_breakpoint_check, .translate_insn =3D rx_tr_translate_insn, .tb_stop =3D rx_tr_tb_stop, .disas_log =3D rx_tr_disas_log, diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 92fa7656c2..0632b0374b 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6552,29 +6552,6 @@ static void s390x_tr_insn_start(DisasContextBase *dc= base, CPUState *cs) { } =20 -static bool s390x_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *= cs, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - /* - * Emit an insn_start to accompany the breakpoint exception. - * The ILEN value is a dummy, since this does not result in - * an s390x exception, but an internal qemu exception which - * brings us back to interact with the gdbstub. - */ - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 2); - - dc->base.is_jmp =3D DISAS_PC_STALE; - dc->do_debug =3D true; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size does the right thing. */ - dc->base.pc_next +=3D 2; - return true; -} - static void s390x_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { CPUS390XState *env =3D cs->env_ptr; @@ -6642,7 +6619,6 @@ static const TranslatorOps s390x_tr_ops =3D { .init_disas_context =3D s390x_tr_init_disas_context, .tb_start =3D s390x_tr_tb_start, .insn_start =3D s390x_tr_insn_start, - .breakpoint_check =3D s390x_tr_breakpoint_check, .translate_insn =3D s390x_tr_translate_insn, .tb_stop =3D s390x_tr_tb_stop, .disas_log =3D s390x_tr_disas_log, diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 40898e2393..8704fea1ca 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2289,23 +2289,6 @@ static void sh4_tr_insn_start(DisasContextBase *dcba= se, CPUState *cs) tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags); } =20 -static bool sh4_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - - /* We have hit a breakpoint - make sure PC is up-to-date */ - gen_save_cpu_state(ctx, true); - gen_helper_debug(cpu_env); - ctx->base.is_jmp =3D DISAS_NORETURN; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - ctx->base.pc_next +=3D 2; - return true; -} - static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { CPUSH4State *env =3D cs->env_ptr; @@ -2369,7 +2352,6 @@ static const TranslatorOps sh4_tr_ops =3D { .init_disas_context =3D sh4_tr_init_disas_context, .tb_start =3D sh4_tr_tb_start, .insn_start =3D sh4_tr_insn_start, - .breakpoint_check =3D sh4_tr_breakpoint_check, .translate_insn =3D sh4_tr_translate_insn, .tb_stop =3D sh4_tr_tb_stop, .disas_log =3D sh4_tr_disas_log, diff --git a/target/sparc/translate.c b/target/sparc/translate.c index e530cb4aa8..11de5a4963 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5854,22 +5854,6 @@ static void sparc_tr_insn_start(DisasContextBase *dc= base, CPUState *cs) } } =20 -static bool sparc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *= cs, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - if (dc->pc !=3D dc->base.pc_first) { - save_state(dc); - } - gen_helper_debug(cpu_env); - tcg_gen_exit_tb(NULL, 0); - dc->base.is_jmp =3D DISAS_NORETURN; - /* update pc_next so that the current instruction is included in tb->s= ize */ - dc->base.pc_next +=3D 4; - return true; -} - static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -5932,7 +5916,6 @@ static const TranslatorOps sparc_tr_ops =3D { .init_disas_context =3D sparc_tr_init_disas_context, .tb_start =3D sparc_tr_tb_start, .insn_start =3D sparc_tr_insn_start, - .breakpoint_check =3D sparc_tr_breakpoint_check, .translate_insn =3D sparc_tr_translate_insn, .tb_stop =3D sparc_tr_tb_stop, .disas_log =3D sparc_tr_disas_log, diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 865020754d..a0cc0f1cb3 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8810,21 +8810,6 @@ static void tricore_tr_insn_start(DisasContextBase *= dcbase, CPUState *cpu) tcg_gen_insn_start(ctx->base.pc_next); } =20 -static bool tricore_tr_breakpoint_check(DisasContextBase *dcbase, CPUState= *cpu, - const CPUBreakpoint *bp) -{ - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - generate_qemu_excp(ctx, EXCP_DEBUG); - /* - * The address covered by the breakpoint must be included in - * [tb->pc, tb->pc + tb->size) in order to for it to be - * properly cleared -- thus we increment the PC here so that - * the logic setting tb->size below does the right thing. - */ - ctx->base.pc_next +=3D 4; - return true; -} - static bool insn_crosses_page(CPUTriCoreState *env, DisasContext *ctx) { /* @@ -8898,7 +8883,6 @@ static const TranslatorOps tricore_tr_ops =3D { .init_disas_context =3D tricore_tr_init_disas_context, .tb_start =3D tricore_tr_tb_start, .insn_start =3D tricore_tr_insn_start, - .breakpoint_check =3D tricore_tr_breakpoint_check, .translate_insn =3D tricore_tr_translate_insn, .tb_stop =3D tricore_tr_tb_stop, .disas_log =3D tricore_tr_disas_log, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 7094cfcf1d..20399d6a04 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1232,22 +1232,6 @@ static void xtensa_tr_insn_start(DisasContextBase *d= cbase, CPUState *cpu) tcg_gen_insn_start(dcbase->pc_next); } =20 -static bool xtensa_tr_breakpoint_check(DisasContextBase *dcbase, CPUState = *cpu, - const CPUBreakpoint *bp) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - - tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); - gen_exception(dc, EXCP_DEBUG); - dc->base.is_jmp =3D DISAS_NORETURN; - /* The address covered by the breakpoint must be included in - [tb->pc, tb->pc + tb->size) in order to for it to be - properly cleared -- thus we increment the PC here so that - the logic setting tb->size below does the right thing. */ - dc->base.pc_next +=3D 2; - return true; -} - static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *c= pu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -1330,7 +1314,6 @@ static const TranslatorOps xtensa_translator_ops =3D { .init_disas_context =3D xtensa_tr_init_disas_context, .tb_start =3D xtensa_tr_tb_start, .insn_start =3D xtensa_tr_insn_start, - .breakpoint_check =3D xtensa_tr_breakpoint_check, .translate_insn =3D xtensa_tr_translate_insn, .tb_stop =3D xtensa_tr_tb_stop, .disas_log =3D xtensa_tr_disas_log, --=20 2.25.1 From nobody Sat May 18 04:13:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[204.210.126.223]) by smtp.gmail.com with ESMTPSA id e4sm25378054pgi.94.2021.07.19.18.18.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 18:18:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PNGGuAbGOXbZh1djyRYowe+1Bkitpoo3mG0dYZQDf8E=; b=LR4emvHi2lR32ttWc8zdgrfA86cwTqToo7HMrUffpK6YNOzk4WIP4JN60THVihEqHS LpwamsK5y5kNbK0Dh6pLjC9WxYpTArgJh5NP0R+nAyDb7ltYjGLjSF7P+T4uD9FUD0ML HlziEq4vkC9MoLfuRnLr0/Ip9TzC2RlVIWBQkP0kPvbRZkk4I5vjniRALPoIYXauW2qq PVwUAbBhL8O5yuT2SqjQSKyG5dlk6RH0bi4BZRtUr919En5lD3kWpKLasZxZq3PM8UGE cc7dpktT+3TiR+27LGwQV3Xc1s8MLJDDKPkme/0EyyvHK4Hy2y5R650GiDUUu0PeV08x C88g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PNGGuAbGOXbZh1djyRYowe+1Bkitpoo3mG0dYZQDf8E=; b=thiPsuykej90Iqam0B4hvmI7Ttxu2NFjG2RgjLMcMWwu9lj3oXoP3gq4c9eQ3iEQ+R xao354IrZ9huTlNR2H/0z0sXzuL2ppHyOme8UUzehLZotmblVM9LECh51D0/XF6Gd38y 0vlegFqNNC6dNd9sFkdUVvOKjJlketxR3OFAyIkUkDWiOGLwlfS+NASUhC0S8RBg+b6V 0PNcLqxMt1NI3TI/EjQ0aFtxB1vK24PFQK+3bhyJ0j+gr1Rq//jHTQaPoXpBQn2mupZC B7fXqrg+QQEbHzkBKiSvm4l6HUeHDy8X5jnlrHYwEEKn/nTeMRiiLyG+hrn3DLOkbZ4n moVg== X-Gm-Message-State: AOAM531HHBuS/P8jV+PmLQbEmTe1ZDKwYF3nWAxdIISkeGjSDAjkupFF dr+OeN1PJWpTbpfacro06qn7fVjJ2VDvdA== X-Google-Smtp-Source: ABdhPJzPxaiDYKA33GPqLAN2rENxY+nAh6tmB7t0tNbDlsSea3ArROFOWFAFDv+MBfFoL66x1JgfKQ== X-Received: by 2002:a63:e350:: with SMTP id o16mr28267418pgj.98.1626743903636; Mon, 19 Jul 2021 18:18:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v5 14/15] accel/tcg: Hoist tb_cflags to a local in translator_loop Date: Mon, 19 Jul 2021 15:17:59 -1000 Message-Id: <20210720011800.483966-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720011800.483966-1-richard.henderson@linaro.org> References: <20210720011800.483966-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626744728541100001 The access internal to tb_cflags() is atomic. Avoid re-reading it as such for the multiple uses. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- accel/tcg/translator.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 4f3728c278..b45337f3ba 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -50,6 +50,7 @@ bool translator_use_goto_tb(DisasContextBase *db, target_= ulong dest) void translator_loop(const TranslatorOps *ops, DisasContextBase *db, CPUState *cpu, TranslationBlock *tb, int max_insns) { + uint32_t cflags =3D tb_cflags(tb); bool plugin_enabled; =20 /* Initialize DisasContext */ @@ -72,8 +73,7 @@ void translator_loop(const TranslatorOps *ops, DisasConte= xtBase *db, ops->tb_start(db, cpu); tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ =20 - plugin_enabled =3D plugin_gen_tb_start(cpu, tb, - tb_cflags(db->tb) & CF_MEMI_ONLY); + plugin_enabled =3D plugin_gen_tb_start(cpu, tb, cflags & CF_MEMI_ONLY); =20 while (true) { db->num_insns++; @@ -88,14 +88,13 @@ void translator_loop(const TranslatorOps *ops, DisasCon= textBase *db, update db->pc_next and db->is_jmp to indicate what should be done next -- either exiting this loop or locate the start of the next instruction. */ - if (db->num_insns =3D=3D db->max_insns - && (tb_cflags(db->tb) & CF_LAST_IO)) { + if (db->num_insns =3D=3D db->max_insns && (cflags & CF_LAST_IO)) { /* Accept I/O on the last instruction. */ gen_io_start(); ops->translate_insn(db, cpu); } else { /* we should only see CF_MEMI_ONLY for io_recompile */ - tcg_debug_assert(!(tb_cflags(db->tb) & CF_MEMI_ONLY)); + tcg_debug_assert(!(cflags & CF_MEMI_ONLY)); ops->translate_insn(db, cpu); } =20 --=20 2.25.1 From nobody Sat May 18 04:13:29 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1626744610675472.97815950295796; Mon, 19 Jul 2021 18:30:10 -0700 (PDT) Received: from localhost ([::1]:39636 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m5eaG-0000V8-Bu for importer@patchew.org; Mon, 19 Jul 2021 21:30:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:32930) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m5eOx-0006u5-Vd for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:28 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:34619) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m5eOw-0003Xm-7A for qemu-devel@nongnu.org; Mon, 19 Jul 2021 21:18:27 -0400 Received: by mail-pg1-x534.google.com with SMTP id 62so21069217pgf.1 for ; Mon, 19 Jul 2021 18:18:25 -0700 (PDT) Received: from localhost.localdomain (204-210-126-223.res.spectrum.com. [204.210.126.223]) by smtp.gmail.com with ESMTPSA id e4sm25378054pgi.94.2021.07.19.18.18.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Jul 2021 18:18:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2FDXCfbsBbtNLEY6fDNcDSK7r82AZnHwFJMSFaWU+Ps=; b=AiEk4SKX09e6GQ31+kpuHldhswWPA0n9reD8aBJdvM5IpDpuBwQ3guioynt/NF0gbg EfCQHZRaIUv21gUwo+3sVQMfLGyYDLZoRIySruxoSm/4gdFHkLu5P9qZbcgmNq+yPnUK fUEUxFJ/4zEqxZduVB4OCirD5YCGeLu1p71haIcpCduIz7AG6Z76x9/6RUl9sq2o7PLB 1OufsmRq26g5qO5/H3h/PQt/JpcmL46siXSuMbVaGmRws8ic9Au/UWAS6N2e/52C6YCE OxX+K7zFX56yIL5kTF2QhU5NsHlPtF+T4gKxdNnZhDo99MZZWnqQ7t5q1vaIDvax5lEI nKXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2FDXCfbsBbtNLEY6fDNcDSK7r82AZnHwFJMSFaWU+Ps=; b=F+giW+UbCE4kYFoKpM6ek4AffdWYaDE0aNXLNSj3l6D7iDuN87b4RZ0PQBXIXoZDOm MotkdnDR94SarjpmjA3Q2U5fYBZWBfrzm71EJHYC2O/yEybm6ITfPukdQf7BNjDX9cyQ RQaAYBartkmcK33m2x571jVzwG1oiEkU0Ks8axSCTbo+qE7l4eztDivJ6mLkPFZhVOaS rl4yNztdgWVWBawJYOr4PLXb5PY8SZQ6BN2kD6e7kmzQe7dv10WfGy4ljPZHeC39YO/t wqbc9EBr7ab/SZ3mBXIHs+WDMQ8OQ6iZWnTb/5TSDO+U6/oIkirV+UmvFE0Dvoa2gh1w D5GQ== X-Gm-Message-State: AOAM530ve0YWwAKdpaPceGR3OQNGWQpim/NtrmpMTs4Kv2+5qqYSfVOb NMbY5pyQTlza7cnWNeWqEZRvCySMyEFi5A== X-Google-Smtp-Source: ABdhPJwlmS1Vfs6DyhXkqJ87p5tj5YoNMg+FjlUd8s/YL603nTRPxrfLAM6bDmElgmw5qxPC+qv5yw== X-Received: by 2002:a65:5186:: with SMTP id h6mr27964717pgq.62.1626743904945; Mon, 19 Jul 2021 18:18:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH for-6.1 v5 15/15] accel/tcg: Record singlestep_enabled in tb->cflags Date: Mon, 19 Jul 2021 15:18:00 -1000 Message-Id: <20210720011800.483966-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210720011800.483966-1-richard.henderson@linaro.org> References: <20210720011800.483966-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, mark.cave-ayland@ilande.co.uk, alex.bennee@linaro.org, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1626744615264100001 Content-Type: text/plain; charset="utf-8" Set CF_SINGLE_STEP when single-stepping is enabled. This avoids the need to flush all tb's when turning single-stepping on or off. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 1 + accel/tcg/cpu-exec.c | 7 ++++++- accel/tcg/translate-all.c | 4 ---- accel/tcg/translator.c | 7 +------ cpu.c | 4 ---- 5 files changed, 8 insertions(+), 15 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 6873cce8df..5d1b6d80fb 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -497,6 +497,7 @@ struct TranslationBlock { #define CF_COUNT_MASK 0x000001ff #define CF_NO_GOTO_TB 0x00000200 /* Do not chain with goto_tb */ #define CF_NO_GOTO_PTR 0x00000400 /* Do not chain with goto_ptr */ +#define CF_SINGLE_STEP 0x00000800 /* gdbstub single-step in effect */ #define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ #define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ #define CF_USE_ICOUNT 0x00020000 diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index f5371e03d4..8b2d41bfa0 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -150,10 +150,15 @@ uint32_t curr_cflags(CPUState *cpu) uint32_t cflags =3D cpu->tcg_cflags; =20 /* + * Record gdb single-step. We should be exiting the TB by raising + * EXCP_DEBUG, but to simplify other tests, disable chaining too. + * * For singlestep and -d nochain, suppress goto_tb so that * we can log -d cpu,exec after every TB. */ - if (singlestep) { + if (unlikely(cpu->singlestep_enabled)) { + cflags |=3D CF_NO_GOTO_TB | CF_NO_GOTO_PTR | CF_SINGLE_STEP | 1; + } else if (singlestep) { cflags |=3D CF_NO_GOTO_TB | 1; } else if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) { cflags |=3D CF_NO_GOTO_TB; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bf82c15aab..bbfcfb698c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1432,10 +1432,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu, } QEMU_BUILD_BUG_ON(CF_COUNT_MASK + 1 !=3D TCG_MAX_INSNS); =20 - if (cpu->singlestep_enabled) { - max_insns =3D 1; - } - buffer_overflow: tb =3D tcg_tb_alloc(tcg_ctx); if (unlikely(!tb)) { diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index b45337f3ba..c53a7f8e44 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -38,11 +38,6 @@ bool translator_use_goto_tb(DisasContextBase *db, target= _ulong dest) return false; } =20 - /* Suppress goto_tb in the case of single-steping. */ - if (db->singlestep_enabled) { - return false; - } - /* Check for the dest on the same page as the start of the TB. */ return ((db->pc_first ^ dest) & TARGET_PAGE_MASK) =3D=3D 0; } @@ -60,7 +55,7 @@ void translator_loop(const TranslatorOps *ops, DisasConte= xtBase *db, db->is_jmp =3D DISAS_NEXT; db->num_insns =3D 0; db->max_insns =3D max_insns; - db->singlestep_enabled =3D cpu->singlestep_enabled; + db->singlestep_enabled =3D cflags & CF_SINGLE_STEP; =20 ops->init_disas_context(db, cpu); tcg_debug_assert(db->is_jmp =3D=3D DISAS_NEXT); /* no early exit */ diff --git a/cpu.c b/cpu.c index 660b56f431..addcb5db9c 100644 --- a/cpu.c +++ b/cpu.c @@ -316,10 +316,6 @@ void cpu_single_step(CPUState *cpu, int enabled) cpu->singlestep_enabled =3D enabled; if (kvm_enabled()) { kvm_update_guest_debug(cpu, 0); - } else { - /* must flush all the translated code to avoid inconsistencies= */ - /* XXX: only flush what is necessary */ - tb_flush(cpu); } trace_breakpoint_singlestep(cpu->cpu_index, enabled); } --=20 2.25.1