From nobody Mon Feb 9 12:26:13 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162620505241155.3249107735071; Tue, 13 Jul 2021 12:37:32 -0700 (PDT) Received: from localhost ([::1]:42352 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m3ODj-0006UB-4a for importer@patchew.org; Tue, 13 Jul 2021 15:37:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51722) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m3O1I-0007OA-4F; Tue, 13 Jul 2021 15:24:40 -0400 Received: from new4-smtp.messagingengine.com ([66.111.4.230]:55507) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m3O1G-0003OZ-DO; Tue, 13 Jul 2021 15:24:39 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailnew.nyi.internal (Postfix) with ESMTP id 93B21580ABA; Tue, 13 Jul 2021 15:24:36 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Tue, 13 Jul 2021 15:24:36 -0400 Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 13 Jul 2021 15:24:34 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irrelevant.dk; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=j/2kmdR7NtEfS Fyn3CnrhKEbyG00F/2ApTM4WM7M1Tk=; b=iyGw0epOf6Ug3CCnaBBmyNTlLONBt YD66tg1QoURD7YJlevvzlF/M0JjVuIELT5no3/DASkn+PlIszxIMtks4GxDRMYfZ cEkyrBGsjZVMXijyXGrdKBmeWlW1JmLkkJpHXhjZPNRTsVDK6rCi0Ze+cWsI6g0h h5eNIfi0YVtyRNOg6iC0jBlGfXEe/AzaOWSPABCNLC0zL1GRcCaJXTIBrpBa0ket RTQAcrZX01Lm0+wGmYa6O4J7Ty74/UbH9Rh2qTVaZQD0yQoAfE8q1XH3HRB45jM1 fY9h8TaWmosnXxxxL3n/P/WPQv5uP8EFOVJjc7RKwJm1CT+Ga75nf9F2g== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm3; bh=j/2kmdR7NtEfSFyn3CnrhKEbyG00F/2ApTM4WM7M1Tk=; b=SehST0Qx dgfXOwahxwRwaDyn9W6kz7wHKPKpl3CW2ryFNq5WEYW6MV6XjGUSYqJLoAhQ2ARA qksBXXqqK+/e4orMoNX1eHkS6xdEh8dSt+RXNtW8JqI7AJI4lA8JJG8e4PVDKC7K hpSgnrOFCtB4igDWQZF5reUp9ONdgSjceP8RZ1LRSPE1T8wCZQfQqvcs6Ykq3aHy ZsV+wMqHT1j7jQnWHiJrxmPoquJX2D7GdhLsoKK2am/GZLeMOBeU7yqqaeAbJL5F UYjCza4egMxe/4+px10q5HxoNFmiPBsKJnn/dE4paExzubxAIhEW6M3yg3jV7EQj ZvNpdcLQTxEeJg== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvtddrudehgdduvdehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefmlhgruhhs ucflvghnshgvnhcuoehithhssehirhhrvghlvghvrghnthdrughkqeenucggtffrrghtth gvrhhnpeeuleetgeeiuefhgfekfefgveejiefgteekiedtgfdtieefhfdthfefueffvefg keenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpehith hssehirhhrvghlvghvrghnthdrughk X-ME-Proxy: From: Klaus Jensen To: qemu-devel@nongnu.org Subject: [PATCH v2 1/5] hw/nvme: split pmrmsc register into upper and lower Date: Tue, 13 Jul 2021 21:24:24 +0200 Message-Id: <20210713192428.950160-2-its@irrelevant.dk> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210713192428.950160-1-its@irrelevant.dk> References: <20210713192428.950160-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=66.111.4.230; envelope-from=its@irrelevant.dk; helo=new4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , Thomas Huth , qemu-block@nongnu.org, Peter Maydell , Laurent Vivier , Klaus Jensen , Gollu Appalanaidu , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1626205052956100001 Content-Type: text/plain; charset="utf-8" From: Klaus Jensen The specification uses a set of 32 bit PMRMSCL and PMRMSCU registers to make up the 64 bit logical PMRMSC register. Make it so. Signed-off-by: Klaus Jensen --- include/block/nvme.h | 31 ++++++++++++++++--------------- hw/nvme/ctrl.c | 9 +++++---- 2 files changed, 21 insertions(+), 19 deletions(-) diff --git a/include/block/nvme.h b/include/block/nvme.h index 527105fafc0b..84053b68b987 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -26,7 +26,8 @@ typedef struct QEMU_PACKED NvmeBar { uint32_t pmrsts; uint32_t pmrebs; uint32_t pmrswtp; - uint64_t pmrmsc; + uint32_t pmrmscl; + uint32_t pmrmscu; uint8_t css[484]; } NvmeBar; =20 @@ -475,25 +476,25 @@ enum NvmePmrswtpMask { #define NVME_PMRSWTP_SET_PMRSWTV(pmrswtp, val) \ (pmrswtp |=3D (uint64_t)(val & PMRSWTP_PMRSWTV_MASK) << PMRSWTP_PMRSWT= V_SHIFT) =20 -enum NvmePmrmscShift { - PMRMSC_CMSE_SHIFT =3D 1, - PMRMSC_CBA_SHIFT =3D 12, +enum NvmePmrmsclShift { + PMRMSCL_CMSE_SHIFT =3D 1, + PMRMSCL_CBA_SHIFT =3D 12, }; =20 -enum NvmePmrmscMask { - PMRMSC_CMSE_MASK =3D 0x1, - PMRMSC_CBA_MASK =3D 0xfffffffffffff, +enum NvmePmrmsclMask { + PMRMSCL_CMSE_MASK =3D 0x1, + PMRMSCL_CBA_MASK =3D 0xfffff, }; =20 -#define NVME_PMRMSC_CMSE(pmrmsc) \ - ((pmrmsc >> PMRMSC_CMSE_SHIFT) & PMRMSC_CMSE_MASK) -#define NVME_PMRMSC_CBA(pmrmsc) \ - ((pmrmsc >> PMRMSC_CBA_SHIFT) & PMRMSC_CBA_MASK) +#define NVME_PMRMSCL_CMSE(pmrmscl) \ + ((pmrmscl >> PMRMSCL_CMSE_SHIFT) & PMRMSCL_CMSE_MASK) +#define NVME_PMRMSCL_CBA(pmrmscl) \ + ((pmrmscl >> PMRMSCL_CBA_SHIFT) & PMRMSCL_CBA_MASK) =20 -#define NVME_PMRMSC_SET_CMSE(pmrmsc, val) \ - (pmrmsc |=3D (uint64_t)(val & PMRMSC_CMSE_MASK) << PMRMSC_CMSE_SHIFT) -#define NVME_PMRMSC_SET_CBA(pmrmsc, val) \ - (pmrmsc |=3D (uint64_t)(val & PMRMSC_CBA_MASK) << PMRMSC_CBA_SHIFT) +#define NVME_PMRMSCL_SET_CMSE(pmrmscl, val) \ + (pmrmscl |=3D (uint32_t)(val & PMRMSCL_CMSE_MASK) << PMRMSCL_CMSE_SHIF= T) +#define NVME_PMRMSCL_SET_CBA(pmrmscl, val) \ + (pmrmscl |=3D (uint32_t)(val & PMRMSCL_CBA_MASK) << PMRMSCL_CBA_SHIFT) =20 enum NvmeSglDescriptorType { NVME_SGL_DESCR_TYPE_DATA_BLOCK =3D 0x0, diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 2f0524e12a36..28299c6f3764 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -5916,11 +5916,12 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offs= et, uint64_t data, return; } =20 - n->bar.pmrmsc =3D (n->bar.pmrmsc & ~0xffffffff) | (data & 0xffffff= ff); + n->bar.pmrmscl =3D data & 0xffffffff; n->pmr.cmse =3D false; =20 - if (NVME_PMRMSC_CMSE(n->bar.pmrmsc)) { - hwaddr cba =3D NVME_PMRMSC_CBA(n->bar.pmrmsc) << PMRMSC_CBA_SH= IFT; + if (NVME_PMRMSCL_CMSE(n->bar.pmrmscl)) { + hwaddr cba =3D n->bar.pmrmscu | + (NVME_PMRMSCL_CBA(n->bar.pmrmscl) << PMRMSCL_CBA_SHIFT); if (cba + int128_get64(n->pmr.dev->mr.size) < cba) { NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 1); return; @@ -5936,7 +5937,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset= , uint64_t data, return; } =20 - n->bar.pmrmsc =3D (n->bar.pmrmsc & 0xffffffff) | (data << 32); + n->bar.pmrmscu =3D data & 0xffffffff; return; default: NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid, --=20 2.32.0