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[83.35.24.93]) by smtp.gmail.com with ESMTPSA id x8sm1465068wrt.93.2021.07.10.10.50.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Jul 2021 10:50:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=y5KSWA1vpNfd6M+9kKkYOA/X1eCKYfSslffBBwebk8k=; b=u42PE4D/A64yM3hVVOsKQ6T9Ox3DEH4QSxhPeKCdkKcJ5CV8jm4xpopXdCyDxiciQn l0BoezHDLZRRCZC9jh0d6r4Hawepz5MSXWQaPbWUW2ww4NV6JssMhRosFtugUMEM3gBK gtw29zXQAjb0w2MmATHWsrGncWPLlws/B6EWqZpIItFZ821bN+CcSL/WPx0osecu0d8k B2cKFfNWHJtX9lvqVn442gtoK8OK5+Z7A5/8Y5WNvz+vflUYgAbMMg5r6x46IdSgSJaW Hr/Z9fZBiaxAsQ/TidCKnWii3HAv/tRe2x7U1ndGHOiuJHkm7KHZ7aOkVq1+r5umAWsd 5AJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=y5KSWA1vpNfd6M+9kKkYOA/X1eCKYfSslffBBwebk8k=; b=fHR3a8aZXmC//Bd8e3F5C0yXSswwFFQJazTA7Xx7OaZTxvHnV7Gd4ocIvLvNT2kIei sP/JK4+dKRYcwN3bYg+Sh+rWDDXOOlZO4fv1SU4G04uFdsz8r5DGxWxuMMFhZvuvXt++ C9H+zg0JX8NGie4nPQsb26Blxp+xaIHOgm6aZ/+jW0LhK3lszFZ+/6kZFMFEENexiolK BBgTHY2V7emV9X/pbhO6KZ1T52WczcAexAF2Pj0d0TASj1713z6ucUZbcPfMzzbkCnhy 2CsWhyM27uRsoP8lhcXII4Nil1UcymNDNbWnID9R95kS0iw03NuEkMWB12KS4DgKdCK5 up/Q== X-Gm-Message-State: AOAM531UCO6lhfSSKERwKmue4XSpb2gzxfNE7c6x9blr+nDl7A4RdniR QGOliXTwJjZ9pNARfxHKOC8= X-Google-Smtp-Source: ABdhPJzHusJlhsRGpTqFNpxpqY9393zpSLuZAKBdsFH0AdwK8KmCcY1fnZ64NcHMbizOeT+hXu+eMw== X-Received: by 2002:adf:dc8b:: with SMTP id r11mr50164893wrj.363.1625939434077; Sat, 10 Jul 2021 10:50:34 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Finn Thain , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Laurent Vivier , Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [NOTFORMERGE PATCH v3 8/8] dp8393x: don't force 32-bit register access Date: Sat, 10 Jul 2021 19:49:54 +0200 Message-Id: <20210710174954.2577195-9-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210710174954.2577195-1-f4bug@amsat.org> References: <20210710174954.2577195-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1625939438276100001 From: Mark Cave-Ayland Commit 3fe9a838ec "dp8393x: Always use 32-bit accesses" set .impl.min_acces= s_size and .impl.max_access_size to 4 to try and fix the Linux jazzsonic driver wh= ich uses 32-bit accesses. The problem with forcing the register access to 32-bit in this way is that = since the dp8393x uses 16-bit registers, a manual endian swap is required for devices= on big endian machines with 32-bit accesses. For both access sizes and machine endians the QEMU memory API can do the ri= ght thing automatically: all that is needed is to set .impl.min_access_size to 2 to d= eclare that the dp8393x implements 16-bit registers. Normally .impl.max_access_size should also be set to 2, however that doesn'= t quite work in this case since the register stride is specified using a (dynamic) = it_shift property which is applied during the MMIO access itself. The effect of this= is that for a 32-bit access the memory API performs 2 x 16-bit accesses, but the us= e of it_shift within the MMIO access itself causes the register value to be repe= ated in both the top 16-bits and bottom 16-bits. The Linux jazzsonic driver expects the = stride to be zero-extended up to access size and therefore fails to correctly detect the= dp8393x device due to the extra data in the top 16-bits. The solution here is to remove .impl.max_access_size so that the memory API= will correctly zero-extend the 16-bit registers to the access size up to and inc= luding it_shift. Since it_shift is never greater than 2 than this will always do t= he right thing for both 16-bit and 32-bit accesses regardless of the machine endian,= allowing the manual endian swap code to be removed. Signed-off-by: Mark Cave-Ayland Fixes: 3fe9a838ec ("dp8393x: Always use 32-bit accesses") Message-Id: <20210705214929.17222-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/net/dp8393x.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index a9224a5bc88..71c82a07c23 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -588,15 +588,14 @@ static uint64_t dp8393x_read(void *opaque, hwaddr add= r, unsigned int size) =20 trace_dp8393x_read(reg, reg_names[reg], val, size); =20 - return s->big_endian ? val << 16 : val; + return val; } =20 -static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, +static void dp8393x_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size) { dp8393xState *s =3D opaque; int reg =3D addr >> s->it_shift; - uint32_t val =3D s->big_endian ? data >> 16 : data; =20 trace_dp8393x_write(reg, reg_names[reg], val, size); =20 @@ -677,11 +676,16 @@ static void dp8393x_write(void *opaque, hwaddr addr, = uint64_t data, } } =20 +/* + * Since .impl.max_access_size is effectively controlled by the it_shift + * property, leave it unspecified for now to allow the memory API to + * correctly zero extend the 16-bit register values to the access size up = to and + * including it_shift. + */ static const MemoryRegionOps dp8393x_ops =3D { .read =3D dp8393x_read, .write =3D dp8393x_write, - .impl.min_access_size =3D 4, - .impl.max_access_size =3D 4, + .impl.min_access_size =3D 2, .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 --=20 2.31.1