From nobody Thu Dec 18 22:18:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625847272; cv=none; d=zohomail.com; s=zohoarc; b=JBTvyc8wf4HYm0XsSzmRUVeGVugc8Nv4r3gEhFzpqZAvmh75SoE4OWWLDs9A2hqNtULGEje9h53Aks2Ea7CJRikWmYChFfB8WPDDlO7I9uhHG2WDGWjv7Mr1wm+asyF8AaDMpQA4I2D9BFbXcUkpG8FxtlRbcyY+PkW9YvDfDEo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625847272; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ABFIjV70ljY3468vVCXOJuCIIQsgtwS9QEm86L1ViA8=; b=n9M9jTVwK5yQs1nRUKhT9kPRtBvSoyA6XNTtr6klFCIpwLGEOpnqgwfbEWihNYNxcOmh8drh7zRJ66jbOf/Vn1s2UZD4YwO75Z1A5Mwdvnxj91FIg6VKLrJ/B9Rh3P4049uwv4VUs5umwThnbwdef+rJGM8r95yYNDbb3dtkyDQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1625847272526159.0329405458234; Fri, 9 Jul 2021 09:14:32 -0700 (PDT) Received: from localhost ([::1]:36946 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1t94-0001XB-VX for importer@patchew.org; Fri, 09 Jul 2021 12:14:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37422) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1t4s-0001Mr-0h for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:10 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:46060) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m1t4p-0000sT-Ea for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:09 -0400 Received: by mail-wr1-x42e.google.com with SMTP id i8so12805839wrp.12 for ; Fri, 09 Jul 2021 09:10:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x19sm5232277wmi.10.2021.07.09.09.10.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 09:10:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ABFIjV70ljY3468vVCXOJuCIIQsgtwS9QEm86L1ViA8=; b=T4P6tiwc08L6W4jTA1Mf7dL5cjG5Tp4GtsM46KEfpwRmcpkjPFTX4N1aguWMwX6mkO xEOR2nZP3s0vbjwpEWzhh/p43g4mttA0NWdKtrflVhYk/9/8O/SLESgSDqAeTBqgMsPy 5LccvudNgdFQzyWcKFT/wdarRbjoVrE5KBECP0Vk0/9y+jXiGEb5LQHqoLHRc5z/FeiA 0cgQvbDvRI7IyMcuiTgWQt1YQqn9C4Tkc/CLHUo2DOuPrc7CKvx92fssIUnTf7f5xa6p jWZX1YwMGEdnJcqsAYzRVfTcn5FNV2vLPTHE58qsXfASjm5XKHwumn8O1yoXX1jDxFQ/ kd4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ABFIjV70ljY3468vVCXOJuCIIQsgtwS9QEm86L1ViA8=; b=i4cxXDi64/d5CO7zabOEkjGPEhiFjPCELy6a3aHH9PI8jwjit0D4I42WS9zGH/pipU fO04dfTXG5/nh10YeA6ckyiqpGnjM8XknFx1j8g+DgJ04p98xD7RllQ8aqo5sAiUQIgA GcALUWZUyMlODdek+I5wI/yjUewR9QHtYElNewobfP9pC6GE69+MnPdWgG1+itLOGV1r GZj5eyak6tSoMTe8r9Z+o1jmYZ9JDkh0n3KeepD0kdF3GUXggNNJ2VyCvKJiz6e6Hufn BBXZAkt6hrp7ap+lQX0zV8JovtLo9O3N5I8oq2Sh1PG1OySzAD1OR3Z5YHg10cf/7oCu ne+w== X-Gm-Message-State: AOAM532pQb9SFTwQO50QapRV4UEtd5b4eP1MDZzF2UtlPI/lO4Je5pfp GFTeAvB+Lel3BFDaFfBv0fpPXo8qAe7CKs1V X-Google-Smtp-Source: ABdhPJyaAsmDO+Z2W6mUiTb6g4w/s/fj2WNXw5UmbvlQfxmMeeepSkl8zpZWe2Ri9pke/uryQeAlJg== X-Received: by 2002:a5d:6850:: with SMTP id o16mr9268877wrw.319.1625847005908; Fri, 09 Jul 2021 09:10:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/17] stm32f100: Add the stm32f100 SoC Date: Fri, 9 Jul 2021 17:09:47 +0100 Message-Id: <20210709161003.25874-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210709161003.25874-1-peter.maydell@linaro.org> References: <20210709161003.25874-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625847274391100002 Content-Type: text/plain; charset="utf-8" From: Alexandre Iooss This SoC is similar to stm32f205 SoC. This will be used by the STM32VLDISCOVERY to create a machine. Signed-off-by: Alexandre Iooss Reviewed-by: Alistair Francis Message-id: 20210617165647.2575955-2-erdnaxe@crans.org Signed-off-by: Peter Maydell --- include/hw/arm/stm32f100_soc.h | 57 +++++++++++ hw/arm/stm32f100_soc.c | 182 +++++++++++++++++++++++++++++++++ MAINTAINERS | 6 ++ hw/arm/Kconfig | 6 ++ hw/arm/meson.build | 1 + 5 files changed, 252 insertions(+) create mode 100644 include/hw/arm/stm32f100_soc.h create mode 100644 hw/arm/stm32f100_soc.c diff --git a/include/hw/arm/stm32f100_soc.h b/include/hw/arm/stm32f100_soc.h new file mode 100644 index 00000000000..71bffcf4fd5 --- /dev/null +++ b/include/hw/arm/stm32f100_soc.h @@ -0,0 +1,57 @@ +/* + * STM32F100 SoC + * + * Copyright (c) 2021 Alexandre Iooss + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_ARM_STM32F100_SOC_H +#define HW_ARM_STM32F100_SOC_H + +#include "hw/char/stm32f2xx_usart.h" +#include "hw/ssi/stm32f2xx_spi.h" +#include "hw/arm/armv7m.h" +#include "qom/object.h" + +#define TYPE_STM32F100_SOC "stm32f100-soc" +OBJECT_DECLARE_SIMPLE_TYPE(STM32F100State, STM32F100_SOC) + +#define STM_NUM_USARTS 3 +#define STM_NUM_SPIS 2 + +#define FLASH_BASE_ADDRESS 0x08000000 +#define FLASH_SIZE (128 * 1024) +#define SRAM_BASE_ADDRESS 0x20000000 +#define SRAM_SIZE (8 * 1024) + +struct STM32F100State { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + char *cpu_type; + + ARMv7MState armv7m; + + STM32F2XXUsartState usart[STM_NUM_USARTS]; + STM32F2XXSPIState spi[STM_NUM_SPIS]; +}; + +#endif diff --git a/hw/arm/stm32f100_soc.c b/hw/arm/stm32f100_soc.c new file mode 100644 index 00000000000..0c4a5c66451 --- /dev/null +++ b/hw/arm/stm32f100_soc.c @@ -0,0 +1,182 @@ +/* + * STM32F100 SoC + * + * Copyright (c) 2021 Alexandre Iooss + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/module.h" +#include "hw/arm/boot.h" +#include "exec/address-spaces.h" +#include "hw/arm/stm32f100_soc.h" +#include "hw/qdev-properties.h" +#include "hw/misc/unimp.h" +#include "sysemu/sysemu.h" + +/* stm32f100_soc implementation is derived from stm32f205_soc */ + +static const uint32_t usart_addr[STM_NUM_USARTS] =3D { 0x40013800, 0x40004= 400, + 0x40004800 }; +static const uint32_t spi_addr[STM_NUM_SPIS] =3D { 0x40013000, 0x40003800 = }; + +static const int usart_irq[STM_NUM_USARTS] =3D {37, 38, 39}; +static const int spi_irq[STM_NUM_SPIS] =3D {35, 36}; + +static void stm32f100_soc_initfn(Object *obj) +{ + STM32F100State *s =3D STM32F100_SOC(obj); + int i; + + object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M); + + for (i =3D 0; i < STM_NUM_USARTS; i++) { + object_initialize_child(obj, "usart[*]", &s->usart[i], + TYPE_STM32F2XX_USART); + } + + for (i =3D 0; i < STM_NUM_SPIS; i++) { + object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_= SPI); + } +} + +static void stm32f100_soc_realize(DeviceState *dev_soc, Error **errp) +{ + STM32F100State *s =3D STM32F100_SOC(dev_soc); + DeviceState *dev, *armv7m; + SysBusDevice *busdev; + int i; + + MemoryRegion *system_memory =3D get_system_memory(); + MemoryRegion *sram =3D g_new(MemoryRegion, 1); + MemoryRegion *flash =3D g_new(MemoryRegion, 1); + MemoryRegion *flash_alias =3D g_new(MemoryRegion, 1); + + /* + * Init flash region + * Flash starts at 0x08000000 and then is aliased to boot memory at 0x0 + */ + memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F100.flash", + FLASH_SIZE, &error_fatal); + memory_region_init_alias(flash_alias, OBJECT(dev_soc), + "STM32F100.flash.alias", flash, 0, FLASH_SIZE= ); + memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); + memory_region_add_subregion(system_memory, 0, flash_alias); + + /* Init SRAM region */ + memory_region_init_ram(sram, NULL, "STM32F100.sram", SRAM_SIZE, + &error_fatal); + memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); + + /* Init ARMv7m */ + armv7m =3D DEVICE(&s->armv7m); + qdev_prop_set_uint32(armv7m, "num-irq", 61); + qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_bit(armv7m, "enable-bitband", true); + object_property_set_link(OBJECT(&s->armv7m), "memory", + OBJECT(get_system_memory()), &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) { + return; + } + + /* Attach UART (uses USART registers) and USART controllers */ + for (i =3D 0; i < STM_NUM_USARTS; i++) { + dev =3D DEVICE(&(s->usart[i])); + qdev_prop_set_chr(dev, "chardev", serial_hd(i)); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) { + return; + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, usart_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i= ])); + } + + /* SPI 1 and 2 */ + for (i =3D 0; i < STM_NUM_SPIS; i++) { + dev =3D DEVICE(&(s->spi[i])); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { + return; + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, spi_addr[i]); + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])= ); + } + + create_unimplemented_device("timer[2]", 0x40000000, 0x400); + create_unimplemented_device("timer[3]", 0x40000400, 0x400); + create_unimplemented_device("timer[4]", 0x40000800, 0x400); + create_unimplemented_device("timer[6]", 0x40001000, 0x400); + create_unimplemented_device("timer[7]", 0x40001400, 0x400); + create_unimplemented_device("RTC", 0x40002800, 0x400); + create_unimplemented_device("WWDG", 0x40002C00, 0x400); + create_unimplemented_device("IWDG", 0x40003000, 0x400); + create_unimplemented_device("I2C1", 0x40005400, 0x400); + create_unimplemented_device("I2C2", 0x40005800, 0x400); + create_unimplemented_device("BKP", 0x40006C00, 0x400); + create_unimplemented_device("PWR", 0x40007000, 0x400); + create_unimplemented_device("DAC", 0x40007400, 0x400); + create_unimplemented_device("CEC", 0x40007800, 0x400); + create_unimplemented_device("AFIO", 0x40010000, 0x400); + create_unimplemented_device("EXTI", 0x40010400, 0x400); + create_unimplemented_device("GPIOA", 0x40010800, 0x400); + create_unimplemented_device("GPIOB", 0x40010C00, 0x400); + create_unimplemented_device("GPIOC", 0x40011000, 0x400); + create_unimplemented_device("GPIOD", 0x40011400, 0x400); + create_unimplemented_device("GPIOE", 0x40011800, 0x400); + create_unimplemented_device("ADC1", 0x40012400, 0x400); + create_unimplemented_device("timer[1]", 0x40012C00, 0x400); + create_unimplemented_device("timer[15]", 0x40014000, 0x400); + create_unimplemented_device("timer[16]", 0x40014400, 0x400); + create_unimplemented_device("timer[17]", 0x40014800, 0x400); + create_unimplemented_device("DMA", 0x40020000, 0x400); + create_unimplemented_device("RCC", 0x40021000, 0x400); + create_unimplemented_device("Flash Int", 0x40022000, 0x400); + create_unimplemented_device("CRC", 0x40023000, 0x400); +} + +static Property stm32f100_soc_properties[] =3D { + DEFINE_PROP_STRING("cpu-type", STM32F100State, cpu_type), + DEFINE_PROP_END_OF_LIST(), +}; + +static void stm32f100_soc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D stm32f100_soc_realize; + device_class_set_props(dc, stm32f100_soc_properties); +} + +static const TypeInfo stm32f100_soc_info =3D { + .name =3D TYPE_STM32F100_SOC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(STM32F100State), + .instance_init =3D stm32f100_soc_initfn, + .class_init =3D stm32f100_soc_class_init, +}; + +static void stm32f100_soc_types(void) +{ + type_register_static(&stm32f100_soc_info); +} + +type_init(stm32f100_soc_types) diff --git a/MAINTAINERS b/MAINTAINERS index 809830c6551..8cfed2dd2d7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -948,6 +948,12 @@ L: qemu-arm@nongnu.org S: Maintained F: hw/arm/virt-acpi-build.c =20 +STM32F100 +M: Alexandre Iooss +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/stm32f100_soc.c + STM32F205 M: Alistair Francis M: Peter Maydell diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 647b5c8b43a..a5c2e1d9912 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -326,6 +326,12 @@ config RASPI select SDHCI select USB_DWC2 =20 +config STM32F100_SOC + bool + select ARM_V7M + select STM32F2XX_USART + select STM32F2XX_SPI + config STM32F205_SOC bool select ARM_V7M diff --git a/hw/arm/meson.build b/hw/arm/meson.build index be39117b9b6..0e637e6a9ee 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -39,6 +39,7 @@ arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('stro= ngarm.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c',= 'cubieboard.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', '= orangepi.c')) arm_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c', '= bcm2836.c', 'raspi.c')) +arm_ss.add(when: 'CONFIG_STM32F100_SOC', if_true: files('stm32f100_soc.c')) arm_ss.add(when: 'CONFIG_STM32F205_SOC', if_true: files('stm32f205_soc.c')) arm_ss.add(when: 'CONFIG_STM32F405_SOC', if_true: files('stm32f405_soc.c')) arm_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp.c',= 'xlnx-zcu102.c')) --=20 2.20.1 From nobody Thu Dec 18 22:18:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x19sm5232277wmi.10.2021.07.09.09.10.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 09:10:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Ygi3D826J101WsOE6G4t2D8GAHPSSbKcuMLxJm7wYDM=; b=bcDFMSysOerKYckz0QhkdTHhlkuUvDwpx/ym4xLL2qk+xc1E2kTWRzU2wXFSky88/F N1D7WOVyvUK8/JI/HG3YRo3+1g3lTockx8+syV7sUbwsm5oXl5h7yZQuAJfWNjSaYFcu kpOgx7I9nL12f+9GBr9WltCRnbVctSW+EwgFuju8p8RARZzCWeVrjRlpiXB0a0pRq82L xkE5NTbtx4UJtipo9daiKkLLoOx/JagfGIZm0GGw0yzyw/qhDljWHBivS6PHYfE5eION kHlOnmFXPfPGiPicCIN6aHfH42Tr54jBHBUCWm4NElD5SQtOOe3vjQWFQtPS0O5yKzzy XYDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ygi3D826J101WsOE6G4t2D8GAHPSSbKcuMLxJm7wYDM=; b=D9WxhjNk3mDB4tY+EKHTRBeQzjuKcNUePpVLCYeAeqSnfsb/62Ce/B6jQWfJT46PDO DFX0cf2YADKVl84KcXCXthyxd0QfruyIAn+wluJWMHWC6LiZ5HNNJYTMuIBKkBGglKc1 BCtIunLd5vcs3SnkVoeh7h9wtS9ttGYCWo8FeQibz5QzC4fz8/koyZSp+YCn+5Y9qdFE kDcje1aDJ/B3dkELGJYV4ZiK6RAbcim0NpOnNfJV5oKgVBEHJaQ8GoueyBTt98WtItlc 7TevwIuNY2WV5WRbp+3sveffq0maIBt3LW8IVJihA93PuaD7vACI8J80Lsmf9be5Njah jUQg== X-Gm-Message-State: AOAM532xQyRRLlzFi063h540Gb6U76ns349xNSP4wnUvd9sT10BaL4Im nQmD2wwdC7QICnqQPml/q28yRJKV/oWrocRU X-Google-Smtp-Source: ABdhPJyth3FeACeW1Ii+4VYEMGe4XwBwCLHuF9N+brOs581FwZSMOSSXhJ3601R1dQY355mSjCQLrg== X-Received: by 2002:adf:fd4d:: with SMTP id h13mr37082544wrs.5.1625847006634; Fri, 09 Jul 2021 09:10:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/17] stm32vldiscovery: Add the STM32VLDISCOVERY Machine Date: Fri, 9 Jul 2021 17:09:48 +0100 Message-Id: <20210709161003.25874-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210709161003.25874-1-peter.maydell@linaro.org> References: <20210709161003.25874-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625847140325100003 Content-Type: text/plain; charset="utf-8" From: Alexandre Iooss This is a Cortex-M3 based machine. Information can be found at: https://www.st.com/en/evaluation-tools/stm32vldiscovery.html Signed-off-by: Alexandre Iooss Reviewed-by: Alistair Francis Message-id: 20210617165647.2575955-3-erdnaxe@crans.org Signed-off-by: Peter Maydell --- default-configs/devices/arm-softmmu.mak | 1 + hw/arm/stm32vldiscovery.c | 66 +++++++++++++++++++++++++ MAINTAINERS | 6 +++ hw/arm/Kconfig | 4 ++ hw/arm/meson.build | 1 + 5 files changed, 78 insertions(+) create mode 100644 hw/arm/stm32vldiscovery.c diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devi= ces/arm-softmmu.mak index 0500156a0c7..cdc0e97f9d7 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -18,6 +18,7 @@ CONFIG_CHEETAH=3Dy CONFIG_SX1=3Dy CONFIG_NSERIES=3Dy CONFIG_STELLARIS=3Dy +CONFIG_STM32VLDISCOVERY=3Dy CONFIG_REALVIEW=3Dy CONFIG_VERSATILE=3Dy CONFIG_VEXPRESS=3Dy diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c new file mode 100644 index 00000000000..7e8191ebf5f --- /dev/null +++ b/hw/arm/stm32vldiscovery.c @@ -0,0 +1,66 @@ +/* + * ST STM32VLDISCOVERY machine + * + * Copyright (c) 2021 Alexandre Iooss + * Copyright (c) 2014 Alistair Francis + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/qdev-properties.h" +#include "qemu/error-report.h" +#include "hw/arm/stm32f100_soc.h" +#include "hw/arm/boot.h" + +/* stm32vldiscovery implementation is derived from netduinoplus2 */ + +/* Main SYSCLK frequency in Hz (24MHz) */ +#define SYSCLK_FRQ 24000000ULL + +static void stm32vldiscovery_init(MachineState *machine) +{ + DeviceState *dev; + + /* + * TODO: ideally we would model the SoC RCC and let it handle + * system_clock_scale, including its ability to define different + * possible SYSCLK sources. + */ + system_clock_scale =3D NANOSECONDS_PER_SECOND / SYSCLK_FRQ; + + dev =3D qdev_new(TYPE_STM32F100_SOC); + qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + armv7m_load_kernel(ARM_CPU(first_cpu), + machine->kernel_filename, + FLASH_SIZE); +} + +static void stm32vldiscovery_machine_init(MachineClass *mc) +{ + mc->desc =3D "ST STM32VLDISCOVERY (Cortex-M3)"; + mc->init =3D stm32vldiscovery_init; +} + +DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init) + diff --git a/MAINTAINERS b/MAINTAINERS index 8cfed2dd2d7..f5919498af4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -893,6 +893,12 @@ F: hw/*/stellaris* F: include/hw/input/gamepad.h F: docs/system/arm/stellaris.rst =20 +STM32VLDISCOVERY +M: Alexandre Iooss +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/stm32vldiscovery.c + Versatile Express M: Peter Maydell L: qemu-arm@nongnu.org diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index a5c2e1d9912..c5211896284 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -239,6 +239,10 @@ config STELLARIS select STELLARIS_ENET # ethernet select UNIMP =20 +config STM32VLDISCOVERY + bool + select STM32F100_SOC + config STRONGARM bool select PXA2XX diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 0e637e6a9ee..721a8eb8bed 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -24,6 +24,7 @@ arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c')) arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c')) arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c')) arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c')) +arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscove= ry.c')) arm_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c')) arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c')) arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c')) --=20 2.20.1 From nobody Thu Dec 18 22:18:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x19sm5232277wmi.10.2021.07.09.09.10.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 09:10:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=dHPWbK5KgEsozA6CwOuy0L1hAHPICBDNahq3VbvQpN8=; b=T/vWH5iK5VSDQ/EvLN1KzB1zRhCvsYSiTlYt9B9D1cUZzzmOXsa9pMILdJ5nHWjSTI 5MSBZ9TV7VfcTuwIij8q8tJmbv0TAzFeTOJPJ3Km2pjfUZvCQTU7CLJQ1L6jU/Eh6C0N W5gB8nSwh0rmS7tuC0A1qfG53WqdnoQraI/gj71VkecsE9tkK9ykj4tAZHV3Kos11pCf 4GXmeZkd8v6Gsb08k9ifQxEuy3g6gQxr/ZXbbWNfe8keXQdVeW5jw3jp3SkrTwBwkGLk Z1PKzEcfTYSfvDyLyksFV3fDR76CkkizGKOgn1B1sFeHdK7+SSyU+e3hRn0QOptj5iSJ soVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dHPWbK5KgEsozA6CwOuy0L1hAHPICBDNahq3VbvQpN8=; b=gUw8ebscQtDowd/tEelGyRrvJqjOLh8flk01wad94gWkQC//UkUU0DC7m9fMBchukk N1yyQTvheiJHsqdM+5McpXKV7LVSG4b+a+HGubsoiREz/Yeu1YK/+O04DIqokLzoYy2B fCGQvPmpm7efMzPN6mFsbR8dZ8+R1wmdaFUkCjjKfBmpv5755JEPUriQTiBFQprKuSnb wvr2wVrh4T28u2dVKnhZBmqBqgIRcGe3i8hmG7qULI9uZTDRl2mfE7Ht++h1VvEC7lcY hbzFBNPnduTux7OrhkYOZ0hqEgUuvVOi1HJ3FrDJc0O4VZDZRdBye+h7i3By3zTRM+x3 okdA== X-Gm-Message-State: AOAM530KK7+UA6IYhLR871HC9TDUroS2Nqp30qzdUa6XwiTXoS2Ae28u a6EOA+JSV91H51LsPMM0BkcEKdEaD52cNQn3 X-Google-Smtp-Source: ABdhPJwp/zplchst3Koj5KvdjmMu7CrYNzJRUu0YXWc7kCKlDUeo9aCjdxHQFCDV3J5QY/4fYfbQsg== X-Received: by 2002:adf:f885:: with SMTP id u5mr1664506wrp.84.1625847007298; Fri, 09 Jul 2021 09:10:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/17] docs/system: arm: Add stm32 boards description Date: Fri, 9 Jul 2021 17:09:49 +0100 Message-Id: <20210709161003.25874-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210709161003.25874-1-peter.maydell@linaro.org> References: <20210709161003.25874-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625847274293100001 Content-Type: text/plain; charset="utf-8" From: Alexandre Iooss This adds the target guide for Netduino 2, Netduino Plus 2 and STM32VLDISCO= VERY. Signed-off-by: Alexandre Iooss Reviewed-by: Alistair Francis Message-id: 20210617165647.2575955-4-erdnaxe@crans.org Signed-off-by: Peter Maydell --- docs/system/arm/stm32.rst | 66 ++++++++++++++++++++++++++++++++++++++ docs/system/target-arm.rst | 1 + MAINTAINERS | 1 + 3 files changed, 68 insertions(+) create mode 100644 docs/system/arm/stm32.rst diff --git a/docs/system/arm/stm32.rst b/docs/system/arm/stm32.rst new file mode 100644 index 00000000000..508b92cf862 --- /dev/null +++ b/docs/system/arm/stm32.rst @@ -0,0 +1,66 @@ +STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``stm32= vldiscovery``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by +STMicroelectronics. + +.. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32= -bit-arm-cortex-mcus.html + +The STM32F1 series is based on ARM Cortex-M3 core. The following machines = are +based on this chip : + +- ``stm32vldiscovery`` STM32VLDISCOVERY board with STM32F100RBT6 microcon= troller + +The STM32F2 series is based on ARM Cortex-M3 core. The following machines = are +based on this chip : + +- ``netduino2`` Netduino 2 board with STM32F205RFT6 microcontroller + +The STM32F4 series is based on ARM Cortex-M4F core. This series is pin-to-= pin +compatible with STM32F2 series. The following machines are based on this c= hip : + +- ``netduinoplus2`` Netduino Plus 2 board with STM32F405RGT6 microcont= roller + +There are many other STM32 series that are currently not supported by QEMU. + +Supported devices +----------------- + + * ARM Cortex-M3, Cortex M4F + * Analog to Digital Converter (ADC) + * EXTI interrupt + * Serial ports (USART) + * SPI controller + * System configuration (SYSCFG) + * Timer controller (TIMER) + +Missing devices +--------------- + + * Camera interface (DCMI) + * Controller Area Network (CAN) + * Cycle Redundancy Check (CRC) calculation unit + * Digital to Analog Converter (DAC) + * DMA controller + * Ethernet controller + * Flash Interface Unit + * GPIO controller + * I2C controller + * Inter-Integrated Sound (I2S) controller + * Power supply configuration (PWR) + * Random Number Generator (RNG) + * Real-Time Clock (RTC) controller + * Reset and Clock Controller (RCC) + * Secure Digital Input/Output (SDIO) interface + * USB OTG + * Watchdog controller (IWDG, WWDG) + +Boot options +------------ + +The STM32 machines can be started using the ``-kernel`` option to load a +firmware. Example: + +.. code-block:: bash + + $ qemu-system-arm -M stm32vldiscovery -kernel firmware.bin diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index 13b3eeaf076..705b8835e48 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -97,6 +97,7 @@ undocumented; you can get a complete list by running arm/collie arm/sx1 arm/stellaris + arm/stm32 arm/virt arm/xlnx-versal-virt =20 diff --git a/MAINTAINERS b/MAINTAINERS index f5919498af4..bad893bfd90 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -898,6 +898,7 @@ M: Alexandre Iooss L: qemu-arm@nongnu.org S: Maintained F: hw/arm/stm32vldiscovery.c +F: docs/system/arm/stm32.rst =20 Versatile Express M: Peter Maydell --=20 2.20.1 From nobody Thu Dec 18 22:18:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625847560; cv=none; d=zohomail.com; s=zohoarc; b=B9uDhMX0jRveIat3cqnNWNB3++Ud+Jpe2yNrGZz3JDukS08w7J8JRfrT6ZMjQOAwaw/802JbPNhyTnRMByG8QACovUjkjtcN2l9fv3HJad5AGRZCtcK6wSPKSj5a5KkoR3oL8lWkw2zIytMHRlFNsUc7Vdn02QPBNgNRjbHYlUI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625847560; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=juTft1gatBMC6rpbTOnW3It8WuOd1TRakdFeysyyfkg=; b=RvSquEOubM2kuiwqASuiQgOgH3pKzPbFS2K0dwZDxu5KfI3OZZuAreuNFqUNCG8ewhTmtJqT8jDvf4521elHCSKvXCJVA8f/sRu2HYCzLx54iQthdeMkSTMIpp2o7hM362jzT1ce6KgmYhDboO0dVnPvE9zW+0xjAimyNl9ndq4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1625847560604184.65192395377403; Fri, 9 Jul 2021 09:19:20 -0700 (PDT) Received: from localhost ([::1]:49968 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1tDj-00028u-Hv for importer@patchew.org; Fri, 09 Jul 2021 12:19:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37568) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1t52-0001Tx-5L for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:20 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:35486) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m1t4r-0000tO-Mu for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:19 -0400 Received: by mail-wm1-x336.google.com with SMTP id k31-20020a05600c1c9fb029021727d66d33so5114781wms.0 for ; Fri, 09 Jul 2021 09:10:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x19sm5232277wmi.10.2021.07.09.09.10.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 09:10:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=juTft1gatBMC6rpbTOnW3It8WuOd1TRakdFeysyyfkg=; b=VCBIJ24VStgi7VFRfkPY65w+U/nbk48wX0j4Jt77akBSDR2FYelCi3dZmT9HB2ligE amRElLKIXzW+Yp0TH86KGFIkN1wYdah2kWF41Zw+G/J8OK8FUValyRkY72H3SOuAyok4 VPMv9HV3EAT1w24v1DSYTY/sTFazrsOGZw1YIEGyGoo9q9CX/9LyYpmn0HcuKmPscLh4 J+wWfSSV8KqcBEREQi/EQMVX3ciElYMClb8erwsXYtsVUuufy5VbD1ik2mhuj9JBwulf 4S8UcFaE7f/LfgB6g87quOGcB0olSSynCpMtnrMSU8Sb3wPCt1XJk7oVMX60ZYbMz3aK t4XQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=juTft1gatBMC6rpbTOnW3It8WuOd1TRakdFeysyyfkg=; b=FTvE3fEKUNUrKTfX8BnUBo5vbM2HdxVzDt98lr/tugeu9t1S7fxV/+eCu56BSuIaVm HlThQRSQSYfOrEvyluOh5RlDsSRak798CJr/wAasf0mmJTbJhqWn3cMLXUcYoXqpa4a9 pdtIaPm2OwMaJgwDFjgLNAvMObeZf+eLC82KrE35pBoTPMEvC6bO1NarPiQgQT4XM4dQ VJV6pFVTRIoa1KhFSlnnyUHRKJ3/nWLQEEAwoSazC4hkgJUKf9O9v0W0qbUy8t1lsZGc 0BuGfyuM6C7wTJlXYZE9a0TL7jjup5IxpqA3U3qXs0DXgWLWnbcpkC2Foodvxo2DCcZF yG0g== X-Gm-Message-State: AOAM532AUrhHKnfKzBjCZDWMCsapSEnbjHvchbd0LDWq6tIzZgQpB0Ki tWr+qM3CeHHqLpnUIwiSAmVK7/qsE3JPuzya X-Google-Smtp-Source: ABdhPJwgikykNBi+AVf3LxWklXRXlcgwNctVynhe68lCwXpqwm+5GUn5jAWjmK2CFbabq3rPhjLvUw== X-Received: by 2002:a7b:c74a:: with SMTP id w10mr12650146wmk.54.1625847008197; Fri, 09 Jul 2021 09:10:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/17] tests/boot-serial-test: Add STM32VLDISCOVERY board testcase Date: Fri, 9 Jul 2021 17:09:50 +0100 Message-Id: <20210709161003.25874-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210709161003.25874-1-peter.maydell@linaro.org> References: <20210709161003.25874-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625847560883100001 Content-Type: text/plain; charset="utf-8" From: Alexandre Iooss New mini-kernel test for STM32VLDISCOVERY USART1. Signed-off-by: Alexandre Iooss Acked-by: Thomas Huth Acked-by: Alistair Francis Message-id: 20210617165647.2575955-5-erdnaxe@crans.org Signed-off-by: Peter Maydell --- tests/qtest/boot-serial-test.c | 37 ++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/tests/qtest/boot-serial-test.c b/tests/qtest/boot-serial-test.c index d40adddafa3..96849cec915 100644 --- a/tests/qtest/boot-serial-test.c +++ b/tests/qtest/boot-serial-test.c @@ -94,6 +94,41 @@ static const uint8_t kernel_nrf51[] =3D { 0x1c, 0x25, 0x00, 0x40 /* 0x4000251c =3D UART TXD */ }; =20 +static const uint8_t kernel_stm32vldiscovery[] =3D { + 0x00, 0x00, 0x00, 0x00, /* Stack top address */ + 0x1d, 0x00, 0x00, 0x00, /* Reset handler address */ + 0x00, 0x00, 0x00, 0x00, /* NMI */ + 0x00, 0x00, 0x00, 0x00, /* Hard fault */ + 0x00, 0x00, 0x00, 0x00, /* Memory management fault */ + 0x00, 0x00, 0x00, 0x00, /* Bus fault */ + 0x00, 0x00, 0x00, 0x00, /* Usage fault */ + 0x0b, 0x4b, /* ldr r3, [pc, #44] Get RCC = */ + 0x44, 0xf2, 0x04, 0x02, /* movw r2, #16388 */ + 0x1a, 0x60, /* str r2, [r3] */ + 0x0a, 0x4b, /* ldr r3, [pc, #40] Get GPIO= A */ + 0x1a, 0x68, /* ldr r2, [r3] */ + 0x22, 0xf0, 0xf0, 0x02, /* bic r2, r2, #240 */ + 0x1a, 0x60, /* str r2, [r3] */ + 0x1a, 0x68, /* ldr r2, [r3] */ + 0x42, 0xf0, 0xb0, 0x02, /* orr r2, r2, #176 */ + 0x1a, 0x60, /* str r2, [r3] */ + 0x07, 0x4b, /* ldr r3, [pc, #26] Get BAUD= */ + 0x45, 0x22, /* movs r2, #69 */ + 0x1a, 0x60, /* str r2, [r3] */ + 0x06, 0x4b, /* ldr r3, [pc, #24] Get ENAB= LE */ + 0x42, 0xf2, 0x08, 0x02, /* movw r2, #8200 */ + 0x1a, 0x60, /* str r2, [r3] */ + 0x05, 0x4b, /* ldr r3, [pc, #20] Get TXD = */ + 0x54, 0x22, /* movs r2, 'T' */ + 0x1a, 0x60, /* str r2, [r3] */ + 0xfe, 0xe7, /* b . */ + 0x18, 0x10, 0x02, 0x40, /* 0x40021018 =3D RCC */ + 0x04, 0x08, 0x01, 0x40, /* 0x40010804 =3D GPIOA */ + 0x08, 0x38, 0x01, 0x40, /* 0x40013808 =3D USART1 BAUD = */ + 0x0c, 0x38, 0x01, 0x40, /* 0x4001380c =3D USART1 ENABL= E */ + 0x04, 0x38, 0x01, 0x40 /* 0x40013804 =3D USART1 TXD */ +}; + typedef struct testdef { const char *arch; /* Target architecture */ const char *machine; /* Name of the machine */ @@ -144,6 +179,8 @@ static testdef_t tests[] =3D { { "aarch64", "virt", "-cpu max", "TT", sizeof(kernel_aarch64), kernel_aarch64 }, { "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 }, + { "arm", "stm32vldiscovery", "", "T", + sizeof(kernel_stm32vldiscovery), kernel_stm32vldiscovery }, =20 { NULL } }; --=20 2.20.1 From nobody Thu Dec 18 22:18:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625847656; cv=none; d=zohomail.com; s=zohoarc; b=NB3oW8ct+K2njfAjK5v2hBjniZwtT6EDSGa2DOuDXohQL3bLa3MkEkXPpvzoqUBVjgqQ3qznlSZM6pR1IIzDA2tYrx1w/cbklgTPcsRr9UHpX7GQgSE+kV0xu6eMVGE+Jg3+lP6bzFcOF99/9rt6/y09X3Fr4xh5E0pNk96sUXM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625847656; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dKDIzuvtaX8JxLTVV3qVEDghKCjpF+iPJawU1M1UYxo=; b=lUulOj42dV+ExYDNbSLPRa+SCdYKmncCF2K3xSKmX1NfPHe3zY7xQpZ3rb9utWWgPG5QciMF2TDiYPCaqNYABb9CCnDYNaIZho6YwnSSKBQE8W05a2YCqLWHVa5fXDdJMSXbX/bCgeA7BlhkRYv95Q7PlyxHMGTLhmtisaWOTdM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1625847656479185.33802613693604; Fri, 9 Jul 2021 09:20:56 -0700 (PDT) Received: from localhost ([::1]:55806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1tFH-0006I8-Bs for importer@patchew.org; Fri, 09 Jul 2021 12:20:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37468) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1t4u-0001PP-UA for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:12 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:35747) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m1t4s-0000tY-3b for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:12 -0400 Received: by mail-wr1-x436.google.com with SMTP id m2so1815693wrq.2 for ; Fri, 09 Jul 2021 09:10:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x19sm5232277wmi.10.2021.07.09.09.10.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 09:10:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=dKDIzuvtaX8JxLTVV3qVEDghKCjpF+iPJawU1M1UYxo=; b=POPCJin69Q/KQhpXM5N7RR4u3HnyxsFcUDZHKBE4e5qM0u/f6V3ex3DQ2fW89ao4Us a+zrpuR3kD4xkBa7ej6zmcHertJknzV2T3sQPGepM4UXaX9yApuSp3FZ6vDJjlkJsQiD ZvBV9T7dJVtSqROQTOwPld6Q9+ogUGKbVChVTKf/EQvAyJdZ6QKSz8Z1oFD3ZYTSBB5V 8e6Tuou6Uhif3jP7XudT82+1EBLlKauDUdHOjGltkJEVMw6//SKllnJCf4YvfNQvKfc/ 25tvRhpFy0vdvjU8S6aGuBvmm9CL3D3pe/LqMY+yL06VDHkhoTaPpWV4wKP5VSVNDr0K HONA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dKDIzuvtaX8JxLTVV3qVEDghKCjpF+iPJawU1M1UYxo=; b=BXmp2iIs6WfnGQWM9vSqU38pWAKee55g6SCVDr2yQGOW34EEE2r8pxhz3gg+sKCR6D Nhnt7g990QEVPLzwbYJp++YQk6sMtvZKUrZrtyI5mYNVEZpE6Vnlo1rXwXspT3k0oPE1 lO+vSINgzUe2EyMVqgAOLjD8cS+qBaxXOqoZX4JOolh+4cKADh14no66ctNs8X3BkCSt dEa3raR1RpQ4qeFLsctvwLg6W0SXOmq9/MxrKoEWl9iA3Fr46f75o/QCzkTKIfd0/H3V IL0KbdebD9f6ui29pjtuRfhVRNylgMSu2dbFZVmITJ+cgR3D1fobaSnnaiOLWSp6FqBQ qjyA== X-Gm-Message-State: AOAM533T5QbRK+cHZyTutSq7u3MeDmzC4+t5EmhEBt3Ut30n5bhgEhg9 AOrF/m+Q325g3KTUavLozuuMxqEye7rmAiL5 X-Google-Smtp-Source: ABdhPJxik5TPdY27kaEp2qvnM/UzgNRT6OA5MZ7wBP4ufrf2T8VUj246GTHAlfP8jKsWx900kRzGRA== X-Received: by 2002:a5d:6281:: with SMTP id k1mr4393849wru.369.1625847008799; Fri, 09 Jul 2021 09:10:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/17] hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir|eoir]_write Date: Fri, 9 Jul 2021 17:09:51 +0100 Message-Id: <20210709161003.25874-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210709161003.25874-1-peter.maydell@linaro.org> References: <20210709161003.25874-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625847658222100001 Content-Type: text/plain; charset="utf-8" From: Ricardo Koller icv_eoir_write() and icv_dir_write() ignore invalid virtual IRQ numbers (like LPIs). The issue is that these functions check against the number of implemented IRQs (QEMU's default is num_irq=3D288) which can be lower than the maximum virtual IRQ number (1020 - 1). The consequence is that if a hypervisor creates an LR for an IRQ between 288 and 1020, then the guest is unable to deactivate the resulting IRQ. Note that other functions that deal with large IRQ numbers, like icv_iar_read, check against 1020 and not against num_irq. Fix the checks by using GICV3_MAXIRQ (1020) instead of the number of implemented IRQs. Signed-off-by: Ricardo Koller Message-id: 20210702233701.3369-1-ricarkol@google.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 3e0641aff97..a032d505f53 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -1227,7 +1227,7 @@ static void icv_dir_write(CPUARMState *env, const ARM= CPRegInfo *ri, =20 trace_gicv3_icv_dir_write(gicv3_redist_affid(cs), value); =20 - if (irq >=3D cs->gic->num_irq) { + if (irq >=3D GICV3_MAXIRQ) { /* Also catches special interrupt numbers and LPIs */ return; } @@ -1262,7 +1262,7 @@ static void icv_eoir_write(CPUARMState *env, const AR= MCPRegInfo *ri, trace_gicv3_icv_eoir_write(ri->crm =3D=3D 8 ? 0 : 1, gicv3_redist_affid(cs), value); =20 - if (irq >=3D cs->gic->num_irq) { + if (irq >=3D GICV3_MAXIRQ) { /* Also catches special interrupt numbers and LPIs */ return; } --=20 2.20.1 From nobody Thu Dec 18 22:18:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625847819; cv=none; d=zohomail.com; s=zohoarc; b=AvIuaMZY5txXrN1s7/G1ZwwCaUcCTNrfcnVr0ugBSEyqc/hyJOHJd1O7NXecw+TDL6LEs9p5wHZDNiRD3CJkALzHcjs3BRGIqFh4AovTo41RpkAfiHcdgkSNltqzSkoXZYgZs4/Wtcu8uA+D93Yfy6QwejIPM1xmM7zrmwz/vMI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625847819; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0+XntP6qWzF22D6wPU4jk81ujCejMaHle/+oEGxM0lA=; b=fDi1Y+6wr/zUxzkjODzdJtBW4Ne+0iVj3+vh4uezmxNy6knaE14K9wkJPSlivlmKeieSUQpG5DdKymkc0cYRQPpowDSrbNzZVp8vIJb0ISG4QUeaSGCNBz/03h3k2odbYgFmd7jTfI0org88tbGPJJBMf2yXLb2Ds8vBDr8p3I0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1625847819143383.22732735251293; Fri, 9 Jul 2021 09:23:39 -0700 (PDT) Received: from localhost ([::1]:36244 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1tHu-0004QS-2D for importer@patchew.org; Fri, 09 Jul 2021 12:23:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37570) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1t52-0001Ty-6J for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:20 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:46055) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m1t4u-0000uH-DP for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:19 -0400 Received: by mail-wm1-x332.google.com with SMTP id u8-20020a7bcb080000b02901e44e9caa2aso6621260wmj.4 for ; Fri, 09 Jul 2021 09:10:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x19sm5232277wmi.10.2021.07.09.09.10.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 09:10:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0+XntP6qWzF22D6wPU4jk81ujCejMaHle/+oEGxM0lA=; b=nTlD1IXWvDB7o5dHO9loAjAw4pmsx14oUCjlEXTY/5cBz23r+Akclw3QxInBLlJQI3 kNiOWvY97kooik+hOcBoiPMbPcaY4fImZBchZ7px4dsvOHczD+yuwByEbO+FZKTAr/UD NRs6YTesxl4YKLuwfYfdQ9YwnKoXKKJDIfcoep2z8vy0xHAxXW5RvTTRmz27OuKvG6/d vH9Xs8VDtUMuxY5gJb7c+ImbVX0VdV1NfVi+rg13uEuflSgxUnGilwNu3LuJ+Tjlyzhv T/K/wvgvIuKs0AhwLYfF8myoKDXKurYWqRnnVuyvP5BPqVsZ1K+QOPpeSpQAZHGkpJpg Ffcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0+XntP6qWzF22D6wPU4jk81ujCejMaHle/+oEGxM0lA=; b=dH5zbUyRbqGMUwQh4+TBUbFalI45Ig8ZxuAskBwpZWs9ywV0d5vjv+2I5D5oxZYewo qZToRrFgaP4XnPVEoGW1WaZZY3B9PvqCCAQ3d7w2kkPx3NYd5I4DmY/ZOBfWn5qXwMNy UQtQOAWkbkaWM9rZK+VQXM5mlFLWlyGA7Q3DcoG0U6XVfPZ9LLeo+aHWFVAdcyX4gVFP ZKeMQDM2A/S/2DfDeuEoDv77QcZNeZzsvh05j7fdfu7VUDO7oQW6kHVKoK6dfV53kH+3 LJyYX6yU31zsxaMqSOrElDyLs5v9L9dq5En5pHNNvZrGJCR+tIr/sHxGNNoRKtv0QiPd a8Sw== X-Gm-Message-State: AOAM531mqfyVZ84wGXzZKM9+SfpFAIJ5nwyxkl2rbWlE/UOkBYIxYgQS ary/tePjLTn3tq+UvXUtLSeW7dsPe28T+6Id X-Google-Smtp-Source: ABdhPJwgoP4YP2smT2gyA0BJKAm25tflrlZCwkVT2827yGfW5gstlm+dRoLWH6F4SZoRRCFv4VyRWw== X-Received: by 2002:a7b:c351:: with SMTP id l17mr40709090wmj.120.1625847009576; Fri, 09 Jul 2021 09:10:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/17] hw/gpio/pl061: Convert DPRINTF to tracepoints Date: Fri, 9 Jul 2021 17:09:52 +0100 Message-Id: <20210709161003.25874-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210709161003.25874-1-peter.maydell@linaro.org> References: <20210709161003.25874-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625847819830100001 Convert the use of the DPRINTF debug macro in the PL061 model to use tracepoints. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/gpio/pl061.c | 27 +++++++++------------------ hw/gpio/trace-events | 6 ++++++ 2 files changed, 15 insertions(+), 18 deletions(-) diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index e72e77572a0..a6ace88895d 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -15,19 +15,7 @@ #include "qemu/log.h" #include "qemu/module.h" #include "qom/object.h" - -//#define DEBUG_PL061 1 - -#ifdef DEBUG_PL061 -#define DPRINTF(fmt, ...) \ -do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0) -#define BADF(fmt, ...) \ -do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} whi= le (0) -#else -#define DPRINTF(fmt, ...) do {} while(0) -#define BADF(fmt, ...) \ -do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0) -#endif +#include "trace.h" =20 static const uint8_t pl061_id[12] =3D { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1= }; @@ -107,7 +95,7 @@ static void pl061_update(PL061State *s) uint8_t out; int i; =20 - DPRINTF("dir =3D %d, data =3D %d\n", s->dir, s->data); + trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data); =20 /* Outputs float high. */ /* FIXME: This is board dependent. */ @@ -118,8 +106,9 @@ static void pl061_update(PL061State *s) for (i =3D 0; i < N_GPIOS; i++) { mask =3D 1 << i; if (changed & mask) { - DPRINTF("Set output %d =3D %d\n", i, (out & mask) !=3D 0); - qemu_set_irq(s->out[i], (out & mask) !=3D 0); + int level =3D (out & mask) !=3D 0; + trace_pl061_set_output(DEVICE(s)->canonical_path, i, level= ); + qemu_set_irq(s->out[i], level); } } } @@ -131,7 +120,8 @@ static void pl061_update(PL061State *s) for (i =3D 0; i < N_GPIOS; i++) { mask =3D 1 << i; if (changed & mask) { - DPRINTF("Changed input %d =3D %d\n", i, (s->data & mask) != =3D 0); + trace_pl061_input_change(DEVICE(s)->canonical_path, i, + (s->data & mask) !=3D 0); =20 if (!(s->isense & mask)) { /* Edge interrupt */ @@ -150,7 +140,8 @@ static void pl061_update(PL061State *s) /* Level interrupt */ s->istate |=3D ~(s->data ^ s->iev) & s->isense; =20 - DPRINTF("istate =3D %02X\n", s->istate); + trace_pl061_update_istate(DEVICE(s)->canonical_path, + s->istate, s->im, (s->istate & s->im) !=3D 0= ); =20 qemu_set_irq(s->irq, (s->istate & s->im) !=3D 0); } diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index f0b664158e2..48ccbb183cc 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -13,6 +13,12 @@ nrf51_gpio_write(uint64_t offset, uint64_t value) "offse= t 0x%" PRIx64 " value 0x nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRI= i64 nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 = " value %" PRIi64 =20 +# pl061.c +pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x= GPIODATA 0x%x" +pl061_set_output(const char *id, int gpio, int level) "%s setting output %= d to %d" +pl061_input_change(const char *id, int gpio, int level) "%s input %d chang= ed to %d" +pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int leve= l) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d" + # sifive_gpio.c sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value = 0x%" PRIx64 sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " v= alue 0x%" PRIx64 --=20 2.20.1 From nobody Thu Dec 18 22:18:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x19sm5232277wmi.10.2021.07.09.09.10.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 09:10:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DB45w+Xf+giGngvepfeNyHkgFOBsKxRzO/+f+Z0SSXM=; b=eLBu/s//3SGtE7lNcx+3cEJpXDKMYsyNvB7A60tFYzN9ArQBkD666BBdI8Ab9yn1nB fsdTlKWXBBEasbqs+qt4h5mLMtuJZ0XbQVUMVVqI9DZdEJCTQDNihPruG5IQrHGuXo3D nJBFr8cHa3NiTjzr931CqNrFl5NNmKEDrmfTvRJ3/OvBt78e92Ggpp5+CBvuZT5jGrJm Lqa8RV1v92JamGWKTtzxg1nisCAvhwucSFBmR2fHDJCDvZY6Ftjxb2facikmz7MVeQJd ufiQh0k1aBSYsaqvYxVE5Iet6tmrWXj/lYt1kbeq4Re0j5GYG1tt6YWNA0rqhuppyEJe vEng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DB45w+Xf+giGngvepfeNyHkgFOBsKxRzO/+f+Z0SSXM=; b=E/V3GeJSFjWdkh0kKKjxZqXPCLKuPoqqPsZkFvOqazJl3uMSMBvlB/Do3x5NRdq+C0 hLvL716BBkxPdSNDCzjw3MTn9DmQxeAscgKzdYdLA6WZ1sz+6PINQKJPGYtaZQOtfTjg 2M82cz5ggQTkGOPzG/rHteZzgOkTihHGbDDfK1cb7YofBKwX3vCv0J5YCmD+lUAO4cJs Ucz1m80czGSkUSH2UHzawGovspq9/AL6yy8KV/qvqu2Jzb9eVJYYC9fVz+Ig7R4Uk+GP u+ZAUZrSqAKDoimg+tdogwXdaLVd6VLItISrFCKEdssUEsKey0qr1iH8HR8I8VA07sy+ 5vVA== X-Gm-Message-State: AOAM530MtPkqzd5KnEr8xLX3GObsIs+JqpQnG7UO1xj2VSyORLsAGVx2 q7mG4gMwbF9tDjct03eWk03mEE33MarRjLDl X-Google-Smtp-Source: ABdhPJw9Dcxw2JgcGxmIkFePVlELOtI+rM6JTAwr5Mcdy2XH/tf0LG0EwQzb1BDHHqHVjUyaRIaucw== X-Received: by 2002:a5d:47a7:: with SMTP id 7mr11167489wrb.150.1625847010495; Fri, 09 Jul 2021 09:10:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/17] hw/gpio/pl061: Clean up read/write offset handling logic Date: Fri, 9 Jul 2021 17:09:53 +0100 Message-Id: <20210709161003.25874-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210709161003.25874-1-peter.maydell@linaro.org> References: <20210709161003.25874-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625847407603100001 Content-Type: text/plain; charset="utf-8" Currently the pl061_read() and pl061_write() functions handle offsets using a combination of three if() statements and a switch(). Clean this up to use just a switch, using case ranges. This requires that instead of catching accesses to the luminary-only registers on a stock PL061 via a check on s->rsvd_start we use an "is this luminary?" check in the cases for each luminary-only register. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/gpio/pl061.c | 104 ++++++++++++++++++++++++++++++++++++------------ 1 file changed, 79 insertions(+), 25 deletions(-) diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index a6ace88895d..b21b230402f 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -55,7 +55,6 @@ struct PL061State { qemu_irq irq; qemu_irq out[N_GPIOS]; const unsigned char *id; - uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */ }; =20 static const VMStateDescription vmstate_pl061 =3D { @@ -151,16 +150,9 @@ static uint64_t pl061_read(void *opaque, hwaddr offset, { PL061State *s =3D (PL061State *)opaque; =20 - if (offset < 0x400) { - return s->data & (offset >> 2); - } - if (offset >=3D s->rsvd_start && offset <=3D 0xfcc) { - goto err_out; - } - if (offset >=3D 0xfd0 && offset < 0x1000) { - return s->id[(offset - 0xfd0) >> 2]; - } switch (offset) { + case 0x0 ... 0x3ff: /* Data */ + return s->data & (offset >> 2); case 0x400: /* Direction */ return s->dir; case 0x404: /* Interrupt sense */ @@ -178,33 +170,68 @@ static uint64_t pl061_read(void *opaque, hwaddr offse= t, case 0x420: /* Alternate function select */ return s->afsel; case 0x500: /* 2mA drive */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->dr2r; case 0x504: /* 4mA drive */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->dr4r; case 0x508: /* 8mA drive */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->dr8r; case 0x50c: /* Open drain */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->odr; case 0x510: /* Pull-up */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->pur; case 0x514: /* Pull-down */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->pdr; case 0x518: /* Slew rate control */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->slr; case 0x51c: /* Digital enable */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->den; case 0x520: /* Lock */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->locked; case 0x524: /* Commit */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->cr; case 0x528: /* Analog mode select */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->amsel; + case 0xfd0 ... 0xfff: /* ID registers */ + return s->id[(offset - 0xfd0) >> 2]; default: + bad_offset: + qemu_log_mask(LOG_GUEST_ERROR, + "pl061_read: Bad offset %x\n", (int)offset); break; } -err_out: - qemu_log_mask(LOG_GUEST_ERROR, - "pl061_read: Bad offset %x\n", (int)offset); return 0; } =20 @@ -214,16 +241,12 @@ static void pl061_write(void *opaque, hwaddr offset, PL061State *s =3D (PL061State *)opaque; uint8_t mask; =20 - if (offset < 0x400) { + switch (offset) { + case 0 ... 0x3ff: mask =3D (offset >> 2) & s->dir; s->data =3D (s->data & ~mask) | (value & mask); pl061_update(s); return; - } - if (offset >=3D s->rsvd_start) { - goto err_out; - } - switch (offset) { case 0x400: /* Direction */ s->dir =3D value & 0xff; break; @@ -247,47 +270,80 @@ static void pl061_write(void *opaque, hwaddr offset, s->afsel =3D (s->afsel & ~mask) | (value & mask); break; case 0x500: /* 2mA drive */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->dr2r =3D value & 0xff; break; case 0x504: /* 4mA drive */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->dr4r =3D value & 0xff; break; case 0x508: /* 8mA drive */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->dr8r =3D value & 0xff; break; case 0x50c: /* Open drain */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->odr =3D value & 0xff; break; case 0x510: /* Pull-up */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->pur =3D value & 0xff; break; case 0x514: /* Pull-down */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->pdr =3D value & 0xff; break; case 0x518: /* Slew rate control */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->slr =3D value & 0xff; break; case 0x51c: /* Digital enable */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->den =3D value & 0xff; break; case 0x520: /* Lock */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->locked =3D (value !=3D 0xacce551); break; case 0x524: /* Commit */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } if (!s->locked) s->cr =3D value & 0xff; break; case 0x528: + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->amsel =3D value & 0xff; break; default: - goto err_out; + bad_offset: + qemu_log_mask(LOG_GUEST_ERROR, + "pl061_write: Bad offset %x\n", (int)offset); + return; } pl061_update(s); return; -err_out: - qemu_log_mask(LOG_GUEST_ERROR, - "pl061_write: Bad offset %x\n", (int)offset); } =20 static void pl061_reset(DeviceState *dev) @@ -343,7 +399,6 @@ static void pl061_luminary_init(Object *obj) PL061State *s =3D PL061(obj); =20 s->id =3D pl061_id_luminary; - s->rsvd_start =3D 0x52c; } =20 static void pl061_init(Object *obj) @@ -353,7 +408,6 @@ static void pl061_init(Object *obj) SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); =20 s->id =3D pl061_id; - s->rsvd_start =3D 0x424; =20 memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000); sysbus_init_mmio(sbd, &s->iomem); --=20 2.20.1 From nobody Thu Dec 18 22:18:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625847502; cv=none; d=zohomail.com; s=zohoarc; b=inTi1AlxIv/OYO+2xAwhgQRNnPDR7Y7X0AQtFBsQqsm/PvRmFrr7Eht/wI1ht5FyfHiwSYMzB/ESHRJTcHA+euEt5hlD/4ba7PJuVs4M6j+iWYL043jw3V0H8n9AaE/KIE/kCxyjYF+gIRIMoOYgA8x0uUAd/6cHezrGl795U4Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625847502; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x19sm5232277wmi.10.2021.07.09.09.10.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 09:10:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rfdm8hMp1rU2ugPXFVshopocV670fyDA7HBkl2H1lks=; b=NEx859oQbJPSqQpMMe44kUEz3saIt1n03EWV+Jvd8HDv6HFGDI9nCpx8XzEbHrIgO9 1ZkVRTPvhskMV8IzOZFifcQWQXutRjtowyi40D5rlp+6ZWPqzem3csUJM7KemMZDMqnO I28AG0jgAXa3rFDfi4ceOwcRnxRttx3ie7A92Sf5iAF4G17yZubSG5UX6NQGnWP52uLg Hn4c9GBfSH9fyu0XRVJ00+8LSS2WvR/hfGatYPOLJLrrFeVkTSBGAMZmq8KSV8qXQ03s e7Wd3wxMkSH0VBw6ouEajqRz/JYGOKJwJ+iS/Eem66h+FLHiCgUXLqGbuo5gTBLdkOJ5 5tgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rfdm8hMp1rU2ugPXFVshopocV670fyDA7HBkl2H1lks=; b=apS5zfmN6L1QwdIpp9cjkIWOUhsk0DqQZWXTJhlI+35FNh6ohPnCdI+fGAPryBYnKG +pAFdQsAzSCgvMC035faD6NYR9Hz6KaCBsPQajIXaJaSjW42Mj7RLGnw1Tp7a1vb50lg Jv9fbvVB5xMt6L82Ys9SmbbSbDtT9jcPvejdlCmHSy8/E3QPlt7rm19o5uHgXB/8uhCJ ufVbaPX2tsUgYME5RnlY4Oi7mbVR8vjcTo3/aRs/M5NBPz8KhmwIAqtp7tvJUojaEHV7 EYIq6VG0NcB1t2AKhsAdsfDr3HalPdmbT+B3a6z7Lbn9KX21swE/WBMP1zsWcW5DrxBG 4p9g== X-Gm-Message-State: AOAM53000mpK6a+yGlM6Wo1tnSfJbNsMMbGCmV/NtTRcmWtwI+51M4je D18qT8odm3mBViQmLVphM+xOF6SWEEoNwAoW X-Google-Smtp-Source: ABdhPJxARkezFxP+o/HVFL6UEJCrpfa9vxHhCZlDgF4jRP+qQvGRhyr4L2SniWKElagcA7Kt3HJ4Ew== X-Received: by 2002:adf:f04a:: with SMTP id t10mr41848297wro.318.1625847011233; Fri, 09 Jul 2021 09:10:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/17] hw/gpio/pl061: Add tracepoints for register read and write Date: Fri, 9 Jul 2021 17:09:54 +0100 Message-Id: <20210709161003.25874-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210709161003.25874-1-peter.maydell@linaro.org> References: <20210709161003.25874-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625847504213100001 Add tracepoints for reads and writes to the PL061 registers. This requires restructuring pl061_read() to only return after the tracepoint, rather than having lots of early-returns. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/gpio/pl061.c | 70 ++++++++++++++++++++++++++++++-------------- hw/gpio/trace-events | 2 ++ 2 files changed, 50 insertions(+), 22 deletions(-) diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index b21b230402f..42f6e6c4891 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -149,90 +149,114 @@ static uint64_t pl061_read(void *opaque, hwaddr offs= et, unsigned size) { PL061State *s =3D (PL061State *)opaque; + uint64_t r =3D 0; =20 switch (offset) { case 0x0 ... 0x3ff: /* Data */ - return s->data & (offset >> 2); + r =3D s->data & (offset >> 2); + break; case 0x400: /* Direction */ - return s->dir; + r =3D s->dir; + break; case 0x404: /* Interrupt sense */ - return s->isense; + r =3D s->isense; + break; case 0x408: /* Interrupt both edges */ - return s->ibe; + r =3D s->ibe; + break; case 0x40c: /* Interrupt event */ - return s->iev; + r =3D s->iev; + break; case 0x410: /* Interrupt mask */ - return s->im; + r =3D s->im; + break; case 0x414: /* Raw interrupt status */ - return s->istate; + r =3D s->istate; + break; case 0x418: /* Masked interrupt status */ - return s->istate & s->im; + r =3D s->istate & s->im; + break; case 0x420: /* Alternate function select */ - return s->afsel; + r =3D s->afsel; + break; case 0x500: /* 2mA drive */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->dr2r; + r =3D s->dr2r; + break; case 0x504: /* 4mA drive */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->dr4r; + r =3D s->dr4r; + break; case 0x508: /* 8mA drive */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->dr8r; + r =3D s->dr8r; + break; case 0x50c: /* Open drain */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->odr; + r =3D s->odr; + break; case 0x510: /* Pull-up */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->pur; + r =3D s->pur; + break; case 0x514: /* Pull-down */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->pdr; + r =3D s->pdr; + break; case 0x518: /* Slew rate control */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->slr; + r =3D s->slr; + break; case 0x51c: /* Digital enable */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->den; + r =3D s->den; + break; case 0x520: /* Lock */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->locked; + r =3D s->locked; + break; case 0x524: /* Commit */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->cr; + r =3D s->cr; + break; case 0x528: /* Analog mode select */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->amsel; + r =3D s->amsel; + break; case 0xfd0 ... 0xfff: /* ID registers */ - return s->id[(offset - 0xfd0) >> 2]; + r =3D s->id[(offset - 0xfd0) >> 2]; + break; default: bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "pl061_read: Bad offset %x\n", (int)offset); break; } - return 0; + + trace_pl061_read(DEVICE(s)->canonical_path, offset, r); + return r; } =20 static void pl061_write(void *opaque, hwaddr offset, @@ -241,6 +265,8 @@ static void pl061_write(void *opaque, hwaddr offset, PL061State *s =3D (PL061State *)opaque; uint8_t mask; =20 + trace_pl061_write(DEVICE(s)->canonical_path, offset, value); + switch (offset) { case 0 ... 0x3ff: mask =3D (offset >> 2) & s->dir; diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index 48ccbb183cc..442be9406f5 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -18,6 +18,8 @@ pl061_update(const char *id, uint32_t dir, uint32_t data)= "%s GPIODIR 0x%x GPIOD pl061_set_output(const char *id, int gpio, int level) "%s setting output %= d to %d" pl061_input_change(const char *id, int gpio, int level) "%s input %d chang= ed to %d" pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int leve= l) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d" +pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PR= Ix64 " value 0x%" PRIx64 +pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x= %" PRIx64 " value 0x%" PRIx64 =20 # sifive_gpio.c sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value = 0x%" PRIx64 --=20 2.20.1 From nobody Thu Dec 18 22:18:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625847972; cv=none; d=zohomail.com; s=zohoarc; b=QpVP3X+yIzsG0rTDmJhOr3RyGoBVKOJRX+RDNfWM5jyKmv7FqISQq6MCTzI06E4L8tzRe9bI6zggBBuS0PHaGalL/8P9FeDRs7LsmGeJrkvyYckdliX14bGiZ6Ptest0wx+up4B6xubaWX0YNjNAe/imirYWDUXkRrMlSxZbwyI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625847972; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MBTkeOxa7kZ6L35aP7m9uF9eaW4Hvs6rU41xNfdKBxI=; b=jsSgBMShsDMA6n1Avd0O5a3G/tY257oFXcNetosq7Dlj/qqlElg45fNlxmudn3CIukb/9RowxGjXtelHbpKqcvyGBKTYI5GB6uxEz7ggfMluw8dNa6jacgWxzyFN4DaCiJggdSSpYAGBH+cKU7gRoF0efNdcPo15yZPgVb/xu0I= ARC-Authentication-Results: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x19sm5232277wmi.10.2021.07.09.09.10.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 09:10:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=MBTkeOxa7kZ6L35aP7m9uF9eaW4Hvs6rU41xNfdKBxI=; b=jptwMPhpxo7R/xOT8AHDUDNb1ap27N1GgG7CGo57FhXzAd7/9wBGCIT8iwOOsq6BsV 3luykQ3JhWqzlUxzCrApQ6LB6v/6IYGG4sVFmeRlDd6+lEKaMAR7K7fk2xOJqy1drFOf K+sXjBWTXJ3v+rf5z3zw0ZxpYTza39rCLnjw0HSSYdDGWg+9uOTa/4JkUIcfWxD98Na6 wQtYkvIiWYsp0p1I/SB88BxRC/g5r0xENU/Bus9vJw92IfI6t6RmzuqP1+W4E4I1vXuK 86hojcRXcCJ9LvFDJp3wTjA5FTirQn7w+WihA0jsCLASPuiZyJomDmZL0aYyWl3bYd88 gZ2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MBTkeOxa7kZ6L35aP7m9uF9eaW4Hvs6rU41xNfdKBxI=; b=m9zkcmZxf3M/arPOeahL/dt8Z1WX6cOFXJQQDIgZjPeN0XoYThfWqkwgH2CEbrvH/I fmIqedQS2dcuJb1AxeVsg8ByBzaf0OFG8EhxvFkU1JfVc2OeKbuKRQBwcCFE5AS3F6cR 3dBy5o46RwurNWfyULiJIS5PpExC9AwgF97U85tJzjSClpxR4XrkLXOMXnCSGoeAn+OG GgIEOnBzzSD2yHdpRyKtfKuragpbG/8L3pH2kpGnX0WqOBK/ESUlyWdzk3/uJG6cO4h3 sO4DcJ+p/V43T+KTpul8Md+KFYmYj1b+TJ5kJdxnLQG21ufgsiIOR7E9QES44b0gUVGA k3oA== X-Gm-Message-State: AOAM533mhQNzK4+6ocqBmxkiKgpo6g/z9QLwmm7Dc3VDoIIQLd6bkiwu n42sXltGB9CmMl/y0N5Zj+NL8jmqH65EGDN1 X-Google-Smtp-Source: ABdhPJyQTdV+kokguax4uHsPQrLs0o9F+86EJDdGZqT80bcfYVwfR6UJMA+3NI0+fm0sKYc8zw1fjA== X-Received: by 2002:adf:b307:: with SMTP id j7mr18941649wrd.243.1625847011870; Fri, 09 Jul 2021 09:10:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/17] hw/gpio/pl061: Document the interface of this device Date: Fri, 9 Jul 2021 17:09:55 +0100 Message-Id: <20210709161003.25874-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210709161003.25874-1-peter.maydell@linaro.org> References: <20210709161003.25874-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625847974255100001 Content-Type: text/plain; charset="utf-8" Add a comment documenting the "QEMU interface" of this device: which MMIO regions, IRQ lines, GPIO lines, etc it exposes. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/gpio/pl061.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index 42f6e6c4891..a3c13862212 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -6,6 +6,13 @@ * Written by Paul Brook * * This code is licensed under the GPL. + * + * QEMU interface: + * + sysbus MMIO region 0: the device registers + * + sysbus IRQ: the GPIOINTR interrupt line + * + unnamed GPIO inputs 0..7: inputs to connect to the emulated GPIO lin= es + * + unnamed GPIO outputs 0..7: the emulated GPIO lines, considered as + * outputs */ =20 #include "qemu/osdep.h" --=20 2.20.1 From nobody Thu Dec 18 22:18:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625848089; cv=none; d=zohomail.com; s=zohoarc; b=jwlP5UHZvpDYcENRVCgu0zLBFK2KGifzknzh7lPc5onyT82GBgAOajhW6ydxe5EbCO9vXhV4K2Zu+pb5ifldtGbi3+U0i2IXayMW/tqE6+f5InhrrEGYzqGdS6EOnFlUDvTmRvYUdil6hR/2Dsnb+sCpo1CyKKfqr4yoYjROhkM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625848089; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/woNcoh3ZeS8B1EeIl8RNXxUxRvnbu60lOJtJFH7KKU=; b=ThvAx6JKUq6HF/7JWzJaZJThQmLUnyGzziknbZmUbOA6YnYeLCmnrMQLYxQ+06UiJP8dV4Rqy0fd4Rh4PqlKwoH2pSuk4O5eVm+Lp59xDZhc3AZyzSQ0x7d2L6EevDtWk+U4uQxOqTGh8vQ+imlFk11jxbRtunJ02qA66S3NqGk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162584808902715.706406897256102; Fri, 9 Jul 2021 09:28:09 -0700 (PDT) Received: from localhost ([::1]:51994 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1tMF-0007Cz-W5 for importer@patchew.org; Fri, 09 Jul 2021 12:28:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37618) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1t55-0001WW-V2 for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:24 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:41573) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m1t4v-0000vA-Sl for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:23 -0400 Received: by mail-wr1-x433.google.com with SMTP id k4so6549982wrc.8 for ; Fri, 09 Jul 2021 09:10:13 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x19sm5232277wmi.10.2021.07.09.09.10.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 09:10:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/woNcoh3ZeS8B1EeIl8RNXxUxRvnbu60lOJtJFH7KKU=; b=WUylE5Gslm0CIEaCxoMPMivMqv/HUwyJvE5N9l9T68X1t4EjWl0g/LOtLnehb9OfO+ cnMsrmFABq1oDrhY0crvbiR0rp/3RdTXmIx7rwl/onbBHpu1efpEnJocayITuNxc/M+J +4gIeakrzM92/1Sbd3QFhITcNjh45Z+N39aEiWykSaymNHAbmX7c4hjrM1YaG1lxBw4w UrxiHCxM84VU2HJTIVwSERXVyBMuhu/TPdITPoxbb9dJr34rtmFNNf3LJ+k9Wtgk2c8d rbJhYKHqnyRwvoGxiFs43olLhgPRbJS+HJTqKqPLNZbbcJ73D9WnfrbBt2GTDPKq+lV3 sjug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/woNcoh3ZeS8B1EeIl8RNXxUxRvnbu60lOJtJFH7KKU=; b=X9NJ23lo9tHRt9k+K4+HB/Us+1W0nSJKXSTmmEx80vXT5vQfAws+Zr6cFk17s7CS14 pKWzLXJ+GMsGw1wxR87gN5NzpYogm/Er4TMuwtQ8DYH1Vi3Ryyh9ETd5uFvJLVI1SlDK PsmMYVe4zQ3L8iavwZTpTu6cGlYzUgMJ0/Kfo6t+Dy0eWzPHOA4Qxx+rVwYwzf7pAyUL 6YES6qdPZOhXal5A+JKCdD41zSakx6AIjPpdUuES380DqDhGL/zI+2GnUPuxATmGlXoF mTKw0MS5Og/ctOJG/0OZwSoro1UQHYQzhGiHoP5hcxsX4bQyI0427Zr4VR4vga2H/gGb NEPw== X-Gm-Message-State: AOAM5313pVhLrmM/Vz9ZXThAB+qdU85laRVWTvfGNCiOH/im75e4VdP+ XqN9O+erUxZ46KuW3+Fsla8QwwDAzs+W8QeA X-Google-Smtp-Source: ABdhPJzyRQ8tyPjt52ZAmUlO/MH2TGpRHZ0JgtdZjyu+IHOl1e9WmE4Dv19goXE0r/tU0fq/QuvGEQ== X-Received: by 2002:adf:f789:: with SMTP id q9mr13379511wrp.81.1625847012578; Fri, 09 Jul 2021 09:10:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/17] hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers Date: Fri, 9 Jul 2021 17:09:56 +0100 Message-Id: <20210709161003.25874-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210709161003.25874-1-peter.maydell@linaro.org> References: <20210709161003.25874-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625848090380100001 Content-Type: text/plain; charset="utf-8" The Luminary variant of the PL061 has registers GPIOPUR and GPIOPDR which lets the guest configure whether the GPIO lines are pull-up, pull-down, or truly floating. Instead of assuming all lines are pulled high, honour the PUR and PDR registers. For the plain PL061, continue to assume that lines have an external pull-up resistor, as we did before. The stellaris board actually relies on this behaviour -- the CD line of the ssd0323 display device is connected to GPIO output C7, and it is only because of a different bug which we're about to fix that we weren't incorrectly driving this line high on reset and putting the ssd0323 into data mode. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/gpio/pl061.c | 58 +++++++++++++++++++++++++++++++++++++++++--- hw/gpio/trace-events | 2 +- 2 files changed, 55 insertions(+), 5 deletions(-) diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index a3c13862212..9360c143eef 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -94,18 +94,68 @@ static const VMStateDescription vmstate_pl061 =3D { } }; =20 +static uint8_t pl061_floating(PL061State *s) +{ + /* + * Return mask of bits which correspond to pins configured as inputs + * and which are floating (neither pulled up to 1 nor down to 0). + */ + uint8_t floating; + + if (s->id =3D=3D pl061_id_luminary) { + /* + * If both PUR and PDR bits are clear, there is neither a pullup + * nor a pulldown in place, and the output truly floats. + */ + floating =3D ~(s->pur | s->pdr); + } else { + /* Assume outputs are pulled high. FIXME: this is board dependent.= */ + floating =3D 0; + } + return floating & ~s->dir; +} + +static uint8_t pl061_pullups(PL061State *s) +{ + /* + * Return mask of bits which correspond to pins configured as inputs + * and which are pulled up to 1. + */ + uint8_t pullups; + + if (s->id =3D=3D pl061_id_luminary) { + /* + * The Luminary variant of the PL061 has an extra registers which + * the guest can use to configure whether lines should be pullup + * or pulldown. + */ + pullups =3D s->pur; + } else { + /* Assume outputs are pulled high. FIXME: this is board dependent.= */ + pullups =3D 0xff; + } + return pullups & ~s->dir; +} + static void pl061_update(PL061State *s) { uint8_t changed; uint8_t mask; uint8_t out; int i; + uint8_t pullups =3D pl061_pullups(s); + uint8_t floating =3D pl061_floating(s); =20 - trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data); + trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data, + pullups, floating); =20 - /* Outputs float high. */ - /* FIXME: This is board dependent. */ - out =3D (s->data & s->dir) | ~s->dir; + /* + * Pins configured as output are driven from the data register; + * otherwise if they're pulled up they're 1, and if they're floating + * then we give them the same value they had previously, so we don't + * report any change to the other end. + */ + out =3D (s->data & s->dir) | pullups | (s->old_out_data & floating); changed =3D s->old_out_data ^ out; if (changed) { s->old_out_data =3D out; diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index 442be9406f5..eb5fb4701c6 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -14,7 +14,7 @@ nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi= 64 " value %" PRIi64 nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 = " value %" PRIi64 =20 # pl061.c -pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x= GPIODATA 0x%x" +pl061_update(const char *id, uint32_t dir, uint32_t data, uint32_t pullups= , uint32_t floating) "%s GPIODIR 0x%x GPIODATA 0x%x pullups 0x%x floating 0= x%x" pl061_set_output(const char *id, int gpio, int level) "%s setting output %= d to %d" pl061_input_change(const char *id, int gpio, int level) "%s input %d chang= ed to %d" pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int leve= l) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d" --=20 2.20.1 From nobody Thu Dec 18 22:18:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625847695; cv=none; d=zohomail.com; s=zohoarc; b=Gbs4FiX1H4F+OPnq0VyIkoIb4/fEy+tCrBINxhcRMIWcdBMkWH91cGJSO+I4QekHyHB2ShHpR0TKjceAcmyQ9t3WZLy8Yd0lwum/X9i/eimzJWRdMbzm6jSPWD2yoeqQRszyQ+rV2eXARBhjMKEok+5nFhm7TWlJtY9bo3+EVi8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625847695; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aHRaVWqPn2HCxCJuZ+zjdoZsyhFaWY2cM+MNuYOv0sg=; b=fYhBtoqADt1cXR2yOy5jCGQ0tvmh+rcuUNbLawJ84BX4tKTZoCh/lVxtuJHw39yOap6fNf40EzpY2/qlLdfZn4ksqfZXbWiDEqcjvaFP/+8CEoFr0OlqucveSfoRYnYNlWDhqx72aWUGyCQe48QLKVIpw7Ra6RLwK3f2yv/gFSU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162584769534992.66704218669793; Fri, 9 Jul 2021 09:21:35 -0700 (PDT) Received: from localhost ([::1]:58656 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1tFu-0008FG-BE for importer@patchew.org; Fri, 09 Jul 2021 12:21:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37598) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1t54-0001W1-B5 for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:22 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:38608) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m1t4x-0000vl-OE for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:22 -0400 Received: by mail-wm1-x32f.google.com with SMTP id b14-20020a1c1b0e0000b02901fc3a62af78so9393266wmb.3 for ; Fri, 09 Jul 2021 09:10:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x19sm5232277wmi.10.2021.07.09.09.10.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 09:10:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=aHRaVWqPn2HCxCJuZ+zjdoZsyhFaWY2cM+MNuYOv0sg=; b=gDD4+lQr6ivR7RbLcQkQ7EXJgA5OT03URLGTVBDLVD3CcJYjLrVxqfHyJuKE6iCkzD mxz1hCDx5XSXqfMS92TKy5Dof4EipkkW68CilRUa8yzpvyu0YACNKbLU+fQa9KMI/Xot VmrpLUQca9iQKtxx3twK5CopGE1FwrASebDmBOjMQoiGkvVUGpUWSU3aczGPRv9dajWp IaL7jb3cqBHhFOQhXCXRVEBJO/wZvky8IdoitOyNYNy1j6dJ4YS6kd0M1urQ/jneqjLQ A73g0fwEWXNWWnsc1lfgFYb8D9z5SeATGLDWXYd+JgWRWJEbsgtZZ1QHhj+EgHVaFEPT t+3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aHRaVWqPn2HCxCJuZ+zjdoZsyhFaWY2cM+MNuYOv0sg=; b=BFSPwABV7cx1CGvWalf6ZyLPNhBA+bDzhKMasLyXls3tHW0MMqygjEML+6MkpSzdk7 qQYWwqoLlBay0INmqb05FGWEkv9ZbUH13az2Q3yN+7e4jpSDODbMUNIVTjcug0raHFY2 XNgLgV2UcRvwLlZKTL18OwjnQxzCOt3FH0RT+Bv1HggPUmln1v+6CnfzRYPCu0igC6cF ch/5pMJb9CEhCghG6woFHJ9N0y6wDEZA3HLZNCWLDMWYNWhmnLYLJ6e2fNHAjBilaPud Cy7X6k1BIdhvlRUsmCPRVaF1eaVLLgIMxWHWOUy4wu6GIwAe+yRGJX3SNYXoFEhQP2rV hXuA== X-Gm-Message-State: AOAM5320QH1wmshO1yWO5oS43C7B3noBi5zLj0IfO40ItFvH0adp5RLo b+wF1Ni4HyxPPW4R7lKKz7ZA4X29vcNDclRc X-Google-Smtp-Source: ABdhPJy75iZgD47RFitS4T9yo2w0PSEIngdgkhGseye2HSlBJyn2vRDDRKHqnS9wSpD2wy/UI3VpLQ== X-Received: by 2002:a1c:4d14:: with SMTP id o20mr10666590wmh.89.1625847013236; Fri, 09 Jul 2021 09:10:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/17] hw/gpio/pl061: Make pullup/pulldown of outputs configurable Date: Fri, 9 Jul 2021 17:09:57 +0100 Message-Id: <20210709161003.25874-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210709161003.25874-1-peter.maydell@linaro.org> References: <20210709161003.25874-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625847697287100001 Content-Type: text/plain; charset="utf-8" The PL061 GPIO does not itself include pullup or pulldown resistors to set the value of a GPIO line treated as an output when it is configured as an input (ie when the PL061 itself is not driving it). In real hardware it is up to the board to add suitable pullups or pulldowns. Currently our implementation hardwires this to "outputs pulled high", which is correct for some boards (eg the realview ones: see figure 3-29 in the "RealView Platform Baseboard for ARM926EJ-S User Guide" DUI0224I), but wrong for others. In particular, the wiring in the 'virt' board and the gpio-pwr device assumes that wires should be pulled low, because otherwise the pull-to-high will trigger a shutdown or reset action. (The only reason this doesn't happen immediately on startup is due to another bug in the PL061, where we don't assert the GPIOs to the correct value on reset, but will do so as soon as the guest touches a register and pl061_update() gets called.) Add properties to the pl061 so the board can configure whether it wants GPIO lines to have pullup, pulldown, or neither. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/gpio/pl061.c | 51 +++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 47 insertions(+), 4 deletions(-) diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index 9360c143eef..5ba398fcd42 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -13,12 +13,28 @@ * + unnamed GPIO inputs 0..7: inputs to connect to the emulated GPIO lin= es * + unnamed GPIO outputs 0..7: the emulated GPIO lines, considered as * outputs + * + QOM property "pullups": an integer defining whether non-floating lin= es + * configured as inputs should be pulled up to logical 1 (ie whether in + * real hardware they have a pullup resistor on the line out of the PL0= 61). + * This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should + * be pulled high, bit 1 configures line 1, and so on. The default is 0= xff, + * indicating that all GPIO lines are pulled up to logical 1. + * + QOM property "pulldowns": an integer defining whether non-floating l= ines + * configured as inputs should be pulled down to logical 0 (ie whether = in + * real hardware they have a pulldown resistor on the line out of the P= L061). + * This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should + * be pulled low, bit 1 configures line 1, and so on. The default is 0x= 0. + * It is an error to set a bit in both "pullups" and "pulldowns". If a = bit + * is 0 in both, then the line is considered to be floating, and it will + * not have qemu_set_irq() called on it when it is configured as an inp= ut. */ =20 #include "qemu/osdep.h" #include "hw/irq.h" #include "hw/sysbus.h" +#include "hw/qdev-properties.h" #include "migration/vmstate.h" +#include "qapi/error.h" #include "qemu/log.h" #include "qemu/module.h" #include "qom/object.h" @@ -62,6 +78,9 @@ struct PL061State { qemu_irq irq; qemu_irq out[N_GPIOS]; const unsigned char *id; + /* Properties, for non-Luminary PL061 */ + uint32_t pullups; + uint32_t pulldowns; }; =20 static const VMStateDescription vmstate_pl061 =3D { @@ -109,8 +128,7 @@ static uint8_t pl061_floating(PL061State *s) */ floating =3D ~(s->pur | s->pdr); } else { - /* Assume outputs are pulled high. FIXME: this is board dependent.= */ - floating =3D 0; + floating =3D ~(s->pullups | s->pulldowns); } return floating & ~s->dir; } @@ -131,8 +149,7 @@ static uint8_t pl061_pullups(PL061State *s) */ pullups =3D s->pur; } else { - /* Assume outputs are pulled high. FIXME: this is board dependent.= */ - pullups =3D 0xff; + pullups =3D s->pullups; } return pullups & ~s->dir; } @@ -499,12 +516,38 @@ static void pl061_init(Object *obj) qdev_init_gpio_out(dev, s->out, N_GPIOS); } =20 +static void pl061_realize(DeviceState *dev, Error **errp) +{ + PL061State *s =3D PL061(dev); + + if (s->pullups > 0xff) { + error_setg(errp, "pullups property must be between 0 and 0xff"); + return; + } + if (s->pulldowns > 0xff) { + error_setg(errp, "pulldowns property must be between 0 and 0xff"); + return; + } + if (s->pullups & s->pulldowns) { + error_setg(errp, "no bit may be set both in pullups and pulldowns"= ); + return; + } +} + +static Property pl061_props[] =3D { + DEFINE_PROP_UINT32("pullups", PL061State, pullups, 0xff), + DEFINE_PROP_UINT32("pulldowns", PL061State, pulldowns, 0x0), + DEFINE_PROP_END_OF_LIST() +}; + static void pl061_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->vmsd =3D &vmstate_pl061; dc->reset =3D &pl061_reset; + dc->realize =3D pl061_realize; + device_class_set_props(dc, pl061_props); } =20 static const TypeInfo pl061_info =3D { --=20 2.20.1 From nobody Thu Dec 18 22:18:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625848311; cv=none; d=zohomail.com; s=zohoarc; b=ALSTqAjrOKKO51eKHgG+hN2a21mT+GO+MjjlZMBVfH2afB29efrk5fZvgInqo20LQCAGwey88JULe7wqprnkj/qIxKjpZovOdWLdHYLeiBFVkm2KUZCwsdagQUc/fQdfF85EYjH/K2yTnyTGrVBn2EmS6FvZyi2i3cHfhnrTjak= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625848311; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OMOutzP5V+LKhVzV0NiCVOi1/mPW5v43bptuBd6wcgo=; b=mqp32hJDiRi0IDAErP/EerrhyIPTdF3SBNrXh0BpFp6o4kiVRGkG4DCHA147JCLY+H58c7eT/4sLa0u4ekAbGA+jdSJDMpvzmfFWaPH131kwJ1yavtR0+TUZq3DJp3VxoVl5vXJH4pRggsReKX01Q9KAxFNk+sLQAfmezumAxQY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1625848311839605.2914911398776; Fri, 9 Jul 2021 09:31:51 -0700 (PDT) Received: from localhost ([::1]:36570 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1tPq-0008Ce-IB for importer@patchew.org; Fri, 09 Jul 2021 12:31:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37642) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1t57-0001Yw-6j for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:25 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:36517) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m1t4y-0000wM-Nh for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:24 -0400 Received: by mail-wm1-x32e.google.com with SMTP id t14-20020a05600c198eb029020c8aac53d4so26460737wmq.1 for ; Fri, 09 Jul 2021 09:10:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x19sm5232277wmi.10.2021.07.09.09.10.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 09:10:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=OMOutzP5V+LKhVzV0NiCVOi1/mPW5v43bptuBd6wcgo=; b=Dj7H1+4vg2laI7rDF8KXygC9Bv0KwQzh/VKAu0pphs+b99VzNX2Mr633kXFI/2Eyc3 rPweFleCHGh9mpe606obQ4ghvjQLsGSNY2D4sP+qyWSp/MUXLcszQKOHRLX455xJ7YSZ oV415V5zbfixVebmc11rZrS3U/E7bwVhEEn6j5Ggf5VGwGqHKVnqHexKVgybTHFtYXjU Y6z4vy8wAZj84nU3+YFjLCyFc8HLQT2NIvc9m3n9ZGCj0aSDlYPRBtEmUL63Qv34lLd7 LJTD5FWfF6mi3cD4hmWYXj++WYLrJ4335/mHjA6AOIMUbJDcb6P80sJaqzQFjwHq5qlH IvyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OMOutzP5V+LKhVzV0NiCVOi1/mPW5v43bptuBd6wcgo=; b=QxJRT2aeWPnQeWzdsvxs4+Kot2grtsoHsoc4eBGZLc1aRMcTkK2URjlROU6UWdHFFO 4rbqBBiIBCURQYcVVmi+ClAn85/1RhNR4ddiK8nGYt+9Yn5MaMOJHPNGo2Gz4RR+mq2Q gDTitRU6Ob91etrGIez/39zlFulq8LU3jpcXqDH2eZ83PeAkS4WIcesDNZN5LTteIV0O CQhFRriHsoKjfxoRGftf/ph29xNoaKi38xwBWlMq//YRkQ0wFdKeC//mN0yN6G2U2Qs9 mIbkfy8dkJs0B5yNBvg24HqepX7Xbd1ERX+7Fd4XSz5vx52AqBRWbkygYB2piwSgMqFg Gwhw== X-Gm-Message-State: AOAM531S3r1xLnwaZBUpP2qAcDQs9tmV56jkGgRbUSUt4V98IUU9GW8t pP/K0K8gMcPWhXRbSrtIJ/5cEUOyVfV9cdve X-Google-Smtp-Source: ABdhPJzaFBuexlUbLIdAQ9xhd7z8Uj7c286u/rAqTCzSfvCoYfAfIcV1aw2FhLqjg8+20M4as8T/3w== X-Received: by 2002:a05:600c:4f87:: with SMTP id n7mr41290167wmq.9.1625847013810; Fri, 09 Jul 2021 09:10:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/17] hw/arm/virt: Make PL061 GPIO lines pulled low, not high Date: Fri, 9 Jul 2021 17:09:58 +0100 Message-Id: <20210709161003.25874-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210709161003.25874-1-peter.maydell@linaro.org> References: <20210709161003.25874-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625848312827100003 Content-Type: text/plain; charset="utf-8" For the virt board we have two PL061 devices -- one for NonSecure which is inputs only, and one for Secure which is outputs only. For the former, we don't care whether its outputs are pulled low or high when the line is configured as an input, because we don't connect them. For the latter, we do care, because we wire the lines up to the gpio-pwr device, which assumes that level 1 means "do the action" and 1 means "do nothing". For consistency in case we add more outputs in future, configure both PL061s to pull GPIO lines down to 0. Reported-by: Maxim Uvarov Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/virt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 4b96f060140..93ab9d21ea0 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -895,6 +895,9 @@ static void create_gpio_devices(const VirtMachineState = *vms, int gpio, MachineState *ms =3D MACHINE(vms); =20 pl061_dev =3D qdev_new("pl061"); + /* Pull lines down to 0 if not driven by the PL061 */ + qdev_prop_set_uint32(pl061_dev, "pullups", 0); + qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); s =3D SYS_BUS_DEVICE(pl061_dev); sysbus_realize_and_unref(s, &error_fatal); memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); --=20 2.20.1 From nobody Thu Dec 18 22:18:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625848488; cv=none; d=zohomail.com; s=zohoarc; b=SdeEuedgZTFZxW5j/UVm1knL5pcPlk4ca1Lh3hGiPfy8wuQ3IAF5jF/bgYuvhVgmdaAHHyR9qa0UJ5icHd+X/DhjmWqjWrr4q2orLJa1JuXDvGdBIxnkYykbCaw0hFe+aVMklmhJ276+Kv1r1iO+ZhW5/Q7nAuDttUW7lMDo5tE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625848488; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=g5RTMo3cZi5CJpdjcBxAxRPO+ziLZygfzXi5BsAwtdU=; b=cGgYlI+aoQeFm00k8ZGiHOr5ok69t2t4JffJWHoSuzPr2X2TNaURakXoMN8WUA5VXRFIHSlHlK5hxA9C+40Ngy0pvx76qPbG35d1e2RQAeq/fuYr607vWEgE352kIapOA+eBm4IlFjrqeZbiaDANmt/EOu9f6DcgAq6iy7ym3WY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1625848488053295.8785522181299; Fri, 9 Jul 2021 09:34:48 -0700 (PDT) Received: from localhost ([::1]:41918 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1tSg-0003W3-VU for importer@patchew.org; Fri, 09 Jul 2021 12:34:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37656) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1t57-0001c2-WC for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:26 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:43801) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m1t4x-0000wr-Pp for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:25 -0400 Received: by mail-wr1-x435.google.com with SMTP id a13so12819079wrf.10 for ; Fri, 09 Jul 2021 09:10:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x19sm5232277wmi.10.2021.07.09.09.10.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 09:10:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=g5RTMo3cZi5CJpdjcBxAxRPO+ziLZygfzXi5BsAwtdU=; b=nYPSSlWm2EF0O1qqle987sSYtMkTDJNvV41p51RQI3NcJ7qgEtybkm84/QpWBac2r7 dF29cakrs2va8pBE+LWTloMpJ1j9RIZx9QKyrgaw9t1rFF53Q8t0X3JqPUH6o3HMNhMZ Yg1qlcZ+4+4X+wtJMXnpx+fSDXV8ECaZQxl5tlo8fFKcUW9u0bbuP3Yr/8zlQidfrwbq HNyRndrM2pwIpZl+JiUObJNg6LfUKir2ZuiGAjfQBG7fOlVsRlLNuHzHybvGqw/J+dYJ X3EJstpajc179PCdZNkWb8mFEM1OGrBmJd4dE4OjXMAz5lgGnmh9FrBRiVpH0yQSgTyb fmjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g5RTMo3cZi5CJpdjcBxAxRPO+ziLZygfzXi5BsAwtdU=; b=Z3z2ImvD42WhPk2wLPa8XRniYq7FCPQsJXbA3TODffAF1idAnQgT4FQc+7MbtDN+cF 9st2EfOMdzlukcmlrEQkxai/YLFyL/ByjxBJuh+QFBGGL5pQkF5kvJHmqcVXjuXz3oKi 8vDgchRg9tlFBlfQKC75K2qtOtTY9wP+ig6X0msgLNKxy+htbIk2ujUrSGnfuLqzSwwW UUpEdF9HOpVUgvpaUHXtxRjrNURPNe/t3FK+uZY/2vIbnpBNHqLReNNnjzEW6UFoymEs taFFi9mECrgzg4GpnUs5yhaFy/zNthfRvABtECRvJald1+pT26oHk6FxYMQIYZq4ZqjB Bx+w== X-Gm-Message-State: AOAM530D0hNUUNdiGwDG6JxdjSof+in5PK9gelYqO40WBJAKmOka5BZ/ 4iRmfrCC2//3yIi/SmytbNX4/XyRHjwA7qrF X-Google-Smtp-Source: ABdhPJynDQS5nzVI8wekz3siPX2KEyMrNjTgYh7q+cVQ4euNDf89TqFyM19ITD0GdMlB6dOcZaHn9g== X-Received: by 2002:adf:f2d1:: with SMTP id d17mr24440230wrp.254.1625847014466; Fri, 09 Jul 2021 09:10:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/17] hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset Date: Fri, 9 Jul 2021 17:09:59 +0100 Message-Id: <20210709161003.25874-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210709161003.25874-1-peter.maydell@linaro.org> References: <20210709161003.25874-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625848490286100001 The PL061 comes out of reset with all its lines configured as input, which means they might need to be pulled to 0 or 1 depending on the 'pullups' and 'pulldowns' properties. Currently we do not assert these lines on reset; they will only be set whenever the guest first touches a register that triggers a call to pl061_update(). Convert the device to three-phase reset so we have a place where we can safely call qemu_set_irq() to set the floating lines to their correct values. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/gpio/pl061.c | 29 +++++++++++++++++++++++++---- hw/gpio/trace-events | 1 + 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index 5ba398fcd42..4002ab51544 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -446,13 +446,14 @@ static void pl061_write(void *opaque, hwaddr offset, return; } =20 -static void pl061_reset(DeviceState *dev) +static void pl061_enter_reset(Object *obj, ResetType type) { - PL061State *s =3D PL061(dev); + PL061State *s =3D PL061(obj); + + trace_pl061_reset(DEVICE(s)->canonical_path); =20 /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data She= et */ s->data =3D 0; - s->old_out_data =3D 0; s->old_in_data =3D 0; s->dir =3D 0; s->isense =3D 0; @@ -474,6 +475,24 @@ static void pl061_reset(DeviceState *dev) s->amsel =3D 0; } =20 +static void pl061_hold_reset(Object *obj) +{ + PL061State *s =3D PL061(obj); + int i, level; + uint8_t floating =3D pl061_floating(s); + uint8_t pullups =3D pl061_pullups(s); + + for (i =3D 0; i < N_GPIOS; i++) { + if (extract32(floating, i, 1)) { + continue; + } + level =3D extract32(pullups, i, 1); + trace_pl061_set_output(DEVICE(s)->canonical_path, i, level); + qemu_set_irq(s->out[i], level); + } + s->old_out_data =3D pullups; +} + static void pl061_set_irq(void * opaque, int irq, int level) { PL061State *s =3D (PL061State *)opaque; @@ -543,11 +562,13 @@ static Property pl061_props[] =3D { static void pl061_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 dc->vmsd =3D &vmstate_pl061; - dc->reset =3D &pl061_reset; dc->realize =3D pl061_realize; device_class_set_props(dc, pl061_props); + rc->phases.enter =3D pl061_enter_reset; + rc->phases.hold =3D pl061_hold_reset; } =20 static const TypeInfo pl061_info =3D { diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index eb5fb4701c6..1dab99c5604 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -20,6 +20,7 @@ pl061_input_change(const char *id, int gpio, int level) "= %s input %d changed to pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int leve= l) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d" pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PR= Ix64 " value 0x%" PRIx64 pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x= %" PRIx64 " value 0x%" PRIx64 +pl061_reset(const char *id) "%s reset" =20 # sifive_gpio.c sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value = 0x%" PRIx64 --=20 2.20.1 From nobody Thu Dec 18 22:18:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x19sm5232277wmi.10.2021.07.09.09.10.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 09:10:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6G1TjmFOce0UBb+D3g5YhN34aVbiVQHBMI6am3GYruA=; b=HIHrGNE0Jyhdv2qVsFTV136Wn365LGklrMRqMhAM72NWH4RZO+2o902dXYjc1zD9zG LRFC//v65xZelfzQfsu4+Fhj7Ba6np6HoLJ1cJqq/jjNdgK7LG/hrKN0vt3PCVQMGktr YPKUzihzi7eS7u3h7p1/NCBEAkLr8Xotiyu/I9iOEzXzgayDU++bTidIWOYuyBBGnPlR fCA07TsTw0T067GzlC+c09j55xhrSjEMdXhgxInIKWPviSz6fZSkvkforAVcoSIaOR+f jRvhVk97gjtBYmv8QI40l/vND8KZgZSvhMCNF/ukY0E4VYJt7d2Z8vdWD8kKQf2DAoBl pKww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6G1TjmFOce0UBb+D3g5YhN34aVbiVQHBMI6am3GYruA=; b=N+UbkzRS5I05+dFWOKZbW0UV7q7paxVsi6uZC9A+zdCEFiU+HtLz2POxUeDbaX6E7u N5FdsgDwA6ck4fZWiF9Xa1tpY0ZuLwsdI5qpz8DW9CSuW3YFrXWjLqChmHgg6ifmTKlG CxvYPCZDi61Ii/jfudKAjNB6/zm70bv0H1sUHo+O32UOaEKtcpA/ZGKUrMVgrJ524Yae vF3QtGPb7s1lp/hC48vGu2Wrixsn6oIm6HWBL1osdQUmKwPYKz7jHQ4MRZiXOjow4KTp xT4zIfWPEDueXmTIwbmfTPE4kO+D85G4wPQg8THxVb5oLzKo+GcbWk9SWAoft3c+pgKZ qEaQ== X-Gm-Message-State: AOAM533GVGMeilw/ZmG+tItCailf3NL3r3uiDICKo2ZwVWmnxbPJ07vB n5Avedt7nbyGX/N4jnQcb1COMGmyge0xZ2L2 X-Google-Smtp-Source: ABdhPJyCW4kc2Ak6DEFMnElAEW5YwBiq7Szzw3uYIOCz/ENYaD3a49vLoE93sneAqM1fKLvG86sU6Q== X-Received: by 2002:a5d:4e4e:: with SMTP id r14mr40081792wrt.251.1625847015039; Fri, 09 Jul 2021 09:10:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/17] hw/gpio/pl061: Document a shortcoming in our implementation Date: Fri, 9 Jul 2021 17:10:00 +0100 Message-Id: <20210709161003.25874-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210709161003.25874-1-peter.maydell@linaro.org> References: <20210709161003.25874-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625848191309100001 The Luminary PL061s in the Stellaris LM3S9695 don't all have the same reset value for GPIOPUR. We can get away with not letting the board configure the PUR reset value because we don't actually wire anything up to the lines which should reset to pull-up. Add a comment noting this omission. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/gpio/pl061.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index 4002ab51544..899be861cc5 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -453,6 +453,15 @@ static void pl061_enter_reset(Object *obj, ResetType t= ype) trace_pl061_reset(DEVICE(s)->canonical_path); =20 /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data She= et */ + + /* + * FIXME: For the LM3S6965, not all of the PL061 instances have the + * same reset values for GPIOPUR, GPIOAFSEL and GPIODEN, so in theory + * we should allow the board to configure these via properties. + * In practice, we don't wire anything up to the affected GPIO lines + * (PB7, PC0, PC1, PC2, PC3 -- they're used for JTAG), so we can + * get away with this inaccuracy. + */ s->data =3D 0; s->old_in_data =3D 0; s->dir =3D 0; --=20 2.20.1 From nobody Thu Dec 18 22:18:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625847503; cv=none; d=zohomail.com; s=zohoarc; b=hCwxMBH36v+G0y8tWdH1Av/zut84dehmPfiyEVPu76HIv49Fm+eZjCxzaVzkj4SGOBNzjrcnODWBl2+CMMntHP/x2Z4NtgF8fcPKCvduQAq+gx+pa29ppE1JG4Qsc9gBCq3yoogjLg6v5bF7zQrJxjPMVno87jCnBBSPJ+DbBgI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625847503; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=x+uSZxacODbTK/KRgyLGc1oZvH48wQ1/apF/C2TkCec=; b=DXrIKJE1KFrdXd4GQFGeGtLmk1F2W9Voh5sC4cEUfe4QPhZ/d8Vn7gpK+acBqyAN9zQ04E5pWR44SoaAzVgP2ObQCHEDF8f6r+hGgbKk48VYlb4h6TdtGHwJF82dWXsHI7PEJ84DE3KDLJQJzdnxSrV1ku8aPLqeadK5qJW4ai8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1625847503712152.11489534083125; Fri, 9 Jul 2021 09:18:23 -0700 (PDT) Received: from localhost ([::1]:45830 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1tCo-0007qL-Hs for importer@patchew.org; Fri, 09 Jul 2021 12:18:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37658) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1t58-0001ct-8G for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:26 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:39883) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m1t4z-0000xh-TY for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:25 -0400 Received: by mail-wr1-x42e.google.com with SMTP id f17so12842830wrt.6 for ; Fri, 09 Jul 2021 09:10:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x19sm5232277wmi.10.2021.07.09.09.10.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 09:10:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=x+uSZxacODbTK/KRgyLGc1oZvH48wQ1/apF/C2TkCec=; b=n8yAjSIiSgFWqF5Ss7+Q3O2q3F6bLmijhj8dF2ELS9ak5D4RS+YzkGAAaeRU8xi0Ig WwowxgpexoGByINoHnFEZg6XD5POGF7DlITodT1BON9ktoQKU0Nn4HQZzsQZiB65Mzfu I9ZkJ25t6MX2sWC/Xzv6waBy3KorWz5Par+f4YIvxdL7/5e8Crxo13fumSm19yfPqsW/ qMQlQDyzjAWn2q2XEtKi+hBpW4fJN9L57ga5XlABORtfYK43ffWhoAkCvCVguG0+0a3S Ji8uurD8lhusqAer3yursKhAgeMoTcA07l6P+lgddzKNu28UjIQBBITnmDKtGJvMooyV Wlbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x+uSZxacODbTK/KRgyLGc1oZvH48wQ1/apF/C2TkCec=; b=iHLBqeh+xrSmy87lYPnCcfCsorHbMcRrcMlcyAKHBmmI8PBPIv/DxjnbDYAea28oC2 w3OpC9X54dFhMnZT/mbTAlx5xlvd4lZWuPUkNPzq0jbPU0cbmH6HMEe18iYTtvORfZRm VNkSYavniPINTDddU1XMvVZxXqii+Vl74Drr8VzoDIChzBIwzxCi/7fbnk76nK7CyJPg DHE7/V1bTmNfUZNu2MhjL7jFS7n2ILEotBmTxSJV0YqL+P+MO8jasAHs8lcOo/2gxuhI 6ggFl3qRinWVcRqhAGJRixTcXDR554J+WmLRNfT6ghwDOLmK1wQtis7d2MuG8xvuZCU8 /QEA== X-Gm-Message-State: AOAM5333C9GjL34RwbiMrW6dCCVQS5MhgrfQVs4QQX8r2B2E/YWj/97z CtqsM8pvHlNFqTVPWzuzJtcFywSYdeWSP+WU X-Google-Smtp-Source: ABdhPJyzzERvvs9XQhYuxUTx6M9lE9sLyE/c9kAnaVYq5dZ5rfFD3A8hMpHgES4ivdKEVntvQlWjag== X-Received: by 2002:adf:dfc4:: with SMTP id q4mr2494693wrn.329.1625847015756; Fri, 09 Jul 2021 09:10:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/17] hw/arm/stellaris: Expand comment about handling of OLED chipselect Date: Fri, 9 Jul 2021 17:10:01 +0100 Message-Id: <20210709161003.25874-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210709161003.25874-1-peter.maydell@linaro.org> References: <20210709161003.25874-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625847504272100002 Content-Type: text/plain; charset="utf-8" The stellaris board doesn't emulate the handling of the OLED chipselect line correctly. Expand the comment describing this, including a sketch of the theoretical correct way to do it. Signed-off-by: Peter Maydell --- hw/arm/stellaris.c | 56 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 8b4dab9b79f..ad48cf26058 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1453,13 +1453,67 @@ static void stellaris_init(MachineState *ms, stella= ris_board_info *board) DeviceState *sddev; DeviceState *ssddev; =20 - /* Some boards have both an OLED controller and SD card connec= ted to + /* + * Some boards have both an OLED controller and SD card connec= ted to * the same SSI port, with the SD card chip select connected t= o a * GPIO pin. Technically the OLED chip select is connected to= the * SSI Fss pin. We do not bother emulating that as both devic= es * should never be selected simultaneously, and our OLED contr= oller * ignores stray 0xff commands that occur when deselecting the= SD * card. + * + * The h/w wiring is: + * - GPIO pin D0 is wired to the active-low SD card chip sele= ct + * - GPIO pin A3 is wired to the active-low OLED chip select + * - The SoC wiring of the PL061 "auxiliary function" for A3 = is + * SSI0Fss ("frame signal"), which is an output from the So= C's + * SSI controller. The SSI controller takes SSI0Fss low whe= n it + * transmits a frame, so it can work as a chip-select signa= l. + * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card= Tx + * (the OLED never sends data to the CPU, so no wiring need= ed) + * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card= Rx + * and the OLED display-data-in + * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OL= ED + * serial-clock input + * So a guest that wants to use the OLED can configure the PL0= 61 + * to make pins A2, A3, A5 aux-function, so they are connected + * directly to the SSI controller. When the SSI controller sen= ds + * data it asserts SSI0Fss which selects the OLED. + * A guest that wants to use the SD card configures A2, A4 and= A5 + * as aux-function, but leaves A3 as a software-controlled GPIO + * line. It asserts the SD card chip-select by using the PL061 + * to control pin D0, and lets the SSI controller handle Clk, = Tx + * and Rx. (The SSI controller asserts Fss during tx cycles as + * usual, but because A3 is not set to aux-function this is not + * forwarded to the OLED, and so the OLED stays unselected.) + * + * The QEMU implementation instead is: + * - GPIO pin D0 is wired to the active-low SD card chip sele= ct, + * and also to the OLED chip-select which is implemented + * as *active-high* + * - SSI controller signals go to the devices regardless of + * whether the guest programs A2, A4, A5 as aux-function or= not + * + * The problem with this implementation is if the guest doesn't + * care about the SD card and only uses the OLED. In that case= it + * may choose never to do anything with D0 (leaving it in its + * default floating state, which reliably leaves the card disa= bled + * because an SD card has a pullup on CS within the card itsel= f), + * and only set up A2, A3, A5. This for us would mean the OLED + * never gets the chip-select assert it needs. We work around + * this with a manual raise of D0 here (despite board creation + * code being the wrong place to raise IRQ lines) to put the O= LED + * into an initially selected state. + * + * In theory the right way to model this would be: + * - Implement aux-function support in the PL061, with an + * extra set of AFIN and AFOUT GPIO lines (set up so that + * if a GPIO line is in auxfn mode the main GPIO in and out + * track the AFIN and AFOUT lines) + * - Wire the AFOUT for D0 up to either a line from the + * SSI controller that's pulled low around every transmit, + * or at least to an always-0 line here on the board + * - Make the ssd0323 OLED controller chipselect active-low */ bus =3D qdev_get_child_bus(dev, "ssi"); =20 --=20 2.20.1 From nobody Thu Dec 18 22:18:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625847799; cv=none; d=zohomail.com; s=zohoarc; b=GPG+tB/rMF23+DLtEpWlFNOqZuAdLP7SPz6/XK/OsNmWstSJFM+TCGHcfuDk5x+jwrxMPnk1dQ6Fs68MQHZSG+/FWkrZK6VgkZxxWOQ3yy0EoEXr/shKZbg1E4EN6KyjOCjvcoUR4bzIVAH1iK+c9JcBkV8RzIpNcDbLSpv9s44= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625847799; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zIGcHABe/pzobGUgmxz+iMJPc2gByN1I1kKPS8O7gyo=; b=fGPBSdiwX4tXDtg1llNapfV+nlRzBTkcerIukF1XcnxMiljY5o3qTelnXToaR01lKFWoTfjR3bEMQfWZTB5QBkAbIvvLqyPxGsgReaky20WVPIIK5t9tkLPM9ovuEKVPUyt0UVqO1H0l0kCqJkU4BDoCGJeJLAU4PsnIoAKtPUY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1625847799921722.9559763664046; Fri, 9 Jul 2021 09:23:19 -0700 (PDT) Received: from localhost ([::1]:34806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1tHa-0003Aq-Ln for importer@patchew.org; Fri, 09 Jul 2021 12:23:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37662) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1t59-0001in-Lq for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:27 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:51797) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m1t50-0000yU-0r for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:27 -0400 Received: by mail-wm1-x331.google.com with SMTP id n33so6652617wms.1 for ; Fri, 09 Jul 2021 09:10:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x19sm5232277wmi.10.2021.07.09.09.10.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 09:10:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zIGcHABe/pzobGUgmxz+iMJPc2gByN1I1kKPS8O7gyo=; b=MO0EaRCRPZVwEWNA+smiUPNqdWCKWw7JhqN/neuKo8shBVkkY2J31ZcGgkDUwIZa89 5ttqyObCp/c2I3vxyBpUYvafM0ZozX+rNs1bKQ5PBQXWw7nyOqYURsspc0s728meQVND OzBl8lDjsbCImeEHcF+BMZoBUb/t/NV2JnNyb/wj9qGdw4pVkXcVbT/kAgVB/0z0NB9/ Rm0jlETTUFnRh7iOXaeLl7O9yAjN2/sGcPSDCxmjKcqmR2+xOV6rIAHI2Xo6F5QcMnSP lesN0A9pJr8TTT1guu0FmG+hTPHDzGXG2ExPSGu/vY+t0+EQVOTrBMHMfYimbSzxlTTy 4tSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zIGcHABe/pzobGUgmxz+iMJPc2gByN1I1kKPS8O7gyo=; b=BzfN6vBOD7VqToUo2IMlTdzsk5oodTScTtZpdY7DIN1A+TsnwxcxLpCDaIf2E7yq24 AMIKMhd4fz3Uk7cYuluY7t5ScJlVguS1IYqF7LopAzLDfnrSlXZYAMJPrWKREDwwDHY+ 3OPcfAhIgz3T+DRVJB4+utGCu8NXVUMkm1Ur0/wxJs8urHRlHoa9MQoj+53MjTdyJvHA TKBXAM6dGXOrF1raARB2jXjkB5LjxpZ2Xt+DI8OcBZugSglIWaynMQ14ZfbNGkvJfou0 7YHFQ+4lUV+r+r25xIrw/+FhMW6U6Oj4yceIr0yETQd3ELu57ykrIQXbKSYgUN2LNfip 0lKg== X-Gm-Message-State: AOAM532FrbqIkb4S6hyR/APCyzxzeRYgOzRDyUe5WW6/ghrl8X6SAjCM ylGpFWJcZ/5GyeX23Y+FbUHj06+nf+FyrRZQ X-Google-Smtp-Source: ABdhPJyukfB+3SFRuzAiI237LOkgI6innDnGe3cLGZf44XBsP+3xUf/dABDEQ6PidWftA3vQwrCGUg== X-Received: by 2002:a7b:c4ca:: with SMTP id g10mr12871021wmk.148.1625847016387; Fri, 09 Jul 2021 09:10:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/17] target/arm: Correct the encoding of MDCCSR_EL0 and DBGDSCRint Date: Fri, 9 Jul 2021 17:10:02 +0100 Message-Id: <20210709161003.25874-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210709161003.25874-1-peter.maydell@linaro.org> References: <20210709161003.25874-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625847801527100001 Content-Type: text/plain; charset="utf-8" From: "hnick@vmware.com" Signed-off-by: Nick Hudson Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a66c1f0b9eb..910ace42741 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6326,11 +6326,21 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tda, .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), .resetvalue =3D 0 }, - /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. + /* + * MDCCSR_EL0[30:29] map to EDSCR[30:29]. Simply RAZ as the external + * Debug Communication Channel is not implemented. + */ + { .name =3D "MDCCSR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 2, .opc1 =3D 3, .crn =3D 0, .crm =3D 1, .opc2 =3D 0, + .access =3D PL0_R, .accessfn =3D access_tda, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + /* + * DBGDSCRint[15,12,5:2] map to MDSCR_EL1[15,12,5:2]. Map all bits as + * it is unlikely a guest will care. * We don't implement the configurable EL0 access. */ - { .name =3D "MDCCSR_EL0", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 = =3D 0, + { .name =3D "DBGDSCRint", .state =3D ARM_CP_STATE_AA32, + .cp =3D 14, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D 0, .type =3D ARM_CP_ALIAS, .access =3D PL1_R, .accessfn =3D access_tda, .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), }, --=20 2.20.1 From nobody Thu Dec 18 22:18:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625847628; cv=none; d=zohomail.com; s=zohoarc; b=f7RzUEcSiOinOfJL6ZXnCMjHGoSGgCVOJCGelW1bOjL12qIqLyPaB/NrJSPd3xdrVpHNywr6YSn7gEpY2lDUmyorjIDgsqj8dQXXOGNTImh7taDmUexriAI/veam8qhG9eGLtlJeisQGM+hGL0o3KDYhn/32y1N3UpFCrQ93xqo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625847628; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Mv7J+7tjraCJlq85GUy80KHgiJAGBqDRnv9zd0CWMwk=; b=GvcIP+n+9IBI6nOx2OendpgNMB7SSfImLabWkESclGrSN7jynZao0AsNxDULJZ/7g+kfQkzLw70RdhGqr5OjEXkXweYAt66Ykm9kGSneHLeiCxj9/08YI+oH4YGlYLRUROssgpmp7ereBMNkdCUfcJAptwTOpX2UlqPnOs5DjN0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1625847628402562.4966199537668; Fri, 9 Jul 2021 09:20:28 -0700 (PDT) Received: from localhost ([::1]:54464 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m1tEo-00055U-42 for importer@patchew.org; Fri, 09 Jul 2021 12:20:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37660) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m1t58-0001dt-GG for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:26 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:37681) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1m1t50-0000yq-L1 for qemu-devel@nongnu.org; Fri, 09 Jul 2021 12:10:26 -0400 Received: by mail-wm1-x32d.google.com with SMTP id y21-20020a7bc1950000b02902161fccabf1so6211831wmi.2 for ; Fri, 09 Jul 2021 09:10:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id x19sm5232277wmi.10.2021.07.09.09.10.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Jul 2021 09:10:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Mv7J+7tjraCJlq85GUy80KHgiJAGBqDRnv9zd0CWMwk=; b=zYpYSv16odZT0psg1mjURzbnkoKy+nl7zlfS0M1X8OPh2hNQ688aM7Aa+EhqAdfmNG WZg6kSWSGFqZJfZPhJsHCxMDyGP5BZlkfR7OtZ+8KMHzGf/ShqKQy1UA9/N6+EbqDovq v2PC6pE3qOqOwisBDBIXrTuknXYeNxvLqmiataP4u6ph1y4Qp3T0Q1tP/XFpw53B84FK UUQXCH1U4l6dSrIM2IkrfXcKRRJc3n4wFD2dAtr28+QL+KsOv9zhmt4+b8yBt4YeP/Zj PU+EcMsYsYxccLeW8rFxyev8+4fzcRu5zDGaG9aiYo2xSaZa3Eg8E83kxT2uczkZnMy4 mauw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Mv7J+7tjraCJlq85GUy80KHgiJAGBqDRnv9zd0CWMwk=; b=H8NDPjm1x+1qjyEHRA5hKNZkfEsKonbGWMbZmhPUxl7Zycu4BUaoenrIj+3D5mxjqC X4p7NZMNwKEwuLtVtNnUdtgR/MbFnBwpaF1I6e1iObZZ6CXf6a155E2c+Z00IKeXXowC WrL6hhk5IrQ9WpfUimU5b75zZz09rLp9CcPk2BgUdmqoToF4wJVZeoKjubgtl+JezFUq gPPDI0EMvhOl/LstZ0dn3R8ey47Itgds/8PMH0I6NlQIA+T6lDJl01c+kxTO254dGV0x SC/KBGwz9J+j0k77//xDMejXgCmcRw62Mll4P2J33tyXizDW4p2l9l3LTYhXkk4EzF9I DzLA== X-Gm-Message-State: AOAM533C1ZakY11272zySvTVY2N1L3blsb+gqFqnV3WsO4mlkT9+RnmV 6Sls7GL93ZL0re/DNKmNeEflEbcxEmQy41Yr X-Google-Smtp-Source: ABdhPJxkNKK1Gbgfw09N8Xq5jb0glH5M76AUCyltkngrbdPbG+w7T9o6MK6sVj76Pjwy5y8tWViBkQ== X-Received: by 2002:a05:600c:224a:: with SMTP id a10mr12973050wmm.7.1625847017044; Fri, 09 Jul 2021 09:10:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/17] hw/intc: Improve formatting of MEMTX_ERROR guest error message Date: Fri, 9 Jul 2021 17:10:03 +0100 Message-Id: <20210709161003.25874-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210709161003.25874-1-peter.maydell@linaro.org> References: <20210709161003.25874-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625847630506100001 From: Rebecca Cran Add a space in the message printed when gicr_read*/gicr_write* returns MEMTX_ERROR in arm_gicv3_redist.c. Signed-off-by: Rebecca Cran Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210706211432.31902-1-rebecca@nuviainc.com Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_redist.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index 8645220d618..53da703ed84 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -453,7 +453,7 @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offs= et, uint64_t *data, if (r =3D=3D MEMTX_ERROR) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest read at offset " TARGET_FMT_plx - "size %u\n", __func__, offset, size); + " size %u\n", __func__, offset, size); trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset, size, attrs.secure); /* The spec requires that reserved registers are RAZ/WI; @@ -510,7 +510,7 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr off= set, uint64_t data, if (r =3D=3D MEMTX_ERROR) { qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write at offset " TARGET_FMT_plx - "size %u\n", __func__, offset, size); + " size %u\n", __func__, offset, size); trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data, size, attrs.secure); /* The spec requires that reserved registers are RAZ/WI; --=20 2.20.1