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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1625806303215100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvf.c.inc | 131 +++++++++--------------- 1 file changed, 49 insertions(+), 82 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index 89f78701e7..ff8e942199 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -27,14 +27,23 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - tcg_gen_addi_tl(t0, t0, a->imm); =20 - tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL); - gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); + TCGv addr =3D gpr_src(ctx, a->rs1); + TCGv temp =3D NULL; =20 - tcg_temp_free(t0); + if (a->imm) { + temp =3D tcg_temp_new(); + tcg_gen_addi_tl(temp, addr, a->imm); + addr =3D temp; + } + + TCGv_i64 dest =3D cpu_fpr[a->rd]; + tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL); + gen_nanbox_s(dest, dest); + + if (temp) { + tcg_temp_free(temp); + } mark_fs_dirty(ctx); return true; } @@ -43,14 +52,21 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); =20 - tcg_gen_addi_tl(t0, t0, a->imm); + TCGv addr =3D gpr_src(ctx, a->rs1); + TCGv temp =3D NULL; =20 - tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL); + if (a->imm) { + temp =3D tcg_temp_new(); + tcg_gen_addi_tl(temp, addr, a->imm); + addr =3D temp; + } =20 - tcg_temp_free(t0); + tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL); + + if (temp) { + tcg_temp_free(temp); + } return true; } =20 @@ -271,12 +287,8 @@ static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt= _w_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); gen_set_rm(ctx, a->rm); - gen_helper_fcvt_w_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - + gen_helper_fcvt_w_s(gpr_dst(ctx, a->rd), cpu_env, cpu_fpr[a->rs1]); return true; } =20 @@ -285,12 +297,8 @@ static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcv= t_wu_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); gen_set_rm(ctx, a->rm); - gen_helper_fcvt_wu_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - + gen_helper_fcvt_wu_s(gpr_dst(ctx, a->rd), cpu_env, cpu_fpr[a->rs1]); return true; } =20 @@ -300,17 +308,14 @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_= x_w *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); + TCGv dest =3D gpr_dst(ctx, a->rd); =20 #if defined(TARGET_RISCV64) - tcg_gen_ext32s_tl(t0, cpu_fpr[a->rs1]); + tcg_gen_ext32s_tl(dest, cpu_fpr[a->rs1]); #else - tcg_gen_extrl_i64_i32(t0, cpu_fpr[a->rs1]); + tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]); #endif =20 - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - return true; } =20 @@ -318,10 +323,9 @@ static bool trans_feq_s(DisasContext *ctx, arg_feq_s *= a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - TCGv t0 =3D tcg_temp_new(); - gen_helper_feq_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); + + gen_helper_feq_s(gpr_dst(ctx, a->rd), cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); return true; } =20 @@ -329,10 +333,9 @@ static bool trans_flt_s(DisasContext *ctx, arg_flt_s *= a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - TCGv t0 =3D tcg_temp_new(); - gen_helper_flt_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); + + gen_helper_flt_s(gpr_dst(ctx, a->rd), cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); return true; } =20 @@ -340,10 +343,9 @@ static bool trans_fle_s(DisasContext *ctx, arg_fle_s *= a) { REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); - TCGv t0 =3D tcg_temp_new(); - gen_helper_fle_s(t0, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); + + gen_helper_fle_s(gpr_dst(ctx, a->rd), cpu_env, + cpu_fpr[a->rs1], cpu_fpr[a->rs2]); return true; } =20 @@ -352,13 +354,7 @@ static bool trans_fclass_s(DisasContext *ctx, arg_fcla= ss_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - - gen_helper_fclass_s(t0, cpu_fpr[a->rs1]); - - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); - + gen_helper_fclass_s(gpr_dst(ctx, a->rd), cpu_fpr[a->rs1]); return true; } =20 @@ -367,15 +363,10 @@ static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcv= t_s_w *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, t0); + gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, gpr_src(ctx, a->rs1)); =20 mark_fs_dirty(ctx); - tcg_temp_free(t0); - return true; } =20 @@ -384,15 +375,10 @@ static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fc= vt_s_wu *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, t0); + gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, gpr_src(ctx, a->rs1)); =20 mark_fs_dirty(ctx); - tcg_temp_free(t0); - return true; } =20 @@ -402,15 +388,10 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_= w_x *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - - tcg_gen_extu_tl_i64(cpu_fpr[a->rd], t0); + tcg_gen_extu_tl_i64(cpu_fpr[a->rd], gpr_src(ctx, a->rs1)); gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); =20 mark_fs_dirty(ctx); - tcg_temp_free(t0); - return true; } =20 @@ -420,11 +401,8 @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcvt= _l_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); gen_set_rm(ctx, a->rm); - gen_helper_fcvt_l_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); + gen_helper_fcvt_l_s(gpr_dst(ctx, a->rd), cpu_env, cpu_fpr[a->rs1]); return true; } =20 @@ -434,11 +412,8 @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fcv= t_lu_s *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); gen_set_rm(ctx, a->rm); - gen_helper_fcvt_lu_s(t0, cpu_env, cpu_fpr[a->rs1]); - gen_set_gpr(a->rd, t0); - tcg_temp_free(t0); + gen_helper_fcvt_lu_s(gpr_dst(ctx, a->rd), cpu_env, cpu_fpr[a->rs1]); return true; } =20 @@ -448,14 +423,10 @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcv= t_s_l *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, t0); + gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, gpr_src(ctx, a->rs1)); =20 mark_fs_dirty(ctx); - tcg_temp_free(t0); return true; } =20 @@ -465,13 +436,9 @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fcv= t_s_lu *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); =20 - TCGv t0 =3D tcg_temp_new(); - gen_get_gpr(t0, a->rs1); - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, t0); + gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, gpr_src(ctx, a->rs1)); =20 mark_fs_dirty(ctx); - tcg_temp_free(t0); return true; } --=20 2.25.1