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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: shorne@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625780395873100001 Content-Type: text/plain; charset="utf-8" The temp allocated for tcg_const_tl is auto-freed at branches, but pure constants are not. So we can remove the extra hoop jumping in trans_l_swa. Signed-off-by: Richard Henderson Reviewed-by: Stafford Horne --- target/openrisc/translate.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 1e437d2f9d..96df513fd3 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -733,12 +733,6 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a) ea =3D tcg_temp_new(); tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i); =20 - /* For TB_FLAGS_R0_0, the branch below invalidates the temporary assig= ned - to cpu_regs[0]. Since l.swa is quite often immediately followed by= a - branch, don't bother reallocating; finish the TB using the "real" R= 0. - This also takes care of RB input across the branch. */ - dc->R0 =3D cpu_regs[0]; - lab_fail =3D gen_new_label(); lab_done =3D gen_new_label(); tcg_gen_brcond_tl(TCG_COND_NE, ea, cpu_lock_addr, lab_fail); @@ -746,7 +740,7 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a) =20 val =3D tcg_temp_new(); tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value, - cpu_regs[a->b], dc->mem_idx, MO_TEUL); + cpu_R(dc, a->b), dc->mem_idx, MO_TEUL); tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value); tcg_temp_free(val); =20 @@ -1602,7 +1596,7 @@ static void openrisc_tr_tb_start(DisasContextBase *db= , CPUState *cs) /* Allow the TCG optimizer to see that R0 =3D=3D 0, when it's true, which is the common case. */ if (dc->tb_flags & TB_FLAGS_R0_0) { - dc->R0 =3D tcg_const_tl(0); + dc->R0 =3D tcg_constant_tl(0); } else { dc->R0 =3D cpu_regs[0]; } --=20 2.25.1