From nobody Tue Feb 10 10:42:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1625521876024523.8344718348856; Mon, 5 Jul 2021 14:51:16 -0700 (PDT) Received: from localhost ([::1]:55980 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m0WUk-00079y-RE for importer@patchew.org; Mon, 05 Jul 2021 17:51:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51418) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m0WTZ-0004wf-HP for qemu-devel@nongnu.org; Mon, 05 Jul 2021 17:50:01 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43364 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m0WTX-0006TQ-AD for qemu-devel@nongnu.org; Mon, 05 Jul 2021 17:50:01 -0400 Received: from host86-179-59-238.range86-179.btcentralplus.com ([86.179.59.238] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1m0WTF-0001ZF-H3; Mon, 05 Jul 2021 22:49:42 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, jasowang@redhat.com, laurent@vivier.eu, fthain@linux-m68k.org, f4bug@amsat.org Date: Mon, 5 Jul 2021 22:49:29 +0100 Message-Id: <20210705214929.17222-5-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210705214929.17222-1-mark.cave-ayland@ilande.co.uk> References: <20210705214929.17222-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.179.59.238 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH 4/4] dp8393x: Rewrite dp8393x_get() / dp8393x_put() X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1625521877445100001 From: Philippe Mathieu-Daud=C3=A9 Instead of accessing N registers via a single address_space API call using a temporary buffer (stored in the device state) and updating each register, move the address_space call in the register put/get. The load/store and word size checks are moved to put/get too. This simplifies a bit, making the code easier to read. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/net/dp8393x.c | 160 +++++++++++++++++++---------------------------- 1 file changed, 63 insertions(+), 97 deletions(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index 22ceea338c..a03f8f0837 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -162,7 +162,6 @@ struct dp8393xState { =20 /* Temporaries */ uint8_t tx_buffer[0x10000]; - uint16_t data[12]; int loopback_packet; =20 /* Memory access */ @@ -219,34 +218,48 @@ static uint32_t dp8393x_wt(dp8393xState *s) return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0]; } =20 -static uint16_t dp8393x_get(dp8393xState *s, int width, int offset) +static uint16_t dp8393x_get(dp8393xState *s, hwaddr addr, int offset) { + const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; uint16_t val; =20 - if (s->big_endian) { - val =3D be16_to_cpu(s->data[offset * width + width - 1]); + if (s->regs[SONIC_DCR] & SONIC_DCR_DW) { + addr +=3D offset << 2; + if (s->big_endian) { + val =3D address_space_ldl_be(&s->as, addr, attrs, NULL); + } else { + val =3D address_space_ldl_le(&s->as, addr, attrs, NULL); + } } else { - val =3D le16_to_cpu(s->data[offset * width]); + addr +=3D offset << 1; + if (s->big_endian) { + val =3D address_space_lduw_be(&s->as, addr, attrs, NULL); + } else { + val =3D address_space_lduw_le(&s->as, addr, attrs, NULL); + } } + return val; } =20 -static void dp8393x_put(dp8393xState *s, int width, int offset, - uint16_t val) +static void dp8393x_put(dp8393xState *s, + hwaddr addr, int offset, uint16_t val) { - if (s->big_endian) { - if (width =3D=3D 2) { - s->data[offset * 2] =3D 0; - s->data[offset * 2 + 1] =3D cpu_to_be16(val); + const MemTxAttrs attrs =3D MEMTXATTRS_UNSPECIFIED; + + if (s->regs[SONIC_DCR] & SONIC_DCR_DW) { + addr +=3D offset << 2; + if (s->big_endian) { + address_space_stl_be(&s->as, addr, val, attrs, NULL); } else { - s->data[offset] =3D cpu_to_be16(val); + address_space_stl_le(&s->as, addr, val, attrs, NULL); } } else { - if (width =3D=3D 2) { - s->data[offset * 2] =3D cpu_to_le16(val); - s->data[offset * 2 + 1] =3D 0; + addr +=3D offset << 1; + if (s->big_endian) { + address_space_stw_be(&s->as, addr, val, attrs, NULL); } else { - s->data[offset] =3D cpu_to_le16(val); + address_space_stw_le(&s->as, addr, val, attrs, NULL); } } } @@ -277,12 +290,10 @@ static void dp8393x_do_load_cam(dp8393xState *s) =20 while (s->regs[SONIC_CDC] & 0x1f) { /* Fill current entry */ - address_space_read(&s->as, dp8393x_cdp(s), - MEMTXATTRS_UNSPECIFIED, s->data, size); - index =3D dp8393x_get(s, width, 0) & 0xf; - s->cam[index][0] =3D dp8393x_get(s, width, 1); - s->cam[index][1] =3D dp8393x_get(s, width, 2); - s->cam[index][2] =3D dp8393x_get(s, width, 3); + index =3D dp8393x_get(s, dp8393x_cdp(s), 0) & 0xf; + s->cam[index][0] =3D dp8393x_get(s, dp8393x_cdp(s), 1); + s->cam[index][1] =3D dp8393x_get(s, dp8393x_cdp(s), 2); + s->cam[index][2] =3D dp8393x_get(s, dp8393x_cdp(s), 3); trace_dp8393x_load_cam(index, s->cam[index][0] >> 8, s->cam[index][0] & 0= xff, s->cam[index][1] >> 8, s->cam[index][1] & 0= xff, @@ -293,9 +304,7 @@ static void dp8393x_do_load_cam(dp8393xState *s) } =20 /* Read CAM enable */ - address_space_read(&s->as, dp8393x_cdp(s), - MEMTXATTRS_UNSPECIFIED, s->data, size); - s->regs[SONIC_CE] =3D dp8393x_get(s, width, 0); + s->regs[SONIC_CE] =3D dp8393x_get(s, dp8393x_cdp(s), 0); trace_dp8393x_load_cam_done(s->regs[SONIC_CE]); =20 /* Done */ @@ -311,14 +320,12 @@ static void dp8393x_do_read_rra(dp8393xState *s) /* Read memory */ width =3D (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; size =3D sizeof(uint16_t) * 4 * width; - address_space_read(&s->as, dp8393x_rrp(s), - MEMTXATTRS_UNSPECIFIED, s->data, size); =20 /* Update SONIC registers */ - s->regs[SONIC_CRBA0] =3D dp8393x_get(s, width, 0); - s->regs[SONIC_CRBA1] =3D dp8393x_get(s, width, 1); - s->regs[SONIC_RBWC0] =3D dp8393x_get(s, width, 2); - s->regs[SONIC_RBWC1] =3D dp8393x_get(s, width, 3); + s->regs[SONIC_CRBA0] =3D dp8393x_get(s, dp8393x_rrp(s), 0); + s->regs[SONIC_CRBA1] =3D dp8393x_get(s, dp8393x_rrp(s), 1); + s->regs[SONIC_RBWC0] =3D dp8393x_get(s, dp8393x_rrp(s), 2); + s->regs[SONIC_RBWC1] =3D dp8393x_get(s, dp8393x_rrp(s), 3); trace_dp8393x_read_rra_regs(s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]= ); =20 @@ -414,28 +421,22 @@ static void dp8393x_do_receiver_disable(dp8393xState = *s) static void dp8393x_do_transmit_packets(dp8393xState *s) { NetClientState *nc =3D qemu_get_queue(s->nic); - int width, size; int tx_len, len; uint16_t i; =20 - width =3D (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; - while (1) { /* Read memory */ - size =3D sizeof(uint16_t) * 6 * width; s->regs[SONIC_TTDA] =3D s->regs[SONIC_CTDA]; trace_dp8393x_transmit_packet(dp8393x_ttda(s)); - address_space_read(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * wi= dth, - MEMTXATTRS_UNSPECIFIED, s->data, size); tx_len =3D 0; =20 /* Update registers */ - s->regs[SONIC_TCR] =3D dp8393x_get(s, width, 0) & 0xf000; - s->regs[SONIC_TPS] =3D dp8393x_get(s, width, 1); - s->regs[SONIC_TFC] =3D dp8393x_get(s, width, 2); - s->regs[SONIC_TSA0] =3D dp8393x_get(s, width, 3); - s->regs[SONIC_TSA1] =3D dp8393x_get(s, width, 4); - s->regs[SONIC_TFS] =3D dp8393x_get(s, width, 5); + s->regs[SONIC_TCR] =3D dp8393x_get(s, dp8393x_ttda(s), 1) & 0xf000; + s->regs[SONIC_TPS] =3D dp8393x_get(s, dp8393x_ttda(s), 2); + s->regs[SONIC_TFC] =3D dp8393x_get(s, dp8393x_ttda(s), 3); + s->regs[SONIC_TSA0] =3D dp8393x_get(s, dp8393x_ttda(s), 4); + s->regs[SONIC_TSA1] =3D dp8393x_get(s, dp8393x_ttda(s), 5); + s->regs[SONIC_TFS] =3D dp8393x_get(s, dp8393x_ttda(s), 6); =20 /* Handle programmable interrupt */ if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) { @@ -457,15 +458,12 @@ static void dp8393x_do_transmit_packets(dp8393xState = *s) i++; if (i !=3D s->regs[SONIC_TFC]) { /* Read next fragment details */ - size =3D sizeof(uint16_t) * 3 * width; - address_space_read(&s->as, - dp8393x_ttda(s) - + sizeof(uint16_t) * width * (4 + 3 * i= ), - MEMTXATTRS_UNSPECIFIED, s->data, - size); - s->regs[SONIC_TSA0] =3D dp8393x_get(s, width, 0); - s->regs[SONIC_TSA1] =3D dp8393x_get(s, width, 1); - s->regs[SONIC_TFS] =3D dp8393x_get(s, width, 2); + s->regs[SONIC_TSA0] =3D dp8393x_get(s, dp8393x_ttda(s), + 4 + 3 * i); + s->regs[SONIC_TSA1] =3D dp8393x_get(s, dp8393x_ttda(s), + 5 + 3 * i); + s->regs[SONIC_TFS] =3D dp8393x_get(s, dp8393x_ttda(s), + 6 + 3 * i); } } =20 @@ -498,22 +496,12 @@ static void dp8393x_do_transmit_packets(dp8393xState = *s) s->regs[SONIC_TCR] |=3D SONIC_TCR_PTX; =20 /* Write status */ - dp8393x_put(s, width, 0, - s->regs[SONIC_TCR] & 0x0fff); /* status */ - size =3D sizeof(uint16_t) * width; - address_space_write(&s->as, dp8393x_ttda(s), - MEMTXATTRS_UNSPECIFIED, s->data, size); + dp8393x_put(s, dp8393x_ttda(s), 0, s->regs[SONIC_TCR] & 0x0fff); =20 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { /* Read footer of packet */ - size =3D sizeof(uint16_t) * width; - address_space_read(&s->as, - dp8393x_ttda(s) - + sizeof(uint16_t) * width - * (4 + 3 * s->regs[SONIC_TFC]), - MEMTXATTRS_UNSPECIFIED, s->data, - size); - s->regs[SONIC_CTDA] =3D dp8393x_get(s, width, 0); + s->regs[SONIC_CTDA] =3D dp8393x_get(s, dp8393x_ttda(s), + 4 + 3 * s->regs[SONIC_TFC]); if (s->regs[SONIC_CTDA] & SONIC_DESC_EOL) { /* EOL detected */ break; @@ -765,7 +753,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, cons= t uint8_t * buf, dp8393xState *s =3D qemu_get_nic_opaque(nc); int packet_type; uint32_t available, address; - int width, rx_len, padded_len; + int rx_len, padded_len; uint32_t checksum; int size; =20 @@ -778,10 +766,8 @@ static ssize_t dp8393x_receive(NetClientState *nc, con= st uint8_t * buf, =20 rx_len =3D pkt_size + sizeof(checksum); if (s->regs[SONIC_DCR] & SONIC_DCR_DW) { - width =3D 2; padded_len =3D ((rx_len - 1) | 3) + 1; } else { - width =3D 1; padded_len =3D ((rx_len - 1) | 1) + 1; } =20 @@ -802,11 +788,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, con= st uint8_t * buf, /* Check for EOL */ if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { /* Are we still in resource exhaustion? */ - size =3D sizeof(uint16_t) * 1 * width; - address =3D dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; - address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED, - s->data, size); - s->regs[SONIC_LLFA] =3D dp8393x_get(s, width, 0); + s->regs[SONIC_LLFA] =3D dp8393x_get(s, dp8393x_crda(s), 5); if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { /* Still EOL ; stop reception */ return -1; @@ -814,11 +796,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, con= st uint8_t * buf, /* Link has been updated by host */ =20 /* Clear in_use */ - size =3D sizeof(uint16_t) * width; - address =3D dp8393x_crda(s) + sizeof(uint16_t) * 6 * width; - dp8393x_put(s, width, 0, 0); - address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, - (uint8_t *)s->data, size); + dp8393x_put(s, dp8393x_crda(s), 6, 0x0000); =20 /* Move to next descriptor */ s->regs[SONIC_CRDA] =3D s->regs[SONIC_LLFA]; @@ -872,32 +850,20 @@ static ssize_t dp8393x_receive(NetClientState *nc, co= nst uint8_t * buf, =20 /* Write status to memory */ trace_dp8393x_receive_write_status(dp8393x_crda(s)); - dp8393x_put(s, width, 0, s->regs[SONIC_RCR]); /* status */ - dp8393x_put(s, width, 1, rx_len); /* byte count */ - dp8393x_put(s, width, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */ - dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */ - dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */ - size =3D sizeof(uint16_t) * 5 * width; - address_space_write(&s->as, dp8393x_crda(s), - MEMTXATTRS_UNSPECIFIED, - s->data, size); + dp8393x_put(s, dp8393x_crda(s), 0, s->regs[SONIC_RCR]); /* status */ + dp8393x_put(s, dp8393x_crda(s), 1, rx_len); /* byte count */ + dp8393x_put(s, dp8393x_crda(s), 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 = */ + dp8393x_put(s, dp8393x_crda(s), 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 = */ + dp8393x_put(s, dp8393x_crda(s), 4, s->regs[SONIC_RSC]); /* seq_no */ =20 /* Check link field */ - size =3D sizeof(uint16_t) * width; - address_space_read(&s->as, - dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, - MEMTXATTRS_UNSPECIFIED, s->data, size); - s->regs[SONIC_LLFA] =3D dp8393x_get(s, width, 0); + s->regs[SONIC_LLFA] =3D dp8393x_get(s, dp8393x_crda(s), 5); if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { /* EOL detected */ s->regs[SONIC_ISR] |=3D SONIC_ISR_RDE; } else { /* Clear in_use */ - size =3D sizeof(uint16_t) * width; - address =3D dp8393x_crda(s) + sizeof(uint16_t) * 6 * width; - dp8393x_put(s, width, 0, 0); - address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, - s->data, size); + dp8393x_put(s, dp8393x_crda(s), 6, 0x0000); =20 /* Move to next descriptor */ s->regs[SONIC_CRDA] =3D s->regs[SONIC_LLFA]; --=20 2.20.1