From nobody Wed Feb 11 00:55:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1625521937158323.75871973248127; Mon, 5 Jul 2021 14:52:17 -0700 (PDT) Received: from localhost ([::1]:60530 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1m0WVk-0001jM-4a for importer@patchew.org; Mon, 05 Jul 2021 17:52:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51408) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m0WTY-0004so-2t for qemu-devel@nongnu.org; Mon, 05 Jul 2021 17:50:00 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:43358 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1m0WTW-0006Sp-Ff for qemu-devel@nongnu.org; Mon, 05 Jul 2021 17:49:59 -0400 Received: from host86-179-59-238.range86-179.btcentralplus.com ([86.179.59.238] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1m0WTB-0001ZF-7u; Mon, 05 Jul 2021 22:49:41 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, jasowang@redhat.com, laurent@vivier.eu, fthain@linux-m68k.org, f4bug@amsat.org Date: Mon, 5 Jul 2021 22:49:28 +0100 Message-Id: <20210705214929.17222-4-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210705214929.17222-1-mark.cave-ayland@ilande.co.uk> References: <20210705214929.17222-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 86.179.59.238 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH 3/4] dp8393x: Store CAM registers as 16-bit X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1625521938236100003 From: Philippe Mathieu-Daud=C3=A9 Per the DP83932C datasheet from July 1995: 4.0 SONIC Registers 4.1 THE CAM UNIT The Content Addressable Memory (CAM) consists of sixteen 48-bit entries for complete address filtering of network packets. Each entry corresponds to a 48-bit destination address that is user programmable and can contain any combination of Multicast or Physical addresses. Each entry is partitioned into three 16-bit CAM cells accessible through CAM Address Ports (CAP 2, CAP 1 and CAP 0) with CAP0 corresponding to the least significant 16 bits of the Destination Address and CAP2 corresponding to the most significant bits. Store the CAM registers as 16-bit as it simplifies the code. There is no change in the migration stream. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/net/dp8393x.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index cc7c001edb..22ceea338c 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -157,7 +157,7 @@ struct dp8393xState { MemoryRegion mmio; =20 /* Registers */ - uint8_t cam[16][6]; + uint16_t cam[16][3]; uint16_t regs[0x40]; =20 /* Temporaries */ @@ -280,15 +280,13 @@ static void dp8393x_do_load_cam(dp8393xState *s) address_space_read(&s->as, dp8393x_cdp(s), MEMTXATTRS_UNSPECIFIED, s->data, size); index =3D dp8393x_get(s, width, 0) & 0xf; - s->cam[index][0] =3D dp8393x_get(s, width, 1) & 0xff; - s->cam[index][1] =3D dp8393x_get(s, width, 1) >> 8; - s->cam[index][2] =3D dp8393x_get(s, width, 2) & 0xff; - s->cam[index][3] =3D dp8393x_get(s, width, 2) >> 8; - s->cam[index][4] =3D dp8393x_get(s, width, 3) & 0xff; - s->cam[index][5] =3D dp8393x_get(s, width, 3) >> 8; - trace_dp8393x_load_cam(index, s->cam[index][0], s->cam[index][1], - s->cam[index][2], s->cam[index][3], - s->cam[index][4], s->cam[index][5]); + s->cam[index][0] =3D dp8393x_get(s, width, 1); + s->cam[index][1] =3D dp8393x_get(s, width, 2); + s->cam[index][2] =3D dp8393x_get(s, width, 3); + trace_dp8393x_load_cam(index, + s->cam[index][0] >> 8, s->cam[index][0] & 0= xff, + s->cam[index][1] >> 8, s->cam[index][1] & 0= xff, + s->cam[index][2] >> 8, s->cam[index][2] & 0= xff); /* Move to next entry */ s->regs[SONIC_CDC]--; s->regs[SONIC_CDP] +=3D size; @@ -591,8 +589,7 @@ static uint64_t dp8393x_read(void *opaque, hwaddr addr,= unsigned int size) case SONIC_CAP1: case SONIC_CAP0: if (s->regs[SONIC_CR] & SONIC_CR_RST) { - val =3D s->cam[s->regs[SONIC_CEP] & 0xf][2 * (SONIC_CAP0 - reg= ) + 1] << 8; - val |=3D s->cam[s->regs[SONIC_CEP] & 0xf][2 * (SONIC_CAP0 - re= g)]; + val =3D s->cam[s->regs[SONIC_CEP] & 0xf][2 * (SONIC_CAP0 - reg= )]; } break; /* All other registers have no special contraints */ @@ -990,7 +987,7 @@ static const VMStateDescription vmstate_dp8393x =3D { .version_id =3D 0, .minimum_version_id =3D 0, .fields =3D (VMStateField []) { - VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6), + VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 3 * 2), VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40), VMSTATE_END_OF_LIST() } --=20 2.20.1