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[92.184.108.23]) by smtp.gmail.com with ESMTPSA id 12sm13818781wme.28.2021.07.02.06.36.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 06:36:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6SjNTNzzmhwEPVZj6BseAgSSsGle0gDtK79Bw/VO9BM=; b=qLcaIT6ez1LLeRUhcFFHNmBAGy3IgyPTHV5AHk/0THkgLGh5tMP8+1ao0gLAX/eXFN /J6WvTwnAuUILnQdS2OZXZQFsKKDaFPyuel7NGsJOosphFgD+r5pfhLeb6tPiV4Z3dnB j/d8ljvI451K0BNeWMjO9xNilLVcUxmPdYAF7vvxxaWckwfSLZbqXpowiudJUUookw1J gIjkuNvstpZrPa1GjlEr0zZMt45Jdr1TgL/G6MpveGNLbMggRE6CMFCm7fEWOTdl1Dst 7I6d55UZBeAufXY1cnA5VgHgo6kIhoRlN/cDN9HitP7P3BQeR+7u2uO4YrF4g2OEnnN9 2BxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=6SjNTNzzmhwEPVZj6BseAgSSsGle0gDtK79Bw/VO9BM=; b=fI0apWHfeZo7T+UbduUu86acRWnO1/ZznbUEYvt1BB4kP5u/cxuLpR1XE7DinfP3FI TWFQrB1vEeVxFy0ZwNJ+1KIza0rUSn7mfj5im8SVSkSXi9sNdz0ThByk0wlCLsirbg6I 4U9lBADtIEbngxdYERjhKMAF/83Q7qrhJy169NsaW/2ZWmv+4Slqy88401QY1xIVxarL arGYemm/ZTLwYICQlugjDjJmAh5mUeK5+aI2LtgUkn13bEXHuL+oUIn8w7Jw138fD5p4 wSOOiXcF66XKEMJgO+4D4Ub/q38PF4tV54UoHsknVPsWT4Wdy485qfxY/+vZmqpeW1Mh INTA== X-Gm-Message-State: AOAM531qRE1CwzvksrJLQ0lD0XpGaylUSHXYB1HUAC8pxm1v2iNrWBhI PhbynOCeeP9FJpkCz918Hvk= X-Google-Smtp-Source: ABdhPJw6d8jE9xJfuhvSOPUKaDYl1J0qM8JABqzy0N4k6eRpKKcvrK09h5dtF+tA60i5ORokrv+cDA== X-Received: by 2002:a5d:4f05:: with SMTP id c5mr5927418wru.362.1625232997916; Fri, 02 Jul 2021 06:36:37 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , BALATON Zoltan , Jiaxun Yang Subject: [PULL 06/18] hw/pci-host/bonito: Allow PCI config accesses smaller than 32-bit Date: Fri, 2 Jul 2021 15:35:45 +0200 Message-Id: <20210702133557.60317-7-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210702133557.60317-1-f4bug@amsat.org> References: <20210702133557.60317-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1625233000864100001 When running the official PMON firmware for the Fuloong 2E, we see 8-bit and 16-bit accesses to PCI config space: $ qemu-system-mips64el -M fuloong2e -bios pmon_2e.bin \ -trace -trace bonito\* -trace pci_cfg\* pci_cfg_write vt82c686b-pm 05:4 @0x90 <- 0xeee1 bonito_spciconf_small_access PCI config address is smaller then 32-bit, a= ddr: 0x4d2, size: 2 pci_cfg_write vt82c686b-pm 05:4 @0xd2 <- 0x1 pci_cfg_write vt82c686b-pm 05:4 @0x4 <- 0x1 pci_cfg_write vt82c686b-isa 05:0 @0x4 <- 0x7 bonito_spciconf_small_access PCI config address is smaller then 32-bit, a= ddr: 0x81, size: 1 pci_cfg_read vt82c686b-isa 05:0 @0x81 -> 0x0 bonito_spciconf_small_access PCI config address is smaller then 32-bit, a= ddr: 0x81, size: 1 pci_cfg_write vt82c686b-isa 05:0 @0x81 <- 0x80 bonito_spciconf_small_access PCI config address is smaller then 32-bit, a= ddr: 0x83, size: 1 pci_cfg_write vt82c686b-isa 05:0 @0x83 <- 0x89 bonito_spciconf_small_access PCI config address is smaller then 32-bit, a= ddr: 0x85, size: 1 pci_cfg_write vt82c686b-isa 05:0 @0x85 <- 0x3 bonito_spciconf_small_access PCI config address is smaller then 32-bit, a= ddr: 0x5a, size: 1 pci_cfg_write vt82c686b-isa 05:0 @0x5a <- 0x7 bonito_spciconf_small_access PCI config address is smaller then 32-bit, a= ddr: 0x85, size: 1 pci_cfg_write vt82c686b-isa 05:0 @0x85 <- 0x1 Also this is what the Linux kernel does since it supports the Bonito north bridge: https://elixir.bootlin.com/linux/v2.6.15/source/arch/mips/pci/ops-bonito64.= c#L85 So it seems safe to assume the datasheet is incomplete or outdated regarding the address constraints. This problem was exposed by commit 911629e6d3773a8adeab48b ("vt82c686: Fix SMBus IO base and configuration registers"). Reported-by: BALATON Zoltan Suggested-by: Jiaxun Yang Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210624202747.1433023-4-f4bug@amsat.org> Tested-by: BALATON Zoltan --- hw/pci-host/bonito.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c index 751fdcec689..a57e81e3a97 100644 --- a/hw/pci-host/bonito.c +++ b/hw/pci-host/bonito.c @@ -187,7 +187,7 @@ FIELD(BONGENCFG, PCIQUEUE, 12, 1) #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */ #define BONITO_PCICONF_FUN_OFFSET 8 #define BONITO_PCICONF_REG_MASK_DS (~3) /* Per datasheet */ -#define BONITO_PCICONF_REG_MASK 0xFC +#define BONITO_PCICONF_REG_MASK_HW 0xff /* As seen running PMO= N */ #define BONITO_PCICONF_REG_OFFSET 0 =20 =20 @@ -466,7 +466,7 @@ static uint32_t bonito_sbridge_pciaddr(void *opaque, hw= addr addr) BONITO_PCICONF_IDSEL_OFFSET; devno =3D ctz32(idsel); funno =3D (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OF= FSET; - regno =3D (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OF= FSET; + regno =3D (cfgaddr & BONITO_PCICONF_REG_MASK_HW) >> BONITO_PCICONF_REG= _OFFSET; =20 if (idsel =3D=3D 0) { error_report("error in bonito pci config address 0x" TARGET_FMT_plx --=20 2.31.1