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[92.184.108.23]) by smtp.gmail.com with ESMTPSA id d12sm3387976wri.77.2021.07.02.06.36.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 06:36:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G063yAbshkplc+JBOrHG+Ax7yPLtkUG8hisGeshfJgs=; b=rVYnxLJvj+CRV+aLRw2XbY13b2IHV76ePZzyEsxpP1KAQVNr3Z58Is3Vi+eeSCIDiX CAX+9RaX3S7Jxfe0QMx3pJxV4L5rbueiGUCAcs7H+YCdqUE+MYKCwtO0W5CGILWG86e4 O+fQtvpkMrRaJ1kePxipnOaEWaGYOWGj5OUNlREBgmDYon/dyHCdhNuIRD2PMReuFjol SZZwYYTa2zKnDh7XsQyoXh2agXED2ZJ3iG+J87bXqwtJNFf5DxQSsEpF6M0HdRwTk0Z7 6MF+N7ylTy56gyklWVJypJtDIQqNY6+oAK5ZcMpTw7ZAuXj+d9rM3bVy/jk7nuE237dh zJkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=G063yAbshkplc+JBOrHG+Ax7yPLtkUG8hisGeshfJgs=; b=YPcedTsXEiE6LNLneAm3Xhs69W14VZIuDXlS+VVpi4UaZZlTH4Eo4sXmcwaZ2TNdVv zouJEJlvzeJbj2ePgO8olOSsbqm/h4QgWZfSNKb0AEv28puk2d4zJhpN5tRFYjsc0+01 +1bp0ASg7PsVdMGYFLsvwUxjmM5DSKA0+0YCKOknK5ZpwkwtFsSnno5YQKX12Kxc1sWE YN7InQOuPiQi8Yhi5lb9qhjmucTS9jsUbVgq7lfTu82fZtSezzXz72pGe1OYjhW3IFPI CDMhYxuBzczYW95pb5lgyZ2d/67cUTHRAxoBS53HKhqEsgLu24EHWvwi6VAOd0laBSNX Bnaw== X-Gm-Message-State: AOAM5331u0yTeI/NQMIHCJtnbtRz9NH3DI8ouHySkJk4wiYvHCU5i4Fo 0Y7hWnmufNu3cb7kTTybtNo= X-Google-Smtp-Source: ABdhPJzPwFqXMJjKM0+/eaADA4cqC+lT+inZOiK7mxeQgViv88zx/sVHOXgNMys0UYCGe/t38PQwXQ== X-Received: by 2002:adf:f68f:: with SMTP id v15mr5998955wrp.291.1625233017494; Fri, 02 Jul 2021 06:36:57 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Finn Thain Subject: [PULL 10/18] dp8393x: checkpatch fixes Date: Fri, 2 Jul 2021 15:35:49 +0200 Message-Id: <20210702133557.60317-11-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210702133557.60317-1-f4bug@amsat.org> References: <20210702133557.60317-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1625233021361100001 From: Mark Cave-Ayland Also fix a simple comment typo of "constrainst" to "constraints". Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Finn Thain Message-Id: <20210625065401.30170-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/net/dp8393x.c | 231 +++++++++++++++++++++++++---------------------- 1 file changed, 122 insertions(+), 109 deletions(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index 533a8304d0b..56af08f0fe5 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -29,14 +29,14 @@ #include #include "qom/object.h" =20 -//#define DEBUG_SONIC +/* #define DEBUG_SONIC */ =20 #define SONIC_PROM_SIZE 0x1000 =20 #ifdef DEBUG_SONIC #define DPRINTF(fmt, ...) \ do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0) -static const char* reg_names[] =3D { +static const char *reg_names[] =3D { "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA", "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0", "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP", @@ -185,7 +185,8 @@ struct dp8393xState { AddressSpace as; }; =20 -/* Accessor functions for values which are formed by +/* + * Accessor functions for values which are formed by * concatenating two 16 bit device registers. By putting these * in their own functions with a uint32_t return type we avoid the * pitfall of implicit sign extension where ((x << 16) | y) is a @@ -350,8 +351,7 @@ static void dp8393x_do_read_rra(dp8393xState *s) } =20 /* Warn the host if CRBA now has the last available resource */ - if (s->regs[SONIC_RRP] =3D=3D s->regs[SONIC_RWP]) - { + if (s->regs[SONIC_RRP] =3D=3D s->regs[SONIC_RWP]) { s->regs[SONIC_ISR] |=3D SONIC_ISR_RBE; dp8393x_update_irq(s); } @@ -364,7 +364,8 @@ static void dp8393x_do_software_reset(dp8393xState *s) { timer_del(s->watchdog); =20 - s->regs[SONIC_CR] &=3D ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP = | SONIC_CR_HTX); + s->regs[SONIC_CR] &=3D ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | + SONIC_CR_HTX); s->regs[SONIC_CR] |=3D SONIC_CR_RST | SONIC_CR_RXDIS; } =20 @@ -490,8 +491,10 @@ static void dp8393x_do_transmit_packets(dp8393xState *= s) =20 /* Handle Ethernet checksum */ if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) { - /* Don't append FCS there, to look like slirp packets - * which don't have one */ + /* + * Don't append FCS there, to look like slirp packets + * which don't have one + */ } else { /* Remove existing FCS */ tx_len -=3D 4; @@ -558,26 +561,34 @@ static void dp8393x_do_command(dp8393xState *s, uint1= 6_t command) =20 s->regs[SONIC_CR] |=3D (command & SONIC_CR_MASK); =20 - if (command & SONIC_CR_HTX) + if (command & SONIC_CR_HTX) { dp8393x_do_halt_transmission(s); - if (command & SONIC_CR_TXP) + } + if (command & SONIC_CR_TXP) { dp8393x_do_transmit_packets(s); - if (command & SONIC_CR_RXDIS) + } + if (command & SONIC_CR_RXDIS) { dp8393x_do_receiver_disable(s); - if (command & SONIC_CR_RXEN) + } + if (command & SONIC_CR_RXEN) { dp8393x_do_receiver_enable(s); - if (command & SONIC_CR_STP) + } + if (command & SONIC_CR_STP) { dp8393x_do_stop_timer(s); - if (command & SONIC_CR_ST) + } + if (command & SONIC_CR_ST) { dp8393x_do_start_timer(s); - if (command & SONIC_CR_RST) + } + if (command & SONIC_CR_RST) { dp8393x_do_software_reset(s); + } if (command & SONIC_CR_RRRA) { dp8393x_do_read_rra(s); s->regs[SONIC_CR] &=3D ~SONIC_CR_RRRA; } - if (command & SONIC_CR_LCAM) + if (command & SONIC_CR_LCAM) { dp8393x_do_load_cam(s); + } } =20 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size) @@ -587,24 +598,24 @@ static uint64_t dp8393x_read(void *opaque, hwaddr add= r, unsigned int size) uint16_t val =3D 0; =20 switch (reg) { - /* Update data before reading it */ - case SONIC_WT0: - case SONIC_WT1: - dp8393x_update_wt_regs(s); - val =3D s->regs[reg]; - break; - /* Accept read to some registers only when in reset mode */ - case SONIC_CAP2: - case SONIC_CAP1: - case SONIC_CAP0: - if (s->regs[SONIC_CR] & SONIC_CR_RST) { - val =3D s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - = reg) + 1] << 8; - val |=3D s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 -= reg)]; - } - break; - /* All other registers have no special contrainst */ - default: - val =3D s->regs[reg]; + /* Update data before reading it */ + case SONIC_WT0: + case SONIC_WT1: + dp8393x_update_wt_regs(s); + val =3D s->regs[reg]; + break; + /* Accept read to some registers only when in reset mode */ + case SONIC_CAP2: + case SONIC_CAP1: + case SONIC_CAP0: + if (s->regs[SONIC_CR] & SONIC_CR_RST) { + val =3D s->cam[s->regs[SONIC_CEP] & 0xf][2 * (SONIC_CAP0 - reg= ) + 1] << 8; + val |=3D s->cam[s->regs[SONIC_CEP] & 0xf][2 * (SONIC_CAP0 - re= g)]; + } + break; + /* All other registers have no special contraints */ + default: + val =3D s->regs[reg]; } =20 DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]); @@ -622,75 +633,75 @@ static void dp8393x_write(void *opaque, hwaddr addr, = uint64_t data, DPRINTF("write 0x%04x to reg %s\n", (uint16_t)val, reg_names[reg]); =20 switch (reg) { - /* Command register */ - case SONIC_CR: - dp8393x_do_command(s, val); - break; - /* Prevent write to read-only registers */ - case SONIC_CAP2: - case SONIC_CAP1: - case SONIC_CAP0: - case SONIC_SR: - case SONIC_MDT: - DPRINTF("writing to reg %d invalid\n", reg); - break; - /* Accept write to some registers only when in reset mode */ - case SONIC_DCR: - if (s->regs[SONIC_CR] & SONIC_CR_RST) { - s->regs[reg] =3D val & 0xbfff; - } else { - DPRINTF("writing to DCR invalid\n"); - } - break; - case SONIC_DCR2: - if (s->regs[SONIC_CR] & SONIC_CR_RST) { - s->regs[reg] =3D val & 0xf017; - } else { - DPRINTF("writing to DCR2 invalid\n"); - } - break; - /* 12 lower bytes are Read Only */ - case SONIC_TCR: - s->regs[reg] =3D val & 0xf000; - break; - /* 9 lower bytes are Read Only */ - case SONIC_RCR: - s->regs[reg] =3D val & 0xffe0; - break; - /* Ignore most significant bit */ - case SONIC_IMR: - s->regs[reg] =3D val & 0x7fff; - dp8393x_update_irq(s); - break; - /* Clear bits by writing 1 to them */ - case SONIC_ISR: - val &=3D s->regs[reg]; - s->regs[reg] &=3D ~val; - if (val & SONIC_ISR_RBE) { - dp8393x_do_read_rra(s); - } - dp8393x_update_irq(s); - break; - /* The guest is required to store aligned pointers here */ - case SONIC_RSA: - case SONIC_REA: - case SONIC_RRP: - case SONIC_RWP: - if (s->regs[SONIC_DCR] & SONIC_DCR_DW) { - s->regs[reg] =3D val & 0xfffc; - } else { - s->regs[reg] =3D val & 0xfffe; - } - break; - /* Invert written value for some registers */ - case SONIC_CRCT: - case SONIC_FAET: - case SONIC_MPT: - s->regs[reg] =3D val ^ 0xffff; - break; - /* All other registers have no special contrainst */ - default: - s->regs[reg] =3D val; + /* Command register */ + case SONIC_CR: + dp8393x_do_command(s, val); + break; + /* Prevent write to read-only registers */ + case SONIC_CAP2: + case SONIC_CAP1: + case SONIC_CAP0: + case SONIC_SR: + case SONIC_MDT: + DPRINTF("writing to reg %d invalid\n", reg); + break; + /* Accept write to some registers only when in reset mode */ + case SONIC_DCR: + if (s->regs[SONIC_CR] & SONIC_CR_RST) { + s->regs[reg] =3D val & 0xbfff; + } else { + DPRINTF("writing to DCR invalid\n"); + } + break; + case SONIC_DCR2: + if (s->regs[SONIC_CR] & SONIC_CR_RST) { + s->regs[reg] =3D val & 0xf017; + } else { + DPRINTF("writing to DCR2 invalid\n"); + } + break; + /* 12 lower bytes are Read Only */ + case SONIC_TCR: + s->regs[reg] =3D val & 0xf000; + break; + /* 9 lower bytes are Read Only */ + case SONIC_RCR: + s->regs[reg] =3D val & 0xffe0; + break; + /* Ignore most significant bit */ + case SONIC_IMR: + s->regs[reg] =3D val & 0x7fff; + dp8393x_update_irq(s); + break; + /* Clear bits by writing 1 to them */ + case SONIC_ISR: + val &=3D s->regs[reg]; + s->regs[reg] &=3D ~val; + if (val & SONIC_ISR_RBE) { + dp8393x_do_read_rra(s); + } + dp8393x_update_irq(s); + break; + /* The guest is required to store aligned pointers here */ + case SONIC_RSA: + case SONIC_REA: + case SONIC_RRP: + case SONIC_RWP: + if (s->regs[SONIC_DCR] & SONIC_DCR_DW) { + s->regs[reg] =3D val & 0xfffc; + } else { + s->regs[reg] =3D val & 0xfffe; + } + break; + /* Invert written value for some registers */ + case SONIC_CRCT: + case SONIC_FAET: + case SONIC_MPT: + s->regs[reg] =3D val ^ 0xffff; + break; + /* All other registers have no special contrainst */ + default: + s->regs[reg] =3D val; } =20 if (reg =3D=3D SONIC_WT0 || reg =3D=3D SONIC_WT1) { @@ -747,17 +758,18 @@ static int dp8393x_receive_filter(dp8393xState *s, co= nst uint8_t * buf, } =20 /* Check broadcast */ - if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof= (bcast))) { + if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && + !memcmp(buf, bcast, sizeof(bcast))) { return SONIC_RCR_BC; } =20 /* Check CAM */ for (i =3D 0; i < 16; i++) { if (s->regs[SONIC_CE] & (1 << i)) { - /* Entry enabled */ - if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) { - return 0; - } + /* Entry enabled */ + if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) { + return 0; + } } } =20 @@ -938,7 +950,8 @@ static void dp8393x_reset(DeviceState *dev) s->regs[SONIC_SR] =3D 0x0004; /* only revision recognized by Linux/mip= s */ s->regs[SONIC_CR] =3D SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS; s->regs[SONIC_DCR] &=3D ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR); - s->regs[SONIC_RCR] &=3D ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BR= D | SONIC_RCR_RNT); + s->regs[SONIC_RCR] &=3D ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BR= D | + SONIC_RCR_RNT); s->regs[SONIC_TCR] |=3D SONIC_TCR_NCRS | SONIC_TCR_PTX; s->regs[SONIC_TCR] &=3D ~SONIC_TCR_BCM; s->regs[SONIC_IMR] =3D 0; --=20 2.31.1