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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 10/24] target/arm: Use asimd_imm_const for A64 decode
Date: Fri, 2 Jul 2021 13:59:40 +0100
Message-Id: <20210702125954.13247-11-peter.maydell@linaro.org>
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The A64 AdvSIMD modified-immediate grouping uses almost the same
constant encoding that A32 Neon does; reuse asimd_imm_const() (to
which we add the AArch64-specific case for cmode 15 op 1) instead of
reimplementing it all.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210628135835.6690-5-peter.maydell@linaro.org
---
target/arm/translate.h | 3 +-
target/arm/translate-a64.c | 86 ++++----------------------------------
target/arm/translate.c | 17 +++++++-
3 files changed, 24 insertions(+), 82 deletions(-)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 6c8d5f6ede1..e2f056c32c2 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -540,7 +540,8 @@ static inline MemOp finalize_memop(DisasContext *s, Mem=
Op opc)
* VMVN and VBIC (when cmode < 14 && op =3D=3D 1).
*
* The combination cmode =3D=3D 15 op =3D=3D 1 is a reserved encoding for =
AArch32;
- * callers must catch this.
+ * callers must catch this; we return the 64-bit constant value defined
+ * for AArch64.
*
* cmode =3D 2,3,4,5,6,7,10,11,12,13 imm=3D0 was UNPREDICTABLE in v7A but
* is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 1a40e49db7f..66781f71cb2 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -8190,8 +8190,6 @@ static void disas_simd_mod_imm(DisasContext *s, uint3=
2_t insn)
{
int rd =3D extract32(insn, 0, 5);
int cmode =3D extract32(insn, 12, 4);
- int cmode_3_1 =3D extract32(cmode, 1, 3);
- int cmode_0 =3D extract32(cmode, 0, 1);
int o2 =3D extract32(insn, 11, 1);
uint64_t abcdefgh =3D extract32(insn, 5, 5) | (extract32(insn, 16, 3) =
<< 5);
bool is_neg =3D extract32(insn, 29, 1);
@@ -8210,83 +8208,13 @@ static void disas_simd_mod_imm(DisasContext *s, uin=
t32_t insn)
return;
}
=20
- /* See AdvSIMDExpandImm() in ARM ARM */
- switch (cmode_3_1) {
- case 0: /* Replicate(Zeros(24):imm8, 2) */
- case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
- case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
- case 3: /* Replicate(imm8:Zeros(24), 2) */
- {
- int shift =3D cmode_3_1 * 8;
- imm =3D bitfield_replicate(abcdefgh << shift, 32);
- break;
- }
- case 4: /* Replicate(Zeros(8):imm8, 4) */
- case 5: /* Replicate(imm8:Zeros(8), 4) */
- {
- int shift =3D (cmode_3_1 & 0x1) * 8;
- imm =3D bitfield_replicate(abcdefgh << shift, 16);
- break;
- }
- case 6:
- if (cmode_0) {
- /* Replicate(Zeros(8):imm8:Ones(16), 2) */
- imm =3D (abcdefgh << 16) | 0xffff;
- } else {
- /* Replicate(Zeros(16):imm8:Ones(8), 2) */
- imm =3D (abcdefgh << 8) | 0xff;
- }
- imm =3D bitfield_replicate(imm, 32);
- break;
- case 7:
- if (!cmode_0 && !is_neg) {
- imm =3D bitfield_replicate(abcdefgh, 8);
- } else if (!cmode_0 && is_neg) {
- int i;
- imm =3D 0;
- for (i =3D 0; i < 8; i++) {
- if ((abcdefgh) & (1 << i)) {
- imm |=3D 0xffULL << (i * 8);
- }
- }
- } else if (cmode_0) {
- if (is_neg) {
- imm =3D (abcdefgh & 0x3f) << 48;
- if (abcdefgh & 0x80) {
- imm |=3D 0x8000000000000000ULL;
- }
- if (abcdefgh & 0x40) {
- imm |=3D 0x3fc0000000000000ULL;
- } else {
- imm |=3D 0x4000000000000000ULL;
- }
- } else {
- if (o2) {
- /* FMOV (vector, immediate) - half-precision */
- imm =3D vfp_expand_imm(MO_16, abcdefgh);
- /* now duplicate across the lanes */
- imm =3D bitfield_replicate(imm, 16);
- } else {
- imm =3D (abcdefgh & 0x3f) << 19;
- if (abcdefgh & 0x80) {
- imm |=3D 0x80000000;
- }
- if (abcdefgh & 0x40) {
- imm |=3D 0x3e000000;
- } else {
- imm |=3D 0x40000000;
- }
- imm |=3D (imm << 32);
- }
- }
- }
- break;
- default:
- g_assert_not_reached();
- }
-
- if (cmode_3_1 !=3D 7 && is_neg) {
- imm =3D ~imm;
+ if (cmode =3D=3D 15 && o2 && !is_neg) {
+ /* FMOV (vector, immediate) - half-precision */
+ imm =3D vfp_expand_imm(MO_16, abcdefgh);
+ /* now duplicate across the lanes */
+ imm =3D bitfield_replicate(imm, 16);
+ } else {
+ imm =3D asimd_imm_const(abcdefgh, cmode, is_neg);
}
=20
if (!((cmode & 0x9) =3D=3D 0x1 || (cmode & 0xd) =3D=3D 0x9)) {
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 95ceb24ec3b..66b24ab56e9 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -121,8 +121,8 @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int o=
p)
case 14:
if (op) {
/*
- * This is the only case where the top and bottom 32 bits
- * of the encoded constant differ.
+ * This and cmode =3D=3D 15 op =3D=3D 1 are the only cases whe=
re
+ * the top and bottom 32 bits of the encoded constant differ.
*/
uint64_t imm64 =3D 0;
int n;
@@ -137,6 +137,19 @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int =
op)
imm |=3D (imm << 8) | (imm << 16) | (imm << 24);
break;
case 15:
+ if (op) {
+ /* Reserved encoding for AArch32; valid for AArch64 */
+ uint64_t imm64 =3D (uint64_t)(imm & 0x3f) << 48;
+ if (imm & 0x80) {
+ imm64 |=3D 0x8000000000000000ULL;
+ }
+ if (imm & 0x40) {
+ imm64 |=3D 0x3fc0000000000000ULL;
+ } else {
+ imm64 |=3D 0x4000000000000000ULL;
+ }
+ return imm64;
+ }
imm =3D ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
| ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
break;
--=20
2.20.1