From nobody Tue Dec 16 02:36:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625222539; cv=none; d=zohomail.com; s=zohoarc; b=Wt1S9BP2uaSgCfLdCDsKTSGm31teYLW/txNPu9KT+NbO7zvv/0YMlN+SGCVnsKgy50XufEMoLvsXNO/A6Kzmb+oghglxP7YqyXWMgjIp6wRkZu2dX+mSrzbKlkE4GZLIo3Cfj7dxRbgp0CfZtCN9Uzpc+EUdgKFPjR5W5/Hq29g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625222539; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hMxqgRMRaEeAuAomNzQfVfuioKmuSQPXmbHQvftFpp4=; b=hd2v3VCYPskT9+5UKFxMt6dJfubCP1odBEB0C5d3KmAOSlJRVUHqXhiTvV/RpP0doDf0jqob9gTpsdnc2Xl99947kLTAiA/hBjLtumCEBpB8M3aRbKXZ6zavHu03nySmdndzdV9lyhj9fayUlrfBz85y1Fjp2Sn3FyE+B/ZGlKk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1625222539355415.67337837723505; Fri, 2 Jul 2021 03:42:19 -0700 (PDT) Received: from localhost ([::1]:60124 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lzGcj-0007U5-76 for importer@patchew.org; Fri, 02 Jul 2021 06:42:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59628) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lzGav-0004aw-Hg for qemu-devel@nongnu.org; Fri, 02 Jul 2021 06:40:25 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:43609) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lzGat-0006YK-Cz for qemu-devel@nongnu.org; Fri, 02 Jul 2021 06:40:24 -0400 Received: by mail-wm1-x32f.google.com with SMTP id q18-20020a1ce9120000b02901f259f3a250so6054625wmc.2 for ; Fri, 02 Jul 2021 03:40:22 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hMxqgRMRaEeAuAomNzQfVfuioKmuSQPXmbHQvftFpp4=; b=glOzzCDpuBPmTjQb5ZHwS0fOGxVVg4IovFuV0otzdc5FAwLn3JNAEZfp4bBWi9FV1m D7SHC0qoVvS955HPIl+ZQeoHbGVSheVpetyPyU34RnkENNqcI4pvh9RVknh2r4GWho0A sUtdHGtwhevjXBeWSBQSfqYk6RUACkiukpwkvNqVyGjuSm6ppBE72b4vBHbblBr6ikYy ModlY6X9ahXFv+CX/PaQ8Sz8QifMdq3DLGq0yJ1z0l6DSe0c2U/YmqEB0amzeQMfO6+2 xO7to8Kh/LqcabtyQrn0P2opQ0sEQCfRcnI+aq9GVIiLMDfpkvsI1Y+7/HtvUB5BVdUv bHiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hMxqgRMRaEeAuAomNzQfVfuioKmuSQPXmbHQvftFpp4=; b=idtZ4VmoroddiPH8ECjXcrSkkYpEaoxBMfJct849DMkyuGwnxfojV0UgQt/sYQrTml KV++AgvTYbbqicYofC3R+EKakFxHKGSbvwxIkFvFUW1/zGS/wu5B1Uq0ytim8DfML2g/ 9a4KEVf6vebgMhDLokRclib425UJGExSJ2YP+NguhPv/IqUwLvkDoH8Mh+5WmdBNo36X 3u+Kr2NxvHW4c5o4sV9AvUov76iBuNSbVH3+U13SZq6WI9ROImDZqtHQSSq/Q+90XsXd a80fblb9524dCCvY4SjdiqMVG1KfwFSRroK4rl62V213UrkjjuzOAICkAPTSagR+9GXv /3RQ== X-Gm-Message-State: AOAM530dITjxpT/bAkUf1ZnAOqUzcYosEFTvfZWiA+U2u4D/YMVYo62V e/bNGXVPdVw0rdwHMa7oYLDjAg== X-Google-Smtp-Source: ABdhPJzm3YmughZtZ249rQ3pwnHta4pk4xYaayWXpx4jpWfUhTRzbLiSM8Wb955mkhMhKYdxKSEipg== X-Received: by 2002:a7b:cb91:: with SMTP id m17mr15561780wmi.26.1625222421543; Fri, 02 Jul 2021 03:40:21 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 01/11] hw/gpio/gpio_pwr: use shutdown function for reboot Date: Fri, 2 Jul 2021 11:40:08 +0100 Message-Id: <20210702104018.19881-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625222541839100001 Content-Type: text/plain; charset="utf-8" From: Maxim Uvarov qemu has 2 type of functions: shutdown and reboot. Shutdown function has to be used for machine shutdown. Otherwise we cause a reset with a bogus "cause" value, when we intended a shutdown. Signed-off-by: Maxim Uvarov Reviewed-by: Peter Maydell Message-id: 20210625111842.3790-3-maxim.uvarov@linaro.org [PMM: tweaked commit message] Signed-off-by: Peter Maydell --- hw/gpio/gpio_pwr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/gpio/gpio_pwr.c b/hw/gpio/gpio_pwr.c index 7714fa0dc4d..dbaf1c70c88 100644 --- a/hw/gpio/gpio_pwr.c +++ b/hw/gpio/gpio_pwr.c @@ -43,7 +43,7 @@ static void gpio_pwr_reset(void *opaque, int n, int level) static void gpio_pwr_shutdown(void *opaque, int n, int level) { if (level) { - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); } } =20 --=20 2.20.1 From nobody Tue Dec 16 02:36:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625222553; cv=none; d=zohomail.com; s=zohoarc; b=h02pJaYaIajhdrDmdWaPt/Fdy6dmHLwPezP3aDra/oges6Ogqt3UQg2ypElbSKDFPKmBlW1kLM+kmS4LAaqNgeugX6qW8YYbWcyRvce51QHPRMIdIvF0UrtKbmyXY9AHkL/MSOAblnR5CPuHyPiF+tkcEtVUAO5p5t3+rSfgqNU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625222553; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cyVR+RM9P0Fu8J9agxc+syCsAuN2LmIMWIgCF4vgRTg=; b=HE0UqhiMLW2Hj2kwZ6/B9XXvxtyt1c3bAvpCQLdHH1Q+8kbLch4t00MeTgtGUCy1hlfuAzTiy8ACsU9s4CALMeNhzrVSO9HuTJb7a/R1tT6ttJxrtxgaAvk6Qlibumr4H49+Sy0dMEcNL7xDQ556/FCFsTKcv3/912XK07pRbdQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1625222553875370.5345737122585; Fri, 2 Jul 2021 03:42:33 -0700 (PDT) Received: from localhost ([::1]:32908 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lzGcy-00089r-R7 for importer@patchew.org; Fri, 02 Jul 2021 06:42:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59684) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lzGaw-0004c8-Qi for qemu-devel@nongnu.org; Fri, 02 Jul 2021 06:40:27 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:45766) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lzGat-0006Yp-Hk for qemu-devel@nongnu.org; Fri, 02 Jul 2021 06:40:26 -0400 Received: by mail-wr1-x431.google.com with SMTP id j2so11865362wrs.12 for ; Fri, 02 Jul 2021 03:40:23 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cyVR+RM9P0Fu8J9agxc+syCsAuN2LmIMWIgCF4vgRTg=; b=sdDsSJM3o8ByLAVGX+u7ux2gd3O5MnBkU/Qg9bXeucpPywXtLQNnMQIdOvJ3A0ecaI e5TSBB8re+kwEPdCH9hpzoGBiOigGy0L1mJAqpAxs51kk1IYu05ZXijTjBThmOq9NQqj PHPjivs9jOyikzNJAh16ui3KOwaNTu3LQrv+Q5c1UMwvSPtI6iJcQw3SlATAiqOELG0Q PLKu3KhuoYmdnNErCnF4qdkgqH85mpuY+NI/UNd01kOkM+i8ChiWbq0oV2xPfW/lE4B1 5lohes8Or1THXOgHK0+Od3aaiNGvISi0YUQLp6pAWp55/lxNWnol/2o1oN5U/BrRFxar N4Yg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cyVR+RM9P0Fu8J9agxc+syCsAuN2LmIMWIgCF4vgRTg=; b=OFvfaXKqxTOqt4fo3vRIqZnseICg/kvW86qcmsN/k1SLSEbMVkcx9zh5joHfChPOSJ +jTTw+LDKapVqDlp3OG6uMUbu4c5zaPAAKf/66CftoNc9n3L0eldaa0/bYIeF6HYyu+T bw0aqJOGlZ3s1R3iqEAgta6BvXwcgb6DOxeLfbfg4UXKBEDBfdF89cNbFNHa+HRVHbGC hE1gVovxDBYNt/iPRKGvtt4ggYGCUBU9qz8MNgqEtWFZs9uWcwqZheCApoL7fvjmtq/Y ayKwrHYfHArm4KtBlnOd8pwli1FAjKe0BSif7pgst1ZflAS1sjGG0CERXl97pAtMQlic 8z0Q== X-Gm-Message-State: AOAM533+YCj8e97peb86LGPUsULK5/mM9bob4p8vyFFhlA4+heWPhuDr 0j1CRcrDjaA1YWP9F7RbV8o9LA== X-Google-Smtp-Source: ABdhPJw0BPQrnNs8gAxKbHD2/X6aczSpVFj1v0Zdpre1k9KiKDPAJFbQa99ZUDHhivKZcxMtlgYO+Q== X-Received: by 2002:a5d:6742:: with SMTP id l2mr4983888wrw.202.1625222422232; Fri, 02 Jul 2021 03:40:22 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 02/11] hw/gpio/pl061: Convert DPRINTF to tracepoints Date: Fri, 2 Jul 2021 11:40:09 +0100 Message-Id: <20210702104018.19881-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625222556166100003 Content-Type: text/plain; charset="utf-8" Convert the use of the DPRINTF debug macro in the PL061 model to use tracepoints. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/gpio/pl061.c | 27 +++++++++------------------ hw/gpio/trace-events | 6 ++++++ 2 files changed, 15 insertions(+), 18 deletions(-) diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index e72e77572a0..a6ace88895d 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -15,19 +15,7 @@ #include "qemu/log.h" #include "qemu/module.h" #include "qom/object.h" - -//#define DEBUG_PL061 1 - -#ifdef DEBUG_PL061 -#define DPRINTF(fmt, ...) \ -do { printf("pl061: " fmt , ## __VA_ARGS__); } while (0) -#define BADF(fmt, ...) \ -do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__); exit(1);} whi= le (0) -#else -#define DPRINTF(fmt, ...) do {} while(0) -#define BADF(fmt, ...) \ -do { fprintf(stderr, "pl061: error: " fmt , ## __VA_ARGS__);} while (0) -#endif +#include "trace.h" =20 static const uint8_t pl061_id[12] =3D { 0x00, 0x00, 0x00, 0x00, 0x61, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1= }; @@ -107,7 +95,7 @@ static void pl061_update(PL061State *s) uint8_t out; int i; =20 - DPRINTF("dir =3D %d, data =3D %d\n", s->dir, s->data); + trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data); =20 /* Outputs float high. */ /* FIXME: This is board dependent. */ @@ -118,8 +106,9 @@ static void pl061_update(PL061State *s) for (i =3D 0; i < N_GPIOS; i++) { mask =3D 1 << i; if (changed & mask) { - DPRINTF("Set output %d =3D %d\n", i, (out & mask) !=3D 0); - qemu_set_irq(s->out[i], (out & mask) !=3D 0); + int level =3D (out & mask) !=3D 0; + trace_pl061_set_output(DEVICE(s)->canonical_path, i, level= ); + qemu_set_irq(s->out[i], level); } } } @@ -131,7 +120,8 @@ static void pl061_update(PL061State *s) for (i =3D 0; i < N_GPIOS; i++) { mask =3D 1 << i; if (changed & mask) { - DPRINTF("Changed input %d =3D %d\n", i, (s->data & mask) != =3D 0); + trace_pl061_input_change(DEVICE(s)->canonical_path, i, + (s->data & mask) !=3D 0); =20 if (!(s->isense & mask)) { /* Edge interrupt */ @@ -150,7 +140,8 @@ static void pl061_update(PL061State *s) /* Level interrupt */ s->istate |=3D ~(s->data ^ s->iev) & s->isense; =20 - DPRINTF("istate =3D %02X\n", s->istate); + trace_pl061_update_istate(DEVICE(s)->canonical_path, + s->istate, s->im, (s->istate & s->im) !=3D 0= ); =20 qemu_set_irq(s->irq, (s->istate & s->im) !=3D 0); } diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index f0b664158e2..48ccbb183cc 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -13,6 +13,12 @@ nrf51_gpio_write(uint64_t offset, uint64_t value) "offse= t 0x%" PRIx64 " value 0x nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRI= i64 nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 = " value %" PRIi64 =20 +# pl061.c +pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x= GPIODATA 0x%x" +pl061_set_output(const char *id, int gpio, int level) "%s setting output %= d to %d" +pl061_input_change(const char *id, int gpio, int level) "%s input %d chang= ed to %d" +pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int leve= l) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d" + # sifive_gpio.c sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value = 0x%" PRIx64 sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " v= alue 0x%" PRIx64 --=20 2.20.1 From nobody Tue Dec 16 02:36:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yLZPF7xM8ZCBR3B2tWpuKNDyEXma9ARshxBKe1boF+8=; b=aoeaECMlWLk9zvfstylw19ZTyNYpc6fGOL9SrnV1oJxq3vWxUL5QXM17Hzw6Ut8kFn M8h13oqd0UmqyuT0L8ZCJVlW2gRUEBkxautyGUi4i/SepRYl3wNth/G8YjToWSr9I6eu lQXdEZ2mQoZO31E2/TA/4C1griKwZr2gbJ/3G5QymrUF6bOT8C2NdqEys3V6LL9wtzDB fx4SNqRsTQPNdvXk3O5COaOU5c64EuT999LRiOn8ZHiF4dANbTupu8Gs3l3Wls47xxt3 mKkDf50dQHvGSNePb7C6e3EZrFkkV2pR1RBKwn5ug+kPIa2F6O8QoaAsRPd0d3zbmncK /YcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yLZPF7xM8ZCBR3B2tWpuKNDyEXma9ARshxBKe1boF+8=; b=VYis6MSSowxvOeQD2SzTX08Nixf2yDsCERC51uXS+DPwfJ4cmJjECAt9Notld+O2Pa Og0mpo8q81lT33XGhdC4TDxbdhEW/vrwWW/CB6cl79p+N0KmUA6rX8WXueUK2YkbCucu mcv67152I6sMw/NSMuNncpXlXF3RH99giLuOJ8xprcEPMSIxgO+r8jdIE6ReWYDekVWO 1HlhO1rSruJFvOGqzjayTtMsgV196hmQC1fOn2Cmlj6eo6zH4XBTspj8OlSOgjepkWkF uuLpTFUyANzRRzPbbkgdDZgrHBPmnGjxdTpx2P+EWzSVwwQj9f9XFkUUVHBkKGz9VQRP HCfg== X-Gm-Message-State: AOAM531XXn0ac+mpCTl6u6Dz7vVxwRFKnl7U4QaVBgRn6x37p8ofZfpT ysl/qzYvYVmil7VHI89VSdtFuQ== X-Google-Smtp-Source: ABdhPJzYZlZjtM/PYJiHziW2cNvrU6Nm5Y+7+oGeO+1H2Px837SH3zFd/mdUKqn0rwMsb+Lo8az4oQ== X-Received: by 2002:a7b:c4ca:: with SMTP id g10mr15932042wmk.148.1625222423019; Fri, 02 Jul 2021 03:40:23 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 03/11] hw/gpio/pl061: Clean up read/write offset handling logic Date: Fri, 2 Jul 2021 11:40:10 +0100 Message-Id: <20210702104018.19881-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625222702737100001 Content-Type: text/plain; charset="utf-8" Currently the pl061_read() and pl061_write() functions handle offsets using a combination of three if() statements and a switch(). Clean this up to use just a switch, using case ranges. This requires that instead of catching accesses to the luminary-only registers on a stock PL061 via a check on s->rsvd_start we use an "is this luminary?" check in the cases for each luminary-only register. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/gpio/pl061.c | 106 ++++++++++++++++++++++++++++++++++++------------ 1 file changed, 81 insertions(+), 25 deletions(-) diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index a6ace88895d..0f5d12e6d5a 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -55,7 +55,6 @@ struct PL061State { qemu_irq irq; qemu_irq out[N_GPIOS]; const unsigned char *id; - uint32_t rsvd_start; /* reserved area: [rsvd_start, 0xfcc] */ }; =20 static const VMStateDescription vmstate_pl061 =3D { @@ -151,16 +150,9 @@ static uint64_t pl061_read(void *opaque, hwaddr offset, { PL061State *s =3D (PL061State *)opaque; =20 - if (offset < 0x400) { - return s->data & (offset >> 2); - } - if (offset >=3D s->rsvd_start && offset <=3D 0xfcc) { - goto err_out; - } - if (offset >=3D 0xfd0 && offset < 0x1000) { - return s->id[(offset - 0xfd0) >> 2]; - } switch (offset) { + case 0x0 ... 0x3fc: /* Data */ + return s->data & (offset >> 2); case 0x400: /* Direction */ return s->dir; case 0x404: /* Interrupt sense */ @@ -178,33 +170,70 @@ static uint64_t pl061_read(void *opaque, hwaddr offse= t, case 0x420: /* Alternate function select */ return s->afsel; case 0x500: /* 2mA drive */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->dr2r; case 0x504: /* 4mA drive */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->dr4r; case 0x508: /* 8mA drive */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->dr8r; case 0x50c: /* Open drain */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->odr; case 0x510: /* Pull-up */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->pur; case 0x514: /* Pull-down */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->pdr; case 0x518: /* Slew rate control */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->slr; case 0x51c: /* Digital enable */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->den; case 0x520: /* Lock */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->locked; case 0x524: /* Commit */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->cr; case 0x528: /* Analog mode select */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } return s->amsel; + case 0x52c ... 0xfcc: /* Reserved */ + goto bad_offset; + case 0xfd0 ... 0xffc: /* ID registers */ + return s->id[(offset - 0xfd0) >> 2]; default: + bad_offset: + qemu_log_mask(LOG_GUEST_ERROR, + "pl061_read: Bad offset %x\n", (int)offset); break; } -err_out: - qemu_log_mask(LOG_GUEST_ERROR, - "pl061_read: Bad offset %x\n", (int)offset); return 0; } =20 @@ -214,16 +243,12 @@ static void pl061_write(void *opaque, hwaddr offset, PL061State *s =3D (PL061State *)opaque; uint8_t mask; =20 - if (offset < 0x400) { + switch (offset) { + case 0 ... 0x3fc: mask =3D (offset >> 2) & s->dir; s->data =3D (s->data & ~mask) | (value & mask); pl061_update(s); return; - } - if (offset >=3D s->rsvd_start) { - goto err_out; - } - switch (offset) { case 0x400: /* Direction */ s->dir =3D value & 0xff; break; @@ -247,47 +272,80 @@ static void pl061_write(void *opaque, hwaddr offset, s->afsel =3D (s->afsel & ~mask) | (value & mask); break; case 0x500: /* 2mA drive */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->dr2r =3D value & 0xff; break; case 0x504: /* 4mA drive */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->dr4r =3D value & 0xff; break; case 0x508: /* 8mA drive */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->dr8r =3D value & 0xff; break; case 0x50c: /* Open drain */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->odr =3D value & 0xff; break; case 0x510: /* Pull-up */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->pur =3D value & 0xff; break; case 0x514: /* Pull-down */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->pdr =3D value & 0xff; break; case 0x518: /* Slew rate control */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->slr =3D value & 0xff; break; case 0x51c: /* Digital enable */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->den =3D value & 0xff; break; case 0x520: /* Lock */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->locked =3D (value !=3D 0xacce551); break; case 0x524: /* Commit */ + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } if (!s->locked) s->cr =3D value & 0xff; break; case 0x528: + if (s->id !=3D pl061_id_luminary) { + goto bad_offset; + } s->amsel =3D value & 0xff; break; default: - goto err_out; + bad_offset: + qemu_log_mask(LOG_GUEST_ERROR, + "pl061_write: Bad offset %x\n", (int)offset); + return; } pl061_update(s); return; -err_out: - qemu_log_mask(LOG_GUEST_ERROR, - "pl061_write: Bad offset %x\n", (int)offset); } =20 static void pl061_reset(DeviceState *dev) @@ -343,7 +401,6 @@ static void pl061_luminary_init(Object *obj) PL061State *s =3D PL061(obj); =20 s->id =3D pl061_id_luminary; - s->rsvd_start =3D 0x52c; } =20 static void pl061_init(Object *obj) @@ -353,7 +410,6 @@ static void pl061_init(Object *obj) SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); =20 s->id =3D pl061_id; - s->rsvd_start =3D 0x424; =20 memory_region_init_io(&s->iomem, obj, &pl061_ops, s, "pl061", 0x1000); sysbus_init_mmio(sbd, &s->iomem); --=20 2.20.1 From nobody Tue Dec 16 02:36:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625222555; cv=none; d=zohomail.com; s=zohoarc; b=MoL7Tt/5z5RS9nuSzAJE4G7kuUw2IGgutM/vUhybMywhKidvxDSdhQLrfhqyddUZI0ctQPXJbclPkql8fFE/ezE+cVC9TPa+HwPeoAF+eg9ebGi21/qQY8rqynfrl4+kY2lpC2+7HJw1Ayj/LDyb1LJFAwpAS4AKaonrrSOiXOI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625222555; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=V8sS0Bb0e+XFKMXcd7X5sBnIKxL0C6ytZPnPqSvPiJU=; b=CJU/ZSNyxabb0AWd/Kuic/rkOR/4dAGTEg2H5OmumG6WumJWQc4sdZHVrq/6sMLfM+ Y1uePmtw6ATBU9Sq74NBGxTPpC5soFmnLxwfHOYGUDfG2LQlktYQ7WoXl4IhEagqI6JN HN6VwxtE2tAHAtsglKV2huQREXP5p8cGpsO2pmKvpdGctw5H3nvxFNrgCGDFvmCMPmQ+ OtVPvNifRz07ms+6uznbxXtScOokxQZdcAn2HOesoMIMUftVdC8Azj4jvFgfmG542O9n SoVJtNlhxujWWPAtzDT0PN3K4c46mFWJRG15/6DeU0n1rWYyw/3Py+JmZtg9zvHW/7di BLKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V8sS0Bb0e+XFKMXcd7X5sBnIKxL0C6ytZPnPqSvPiJU=; b=j86QLmA6DJcC01v0/D/jpyVE+/Qo89UEg/rZO2cZoSJBWDRbRJhEYJJmKSXdW36YRX Uxx2E/yUUgGK5rok6iYrDtpACCfzxuajFpuEOHy4M2KYg/837Ech8DNT5g5jSUzPNfrw tIm6jh8n3urlJMSUFMEZtN3kcVeRsZwhn3jHOd415yfBxfQadv/640rIoVXiJT3oA0p7 f8l0Hj/9dokulIkxFn5l/Fnhe9LQ9ql7zmWDba9gHzgayPVUsyZZxLdV8eABMzfGrjJd sM7oyz/fC0Wb9HTIRwfsZZPC+sQSW5BB3H1BraiMMmM4TphunlQoMrPiBLMYm1/oOg3H 54Fg== X-Gm-Message-State: AOAM532o5639hxh0mexWJbkkDbH7yeCIFVvioXRav3c5SHkvTA4SnbPn QSVVbaof5waPX3H79QEEnjwNMQ== X-Google-Smtp-Source: ABdhPJz39ucoSTaOuznc+qkugdbt86TaBaIgbsuwD/QVXOz78nLBadGLp3mHpj+DiZ8xxxKJF/5ekA== X-Received: by 2002:adf:f10d:: with SMTP id r13mr5022432wro.59.1625222423805; Fri, 02 Jul 2021 03:40:23 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/11] hw/gpio/pl061: Add tracepoints for register read and write Date: Fri, 2 Jul 2021 11:40:11 +0100 Message-Id: <20210702104018.19881-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625222558232100005 Content-Type: text/plain; charset="utf-8" Add tracepoints for reads and writes to the PL061 registers. This requires restructuring pl061_read() to only return after the tracepoint, rather than having lots of early-returns. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/gpio/pl061.c | 70 ++++++++++++++++++++++++++++++-------------- hw/gpio/trace-events | 2 ++ 2 files changed, 50 insertions(+), 22 deletions(-) diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index 0f5d12e6d5a..f3b80c7776f 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -149,92 +149,116 @@ static uint64_t pl061_read(void *opaque, hwaddr offs= et, unsigned size) { PL061State *s =3D (PL061State *)opaque; + uint64_t r =3D 0; =20 switch (offset) { case 0x0 ... 0x3fc: /* Data */ - return s->data & (offset >> 2); + r =3D s->data & (offset >> 2); + break; case 0x400: /* Direction */ - return s->dir; + r =3D s->dir; + break; case 0x404: /* Interrupt sense */ - return s->isense; + r =3D s->isense; + break; case 0x408: /* Interrupt both edges */ - return s->ibe; + r =3D s->ibe; + break; case 0x40c: /* Interrupt event */ - return s->iev; + r =3D s->iev; + break; case 0x410: /* Interrupt mask */ - return s->im; + r =3D s->im; + break; case 0x414: /* Raw interrupt status */ - return s->istate; + r =3D s->istate; + break; case 0x418: /* Masked interrupt status */ - return s->istate & s->im; + r =3D s->istate & s->im; + break; case 0x420: /* Alternate function select */ - return s->afsel; + r =3D s->afsel; + break; case 0x500: /* 2mA drive */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->dr2r; + r =3D s->dr2r; + break; case 0x504: /* 4mA drive */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->dr4r; + r =3D s->dr4r; + break; case 0x508: /* 8mA drive */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->dr8r; + r =3D s->dr8r; + break; case 0x50c: /* Open drain */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->odr; + r =3D s->odr; + break; case 0x510: /* Pull-up */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->pur; + r =3D s->pur; + break; case 0x514: /* Pull-down */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->pdr; + r =3D s->pdr; + break; case 0x518: /* Slew rate control */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->slr; + r =3D s->slr; + break; case 0x51c: /* Digital enable */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->den; + r =3D s->den; + break; case 0x520: /* Lock */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->locked; + r =3D s->locked; + break; case 0x524: /* Commit */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->cr; + r =3D s->cr; + break; case 0x528: /* Analog mode select */ if (s->id !=3D pl061_id_luminary) { goto bad_offset; } - return s->amsel; + r =3D s->amsel; + break; case 0x52c ... 0xfcc: /* Reserved */ goto bad_offset; case 0xfd0 ... 0xffc: /* ID registers */ - return s->id[(offset - 0xfd0) >> 2]; + r =3D s->id[(offset - 0xfd0) >> 2]; + break; default: bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "pl061_read: Bad offset %x\n", (int)offset); break; } - return 0; + + trace_pl061_read(DEVICE(s)->canonical_path, offset, r); + return r; } =20 static void pl061_write(void *opaque, hwaddr offset, @@ -243,6 +267,8 @@ static void pl061_write(void *opaque, hwaddr offset, PL061State *s =3D (PL061State *)opaque; uint8_t mask; =20 + trace_pl061_write(DEVICE(s)->canonical_path, offset, value); + switch (offset) { case 0 ... 0x3fc: mask =3D (offset >> 2) & s->dir; diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index 48ccbb183cc..442be9406f5 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -18,6 +18,8 @@ pl061_update(const char *id, uint32_t dir, uint32_t data)= "%s GPIODIR 0x%x GPIOD pl061_set_output(const char *id, int gpio, int level) "%s setting output %= d to %d" pl061_input_change(const char *id, int gpio, int level) "%s input %d chang= ed to %d" pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int leve= l) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d" +pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PR= Ix64 " value 0x%" PRIx64 +pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x= %" PRIx64 " value 0x%" PRIx64 =20 # sifive_gpio.c sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value = 0x%" PRIx64 --=20 2.20.1 From nobody Tue Dec 16 02:36:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=b4cQvDxv3U0hq7oSF/cGe7YwUjG/pIr/hMSWdlGoaBw=; b=PEVszNmTs/x19yK9bZJV98DZatrUysk+75eEB8JwhZvZSkjxT0VxfFwjdW2pZv2h8Y 5XVZBuqmBXMtW5bWHmHBEuSw6XiZ9uQtDF2TQeLnW336RgyXImdzoJEVU99rhiX0O4da GK5bEC+Lin/VqFdiKOJFSDS0wJ3FrXTnvWwSjE9p2a6S2+kUmdBegUA1mTRuxsS7XAJB CWhcxRvXFKVC1mRldZ4HJ0/MGjehiK10LuUSZjht71W0x53GB8yKhyXoqO0u64kxuIcw qhVTq96fn35DUGHtTrEIPKLSCwY2WiszXGzomqBEBnhx/TINgHMFLLXwJTMsjfATWwdk OiZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=b4cQvDxv3U0hq7oSF/cGe7YwUjG/pIr/hMSWdlGoaBw=; b=ZlBjlCGBCjoX+N7s3e2AyLGg87ko7Z5Ih5TmvllwyudyphIW8uHcuyRgUEM9JHVg9w g1KSw2YQM4aU+eJtGo2NdSOBh08/kFObqLiE2+pjFNoC8ho/L+Awq1JD4ecAr3/r8u/0 ZR8xEyNlmVwN3fAHDQ0IXF3nIwGJl0Bd1LWefbKD7Z/rz6ytsZHiizHMJrchhfJ+NJ4g R4VBwIEh2by1ieSmkHYrmgfRrdj/EJVMsMbqF8DZRFjbaFp5KYiaWv3Ao3a22WRUZUjn 40qVdwNod1tQ7MD/fstBx2xywn2GHJIVB2Q6JoI+O7rqvuHZkcLSchyxhQbfxa1cxB5h QKDA== X-Gm-Message-State: AOAM530uZwn3WzbaOE5D09odaA9uKHQkodgnPD3uEMYsw8BCzI1CnRRg 7V+PoCuvqPLknggqH6n41E6KXQ== X-Google-Smtp-Source: ABdhPJwHAw5EkYyJx+n/VtwsOCf6+Wd0X7aPRv3rpBuAMJ0DgSg4QpVBssW9JvOb0GsJPTblCjmNkw== X-Received: by 2002:a7b:ce82:: with SMTP id q2mr15536075wmj.60.1625222424453; Fri, 02 Jul 2021 03:40:24 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 05/11] hw/gpio/pl061: Document the interface of this device Date: Fri, 2 Jul 2021 11:40:12 +0100 Message-Id: <20210702104018.19881-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625222890265100001 Content-Type: text/plain; charset="utf-8" Add a comment documenting the "QEMU interface" of this device: which MMIO regions, IRQ lines, GPIO lines, etc it exposes. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/gpio/pl061.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index f3b80c7776f..06a1b82a503 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -6,6 +6,13 @@ * Written by Paul Brook * * This code is licensed under the GPL. + * + * QEMU interface: + * + sysbus MMIO region 0: the device registers + * + sysbus IRQ: the GPIOINTR interrupt line + * + unnamed GPIO inputs 0..7: inputs to connect to the emulated GPIO lin= es + * + unnamed GPIO outputs 0..7: the emulated GPIO lines, considered as + * outputs */ =20 #include "qemu/osdep.h" --=20 2.20.1 From nobody Tue Dec 16 02:36:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625222904; cv=none; d=zohomail.com; s=zohoarc; b=RyMLmBtjtaFntfCECfoMDdVwre3vGRUIR1aHqxemTTps80gkY4K/K0yc1NZ5MLfBKytCXVKKRMO1YO3QemGH7wD6jPK5jMCwQ6jayroSY2zc1blnp0HbtgSgSfGWMCt0sziSoVHC12t2l5uZ8WUD/JIfZqgSnj6HdNgygvalLgU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625222904; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CnOCqrZmWUxfwjKjUalVZwOU/ZbiNiTaO6KmtADP/mk=; b=lLKtkaKlEUhUrH4AX1Q2AwVo5pjsa6nb3Qb+SVBzwlXljD3bZp58NmBvE8NtvMYTOzwYaXsJ2o4MgRJj1bAGTFYnqI8W8D2ORV6QfCHVirIliPp6uEuvsdHRMvy2Wv+FcAp5HlIr4fRSrKnfX5OrCPAl4B2QrIXd9Q/AfMPMyjA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1625222904743717.4145496488637; Fri, 2 Jul 2021 03:48:24 -0700 (PDT) Received: from localhost ([::1]:48198 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lzGid-0001dK-NE for importer@patchew.org; Fri, 02 Jul 2021 06:48:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59874) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lzGb3-0004mn-VD for qemu-devel@nongnu.org; Fri, 02 Jul 2021 06:40:34 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:36466) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lzGax-0006d9-84 for qemu-devel@nongnu.org; Fri, 02 Jul 2021 06:40:33 -0400 Received: by mail-wm1-x32a.google.com with SMTP id m41-20020a05600c3b29b02901dcd3733f24so8761235wms.1 for ; Fri, 02 Jul 2021 03:40:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CnOCqrZmWUxfwjKjUalVZwOU/ZbiNiTaO6KmtADP/mk=; b=Bg5ipmEdn5wI/Damf0iQdqGhk40VGHkKnPgiZnflIo/pVz7CwVq9eEGs9CvdScXgz3 My0PlJ0HHbIIR1sRg/Neran4WFC1D9++tqU1+RyGud4nshhJVLgchVJjHqrUVZI9dqpZ WgBBIaLCFiVu1b2juv5mNDinxbx6eu1cqWeqBtnwKaZ850eVwdrHqAM1qOYufiEMymBh ovchTKpEHcb4kiWIxQ+0ujHQu39a9JgzKKZIBAG0ZGAzb1RHpFLzamXXJbqFyirLDsqn BZLMyup+4g1zUSMyisbA0ysAmOU8tk/Yv5nFHkbZ6el4wi/ZnjDGkBnVuyiDwHhOR8wN fxJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CnOCqrZmWUxfwjKjUalVZwOU/ZbiNiTaO6KmtADP/mk=; b=NraJGfCq+4oEa9JDpxqtut1v8YyGbgAhQHTPhvx50OvlHQlE/NUtqlbwqGBREXX/NF 8RdCLEANOFLLalBUZG/ZAgmFKjqOBxw6rwpHXmu8x0Wx1laI4NN910eeCAFq3kFRUXE2 5nQKlxAbYnXewKpWbQIuBbh+cgIDwT8LSXraGpeqqWUzuYQsxnaQGfsuu2HwJeaxCQhs shkDs+VdMJM+lK85+WXZCohlGoCLq+bXQBz/4y8wbJikusdT3lkoh7bQ4HifTnmabkL3 q8BKTBqv13UurwJBZxQCPZEfRR1HpWSPw93AlXoGs6XjuDcQRx/KEIsDde5EWgjkptqS 2MAw== X-Gm-Message-State: AOAM531y5bHH8EfVn0Yq4uIpzRWBW+Os+V4d2xExF/iQDBPJWWoYQLFF Vsgyk3BM5vJTe3qlKhptYKzzP/lglyYWtKqP X-Google-Smtp-Source: ABdhPJzYhp2oVI3fW4t+ccM+An6/SkJc9UW7q495KvjuofzfRHCuQ5TObwxA1eQMPVMaqTi2I5svVA== X-Received: by 2002:a05:600c:296:: with SMTP id 22mr15229146wmk.17.1625222425235; Fri, 02 Jul 2021 03:40:25 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 06/11] hw/gpio/pl061: Honour Luminary PL061 PUR and PDR registers Date: Fri, 2 Jul 2021 11:40:13 +0100 Message-Id: <20210702104018.19881-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625222905229100001 Content-Type: text/plain; charset="utf-8" The Luminary variant of the PL061 has registers GPIOPUR and GPIOPDR which lets the guest configure whether the GPIO lines are pull-up, pull-down, or truly floating. Instead of assuming all lines are pulled high, honour the PUR and PDR registers. For the plain PL061, continue to assume that lines have an external pull-up resistor, as we did before. The stellaris board actually relies on this behaviour -- the CD line of the ssd0323 display device is connected to GPIO output C7, and it is only because of a different bug which we're about to fix that we weren't incorrectly driving this line high on reset and putting the ssd0323 into data mode. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/gpio/pl061.c | 58 +++++++++++++++++++++++++++++++++++++++++--- hw/gpio/trace-events | 2 +- 2 files changed, 55 insertions(+), 5 deletions(-) diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index 06a1b82a503..44bed56fef0 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -94,18 +94,68 @@ static const VMStateDescription vmstate_pl061 =3D { } }; =20 +static uint8_t pl061_floating(PL061State *s) +{ + /* + * Return mask of bits which correspond to pins configured as inputs + * and which are floating (neither pulled up to 1 nor down to 0). + */ + uint8_t floating; + + if (s->id =3D=3D pl061_id_luminary) { + /* + * If both PUR and PDR bits are clear, there is neither a pullup + * nor a pulldown in place, and the output truly floats. + */ + floating =3D ~(s->pur | s->pdr); + } else { + /* Assume outputs are pulled high. FIXME: this is board dependent.= */ + floating =3D 0; + } + return floating & ~s->dir; +} + +static uint8_t pl061_pullups(PL061State *s) +{ + /* + * Return mask of bits which correspond to pins configured as inputs + * and which are pulled up to 1. + */ + uint8_t pullups; + + if (s->id =3D=3D pl061_id_luminary) { + /* + * The Luminary variant of the PL061 has an extra registers which + * the guest can use to configure whether lines should be pullup + * or pulldown. + */ + pullups =3D s->pur; + } else { + /* Assume outputs are pulled high. FIXME: this is board dependent.= */ + pullups =3D 0xff; + } + return pullups & ~s->dir; +} + static void pl061_update(PL061State *s) { uint8_t changed; uint8_t mask; uint8_t out; int i; + uint8_t pullups =3D pl061_pullups(s); + uint8_t floating =3D pl061_floating(s); =20 - trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data); + trace_pl061_update(DEVICE(s)->canonical_path, s->dir, s->data, + pullups, floating); =20 - /* Outputs float high. */ - /* FIXME: This is board dependent. */ - out =3D (s->data & s->dir) | ~s->dir; + /* + * Pins configured as output are driven from the data register; + * otherwise if they're pulled up they're 1, and if they're floating + * then we give them the same value they had previously, so we don't + * report any change to the other end. + */ + out =3D (s->data & s->dir) | pullups | (s->old_out_data & floating); changed =3D s->old_out_data ^ out; if (changed) { s->old_out_data =3D out; diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index 442be9406f5..eb5fb4701c6 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -14,7 +14,7 @@ nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi= 64 " value %" PRIi64 nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 = " value %" PRIi64 =20 # pl061.c -pl061_update(const char *id, uint32_t dir, uint32_t data) "%s GPIODIR 0x%x= GPIODATA 0x%x" +pl061_update(const char *id, uint32_t dir, uint32_t data, uint32_t pullups= , uint32_t floating) "%s GPIODIR 0x%x GPIODATA 0x%x pullups 0x%x floating 0= x%x" pl061_set_output(const char *id, int gpio, int level) "%s setting output %= d to %d" pl061_input_change(const char *id, int gpio, int level) "%s input %d chang= ed to %d" pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int leve= l) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d" --=20 2.20.1 From nobody Tue Dec 16 02:36:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625222883; cv=none; d=zohomail.com; s=zohoarc; b=QOJYdq/GRrGzHMm/EOZNap5Ds1zsU1fgQPzmJztEtdxe8k+HmfKp6Fg87SIoJvptBieygVQWvHaw/+CMHzcz+f5uDMPRZrhw/SkQtN2reb4LaTLmaY3ZP9jLu2Bjh0AuDY4bGy4kvf1+uhuoP1OBCnsyvQlKnuurMdwChziLUG0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625222883; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OHxj/xUOSn5B7Ujk/a1aY2KoAO5Tcc5/XFJvO0oLWf4=; b=n/Sred1FGaE8GeCccHi0EmIRtwfSxdHE74lOE0MuEeNgF23OcHlC5Hk0j991copU7nrddzLlesgOa5xmv6F6v0A6MtvJD7UWj64fwBPDexV7SdX3K7OsGVpKRRW6HrPD7rtAuCjf/WWwzw2OYTsv1gY7Mmj2mNGuV8iqzEnX3zQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1625222883681518.731950743118; Fri, 2 Jul 2021 03:48:03 -0700 (PDT) Received: from localhost ([::1]:46650 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lzGiI-0000bG-88 for importer@patchew.org; Fri, 02 Jul 2021 06:48:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59842) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lzGb2-0004j7-8B for qemu-devel@nongnu.org; Fri, 02 Jul 2021 06:40:32 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:38664) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lzGax-0006dT-A2 for qemu-devel@nongnu.org; Fri, 02 Jul 2021 06:40:31 -0400 Received: by mail-wr1-x434.google.com with SMTP id a8so218443wrp.5 for ; Fri, 02 Jul 2021 03:40:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OHxj/xUOSn5B7Ujk/a1aY2KoAO5Tcc5/XFJvO0oLWf4=; b=pKfNGLE80XJP6BdmjqJu83DHv/hT0/LRl/xezT6oIy5lof2rbz2iCvfGumKzWaudet TGA8SIWrvJ3MmRrk3u4FsrhDE7Qef2jJcSeVyUKQY45c2o5jk4OZ7wcxMLkPPNKfXQot bTz6G2h0Xbw55PQuF3qQ9bOLOpD8s0xz/Y4cGjGlztfwddZINmDks8M4/B0TaRtI2Lwn Hst+POFYWA58yyyfF7s/GSzBaifKrIbiECU/l/zwN8ICik5NkQFrRqYBXrAYkO7/DNjB i7hA2d4YkU/ZygiUhCNOXb0i8f9WSaGjSpiSwpcS3+lB0e0yC+her/pMNf61snjm4JPd cDxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OHxj/xUOSn5B7Ujk/a1aY2KoAO5Tcc5/XFJvO0oLWf4=; b=En4c6CgLnqI7zmeRdJza0w91ZU2Zl62Wk6Xi+IgwdcmrqBZG9iW4zDFBbOy7LKJFwR PxK4oFFb9kFt7ZKWU4XI8Ci6LQyyjYQm69xsNMKe9bxRSvy8LHxjTFjctboD0xTcPZAN h7s4Atdo1JhfcGHts08BQWT45BJcqkmyQYT0KNNZPoJJP6V/+xhPy2cGWocBK1S14n9W vqeDF+M00HJCvMHZicwK87+lR5sYpGD07/00qt+/bj/Telij8UJ49EnxzcWO6/FpLxJJ RPwI5YcF/sMhv1DQQShy9hnlaB1wVW60x3TqJnVnNkCSZ3QVKkdB416ncXb14YBef2fx ddHw== X-Gm-Message-State: AOAM530xSJ9cVwW+69r/4ZlctmEg0kB2CWpkg8H0NHxdYlpb/RKUFzzN kHgsEiqq5pWOIlqu/zrR/C0rSA== X-Google-Smtp-Source: ABdhPJwZV5+ooyS1lmSsnhAjWtJ59nFkT66MB7YbRwjWPUo8mt801vbrTVwJub9IWMCkHQQo8SOK8A== X-Received: by 2002:adf:eece:: with SMTP id a14mr5043230wrp.313.1625222426063; Fri, 02 Jul 2021 03:40:26 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 07/11] hw/gpio/pl061: Make pullup/pulldown of outputs configurable Date: Fri, 2 Jul 2021 11:40:14 +0100 Message-Id: <20210702104018.19881-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625222885864100001 Content-Type: text/plain; charset="utf-8" The PL061 GPIO does not itself include pullup or pulldown resistors to set the value of a GPIO line treated as an output when it is configured as an input (ie when the PL061 itself is not driving it). In real hardware it is up to the board to add suitable pullups or pulldowns. Currently our implementation hardwires this to "outputs pulled high", which is correct for some boards (eg the realview ones: see figure 3-29 in the "RealView Platform Baseboard for ARM926EJ-S User Guide" DUI0224I), but wrong for others. In particular, the wiring in the 'virt' board and the gpio-pwr device assumes that wires should be pulled low, because otherwise the pull-to-high will trigger a shutdown or reset action. (The only reason this doesn't happen immediately on startup is due to another bug in the PL061, where we don't assert the GPIOs to the correct value on reset, but will do so as soon as the guest touches a register and pl061_update() gets called.) Add properties to the pl061 so the board can configure whether it wants GPIO lines to have pullup, pulldown, or neither. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/gpio/pl061.c | 51 +++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 47 insertions(+), 4 deletions(-) diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index 44bed56fef0..bb496a19ade 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -13,12 +13,28 @@ * + unnamed GPIO inputs 0..7: inputs to connect to the emulated GPIO lin= es * + unnamed GPIO outputs 0..7: the emulated GPIO lines, considered as * outputs + * + QOM property "pullups": an integer defining whether non-floating lin= es + * configured as inputs should be pulled up to logical 1 (ie whether in + * real hardware they have a pullup resistor on the line out of the PL0= 61). + * This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should + * be pulled high, bit 1 configures line 1, and so on. The default is 0= xff, + * indicating that all GPIO lines are pulled up to logical 1. + * + QOM property "pulldowns": an integer defining whether non-floating l= ines + * configured as inputs should be pulled down to logical 0 (ie whether = in + * real hardware they have a pulldown resistor on the line out of the P= L061). + * This should be an 8-bit value, where bit 0 is 1 if GPIO line 0 should + * be pulled low, bit 1 configures line 1, and so on. The default is 0x= 0. + * It is an error to set a bit in both "pullups" and "pulldowns". If a = bit + * is 0 in both, then the line is considered to be floating, and it will + * not have qemu_set_irq() called on it when it is configured as an inp= ut. */ =20 #include "qemu/osdep.h" #include "hw/irq.h" #include "hw/sysbus.h" +#include "hw/qdev-properties.h" #include "migration/vmstate.h" +#include "qapi/error.h" #include "qemu/log.h" #include "qemu/module.h" #include "qom/object.h" @@ -62,6 +78,9 @@ struct PL061State { qemu_irq irq; qemu_irq out[N_GPIOS]; const unsigned char *id; + /* Properties, for non-Luminary PL061 */ + uint32_t pullups; + uint32_t pulldowns; }; =20 static const VMStateDescription vmstate_pl061 =3D { @@ -109,8 +128,7 @@ static uint8_t pl061_floating(PL061State *s) */ floating =3D ~(s->pur | s->pdr); } else { - /* Assume outputs are pulled high. FIXME: this is board dependent.= */ - floating =3D 0; + floating =3D ~(s->pullups | s->pulldowns); } return floating & ~s->dir; } @@ -131,8 +149,7 @@ static uint8_t pl061_pullups(PL061State *s) */ pullups =3D s->pur; } else { - /* Assume outputs are pulled high. FIXME: this is board dependent.= */ - pullups =3D 0xff; + pullups =3D s->pullups; } return pullups & ~s->dir; } @@ -501,12 +518,38 @@ static void pl061_init(Object *obj) qdev_init_gpio_out(dev, s->out, N_GPIOS); } =20 +static void pl061_realize(DeviceState *dev, Error **errp) +{ + PL061State *s =3D PL061(dev); + + if (s->pullups > 0xff) { + error_setg(errp, "pullups property must be between 0 and 0xff"); + return; + } + if (s->pulldowns > 0xff) { + error_setg(errp, "pulldowns property must be between 0 and 0xff"); + return; + } + if (s->pullups & s->pulldowns) { + error_setg(errp, "no bit may be set both in pullups and pulldowns"= ); + return; + } +} + +static Property pl061_props[] =3D { + DEFINE_PROP_UINT32("pullups", PL061State, pullups, 0xff), + DEFINE_PROP_UINT32("pulldowns", PL061State, pulldowns, 0x0), + DEFINE_PROP_END_OF_LIST() +}; + static void pl061_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->vmsd =3D &vmstate_pl061; dc->reset =3D &pl061_reset; + dc->realize =3D pl061_realize; + device_class_set_props(dc, pl061_props); } =20 static const TypeInfo pl061_info =3D { --=20 2.20.1 From nobody Tue Dec 16 02:36:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625223051; cv=none; d=zohomail.com; s=zohoarc; b=O3ER8C4z5LXyENX2lX+UHP33eb5z5AA6T2OdBQecA5dkfjw6w80OvfI+cJDb1BWs0QQm63ngvXHNUX7wxWDUfhUXCq3FGHnAHvC/2koCgtmFX1uy2sbrqV2+VdnXpDNUVdJBeypZPv1OE5A3SOOiHS2xylvJ5EHxwrCRzT9VDE8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625223051; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DIGZ1OnFIqnIhBTRUfPjwDd5CcBHiyNlzbgBPSbVdrw=; b=kQRWi2olid++LKTCJwBiaUfjcsuQQvnnfjRoddFuJwN/019IO/MZz/3W2UzPiPiLJChnkIpM02L64yc419L2GuJ790kOlGr/sbqTH0yBFLahS78kxd3ijuxle2rmUK1Ni1c+QMZSAi9KxZgXnCCcS298V7JERTXcyicMCUpos58= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1625223051793953.6063137616189; Fri, 2 Jul 2021 03:50:51 -0700 (PDT) Received: from localhost ([::1]:54770 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lzGl0-0005xO-Pg for importer@patchew.org; Fri, 02 Jul 2021 06:50:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59908) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lzGb6-0004qX-8i for qemu-devel@nongnu.org; Fri, 02 Jul 2021 06:40:36 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:43607) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lzGay-0006eI-8e for qemu-devel@nongnu.org; Fri, 02 Jul 2021 06:40:35 -0400 Received: by mail-wm1-x32c.google.com with SMTP id q18-20020a1ce9120000b02901f259f3a250so6054813wmc.2 for ; Fri, 02 Jul 2021 03:40:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DIGZ1OnFIqnIhBTRUfPjwDd5CcBHiyNlzbgBPSbVdrw=; b=IpqWMlIuauj2fBX47HmfivH2y06YJ0rjzRziKQunFdvjyKzOAtdvQh7KALlbUYpY+w 81/mdqajlzmxC1xXExmDNZbKaPrnADzgFEcoo79H4wQTyzm+vtZeqGHhH3KQ3dZZSKhb DXfwGJ/eYr5pbdIZM724imio3moC8YuEs05SNwmIjCXYK8xF0GG3q9eLaGHjrhQQg2W/ OyLVrRF1+6DmecbHfvgKHVt/Zluxlhbh1drjAGD2WfXmAeos267rwDRuSoOHzoRoAw2x eL7kOmmHfwk73PPbqKHM+GqExswQEkyOIMT+6vS4cIyviwf2nnsyqjqrY3/yuRrdCxhp TVBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DIGZ1OnFIqnIhBTRUfPjwDd5CcBHiyNlzbgBPSbVdrw=; b=AgARDhX/H6cUQ5M7YZjnVxG/nnpHIzYkbk/MGL4lbkO+LiwH2qWDKZwgTZ0UvBTpub EM1ajgCRGyXVyCiuIzBupZ9CVinrwKOP/fdTko4Oih1HuhFkqyG12UBhKFT/+UdyOfhN CK7xpB4owlzIX4lTOUuasruYG65FMT7bt5GgD48k6k0bmomoF9qfLL4IXcuCKmm4YPAi QFblGO44WPTMgg2va4EJ/vDKW8QqPTANArrRhAJgvhNQcweANJVX/am3hVhFJwm8bj86 7LgGhim8RSHeVdhI+vOKBl3Wa50tYnw4lOOcBwAKdwK5ccIfJMITlCkW3I+qp97nyyMv W95g== X-Gm-Message-State: AOAM530rIFqanPTAaGW5h1n2cdfmrEss/8jffBxBjZz782jXDzUwFBGE iRtUOzSfsfWdV67u9zbCP3PR0orvBSfZGk2s X-Google-Smtp-Source: ABdhPJzoTSdjxRQPcDxq3kjbX99YShRV6LjnMgTsiaNwYl1iycbOgyCAR6wED3yV9cozURGmM2cMeQ== X-Received: by 2002:a1c:26c2:: with SMTP id m185mr15269864wmm.146.1625222426876; Fri, 02 Jul 2021 03:40:26 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/11] hw/arm/virt: Make PL061 GPIO lines pulled low, not high Date: Fri, 2 Jul 2021 11:40:15 +0100 Message-Id: <20210702104018.19881-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625223053443100001 Content-Type: text/plain; charset="utf-8" For the virt board we have two PL061 devices -- one for NonSecure which is inputs only, and one for Secure which is outputs only. For the former, we don't care whether its outputs are pulled low or high when the line is configured as an input, because we don't connect them. For the latter, we do care, because we wire the lines up to the gpio-pwr device, which assumes that level 1 means "do the action" and 1 means "do nothing". For consistency in case we add more outputs in future, configure both PL061s to pull GPIO lines down to 0. Reported-by: Maxim Uvarov Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/virt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 4b96f060140..93ab9d21ea0 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -895,6 +895,9 @@ static void create_gpio_devices(const VirtMachineState = *vms, int gpio, MachineState *ms =3D MACHINE(vms); =20 pl061_dev =3D qdev_new("pl061"); + /* Pull lines down to 0 if not driven by the PL061 */ + qdev_prop_set_uint32(pl061_dev, "pullups", 0); + qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff); s =3D SYS_BUS_DEVICE(pl061_dev); sysbus_realize_and_unref(s, &error_fatal); memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); --=20 2.20.1 From nobody Tue Dec 16 02:36:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625222771; cv=none; d=zohomail.com; s=zohoarc; b=AxrpJjQNpRhJUEzNEvZ8kuBLDMVZhPOEAB50sQbkWKJUj6Q89yXTGCSALn6Vf4rnkKZEZMxtCTeYtimbV8QKYllrMNDqE/sIP9ICysFXRi02C1Fb0j0oaINrfq+1ZyxRyEmLcbeJCkh08K71vg/oW0UKZzcIpnCLzad41bx7mF8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625222771; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=L7U6W9EH1FihHhwpCAtDoJvA3yxH/uDVM+98Ig5Lyfk=; b=fx/RGd8J5yTxBG8Md3YCtl1F0wwAluKF4sZCGsup1EwLPgWCnIVSfV+g1Ra+ierxsX9UF0XCEZUqwHfvmamwDEXj6Wxz61273lesHL8nNjnW4dPlKjgLLL9SROfyAQ6D5iof6EK8F9xHqcANCs9+uvq8F1WD2l6cdtzQm0Qwzn8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162522277161553.34399103052965; Fri, 2 Jul 2021 03:46:11 -0700 (PDT) Received: from localhost ([::1]:41688 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lzGgU-0005dP-Ia for importer@patchew.org; Fri, 02 Jul 2021 06:46:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59872) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lzGb3-0004ml-SM for qemu-devel@nongnu.org; Fri, 02 Jul 2021 06:40:34 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:36796) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lzGay-0006fN-TT for qemu-devel@nongnu.org; Fri, 02 Jul 2021 06:40:33 -0400 Received: by mail-wr1-x42c.google.com with SMTP id v5so11903087wrt.3 for ; Fri, 02 Jul 2021 03:40:28 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=L7U6W9EH1FihHhwpCAtDoJvA3yxH/uDVM+98Ig5Lyfk=; b=bq6gKAWvABTAkpFGvttT1LTiw5mJ/W3RUwScC7njlKR7MOunXjk7tA3RF4zpXJ5uee VaXWXnFdfoYIaPy9Kc7n2sd1dFQKTpQ0k6MJoDdA3ZHXn1WVDODeNIMnc5EYNHwbjfwS HwL0Ak6Sgi9VgjFDgKSZdkOiem21+Xh/APQ8wYuFovV6KpMvrlbUJITWwbAdfKuzcS6e sfEL8aitjaEccxFciZKtelQeP1x9ez7vfBHw7YigBLlORsPOvFkQkQT/niahDGiENRSa F8RP8tp/y5mj/oGwNUV+aEWNv4hGXTkD2FfRSrsVgJ96v/3EYMResgxo/gtYRt5MDoPA azKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=L7U6W9EH1FihHhwpCAtDoJvA3yxH/uDVM+98Ig5Lyfk=; b=s4o4HtDg9/OKIOtTZaFwsahF7meDpoPdeRAsKNFF5tU0GRQrZBZdtEj8nplgibaveO 51MnRx3g6VMOACI+I8VIhBwdrK3VK+xht8lspqSI9fAH5bJGYCtwoOTFxEKHVfMvnBR8 QxkRvRP6RVV6WuXawZt4ldd0ROfh+6CCpDWEglHILFbLGtVvJXgSGqqKp3T006V4wZAm BN/XC1LsY5j1vJlLJ8VAbqNHiJ6TeyBXF1NBG3FXEsg0lKvcmz/ygmfM/+MxnMxqQYAw bFCu2HnCrKsCMYcoU7hxEvlDbjUkDvOg2LcVFFeoJzj7Jbtz6+UlQguNnnQj1G0vHjFh YyYQ== X-Gm-Message-State: AOAM531wGoZ0HsLyNs9Dv8xkir9Fp9duKkU1obtyu9uwy7LA85mYV7z0 ZGilH7x4+0GxSh680y/rGfVZ4A== X-Google-Smtp-Source: ABdhPJw1blM4SP3fVase9l72kNe2+Q1redCThuzDvc4KfCzHhy3LR1fT3GgyBv7clYaBoZv58bifdg== X-Received: by 2002:a5d:524e:: with SMTP id k14mr5126206wrc.390.1625222427679; Fri, 02 Jul 2021 03:40:27 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 09/11] hw/gpio/pl061: Convert to 3-phase reset and assert GPIO lines correctly on reset Date: Fri, 2 Jul 2021 11:40:16 +0100 Message-Id: <20210702104018.19881-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625222772156100001 Content-Type: text/plain; charset="utf-8" The PL061 comes out of reset with all its lines configured as input, which means they might need to be pulled to 0 or 1 depending on the 'pullups' and 'pulldowns' properties. Currently we do not assert these lines on reset; they will only be set whenever the guest first touches a register that triggers a call to pl061_update(). Convert the device to three-phase reset so we have a place where we can safely call qemu_set_irq() to set the floating lines to their correct values. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/gpio/pl061.c | 29 +++++++++++++++++++++++++---- hw/gpio/trace-events | 1 + 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index bb496a19ade..8d12b2d6b97 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -448,13 +448,14 @@ static void pl061_write(void *opaque, hwaddr offset, return; } =20 -static void pl061_reset(DeviceState *dev) +static void pl061_enter_reset(Object *obj, ResetType type) { - PL061State *s =3D PL061(dev); + PL061State *s =3D PL061(obj); + + trace_pl061_reset(DEVICE(s)->canonical_path); =20 /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data She= et */ s->data =3D 0; - s->old_out_data =3D 0; s->old_in_data =3D 0; s->dir =3D 0; s->isense =3D 0; @@ -476,6 +477,24 @@ static void pl061_reset(DeviceState *dev) s->amsel =3D 0; } =20 +static void pl061_hold_reset(Object *obj) +{ + PL061State *s =3D PL061(obj); + int i, level; + uint8_t floating =3D pl061_floating(s); + uint8_t pullups =3D pl061_pullups(s); + + for (i =3D 0; i < N_GPIOS; i++) { + if (extract32(floating, i, 1)) { + continue; + } + level =3D extract32(pullups, i, 1); + trace_pl061_set_output(DEVICE(s)->canonical_path, i, level); + qemu_set_irq(s->out[i], level); + } + s->old_out_data =3D pullups; +} + static void pl061_set_irq(void * opaque, int irq, int level) { PL061State *s =3D (PL061State *)opaque; @@ -545,11 +564,13 @@ static Property pl061_props[] =3D { static void pl061_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 dc->vmsd =3D &vmstate_pl061; - dc->reset =3D &pl061_reset; dc->realize =3D pl061_realize; device_class_set_props(dc, pl061_props); + rc->phases.enter =3D pl061_enter_reset; + rc->phases.hold =3D pl061_hold_reset; } =20 static const TypeInfo pl061_info =3D { diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index eb5fb4701c6..1dab99c5604 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -20,6 +20,7 @@ pl061_input_change(const char *id, int gpio, int level) "= %s input %d changed to pl061_update_istate(const char *id, uint32_t istate, uint32_t im, int leve= l) "%s GPIORIS 0x%x GPIOIE 0x%x interrupt level %d" pl061_read(const char *id, uint64_t offset, uint64_t r) "%s offset 0x%" PR= Ix64 " value 0x%" PRIx64 pl061_write(const char *id, uint64_t offset, uint64_t value) "%s offset 0x= %" PRIx64 " value 0x%" PRIx64 +pl061_reset(const char *id) "%s reset" =20 # sifive_gpio.c sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value = 0x%" PRIx64 --=20 2.20.1 From nobody Tue Dec 16 02:36:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pPs0EK8qhWJ7QET2DXUmT74qvqEztx/Rozsf7xNVhPY=; b=QNlW6bmCpuhuwYHEHYgR1XD/1wxGj7e2zKRXVYVQvq/Tw1eT0zN19yZWenyKq1A7dn wmK6AZH0YcB3tY7f4CUmpODZKr/zbtIDcwtNKJAPmeE8DdpW6ZdAKIqcjpApOSoqsiRP 9bWJwBQVndRip0ZzzOND27xel0KAUB/TtlzejfF+d29L55Z2ukfrtzYn5bv0XNWYhnsj +4WDKUszqdBBga8FlqPg+RcHGdmGJz+s6Yu8d4RuJZJcLM+0Forg6AdcT7SxyxLKosm2 5HgtJZqbzBGG/AaRDgTIaNa1AJY/zUgmL802b2etKs6+WbHlMwWbKMEdZIhakJaTCVQo satw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pPs0EK8qhWJ7QET2DXUmT74qvqEztx/Rozsf7xNVhPY=; b=a09DCH+JO9/5SxUXbnROHJCx6svtbFq9vq0r6AbCFFobYKK35NrJa242sNc0hAYK0E +3rNb1fuunaZmKWLVxdDIJoRDfgcHp5vjPWZq2faqjMvvZLaCYdl0oeXEVoF20rvZ0b/ EBlNIIqpJHnajnnzkb41AU9y35pyLuLPCnMcyUnOTZU8zIL4aWnYLhx4tQrUsCZyqlF7 Ds+NvsaMZOaZQClgFzisp9eSe1K8uN3/WKDAVzE73SqlyOokPMTLdyLUF9kxIxJz+nEa 6rQoObXIDnaE3rujI5pX5PkxVJeJzpDlI8xyJebQSZ/AvdZ+jQYdvdyyENKNcjEMkSHT UG+g== X-Gm-Message-State: AOAM530wVd/zf90zL9nwQb1SXILNAYgDkSr6HKf7Aha471ozD4liK2Oq GmuH2InbZNOOXEI4Slu8K9wQsA== X-Google-Smtp-Source: ABdhPJy4H80rg7isC+SSIOpnUG/0lRRSbGqkviiSsjcmV++nPf/N3JuIeplHtwOQii2UoYKryR43OQ== X-Received: by 2002:a5d:52c1:: with SMTP id r1mr1441628wrv.294.1625222428373; Fri, 02 Jul 2021 03:40:28 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 10/11] hw/gpio/pl061: Document a shortcoming in our implementation Date: Fri, 2 Jul 2021 11:40:17 +0100 Message-Id: <20210702104018.19881-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625223044515100001 Content-Type: text/plain; charset="utf-8" The Luminary PL061s in the Stellaris LM3S9695 don't all have the same reset value for GPIOPUR. We can get away with not letting the board configure the PUR reset value because we don't actually wire anything up to the lines which should reset to pull-up. Add a comment noting this omission. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Not worth actually fixing, but I wanted a note since I spotted this while I was reading the datasheet anyway. --- hw/gpio/pl061.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index 8d12b2d6b97..2cb3a231b43 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -455,6 +455,15 @@ static void pl061_enter_reset(Object *obj, ResetType t= ype) trace_pl061_reset(DEVICE(s)->canonical_path); =20 /* reset values from PL061 TRM, Stellaris LM3S5P31 & LM3S8962 Data She= et */ + + /* + * FIXME: For the LM3S6965, not all of the PL061 instances have the + * same reset values for GPIOPUR, GPIOAFSEL and GPIODEN, so in theory + * we should allow the board to configure these via properties. + * In practice, we don't wire anything up to the affected GPIO lines + * (PB7, PC0, PC1, PC2, PC3 -- they're used for JTAG), so we can + * get away with this inaccuracy. + */ s->data =3D 0; s->old_in_data =3D 0; s->dir =3D 0; --=20 2.20.1 From nobody Tue Dec 16 02:36:46 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1625223205; cv=none; d=zohomail.com; s=zohoarc; b=DPFkx4gDE5ESytAA3HGks1KA99f+pT7eXgVHnDU1DnlPAHQ29n6F5R5SkYtNG/pIT69bhlo6R48DzWIFVtNVshg/fZlh6MVOAiAi7kWoAWazE50JdfGhbXHrEZfpr/XKSw6nqV37sdzIbEjGZLz1MOOPCGZ0pan4CMwHlh44CVs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625223205; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4BANoWgI0RjhipvmntovUAzoJsSWS5FJsfiHUg00m54=; b=hGlBNjmsiDtM6nUwTtifGevKrEib7qqBdWtNOyvu2QLN1aYh/Js7CR27hbXaympwmbdxoeFh1zmibFQTWVcw4pWJOPKCbqhcekhZmzbqVryjTYQbh4zj9LrUGSM53y9t2H/YaDoA44ZxCcf2nwv9wbh4TUuUOkY7GEM/RSLwe90= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1625223205396484.14256138546034; Fri, 2 Jul 2021 03:53:25 -0700 (PDT) Received: from localhost ([::1]:60958 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lzGnT-0001hG-Cd for importer@patchew.org; Fri, 02 Jul 2021 06:53:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59906) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lzGb5-0004qS-ND for qemu-devel@nongnu.org; Fri, 02 Jul 2021 06:40:36 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:34754) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lzGb0-0006gh-EH for qemu-devel@nongnu.org; Fri, 02 Jul 2021 06:40:35 -0400 Received: by mail-wr1-x42e.google.com with SMTP id p8so11918305wrr.1 for ; Fri, 02 Jul 2021 03:40:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p16sm2745810wrs.52.2021.07.02.03.40.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:40:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4BANoWgI0RjhipvmntovUAzoJsSWS5FJsfiHUg00m54=; b=QksazumLwCZ8AW6hLacg+J8/71Omk45FlLqCWaed+2MOyNiGEJjyf8y9CWbJMwg7hH 1+p3DKi4OA4LItQ9VEM2iscgFp4/CxBPj5/3y4i8tkCvZRr5pXWKCqc94WDjD9BaYhGB MUA8j8yZPrPfIegkWZhcf768G74r2t6FQhDnLxKXSz3RECZJIsZaa7y4o5U2n89F8Y93 OEk/N301J7qhB6Ida+ZEN6ppYucSbvCllL6ZujZPUwLl6FMA74KKhLsOVAoPxGruQhGu xju+xHlejbTeaq8fNadqH1JiD7kW/Xr/llpNJ8/fknRYxnclaFstB3C7YilQP0RA/cIi LxdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4BANoWgI0RjhipvmntovUAzoJsSWS5FJsfiHUg00m54=; b=AwfhgG8hoqcunquXNhE5pkpQH/+gj5dLoTT+8A0wosiFhQhNPxmTj+gX6bfW5LpjCe zdv0JcxN9sFJb6MfnT16+2OMuEgDTamTxDKSuyTfl+feaCimrxtkZz+XM3+yAKsW8Mku ccTdn0lTOTuYfZv599xS74aPGXnCaV6gid2Z8tUWeX9Z+z7gz4XomIXmk/Pcrm5q9Hg3 kmuNzLGtgxg4uWA45Lxu/qeUX5d/KDhs9wqOTNBxMVXgUlvDDhjkAzuG4aRVEUyODv6J 0xd/fMWmh8fYrTLTSrELjA9BjCHrhiLQEOD1EuzbRypbOnuxuRRZSaZNiL8s6uCbcGTw W4fg== X-Gm-Message-State: AOAM532csYVYpUHtt3a2voNYnaDTyCGxJdf4OeN+22BYB5HQKipLnQ54 Iq41UKdyZcTvDzgKtiRXBefzy/WbeYk0n+ls X-Google-Smtp-Source: ABdhPJyN7i1LmYXKR0XM3sdwkQkmOM8yCf/9IUh9CKxWUOz/0tWI34oWZOV/mrG669H8o7j4bDd9aw== X-Received: by 2002:adf:fd42:: with SMTP id h2mr5150186wrs.262.1625222429140; Fri, 02 Jul 2021 03:40:29 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 11/11] hw/arm/stellaris: Expand comment about handling of OLED chipselect Date: Fri, 2 Jul 2021 11:40:18 +0100 Message-Id: <20210702104018.19881-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210702104018.19881-1-peter.maydell@linaro.org> References: <20210702104018.19881-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxim Uvarov Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1625223206376100001 Content-Type: text/plain; charset="utf-8" The stellaris board doesn't emulate the handling of the OLED chipselect line correctly. Expand the comment describing this, including a sketch of the theoretical correct way to do it. Signed-off-by: Peter Maydell --- Given the stellaris board is old and not very useful these days, I didn't think it worth the effort of actually implementing the correct behaviour, but I wanted to record what I figured out from various data sheets while I was looking at PL061 stuff... --- hw/arm/stellaris.c | 56 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 8b4dab9b79f..ad48cf26058 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1453,13 +1453,67 @@ static void stellaris_init(MachineState *ms, stella= ris_board_info *board) DeviceState *sddev; DeviceState *ssddev; =20 - /* Some boards have both an OLED controller and SD card connec= ted to + /* + * Some boards have both an OLED controller and SD card connec= ted to * the same SSI port, with the SD card chip select connected t= o a * GPIO pin. Technically the OLED chip select is connected to= the * SSI Fss pin. We do not bother emulating that as both devic= es * should never be selected simultaneously, and our OLED contr= oller * ignores stray 0xff commands that occur when deselecting the= SD * card. + * + * The h/w wiring is: + * - GPIO pin D0 is wired to the active-low SD card chip sele= ct + * - GPIO pin A3 is wired to the active-low OLED chip select + * - The SoC wiring of the PL061 "auxiliary function" for A3 = is + * SSI0Fss ("frame signal"), which is an output from the So= C's + * SSI controller. The SSI controller takes SSI0Fss low whe= n it + * transmits a frame, so it can work as a chip-select signa= l. + * - GPIO A4 is aux-function SSI0Rx, and wired to the SD card= Tx + * (the OLED never sends data to the CPU, so no wiring need= ed) + * - GPIO A5 is aux-function SSI0Tx, and wired to the SD card= Rx + * and the OLED display-data-in + * - GPIO A2 is aux-function SSI0Clk, wired to SD card and OL= ED + * serial-clock input + * So a guest that wants to use the OLED can configure the PL0= 61 + * to make pins A2, A3, A5 aux-function, so they are connected + * directly to the SSI controller. When the SSI controller sen= ds + * data it asserts SSI0Fss which selects the OLED. + * A guest that wants to use the SD card configures A2, A4 and= A5 + * as aux-function, but leaves A3 as a software-controlled GPIO + * line. It asserts the SD card chip-select by using the PL061 + * to control pin D0, and lets the SSI controller handle Clk, = Tx + * and Rx. (The SSI controller asserts Fss during tx cycles as + * usual, but because A3 is not set to aux-function this is not + * forwarded to the OLED, and so the OLED stays unselected.) + * + * The QEMU implementation instead is: + * - GPIO pin D0 is wired to the active-low SD card chip sele= ct, + * and also to the OLED chip-select which is implemented + * as *active-high* + * - SSI controller signals go to the devices regardless of + * whether the guest programs A2, A4, A5 as aux-function or= not + * + * The problem with this implementation is if the guest doesn't + * care about the SD card and only uses the OLED. In that case= it + * may choose never to do anything with D0 (leaving it in its + * default floating state, which reliably leaves the card disa= bled + * because an SD card has a pullup on CS within the card itsel= f), + * and only set up A2, A3, A5. This for us would mean the OLED + * never gets the chip-select assert it needs. We work around + * this with a manual raise of D0 here (despite board creation + * code being the wrong place to raise IRQ lines) to put the O= LED + * into an initially selected state. + * + * In theory the right way to model this would be: + * - Implement aux-function support in the PL061, with an + * extra set of AFIN and AFOUT GPIO lines (set up so that + * if a GPIO line is in auxfn mode the main GPIO in and out + * track the AFIN and AFOUT lines) + * - Wire the AFOUT for D0 up to either a line from the + * SSI controller that's pulled low around every transmit, + * or at least to an always-0 line here on the board + * - Make the ssd0323 OLED controller chipselect active-low */ bus =3D qdev_get_child_bus(dev, "ssi"); =20 --=20 2.20.1