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[92.184.108.94]) by smtp.gmail.com with ESMTPSA id g7sm2311001wmq.27.2021.07.02.02.24.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 02:24:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1625217888; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=reU/EERyCRIMmUMeN/sG3kQwb7Xc7HiGTNBUAqpoIMw=; b=fYaVbKLTOBfA7PaOQ2dSOi865x4FNNQFaO6dz7Jtuiv7G1FI4BELCtzyncwjA0WzgegK7s 4bEz6JWVjrVLK6gqHTUM6F6scjJp0tSJdWENuwnNm9VC4R184iEgTCZpO3WZpwhmC1d0y7 2ZRo+xhigUFfy3uVAkwMyJTgR8A9bz0= X-MC-Unique: tK87Xzc3O9-ZYJtfr0v4aQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=reU/EERyCRIMmUMeN/sG3kQwb7Xc7HiGTNBUAqpoIMw=; b=p9T/J/Lpii/MyLxzq4FEeUHOoycNrSvDliCZyxR8kVsPeNPFQnLKuq8YmwaslUNdlo YiLJMgjF3UY6MwKCDK1uC06iOBM1JsYCxiRzHVcJBJr5xr4TND0kW8ikkGp3QMy9K/Ss RDVyg36iDsAoz2QeUzFnSNAWd0iS72oWHSE8Pevk7rsA+SNMxDw8nlth0DZaf1hfKRKK snKYNtKmz7eX6T1GmoCUHV3t3R/R6eyZC43oRLRHwDb3OHnPKhvGg6sL+khtczYkPjLU S+C5hk/YnrHonj7Ucc1PYZd+y3raFD1gC/gnk7RQJNiIy2T9zwJWHmNl+PWyDMYriX58 +V7Q== X-Gm-Message-State: AOAM533v2eGqMzCRpY/apHtVurKRzwzRFtUWyw78QIhvO8kNxawntFP5 ha2WHcRa8JV1FbwzPadz3wXGT600oimN0pSI9JpL8mhMNf8h56ZXomL5j8g25cnYxItHXwQRBJI TVtYmjXi7t2gHvA== X-Received: by 2002:a5d:69c9:: with SMTP id s9mr4656631wrw.155.1625217885922; Fri, 02 Jul 2021 02:24:45 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwkRXpd/GmlSQr2jKtQ3FFI68N74LgRgjTIGiy8yU/dKA9gljxIfL90OWvrEh4QoePpu3yRxA== X-Received: by 2002:a5d:69c9:: with SMTP id s9mr4656616wrw.155.1625217885754; Fri, 02 Jul 2021 02:24:45 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Alexander Bulekov , Stefan Hajnoczi , Mauro Matteo Cascella , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Li Qiang , "Edgar E . Iglesias" Subject: [PATCH v3 1/6] dma: Let dma_memory_valid() take MemTxAttrs argument Date: Fri, 2 Jul 2021 11:24:34 +0200 Message-Id: <20210702092439.989969-2-philmd@redhat.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210702092439.989969-1-philmd@redhat.com> References: <20210702092439.989969-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1625217890776100003 Let devices specify transaction attributes when calling dma_memory_valid(). Reviewed-by: Richard Henderson Reviewed-by: Li Qiang Reviewed-by: Edgar E. Iglesias Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Stefan Hajnoczi --- include/hw/ppc/spapr_vio.h | 2 +- include/sysemu/dma.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/hw/ppc/spapr_vio.h b/include/hw/ppc/spapr_vio.h index 4bea87f39cc..4c45f1579fa 100644 --- a/include/hw/ppc/spapr_vio.h +++ b/include/hw/ppc/spapr_vio.h @@ -91,7 +91,7 @@ static inline void spapr_vio_irq_pulse(SpaprVioDevice *de= v) static inline bool spapr_vio_dma_valid(SpaprVioDevice *dev, uint64_t taddr, uint32_t size, DMADirection dir) { - return dma_memory_valid(&dev->as, taddr, size, dir); + return dma_memory_valid(&dev->as, taddr, size, dir, MEMTXATTRS_UNSPECI= FIED); } =20 static inline int spapr_vio_dma_read(SpaprVioDevice *dev, uint64_t taddr, diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h index 3201e7901db..296f3b57c9c 100644 --- a/include/sysemu/dma.h +++ b/include/sysemu/dma.h @@ -73,11 +73,11 @@ static inline void dma_barrier(AddressSpace *as, DMADir= ection dir) * dma_memory_{read,write}() and check for errors */ static inline bool dma_memory_valid(AddressSpace *as, dma_addr_t addr, dma_addr_t len, - DMADirection dir) + DMADirection dir, MemTxAttrs attrs) { return address_space_access_valid(as, addr, len, dir =3D=3D DMA_DIRECTION_FROM_DEVICE, - MEMTXATTRS_UNSPECIFIED); + attrs); } =20 static inline MemTxResult dma_memory_rw_relaxed(AddressSpace *as, --=20 2.31.1 From nobody Sun May 19 14:14:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 170.10.133.124 as permitted sender) client-ip=170.10.133.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of redhat.com designates 170.10.133.124 as permitted sender) smtp.mailfrom=philmd@redhat.com; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1625217894; cv=none; d=zohomail.com; s=zohoarc; b=bNjPcNPTheeT/WxEc13oJICiyqQt8R6sltLRECsgyUq8u6f4rqFSqMljZeXKdcNLW/oMpK2y/BTESNGS2OyKRJ3Wp6YWkqQ30NQxNmFIIHcahOR2S8WuTZ07Zmva2e8MTjM8zaH0Zcfv3zBC+aWORSzAiAugo+4BedhkIZzRszM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625217894; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=iiJ+z74eASISUbcozFLozDh4qxKrnkY4zanz2+HAJIE=; b=oIiYQOo6zknWd1KIpY/OxYb/vN9u35fH041DDcVgqVylki4bBlu/b2tN6LN+yrELxLLVetWtkDFHGhPQO7fX/HMxQ2eXQOe3f1Gv9okRP4xa4lRWGl9/UGOuZ5MGo3gQQQQhudK7YiS+AnNmF9voZUg0hF8J0NitcjjVYx8bXgo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of redhat.com designates 170.10.133.124 as permitted sender) smtp.mailfrom=philmd@redhat.com; dmarc=pass header.from= (p=none dis=none) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mx.zohomail.com with SMTPS id 1625217894132474.6710240427908; Fri, 2 Jul 2021 02:24:54 -0700 (PDT) Received: from mail-wm1-f69.google.com (mail-wm1-f69.google.com [209.85.128.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-586-R0N_f1zwN325KVjiEN1hdQ-1; Fri, 02 Jul 2021 05:24:52 -0400 Received: by mail-wm1-f69.google.com with SMTP id f11-20020a05600c154bb02901e0210617aaso2748224wmg.1 for ; Fri, 02 Jul 2021 02:24:51 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.Ascou-CH1 (pop.92-184-108-94.mobile.abo.orange.fr. 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Iglesias" Subject: [PATCH v3 2/6] dma: Let dma_memory_set() take MemTxAttrs argument Date: Fri, 2 Jul 2021 11:24:35 +0200 Message-Id: <20210702092439.989969-3-philmd@redhat.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210702092439.989969-1-philmd@redhat.com> References: <20210702092439.989969-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1625217894827100001 Let devices specify transaction attributes when calling dma_memory_set(). Reviewed-by: Richard Henderson Reviewed-by: Li Qiang Reviewed-by: Edgar E. Iglesias Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Stefan Hajnoczi --- include/hw/ppc/spapr_vio.h | 3 ++- include/sysemu/dma.h | 3 ++- hw/nvram/fw_cfg.c | 3 ++- softmmu/dma-helpers.c | 5 ++--- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/include/hw/ppc/spapr_vio.h b/include/hw/ppc/spapr_vio.h index 4c45f1579fa..c90e74a67dd 100644 --- a/include/hw/ppc/spapr_vio.h +++ b/include/hw/ppc/spapr_vio.h @@ -111,7 +111,8 @@ static inline int spapr_vio_dma_write(SpaprVioDevice *d= ev, uint64_t taddr, static inline int spapr_vio_dma_set(SpaprVioDevice *dev, uint64_t taddr, uint8_t c, uint32_t size) { - return (dma_memory_set(&dev->as, taddr, c, size) !=3D 0) ? + return (dma_memory_set(&dev->as, taddr, + c, size, MEMTXATTRS_UNSPECIFIED) !=3D 0) ? H_DEST_PARM : H_SUCCESS; } =20 diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h index 296f3b57c9c..d23516f020a 100644 --- a/include/sysemu/dma.h +++ b/include/sysemu/dma.h @@ -175,9 +175,10 @@ static inline MemTxResult dma_memory_write(AddressSpac= e *as, dma_addr_t addr, * @addr: address within that address space * @c: constant byte to fill the memory * @len: the number of bytes to fill with the constant byte + * @attrs: memory transaction attributes */ MemTxResult dma_memory_set(AddressSpace *as, dma_addr_t addr, - uint8_t c, dma_addr_t len); + uint8_t c, dma_addr_t len, MemTxAttrs attrs); =20 /** * address_space_map: Map a physical memory region into a host virtual add= ress. diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index 9b8dcca4ead..d3c3b15a728 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -399,7 +399,8 @@ static void fw_cfg_dma_transfer(FWCfgState *s) * tested before. */ if (read) { - if (dma_memory_set(s->dma_as, dma.address, 0, len)) { + if (dma_memory_set(s->dma_as, dma.address, 0, len, + MEMTXATTRS_UNSPECIFIED)) { dma.control |=3D FW_CFG_DMA_CTL_ERROR; } } diff --git a/softmmu/dma-helpers.c b/softmmu/dma-helpers.c index 7d766a5e89a..1f07217ad4a 100644 --- a/softmmu/dma-helpers.c +++ b/softmmu/dma-helpers.c @@ -19,7 +19,7 @@ /* #define DEBUG_IOMMU */ =20 MemTxResult dma_memory_set(AddressSpace *as, dma_addr_t addr, - uint8_t c, dma_addr_t len) + uint8_t c, dma_addr_t len, MemTxAttrs attrs) { dma_barrier(as, DMA_DIRECTION_FROM_DEVICE); =20 @@ -31,8 +31,7 @@ MemTxResult dma_memory_set(AddressSpace *as, dma_addr_t a= ddr, memset(fillbuf, c, FILLBUF_SIZE); while (len > 0) { l =3D len < FILLBUF_SIZE ? len : FILLBUF_SIZE; - error |=3D address_space_write(as, addr, MEMTXATTRS_UNSPECIFIED, - fillbuf, l); + error |=3D address_space_write(as, addr, attrs, fillbuf, l); len -=3D l; addr +=3D l; } --=20 2.31.1 From nobody Sun May 19 14:14:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=philmd@redhat.com; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1625217901; cv=none; d=zohomail.com; s=zohoarc; b=Lf9naOb7tlmBQwBGGPMRwyUdp5BsBHOkeRqkAeQRfb4TWxUFHL/xdgCQEKU9fW/q/Xtp2JbvlNLGXy3O7TNmSrxXjFFVggRxqWOilmiFLPDsA1puz6YQJHDxfsiiBVIjBuXCxJcHquxMzcXiwt8aGICCDgDERj4CzRJdScObN6E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625217901; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=d94e4cvzy5znF4XYXKjG7KaQl0I03KmgN6PaaJlSi/E=; b=L06ctgJhULmvzDS6OLq5P+f26mZriJwRJC99IOOV574RJLPmADcXeOEoPETmOhlxJyAgm09/dqu/8wppKHqeSFJdnz1PlM/8wp4On5cSmvgGijSv3qxbWzp850rqSTHRPsDVuL5MorK3HsE2DfcNAFC7fuZK2b4qnhmjPdnxmac= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=philmd@redhat.com; dmarc=pass header.from= (p=none dis=none) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [216.205.24.124]) by mx.zohomail.com with SMTPS id 1625217901063135.40257125680387; Fri, 2 Jul 2021 02:25:01 -0700 (PDT) Received: from mail-wm1-f72.google.com (mail-wm1-f72.google.com [209.85.128.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-511-Yelhg_alOxuiUgFUVrUWZA-1; Fri, 02 Jul 2021 05:24:57 -0400 Received: by mail-wm1-f72.google.com with SMTP id o3-20020a05600c5103b02901aeb7a4ac06so6004174wms.5 for ; Fri, 02 Jul 2021 02:24:56 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.Ascou-CH1 (pop.92-184-108-94.mobile.abo.orange.fr. [92.184.108.94]) by smtp.gmail.com with ESMTPSA id q19sm11820889wmc.44.2021.07.02.02.24.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 02:24:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1625217900; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=d94e4cvzy5znF4XYXKjG7KaQl0I03KmgN6PaaJlSi/E=; b=JWR5b/H1V4b+pEBeu8quEx7+ckWSIb7SKsrK06OXd//bQ+xaR5cBF1/yejn8llvS8M7Kyl t9Pr6m9jeBBSrmIRwHcX0i5OaDcXFH20yN39QE5MWQqZ9pEXqIwS8GOu0ijpAMJOg0ma7c 0lIGIAvumuS/4HKzZMV0OLVfQp1t8uc= X-MC-Unique: Yelhg_alOxuiUgFUVrUWZA-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d94e4cvzy5znF4XYXKjG7KaQl0I03KmgN6PaaJlSi/E=; b=td9FQMORwjDcKg+OxXdUP23pidyXi8y6WlMC1Pvr2Mtmhl4vVk/bdyKXGjfB27IqwO 5CDdQ/o6WslhkOGHGlGMWE7LYQKeUZdmzGxkPmPiUdkn+b9zAXhzVuhHyiF+uLGhn6dn 55BIcad2PCrOMFlO8h/ZWPUyQyK8/iJA2MuR2Ezpn0TJ4q8YiToYJgKLW4P0xz5zVE2V gkelDDl/s5ykAfPAJ9dIJe2WHe8eSPHKxmseclOmee3lNYSU1yfY8V9ZyfeiXHIe6fi/ kQS7xCCzPoPVZxZ5480dX2h6om1M0pYe3nZli3V4NerRZoc5lq+vgQzXdSaZJMtXAezk PJ0w== X-Gm-Message-State: AOAM533FNwq91IH++/7pNoCkgXktQOguaJLyb3zCykIuog7NPocuBQ65 6y3WIZ4CRbokDbXPca8oSZqoLAPutn0pRjXUCxhU5Si1OabBULYH97XAqF6nP5NpPs3koDFNIug imsU8sXG5ROqMag== X-Received: by 2002:adf:d1cd:: with SMTP id b13mr4773178wrd.228.1625217895922; Fri, 02 Jul 2021 02:24:55 -0700 (PDT) X-Google-Smtp-Source: ABdhPJza5wmMSim88cN2MF42/Bamk0G+i1GJ8j15qypJ14oe4tfK3g0gqAQ7h1213P9eITOvYdTWSQ== X-Received: by 2002:adf:d1cd:: with SMTP id b13mr4773161wrd.228.1625217895805; Fri, 02 Jul 2021 02:24:55 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Alexander Bulekov , Stefan Hajnoczi , Mauro Matteo Cascella , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Li Qiang , "Edgar E . Iglesias" Subject: [PATCH v3 3/6] dma: Let dma_memory_rw_relaxed() take MemTxAttrs argument Date: Fri, 2 Jul 2021 11:24:36 +0200 Message-Id: <20210702092439.989969-4-philmd@redhat.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210702092439.989969-1-philmd@redhat.com> References: <20210702092439.989969-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1625217903262100001 We will add the MemTxAttrs argument to dma_memory_rw() in the next commit. Since dma_memory_rw_relaxed() is only used by dma_memory_rw(), modify it first in a separate commit to keep the next commit easier to review. Reviewed-by: Richard Henderson Reviewed-by: Li Qiang Reviewed-by: Edgar E. Iglesias Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Stefan Hajnoczi --- include/sysemu/dma.h | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h index d23516f020a..3be803cf3ff 100644 --- a/include/sysemu/dma.h +++ b/include/sysemu/dma.h @@ -83,9 +83,10 @@ static inline bool dma_memory_valid(AddressSpace *as, static inline MemTxResult dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr, void *buf, dma_addr_t len, - DMADirection dir) + DMADirection dir, + MemTxAttrs attrs) { - return address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, + return address_space_rw(as, addr, attrs, buf, len, dir =3D=3D DMA_DIRECTION_FROM_DEVICE= ); } =20 @@ -93,7 +94,9 @@ static inline MemTxResult dma_memory_read_relaxed(Address= Space *as, dma_addr_t addr, void *buf, dma_addr_t le= n) { - return dma_memory_rw_relaxed(as, addr, buf, len, DMA_DIRECTION_TO_DEVI= CE); + return dma_memory_rw_relaxed(as, addr, buf, len, + DMA_DIRECTION_TO_DEVICE, + MEMTXATTRS_UNSPECIFIED); } =20 static inline MemTxResult dma_memory_write_relaxed(AddressSpace *as, @@ -102,7 +105,8 @@ static inline MemTxResult dma_memory_write_relaxed(Addr= essSpace *as, dma_addr_t len) { return dma_memory_rw_relaxed(as, addr, (void *)buf, len, - DMA_DIRECTION_FROM_DEVICE); + DMA_DIRECTION_FROM_DEVICE, + MEMTXATTRS_UNSPECIFIED); } =20 /** @@ -124,7 +128,8 @@ static inline MemTxResult dma_memory_rw(AddressSpace *a= s, dma_addr_t addr, { dma_barrier(as, dir); =20 - return dma_memory_rw_relaxed(as, addr, buf, len, dir); + return dma_memory_rw_relaxed(as, addr, buf, len, dir, + MEMTXATTRS_UNSPECIFIED); } =20 /** --=20 2.31.1 From nobody Sun May 19 14:14:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 170.10.133.124 as permitted sender) client-ip=170.10.133.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of redhat.com designates 170.10.133.124 as permitted sender) smtp.mailfrom=philmd@redhat.com; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1625217906; cv=none; d=zohomail.com; s=zohoarc; b=Pw/a8RwcpcJ7LqqgMYXArFFpjllpjCClckib+HFt1s2YRwdFIO4CFkX1YKB09tOpcraLt3C5/UT3VZPdnLg6p2ZfO8OfaPoRpFu2Nf+abDnnibaI9+0u4DIgi4V1V5kE5ekxK6LPQG8tN9eljAy+8NxDbqeGPsgx4JItVU6SF1g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1625217906; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=2DiP3BDoXXRMG7E5lnGiuw8kLZOvB50ScwR/oV8195s=; b=KHzWlFpYlXx09bk+8KZ2oofhzyaRzlS1NdAaJxGKLgmpmUcb+TjZ72MsgG2465l76ijAF7al09X6K01oufAJpoI5jmQva6FT4MoAm/WuBkjVqRH2UDQVs/rPzCAadMax/JL8zr1RaUkCi7iOXKrunHR+xc4jwB7DoM2LaGRKqmA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of redhat.com designates 170.10.133.124 as permitted sender) smtp.mailfrom=philmd@redhat.com; dmarc=pass header.from= (p=none dis=none) Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mx.zohomail.com with SMTPS id 1625217906210751.0264318248065; Fri, 2 Jul 2021 02:25:06 -0700 (PDT) Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-478-oLcUiHdoNgOVmK14wJL9QQ-1; Fri, 02 Jul 2021 05:25:02 -0400 Received: by mail-wr1-f72.google.com with SMTP id g4-20020a5d64e40000b029012469ad3be8so3701778wri.1 for ; Fri, 02 Jul 2021 02:25:01 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.Ascou-CH1 (pop.92-184-108-94.mobile.abo.orange.fr. [92.184.108.94]) by smtp.gmail.com with ESMTPSA id e15sm2537357wrm.60.2021.07.02.02.24.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 02:25:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1625217905; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2DiP3BDoXXRMG7E5lnGiuw8kLZOvB50ScwR/oV8195s=; b=iSGTY6n5J09MNpbWq4kEXmJRzRTdFo5m13YFVLkZJaqjh/LPjU5BeP0lDxRV8wn19MZabg z/i2IQ+tbgfNBuo/MML13AvqVxEg8scZv4IdseTQF5QBPoSgx8Zh69hA92rhEL+Fg5e/KZ 200WIPqu5FdDKZeY+nWjs0QLoPa3kLY= X-MC-Unique: oLcUiHdoNgOVmK14wJL9QQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2DiP3BDoXXRMG7E5lnGiuw8kLZOvB50ScwR/oV8195s=; b=lHpQx9AbjjBNZ3BHMo6slbw9AUFX9gpocZm+NMCBkBUk7dFQ54OjSQgQnTc8jLGXw4 TjOD5B8675AeJsgv1+1xzKsdvVNzBsAgFCdyzjkBliRo07Vyqz+YznUbaC5ChRiCEhTn TRe3tNHnmZ0GnHLu+XpSbo61h6mIlaeNgIpPO33SAtelmUfkWmHIxLRFkeF03mWmzBId OjZFJ4iA5/t5zAQs/flwpDABdBnMFNP8PVBYop4x14hivG8p/2irDM9K4/7GkmBhplb6 UBt8WlCmyAPKU6MsETM9BVDNiM6FOKK4QyxgRJxCNRSC97LszOIaXhgborbiJo6V/xT7 4+7w== X-Gm-Message-State: AOAM530JgiLuIVw6XmOUMN7XRr1x47sd8aJBp2xCuDGqtTVQJE/3RYTl MMcXTT8gWVHW4BzXRIawowKZCkUJsNMT/lzK/0XI3snxUtTVXpYqUo7fDx7lc5XTAH6UWalap+w 1Gb4TuK0Q1Toovw== X-Received: by 2002:a05:600c:1c8b:: with SMTP id k11mr15337757wms.41.1625217900728; Fri, 02 Jul 2021 02:25:00 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxd/h1IWfeKbPXwgQI9YWIVcyNxm+9KYo0T4u5NzIc2NbzpQ+KesS2RpoU641dzQaXk99hpcQ== X-Received: by 2002:a05:600c:1c8b:: with SMTP id k11mr15337740wms.41.1625217900574; Fri, 02 Jul 2021 02:25:00 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Alexander Bulekov , Stefan Hajnoczi , Mauro Matteo Cascella , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Li Qiang , "Edgar E . Iglesias" Subject: [PATCH v3 4/6] dma: Let dma_memory_rw() take MemTxAttrs argument Date: Fri, 2 Jul 2021 11:24:37 +0200 Message-Id: <20210702092439.989969-5-philmd@redhat.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210702092439.989969-1-philmd@redhat.com> References: <20210702092439.989969-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1625217907499100001 Let devices specify transaction attributes when calling dma_memory_rw(). Reviewed-by: Richard Henderson Reviewed-by: Li Qiang Reviewed-by: Edgar E. Iglesias Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Stefan Hajnoczi --- include/hw/pci/pci.h | 3 ++- include/sysemu/dma.h | 11 ++++++----- hw/intc/spapr_xive.c | 3 ++- hw/usb/hcd-ohci.c | 10 ++++++---- softmmu/dma-helpers.c | 3 ++- 5 files changed, 18 insertions(+), 12 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 6be4e0c460c..252c91686de 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -801,7 +801,8 @@ static inline MemTxResult pci_dma_rw(PCIDevice *dev, dm= a_addr_t addr, void *buf, dma_addr_t len, DMADirection dir) { - return dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir); + return dma_memory_rw(pci_get_address_space(dev), addr, buf, len, + dir, MEMTXATTRS_UNSPECIFIED); } =20 /** diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h index 3be803cf3ff..e8ad42226f6 100644 --- a/include/sysemu/dma.h +++ b/include/sysemu/dma.h @@ -121,15 +121,15 @@ static inline MemTxResult dma_memory_write_relaxed(Ad= dressSpace *as, * @buf: buffer with the data transferred * @len: the number of bytes to read or write * @dir: indicates the transfer direction + * @attrs: memory transaction attributes */ static inline MemTxResult dma_memory_rw(AddressSpace *as, dma_addr_t addr, void *buf, dma_addr_t len, - DMADirection dir) + DMADirection dir, MemTxAttrs attrs) { dma_barrier(as, dir); =20 - return dma_memory_rw_relaxed(as, addr, buf, len, dir, - MEMTXATTRS_UNSPECIFIED); + return dma_memory_rw_relaxed(as, addr, buf, len, dir, attrs); } =20 /** @@ -147,7 +147,8 @@ static inline MemTxResult dma_memory_rw(AddressSpace *a= s, dma_addr_t addr, static inline MemTxResult dma_memory_read(AddressSpace *as, dma_addr_t add= r, void *buf, dma_addr_t len) { - return dma_memory_rw(as, addr, buf, len, DMA_DIRECTION_TO_DEVICE); + return dma_memory_rw(as, addr, buf, len, + DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED); } =20 /** @@ -166,7 +167,7 @@ static inline MemTxResult dma_memory_write(AddressSpace= *as, dma_addr_t addr, const void *buf, dma_addr_t len) { return dma_memory_rw(as, addr, (void *)buf, len, - DMA_DIRECTION_FROM_DEVICE); + DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED= ); } =20 /** diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 89cfa018f59..91e733e74cd 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -1684,7 +1684,8 @@ static target_ulong h_int_esb(PowerPCCPU *cpu, mmio_addr =3D xive->vc_base + xive_source_esb_mgmt(xsrc, lisn) + o= ffset; =20 if (dma_memory_rw(&address_space_memory, mmio_addr, &data, 8, - (flags & SPAPR_XIVE_ESB_STORE))) { + (flags & SPAPR_XIVE_ESB_STORE), + MEMTXATTRS_UNSPECIFIED)) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to access ESB @0x= %" HWADDR_PRIx "\n", mmio_addr); return H_HARDWARE; diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c index 1cf2816772c..56e2315c734 100644 --- a/hw/usb/hcd-ohci.c +++ b/hw/usb/hcd-ohci.c @@ -586,7 +586,8 @@ static int ohci_copy_td(OHCIState *ohci, struct ohci_td= *td, if (n > len) n =3D len; =20 - if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, n, dir)) { + if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, + n, dir, MEMTXATTRS_UNSPECIFIED)) { return -1; } if (n =3D=3D len) { @@ -595,7 +596,7 @@ static int ohci_copy_td(OHCIState *ohci, struct ohci_td= *td, ptr =3D td->be & ~0xfffu; buf +=3D n; if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, - len - n, dir)) { + len - n, dir, MEMTXATTRS_UNSPECIFIED)) { return -1; } return 0; @@ -613,7 +614,8 @@ static int ohci_copy_iso_td(OHCIState *ohci, if (n > len) n =3D len; =20 - if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, n, dir)) { + if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, + n, dir, MEMTXATTRS_UNSPECIFIED)) { return -1; } if (n =3D=3D len) { @@ -622,7 +624,7 @@ static int ohci_copy_iso_td(OHCIState *ohci, ptr =3D end_addr & ~0xfffu; buf +=3D n; if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, - len - n, dir)) { + len - n, dir, MEMTXATTRS_UNSPECIFIED)) { return -1; } return 0; diff --git a/softmmu/dma-helpers.c b/softmmu/dma-helpers.c index 1f07217ad4a..5bf76fff6bd 100644 --- a/softmmu/dma-helpers.c +++ b/softmmu/dma-helpers.c @@ -305,7 +305,8 @@ static uint64_t dma_buf_rw(uint8_t *ptr, int32_t len, Q= EMUSGList *sg, while (len > 0) { ScatterGatherEntry entry =3D sg->sg[sg_cur_index++]; int32_t xfer =3D MIN(len, entry.len); - dma_memory_rw(sg->as, entry.base, ptr, xfer, dir); + dma_memory_rw(sg->as, entry.base, ptr, xfer, dir, + MEMTXATTRS_UNSPECIFIED); ptr +=3D xfer; len -=3D xfer; resid -=3D xfer; --=20 2.31.1 From nobody Sun May 19 14:14:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; 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Iglesias" Subject: [PATCH v3 5/6] dma: Let dma_memory_read/write() take MemTxAttrs argument Date: Fri, 2 Jul 2021 11:24:38 +0200 Message-Id: <20210702092439.989969-6-philmd@redhat.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210702092439.989969-1-philmd@redhat.com> References: <20210702092439.989969-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1625217914044100001 Let devices specify transaction attributes when calling dma_memory_read() or dma_memory_write(). Patch created mechanically using spatch with this script: @@ expression E1, E2, E3, E4; @@ ( - dma_memory_read(E1, E2, E3, E4) + dma_memory_read(E1, E2, E3, E4, MEMTXATTRS_UNSPECIFIED) | - dma_memory_write(E1, E2, E3, E4) + dma_memory_write(E1, E2, E3, E4, MEMTXATTRS_UNSPECIFIED) ) Reviewed-by: Richard Henderson Reviewed-by: Li Qiang Reviewed-by: Edgar E. Iglesias Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Stefan Hajnoczi --- include/hw/ppc/spapr_vio.h | 6 ++++-- include/sysemu/dma.h | 20 ++++++++++++-------- hw/arm/musicpal.c | 13 +++++++------ hw/arm/smmu-common.c | 3 ++- hw/arm/smmuv3.c | 14 +++++++++----- hw/core/generic-loader.c | 3 ++- hw/dma/pl330.c | 12 ++++++++---- hw/dma/sparc32_dma.c | 16 ++++++++++------ hw/dma/xlnx-zynq-devcfg.c | 6 ++++-- hw/dma/xlnx_dpdma.c | 10 ++++++---- hw/i386/amd_iommu.c | 16 +++++++++------- hw/i386/intel_iommu.c | 28 +++++++++++++++++----------- hw/ide/macio.c | 2 +- hw/intc/xive.c | 7 ++++--- hw/misc/bcm2835_property.c | 3 ++- hw/misc/macio/mac_dbdma.c | 10 ++++++---- hw/net/allwinner-sun8i-emac.c | 18 ++++++++++++------ hw/net/ftgmac100.c | 25 ++++++++++++++++--------- hw/net/imx_fec.c | 32 ++++++++++++++++++++------------ hw/net/npcm7xx_emc.c | 20 ++++++++++++-------- hw/nvram/fw_cfg.c | 9 ++++++--- hw/pci-host/pnv_phb3.c | 5 +++-- hw/pci-host/pnv_phb3_msi.c | 9 ++++++--- hw/pci-host/pnv_phb4.c | 5 +++-- hw/sd/allwinner-sdhost.c | 14 ++++++++------ hw/sd/sdhci.c | 35 ++++++++++++++++++++++------------- hw/usb/hcd-dwc2.c | 8 ++++---- hw/usb/hcd-ehci.c | 6 ++++-- hw/usb/hcd-ohci.c | 18 +++++++++++------- hw/usb/hcd-xhci.c | 18 +++++++++++------- 30 files changed, 241 insertions(+), 150 deletions(-) diff --git a/include/hw/ppc/spapr_vio.h b/include/hw/ppc/spapr_vio.h index c90e74a67dd..5d2ea8e6656 100644 --- a/include/hw/ppc/spapr_vio.h +++ b/include/hw/ppc/spapr_vio.h @@ -97,14 +97,16 @@ static inline bool spapr_vio_dma_valid(SpaprVioDevice *= dev, uint64_t taddr, static inline int spapr_vio_dma_read(SpaprVioDevice *dev, uint64_t taddr, void *buf, uint32_t size) { - return (dma_memory_read(&dev->as, taddr, buf, size) !=3D 0) ? + return (dma_memory_read(&dev->as, taddr, + buf, size, MEMTXATTRS_UNSPECIFIED) !=3D 0) ? H_DEST_PARM : H_SUCCESS; } =20 static inline int spapr_vio_dma_write(SpaprVioDevice *dev, uint64_t taddr, const void *buf, uint32_t size) { - return (dma_memory_write(&dev->as, taddr, buf, size) !=3D 0) ? + return (dma_memory_write(&dev->as, taddr, + buf, size, MEMTXATTRS_UNSPECIFIED) !=3D 0) ? H_DEST_PARM : H_SUCCESS; } =20 diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h index e8ad42226f6..522682bf386 100644 --- a/include/sysemu/dma.h +++ b/include/sysemu/dma.h @@ -143,12 +143,14 @@ static inline MemTxResult dma_memory_rw(AddressSpace = *as, dma_addr_t addr, * @addr: address within that address space * @buf: buffer with the data transferred * @len: length of the data transferred + * @attrs: memory transaction attributes */ static inline MemTxResult dma_memory_read(AddressSpace *as, dma_addr_t add= r, - void *buf, dma_addr_t len) + void *buf, dma_addr_t len, + MemTxAttrs attrs) { return dma_memory_rw(as, addr, buf, len, - DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED); + DMA_DIRECTION_TO_DEVICE, attrs); } =20 /** @@ -162,12 +164,14 @@ static inline MemTxResult dma_memory_read(AddressSpac= e *as, dma_addr_t addr, * @addr: address within that address space * @buf: buffer with the data transferred * @len: the number of bytes to write + * @attrs: memory transaction attributes */ static inline MemTxResult dma_memory_write(AddressSpace *as, dma_addr_t ad= dr, - const void *buf, dma_addr_t len) + const void *buf, dma_addr_t len, + MemTxAttrs attrs) { return dma_memory_rw(as, addr, (void *)buf, len, - DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED= ); + DMA_DIRECTION_FROM_DEVICE, attrs); } =20 /** @@ -239,7 +243,7 @@ static inline void dma_memory_unmap(AddressSpace *as, dma_addr_t add= r) \ { \ uint##_bits##_t val; \ - dma_memory_read(as, addr, &val, (_bits) / 8); \ + dma_memory_read(as, addr, &val, (_bits) / 8, MEMTXATTRS_UNSPECIFIE= D); \ return _end##_bits##_to_cpu(val); \ } \ static inline void st##_sname##_##_end##_dma(AddressSpace *as, \ @@ -247,20 +251,20 @@ static inline void dma_memory_unmap(AddressSpace *as, uint##_bits##_t val) \ { \ val =3D cpu_to_##_end##_bits(val); \ - dma_memory_write(as, addr, &val, (_bits) / 8); \ + dma_memory_write(as, addr, &val, (_bits) / 8, MEMTXATTRS_UNSPECIFI= ED); \ } =20 static inline uint8_t ldub_dma(AddressSpace *as, dma_addr_t addr) { uint8_t val; =20 - dma_memory_read(as, addr, &val, 1); + dma_memory_read(as, addr, &val, 1, MEMTXATTRS_UNSPECIFIED); return val; } =20 static inline void stb_dma(AddressSpace *as, dma_addr_t addr, uint8_t val) { - dma_memory_write(as, addr, &val, 1); + dma_memory_write(as, addr, &val, 1, MEMTXATTRS_UNSPECIFIED); } =20 DEFINE_LDST_DMA(uw, w, 16, le); diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 2d612cc0c9b..2680ec55b5a 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -185,13 +185,13 @@ static void eth_rx_desc_put(AddressSpace *dma_as, uin= t32_t addr, cpu_to_le16s(&desc->buffer_size); cpu_to_le32s(&desc->buffer); cpu_to_le32s(&desc->next); - dma_memory_write(dma_as, addr, desc, sizeof(*desc)); + dma_memory_write(dma_as, addr, desc, sizeof(*desc), MEMTXATTRS_UNSPECI= FIED); } =20 static void eth_rx_desc_get(AddressSpace *dma_as, uint32_t addr, mv88w8618_rx_desc *desc) { - dma_memory_read(dma_as, addr, desc, sizeof(*desc)); + dma_memory_read(dma_as, addr, desc, sizeof(*desc), MEMTXATTRS_UNSPECIF= IED); le32_to_cpus(&desc->cmdstat); le16_to_cpus(&desc->bytes); le16_to_cpus(&desc->buffer_size); @@ -215,7 +215,7 @@ static ssize_t eth_receive(NetClientState *nc, const ui= nt8_t *buf, size_t size) eth_rx_desc_get(&s->dma_as, desc_addr, &desc); if ((desc.cmdstat & MP_ETH_RX_OWN) && desc.buffer_size >=3D si= ze) { dma_memory_write(&s->dma_as, desc.buffer + s->vlan_header, - buf, size); + buf, size, MEMTXATTRS_UNSPECIFIED); desc.bytes =3D size + s->vlan_header; desc.cmdstat &=3D ~MP_ETH_RX_OWN; s->cur_rx[i] =3D desc.next; @@ -241,13 +241,13 @@ static void eth_tx_desc_put(AddressSpace *dma_as, uin= t32_t addr, cpu_to_le16s(&desc->bytes); cpu_to_le32s(&desc->buffer); cpu_to_le32s(&desc->next); - dma_memory_write(dma_as, addr, desc, sizeof(*desc)); + dma_memory_write(dma_as, addr, desc, sizeof(*desc), MEMTXATTRS_UNSPECI= FIED); } =20 static void eth_tx_desc_get(AddressSpace *dma_as, uint32_t addr, mv88w8618_tx_desc *desc) { - dma_memory_read(dma_as, addr, desc, sizeof(*desc)); + dma_memory_read(dma_as, addr, desc, sizeof(*desc), MEMTXATTRS_UNSPECIF= IED); le32_to_cpus(&desc->cmdstat); le16_to_cpus(&desc->res); le16_to_cpus(&desc->bytes); @@ -269,7 +269,8 @@ static void eth_send(mv88w8618_eth_state *s, int queue_= index) if (desc.cmdstat & MP_ETH_TX_OWN) { len =3D desc.bytes; if (len < 2048) { - dma_memory_read(&s->dma_as, desc.buffer, buf, len); + dma_memory_read(&s->dma_as, desc.buffer, buf, len, + MEMTXATTRS_UNSPECIFIED); qemu_send_packet(qemu_get_queue(s->nic), buf, len); } desc.cmdstat &=3D ~MP_ETH_TX_OWN; diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 0459850a93d..e09b9c13b74 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -193,7 +193,8 @@ static int get_pte(dma_addr_t baseaddr, uint32_t index,= uint64_t *pte, dma_addr_t addr =3D baseaddr + index * sizeof(*pte); =20 /* TODO: guarantee 64-bit single-copy atomicity */ - ret =3D dma_memory_read(&address_space_memory, addr, pte, sizeof(*pte)= ); + ret =3D dma_memory_read(&address_space_memory, addr, pte, sizeof(*pte), + MEMTXATTRS_UNSPECIFIED); =20 if (ret !=3D MEMTX_OK) { info->type =3D SMMU_PTW_ERR_WALK_EABT; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 01b60bee495..3b43368be0f 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -102,7 +102,8 @@ static inline MemTxResult queue_read(SMMUQueue *q, void= *data) { dma_addr_t addr =3D Q_CONS_ENTRY(q); =20 - return dma_memory_read(&address_space_memory, addr, data, q->entry_siz= e); + return dma_memory_read(&address_space_memory, addr, data, q->entry_siz= e, + MEMTXATTRS_UNSPECIFIED); } =20 static MemTxResult queue_write(SMMUQueue *q, void *data) @@ -110,7 +111,8 @@ static MemTxResult queue_write(SMMUQueue *q, void *data) dma_addr_t addr =3D Q_PROD_ENTRY(q); MemTxResult ret; =20 - ret =3D dma_memory_write(&address_space_memory, addr, data, q->entry_s= ize); + ret =3D dma_memory_write(&address_space_memory, addr, data, q->entry_s= ize, + MEMTXATTRS_UNSPECIFIED); if (ret !=3D MEMTX_OK) { return ret; } @@ -285,7 +287,8 @@ static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr= , STE *buf, =20 trace_smmuv3_get_ste(addr); /* TODO: guarantee 64-bit single-copy atomicity */ - ret =3D dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf)= ); + ret =3D dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf), + MEMTXATTRS_UNSPECIFIED); if (ret !=3D MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, "Cannot fetch pte at address=3D0x%"PRIx64"\n", addr); @@ -306,7 +309,8 @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32= _t ssid, =20 trace_smmuv3_get_cd(addr); /* TODO: guarantee 64-bit single-copy atomicity */ - ret =3D dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf)= ); + ret =3D dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf), + MEMTXATTRS_UNSPECIFIED); if (ret !=3D MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, "Cannot fetch pte at address=3D0x%"PRIx64"\n", addr); @@ -411,7 +415,7 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, = STE *ste, l1ptr =3D (dma_addr_t)(strtab_base + l1_ste_offset * sizeof(l1std)= ); /* TODO: guarantee 64-bit single-copy atomicity */ ret =3D dma_memory_read(&address_space_memory, l1ptr, &l1std, - sizeof(l1std)); + sizeof(l1std), MEMTXATTRS_UNSPECIFIED); if (ret !=3D MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, "Could not read L1PTR at 0X%"PRIx64"\n", l1ptr); diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c index d14f932eea2..9a24ffb8806 100644 --- a/hw/core/generic-loader.c +++ b/hw/core/generic-loader.c @@ -57,7 +57,8 @@ static void generic_loader_reset(void *opaque) =20 if (s->data_len) { assert(s->data_len < sizeof(s->data)); - dma_memory_write(s->cpu->as, s->addr, &s->data, s->data_len); + dma_memory_write(s->cpu->as, s->addr, &s->data, s->data_len, + MEMTXATTRS_UNSPECIFIED); } } =20 diff --git a/hw/dma/pl330.c b/hw/dma/pl330.c index 944ba296b08..e10d4248905 100644 --- a/hw/dma/pl330.c +++ b/hw/dma/pl330.c @@ -1108,7 +1108,8 @@ static inline const PL330InsnDesc *pl330_fetch_insn(P= L330Chan *ch) uint8_t opcode; int i; =20 - dma_memory_read(&address_space_memory, ch->pc, &opcode, 1); + dma_memory_read(&address_space_memory, ch->pc, &opcode, 1, + MEMTXATTRS_UNSPECIFIED); for (i =3D 0; insn_desc[i].size; i++) { if ((opcode & insn_desc[i].opmask) =3D=3D insn_desc[i].opcode) { return &insn_desc[i]; @@ -1122,7 +1123,8 @@ static inline void pl330_exec_insn(PL330Chan *ch, con= st PL330InsnDesc *insn) uint8_t buf[PL330_INSN_MAXSIZE]; =20 assert(insn->size <=3D PL330_INSN_MAXSIZE); - dma_memory_read(&address_space_memory, ch->pc, buf, insn->size); + dma_memory_read(&address_space_memory, ch->pc, buf, insn->size, + MEMTXATTRS_UNSPECIFIED); insn->exec(ch, buf[0], &buf[1], insn->size - 1); } =20 @@ -1186,7 +1188,8 @@ static int pl330_exec_cycle(PL330Chan *channel) if (q !=3D NULL && q->len <=3D pl330_fifo_num_free(&s->fifo)) { int len =3D q->len - (q->addr & (q->len - 1)); =20 - dma_memory_read(&address_space_memory, q->addr, buf, len); + dma_memory_read(&address_space_memory, q->addr, buf, len, + MEMTXATTRS_UNSPECIFIED); trace_pl330_exec_cycle(q->addr, len); if (trace_event_get_state_backends(TRACE_PL330_HEXDUMP)) { pl330_hexdump(buf, len); @@ -1217,7 +1220,8 @@ static int pl330_exec_cycle(PL330Chan *channel) fifo_res =3D pl330_fifo_get(&s->fifo, buf, len, q->tag); } if (fifo_res =3D=3D PL330_FIFO_OK || q->z) { - dma_memory_write(&address_space_memory, q->addr, buf, len); + dma_memory_write(&address_space_memory, q->addr, buf, len, + MEMTXATTRS_UNSPECIFIED); trace_pl330_exec_cycle(q->addr, len); if (trace_event_get_state_backends(TRACE_PL330_HEXDUMP)) { pl330_hexdump(buf, len); diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c index 03bc500878f..0ef13c5e9a8 100644 --- a/hw/dma/sparc32_dma.c +++ b/hw/dma/sparc32_dma.c @@ -81,11 +81,11 @@ void ledma_memory_read(void *opaque, hwaddr addr, addr |=3D s->dmaregs[3]; trace_ledma_memory_read(addr, len); if (do_bswap) { - dma_memory_read(&is->iommu_as, addr, buf, len); + dma_memory_read(&is->iommu_as, addr, buf, len, MEMTXATTRS_UNSPECIF= IED); } else { addr &=3D ~1; len &=3D ~1; - dma_memory_read(&is->iommu_as, addr, buf, len); + dma_memory_read(&is->iommu_as, addr, buf, len, MEMTXATTRS_UNSPECIF= IED); for(i =3D 0; i < len; i +=3D 2) { bswap16s((uint16_t *)(buf + i)); } @@ -103,7 +103,8 @@ void ledma_memory_write(void *opaque, hwaddr addr, addr |=3D s->dmaregs[3]; trace_ledma_memory_write(addr, len); if (do_bswap) { - dma_memory_write(&is->iommu_as, addr, buf, len); + dma_memory_write(&is->iommu_as, addr, buf, len, + MEMTXATTRS_UNSPECIFIED); } else { addr &=3D ~1; len &=3D ~1; @@ -114,7 +115,8 @@ void ledma_memory_write(void *opaque, hwaddr addr, for(i =3D 0; i < l; i +=3D 2) { tmp_buf[i >> 1] =3D bswap16(*(uint16_t *)(buf + i)); } - dma_memory_write(&is->iommu_as, addr, tmp_buf, l); + dma_memory_write(&is->iommu_as, addr, tmp_buf, l, + MEMTXATTRS_UNSPECIFIED); len -=3D l; buf +=3D l; addr +=3D l; @@ -148,7 +150,8 @@ void espdma_memory_read(void *opaque, uint8_t *buf, int= len) IOMMUState *is =3D (IOMMUState *)s->iommu; =20 trace_espdma_memory_read(s->dmaregs[1], len); - dma_memory_read(&is->iommu_as, s->dmaregs[1], buf, len); + dma_memory_read(&is->iommu_as, s->dmaregs[1], buf, len, + MEMTXATTRS_UNSPECIFIED); s->dmaregs[1] +=3D len; } =20 @@ -158,7 +161,8 @@ void espdma_memory_write(void *opaque, uint8_t *buf, in= t len) IOMMUState *is =3D (IOMMUState *)s->iommu; =20 trace_espdma_memory_write(s->dmaregs[1], len); - dma_memory_write(&is->iommu_as, s->dmaregs[1], buf, len); + dma_memory_write(&is->iommu_as, s->dmaregs[1], buf, len, + MEMTXATTRS_UNSPECIFIED); s->dmaregs[1] +=3D len; } =20 diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index e33112b6f0e..f5ad1a0d22c 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -161,12 +161,14 @@ static void xlnx_zynq_devcfg_dma_go(XlnxZynqDevcfg *s) btt =3D MIN(btt, dmah->dest_len); } DB_PRINT("reading %x bytes from %x\n", btt, dmah->src_addr); - dma_memory_read(&address_space_memory, dmah->src_addr, buf, btt); + dma_memory_read(&address_space_memory, dmah->src_addr, buf, btt, + MEMTXATTRS_UNSPECIFIED); dmah->src_len -=3D btt; dmah->src_addr +=3D btt; if (loopback && (dmah->src_len || dmah->dest_len)) { DB_PRINT("writing %x bytes from %x\n", btt, dmah->dest_addr); - dma_memory_write(&address_space_memory, dmah->dest_addr, buf, = btt); + dma_memory_write(&address_space_memory, dmah->dest_addr, buf, = btt, + MEMTXATTRS_UNSPECIFIED); dmah->dest_len -=3D btt; dmah->dest_addr +=3D btt; } diff --git a/hw/dma/xlnx_dpdma.c b/hw/dma/xlnx_dpdma.c index 967548abd31..2d7eae72cd2 100644 --- a/hw/dma/xlnx_dpdma.c +++ b/hw/dma/xlnx_dpdma.c @@ -652,7 +652,7 @@ size_t xlnx_dpdma_start_operation(XlnxDPDMAState *s, ui= nt8_t channel, } =20 if (dma_memory_read(&address_space_memory, desc_addr, &desc, - sizeof(DPDMADescriptor))) { + sizeof(DPDMADescriptor), MEMTXATTRS_UNSPECIFIE= D)) { s->registers[DPDMA_EISR] |=3D ((1 << 1) << channel); xlnx_dpdma_update_irq(s); s->operation_finished[channel] =3D true; @@ -708,7 +708,8 @@ size_t xlnx_dpdma_start_operation(XlnxDPDMAState *s, ui= nt8_t channel, if (dma_memory_read(&address_space_memory, source_addr[0], &s->data[channel][ptr], - line_size)) { + line_size, + MEMTXATTRS_UNSPECIFIED)) { s->registers[DPDMA_ISR] |=3D ((1 << 12) << channel= ); xlnx_dpdma_update_irq(s); DPRINTF("Can't get data.\n"); @@ -736,7 +737,8 @@ size_t xlnx_dpdma_start_operation(XlnxDPDMAState *s, ui= nt8_t channel, if (dma_memory_read(&address_space_memory, source_addr[frag], &(s->data[channel][ptr]), - fragment_len)) { + fragment_len, + MEMTXATTRS_UNSPECIFIED)) { s->registers[DPDMA_ISR] |=3D ((1 << 12) << channel= ); xlnx_dpdma_update_irq(s); DPRINTF("Can't get data.\n"); @@ -754,7 +756,7 @@ size_t xlnx_dpdma_start_operation(XlnxDPDMAState *s, ui= nt8_t channel, DPRINTF("update the descriptor with the done flag set.\n"); xlnx_dpdma_desc_set_done(&desc); dma_memory_write(&address_space_memory, desc_addr, &desc, - sizeof(DPDMADescriptor)); + sizeof(DPDMADescriptor), MEMTXATTRS_UNSPECIFI= ED); } =20 if (xlnx_dpdma_desc_completion_interrupt(&desc)) { diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 2801dff97cd..789eb3f07bc 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -181,7 +181,7 @@ static void amdvi_log_event(AMDVIState *s, uint64_t *ev= t) } =20 if (dma_memory_write(&address_space_memory, s->evtlog + s->evtlog_tail, - evt, AMDVI_EVENT_LEN)) { + evt, AMDVI_EVENT_LEN, MEMTXATTRS_UNSPECIFIED)) { trace_amdvi_evntlog_fail(s->evtlog, s->evtlog_tail); } =20 @@ -376,7 +376,8 @@ static void amdvi_completion_wait(AMDVIState *s, uint64= _t *cmd) } if (extract64(cmd[0], 0, 1)) { if (dma_memory_write(&address_space_memory, addr, &data, - AMDVI_COMPLETION_DATA_SIZE)) { + AMDVI_COMPLETION_DATA_SIZE, + MEMTXATTRS_UNSPECIFIED)) { trace_amdvi_completion_wait_fail(addr); } } @@ -502,7 +503,7 @@ static void amdvi_cmdbuf_exec(AMDVIState *s) uint64_t cmd[2]; =20 if (dma_memory_read(&address_space_memory, s->cmdbuf + s->cmdbuf_head, - cmd, AMDVI_COMMAND_SIZE)) { + cmd, AMDVI_COMMAND_SIZE, MEMTXATTRS_UNSPECIFIED)) { trace_amdvi_command_read_fail(s->cmdbuf, s->cmdbuf_head); amdvi_log_command_error(s, s->cmdbuf + s->cmdbuf_head); return; @@ -836,7 +837,7 @@ static bool amdvi_get_dte(AMDVIState *s, int devid, uin= t64_t *entry) uint32_t offset =3D devid * AMDVI_DEVTAB_ENTRY_SIZE; =20 if (dma_memory_read(&address_space_memory, s->devtab + offset, entry, - AMDVI_DEVTAB_ENTRY_SIZE)) { + AMDVI_DEVTAB_ENTRY_SIZE, MEMTXATTRS_UNSPECIFIED)) { trace_amdvi_dte_get_fail(s->devtab, offset); /* log error accessing dte */ amdvi_log_devtab_error(s, devid, s->devtab + offset, 0); @@ -881,7 +882,8 @@ static inline uint64_t amdvi_get_pte_entry(AMDVIState *= s, uint64_t pte_addr, { uint64_t pte; =20 - if (dma_memory_read(&address_space_memory, pte_addr, &pte, sizeof(pte)= )) { + if (dma_memory_read(&address_space_memory, pte_addr, + &pte, sizeof(pte), MEMTXATTRS_UNSPECIFIED)) { trace_amdvi_get_pte_hwerror(pte_addr); amdvi_log_pagetab_error(s, devid, pte_addr, 0); pte =3D 0; @@ -1048,7 +1050,7 @@ static int amdvi_get_irte(AMDVIState *s, MSIMessage *= origin, uint64_t *dte, trace_amdvi_ir_irte(irte_root, offset); =20 if (dma_memory_read(&address_space_memory, irte_root + offset, - irte, sizeof(*irte))) { + irte, sizeof(*irte), MEMTXATTRS_UNSPECIFIED)) { trace_amdvi_ir_err("failed to get irte"); return -AMDVI_IR_GET_IRTE; } @@ -1108,7 +1110,7 @@ static int amdvi_get_irte_ga(AMDVIState *s, MSIMessag= e *origin, uint64_t *dte, trace_amdvi_ir_irte(irte_root, offset); =20 if (dma_memory_read(&address_space_memory, irte_root + offset, - irte, sizeof(*irte))) { + irte, sizeof(*irte), MEMTXATTRS_UNSPECIFIED)) { trace_amdvi_ir_err("failed to get irte_ga"); return -AMDVI_IR_GET_IRTE; } diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 209b3f55530..60e77d0dd97 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -569,7 +569,8 @@ static int vtd_get_root_entry(IntelIOMMUState *s, uint8= _t index, dma_addr_t addr; =20 addr =3D s->root + index * sizeof(*re); - if (dma_memory_read(&address_space_memory, addr, re, sizeof(*re))) { + if (dma_memory_read(&address_space_memory, addr, + re, sizeof(*re), MEMTXATTRS_UNSPECIFIED)) { re->lo =3D 0; return -VTD_FR_ROOT_TABLE_INV; } @@ -602,7 +603,8 @@ static int vtd_get_context_entry_from_root(IntelIOMMUSt= ate *s, } =20 addr =3D addr + index * ce_size; - if (dma_memory_read(&address_space_memory, addr, ce, ce_size)) { + if (dma_memory_read(&address_space_memory, addr, + ce, ce_size, MEMTXATTRS_UNSPECIFIED)) { return -VTD_FR_CONTEXT_TABLE_INV; } =20 @@ -639,8 +641,8 @@ static uint64_t vtd_get_slpte(dma_addr_t base_addr, uin= t32_t index) assert(index < VTD_SL_PT_ENTRY_NR); =20 if (dma_memory_read(&address_space_memory, - base_addr + index * sizeof(slpte), &slpte, - sizeof(slpte))) { + base_addr + index * sizeof(slpte), + &slpte, sizeof(slpte), MEMTXATTRS_UNSPECIFIED)) { slpte =3D (uint64_t)-1; return slpte; } @@ -704,7 +706,8 @@ static int vtd_get_pdire_from_pdir_table(dma_addr_t pas= id_dir_base, index =3D VTD_PASID_DIR_INDEX(pasid); entry_size =3D VTD_PASID_DIR_ENTRY_SIZE; addr =3D pasid_dir_base + index * entry_size; - if (dma_memory_read(&address_space_memory, addr, pdire, entry_size)) { + if (dma_memory_read(&address_space_memory, addr, + pdire, entry_size, MEMTXATTRS_UNSPECIFIED)) { return -VTD_FR_PASID_TABLE_INV; } =20 @@ -728,7 +731,8 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUSta= te *s, index =3D VTD_PASID_TABLE_INDEX(pasid); entry_size =3D VTD_PASID_ENTRY_SIZE; addr =3D addr + index * entry_size; - if (dma_memory_read(&address_space_memory, addr, pe, entry_size)) { + if (dma_memory_read(&address_space_memory, addr, + pe, entry_size, MEMTXATTRS_UNSPECIFIED)) { return -VTD_FR_PASID_TABLE_INV; } =20 @@ -2275,7 +2279,8 @@ static bool vtd_get_inv_desc(IntelIOMMUState *s, uint32_t dw =3D s->iq_dw ? 32 : 16; dma_addr_t addr =3D base_addr + offset * dw; =20 - if (dma_memory_read(&address_space_memory, addr, inv_desc, dw)) { + if (dma_memory_read(&address_space_memory, addr, + inv_desc, dw, MEMTXATTRS_UNSPECIFIED)) { error_report_once("Read INV DESC failed."); return false; } @@ -2308,8 +2313,9 @@ static bool vtd_process_wait_desc(IntelIOMMUState *s,= VTDInvDesc *inv_desc) dma_addr_t status_addr =3D inv_desc->hi; trace_vtd_inv_desc_wait_sw(status_addr, status_data); status_data =3D cpu_to_le32(status_data); - if (dma_memory_write(&address_space_memory, status_addr, &status_d= ata, - sizeof(status_data))) { + if (dma_memory_write(&address_space_memory, status_addr, + &status_data, sizeof(status_data), + MEMTXATTRS_UNSPECIFIED)) { trace_vtd_inv_desc_wait_write_fail(inv_desc->hi, inv_desc->lo); return false; } @@ -3120,8 +3126,8 @@ static int vtd_irte_get(IntelIOMMUState *iommu, uint1= 6_t index, } =20 addr =3D iommu->intr_root + index * sizeof(*entry); - if (dma_memory_read(&address_space_memory, addr, entry, - sizeof(*entry))) { + if (dma_memory_read(&address_space_memory, addr, + entry, sizeof(*entry), MEMTXATTRS_UNSPECIFIED)) { error_report_once("%s: read failed: ind=3D0x%x addr=3D0x%" PRIx64, __func__, index, addr); return -VTD_FR_IR_ROOT_INVAL; diff --git a/hw/ide/macio.c b/hw/ide/macio.c index b270a101632..df6f3b0a76b 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -97,7 +97,7 @@ static void pmac_ide_atapi_transfer_cb(void *opaque, int = ret) /* Non-block ATAPI transfer - just copy to RAM */ s->io_buffer_size =3D MIN(s->io_buffer_size, io->len); dma_memory_write(&address_space_memory, io->addr, s->io_buffer, - s->io_buffer_size); + s->io_buffer_size, MEMTXATTRS_UNSPECIFIED); io->len =3D 0; ide_atapi_cmd_ok(s); m->dma_active =3D false; diff --git a/hw/intc/xive.c b/hw/intc/xive.c index eeb4e62ba95..71875950b5e 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1262,8 +1262,8 @@ void xive_end_queue_pic_print_info(XiveEND *end, uint= 32_t width, Monitor *mon) uint64_t qaddr =3D qaddr_base + (qindex << 2); uint32_t qdata =3D -1; =20 - if (dma_memory_read(&address_space_memory, qaddr, &qdata, - sizeof(qdata))) { + if (dma_memory_read(&address_space_memory, qaddr, + &qdata, sizeof(qdata), MEMTXATTRS_UNSPECIFIED)= ) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" HWADDR_PRIx "\n", qaddr); return; @@ -1327,7 +1327,8 @@ static void xive_end_enqueue(XiveEND *end, uint32_t d= ata) uint32_t qdata =3D cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); uint32_t qentries =3D 1 << (qsize + 10); =20 - if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdat= a))) { + if (dma_memory_write(&address_space_memory, qaddr, + &qdata, sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x= %" HWADDR_PRIx "\n", qaddr); return; diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c index 73941bdae97..76ea511d53d 100644 --- a/hw/misc/bcm2835_property.c +++ b/hw/misc/bcm2835_property.c @@ -69,7 +69,8 @@ static void bcm2835_property_mbox_push(BCM2835PropertySta= te *s, uint32_t value) break; case 0x00010003: /* Get board MAC address */ resplen =3D sizeof(s->macaddr.a); - dma_memory_write(&s->dma_as, value + 12, s->macaddr.a, resplen= ); + dma_memory_write(&s->dma_as, value + 12, s->macaddr.a, resplen, + MEMTXATTRS_UNSPECIFIED); break; case 0x00010004: /* Get board serial */ qemu_log_mask(LOG_UNIMP, diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c index e220f1a9277..efcc02609fd 100644 --- a/hw/misc/macio/mac_dbdma.c +++ b/hw/misc/macio/mac_dbdma.c @@ -94,7 +94,7 @@ static void dbdma_cmdptr_load(DBDMA_channel *ch) DBDMA_DPRINTFCH(ch, "dbdma_cmdptr_load 0x%08x\n", ch->regs[DBDMA_CMDPTR_LO]); dma_memory_read(&address_space_memory, ch->regs[DBDMA_CMDPTR_LO], - &ch->current, sizeof(dbdma_cmd)); + &ch->current, sizeof(dbdma_cmd), MEMTXATTRS_UNSPECIFIE= D); } =20 static void dbdma_cmdptr_save(DBDMA_channel *ch) @@ -104,7 +104,7 @@ static void dbdma_cmdptr_save(DBDMA_channel *ch) le16_to_cpu(ch->current.xfer_status), le16_to_cpu(ch->current.res_count)); dma_memory_write(&address_space_memory, ch->regs[DBDMA_CMDPTR_LO], - &ch->current, sizeof(dbdma_cmd)); + &ch->current, sizeof(dbdma_cmd), MEMTXATTRS_UNSPECIFI= ED); } =20 static void kill_channel(DBDMA_channel *ch) @@ -371,7 +371,8 @@ static void load_word(DBDMA_channel *ch, int key, uint3= 2_t addr, return; } =20 - dma_memory_read(&address_space_memory, addr, ¤t->cmd_dep, len); + dma_memory_read(&address_space_memory, addr, ¤t->cmd_dep, len, + MEMTXATTRS_UNSPECIFIED); =20 if (conditional_wait(ch)) goto wait; @@ -403,7 +404,8 @@ static void store_word(DBDMA_channel *ch, int key, uint= 32_t addr, return; } =20 - dma_memory_write(&address_space_memory, addr, ¤t->cmd_dep, len); + dma_memory_write(&address_space_memory, addr, ¤t->cmd_dep, len, + MEMTXATTRS_UNSPECIFIED); =20 if (conditional_wait(ch)) goto wait; diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c index ff611f18fbd..ecc0245fe8a 100644 --- a/hw/net/allwinner-sun8i-emac.c +++ b/hw/net/allwinner-sun8i-emac.c @@ -350,7 +350,8 @@ static void allwinner_sun8i_emac_get_desc(AwSun8iEmacSt= ate *s, FrameDescriptor *desc, uint32_t phys_addr) { - dma_memory_read(&s->dma_as, phys_addr, desc, sizeof(*desc)); + dma_memory_read(&s->dma_as, phys_addr, desc, sizeof(*desc), + MEMTXATTRS_UNSPECIFIED); } =20 static uint32_t allwinner_sun8i_emac_next_desc(AwSun8iEmacState *s, @@ -402,7 +403,8 @@ static void allwinner_sun8i_emac_flush_desc(AwSun8iEmac= State *s, FrameDescriptor *desc, uint32_t phys_addr) { - dma_memory_write(&s->dma_as, phys_addr, desc, sizeof(*desc)); + dma_memory_write(&s->dma_as, phys_addr, desc, sizeof(*desc), + MEMTXATTRS_UNSPECIFIED); } =20 static bool allwinner_sun8i_emac_can_receive(NetClientState *nc) @@ -460,7 +462,8 @@ static ssize_t allwinner_sun8i_emac_receive(NetClientSt= ate *nc, << RX_DESC_STATUS_FRM_LEN_SHIFT; } =20 - dma_memory_write(&s->dma_as, desc.addr, buf, desc_bytes); + dma_memory_write(&s->dma_as, desc.addr, buf, desc_bytes, + MEMTXATTRS_UNSPECIFIED); allwinner_sun8i_emac_flush_desc(s, &desc, s->rx_desc_curr); trace_allwinner_sun8i_emac_receive(s->rx_desc_curr, desc.addr, desc_bytes); @@ -512,7 +515,8 @@ static void allwinner_sun8i_emac_transmit(AwSun8iEmacSt= ate *s) desc.status |=3D TX_DESC_STATUS_LENGTH_ERR; break; } - dma_memory_read(&s->dma_as, desc.addr, packet_buf + packet_bytes, = bytes); + dma_memory_read(&s->dma_as, desc.addr, packet_buf + packet_bytes, + bytes, MEMTXATTRS_UNSPECIFIED); packet_bytes +=3D bytes; desc.status &=3D ~DESC_STATUS_CTL; allwinner_sun8i_emac_flush_desc(s, &desc, s->tx_desc_curr); @@ -634,7 +638,8 @@ static uint64_t allwinner_sun8i_emac_read(void *opaque,= hwaddr offset, break; case REG_TX_CUR_BUF: /* Transmit Current Buffer */ if (s->tx_desc_curr !=3D 0) { - dma_memory_read(&s->dma_as, s->tx_desc_curr, &desc, sizeof(des= c)); + dma_memory_read(&s->dma_as, s->tx_desc_curr, &desc, sizeof(des= c), + MEMTXATTRS_UNSPECIFIED); value =3D desc.addr; } else { value =3D 0; @@ -647,7 +652,8 @@ static uint64_t allwinner_sun8i_emac_read(void *opaque,= hwaddr offset, break; case REG_RX_CUR_BUF: /* Receive Current Buffer */ if (s->rx_desc_curr !=3D 0) { - dma_memory_read(&s->dma_as, s->rx_desc_curr, &desc, sizeof(des= c)); + dma_memory_read(&s->dma_as, s->rx_desc_curr, &desc, sizeof(des= c), + MEMTXATTRS_UNSPECIFIED); value =3D desc.addr; } else { value =3D 0; diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c index 25685ba3a95..83ef0a783e7 100644 --- a/hw/net/ftgmac100.c +++ b/hw/net/ftgmac100.c @@ -453,7 +453,8 @@ static void do_phy_ctl(FTGMAC100State *s) =20 static int ftgmac100_read_bd(FTGMAC100Desc *bd, dma_addr_t addr) { - if (dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd))) { + if (dma_memory_read(&address_space_memory, addr, + bd, sizeof(*bd), MEMTXATTRS_UNSPECIFIED)) { qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read descriptor @ 0x= %" HWADDR_PRIx "\n", __func__, addr); return -1; @@ -473,7 +474,8 @@ static int ftgmac100_write_bd(FTGMAC100Desc *bd, dma_ad= dr_t addr) lebd.des1 =3D cpu_to_le32(bd->des1); lebd.des2 =3D cpu_to_le32(bd->des2); lebd.des3 =3D cpu_to_le32(bd->des3); - if (dma_memory_write(&address_space_memory, addr, &lebd, sizeof(lebd))= ) { + if (dma_memory_write(&address_space_memory, addr, + &lebd, sizeof(lebd), MEMTXATTRS_UNSPECIFIED)) { qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to write descriptor @ 0= x%" HWADDR_PRIx "\n", __func__, addr); return -1; @@ -554,7 +556,8 @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t= tx_ring, len =3D sizeof(s->frame) - frame_size; } =20 - if (dma_memory_read(&address_space_memory, bd.des3, ptr, len)) { + if (dma_memory_read(&address_space_memory, bd.des3, + ptr, len, MEMTXATTRS_UNSPECIFIED)) { qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to read packet @ 0x= %x\n", __func__, bd.des3); s->isr |=3D FTGMAC100_INT_AHB_ERR; @@ -1030,20 +1033,24 @@ static ssize_t ftgmac100_receive(NetClientState *nc= , const uint8_t *buf, bd.des1 =3D lduw_be_p(buf + 14) | FTGMAC100_RXDES1_VLANTAG_AVA= IL; =20 if (s->maccr & FTGMAC100_MACCR_RM_VLAN) { - dma_memory_write(&address_space_memory, buf_addr, buf, 12); - dma_memory_write(&address_space_memory, buf_addr + 12, buf= + 16, - buf_len - 16); + dma_memory_write(&address_space_memory, buf_addr, buf, 12, + MEMTXATTRS_UNSPECIFIED); + dma_memory_write(&address_space_memory, buf_addr + 12, + buf + 16, buf_len - 16, + MEMTXATTRS_UNSPECIFIED); } else { - dma_memory_write(&address_space_memory, buf_addr, buf, buf= _len); + dma_memory_write(&address_space_memory, buf_addr, buf, + buf_len, MEMTXATTRS_UNSPECIFIED); } } else { bd.des1 =3D 0; - dma_memory_write(&address_space_memory, buf_addr, buf, buf_len= ); + dma_memory_write(&address_space_memory, buf_addr, buf, buf_len, + MEMTXATTRS_UNSPECIFIED); } buf +=3D buf_len; if (size < 4) { dma_memory_write(&address_space_memory, buf_addr + buf_len, - crc_ptr, 4 - size); + crc_ptr, 4 - size, MEMTXATTRS_UNSPECIFIED); crc_ptr +=3D 4 - size; } =20 diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 9c7035bc948..0db9aaf76a0 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -387,19 +387,22 @@ static void imx_phy_write(IMXFECState *s, int reg, ui= nt32_t val) =20 static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr) { - dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd)); + dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd), + MEMTXATTRS_UNSPECIFIED); =20 trace_imx_fec_read_bd(addr, bd->flags, bd->length, bd->data); } =20 static void imx_fec_write_bd(IMXFECBufDesc *bd, dma_addr_t addr) { - dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd)); + dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd), + MEMTXATTRS_UNSPECIFIED); } =20 static void imx_enet_read_bd(IMXENETBufDesc *bd, dma_addr_t addr) { - dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd)); + dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd), + MEMTXATTRS_UNSPECIFIED); =20 trace_imx_enet_read_bd(addr, bd->flags, bd->length, bd->data, bd->option, bd->status); @@ -407,7 +410,8 @@ static void imx_enet_read_bd(IMXENETBufDesc *bd, dma_ad= dr_t addr) =20 static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr) { - dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd)); + dma_memory_write(&address_space_memory, addr, bd, sizeof(*bd), + MEMTXATTRS_UNSPECIFIED); } =20 static void imx_eth_update(IMXFECState *s) @@ -474,7 +478,8 @@ static void imx_fec_do_tx(IMXFECState *s) len =3D ENET_MAX_FRAME_SIZE - frame_size; s->regs[ENET_EIR] |=3D ENET_INT_BABT; } - dma_memory_read(&address_space_memory, bd.data, ptr, len); + dma_memory_read(&address_space_memory, bd.data, ptr, len, + MEMTXATTRS_UNSPECIFIED); ptr +=3D len; frame_size +=3D len; if (bd.flags & ENET_BD_L) { @@ -555,7 +560,8 @@ static void imx_enet_do_tx(IMXFECState *s, uint32_t ind= ex) len =3D ENET_MAX_FRAME_SIZE - frame_size; s->regs[ENET_EIR] |=3D ENET_INT_BABT; } - dma_memory_read(&address_space_memory, bd.data, ptr, len); + dma_memory_read(&address_space_memory, bd.data, ptr, len, + MEMTXATTRS_UNSPECIFIED); ptr +=3D len; frame_size +=3D len; if (bd.flags & ENET_BD_L) { @@ -1103,11 +1109,12 @@ static ssize_t imx_fec_receive(NetClientState *nc, = const uint8_t *buf, buf_len +=3D size - 4; } buf_addr =3D bd.data; - dma_memory_write(&address_space_memory, buf_addr, buf, buf_len); + dma_memory_write(&address_space_memory, buf_addr, buf, buf_len, + MEMTXATTRS_UNSPECIFIED); buf +=3D buf_len; if (size < 4) { dma_memory_write(&address_space_memory, buf_addr + buf_len, - crc_ptr, 4 - size); + crc_ptr, 4 - size, MEMTXATTRS_UNSPECIFIED); crc_ptr +=3D 4 - size; } bd.flags &=3D ~ENET_BD_E; @@ -1210,8 +1217,8 @@ static ssize_t imx_enet_receive(NetClientState *nc, c= onst uint8_t *buf, */ const uint8_t zeros[2] =3D { 0 }; =20 - dma_memory_write(&address_space_memory, buf_addr, - zeros, sizeof(zeros)); + dma_memory_write(&address_space_memory, buf_addr, zeros, + sizeof(zeros), MEMTXATTRS_UNSPECIFIED); =20 buf_addr +=3D sizeof(zeros); buf_len -=3D sizeof(zeros); @@ -1220,11 +1227,12 @@ static ssize_t imx_enet_receive(NetClientState *nc,= const uint8_t *buf, shift16 =3D false; } =20 - dma_memory_write(&address_space_memory, buf_addr, buf, buf_len); + dma_memory_write(&address_space_memory, buf_addr, buf, buf_len, + MEMTXATTRS_UNSPECIFIED); buf +=3D buf_len; if (size < 4) { dma_memory_write(&address_space_memory, buf_addr + buf_len, - crc_ptr, 4 - size); + crc_ptr, 4 - size, MEMTXATTRS_UNSPECIFIED); crc_ptr +=3D 4 - size; } bd.flags &=3D ~ENET_BD_E; diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c index 7c892f820fb..df2efe1bf84 100644 --- a/hw/net/npcm7xx_emc.c +++ b/hw/net/npcm7xx_emc.c @@ -200,7 +200,8 @@ static void emc_update_irq_from_reg_change(NPCM7xxEMCSt= ate *emc) =20 static int emc_read_tx_desc(dma_addr_t addr, NPCM7xxEMCTxDesc *desc) { - if (dma_memory_read(&address_space_memory, addr, desc, sizeof(*desc)))= { + if (dma_memory_read(&address_space_memory, addr, desc, + sizeof(*desc), MEMTXATTRS_UNSPECIFIED)) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x= %" HWADDR_PRIx "\n", __func__, addr); return -1; @@ -221,7 +222,7 @@ static int emc_write_tx_desc(const NPCM7xxEMCTxDesc *de= sc, dma_addr_t addr) le_desc.status_and_length =3D cpu_to_le32(desc->status_and_length); le_desc.ntxdsa =3D cpu_to_le32(desc->ntxdsa); if (dma_memory_write(&address_space_memory, addr, &le_desc, - sizeof(le_desc))) { + sizeof(le_desc), MEMTXATTRS_UNSPECIFIED)) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0= x%" HWADDR_PRIx "\n", __func__, addr); return -1; @@ -231,7 +232,8 @@ static int emc_write_tx_desc(const NPCM7xxEMCTxDesc *de= sc, dma_addr_t addr) =20 static int emc_read_rx_desc(dma_addr_t addr, NPCM7xxEMCRxDesc *desc) { - if (dma_memory_read(&address_space_memory, addr, desc, sizeof(*desc)))= { + if (dma_memory_read(&address_space_memory, addr, desc, + sizeof(*desc), MEMTXATTRS_UNSPECIFIED)) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read descriptor @ 0x= %" HWADDR_PRIx "\n", __func__, addr); return -1; @@ -252,7 +254,7 @@ static int emc_write_rx_desc(const NPCM7xxEMCRxDesc *de= sc, dma_addr_t addr) le_desc.reserved =3D cpu_to_le32(desc->reserved); le_desc.nrxdsa =3D cpu_to_le32(desc->nrxdsa); if (dma_memory_write(&address_space_memory, addr, &le_desc, - sizeof(le_desc))) { + sizeof(le_desc), MEMTXATTRS_UNSPECIFIED)) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to write descriptor @ 0= x%" HWADDR_PRIx "\n", __func__, addr); return -1; @@ -360,7 +362,8 @@ static void emc_try_send_next_packet(NPCM7xxEMCState *e= mc) buf =3D malloced_buf; } =20 - if (dma_memory_read(&address_space_memory, next_buf_addr, buf, length)= ) { + if (dma_memory_read(&address_space_memory, next_buf_addr, buf, + length, MEMTXATTRS_UNSPECIFIED)) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Failed to read packet @ 0x%x\n= ", __func__, next_buf_addr); emc_set_mista(emc, REG_MISTA_TXBERR); @@ -545,10 +548,11 @@ static ssize_t emc_receive(NetClientState *nc, const = uint8_t *buf, size_t len1) =20 buf_addr =3D rx_desc.rxbsa; emc->regs[REG_CRXBSA] =3D buf_addr; - if (dma_memory_write(&address_space_memory, buf_addr, buf, len) || + if (dma_memory_write(&address_space_memory, buf_addr, buf, + len, MEMTXATTRS_UNSPECIFIED) || (!(emc->regs[REG_MCMDR] & REG_MCMDR_SPCRC) && - dma_memory_write(&address_space_memory, buf_addr + len, crc_ptr, - 4))) { + dma_memory_write(&address_space_memory, buf_addr + len, + crc_ptr, 4, MEMTXATTRS_UNSPECIFIED))) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Bus error writing packet\n", __func__); emc_set_mista(emc, REG_MISTA_RXBERR); diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index d3c3b15a728..c31d8fbeca9 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -357,7 +357,8 @@ static void fw_cfg_dma_transfer(FWCfgState *s) dma_addr =3D s->dma_addr; s->dma_addr =3D 0; =20 - if (dma_memory_read(s->dma_as, dma_addr, &dma, sizeof(dma))) { + if (dma_memory_read(s->dma_as, dma_addr, + &dma, sizeof(dma), MEMTXATTRS_UNSPECIFIED)) { stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control), FW_CFG_DMA_CTL_ERROR); return; @@ -419,7 +420,8 @@ static void fw_cfg_dma_transfer(FWCfgState *s) */ if (read) { if (dma_memory_write(s->dma_as, dma.address, - &e->data[s->cur_offset], len)) { + &e->data[s->cur_offset], len, + MEMTXATTRS_UNSPECIFIED)) { dma.control |=3D FW_CFG_DMA_CTL_ERROR; } } @@ -427,7 +429,8 @@ static void fw_cfg_dma_transfer(FWCfgState *s) if (!e->allow_write || len !=3D dma.length || dma_memory_read(s->dma_as, dma.address, - &e->data[s->cur_offset], len)) { + &e->data[s->cur_offset], len, + MEMTXATTRS_UNSPECIFIED)) { dma.control |=3D FW_CFG_DMA_CTL_ERROR; } else if (e->write_cb) { e->write_cb(e->callback_opaque, s->cur_offset, len); diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index a7f96850055..947efa77dc9 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -715,7 +715,8 @@ static bool pnv_phb3_resolve_pe(PnvPhb3DMASpace *ds) bus_num =3D pci_bus_num(ds->bus); addr =3D rtt & PHB_RTT_BASE_ADDRESS_MASK; addr +=3D 2 * ((bus_num << 8) | ds->devfn); - if (dma_memory_read(&address_space_memory, addr, &rte, sizeof(rte))) { + if (dma_memory_read(&address_space_memory, addr, &rte, + sizeof(rte), MEMTXATTRS_UNSPECIFIED)) { phb3_error(ds->phb, "Failed to read RTT entry at 0x%"PRIx64, addr); /* Set error bits ? fence ? ... */ return false; @@ -794,7 +795,7 @@ static void pnv_phb3_translate_tve(PnvPhb3DMASpace *ds,= hwaddr addr, /* Grab the TCE address */ taddr =3D base | (((addr >> sh) & ((1ul << tbl_shift) - 1)) <<= 3); if (dma_memory_read(&address_space_memory, taddr, &tce, - sizeof(tce))) { + sizeof(tce), MEMTXATTRS_UNSPECIFIED)) { phb3_error(phb, "Failed to read TCE at 0x%"PRIx64, taddr); return; } diff --git a/hw/pci-host/pnv_phb3_msi.c b/hw/pci-host/pnv_phb3_msi.c index 099d2092a2c..8bcbc2cc4f3 100644 --- a/hw/pci-host/pnv_phb3_msi.c +++ b/hw/pci-host/pnv_phb3_msi.c @@ -53,7 +53,8 @@ static bool phb3_msi_read_ive(PnvPHB3 *phb, int srcno, ui= nt64_t *out_ive) return false; } =20 - if (dma_memory_read(&address_space_memory, ive_addr, &ive, sizeof(ive)= )) { + if (dma_memory_read(&address_space_memory, ive_addr, + &ive, sizeof(ive), MEMTXATTRS_UNSPECIFIED)) { qemu_log_mask(LOG_GUEST_ERROR, "Failed to read IVE at 0x%" PRIx64, ive_addr); return false; @@ -73,7 +74,8 @@ static void phb3_msi_set_p(Phb3MsiState *msi, int srcno, = uint8_t gen) return; } =20 - if (dma_memory_write(&address_space_memory, ive_addr + 4, &p, 1)) { + if (dma_memory_write(&address_space_memory, ive_addr + 4, + &p, 1, MEMTXATTRS_UNSPECIFIED)) { qemu_log_mask(LOG_GUEST_ERROR, "Failed to write IVE (set P) at 0x%" PRIx64, ive_add= r); } @@ -89,7 +91,8 @@ static void phb3_msi_set_q(Phb3MsiState *msi, int srcno) return; } =20 - if (dma_memory_write(&address_space_memory, ive_addr + 5, &q, 1)) { + if (dma_memory_write(&address_space_memory, ive_addr + 5, + &q, 1, MEMTXATTRS_UNSPECIFIED)) { qemu_log_mask(LOG_GUEST_ERROR, "Failed to write IVE (set Q) at 0x%" PRIx64, ive_add= r); } diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 54f57c660a9..95facf67fe6 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -891,7 +891,8 @@ static bool pnv_phb4_resolve_pe(PnvPhb4DMASpace *ds) bus_num =3D pci_bus_num(ds->bus); addr =3D rtt & PHB_RTT_BASE_ADDRESS_MASK; addr +=3D 2 * PCI_BUILD_BDF(bus_num, ds->devfn); - if (dma_memory_read(&address_space_memory, addr, &rte, sizeof(rte))) { + if (dma_memory_read(&address_space_memory, addr, &rte, + sizeof(rte), MEMTXATTRS_UNSPECIFIED)) { phb_error(ds->phb, "Failed to read RTT entry at 0x%"PRIx64, addr); /* Set error bits ? fence ? ... */ return false; @@ -961,7 +962,7 @@ static void pnv_phb4_translate_tve(PnvPhb4DMASpace *ds,= hwaddr addr, /* Grab the TCE address */ taddr =3D base | (((addr >> sh) & ((1ul << tbl_shift) - 1)) <<= 3); if (dma_memory_read(&address_space_memory, taddr, &tce, - sizeof(tce))) { + sizeof(tce), MEMTXATTRS_UNSPECIFIED)) { phb_error(ds->phb, "Failed to read TCE at 0x%"PRIx64, tadd= r); return; } diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c index bea6d97ef87..f2db73025d1 100644 --- a/hw/sd/allwinner-sdhost.c +++ b/hw/sd/allwinner-sdhost.c @@ -311,7 +311,8 @@ static uint32_t allwinner_sdhost_process_desc(AwSdHostS= tate *s, uint8_t buf[1024]; =20 /* Read descriptor */ - dma_memory_read(&s->dma_as, desc_addr, desc, sizeof(*desc)); + dma_memory_read(&s->dma_as, desc_addr, desc, sizeof(*desc), + MEMTXATTRS_UNSPECIFIED); if (desc->size =3D=3D 0) { desc->size =3D klass->max_desc_size; } else if (desc->size > klass->max_desc_size) { @@ -337,23 +338,24 @@ static uint32_t allwinner_sdhost_process_desc(AwSdHos= tState *s, /* Write to SD bus */ if (is_write) { dma_memory_read(&s->dma_as, - (desc->addr & DESC_SIZE_MASK) + num_done, - buf, buf_bytes); + (desc->addr & DESC_SIZE_MASK) + num_done, buf, + buf_bytes, MEMTXATTRS_UNSPECIFIED); sdbus_write_data(&s->sdbus, buf, buf_bytes); =20 /* Read from SD bus */ } else { sdbus_read_data(&s->sdbus, buf, buf_bytes); dma_memory_write(&s->dma_as, - (desc->addr & DESC_SIZE_MASK) + num_done, - buf, buf_bytes); + (desc->addr & DESC_SIZE_MASK) + num_done, buf, + buf_bytes, MEMTXATTRS_UNSPECIFIED); } num_done +=3D buf_bytes; } =20 /* Clear hold flag and flush descriptor */ desc->status &=3D ~DESC_STATUS_HOLD; - dma_memory_write(&s->dma_as, desc_addr, desc, sizeof(*desc)); + dma_memory_write(&s->dma_as, desc_addr, desc, sizeof(*desc), + MEMTXATTRS_UNSPECIFIED); =20 return num_done; } diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 5b8678110b0..9574e1b394f 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -616,8 +616,8 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState= *s) s->blkcnt--; } } - dma_memory_write(s->dma_as, s->sdmasysad, - &s->fifo_buffer[begin], s->data_count - begin= ); + dma_memory_write(s->dma_as, s->sdmasysad, &s->fifo_buffer[begi= n], + s->data_count - begin, MEMTXATTRS_UNSPECIFIED= ); s->sdmasysad +=3D s->data_count - begin; if (s->data_count =3D=3D block_size) { s->data_count =3D 0; @@ -637,8 +637,8 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState= *s) s->data_count =3D block_size; boundary_count -=3D block_size - begin; } - dma_memory_read(s->dma_as, s->sdmasysad, - &s->fifo_buffer[begin], s->data_count - begin); + dma_memory_read(s->dma_as, s->sdmasysad, &s->fifo_buffer[begin= ], + s->data_count - begin, MEMTXATTRS_UNSPECIFIED); s->sdmasysad +=3D s->data_count - begin; if (s->data_count =3D=3D block_size) { sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size); @@ -670,9 +670,11 @@ static void sdhci_sdma_transfer_single_block(SDHCIStat= e *s) =20 if (s->trnmod & SDHC_TRNS_READ) { sdbus_read_data(&s->sdbus, s->fifo_buffer, datacnt); - dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); + dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt, + MEMTXATTRS_UNSPECIFIED); } else { - dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); + dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt, + MEMTXATTRS_UNSPECIFIED); sdbus_write_data(&s->sdbus, s->fifo_buffer, datacnt); } s->blkcnt--; @@ -694,7 +696,8 @@ static void get_adma_description(SDHCIState *s, ADMADes= cr *dscr) hwaddr entry_addr =3D (hwaddr)s->admasysaddr; switch (SDHC_DMA_TYPE(s->hostctl1)) { case SDHC_CTRL_ADMA2_32: - dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2)); + dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2), + MEMTXATTRS_UNSPECIFIED); adma2 =3D le64_to_cpu(adma2); /* The spec does not specify endianness of descriptor table. * We currently assume that it is LE. @@ -705,7 +708,8 @@ static void get_adma_description(SDHCIState *s, ADMADes= cr *dscr) dscr->incr =3D 8; break; case SDHC_CTRL_ADMA1_32: - dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(adma1)); + dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(adma1), + MEMTXATTRS_UNSPECIFIED); adma1 =3D le32_to_cpu(adma1); dscr->addr =3D (hwaddr)(adma1 & 0xFFFFF000); dscr->attr =3D (uint8_t)extract32(adma1, 0, 7); @@ -717,10 +721,13 @@ static void get_adma_description(SDHCIState *s, ADMAD= escr *dscr) } break; case SDHC_CTRL_ADMA2_64: - dma_memory_read(s->dma_as, entry_addr, &dscr->attr, 1); - dma_memory_read(s->dma_as, entry_addr + 2, &dscr->length, 2); + dma_memory_read(s->dma_as, entry_addr, &dscr->attr, 1, + MEMTXATTRS_UNSPECIFIED); + dma_memory_read(s->dma_as, entry_addr + 2, &dscr->length, 2, + MEMTXATTRS_UNSPECIFIED); dscr->length =3D le16_to_cpu(dscr->length); - dma_memory_read(s->dma_as, entry_addr + 4, &dscr->addr, 8); + dma_memory_read(s->dma_as, entry_addr + 4, &dscr->addr, 8, + MEMTXATTRS_UNSPECIFIED); dscr->addr =3D le64_to_cpu(dscr->addr); dscr->attr &=3D (uint8_t) ~0xC0; dscr->incr =3D 12; @@ -785,7 +792,8 @@ static void sdhci_do_adma(SDHCIState *s) } dma_memory_write(s->dma_as, dscr.addr, &s->fifo_buffer[begin], - s->data_count - begin); + s->data_count - begin, + MEMTXATTRS_UNSPECIFIED); dscr.addr +=3D s->data_count - begin; if (s->data_count =3D=3D block_size) { s->data_count =3D 0; @@ -810,7 +818,8 @@ static void sdhci_do_adma(SDHCIState *s) } dma_memory_read(s->dma_as, dscr.addr, &s->fifo_buffer[begin], - s->data_count - begin); + s->data_count - begin, + MEMTXATTRS_UNSPECIFIED); dscr.addr +=3D s->data_count - begin; if (s->data_count =3D=3D block_size) { sdbus_write_data(&s->sdbus, s->fifo_buffer, block_= size); diff --git a/hw/usb/hcd-dwc2.c b/hw/usb/hcd-dwc2.c index e1d96acf7ec..8755e9cbb0a 100644 --- a/hw/usb/hcd-dwc2.c +++ b/hw/usb/hcd-dwc2.c @@ -272,8 +272,8 @@ static void dwc2_handle_packet(DWC2State *s, uint32_t d= evadr, USBDevice *dev, =20 if (pid !=3D USB_TOKEN_IN) { trace_usb_dwc2_memory_read(hcdma, tlen); - if (dma_memory_read(&s->dma_as, hcdma, - s->usb_buf[chan], tlen) !=3D MEMTX_OK) { + if (dma_memory_read(&s->dma_as, hcdma, s->usb_buf[chan], tlen, + MEMTXATTRS_UNSPECIFIED) !=3D MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, "%s: dma_memory_read failed= \n", __func__); } @@ -328,8 +328,8 @@ babble: =20 if (pid =3D=3D USB_TOKEN_IN) { trace_usb_dwc2_memory_write(hcdma, actual); - if (dma_memory_write(&s->dma_as, hcdma, s->usb_buf[chan], - actual) !=3D MEMTX_OK) { + if (dma_memory_write(&s->dma_as, hcdma, s->usb_buf[chan], actu= al, + MEMTXATTRS_UNSPECIFIED) !=3D MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, "%s: dma_memory_write faile= d\n", __func__); } diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index 6caa7ac6c28..33a8a377bd9 100644 --- a/hw/usb/hcd-ehci.c +++ b/hw/usb/hcd-ehci.c @@ -383,7 +383,8 @@ static inline int get_dwords(EHCIState *ehci, uint32_t = addr, } =20 for (i =3D 0; i < num; i++, buf++, addr +=3D sizeof(*buf)) { - dma_memory_read(ehci->as, addr, buf, sizeof(*buf)); + dma_memory_read(ehci->as, addr, buf, sizeof(*buf), + MEMTXATTRS_UNSPECIFIED); *buf =3D le32_to_cpu(*buf); } =20 @@ -405,7 +406,8 @@ static inline int put_dwords(EHCIState *ehci, uint32_t = addr, =20 for (i =3D 0; i < num; i++, buf++, addr +=3D sizeof(*buf)) { uint32_t tmp =3D cpu_to_le32(*buf); - dma_memory_write(ehci->as, addr, &tmp, sizeof(tmp)); + dma_memory_write(ehci->as, addr, &tmp, sizeof(tmp), + MEMTXATTRS_UNSPECIFIED); } =20 return num; diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c index 56e2315c734..a93d6b2e988 100644 --- a/hw/usb/hcd-ohci.c +++ b/hw/usb/hcd-ohci.c @@ -452,7 +452,8 @@ static inline int get_dwords(OHCIState *ohci, addr +=3D ohci->localmem_base; =20 for (i =3D 0; i < num; i++, buf++, addr +=3D sizeof(*buf)) { - if (dma_memory_read(ohci->as, addr, buf, sizeof(*buf))) { + if (dma_memory_read(ohci->as, addr, + buf, sizeof(*buf), MEMTXATTRS_UNSPECIFIED)) { return -1; } *buf =3D le32_to_cpu(*buf); @@ -471,7 +472,8 @@ static inline int put_dwords(OHCIState *ohci, =20 for (i =3D 0; i < num; i++, buf++, addr +=3D sizeof(*buf)) { uint32_t tmp =3D cpu_to_le32(*buf); - if (dma_memory_write(ohci->as, addr, &tmp, sizeof(tmp))) { + if (dma_memory_write(ohci->as, addr, + &tmp, sizeof(tmp), MEMTXATTRS_UNSPECIFIED)) { return -1; } } @@ -488,7 +490,8 @@ static inline int get_words(OHCIState *ohci, addr +=3D ohci->localmem_base; =20 for (i =3D 0; i < num; i++, buf++, addr +=3D sizeof(*buf)) { - if (dma_memory_read(ohci->as, addr, buf, sizeof(*buf))) { + if (dma_memory_read(ohci->as, addr, + buf, sizeof(*buf), MEMTXATTRS_UNSPECIFIED)) { return -1; } *buf =3D le16_to_cpu(*buf); @@ -507,7 +510,8 @@ static inline int put_words(OHCIState *ohci, =20 for (i =3D 0; i < num; i++, buf++, addr +=3D sizeof(*buf)) { uint16_t tmp =3D cpu_to_le16(*buf); - if (dma_memory_write(ohci->as, addr, &tmp, sizeof(tmp))) { + if (dma_memory_write(ohci->as, addr, + &tmp, sizeof(tmp), MEMTXATTRS_UNSPECIFIED)) { return -1; } } @@ -537,8 +541,8 @@ static inline int ohci_read_iso_td(OHCIState *ohci, static inline int ohci_read_hcca(OHCIState *ohci, dma_addr_t addr, struct ohci_hcca *hcca) { - return dma_memory_read(ohci->as, addr + ohci->localmem_base, - hcca, sizeof(*hcca)); + return dma_memory_read(ohci->as, addr + ohci->localmem_base, hcca, + sizeof(*hcca), MEMTXATTRS_UNSPECIFIED); } =20 static inline int ohci_put_ed(OHCIState *ohci, @@ -572,7 +576,7 @@ static inline int ohci_put_hcca(OHCIState *ohci, return dma_memory_write(ohci->as, addr + ohci->localmem_base + HCCA_WRITEBACK_OF= FSET, (char *)hcca + HCCA_WRITEBACK_OFFSET, - HCCA_WRITEBACK_SIZE); + HCCA_WRITEBACK_SIZE, MEMTXATTRS_UNSPECIFIED); } =20 /* Read/Write the contents of a TD from/to main memory. */ diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index e01700039b1..ed2b9ea456e 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -487,7 +487,7 @@ static inline void xhci_dma_read_u32s(XHCIState *xhci, = dma_addr_t addr, =20 assert((len % sizeof(uint32_t)) =3D=3D 0); =20 - dma_memory_read(xhci->as, addr, buf, len); + dma_memory_read(xhci->as, addr, buf, len, MEMTXATTRS_UNSPECIFIED); =20 for (i =3D 0; i < (len / sizeof(uint32_t)); i++) { buf[i] =3D le32_to_cpu(buf[i]); @@ -507,7 +507,7 @@ static inline void xhci_dma_write_u32s(XHCIState *xhci,= dma_addr_t addr, for (i =3D 0; i < n; i++) { tmp[i] =3D cpu_to_le32(buf[i]); } - dma_memory_write(xhci->as, addr, tmp, len); + dma_memory_write(xhci->as, addr, tmp, len, MEMTXATTRS_UNSPECIFIED); } =20 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) @@ -618,7 +618,7 @@ static void xhci_write_event(XHCIState *xhci, XHCIEvent= *event, int v) ev_trb.status, ev_trb.control); =20 addr =3D intr->er_start + TRB_SIZE*intr->er_ep_idx; - dma_memory_write(xhci->as, addr, &ev_trb, TRB_SIZE); + dma_memory_write(xhci->as, addr, &ev_trb, TRB_SIZE, MEMTXATTRS_UNSPECI= FIED); =20 intr->er_ep_idx++; if (intr->er_ep_idx >=3D intr->er_size) { @@ -679,7 +679,8 @@ static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRin= g *ring, XHCITRB *trb, =20 while (1) { TRBType type; - dma_memory_read(xhci->as, ring->dequeue, trb, TRB_SIZE); + dma_memory_read(xhci->as, ring->dequeue, trb, TRB_SIZE, + MEMTXATTRS_UNSPECIFIED); trb->addr =3D ring->dequeue; trb->ccs =3D ring->ccs; le64_to_cpus(&trb->parameter); @@ -726,7 +727,8 @@ static int xhci_ring_chain_length(XHCIState *xhci, cons= t XHCIRing *ring) =20 while (1) { TRBType type; - dma_memory_read(xhci->as, dequeue, &trb, TRB_SIZE); + dma_memory_read(xhci->as, dequeue, &trb, TRB_SIZE, + MEMTXATTRS_UNSPECIFIED); le64_to_cpus(&trb.parameter); le32_to_cpus(&trb.status); le32_to_cpus(&trb.control); @@ -781,7 +783,8 @@ static void xhci_er_reset(XHCIState *xhci, int v) xhci_die(xhci); return; } - dma_memory_read(xhci->as, erstba, &seg, sizeof(seg)); + dma_memory_read(xhci->as, erstba, &seg, sizeof(seg), + MEMTXATTRS_UNSPECIFIED); le32_to_cpus(&seg.addr_low); le32_to_cpus(&seg.addr_high); le32_to_cpus(&seg.size); @@ -2397,7 +2400,8 @@ static TRBCCode xhci_get_port_bandwidth(XHCIState *xh= ci, uint64_t pctx) /* TODO: actually implement real values here */ bw_ctx[0] =3D 0; memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ - dma_memory_write(xhci->as, ctx, bw_ctx, sizeof(bw_ctx)); + dma_memory_write(xhci->as, ctx, bw_ctx, sizeof(bw_ctx), + MEMTXATTRS_UNSPECIFIED); =20 return CC_SUCCESS; } --=20 2.31.1 From nobody Sun May 19 14:14:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 170.10.133.124 as permitted sender) client-ip=170.10.133.124; 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[92.184.108.94]) by smtp.gmail.com with ESMTPSA id w8sm2573709wre.70.2021.07.02.02.25.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 02:25:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1625217913; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wovYqlv5diazsDyxYSvnGuwQcZm93XmdRsbIEZ0iPcQ=; b=Qb8B71LWF2No+MdL5Behyo6L+fV8oI9/6C0wYeEkM0kWelyeY6JUMqT2TueiXpcvE5xErE jtuDYWL00gzPJLRWISkf7f2Oe5yXEREgdiv5/qU8WTf7XK1p2nBIbiv9o4nFsCf853MsdN Ggm/AVh+dxQxclOB5r2Kje3Mcq8dVkg= X-MC-Unique: 78RlXlshNO2mECfD_-3qfg-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wovYqlv5diazsDyxYSvnGuwQcZm93XmdRsbIEZ0iPcQ=; b=uE4dsqwATAwUI7cyQ8hksxH9k7JkiuacaUtL8bMCfVAI30b/8JUr/dRDPiaP7a8VxF +OQh4PkpphdZYjam6dh8WTK9DpcCTf+qynBUpnMcTO/hhb4PLbZMk4jYRqBkcFcMpCUy 5beM7qXafATMDG7V4B+HDJPBzut0xBO0zcy8UFsD8QiFcw+ApVGGqigQImH5xu+tMQa7 jfh1WL/Rw3A2Wrgx31DctfKVeh20qKtFwqTkcdj8wjZEtTrhk9oxu3FNq1pvdEtNZi+J pczCIdSqzXqE9UkqyUpqjbLYcsy7dUyrLs4+X4SqSYAox4/KbMz4nmUq3WYz5NKkz7bp jqKw== X-Gm-Message-State: AOAM531EKCmtBwVDyNnL0eoZO1pDUvK7/rCcHyOxshadDPiSgNsKaJha wpl+q90CAqyBuhfGktLDpblhfwAAyNlyCepGiXHkyVZ37neJSVSzS6ajT5uiMHCPgImkHxR8DuG hNH5nkdAZY1wBlg== X-Received: by 2002:a7b:c318:: with SMTP id k24mr4420495wmj.144.1625217911209; Fri, 02 Jul 2021 02:25:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyAXKC/Bkt38oMUGRow7dHAsRohBP8m94azHWvVRpkJGngSSh70QnzumEUDclnnL5+n8+HfAQ== X-Received: by 2002:a7b:c318:: with SMTP id k24mr4420463wmj.144.1625217910827; Fri, 02 Jul 2021 02:25:10 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , Alexander Bulekov , Stefan Hajnoczi , Mauro Matteo Cascella , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Li Qiang , "Edgar E . Iglesias" Subject: [PATCH v3 6/6] dma: Let dma_memory_map() take MemTxAttrs argument Date: Fri, 2 Jul 2021 11:24:39 +0200 Message-Id: <20210702092439.989969-7-philmd@redhat.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210702092439.989969-1-philmd@redhat.com> References: <20210702092439.989969-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1625217916309100001 Let devices specify transaction attributes when calling dma_memory_map(). Patch created mechanically using spatch with this script: @@ expression E1, E2, E3, E4; @@ - dma_memory_map(E1, E2, E3, E4) + dma_memory_map(E1, E2, E3, E4, MEMTXATTRS_UNSPECIFIED) Reviewed-by: Richard Henderson Reviewed-by: Li Qiang Reviewed-by: Edgar E. Iglesias Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Stefan Hajnoczi --- include/hw/pci/pci.h | 3 ++- include/sysemu/dma.h | 5 +++-- hw/display/virtio-gpu.c | 10 ++++++---- hw/hyperv/vmbus.c | 8 +++++--- hw/ide/ahci.c | 8 +++++--- hw/usb/libhw.c | 3 ++- hw/virtio/virtio.c | 6 ++++-- softmmu/dma-helpers.c | 3 ++- 8 files changed, 29 insertions(+), 17 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 252c91686de..49d86d4e5dd 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -868,7 +868,8 @@ static inline void *pci_dma_map(PCIDevice *dev, dma_add= r_t addr, { void *buf; =20 - buf =3D dma_memory_map(pci_get_address_space(dev), addr, plen, dir); + buf =3D dma_memory_map(pci_get_address_space(dev), addr, plen, dir, + MEMTXATTRS_UNSPECIFIED); return buf; } =20 diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h index 522682bf386..97ff6f29f8c 100644 --- a/include/sysemu/dma.h +++ b/include/sysemu/dma.h @@ -202,16 +202,17 @@ MemTxResult dma_memory_set(AddressSpace *as, dma_addr= _t addr, * @addr: address within that address space * @len: pointer to length of buffer; updated on return * @dir: indicates the transfer direction + * @attrs: memory attributes */ static inline void *dma_memory_map(AddressSpace *as, dma_addr_t addr, dma_addr_t *len, - DMADirection dir) + DMADirection dir, MemTxAttrs attrs) { hwaddr xlen =3D *len; void *p; =20 p =3D address_space_map(as, addr, &xlen, dir =3D=3D DMA_DIRECTION_FROM= _DEVICE, - MEMTXATTRS_UNSPECIFIED); + attrs); *len =3D xlen; return p; } diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c index e183f4ecdaa..ea64470cc53 100644 --- a/hw/display/virtio-gpu.c +++ b/hw/display/virtio-gpu.c @@ -820,8 +820,9 @@ int virtio_gpu_create_mapping_iov(VirtIOGPU *g, =20 do { len =3D l; - map =3D dma_memory_map(VIRTIO_DEVICE(g)->dma_as, - a, &len, DMA_DIRECTION_TO_DEVICE); + map =3D dma_memory_map(VIRTIO_DEVICE(g)->dma_as, a, &len, + DMA_DIRECTION_TO_DEVICE, + MEMTXATTRS_UNSPECIFIED); if (!map) { qemu_log_mask(LOG_GUEST_ERROR, "%s: failed to map MMIO mem= ory for" " element %d\n", __func__, e); @@ -1232,8 +1233,9 @@ static int virtio_gpu_load(QEMUFile *f, void *opaque,= size_t size, for (i =3D 0; i < res->iov_cnt; i++) { hwaddr len =3D res->iov[i].iov_len; res->iov[i].iov_base =3D - dma_memory_map(VIRTIO_DEVICE(g)->dma_as, - res->addrs[i], &len, DMA_DIRECTION_TO_DEVIC= E); + dma_memory_map(VIRTIO_DEVICE(g)->dma_as, res->addrs[i], &l= en, + DMA_DIRECTION_TO_DEVICE, + MEMTXATTRS_UNSPECIFIED); =20 if (!res->iov[i].iov_base || len !=3D res->iov[i].iov_len) { /* Clean up the half-a-mapping we just created... */ diff --git a/hw/hyperv/vmbus.c b/hw/hyperv/vmbus.c index 984caf898dc..25420eaea38 100644 --- a/hw/hyperv/vmbus.c +++ b/hw/hyperv/vmbus.c @@ -373,7 +373,8 @@ static ssize_t gpadl_iter_io(GpadlIter *iter, void *buf= , uint32_t len) =20 maddr =3D (iter->gpadl->gfns[idx] << TARGET_PAGE_BITS) | off_i= n_page; =20 - iter->map =3D dma_memory_map(iter->as, maddr, &mlen, iter->dir= ); + iter->map =3D dma_memory_map(iter->as, maddr, &mlen, iter->dir, + MEMTXATTRS_UNSPECIFIED); if (mlen !=3D pgleft) { dma_memory_unmap(iter->as, iter->map, mlen, iter->dir, 0); iter->map =3D NULL; @@ -490,7 +491,8 @@ int vmbus_map_sgl(VMBusChanReq *req, DMADirection dir, = struct iovec *iov, goto err; } =20 - iov[ret_cnt].iov_base =3D dma_memory_map(sgl->as, a, &l, dir); + iov[ret_cnt].iov_base =3D dma_memory_map(sgl->as, a, &l, dir, + MEMTXATTRS_UNSPECIFIED); if (!l) { ret =3D -EFAULT; goto err; @@ -566,7 +568,7 @@ static vmbus_ring_buffer *ringbuf_map_hdr(VMBusRingBufC= ommon *ringbuf) dma_addr_t mlen =3D sizeof(*rb); =20 rb =3D dma_memory_map(ringbuf->as, ringbuf->rb_addr, &mlen, - DMA_DIRECTION_FROM_DEVICE); + DMA_DIRECTION_FROM_DEVICE, MEMTXATTRS_UNSPECIFIED); if (mlen !=3D sizeof(*rb)) { dma_memory_unmap(ringbuf->as, rb, mlen, DMA_DIRECTION_FROM_DEVICE, 0); diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index f2c51574839..0b4acb4a783 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -249,7 +249,8 @@ static void map_page(AddressSpace *as, uint8_t **ptr, u= int64_t addr, dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); } =20 - *ptr =3D dma_memory_map(as, addr, &len, DMA_DIRECTION_FROM_DEVICE); + *ptr =3D dma_memory_map(as, addr, &len, DMA_DIRECTION_FROM_DEVICE, + MEMTXATTRS_UNSPECIFIED); if (len < wanted && *ptr) { dma_memory_unmap(as, *ptr, len, DMA_DIRECTION_FROM_DEVICE, len); *ptr =3D NULL; @@ -939,7 +940,8 @@ static int ahci_populate_sglist(AHCIDevice *ad, QEMUSGL= ist *sglist, =20 /* map PRDT */ if (!(prdt =3D dma_memory_map(ad->hba->as, prdt_addr, &prdt_len, - DMA_DIRECTION_TO_DEVICE))){ + DMA_DIRECTION_TO_DEVICE, + MEMTXATTRS_UNSPECIFIED))){ trace_ahci_populate_sglist_no_map(ad->hba, ad->port_no); return -1; } @@ -1301,7 +1303,7 @@ static int handle_cmd(AHCIState *s, int port, uint8_t= slot) tbl_addr =3D le64_to_cpu(cmd->tbl_addr); cmd_len =3D 0x80; cmd_fis =3D dma_memory_map(s->as, tbl_addr, &cmd_len, - DMA_DIRECTION_TO_DEVICE); + DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFI= ED); if (!cmd_fis) { trace_handle_cmd_badfis(s, port); return -1; diff --git a/hw/usb/libhw.c b/hw/usb/libhw.c index 9c33a1640f7..f350eae443d 100644 --- a/hw/usb/libhw.c +++ b/hw/usb/libhw.c @@ -36,7 +36,8 @@ int usb_packet_map(USBPacket *p, QEMUSGList *sgl) =20 while (len) { dma_addr_t xlen =3D len; - mem =3D dma_memory_map(sgl->as, base, &xlen, dir); + mem =3D dma_memory_map(sgl->as, base, &xlen, dir, + MEMTXATTRS_UNSPECIFIED); if (!mem) { goto err; } diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index ab516ac6144..b812aeb6057 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -1320,7 +1320,8 @@ static bool virtqueue_map_desc(VirtIODevice *vdev, un= signed int *p_num_sg, iov[num_sg].iov_base =3D dma_memory_map(vdev->dma_as, pa, &len, is_write ? DMA_DIRECTION_FROM_DEVICE : - DMA_DIRECTION_TO_DEVICE); + DMA_DIRECTION_TO_DEVICE, + MEMTXATTRS_UNSPECIFIED); if (!iov[num_sg].iov_base) { virtio_error(vdev, "virtio: bogus descriptor or out of resourc= es"); goto out; @@ -1369,7 +1370,8 @@ static void virtqueue_map_iovec(VirtIODevice *vdev, s= truct iovec *sg, sg[i].iov_base =3D dma_memory_map(vdev->dma_as, addr[i], &len, is_write ? DMA_DIRECTION_FROM_DEVICE : - DMA_DIRECTION_TO_DEVICE); + DMA_DIRECTION_TO_DEVICE, + MEMTXATTRS_UNSPECIFIED); if (!sg[i].iov_base) { error_report("virtio: error trying to map MMIO memory"); exit(1); diff --git a/softmmu/dma-helpers.c b/softmmu/dma-helpers.c index 5bf76fff6bd..3c06a2feddd 100644 --- a/softmmu/dma-helpers.c +++ b/softmmu/dma-helpers.c @@ -143,7 +143,8 @@ static void dma_blk_cb(void *opaque, int ret) while (dbs->sg_cur_index < dbs->sg->nsg) { cur_addr =3D dbs->sg->sg[dbs->sg_cur_index].base + dbs->sg_cur_byt= e; cur_len =3D dbs->sg->sg[dbs->sg_cur_index].len - dbs->sg_cur_byte; - mem =3D dma_memory_map(dbs->sg->as, cur_addr, &cur_len, dbs->dir); + mem =3D dma_memory_map(dbs->sg->as, cur_addr, &cur_len, dbs->dir, + MEMTXATTRS_UNSPECIFIED); /* * Make reads deterministic in icount mode. Windows sometimes issu= es * disk read requests with overlapping SGs. It leads --=20 2.31.1