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Use pc_first instead of tb->pc. Increment pc_next prior to decode, leaving the address of the current insn in dc->pc. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/translate.c | 70 +++++++++++++++++++++------------------- 1 file changed, 36 insertions(+), 34 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 6bdd388bd8..12f987651a 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -97,12 +97,10 @@ } =20 typedef struct DisasContext { + DisasContextBase base; TCGv_i32 zero; - int is_jmp; target_ulong pc; - TranslationBlock *tb; int mem_idx; - bool singlestep_enabled; } DisasContext; =20 static TCGv cpu_R[NUM_CORE_REGS]; @@ -149,17 +147,17 @@ static void t_gen_helper_raise_exception(DisasContext= *dc, tcg_gen_movi_tl(cpu_R[R_PC], dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; } =20 static bool use_goto_tb(DisasContext *dc, uint32_t dest) { - if (unlikely(dc->singlestep_enabled)) { + if (unlikely(dc->base.singlestep_enabled)) { return false; } =20 #ifndef CONFIG_USER_ONLY - return (dc->tb->pc & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PAGE_MASK= ); + return (dc->base.pc_first & TARGET_PAGE_MASK) =3D=3D (dest & TARGET_PA= GE_MASK); #else return true; #endif @@ -167,7 +165,7 @@ static bool use_goto_tb(DisasContext *dc, uint32_t dest) =20 static void gen_goto_tb(DisasContext *dc, int n, uint32_t dest) { - TranslationBlock *tb =3D dc->tb; + const TranslationBlock *tb =3D dc->base.tb; =20 if (use_goto_tb(dc, dest)) { tcg_gen_goto_tb(n); @@ -186,7 +184,7 @@ static void gen_excp(DisasContext *dc, uint32_t code, u= int32_t flags) =20 static void gen_check_supervisor(DisasContext *dc) { - if (dc->tb->flags & CR_STATUS_U) { + if (dc->base.tb->flags & CR_STATUS_U) { /* CPU in user mode, privileged instruction called, stop. */ t_gen_helper_raise_exception(dc, EXCP_SUPERI); } @@ -208,7 +206,7 @@ static void jmpi(DisasContext *dc, uint32_t code, uint3= 2_t flags) { J_TYPE(instr, code); gen_goto_tb(dc, 0, (dc->pc & 0xF0000000) | (instr.imm26 << 2)); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; } =20 static void call(DisasContext *dc, uint32_t code, uint32_t flags) @@ -268,7 +266,7 @@ static void br(DisasContext *dc, uint32_t code, uint32_= t flags) I_TYPE(instr, code); =20 gen_goto_tb(dc, 0, dc->pc + 4 + (instr.imm16.s & -4)); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_bxx(DisasContext *dc, uint32_t code, uint32_t flags) @@ -280,7 +278,7 @@ static void gen_bxx(DisasContext *dc, uint32_t code, ui= nt32_t flags) gen_goto_tb(dc, 0, dc->pc + 4); gen_set_label(l1); gen_goto_tb(dc, 1, dc->pc + 4 + (instr.imm16.s & -4)); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; } =20 /* Comparison instructions */ @@ -402,7 +400,7 @@ static void eret(DisasContext *dc, uint32_t code, uint3= 2_t flags) tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]); tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_EA]); =20 - dc->is_jmp =3D DISAS_JUMP; + dc->base.is_jmp =3D DISAS_JUMP; } =20 /* PC <- ra */ @@ -410,7 +408,7 @@ static void ret(DisasContext *dc, uint32_t code, uint32= _t flags) { tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_RA]); =20 - dc->is_jmp =3D DISAS_JUMP; + dc->base.is_jmp =3D DISAS_JUMP; } =20 /* PC <- ba */ @@ -418,7 +416,7 @@ static void bret(DisasContext *dc, uint32_t code, uint3= 2_t flags) { tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_BA]); =20 - dc->is_jmp =3D DISAS_JUMP; + dc->base.is_jmp =3D DISAS_JUMP; } =20 /* PC <- rA */ @@ -428,7 +426,7 @@ static void jmp(DisasContext *dc, uint32_t code, uint32= _t flags) =20 tcg_gen_mov_tl(cpu_R[R_PC], load_gpr(dc, instr.a)); =20 - dc->is_jmp =3D DISAS_JUMP; + dc->base.is_jmp =3D DISAS_JUMP; } =20 /* rC <- PC + 4 */ @@ -452,7 +450,7 @@ static void callr(DisasContext *dc, uint32_t code, uint= 32_t flags) tcg_gen_mov_tl(cpu_R[R_PC], load_gpr(dc, instr.a)); tcg_gen_movi_tl(cpu_R[R_RA], dc->pc + 4); =20 - dc->is_jmp =3D DISAS_JUMP; + dc->base.is_jmp =3D DISAS_JUMP; } =20 /* rC <- ctlN */ @@ -516,11 +514,11 @@ static void wrctl(DisasContext *dc, uint32_t code, ui= nt32_t flags) /* If interrupts were enabled using WRCTL, trigger them. */ #if !defined(CONFIG_USER_ONLY) if ((instr.imm5 + CR_BASE) =3D=3D CR_STATUS) { - if (tb_cflags(dc->tb) & CF_USE_ICOUNT) { + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } gen_helper_check_interrupts(cpu_env); - dc->is_jmp =3D DISAS_UPDATE; + dc->base.is_jmp =3D DISAS_UPDATE; } #endif } @@ -801,7 +799,7 @@ static void gen_exception(DisasContext *dc, uint32_t ex= cp) tcg_gen_movi_tl(cpu_R[R_PC], dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); - dc->is_jmp =3D DISAS_NORETURN; + dc->base.is_jmp =3D DISAS_NORETURN; } =20 /* generate intermediate code for basic block 'tb'. */ @@ -812,11 +810,14 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) int num_insns; =20 /* Initialize DC */ - dc->is_jmp =3D DISAS_NEXT; - dc->pc =3D tb->pc; - dc->tb =3D tb; + + dc->base.tb =3D tb; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.pc_first =3D tb->pc; + dc->base.pc_next =3D tb->pc; + dc->mem_idx =3D cpu_mmu_index(env, false); - dc->singlestep_enabled =3D cs->singlestep_enabled; =20 /* Set up instruction counts */ num_insns =3D 0; @@ -829,10 +830,10 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) =20 gen_tb_start(tb); do { - tcg_gen_insn_start(dc->pc); + tcg_gen_insn_start(dc->base.pc_next); num_insns++; =20 - if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { + if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) { gen_exception(dc, EXCP_DEBUG); /* The address covered by the breakpoint must be included in [tb->pc, tb->pc + tb->size) in order to for it to be @@ -846,25 +847,26 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) gen_io_start(); } =20 + dc->pc =3D dc->base.pc_next; + dc->base.pc_next +=3D 4; + /* Decode an instruction */ handle_instruction(dc, env); =20 - dc->pc +=3D 4; - /* Translation stops when a conditional branch is encountered. * Otherwise the subsequent code could get translated several time= s. * Also stop translation when a page boundary is reached. This * ensures prefetch aborts occur at the right place. */ - } while (!dc->is_jmp && + } while (!dc->base.is_jmp && !tcg_op_buf_full() && num_insns < max_insns); =20 /* Indicate where the next block should start */ - switch (dc->is_jmp) { + switch (dc->base.is_jmp) { case DISAS_NEXT: case DISAS_UPDATE: /* Save the current PC back into the CPU register */ - tcg_gen_movi_tl(cpu_R[R_PC], dc->pc); + tcg_gen_movi_tl(cpu_R[R_PC], dc->base.pc_next); tcg_gen_exit_tb(NULL, 0); break; =20 @@ -883,15 +885,15 @@ void gen_intermediate_code(CPUState *cs, TranslationB= lock *tb, int max_insns) gen_tb_end(tb, num_insns); =20 /* Mark instruction starts for the final generated instruction */ - tb->size =3D dc->pc - tb->pc; + tb->size =3D dc->pc - dc->base.pc_first; tb->icount =3D num_insns; =20 #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) - && qemu_log_in_addr_range(tb->pc)) { + && qemu_log_in_addr_range(dc->base.pc_first)) { FILE *logfile =3D qemu_log_lock(); - qemu_log("IN: %s\n", lookup_symbol(tb->pc)); - log_target_disas(cs, tb->pc, dc->pc - tb->pc); + qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first)); + log_target_disas(cs, tb->pc, dc->base.pc_next - dc->base.pc_first); qemu_log("\n"); qemu_log_unlock(logfile); } --=20 2.25.1