From nobody Tue Feb 10 04:17:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1624889252; cv=none; d=zohomail.com; s=zohoarc; b=QoTE/m7eI7ZEIGxhspxwfdc97E1JiKiEcZdwGxCgTWVhcvPM14TQD7GoWzFjt100L3hKojuDCHtLIZhhVSZ3T1WAeBmferIKXpz9Ic2GIukdLA2HUi/eqyPPs1cOVwexD/Dbc15ONuwWJc+SAWsmqV5Omn/xtC17lh1Z/Jx7SUw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1624889252; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9E74MPT3ybVV57GDlruswg0m9Iqe4oPECULw0v5ivl0=; b=ASgTC47c/A26Cl+t8no5NMLhUMQvm/bhre70rdxf2CGY1rz1nckW6S3Wbp6tTs0ncIK/yuSa5SjYvDqoy/cjBPb74/U8AN4Mgl1Ob44dmfjfUYj9q9uEXpvB++YqK1R9xaZtqqQCfgV6D3D9XEfcem6YTdmDP/PviekWBe6pFgs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624889252591198.25362662133557; Mon, 28 Jun 2021 07:07:32 -0700 (PDT) Received: from localhost ([::1]:43860 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lxrv9-0000NU-CI for importer@patchew.org; Mon, 28 Jun 2021 10:07:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48834) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lxrmr-00036Q-ND for qemu-devel@nongnu.org; Mon, 28 Jun 2021 09:58:57 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:36444) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lxrmb-00061x-JV for qemu-devel@nongnu.org; Mon, 28 Jun 2021 09:58:57 -0400 Received: by mail-wr1-x42c.google.com with SMTP id y3so1999468wrq.3 for ; Mon, 28 Jun 2021 06:58:41 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d12sm12047627wri.77.2021.06.28.06.58.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Jun 2021 06:58:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9E74MPT3ybVV57GDlruswg0m9Iqe4oPECULw0v5ivl0=; b=JfaKf03xleAvSflBHEEk4YHIagi3zZgVPVH5F7qQIOVSEd5olZPWHfLq5ZHny7v9Qq rnFJ1GuabtipkCtlLOui4SooxpC7ZUdX300W0jUiWG9EfZxxGvTXjHPQtKr2D/bf7HBF 5LF/PrKDHp5/DEz88mWyi8i7XIKnUSWfwCLy2zrOE/M7fDDieCe+g/aLYQ3LH3NOa7v/ MG+wTFXlXjeyOjgg8s8fub1u+zWWhJAPQzSws4KtOXQsgZEY/W6N/+Z8t/A/JMakwb2J V2Zk+3dXPgoAANwJpv4mMivBaMQvByJHQfRko6Ivsxwz7kqSPzlJlvguDumb4rPOGVRn IHvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9E74MPT3ybVV57GDlruswg0m9Iqe4oPECULw0v5ivl0=; b=HnrazK42urjzjn5Z1+ZnuHLUZ9dHhl4uSAdB0x2gK7jhVJKQ5L+5g6JLiPBED3UNEY 0yx0XyixzoVhDFZsG5jbHWQKsKncUHGIzA2T3Sa8oUz8vrQbyQ+trznXDABdbD8vdJqm z1Fi/fkF5EsqdTOE9GWniJo0p2dduIodGVmQKsrJN5xAvQMy39MfOwmwVDWjbkNJOJT6 PqC0PRl3u/odaK8XkdwV0v9QPUUbDDQKkFbiDXJJgie35t3rsjOk2CEtlafZNZq1rbdZ 63aVg7DMJ9Qd4cGNaJW+R63kSRPiVwzrxzodqixXVtXcSXKM8hmwKo+EkvXdWLiF1+35 qNYw== X-Gm-Message-State: AOAM533Br+Uf+hZnsFH2mRwLwV67h2tTDiI2idiMouWocOV++r/LdGJ4 mD/dIdBgP3UVoPUT7La5iIkKUA== X-Google-Smtp-Source: ABdhPJzOexE4+GsL+HxzvMzStVOSLbDTEihiX5Ho0yoF3PX46cqF5cFDeUVq2D1R6cX9DdW8JcEO8g== X-Received: by 2002:adf:ec8b:: with SMTP id z11mr2067204wrn.408.1624888720280; Mon, 28 Jun 2021 06:58:40 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/18] target/arm: Use asimd_imm_const for A64 decode Date: Mon, 28 Jun 2021 14:58:21 +0100 Message-Id: <20210628135835.6690-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210628135835.6690-1-peter.maydell@linaro.org> References: <20210628135835.6690-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The A64 AdvSIMD modified-immediate grouping uses almost the same constant encoding that A32 Neon does; reuse asimd_imm_const() (to which we add the AArch64-specific case for cmode 15 op 1) instead of reimplementing it all. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate.h | 3 +- target/arm/translate-a64.c | 86 ++++---------------------------------- target/arm/translate.c | 17 +++++++- 3 files changed, 24 insertions(+), 82 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 6c8d5f6ede1..e2f056c32c2 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -540,7 +540,8 @@ static inline MemOp finalize_memop(DisasContext *s, Mem= Op opc) * VMVN and VBIC (when cmode < 14 && op =3D=3D 1). * * The combination cmode =3D=3D 15 op =3D=3D 1 is a reserved encoding for = AArch32; - * callers must catch this. + * callers must catch this; we return the 64-bit constant value defined + * for AArch64. * * cmode =3D 2,3,4,5,6,7,10,11,12,13 imm=3D0 was UNPREDICTABLE in v7A but * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7f74d0e81a9..97b4a41a0c7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -8199,8 +8199,6 @@ static void disas_simd_mod_imm(DisasContext *s, uint3= 2_t insn) { int rd =3D extract32(insn, 0, 5); int cmode =3D extract32(insn, 12, 4); - int cmode_3_1 =3D extract32(cmode, 1, 3); - int cmode_0 =3D extract32(cmode, 0, 1); int o2 =3D extract32(insn, 11, 1); uint64_t abcdefgh =3D extract32(insn, 5, 5) | (extract32(insn, 16, 3) = << 5); bool is_neg =3D extract32(insn, 29, 1); @@ -8219,83 +8217,13 @@ static void disas_simd_mod_imm(DisasContext *s, uin= t32_t insn) return; } =20 - /* See AdvSIMDExpandImm() in ARM ARM */ - switch (cmode_3_1) { - case 0: /* Replicate(Zeros(24):imm8, 2) */ - case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */ - case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */ - case 3: /* Replicate(imm8:Zeros(24), 2) */ - { - int shift =3D cmode_3_1 * 8; - imm =3D bitfield_replicate(abcdefgh << shift, 32); - break; - } - case 4: /* Replicate(Zeros(8):imm8, 4) */ - case 5: /* Replicate(imm8:Zeros(8), 4) */ - { - int shift =3D (cmode_3_1 & 0x1) * 8; - imm =3D bitfield_replicate(abcdefgh << shift, 16); - break; - } - case 6: - if (cmode_0) { - /* Replicate(Zeros(8):imm8:Ones(16), 2) */ - imm =3D (abcdefgh << 16) | 0xffff; - } else { - /* Replicate(Zeros(16):imm8:Ones(8), 2) */ - imm =3D (abcdefgh << 8) | 0xff; - } - imm =3D bitfield_replicate(imm, 32); - break; - case 7: - if (!cmode_0 && !is_neg) { - imm =3D bitfield_replicate(abcdefgh, 8); - } else if (!cmode_0 && is_neg) { - int i; - imm =3D 0; - for (i =3D 0; i < 8; i++) { - if ((abcdefgh) & (1 << i)) { - imm |=3D 0xffULL << (i * 8); - } - } - } else if (cmode_0) { - if (is_neg) { - imm =3D (abcdefgh & 0x3f) << 48; - if (abcdefgh & 0x80) { - imm |=3D 0x8000000000000000ULL; - } - if (abcdefgh & 0x40) { - imm |=3D 0x3fc0000000000000ULL; - } else { - imm |=3D 0x4000000000000000ULL; - } - } else { - if (o2) { - /* FMOV (vector, immediate) - half-precision */ - imm =3D vfp_expand_imm(MO_16, abcdefgh); - /* now duplicate across the lanes */ - imm =3D bitfield_replicate(imm, 16); - } else { - imm =3D (abcdefgh & 0x3f) << 19; - if (abcdefgh & 0x80) { - imm |=3D 0x80000000; - } - if (abcdefgh & 0x40) { - imm |=3D 0x3e000000; - } else { - imm |=3D 0x40000000; - } - imm |=3D (imm << 32); - } - } - } - break; - default: - g_assert_not_reached(); - } - - if (cmode_3_1 !=3D 7 && is_neg) { - imm =3D ~imm; + if (cmode =3D=3D 15 && o2 && !is_neg) { + /* FMOV (vector, immediate) - half-precision */ + imm =3D vfp_expand_imm(MO_16, abcdefgh); + /* now duplicate across the lanes */ + imm =3D bitfield_replicate(imm, 16); + } else { + imm =3D asimd_imm_const(abcdefgh, cmode, is_neg); } =20 if (!((cmode & 0x9) =3D=3D 0x1 || (cmode & 0xd) =3D=3D 0x9)) { diff --git a/target/arm/translate.c b/target/arm/translate.c index 97eea935433..3cb9996a509 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -121,8 +121,8 @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int o= p) case 14: if (op) { /* - * This is the only case where the top and bottom 32 bits - * of the encoded constant differ. + * This and cmode =3D=3D 15 op =3D=3D 1 are the only cases whe= re + * the top and bottom 32 bits of the encoded constant differ. */ uint64_t imm64 =3D 0; int n; @@ -137,6 +137,19 @@ uint64_t asimd_imm_const(uint32_t imm, int cmode, int = op) imm |=3D (imm << 8) | (imm << 16) | (imm << 24); break; case 15: + if (op) { + /* Reserved encoding for AArch32; valid for AArch64 */ + uint64_t imm64 =3D (uint64_t)(imm & 0x3f) << 48; + if (imm & 0x80) { + imm64 |=3D 0x8000000000000000ULL; + } + if (imm & 0x40) { + imm64 |=3D 0x3fc0000000000000ULL; + } else { + imm64 |=3D 0x4000000000000000ULL; + } + return imm64; + } imm =3D ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); break; --=20 2.20.1