From nobody Fri May 17 03:54:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624604171713479.14446736356865; Thu, 24 Jun 2021 23:56:11 -0700 (PDT) Received: from localhost ([::1]:49768 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lwfl4-0000Hi-JX for importer@patchew.org; Fri, 25 Jun 2021 02:56:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55848) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjO-0005sA-TM for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:26 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:58688 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjE-0001qA-1P for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:26 -0400 Received: from host109-153-84-9.range109-153.btcentralplus.com ([109.153.84.9] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lwfiv-0006FO-Sv; Fri, 25 Jun 2021 07:54:02 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, hpoussin@reactos.org, aleksandar.rikalo@syrmia.com, f4bug@amsat.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, jasowang@redhat.com, fthain@telegraphics.com.au, laurent@vivier.eu Date: Fri, 25 Jun 2021 07:53:52 +0100 Message-Id: <20210625065401.30170-2-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> References: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 109.153.84.9 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 01/10] dp8393x: checkpatch fixes X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Also fix a simple comment typo of "constrainst" to "constraints". Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Finn Thain --- hw/net/dp8393x.c | 231 +++++++++++++++++++++++++---------------------- 1 file changed, 122 insertions(+), 109 deletions(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index 533a8304d0..56af08f0fe 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -29,14 +29,14 @@ #include #include "qom/object.h" =20 -//#define DEBUG_SONIC +/* #define DEBUG_SONIC */ =20 #define SONIC_PROM_SIZE 0x1000 =20 #ifdef DEBUG_SONIC #define DPRINTF(fmt, ...) \ do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0) -static const char* reg_names[] =3D { +static const char *reg_names[] =3D { "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA", "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0", "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP", @@ -185,7 +185,8 @@ struct dp8393xState { AddressSpace as; }; =20 -/* Accessor functions for values which are formed by +/* + * Accessor functions for values which are formed by * concatenating two 16 bit device registers. By putting these * in their own functions with a uint32_t return type we avoid the * pitfall of implicit sign extension where ((x << 16) | y) is a @@ -350,8 +351,7 @@ static void dp8393x_do_read_rra(dp8393xState *s) } =20 /* Warn the host if CRBA now has the last available resource */ - if (s->regs[SONIC_RRP] =3D=3D s->regs[SONIC_RWP]) - { + if (s->regs[SONIC_RRP] =3D=3D s->regs[SONIC_RWP]) { s->regs[SONIC_ISR] |=3D SONIC_ISR_RBE; dp8393x_update_irq(s); } @@ -364,7 +364,8 @@ static void dp8393x_do_software_reset(dp8393xState *s) { timer_del(s->watchdog); =20 - s->regs[SONIC_CR] &=3D ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP = | SONIC_CR_HTX); + s->regs[SONIC_CR] &=3D ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | + SONIC_CR_HTX); s->regs[SONIC_CR] |=3D SONIC_CR_RST | SONIC_CR_RXDIS; } =20 @@ -490,8 +491,10 @@ static void dp8393x_do_transmit_packets(dp8393xState *= s) =20 /* Handle Ethernet checksum */ if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) { - /* Don't append FCS there, to look like slirp packets - * which don't have one */ + /* + * Don't append FCS there, to look like slirp packets + * which don't have one + */ } else { /* Remove existing FCS */ tx_len -=3D 4; @@ -558,26 +561,34 @@ static void dp8393x_do_command(dp8393xState *s, uint1= 6_t command) =20 s->regs[SONIC_CR] |=3D (command & SONIC_CR_MASK); =20 - if (command & SONIC_CR_HTX) + if (command & SONIC_CR_HTX) { dp8393x_do_halt_transmission(s); - if (command & SONIC_CR_TXP) + } + if (command & SONIC_CR_TXP) { dp8393x_do_transmit_packets(s); - if (command & SONIC_CR_RXDIS) + } + if (command & SONIC_CR_RXDIS) { dp8393x_do_receiver_disable(s); - if (command & SONIC_CR_RXEN) + } + if (command & SONIC_CR_RXEN) { dp8393x_do_receiver_enable(s); - if (command & SONIC_CR_STP) + } + if (command & SONIC_CR_STP) { dp8393x_do_stop_timer(s); - if (command & SONIC_CR_ST) + } + if (command & SONIC_CR_ST) { dp8393x_do_start_timer(s); - if (command & SONIC_CR_RST) + } + if (command & SONIC_CR_RST) { dp8393x_do_software_reset(s); + } if (command & SONIC_CR_RRRA) { dp8393x_do_read_rra(s); s->regs[SONIC_CR] &=3D ~SONIC_CR_RRRA; } - if (command & SONIC_CR_LCAM) + if (command & SONIC_CR_LCAM) { dp8393x_do_load_cam(s); + } } =20 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size) @@ -587,24 +598,24 @@ static uint64_t dp8393x_read(void *opaque, hwaddr add= r, unsigned int size) uint16_t val =3D 0; =20 switch (reg) { - /* Update data before reading it */ - case SONIC_WT0: - case SONIC_WT1: - dp8393x_update_wt_regs(s); - val =3D s->regs[reg]; - break; - /* Accept read to some registers only when in reset mode */ - case SONIC_CAP2: - case SONIC_CAP1: - case SONIC_CAP0: - if (s->regs[SONIC_CR] & SONIC_CR_RST) { - val =3D s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - = reg) + 1] << 8; - val |=3D s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 -= reg)]; - } - break; - /* All other registers have no special contrainst */ - default: - val =3D s->regs[reg]; + /* Update data before reading it */ + case SONIC_WT0: + case SONIC_WT1: + dp8393x_update_wt_regs(s); + val =3D s->regs[reg]; + break; + /* Accept read to some registers only when in reset mode */ + case SONIC_CAP2: + case SONIC_CAP1: + case SONIC_CAP0: + if (s->regs[SONIC_CR] & SONIC_CR_RST) { + val =3D s->cam[s->regs[SONIC_CEP] & 0xf][2 * (SONIC_CAP0 - reg= ) + 1] << 8; + val |=3D s->cam[s->regs[SONIC_CEP] & 0xf][2 * (SONIC_CAP0 - re= g)]; + } + break; + /* All other registers have no special contraints */ + default: + val =3D s->regs[reg]; } =20 DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]); @@ -622,75 +633,75 @@ static void dp8393x_write(void *opaque, hwaddr addr, = uint64_t data, DPRINTF("write 0x%04x to reg %s\n", (uint16_t)val, reg_names[reg]); =20 switch (reg) { - /* Command register */ - case SONIC_CR: - dp8393x_do_command(s, val); - break; - /* Prevent write to read-only registers */ - case SONIC_CAP2: - case SONIC_CAP1: - case SONIC_CAP0: - case SONIC_SR: - case SONIC_MDT: - DPRINTF("writing to reg %d invalid\n", reg); - break; - /* Accept write to some registers only when in reset mode */ - case SONIC_DCR: - if (s->regs[SONIC_CR] & SONIC_CR_RST) { - s->regs[reg] =3D val & 0xbfff; - } else { - DPRINTF("writing to DCR invalid\n"); - } - break; - case SONIC_DCR2: - if (s->regs[SONIC_CR] & SONIC_CR_RST) { - s->regs[reg] =3D val & 0xf017; - } else { - DPRINTF("writing to DCR2 invalid\n"); - } - break; - /* 12 lower bytes are Read Only */ - case SONIC_TCR: - s->regs[reg] =3D val & 0xf000; - break; - /* 9 lower bytes are Read Only */ - case SONIC_RCR: - s->regs[reg] =3D val & 0xffe0; - break; - /* Ignore most significant bit */ - case SONIC_IMR: - s->regs[reg] =3D val & 0x7fff; - dp8393x_update_irq(s); - break; - /* Clear bits by writing 1 to them */ - case SONIC_ISR: - val &=3D s->regs[reg]; - s->regs[reg] &=3D ~val; - if (val & SONIC_ISR_RBE) { - dp8393x_do_read_rra(s); - } - dp8393x_update_irq(s); - break; - /* The guest is required to store aligned pointers here */ - case SONIC_RSA: - case SONIC_REA: - case SONIC_RRP: - case SONIC_RWP: - if (s->regs[SONIC_DCR] & SONIC_DCR_DW) { - s->regs[reg] =3D val & 0xfffc; - } else { - s->regs[reg] =3D val & 0xfffe; - } - break; - /* Invert written value for some registers */ - case SONIC_CRCT: - case SONIC_FAET: - case SONIC_MPT: - s->regs[reg] =3D val ^ 0xffff; - break; - /* All other registers have no special contrainst */ - default: - s->regs[reg] =3D val; + /* Command register */ + case SONIC_CR: + dp8393x_do_command(s, val); + break; + /* Prevent write to read-only registers */ + case SONIC_CAP2: + case SONIC_CAP1: + case SONIC_CAP0: + case SONIC_SR: + case SONIC_MDT: + DPRINTF("writing to reg %d invalid\n", reg); + break; + /* Accept write to some registers only when in reset mode */ + case SONIC_DCR: + if (s->regs[SONIC_CR] & SONIC_CR_RST) { + s->regs[reg] =3D val & 0xbfff; + } else { + DPRINTF("writing to DCR invalid\n"); + } + break; + case SONIC_DCR2: + if (s->regs[SONIC_CR] & SONIC_CR_RST) { + s->regs[reg] =3D val & 0xf017; + } else { + DPRINTF("writing to DCR2 invalid\n"); + } + break; + /* 12 lower bytes are Read Only */ + case SONIC_TCR: + s->regs[reg] =3D val & 0xf000; + break; + /* 9 lower bytes are Read Only */ + case SONIC_RCR: + s->regs[reg] =3D val & 0xffe0; + break; + /* Ignore most significant bit */ + case SONIC_IMR: + s->regs[reg] =3D val & 0x7fff; + dp8393x_update_irq(s); + break; + /* Clear bits by writing 1 to them */ + case SONIC_ISR: + val &=3D s->regs[reg]; + s->regs[reg] &=3D ~val; + if (val & SONIC_ISR_RBE) { + dp8393x_do_read_rra(s); + } + dp8393x_update_irq(s); + break; + /* The guest is required to store aligned pointers here */ + case SONIC_RSA: + case SONIC_REA: + case SONIC_RRP: + case SONIC_RWP: + if (s->regs[SONIC_DCR] & SONIC_DCR_DW) { + s->regs[reg] =3D val & 0xfffc; + } else { + s->regs[reg] =3D val & 0xfffe; + } + break; + /* Invert written value for some registers */ + case SONIC_CRCT: + case SONIC_FAET: + case SONIC_MPT: + s->regs[reg] =3D val ^ 0xffff; + break; + /* All other registers have no special contrainst */ + default: + s->regs[reg] =3D val; } =20 if (reg =3D=3D SONIC_WT0 || reg =3D=3D SONIC_WT1) { @@ -747,17 +758,18 @@ static int dp8393x_receive_filter(dp8393xState *s, co= nst uint8_t * buf, } =20 /* Check broadcast */ - if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof= (bcast))) { + if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && + !memcmp(buf, bcast, sizeof(bcast))) { return SONIC_RCR_BC; } =20 /* Check CAM */ for (i =3D 0; i < 16; i++) { if (s->regs[SONIC_CE] & (1 << i)) { - /* Entry enabled */ - if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) { - return 0; - } + /* Entry enabled */ + if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) { + return 0; + } } } =20 @@ -938,7 +950,8 @@ static void dp8393x_reset(DeviceState *dev) s->regs[SONIC_SR] =3D 0x0004; /* only revision recognized by Linux/mip= s */ s->regs[SONIC_CR] =3D SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS; s->regs[SONIC_DCR] &=3D ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR); - s->regs[SONIC_RCR] &=3D ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BR= D | SONIC_RCR_RNT); + s->regs[SONIC_RCR] &=3D ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BR= D | + SONIC_RCR_RNT); s->regs[SONIC_TCR] |=3D SONIC_TCR_NCRS | SONIC_TCR_PTX; s->regs[SONIC_TCR] &=3D ~SONIC_TCR_BCM; s->regs[SONIC_IMR] =3D 0; --=20 2.20.1 From nobody Fri May 17 03:54:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624604318155712.8590836912672; Thu, 24 Jun 2021 23:58:38 -0700 (PDT) Received: from localhost ([::1]:57000 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lwfnR-0005B9-1e for importer@patchew.org; Fri, 25 Jun 2021 02:58:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55798) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjM-0005nt-3X for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:24 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:58694 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjE-0001qL-SK for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:23 -0400 Received: from host109-153-84-9.range109-153.btcentralplus.com ([109.153.84.9] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lwfj0-0006FO-Aq; Fri, 25 Jun 2021 07:54:02 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, hpoussin@reactos.org, aleksandar.rikalo@syrmia.com, f4bug@amsat.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, jasowang@redhat.com, fthain@telegraphics.com.au, laurent@vivier.eu Date: Fri, 25 Jun 2021 07:53:53 +0100 Message-Id: <20210625065401.30170-3-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> References: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 109.153.84.9 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 02/10] dp8393x: convert to trace-events X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Finn Thain --- hw/net/dp8393x.c | 55 +++++++++++++++++---------------------------- hw/net/trace-events | 17 ++++++++++++++ 2 files changed, 37 insertions(+), 35 deletions(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index 56af08f0fe..ea5b22f680 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -28,14 +28,10 @@ #include "qemu/timer.h" #include #include "qom/object.h" - -/* #define DEBUG_SONIC */ +#include "trace.h" =20 #define SONIC_PROM_SIZE 0x1000 =20 -#ifdef DEBUG_SONIC -#define DPRINTF(fmt, ...) \ -do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0) static const char *reg_names[] =3D { "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA", "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0", @@ -45,12 +41,6 @@ static const char *reg_names[] =3D { "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT", "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37", "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" }; -#else -#define DPRINTF(fmt, ...) do {} while (0) -#endif - -#define SONIC_ERROR(fmt, ...) \ -do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (= 0) =20 #define SONIC_CR 0x00 #define SONIC_DCR 0x01 @@ -161,9 +151,7 @@ struct dp8393xState { bool big_endian; bool last_rba_is_full; qemu_irq irq; -#ifdef DEBUG_SONIC int irq_level; -#endif QEMUTimer *watchdog; int64_t wt_last_update; NICConf conf; @@ -270,16 +258,14 @@ static void dp8393x_update_irq(dp8393xState *s) { int level =3D (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0; =20 -#ifdef DEBUG_SONIC if (level !=3D s->irq_level) { s->irq_level =3D level; if (level) { - DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]); + trace_dp8393x_raise_irq(s->regs[SONIC_ISR]); } else { - DPRINTF("lower irq\n"); + trace_dp8393x_lower_irq(); } } -#endif =20 qemu_set_irq(s->irq, level); } @@ -302,9 +288,9 @@ static void dp8393x_do_load_cam(dp8393xState *s) s->cam[index][3] =3D dp8393x_get(s, width, 2) >> 8; s->cam[index][4] =3D dp8393x_get(s, width, 3) & 0xff; s->cam[index][5] =3D dp8393x_get(s, width, 3) >> 8; - DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index, - s->cam[index][0], s->cam[index][1], s->cam[index][2], - s->cam[index][3], s->cam[index][4], s->cam[index][5]); + trace_dp8393x_load_cam(index, s->cam[index][0], s->cam[index][1], + s->cam[index][2], s->cam[index][3], + s->cam[index][4], s->cam[index][5]); /* Move to next entry */ s->regs[SONIC_CDC]--; s->regs[SONIC_CDP] +=3D size; @@ -315,7 +301,7 @@ static void dp8393x_do_load_cam(dp8393xState *s) address_space_read(&s->as, dp8393x_cdp(s), MEMTXATTRS_UNSPECIFIED, s->data, size); s->regs[SONIC_CE] =3D dp8393x_get(s, width, 0); - DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); + trace_dp8393x_load_cam_done(s->regs[SONIC_CE]); =20 /* Done */ s->regs[SONIC_CR] &=3D ~SONIC_CR_LCAM; @@ -338,9 +324,8 @@ static void dp8393x_do_read_rra(dp8393xState *s) s->regs[SONIC_CRBA1] =3D dp8393x_get(s, width, 1); s->regs[SONIC_RBWC0] =3D dp8393x_get(s, width, 2); s->regs[SONIC_RBWC1] =3D dp8393x_get(s, width, 3); - DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n", - s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], - s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]); + trace_dp8393x_read_rra_regs(s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1], + s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]= ); =20 /* Go to next entry */ s->regs[SONIC_RRP] +=3D size; @@ -444,7 +429,7 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) /* Read memory */ size =3D sizeof(uint16_t) * 6 * width; s->regs[SONIC_TTDA] =3D s->regs[SONIC_CTDA]; - DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s)); + trace_dp8393x_transmit_packet(dp8393x_ttda(s)); address_space_read(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * wi= dth, MEMTXATTRS_UNSPECIFIED, s->data, size); tx_len =3D 0; @@ -499,7 +484,7 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) /* Remove existing FCS */ tx_len -=3D 4; if (tx_len < 0) { - SONIC_ERROR("tx_len is %d\n", tx_len); + trace_dp8393x_transmit_txlen_error(tx_len); break; } } @@ -618,7 +603,7 @@ static uint64_t dp8393x_read(void *opaque, hwaddr addr,= unsigned int size) val =3D s->regs[reg]; } =20 - DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]); + trace_dp8393x_read(reg, reg_names[reg], val, size); =20 return s->big_endian ? val << 16 : val; } @@ -630,7 +615,7 @@ static void dp8393x_write(void *opaque, hwaddr addr, ui= nt64_t data, int reg =3D addr >> s->it_shift; uint32_t val =3D s->big_endian ? data >> 16 : data; =20 - DPRINTF("write 0x%04x to reg %s\n", (uint16_t)val, reg_names[reg]); + trace_dp8393x_write(reg, reg_names[reg], val, size); =20 switch (reg) { /* Command register */ @@ -643,21 +628,21 @@ static void dp8393x_write(void *opaque, hwaddr addr, = uint64_t data, case SONIC_CAP0: case SONIC_SR: case SONIC_MDT: - DPRINTF("writing to reg %d invalid\n", reg); + trace_dp8393x_write_invalid(reg); break; /* Accept write to some registers only when in reset mode */ case SONIC_DCR: if (s->regs[SONIC_CR] & SONIC_CR_RST) { s->regs[reg] =3D val & 0xbfff; } else { - DPRINTF("writing to DCR invalid\n"); + trace_dp8393x_write_invalid_dcr("DCR"); } break; case SONIC_DCR2: if (s->regs[SONIC_CR] & SONIC_CR_RST) { s->regs[reg] =3D val & 0xf017; } else { - DPRINTF("writing to DCR2 invalid\n"); + trace_dp8393x_write_invalid_dcr("DCR2"); } break; /* 12 lower bytes are Read Only */ @@ -803,7 +788,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, cons= t uint8_t * buf, } =20 if (padded_len > dp8393x_rbwc(s) * 2) { - DPRINTF("oversize packet, pkt_size is %d\n", pkt_size); + trace_dp8393x_receive_oversize(pkt_size); s->regs[SONIC_ISR] |=3D SONIC_ISR_RBAE; dp8393x_update_irq(s); s->regs[SONIC_RCR] |=3D SONIC_RCR_LPKT; @@ -812,7 +797,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, cons= t uint8_t * buf, =20 packet_type =3D dp8393x_receive_filter(s, buf, pkt_size); if (packet_type < 0) { - DPRINTF("packet not for netcard\n"); + trace_dp8393x_receive_not_netcard(); return -1; } =20 @@ -850,7 +835,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, cons= t uint8_t * buf, checksum =3D cpu_to_le32(crc32(0, buf, pkt_size)); =20 /* Put packet into RBA */ - DPRINTF("Receive packet at %08x\n", dp8393x_crba(s)); + trace_dp8393x_receive_packet(dp8393x_crba(s)); address =3D dp8393x_crba(s); address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, buf, pkt_size); @@ -888,7 +873,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, cons= t uint8_t * buf, } =20 /* Write status to memory */ - DPRINTF("Write status at %08x\n", dp8393x_crda(s)); + trace_dp8393x_receive_write_status(dp8393x_crda(s)); dp8393x_put(s, width, 0, s->regs[SONIC_RCR]); /* status */ dp8393x_put(s, width, 1, rx_len); /* byte count */ dp8393x_put(s, width, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */ diff --git a/hw/net/trace-events b/hw/net/trace-events index c28b91ee1a..643338f610 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -436,3 +436,20 @@ npcm7xx_emc_received_packet(uint32_t len) "Received %u= byte packet" npcm7xx_emc_rx_done(uint32_t crxdsa) "RX done, CRXDSA=3D0x%x" npcm7xx_emc_reg_read(int emc_num, uint32_t result, const char *name, int r= egno) "emc%d: 0x%x =3D reg[%s/%d]" npcm7xx_emc_reg_write(int emc_num, const char *name, int regno, uint32_t v= alue) "emc%d: reg[%s/%d] =3D 0x%x" + +# dp8398x.c +dp8393x_raise_irq(int isr) "raise irq, isr is 0x%04x" +dp8393x_lower_irq(void) "lower irq" +dp8393x_load_cam(int idx, int cam0, int cam1, int cam2, int cam3, int cam4= , int cam5) "load cam[%d] with 0x%02x0x%02x0x%02x0x%02x0x%02x0x%02x" +dp8393x_load_cam_done(int cen) "load cam done. cam enable mask 0x%04x" +dp8393x_read_rra_regs(int crba0, int crba1, int rbwc0, int rbwc1) "CRBA0/1= : 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x" +dp8393x_transmit_packet(int ttda) "Transmit packet at 0x%"PRIx32 +dp8393x_transmit_txlen_error(int len) "tx_len is %d" +dp8393x_read(int reg, const char *name, int val, int size) "reg=3D0x%x [%s= ] val=3D0x%04x size=3D%d" +dp8393x_write(int reg, const char *name, int val, int size) "reg=3D0x%x [%= s] val=3D0x%04x size=3D%d" +dp8393x_write_invalid(int reg) "writing to reg %d invalid" +dp8393x_write_invalid_dcr(const char *name) "writing to %s invalid" +dp8393x_receive_oversize(int size) "oversize packet, pkt_size is %d" +dp8393x_receive_not_netcard(void) "packet not for netcard" +dp8393x_receive_packet(int crba) "Receive packet at 0x%"PRIx32 +dp8393x_receive_write_status(int crba) "Write status at 0x%"PRIx32 --=20 2.20.1 From nobody Fri May 17 03:54:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624604167412943.1042364147569; Thu, 24 Jun 2021 23:56:07 -0700 (PDT) Received: from localhost ([::1]:49276 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lwfl0-0008Lp-7I for importer@patchew.org; Fri, 25 Jun 2021 02:56:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55786) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjK-0005mW-5E for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:22 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:58702 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjF-0001qQ-AY for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:21 -0400 Received: from host109-153-84-9.range109-153.btcentralplus.com ([109.153.84.9] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lwfj1-0006FO-2B; Fri, 25 Jun 2021 07:54:03 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, hpoussin@reactos.org, aleksandar.rikalo@syrmia.com, f4bug@amsat.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, jasowang@redhat.com, fthain@telegraphics.com.au, laurent@vivier.eu Date: Fri, 25 Jun 2021 07:53:54 +0100 Message-Id: <20210625065401.30170-4-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> References: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 109.153.84.9 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 03/10] hw/mips/jazz: move PROM and checksum calculation from dp8393x device to board X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This is in preparation for each board to have its own separate bit storage format and checksum for storing the MAC address. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Finn Thain --- hw/mips/jazz.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index 1e1cf8154e..89ca8bb910 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -119,6 +119,8 @@ static const MemoryRegionOps dma_dummy_ops =3D { #define MAGNUM_BIOS_SIZE = \ (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_M= AX) =20 +#define SONIC_PROM_SIZE 0x1000 + static void mips_jazz_init(MachineState *machine, enum jazz_model_e jazz_model) { @@ -137,6 +139,7 @@ static void mips_jazz_init(MachineState *machine, MemoryRegion *rtc =3D g_new(MemoryRegion, 1); MemoryRegion *i8042 =3D g_new(MemoryRegion, 1); MemoryRegion *dma_dummy =3D g_new(MemoryRegion, 1); + MemoryRegion *dp8393x_prom =3D g_new(MemoryRegion, 1); NICInfo *nd; DeviceState *dev, *rc4030; SysBusDevice *sysbus; @@ -228,6 +231,10 @@ static void mips_jazz_init(MachineState *machine, NULL, "dummy_dma", 0x1000); memory_region_add_subregion(address_space, 0x8000d000, dma_dummy); =20 + memory_region_init_rom(dp8393x_prom, NULL, "dp8393x-jazz.prom", + SONIC_PROM_SIZE, &error_fatal); + memory_region_add_subregion(address_space, 0x8000b000, dp8393x_prom); + /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */ memory_region_init(isa_io, NULL, "isa-io", 0x00010000); memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000); @@ -275,6 +282,9 @@ static void mips_jazz_init(MachineState *machine, nd->model =3D g_strdup("dp83932"); } if (strcmp(nd->model, "dp83932") =3D=3D 0) { + int checksum, i; + uint8_t *prom; + qemu_check_nic_model(nd, "dp83932"); =20 dev =3D qdev_new("dp8393x"); @@ -285,8 +295,19 @@ static void mips_jazz_init(MachineState *machine, sysbus =3D SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(sysbus, &error_fatal); sysbus_mmio_map(sysbus, 0, 0x80001000); - sysbus_mmio_map(sysbus, 1, 0x8000b000); sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4)); + + /* Add MAC address with valid checksum to PROM */ + prom =3D memory_region_get_ram_ptr(dp8393x_prom); + checksum =3D 0; + for (i =3D 0; i < 6; i++) { + prom[i] =3D nd->macaddr.a[i]; + checksum +=3D prom[i]; + if (checksum > 0xff) { + checksum =3D (checksum + 1) & 0xff; + } + } + prom[7] =3D 0xff - checksum; break; } else if (is_help_option(nd->model)) { error_report("Supported NICs: dp83932"); --=20 2.20.1 From nobody Fri May 17 03:54:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624604309109798.1455150445695; Thu, 24 Jun 2021 23:58:29 -0700 (PDT) Received: from localhost ([::1]:56504 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lwfnG-0004qJ-2o for importer@patchew.org; Fri, 25 Jun 2021 02:58:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55812) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjM-0005ov-LT for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:24 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:58712 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjG-0001r2-Uj for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:24 -0400 Received: from host109-153-84-9.range109-153.btcentralplus.com ([109.153.84.9] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lwfj1-0006FO-KD; Fri, 25 Jun 2021 07:54:03 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, hpoussin@reactos.org, aleksandar.rikalo@syrmia.com, f4bug@amsat.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, jasowang@redhat.com, fthain@telegraphics.com.au, laurent@vivier.eu Date: Fri, 25 Jun 2021 07:53:55 +0100 Message-Id: <20210625065401.30170-5-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> References: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 109.153.84.9 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 04/10] hw/m68k/q800: move PROM and checksum calculation from dp8393x device to board X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This is in preparation for each board to have its own separate bit storage format and checksum for storing the MAC address. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Finn Thain --- hw/m68k/q800.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index 11376daa85..491f283a17 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -70,6 +70,8 @@ #define NUBUS_SUPER_SLOT_BASE 0x60000000 #define NUBUS_SLOT_BASE 0xf0000000 =20 +#define SONIC_PROM_SIZE 0x1000 + /* * the video base, whereas it a Nubus address, * is needed by the kernel to have early display and @@ -211,8 +213,10 @@ static void q800_init(MachineState *machine) int32_t initrd_size; MemoryRegion *rom; MemoryRegion *io; + MemoryRegion *dp8393x_prom =3D g_new(MemoryRegion, 1); + uint8_t *prom; const int io_slice_nb =3D (IO_SIZE / IO_SLICE) - 1; - int i; + int i, checksum; ram_addr_t ram_size =3D machine->ram_size; const char *kernel_filename =3D machine->kernel_filename; const char *initrd_filename =3D machine->initrd_filename; @@ -319,9 +323,25 @@ static void q800_init(MachineState *machine) sysbus =3D SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(sysbus, &error_fatal); sysbus_mmio_map(sysbus, 0, SONIC_BASE); - sysbus_mmio_map(sysbus, 1, SONIC_PROM_BASE); sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, 2)); =20 + memory_region_init_rom(dp8393x_prom, NULL, "dp8393x-q800.prom", + SONIC_PROM_SIZE, &error_fatal); + memory_region_add_subregion(get_system_memory(), SONIC_PROM_BASE, + dp8393x_prom); + + /* Add MAC address with valid checksum to PROM */ + prom =3D memory_region_get_ram_ptr(dp8393x_prom); + checksum =3D 0; + for (i =3D 0; i < 6; i++) { + prom[i] =3D nd_table[0].macaddr.a[i]; + checksum +=3D prom[i]; + if (checksum > 0xff) { + checksum =3D (checksum + 1) & 0xff; + } + } + prom[7] =3D 0xff - checksum; + /* SCC */ =20 dev =3D qdev_new(TYPE_ESCC); --=20 2.20.1 From nobody Fri May 17 03:54:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624604319233227.59638881105354; Thu, 24 Jun 2021 23:58:39 -0700 (PDT) Received: from localhost ([::1]:57112 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lwfnS-0005FX-4E for importer@patchew.org; Fri, 25 Jun 2021 02:58:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55814) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjM-0005p9-Nu for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:24 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:58718 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjG-0001rj-Uu for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:24 -0400 Received: from host109-153-84-9.range109-153.btcentralplus.com ([109.153.84.9] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lwfj2-0006FO-5i; Fri, 25 Jun 2021 07:54:04 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, hpoussin@reactos.org, aleksandar.rikalo@syrmia.com, f4bug@amsat.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, jasowang@redhat.com, fthain@telegraphics.com.au, laurent@vivier.eu Date: Fri, 25 Jun 2021 07:53:56 +0100 Message-Id: <20210625065401.30170-6-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> References: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 109.153.84.9 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 05/10] dp8393x: remove onboard PROM containing MAC address and checksum X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" According to the datasheet the dp8393x chipset does not contain any NVRAM c= apable of storing a MAC address or checksum. Now that both the MIPS jazz and m68k = q800 boards generate the PROM region and checksum themselves, remove the generat= ed PROM from the dp8393x device itself. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Finn Thain --- hw/net/dp8393x.c | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index ea5b22f680..252c0a2664 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -30,8 +30,6 @@ #include "qom/object.h" #include "trace.h" =20 -#define SONIC_PROM_SIZE 0x1000 - static const char *reg_names[] =3D { "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA", "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0", @@ -157,7 +155,6 @@ struct dp8393xState { NICConf conf; NICState *nic; MemoryRegion mmio; - MemoryRegion prom; =20 /* Registers */ uint8_t cam[16][6]; @@ -966,16 +963,12 @@ static void dp8393x_instance_init(Object *obj) dp8393xState *s =3D DP8393X(obj); =20 sysbus_init_mmio(sbd, &s->mmio); - sysbus_init_mmio(sbd, &s->prom); sysbus_init_irq(sbd, &s->irq); } =20 static void dp8393x_realize(DeviceState *dev, Error **errp) { dp8393xState *s =3D DP8393X(dev); - int i, checksum; - uint8_t *prom; - Error *local_err =3D NULL; =20 address_space_init(&s->as, s->dma_mr, "dp8393x"); memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s, @@ -986,23 +979,6 @@ static void dp8393x_realize(DeviceState *dev, Error **= errp) qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); =20 s->watchdog =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s); - - memory_region_init_rom(&s->prom, OBJECT(dev), "dp8393x-prom", - SONIC_PROM_SIZE, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - prom =3D memory_region_get_ram_ptr(&s->prom); - checksum =3D 0; - for (i =3D 0; i < 6; i++) { - prom[i] =3D s->conf.macaddr.a[i]; - checksum +=3D prom[i]; - if (checksum > 0xff) { - checksum =3D (checksum + 1) & 0xff; - } - } - prom[7] =3D 0xff - checksum; } =20 static const VMStateDescription vmstate_dp8393x =3D { --=20 2.20.1 From nobody Fri May 17 03:54:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624604170196197.976490832149; Thu, 24 Jun 2021 23:56:10 -0700 (PDT) Received: from localhost ([::1]:49532 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lwfl3-0008W9-4h for importer@patchew.org; Fri, 25 Jun 2021 02:56:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55836) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjO-0005r6-DM for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:26 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:58724 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjG-0001s5-VV for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:26 -0400 Received: from host109-153-84-9.range109-153.btcentralplus.com ([109.153.84.9] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lwfj2-0006FO-OZ; Fri, 25 Jun 2021 07:54:04 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, hpoussin@reactos.org, aleksandar.rikalo@syrmia.com, f4bug@amsat.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, jasowang@redhat.com, fthain@telegraphics.com.au, laurent@vivier.eu Date: Fri, 25 Jun 2021 07:53:57 +0100 Message-Id: <20210625065401.30170-7-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> References: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 109.153.84.9 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 06/10] qemu/bitops.h: add bitrev8 implementation X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This will be required for an upcoming checksum calculation. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Finn Thain --- include/qemu/bitops.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index 03213ce952..110c56e099 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -618,4 +618,26 @@ static inline uint64_t half_unshuffle64(uint64_t x) return x; } =20 +/** + * bitrev8: + * @x: 8-bit value to be reversed + * + * Given an input value with bits:: + * + * ABCDEFGH + * + * return the value with its bits reversed from left to right:: + * + * HGFEDCBA + * + * Returns: the bit-reversed value. + */ +static inline uint8_t bitrev8(uint8_t x) +{ + x =3D ((x >> 1) & 0x55) | ((x << 1) & 0xaa); + x =3D ((x >> 2) & 0x33) | ((x << 2) & 0xcc); + x =3D (x >> 4) | (x << 4) ; + return x; +} + #endif --=20 2.20.1 From nobody Fri May 17 03:54:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624604583629917.1494658292588; Fri, 25 Jun 2021 00:03:03 -0700 (PDT) Received: from localhost ([::1]:37676 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lwfri-0002nt-KS for importer@patchew.org; Fri, 25 Jun 2021 03:03:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55890) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjR-00060i-Tr for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:30 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:58732 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjH-0001sQ-76 for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:29 -0400 Received: from host109-153-84-9.range109-153.btcentralplus.com ([109.153.84.9] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lwfj3-0006FO-7M; Fri, 25 Jun 2021 07:54:05 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, hpoussin@reactos.org, aleksandar.rikalo@syrmia.com, f4bug@amsat.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, jasowang@redhat.com, fthain@telegraphics.com.au, laurent@vivier.eu Date: Fri, 25 Jun 2021 07:53:58 +0100 Message-Id: <20210625065401.30170-8-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> References: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 109.153.84.9 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 07/10] hw/m68k/q800: fix PROM checksum and MAC address storage X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The checksum used by MacOS to validate the PROM content is an exclusive-OR rather than a sum over the corresponding bytes. In addition the MAC address must be stored in bit-reversed format as indicated in comments in Linux's macsonic.c. With the PROM contents fixed MacOS starts to probe the device registers when AppleTalk is enabled in the Control Panel. Signed-off-by: Mark Cave-Ayland Tested-by: Finn Thain --- hw/m68k/q800.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index 491f283a17..6817c8b5d1 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -334,11 +334,8 @@ static void q800_init(MachineState *machine) prom =3D memory_region_get_ram_ptr(dp8393x_prom); checksum =3D 0; for (i =3D 0; i < 6; i++) { - prom[i] =3D nd_table[0].macaddr.a[i]; - checksum +=3D prom[i]; - if (checksum > 0xff) { - checksum =3D (checksum + 1) & 0xff; - } + prom[i] =3D bitrev8(nd_table[0].macaddr.a[i]); + checksum ^=3D prom[i]; } prom[7] =3D 0xff - checksum; =20 --=20 2.20.1 From nobody Fri May 17 03:54:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624604651796981.9690170590354; Fri, 25 Jun 2021 00:04:11 -0700 (PDT) Received: from localhost ([::1]:40508 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lwfso-0004hO-Qj for importer@patchew.org; Fri, 25 Jun 2021 03:04:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55892) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjS-00061m-Ea for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:30 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:58738 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjH-0001sU-Pu for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:30 -0400 Received: from host109-153-84-9.range109-153.btcentralplus.com ([109.153.84.9] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lwfj3-0006FO-M4; Fri, 25 Jun 2021 07:54:05 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, hpoussin@reactos.org, aleksandar.rikalo@syrmia.com, f4bug@amsat.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, jasowang@redhat.com, fthain@telegraphics.com.au, laurent@vivier.eu Date: Fri, 25 Jun 2021 07:53:59 +0100 Message-Id: <20210625065401.30170-9-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> References: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 109.153.84.9 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 08/10] dp8393x: don't force 32-bit register access X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Commit 3fe9a838ec "dp8393x: Always use 32-bit accesses" assumed that all ac= cesses to the registers were 32-bit but this is actually not the case. The access = size is determined by the CPU instruction used and not the number of physical addre= ss lines. The big_endian workaround applied to the register read/writes was actually = caused by forcing the access size to 32-bit when the guest OS was using a 16-bit a= ccess. Since the registers are 16-bit then we can simply set .impl.min_access to 2= and then the memory API will automatically do the right thing for both 16-bit a= ccesses used by Linux and 32-bit accesses used by the MacOS toolbox ROM. Signed-off-by: Mark Cave-Ayland Fixes: 3fe9a838ec ("dp8393x: Always use 32-bit accesses") Tested-by: Finn Thain --- hw/net/dp8393x.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index 252c0a2664..6789bcd3af 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -602,15 +602,14 @@ static uint64_t dp8393x_read(void *opaque, hwaddr add= r, unsigned int size) =20 trace_dp8393x_read(reg, reg_names[reg], val, size); =20 - return s->big_endian ? val << 16 : val; + return val; } =20 -static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, +static void dp8393x_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size) { dp8393xState *s =3D opaque; int reg =3D addr >> s->it_shift; - uint32_t val =3D s->big_endian ? data >> 16 : data; =20 trace_dp8393x_write(reg, reg_names[reg], val, size); =20 @@ -694,7 +693,7 @@ static void dp8393x_write(void *opaque, hwaddr addr, ui= nt64_t data, static const MemoryRegionOps dp8393x_ops =3D { .read =3D dp8393x_read, .write =3D dp8393x_write, - .impl.min_access_size =3D 4, + .impl.min_access_size =3D 2, .impl.max_access_size =3D 4, .endianness =3D DEVICE_NATIVE_ENDIAN, }; --=20 2.20.1 From nobody Fri May 17 03:54:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624604494871962.5724446691876; Fri, 25 Jun 2021 00:01:34 -0700 (PDT) Received: from localhost ([::1]:34082 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lwfqH-0000O2-DL for importer@patchew.org; Fri, 25 Jun 2021 03:01:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55864) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjP-0005uI-KV for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:27 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:58744 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjI-0001sd-7x for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:27 -0400 Received: from host109-153-84-9.range109-153.btcentralplus.com ([109.153.84.9] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lwfj4-0006FO-6A; Fri, 25 Jun 2021 07:54:06 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, hpoussin@reactos.org, aleksandar.rikalo@syrmia.com, f4bug@amsat.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, jasowang@redhat.com, fthain@telegraphics.com.au, laurent@vivier.eu Date: Fri, 25 Jun 2021 07:54:00 +0100 Message-Id: <20210625065401.30170-10-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> References: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 109.153.84.9 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 09/10] dp8393x: fix CAM descriptor entry index X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Currently when a LOAD CAM command is executed the entries are loaded into t= he CAM from memory in order which is incorrect. According to the datasheet the first entry in the CAM descriptor is the entry index which means that each descriptor may update any single entry in the CAM rather than the Nth entry. Decode the CAM entry index and use it store the descriptor in the appropria= te slot in the CAM. This fixes the issue where the MacOS toolbox loads a single CAM descriptor into the final slot in order to perform a loopback test which must succeed before the Ethernet port is enabled. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Finn Thain --- hw/net/dp8393x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index 6789bcd3af..172fd06694 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -270,7 +270,7 @@ static void dp8393x_update_irq(dp8393xState *s) static void dp8393x_do_load_cam(dp8393xState *s) { int width, size; - uint16_t index =3D 0; + uint16_t index; =20 width =3D (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; size =3D sizeof(uint16_t) * 4 * width; @@ -279,6 +279,7 @@ static void dp8393x_do_load_cam(dp8393xState *s) /* Fill current entry */ address_space_read(&s->as, dp8393x_cdp(s), MEMTXATTRS_UNSPECIFIED, s->data, size); + index =3D dp8393x_get(s, width, 0) & 0xf; s->cam[index][0] =3D dp8393x_get(s, width, 1) & 0xff; s->cam[index][1] =3D dp8393x_get(s, width, 1) >> 8; s->cam[index][2] =3D dp8393x_get(s, width, 2) & 0xff; @@ -291,7 +292,6 @@ static void dp8393x_do_load_cam(dp8393xState *s) /* Move to next entry */ s->regs[SONIC_CDC]--; s->regs[SONIC_CDP] +=3D size; - index++; } =20 /* Read CAM enable */ --=20 2.20.1 From nobody Fri May 17 03:54:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624604503971824.13313029928; Fri, 25 Jun 2021 00:01:43 -0700 (PDT) Received: from localhost ([::1]:34484 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lwfqQ-0000ea-NW for importer@patchew.org; Fri, 25 Jun 2021 03:01:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55922) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjU-0006AL-IO for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:32 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:58750 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lwfjS-0001su-RJ for qemu-devel@nongnu.org; Fri, 25 Jun 2021 02:54:32 -0400 Received: from host109-153-84-9.range109-153.btcentralplus.com ([109.153.84.9] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lwfj4-0006FO-MO; Fri, 25 Jun 2021 07:54:06 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, hpoussin@reactos.org, aleksandar.rikalo@syrmia.com, f4bug@amsat.org, aurelien@aurel32.net, jiaxun.yang@flygoat.com, jasowang@redhat.com, fthain@telegraphics.com.au, laurent@vivier.eu Date: Fri, 25 Jun 2021 07:54:01 +0100 Message-Id: <20210625065401.30170-11-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> References: <20210625065401.30170-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 109.153.84.9 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 10/10] hw/mips/jazz: specify correct endian for dp8393x device X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The MIPS magnum machines are available in both big endian (mips64) and litt= le endian (mips64el) configurations. Ensure that the dp893x big_endian property is set accordingly using logic similar to that used for the MIPS malta machines. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Finn Thain --- hw/mips/jazz.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index 89ca8bb910..ee1789183e 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -126,7 +126,7 @@ static void mips_jazz_init(MachineState *machine, { MemoryRegion *address_space =3D get_system_memory(); char *filename; - int bios_size, n; + int bios_size, n, big_endian; Clock *cpuclk; MIPSCPU *cpu; MIPSCPUClass *mcc; @@ -158,6 +158,12 @@ static void mips_jazz_init(MachineState *machine, [JAZZ_PICA61] =3D {33333333, 4}, }; =20 +#ifdef TARGET_WORDS_BIGENDIAN + big_endian =3D 1; +#else + big_endian =3D 0; +#endif + if (machine->ram_size > 256 * MiB) { error_report("RAM size more than 256Mb is not supported"); exit(EXIT_FAILURE); @@ -290,6 +296,7 @@ static void mips_jazz_init(MachineState *machine, dev =3D qdev_new("dp8393x"); qdev_set_nic_properties(dev, nd); qdev_prop_set_uint8(dev, "it_shift", 2); + qdev_prop_set_bit(dev, "big_endian", big_endian > 0); object_property_set_link(OBJECT(dev), "dma_mr", OBJECT(rc4030_dma_mr), &error_abort); sysbus =3D SYS_BUS_DEVICE(dev); --=20 2.20.1