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[83.35.24.93]) by smtp.gmail.com with ESMTPSA id o203sm4402208wmo.36.2021.06.24.13.27.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Jun 2021 13:27:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h4oE4Yl+ZmW3FxHEA+QspghoRSVsp0JhrX2znpzx03E=; b=hFfiNFm66zskVbyDI07zrdYVDlD/qyTttHVZkZYNpiieKMxpzsHvxUhvKTm3XdX81o inB5ioYY45mbrVdMhTGDfkxs1puPqGW7nl43M0mow5E3DQ6XjUJzH4XGz6B94spbaW/0 3vdS6nnrNFdk0qogxQq8JT2b1eAZtJ0BQb5JXkMTCkYYqwk2C1PLYSCNTM9M60+rWe92 uX+JvhHA+uT7Rq+FZmMzhOSCHykjwhCoD0sVByS5W7A1Td7mt5Y//To7rOw3P5P4LD+v lwMeWpD0Fs+WJJTMEZAx2ie8pVjWKssFbeHhYtfrD62DgTZKU9ogYpjo3SogZhXBJDl0 /OZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=h4oE4Yl+ZmW3FxHEA+QspghoRSVsp0JhrX2znpzx03E=; b=e8urQOeI012IIt1vg4S2wk+K3tD+2vBtSfkuFh0yckfJvhFop+XCz+L6KvOWpFl+km oVPO/d7Cb63aL8H1H0Rv8hn85p2jrY1LGtE6iDL2LMTBBIHZbbQu/UgE2xjxcX2OGS1I RBxw63TCdz/Tct604nUIAX+qxy97O0xl9YyLPcNq68Cun/ld28shRkwl7PS9jmVEGdKs TJVbBwU21jefv7BCLp6189/Z2u29MfiRHG7sOSCcSDvwF44y0lPmgFP2xJza/nD380Ve IEYNt+WwciepmDg9eG+ASUxClCDaRqHU84/s2JDePe9y8kwCX9sRIQlvcMW0FpAPW6fA ru5g== X-Gm-Message-State: AOAM531FTUN0W+Aasy/4rT48S6R6Z/LHn7VjbP2Fx4j9Oz7I/ifX+5Ya PU1vAbhuLERE8b2YX9cAHPU= X-Google-Smtp-Source: ABdhPJxH4Z0mGSZ2hOjOS6HM9Yz4r0VPW3NXPu79x7Qf38qAdeEtNEL6ndgC+uFnOhG5mnJzDsOW/w== X-Received: by 2002:a05:600c:8a7:: with SMTP id l39mr6435011wmp.147.1624566474227; Thu, 24 Jun 2021 13:27:54 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Wainer dos Santos Moschetta , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Rikalo , Aurelien Jarno , Cleber Rosa , Huacai Chen , Jiaxun Yang Subject: [PATCH 1/5] hw/isa/vt82c686: Replace magic numbers by definitions Date: Thu, 24 Jun 2021 22:27:43 +0200 Message-Id: <20210624202747.1433023-2-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210624202747.1433023-1-f4bug@amsat.org> References: <20210624202747.1433023-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Replace magic values of the Power Management / SMBus function (#4) by definitions from the datasheet. The result is less compact, and we can follow what the code does without having to recur to the datasheet. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/isa/vt82c686.c | 50 +++++++++++++++++++++++++++++++---------------- 1 file changed, 33 insertions(+), 17 deletions(-) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index f57f3e70679..4ddcf2d398c 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -14,6 +14,7 @@ */ =20 #include "qemu/osdep.h" +#include "hw/registerfields.h" #include "hw/isa/vt82c686.h" #include "hw/pci/pci.h" #include "hw/qdev-properties.h" @@ -38,6 +39,16 @@ #define TYPE_VIA_PM "via-pm" OBJECT_DECLARE_SIMPLE_TYPE(ViaPMState, VIA_PM) =20 +REG8(PM_GEN_CFG0, 0x40) +REG8(PM_GEN_CFG1, 0x41) +FIELD(PM_GEN_CFG1, ACPI_IO_ENABLE, 7, 1) +REG32(PM_IO_BASE, 0x48) +FIELD(PM_IO_BASE, ADDR, 7, 9) +REG32(SMBUS_IO_BASE, 0x90) +FIELD(SMBUS_IO_BASE, ADDR, 4, 12) +REG8(SMBUS_HOST_CONFIG, 0xd2) +FIELD(SMBUS_HOST_CONFIG, ENABLE, 0, 1) + struct ViaPMState { PCIDevice dev; MemoryRegion io; @@ -48,21 +59,24 @@ struct ViaPMState { =20 static void pm_io_space_update(ViaPMState *s) { - uint32_t pmbase =3D pci_get_long(s->dev.config + 0x48) & 0xff80UL; + uint32_t pmbase =3D pci_get_long(s->dev.config + A_PM_IO_BASE); =20 memory_region_transaction_begin(); - memory_region_set_address(&s->io, pmbase); - memory_region_set_enabled(&s->io, s->dev.config[0x41] & BIT(7)); + memory_region_set_address(&s->io, pmbase & R_PM_IO_BASE_ADDR_MASK); + memory_region_set_enabled(&s->io, FIELD_EX32(s->dev.config[A_PM_GEN_CF= G1], + PM_GEN_CFG1, ACPI_IO_ENABLE)); memory_region_transaction_commit(); } =20 static void smb_io_space_update(ViaPMState *s) { - uint32_t smbase =3D pci_get_long(s->dev.config + 0x90) & 0xfff0UL; + uint32_t smbase =3D pci_get_long(s->dev.config + A_SMBUS_IO_BASE); =20 memory_region_transaction_begin(); - memory_region_set_address(&s->smb.io, smbase); - memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & BIT(0)); + memory_region_set_address(&s->smb.io, smbase & R_SMBUS_IO_BASE_ADDR_MA= SK); + memory_region_set_enabled(&s->smb.io, + FIELD_EX32(s->dev.config[A_SMBUS_HOST_CONFIG= ], + SMBUS_HOST_CONFIG, ENABLE)); memory_region_transaction_commit(); } =20 @@ -98,19 +112,21 @@ static void pm_write_config(PCIDevice *d, uint32_t add= r, uint32_t val, int len) =20 trace_via_pm_write(addr, val, len); pci_default_write_config(d, addr, val, len); - if (ranges_overlap(addr, len, 0x48, 4)) { - uint32_t v =3D pci_get_long(s->dev.config + 0x48); - pci_set_long(s->dev.config + 0x48, (v & 0xff80UL) | 1); + if (ranges_overlap(addr, len, A_PM_IO_BASE, 4)) { + uint32_t v =3D pci_get_long(s->dev.config + A_PM_IO_BASE); + pci_set_long(s->dev.config + A_PM_IO_BASE, + (v & R_PM_IO_BASE_ADDR_MASK) | 1); } - if (range_covers_byte(addr, len, 0x41)) { + if (range_covers_byte(addr, len, A_PM_GEN_CFG1)) { pm_io_space_update(s); } - if (ranges_overlap(addr, len, 0x90, 4)) { - uint32_t v =3D pci_get_long(s->dev.config + 0x90); - pci_set_long(s->dev.config + 0x90, (v & 0xfff0UL) | 1); + if (ranges_overlap(addr, len, A_SMBUS_IO_BASE, 4)) { + uint32_t v =3D pci_get_long(s->dev.config + A_SMBUS_IO_BASE); + pci_set_long(s->dev.config + A_SMBUS_IO_BASE, + (v & R_SMBUS_IO_BASE_ADDR_MASK) | 1); } - if (range_covers_byte(addr, len, 0xd2)) { - s->dev.config[0xd2] &=3D 0xf; + if (range_covers_byte(addr, len, A_SMBUS_HOST_CONFIG)) { + s->dev.config[A_SMBUS_HOST_CONFIG] &=3D 0xf; smb_io_space_update(s); } } @@ -176,9 +192,9 @@ static void via_pm_reset(DeviceState *d) memset(s->dev.config + PCI_CONFIG_HEADER_SIZE, 0, PCI_CONFIG_SPACE_SIZE - PCI_CONFIG_HEADER_SIZE); /* Power Management IO base */ - pci_set_long(s->dev.config + 0x48, 1); + pci_set_long(s->dev.config + A_PM_IO_BASE, 1); /* SMBus IO base */ - pci_set_long(s->dev.config + 0x90, 1); + pci_set_long(s->dev.config + A_SMBUS_IO_BASE, 1); =20 acpi_pm1_evt_reset(&s->ar); acpi_pm1_cnt_reset(&s->ar); --=20 2.31.1