From nobody Sat May 18 12:12:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624371103179892.5083135203652; Tue, 22 Jun 2021 07:11:43 -0700 (PDT) Received: from localhost ([::1]:46568 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvh7u-0004eF-4g for importer@patchew.org; Tue, 22 Jun 2021 10:11:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35266) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvh5u-0002eq-5K for qemu-devel@nongnu.org; Tue, 22 Jun 2021 10:09:38 -0400 Received: from us-smtp-delivery-44.mimecast.com ([207.211.30.44]:46854) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvh5r-0000hX-UJ for qemu-devel@nongnu.org; Tue, 22 Jun 2021 10:09:37 -0400 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-597-JYWdPGjVPl-Bq3LeFZ-rCw-1; Tue, 22 Jun 2021 10:09:31 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id A1159362F8; Tue, 22 Jun 2021 14:09:29 +0000 (UTC) Received: from bahia.redhat.com (ovpn-113-182.ams2.redhat.com [10.36.113.182]) by smtp.corp.redhat.com (Postfix) with ESMTP id A66E15C1CF; Tue, 22 Jun 2021 14:09:28 +0000 (UTC) X-MC-Unique: JYWdPGjVPl-Bq3LeFZ-rCw-1 From: Greg Kurz To: qemu-devel@nongnu.org Subject: [PATCH 1/2] target/ppc: Introduce ppc_interrupts_little_endian() Date: Tue, 22 Jun 2021 16:09:25 +0200 Message-Id: <20210622140926.677618-2-groug@kaod.org> In-Reply-To: <20210622140926.677618-1-groug@kaod.org> References: <20210622140926.677618-1-groug@kaod.org> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: kaod.org Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=207.211.30.44; envelope-from=groug@kaod.org; helo=us-smtp-delivery-44.mimecast.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Greg Kurz , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" PowerPC CPUs use big endian by default but starting with POWER7, server grade CPUs use the ILE bit of the LPCR special purpose register to decide on the endianness to use when handling interrupts. This gives a clue to QEMU on the endianness the guest kernel is running, which is needed when generating an ELF dump of the guest or when delivering an FWNMI machine check interrupt. Commit 382d2db62bcb ("target-ppc: Introduce callback for interrupt endianness") added a class method to PowerPCCPUClass to modelize this : default implementation returns a fixed "big endian" value, while POWER7 and newer do the LPCR_ILE check. This is suboptimal as it forces to implement the method for every new CPU family, and it is very unlikely that this will ever be different than what we have today. We basically only have three cases to consider: a) CPU doesn't have an LPCR =3D> big endian b) CPU has an LPCR but doesn't support the ILE bit =3D> big endian c) CPU has an LPCR and supports the ILE bit =3D> little or big endian Instead of class methods, introduce an inline helper that checks the ILE bit in the LPCR_MASK to decide on the outcome. The new helper words little endian instead of big endian. This allows to drop a ! operator in ppc_cpu_do_fwnmi_machine_check(). Signed-off-by: Greg Kurz Reviewed-by: Fabiano Rosas --- target/ppc/cpu.h | 15 +++++++++++++++ target/ppc/arch_dump.c | 8 +++----- target/ppc/excp_helper.c | 3 +-- 3 files changed, 19 insertions(+), 7 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index b4de0db7ff5c..93d308ac8f2d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2643,6 +2643,21 @@ static inline bool ppc_has_spr(PowerPCCPU *cpu, int = spr) return cpu->env.spr_cb[spr].name !=3D NULL; } =20 +static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu) +{ + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); + + /* + * Only models that have an LPCR and know about LPCR_ILE can do little + * endian. + */ + if (pcc->lpcr_mask & LPCR_ILE) { + return !!(cpu->env.spr[SPR_LPCR] & LPCR_ILE); + } + + return false; +} + void dump_mmu(CPUPPCState *env); =20 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len); diff --git a/target/ppc/arch_dump.c b/target/ppc/arch_dump.c index 9210e61ef463..bb392f6d8885 100644 --- a/target/ppc/arch_dump.c +++ b/target/ppc/arch_dump.c @@ -227,22 +227,20 @@ int cpu_get_dump_info(ArchDumpInfo *info, const struct GuestPhysBlockList *guest_phys_blocks) { PowerPCCPU *cpu; - PowerPCCPUClass *pcc; =20 if (first_cpu =3D=3D NULL) { return -1; } =20 cpu =3D POWERPC_CPU(first_cpu); - pcc =3D POWERPC_CPU_GET_CLASS(cpu); =20 info->d_machine =3D PPC_ELF_MACHINE; info->d_class =3D ELFCLASS; =20 - if ((*pcc->interrupts_big_endian)(cpu)) { - info->d_endian =3D ELFDATA2MSB; - } else { + if (ppc_interrupts_little_endian(cpu)) { info->d_endian =3D ELFDATA2LSB; + } else { + info->d_endian =3D ELFDATA2MSB; } /* 64KB is the max page size for pseries kernel */ if (strncmp(object_get_typename(qdev_get_machine()), diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index fd147e2a3766..a79a0ed465e5 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1099,7 +1099,6 @@ void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, tar= get_ulong vector) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; - PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); target_ulong msr =3D 0; =20 /* @@ -1108,7 +1107,7 @@ void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, tar= get_ulong vector) */ msr =3D (1ULL << MSR_ME); msr |=3D env->msr & (1ULL << MSR_SF); - if (!(*pcc->interrupts_big_endian)(cpu)) { + if (ppc_interrupts_little_endian(cpu)) { msr |=3D (1ULL << MSR_LE); } =20 --=20 2.31.1 From nobody Sat May 18 12:12:30 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162437110185183.65960073173437; Tue, 22 Jun 2021 07:11:41 -0700 (PDT) Received: from localhost ([::1]:46472 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvh7s-0004aQ-Or for importer@patchew.org; Tue, 22 Jun 2021 10:11:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35220) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvh5s-0002do-Oh for qemu-devel@nongnu.org; Tue, 22 Jun 2021 10:09:36 -0400 Received: from us-smtp-delivery-44.mimecast.com ([207.211.30.44]:54812) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvh5r-0000h5-6D for qemu-devel@nongnu.org; Tue, 22 Jun 2021 10:09:36 -0400 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-131-VDwtQMmKME66JFPSCvzugQ-1; Tue, 22 Jun 2021 10:09:32 -0400 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id F391B1084F53; Tue, 22 Jun 2021 14:09:30 +0000 (UTC) Received: from bahia.redhat.com (ovpn-113-182.ams2.redhat.com [10.36.113.182]) by smtp.corp.redhat.com (Postfix) with ESMTP id EAE855C1A3; Tue, 22 Jun 2021 14:09:29 +0000 (UTC) X-MC-Unique: VDwtQMmKME66JFPSCvzugQ-1 From: Greg Kurz To: qemu-devel@nongnu.org Subject: [PATCH 2/2] target/ppc: Drop PowerPCCPUClass::interrupts_big_endian() Date: Tue, 22 Jun 2021 16:09:26 +0200 Message-Id: <20210622140926.677618-3-groug@kaod.org> In-Reply-To: <20210622140926.677618-1-groug@kaod.org> References: <20210622140926.677618-1-groug@kaod.org> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=groug@kaod.org X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: kaod.org Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=207.211.30.44; envelope-from=groug@kaod.org; helo=us-smtp-delivery-44.mimecast.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Greg Kurz , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" This isn't used anymore. Signed-off-by: Greg Kurz Reviewed-by: Fabiano Rosas --- target/ppc/cpu-qom.h | 1 - target/ppc/cpu_init.c | 17 ----------------- 2 files changed, 18 deletions(-) diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 06b6571bc9d5..7b424e3cb0bc 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -199,7 +199,6 @@ struct PowerPCCPUClass { void (*init_proc)(CPUPPCState *env); int (*check_pow)(CPUPPCState *env); int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu= _idx); - bool (*interrupts_big_endian)(PowerPCCPU *cpu); }; =20 #ifndef CONFIG_USER_ONLY diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index d0411e7302a2..1a22aef874b1 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2666,18 +2666,6 @@ static int check_pow_hid0_74xx(CPUPPCState *env) return 0; } =20 -static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu) -{ - return true; -} - -#ifdef TARGET_PPC64 -static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu) -{ - return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE); -} -#endif - /*************************************************************************= ****/ /* PowerPC implementations definitions = */ =20 @@ -7740,7 +7728,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) POWERPC_FLAG_VSX; pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; - pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; } =20 static void init_proc_POWER8(CPUPPCState *env) @@ -7918,7 +7905,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) POWERPC_FLAG_VSX | POWERPC_FLAG_TM; pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; - pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; } =20 #ifdef CONFIG_SOFTMMU @@ -8136,7 +8122,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; - pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; } =20 #ifdef CONFIG_SOFTMMU @@ -8347,7 +8332,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; pcc->l1_dcache_size =3D 0x8000; pcc->l1_icache_size =3D 0x8000; - pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_lpcr; } =20 #if !defined(CONFIG_USER_ONLY) @@ -9094,7 +9078,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void = *data) device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, &pcc->parent_unrealize); pcc->pvr_match =3D ppc_pvr_match_default; - pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_always; device_class_set_props(dc, ppc_cpu_properties); =20 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); --=20 2.31.1