From nobody Sat May 18 13:36:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624354752279848.7738478430242; Tue, 22 Jun 2021 02:39:12 -0700 (PDT) Received: from localhost ([::1]:59956 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvcsB-0004b3-1Q for importer@patchew.org; Tue, 22 Jun 2021 05:39:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35924) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvcnn-00037t-LM; Tue, 22 Jun 2021 05:34:39 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:2149) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvcnh-00032h-9y; Tue, 22 Jun 2021 05:34:39 -0400 Received: from dggemv704-chm.china.huawei.com (unknown [172.30.72.54]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4G8Lk40d8Gz72mq; Tue, 22 Jun 2021 17:31:08 +0800 (CST) Received: from dggpemm500023.china.huawei.com (7.185.36.83) by dggemv704-chm.china.huawei.com (10.3.19.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 22 Jun 2021 17:34:22 +0800 Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 22 Jun 2021 17:34:21 +0800 From: Yanan Wang To: Peter Maydell , Andrew Jones , Paolo Bonzini , "Michael S . Tsirkin" , Igor Mammedov , Shannon Zhao , Alistair Francis , David Gibson , , Subject: [RFC PATCH v4 1/7] vl: Add expose=on|off option support in -smp command line Date: Tue, 22 Jun 2021 17:34:07 +0800 Message-ID: <20210622093413.13360-2-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20210622093413.13360-1-wangyanan55@huawei.com> References: <20210622093413.13360-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.188; envelope-from=wangyanan55@huawei.com; helo=szxga02-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Barry Song , Yanan Wang , prime.zeng@hisilicon.com, wanghaibin.wang@huawei.com, yuzenghui@huawei.com, yangyicong@huawei.com, zhukeqian1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Once the view of virtual cpu topology is provided to guest kernel, with a well-designed vCPU pinning to the pCPU we could get a huge benefit, e.g., the scheduling performance improvement. However a virtual cpu topology view of guest may also have a negative impact if the pinning is badly-designed. See Dario Faggioli's research and the related performance tests in [1] for reference. [1] https://kvmforum2020.sched.com/event/eE1y/virtual-topology- for-virtual-machines-friend-or-foe-dario-faggioli-suse So here we go, let's introduce support of generating cpu topology descriptions to the guest. However, instead of quietly enforcing the support for the latest machine type, we'd better introduce a new parameter "expose=3Don|off" in -smp command line to leave QEMU users a choice to decide whether to enable the feature or not. This will allow the feature to work on different machine types and also ideally compat with already in-use -smp command lines. Furthermore, based on existing parsing rules of -smp command line in generic smp_parse() which allows to compute the missing values, another more strict rule is introduced to follow when exposure of cpu topology is enabled. With "expose=3Don", it's important to know what users actually want, so we require that all of cpus/sockets/ cores/threads must be provided while maxcpus is optional. Hopefully the new rule will apply to all kinds of architectures which support the feature. In conclusion, if a QEMU user doesn't hope to enable the virtual cpu topology support, then feel free to configure a -smp cmdline like below and everything will work just like before: -smp 96 -smp 96,expose=3Doff -smp 96,sockets=3D2 -smp 96,sockets=3D2,expose=3Doff ... While if a QEMU user is ready to take advantage of the virtual cpu topology support, then he must configure an accurate -smp cmdline like below, on different machine types: -smp 96,sockets=3D2,cores=3D48,threads=3D1,expose=3Don -smp 96,maxcpus=3D96,sockets=3D2,cores=3D48,threads=3D1,expose=3Don Suggested-by: Andrew Jones Signed-off-by: Yanan Wang --- qemu-options.hx | 24 +++++++++++++++--------- softmmu/vl.c | 3 +++ 2 files changed, 18 insertions(+), 9 deletions(-) diff --git a/qemu-options.hx b/qemu-options.hx index 14258784b3..d18d64958b 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -196,25 +196,31 @@ SRST ERST =20 DEF("smp", HAS_ARG, QEMU_OPTION_smp, - "-smp [cpus=3D]n[,maxcpus=3Dcpus][,cores=3Dcores][,threads=3Dthreads][= ,dies=3Ddies][,sockets=3Dsockets]\n" + "-smp [cpus=3D]n[,maxcpus=3Dcpus][,cores=3Dcores][,threads=3Dthreads][= ,dies=3Ddies][,sockets=3Dsockets][,expose=3Don|off]\n" " set the number of CPUs to 'n' [default=3D1]\n" " maxcpus=3D maximum number of total cpus, including\n" " offline CPUs for hotplug, etc\n" " cores=3D number of CPU cores on one socket (for PC, i= t's on one die)\n" " threads=3D number of threads on one CPU core\n" " dies=3D number of CPU dies on one socket (for PC only= )\n" - " sockets=3D number of discrete sockets in the system\n= ", + " sockets=3D number of discrete sockets in the system\n" + " expose=3Don|off controls support for exposing cpu top= ology\n" + " to the guest (default=3Doff)\n", QEMU_ARCH_ALL) SRST -``-smp [cpus=3D]n[,cores=3Dcores][,threads=3Dthreads][,dies=3Ddies][,socke= ts=3Dsockets][,maxcpus=3Dmaxcpus]`` +``-smp [cpus=3D]n[,cores=3Dcores][,threads=3Dthreads][,dies=3Ddies][,socke= ts=3Dsockets][,maxcpus=3Dmaxcpus][,expose=3Don|off]`` Simulate an SMP system with n CPUs. On the PC target, up to 255 CPUs - are supported. On Sparc32 target, Linux limits the number of usable - CPUs to 4. For the PC target, the number of cores per die, the - number of threads per cores, the number of dies per packages and the - total number of sockets can be specified. Missing values will be - computed. If any on the three values is given, the total number of - CPUs n can be omitted. maxcpus specifies the maximum number of + are supported. On the Sparc32 target, Linux limits the number of usable + CPUs to 4. For the PC target, the number of cores per die, the number + of threads per core, the number of dies per package and the total numb= er + of sockets can be specified. maxcpus specifies the maximum number of hotpluggable CPUs. + + With "expose=3Doff" or not explicitly specified, missing values will be + computed, and the total number of CPUs n can be omitted if any on the + three values is given. Otherwise with "expose=3Don", much more detailed + configuration is required: cpus/sockets/cores/threads must be given, + while maxcpus is optional. ERST =20 DEF("numa", HAS_ARG, QEMU_OPTION_numa, diff --git a/softmmu/vl.c b/softmmu/vl.c index feb4d201f3..f4b59571c7 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -729,6 +729,9 @@ static QemuOptsList qemu_smp_opts =3D { }, { .name =3D "maxcpus", .type =3D QEMU_OPT_NUMBER, + }, { + .name =3D "expose", + .type =3D QEMU_OPT_BOOL, }, { /*End of list */ } }, --=20 2.23.0 From nobody Sat May 18 13:36:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624354588097982.1551301038517; Tue, 22 Jun 2021 02:36:28 -0700 (PDT) Received: from localhost ([::1]:49182 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvcpU-0005kv-Rb for importer@patchew.org; Tue, 22 Jun 2021 05:36:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35844) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvcnj-0002vN-Tn; Tue, 22 Jun 2021 05:34:35 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:2178) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvcnh-00030F-0G; Tue, 22 Jun 2021 05:34:35 -0400 Received: from dggemv703-chm.china.huawei.com (unknown [172.30.72.53]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4G8Lj649lQz71H2; Tue, 22 Jun 2021 17:30:18 +0800 (CST) Received: from dggpemm500023.china.huawei.com (7.185.36.83) by dggemv703-chm.china.huawei.com (10.3.19.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 22 Jun 2021 17:34:24 +0800 Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 22 Jun 2021 17:34:23 +0800 From: Yanan Wang To: Peter Maydell , Andrew Jones , Paolo Bonzini , "Michael S . Tsirkin" , Igor Mammedov , Shannon Zhao , Alistair Francis , David Gibson , , Subject: [RFC PATCH v4 2/7] hw/arm/virt: Add separate -smp parsing function for ARM machines Date: Tue, 22 Jun 2021 17:34:08 +0800 Message-ID: <20210622093413.13360-3-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20210622093413.13360-1-wangyanan55@huawei.com> References: <20210622093413.13360-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.189; envelope-from=wangyanan55@huawei.com; helo=szxga03-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Barry Song , Yanan Wang , prime.zeng@hisilicon.com, wanghaibin.wang@huawei.com, yuzenghui@huawei.com, yangyicong@huawei.com, zhukeqian1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add an ARM-specific -smp parsing function named virt_smp_parse. When support for exposing cpu topology to the guest is disabled, this function shares the same logic with smp_parse(). While when the support is enabled, an accurate virtual cpu topology is very important, so we require that cpus/sockets/cores/threads must be given, while maxcpus is optional. Given that ARM cpu hotplug is not supported yet, a configuration with "maxcpus > cpus" is meaningless, so if exposure is turned on we also explicitly enforce that maxcpus must be equal to smp cpus if specified, until cpu hotplug is available. Given that the virtual cpu topology exposure support may come to different architectures in the future, a new structure member "bool expose_cpu_topology" is also added to MachineState to record whether the feature is supported & enabled. Suggested-by: Andrew Jones Signed-off-by: Yanan Wang --- hw/arm/virt.c | 113 ++++++++++++++++++++++++++++++++++++++++++++ include/hw/boards.h | 1 + 2 files changed, 114 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 4b96f06014..f29d796f3f 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -77,6 +77,8 @@ #include "hw/virtio/virtio-iommu.h" #include "hw/char/pl011.h" #include "qemu/guest-random.h" +#include "qapi/qmp/qerror.h" +#include "sysemu/replay.h" =20 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ @@ -2584,6 +2586,116 @@ static int virt_kvm_type(MachineState *ms, const ch= ar *type_str) return fixed_ipa ? 0 : requested_pa_size; } =20 +/* + * virt_smp_parse - Parses the -smp command line for ARM machines. + * + * When support for exposing cpu topology to the guest is disabled, + * this function shares the same parsing logic with smp_parse(). + * While when the exposure is enabled, an accurate virtual cpu topology + * is important, so we required that cpus/sockets/cores/threads must be + * provided, while maxcpus can be optional. + */ +static void virt_smp_parse(MachineState *ms, QemuOpts *opts) +{ + if (opts) { + unsigned cpus =3D qemu_opt_get_number(opts, "cpus", 0); + unsigned sockets =3D qemu_opt_get_number(opts, "sockets", 0); + unsigned cores =3D qemu_opt_get_number(opts, "cores", 0); + unsigned threads =3D qemu_opt_get_number(opts, "threads", 0); + unsigned maxcpus =3D qemu_opt_get_number(opts, "maxcpus", 0); + bool expose =3D qemu_opt_get_bool(opts, "expose", false); + + if (expose) { + if (cpus =3D=3D 0) { + error_report("expose=3Don: cpus must be specified"); + exit(1); + } + if (sockets =3D=3D 0) { + error_report("expose=3Don: sockets must be specified"); + exit(1); + } + if (cores =3D=3D 0) { + error_report("expose=3Don: cores must be specified"); + exit(1); + } + if (threads =3D=3D 0) { + error_report("expose=3Don: threads must be specified"); + exit(1); + } + } else { + /* + * An accurate cpu topology configuration is not required in t= his + * case, so we compute the missing values preferring sockets o= ver + * cores over threads. + */ + if (cpus =3D=3D 0 || sockets =3D=3D 0) { + cores =3D cores > 0 ? cores : 1; + threads =3D threads > 0 ? threads : 1; + if (cpus =3D=3D 0) { + sockets =3D sockets > 0 ? sockets : 1; + cpus =3D cores * threads * sockets; + } else { + maxcpus =3D maxcpus > 0 ? maxcpus : cpus; + sockets =3D maxcpus / (cores * threads); + } + } else if (cores =3D=3D 0) { + threads =3D threads > 0 ? threads : 1; + cores =3D cpus / (sockets * threads); + cores =3D cores > 0 ? cores : 1; + } else if (threads =3D=3D 0) { + threads =3D cpus / (cores * sockets); + threads =3D threads > 0 ? threads : 1; + } + } + + maxcpus =3D maxcpus > 0 ? maxcpus : cpus; + + if (sockets * cores * threads < cpus) { + error_report("cpu topology: " + "sockets (%u) * cores (%u) * threads (%u) < " + "smp_cpus (%u)", + sockets, cores, threads, cpus); + exit(1); + } + + if (maxcpus < cpus) { + error_report("maxcpus must be equal to or greater than smp"); + exit(1); + } + + if (sockets * cores * threads !=3D maxcpus) { + error_report("Invalid CPU topology: " + "sockets (%u) * cores (%u) * threads (%u) " + "!=3D maxcpus (%u)", + sockets, cores, threads, maxcpus); + exit(1); + } + + /* + * Given that cpu hotplug is not supported yet, require that maxcp= us + * must be equal to smp cpus if we are going to expose cpu topology + * to the guest. + */ + if (expose =3D=3D true && maxcpus !=3D cpus) { + error_report("cpu hotplug is not supported yet, maxcpus must b= e" + "equal to smp"); + } + + ms->smp.cpus =3D cpus; + ms->smp.sockets =3D sockets; + ms->smp.cores =3D cores; + ms->smp.threads =3D threads; + ms->smp.max_cpus =3D maxcpus; + ms->expose_cpu_topology =3D expose; + } + + if (ms->smp.cpus > 1) { + Error *blocker =3D NULL; + error_setg(&blocker, QERR_REPLAY_NOT_SUPPORTED, "smp"); + replay_add_blocker(blocker); + } +} + static void virt_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -2611,6 +2723,7 @@ static void virt_machine_class_init(ObjectClass *oc, = void *data) mc->cpu_index_to_instance_props =3D virt_cpu_index_to_props; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a15"); mc->get_default_cpu_node_id =3D virt_get_default_cpu_node_id; + mc->smp_parse =3D virt_smp_parse; mc->kvm_type =3D virt_kvm_type; assert(!mc->get_hotplug_handler); mc->get_hotplug_handler =3D virt_machine_get_hotplug_handler; diff --git a/include/hw/boards.h b/include/hw/boards.h index 3d55d2bd62..54accc810a 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -332,6 +332,7 @@ struct MachineState { AccelState *accelerator; CPUArchIdList *possible_cpus; CpuTopology smp; + bool expose_cpu_topology; struct NVDIMMState *nvdimms_state; struct NumaState *numa_state; }; --=20 2.23.0 From nobody Sat May 18 13:36:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624354801202801.3207169318983; Tue, 22 Jun 2021 02:40:01 -0700 (PDT) Received: from localhost ([::1]:34796 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvcsy-0006fg-0o for importer@patchew.org; Tue, 22 Jun 2021 05:40:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35892) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvcnl-000315-Q7; Tue, 22 Jun 2021 05:34:37 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:2148) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvcnh-00030b-U3; Tue, 22 Jun 2021 05:34:37 -0400 Received: from dggemv711-chm.china.huawei.com (unknown [172.30.72.53]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4G8Lk63sfcz72kQ; Tue, 22 Jun 2021 17:31:10 +0800 (CST) Received: from dggpemm500023.china.huawei.com (7.185.36.83) by dggemv711-chm.china.huawei.com (10.1.198.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 22 Jun 2021 17:34:25 +0800 Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 22 Jun 2021 17:34:24 +0800 From: Yanan Wang To: Peter Maydell , Andrew Jones , Paolo Bonzini , "Michael S . Tsirkin" , Igor Mammedov , Shannon Zhao , Alistair Francis , David Gibson , , Subject: [RFC PATCH v4 3/7] machine: disallow -smp expose=on for non-ARM machines Date: Tue, 22 Jun 2021 17:34:09 +0800 Message-ID: <20210622093413.13360-4-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20210622093413.13360-1-wangyanan55@huawei.com> References: <20210622093413.13360-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.188; envelope-from=wangyanan55@huawei.com; helo=szxga02-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Barry Song , Yanan Wang , prime.zeng@hisilicon.com, wanghaibin.wang@huawei.com, yuzenghui@huawei.com, yangyicong@huawei.com, zhukeqian1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, support for exposure of cpu topology to the guest is only introduced for ARM machines and we also have an ARM specific parsing function virt_smp_parse(), so we disallow the "-smp expose=3Don" configuration for the other platforms. Signed-off-by: Yanan Wang --- hw/core/machine.c | 7 +++++++ hw/i386/pc.c | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/hw/core/machine.c b/hw/core/machine.c index 55b9bc7817..23721bb77e 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -746,6 +746,13 @@ static void smp_parse(MachineState *ms, QemuOpts *opts) unsigned sockets =3D qemu_opt_get_number(opts, "sockets", 0); unsigned cores =3D qemu_opt_get_number(opts, "cores", 0); unsigned threads =3D qemu_opt_get_number(opts, "threads", 0); + bool expose =3D qemu_opt_get_bool(opts, "expose", false); + + if (expose) { + error_report("expose=3Don: exposing cpu topology to the guest" + "is not supported yet"); + exit(1); + } =20 /* compute missing values, prefer sockets over cores over threads = */ if (cpus =3D=3D 0 || sockets =3D=3D 0) { diff --git a/hw/i386/pc.c b/hw/i386/pc.c index c6d8d0d84d..afabfa0566 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -720,6 +720,13 @@ void pc_smp_parse(MachineState *ms, QemuOpts *opts) unsigned dies =3D qemu_opt_get_number(opts, "dies", 1); unsigned cores =3D qemu_opt_get_number(opts, "cores", 0); unsigned threads =3D qemu_opt_get_number(opts, "threads", 0); + bool expose =3D qemu_opt_get_bool(opts, "expose", false); + + if (expose) { + error_report("expose=3Don: exposing cpu topology to the guest" + "is not supported yet"); + exit(1); + } =20 /* compute missing values, prefer sockets over cores over threads = */ if (cpus =3D=3D 0 || sockets =3D=3D 0) { --=20 2.23.0 From nobody Sat May 18 13:36:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624354657024431.94049692294345; Tue, 22 Jun 2021 02:37:37 -0700 (PDT) Received: from localhost ([::1]:53958 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvcqd-0000bE-Vo for importer@patchew.org; Tue, 22 Jun 2021 05:37:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35890) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvcnl-00030n-M3; Tue, 22 Jun 2021 05:34:37 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:2425) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvcnh-00031B-A5; Tue, 22 Jun 2021 05:34:37 -0400 Received: from dggemv704-chm.china.huawei.com (unknown [172.30.72.53]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4G8LkQ3NMqzZgjc; Tue, 22 Jun 2021 17:31:26 +0800 (CST) Received: from dggpemm500023.china.huawei.com (7.185.36.83) by dggemv704-chm.china.huawei.com (10.3.19.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 22 Jun 2021 17:34:26 +0800 Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 22 Jun 2021 17:34:25 +0800 From: Yanan Wang To: Peter Maydell , Andrew Jones , Paolo Bonzini , "Michael S . Tsirkin" , Igor Mammedov , Shannon Zhao , Alistair Francis , David Gibson , , Subject: [RFC PATCH v4 4/7] device_tree: Add qemu_fdt_add_path Date: Tue, 22 Jun 2021 17:34:10 +0800 Message-ID: <20210622093413.13360-5-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20210622093413.13360-1-wangyanan55@huawei.com> References: <20210622093413.13360-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.187; envelope-from=wangyanan55@huawei.com; helo=szxga01-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Barry Song , Yanan Wang , prime.zeng@hisilicon.com, wanghaibin.wang@huawei.com, yuzenghui@huawei.com, yangyicong@huawei.com, zhukeqian1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" qemu_fdt_add_path() works like qemu_fdt_add_subnode(), except it also adds all missing subnodes from the given path. We'll use it in a coming patch where we will add cpu-map to the device tree. And we also tweak an error message of qemu_fdt_add_subnode(). Cc: David Gibson Cc: Alistair Francis Co-developed-by: Andrew Jones Signed-off-by: Andrew Jones Signed-off-by: Yanan Wang Reviewed-by: David Gibson Reviewed-by: Andrew Jones --- include/sysemu/device_tree.h | 1 + softmmu/device_tree.c | 44 ++++++++++++++++++++++++++++++++++-- 2 files changed, 43 insertions(+), 2 deletions(-) diff --git a/include/sysemu/device_tree.h b/include/sysemu/device_tree.h index 8a2fe55622..ef060a9759 100644 --- a/include/sysemu/device_tree.h +++ b/include/sysemu/device_tree.h @@ -121,6 +121,7 @@ uint32_t qemu_fdt_get_phandle(void *fdt, const char *pa= th); uint32_t qemu_fdt_alloc_phandle(void *fdt); int qemu_fdt_nop_node(void *fdt, const char *node_path); int qemu_fdt_add_subnode(void *fdt, const char *name); +int qemu_fdt_add_path(void *fdt, const char *path); =20 #define qemu_fdt_setprop_cells(fdt, node_path, property, ...) = \ do { = \ diff --git a/softmmu/device_tree.c b/softmmu/device_tree.c index b621f63fba..3965c834ca 100644 --- a/softmmu/device_tree.c +++ b/softmmu/device_tree.c @@ -540,8 +540,8 @@ int qemu_fdt_add_subnode(void *fdt, const char *name) =20 retval =3D fdt_add_subnode(fdt, parent, basename); if (retval < 0) { - error_report("FDT: Failed to create subnode %s: %s", name, - fdt_strerror(retval)); + error_report("%s: Failed to create subnode %s: %s", + __func__, name, fdt_strerror(retval)); exit(1); } =20 @@ -549,6 +549,46 @@ int qemu_fdt_add_subnode(void *fdt, const char *name) return retval; } =20 +/* + * qemu_fdt_add_path: Like qemu_fdt_add_subnode(), but will add + * all missing subnodes from the given path. + */ +int qemu_fdt_add_path(void *fdt, const char *path) +{ + const char *name; + const char *p =3D path; + int namelen, retval; + int parent =3D 0; + + if (path[0] !=3D '/') { + return -1; + } + + while (p) { + name =3D p + 1; + p =3D strchr(name, '/'); + namelen =3D p !=3D NULL ? p - name : strlen(name); + + retval =3D fdt_subnode_offset_namelen(fdt, parent, name, namelen); + if (retval < 0 && retval !=3D -FDT_ERR_NOTFOUND) { + error_report("%s: Unexpected error in finding subnode %.*s: %s= ", + __func__, namelen, name, fdt_strerror(retval)); + exit(1); + } else if (retval =3D=3D -FDT_ERR_NOTFOUND) { + retval =3D fdt_add_subnode_namelen(fdt, parent, name, namelen); + if (retval < 0) { + error_report("%s: Failed to create subnode %.*s: %s", + __func__, namelen, name, fdt_strerror(retval)= ); + exit(1); + } + } + + parent =3D retval; + } + + return retval; +} + void qemu_fdt_dumpdtb(void *fdt, int size) { const char *dumpdtb =3D current_machine->dumpdtb; --=20 2.23.0 From nobody Sat May 18 13:36:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624354911207977.246800406489; Tue, 22 Jun 2021 02:41:51 -0700 (PDT) Received: from localhost ([::1]:39470 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvcuk-0001S4-2m for importer@patchew.org; Tue, 22 Jun 2021 05:41:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35944) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvcns-00039x-2q; Tue, 22 Jun 2021 05:34:44 -0400 Received: from szxga03-in.huawei.com ([45.249.212.189]:2179) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvcni-00032Q-L2; Tue, 22 Jun 2021 05:34:43 -0400 Received: from dggemv703-chm.china.huawei.com (unknown [172.30.72.53]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4G8LjB1vD7z70y7; Tue, 22 Jun 2021 17:30:22 +0800 (CST) Received: from dggpemm500023.china.huawei.com (7.185.36.83) by dggemv703-chm.china.huawei.com (10.3.19.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 22 Jun 2021 17:34:27 +0800 Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 22 Jun 2021 17:34:26 +0800 From: Yanan Wang To: Peter Maydell , Andrew Jones , Paolo Bonzini , "Michael S . Tsirkin" , Igor Mammedov , Shannon Zhao , Alistair Francis , David Gibson , , Subject: [RFC PATCH v4 5/7] hw/arm/virt: Add cpu-map to device tree Date: Tue, 22 Jun 2021 17:34:11 +0800 Message-ID: <20210622093413.13360-6-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20210622093413.13360-1-wangyanan55@huawei.com> References: <20210622093413.13360-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.189; envelope-from=wangyanan55@huawei.com; helo=szxga03-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Barry Song , Yanan Wang , prime.zeng@hisilicon.com, wanghaibin.wang@huawei.com, yuzenghui@huawei.com, yangyicong@huawei.com, zhukeqian1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Andrew Jones Support device tree CPU topology descriptions. In accordance with the Devicetree Specification, the Linux Doc "arm/cpus.yaml" requires that cpus and cpu nodes in the DT are present. And we have already met the requirement by generating /cpus/cpu@* nodes for members within ms->smp.cpus. Accordingly, we should also create subnodes in cpu-map for the present cpus, each of which relates to an unique cpu node. The Linux Doc "cpu/cpu-topology.txt" states that the hierarchy of CPUs in a SMP system is defined through four entities and they are socket/cluster/core/thread. It is also required that a socket node's child nodes must be one or more cluster nodes. Given that currently we are only provided with information of socket/core/thread, we assume there is one cluster child node in each socket node when creating cpu-map. Signed-off-by: Andrew Jones Co-developed-by: Yanan Wang Signed-off-by: Yanan Wang --- hw/arm/virt.c | 58 ++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 48 insertions(+), 10 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index f29d796f3f..645ce7d260 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -355,17 +355,17 @@ static void fdt_add_cpu_nodes(const VirtMachineState = *vms) int smp_cpus =3D ms->smp.cpus; =20 /* - * From Documentation/devicetree/bindings/arm/cpus.txt - * On ARM v8 64-bit systems value should be set to 2, - * that corresponds to the MPIDR_EL1 register size. - * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs - * in the system, #address-cells can be set to 1, since - * MPIDR_EL1[63:32] bits are not used for CPUs - * identification. + * See Linux Documentation/devicetree/bindings/arm/cpus.yaml + * On ARM v8 64-bit systems value should be set to 2, + * that corresponds to the MPIDR_EL1 register size. + * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs + * in the system, #address-cells can be set to 1, since + * MPIDR_EL1[63:32] bits are not used for CPUs + * identification. * - * Here we actually don't know whether our system is 32- or 64-bit on= e. - * The simplest way to go is to examine affinity IDs of all our CPUs.= If - * at least one of them has Aff3 populated, we set #address-cells to = 2. + * Here we actually don't know whether our system is 32- or 64-bit one. + * The simplest way to go is to examine affinity IDs of all our CPUs. = If + * at least one of them has Aff3 populated, we set #address-cells to 2. */ for (cpu =3D 0; cpu < smp_cpus; cpu++) { ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); @@ -408,8 +408,46 @@ static void fdt_add_cpu_nodes(const VirtMachineState *= vms) ms->possible_cpus->cpus[cs->cpu_index].props.node_id); } =20 + if (ms->expose_cpu_topology) { + qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", + qemu_fdt_alloc_phandle(ms->fdt)); + } + g_free(nodename); } + + if (ms->expose_cpu_topology) { + /* + * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt + * In a SMP system, the hierarchy of CPUs is defined through four + * entities that are used to describe the layout of physical CPUs + * in the system: socket/cluster/core/thread. + */ + qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); + + for (cpu =3D smp_cpus - 1; cpu >=3D 0; cpu--) { + char *cpu_path =3D g_strdup_printf("/cpus/cpu@%d", cpu); + char *map_path; + + if (ms->smp.threads > 1) { + map_path =3D g_strdup_printf( + "/cpus/cpu-map/%s%d/cluster0/%s%d/%s%d", + "socket", cpu / (ms->smp.cores * ms->smp.threads), + "core", (cpu / ms->smp.threads) % ms->smp.cores, + "thread", cpu % ms->smp.threads); + } else { + map_path =3D g_strdup_printf( + "/cpus/cpu-map/%s%d/cluster0/%s%d", + "socket", cpu / ms->smp.cores, + "core", cpu % ms->smp.cores); + } + qemu_fdt_add_path(ms->fdt, map_path); + qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); + + g_free(map_path); + g_free(cpu_path); + } + } } =20 static void fdt_add_its_gic_node(VirtMachineState *vms) --=20 2.23.0 From nobody Sat May 18 13:36:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16243549731691008.9364752521108; Tue, 22 Jun 2021 02:42:53 -0700 (PDT) Received: from localhost ([::1]:41982 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvcvk-00039k-2J for importer@patchew.org; Tue, 22 Jun 2021 05:42:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35914) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvcnm-000357-S8; Tue, 22 Jun 2021 05:34:38 -0400 Received: from szxga02-in.huawei.com ([45.249.212.188]:2150) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvcnh-00032p-0R; Tue, 22 Jun 2021 05:34:38 -0400 Received: from dggemv711-chm.china.huawei.com (unknown [172.30.72.54]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4G8LkB1qbyz71kX; Tue, 22 Jun 2021 17:31:14 +0800 (CST) Received: from dggpemm500023.china.huawei.com (7.185.36.83) by dggemv711-chm.china.huawei.com (10.1.198.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 22 Jun 2021 17:34:29 +0800 Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 22 Jun 2021 17:34:28 +0800 From: Yanan Wang To: Peter Maydell , Andrew Jones , Paolo Bonzini , "Michael S . Tsirkin" , Igor Mammedov , Shannon Zhao , Alistair Francis , David Gibson , , Subject: [RFC PATCH v4 6/7] hw/acpi/aml-build: Add Processor hierarchy node structure Date: Tue, 22 Jun 2021 17:34:12 +0800 Message-ID: <20210622093413.13360-7-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20210622093413.13360-1-wangyanan55@huawei.com> References: <20210622093413.13360-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.188; envelope-from=wangyanan55@huawei.com; helo=szxga02-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Barry Song , Yanan Wang , Ying Fang , Henglong Fan , prime.zeng@hisilicon.com, wanghaibin.wang@huawei.com, yuzenghui@huawei.com, yangyicong@huawei.com, zhukeqian1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a generic API to build Processor hierarchy node structure (Type 0), which is strictly consistent with descriptions in ACPI 6.2: 5.2.29.1. This function will be used to build ACPI PPTT table for cpu topology. Co-developed-by: Ying Fang Signed-off-by: Ying Fang Co-developed-by: Henglong Fan Signed-off-by: Henglong Fan Co-developed-by: Yanan Wang Signed-off-by: Yanan Wang Reviewed-by: Andrew Jones --- hw/acpi/aml-build.c | 26 ++++++++++++++++++++++++++ include/hw/acpi/aml-build.h | 4 ++++ 2 files changed, 30 insertions(+) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index d5103e6d7b..9fa5024414 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -1920,6 +1920,32 @@ void build_slit(GArray *table_data, BIOSLinker *link= er, MachineState *ms, table_data->len - slit_start, 1, oem_id, oem_table_id); } =20 +/* ACPI 6.2: 5.2.29.1 Processor hierarchy node structure (Type 0) */ +void build_processor_hierarchy_node(GArray *tbl, uint32_t flags, + uint32_t parent, uint32_t id, + uint32_t *priv_rsrc, uint32_t priv_num) +{ + int i; + + build_append_byte(tbl, 0); /* Type 0 - processor */ + build_append_byte(tbl, 20 + priv_num * 4); /* Length */ + build_append_int_noprefix(tbl, 0, 2); /* Reserved */ + build_append_int_noprefix(tbl, flags, 4); /* Flags */ + build_append_int_noprefix(tbl, parent, 4); /* Parent */ + build_append_int_noprefix(tbl, id, 4); /* ACPI Processor ID */ + + /* Number of private resources */ + build_append_int_noprefix(tbl, priv_num, 4); + + /* Private resources[N] */ + if (priv_num > 0) { + assert(priv_rsrc); + for (i =3D 0; i < priv_num; i++) { + build_append_int_noprefix(tbl, priv_rsrc[i], 4); + } + } +} + /* build rev1/rev3/rev5.1 FADT */ void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f, const char *oem_id, const char *oem_table_id) diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 471266d739..ea74b8f6ed 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -462,6 +462,10 @@ void build_srat_memory(AcpiSratMemoryAffinity *numamem= , uint64_t base, void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms, const char *oem_id, const char *oem_table_id); =20 +void build_processor_hierarchy_node(GArray *tbl, uint32_t flags, + uint32_t parent, uint32_t id, + uint32_t *priv_rsrc, uint32_t priv_num= ); + void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f, const char *oem_id, const char *oem_table_id); =20 --=20 2.23.0 From nobody Sat May 18 13:36:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1624354644968236.3397135002058; Tue, 22 Jun 2021 02:37:24 -0700 (PDT) Received: from localhost ([::1]:52954 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lvcqR-0008Ls-T8 for importer@patchew.org; Tue, 22 Jun 2021 05:37:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35848) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvcnk-0002wC-5p; Tue, 22 Jun 2021 05:34:36 -0400 Received: from szxga01-in.huawei.com ([45.249.212.187]:2426) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lvcnh-000343-1q; Tue, 22 Jun 2021 05:34:35 -0400 Received: from dggemv704-chm.china.huawei.com (unknown [172.30.72.53]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4G8LkV23vDzZh1N; Tue, 22 Jun 2021 17:31:30 +0800 (CST) Received: from dggpemm500023.china.huawei.com (7.185.36.83) by dggemv704-chm.china.huawei.com (10.3.19.47) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 22 Jun 2021 17:34:30 +0800 Received: from DESKTOP-TMVL5KK.china.huawei.com (10.174.187.128) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Tue, 22 Jun 2021 17:34:29 +0800 From: Yanan Wang To: Peter Maydell , Andrew Jones , Paolo Bonzini , "Michael S . Tsirkin" , Igor Mammedov , Shannon Zhao , Alistair Francis , David Gibson , , Subject: [RFC PATCH v4 7/7] hw/acpi/aml-build: Generate PPTT table Date: Tue, 22 Jun 2021 17:34:13 +0800 Message-ID: <20210622093413.13360-8-wangyanan55@huawei.com> X-Mailer: git-send-email 2.8.4.windows.1 In-Reply-To: <20210622093413.13360-1-wangyanan55@huawei.com> References: <20210622093413.13360-1-wangyanan55@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.187; envelope-from=wangyanan55@huawei.com; helo=szxga01-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Barry Song , Yanan Wang , prime.zeng@hisilicon.com, wanghaibin.wang@huawei.com, yuzenghui@huawei.com, yangyicong@huawei.com, zhukeqian1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Andrew Jones Add the Processor Properties Topology Table (PPTT) to expose CPU topology information defined by users to ACPI guests. Note, a DT-boot Linux guest with a non-flat CPU topology will see socket and core IDs being sequential integers starting from zero, which is different from ACPI-boot Linux guest, e.g. with -smp 4,sockets=3D2,cores=3D2,threads=3D1 a DT boot produces: cpu: 0 package_id: 0 core_id: 0 cpu: 1 package_id: 0 core_id: 1 cpu: 2 package_id: 1 core_id: 0 cpu: 3 package_id: 1 core_id: 1 an ACPI boot produces: cpu: 0 package_id: 36 core_id: 0 cpu: 1 package_id: 36 core_id: 1 cpu: 2 package_id: 96 core_id: 2 cpu: 3 package_id: 96 core_id: 3 This is due to several reasons: 1) DT cpu nodes do not have an equivalent field to what the PPTT ACPI Processor ID must be, i.e. something equal to the MADT CPU UID or equal to the UID of an ACPI processor container. In both ACPI cases those are platform dependant IDs assigned by the vendor. 2) While QEMU is the vendor for a guest, if the topology specifies SMT (> 1 thread), then, with ACPI, it is impossible to assign a core-id the same value as a package-id, thus it is not possible to have package-id=3D0 and core-id=3D0. This is because package and core containers must be in the same ACPI namespace and therefore must have unique UIDs. 3) ACPI processor containers are not mandatorily required for PPTT tables to be used and, due to the limitations of which IDs are selected described above in (2), they are not helpful for QEMU, so we don't build them with this patch. In the absence of them, Linux assigns its own unique IDs. The maintainers have chosen not to use counters from zero, but rather ACPI table offsets, which explains why the numbers are so much larger than with DT. 4) When there is no SMT (threads=3D1) the core IDs for ACPI boot guests match the logical CPU IDs, because these IDs must be equal to the MADT CPU UID (as no processor containers are present), and QEMU uses the logical CPU ID for these MADT IDs. So in summary, with QEMU as vender for the guest, we use sequential integers starting from zero for non-leaf nodes without valid ID flag, so that guest will ignore them and use table offsets as unique IDs. And we use logical CPU IDs for leaf nodes to be consistent with MADT. Signed-off-by: Andrew Jones Co-developed-by: Yanan Wang Signed-off-by: Yanan Wang --- hw/acpi/aml-build.c | 49 +++++++++++++++++++++++++++++++++++++ hw/arm/virt-acpi-build.c | 8 +++++- include/hw/acpi/aml-build.h | 3 +++ 3 files changed, 59 insertions(+), 1 deletion(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 9fa5024414..a92c7d8123 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -1946,6 +1946,55 @@ void build_processor_hierarchy_node(GArray *tbl, uin= t32_t flags, } } =20 +/* ACPI 6.2: 5.2.29 Processor Properties Topology Table (PPTT) */ +void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, + const char *oem_id, const char *oem_table_id) +{ + int pptt_start =3D table_data->len; + int uid =3D 0, socket; + + acpi_data_push(table_data, sizeof(AcpiTableHeader)); + + for (socket =3D 0; socket < ms->smp.sockets; socket++) { + uint32_t socket_offset =3D table_data->len - pptt_start; + int core; + + build_processor_hierarchy_node( + table_data, + (1 << 0), /* ACPI 6.2 - Physical package */ + 0, socket, NULL, 0); + + for (core =3D 0; core < ms->smp.cores; core++) { + uint32_t core_offset =3D table_data->len - pptt_start; + int thread; + + if (ms->smp.threads =3D=3D 1) { + build_processor_hierarchy_node( + table_data, + (1 << 1) | /* ACPI 6.2 - ACPI Processor ID valid */ + (1 << 3), /* ACPI 6.3 - Node is a Leaf */ + socket_offset, uid++, NULL, 0); + } else { + build_processor_hierarchy_node(table_data, 0, socket_offse= t, + core, NULL, 0); + + for (thread =3D 0; thread < ms->smp.threads; thread++) { + build_processor_hierarchy_node( + table_data, + (1 << 1) | /* ACPI 6.2 - ACPI Processor ID valid */ + (1 << 2) | /* ACPI 6.3 - Processor is a Thread */ + (1 << 3), /* ACPI 6.3 - Node is a Leaf */ + core_offset, uid++, NULL, 0); + } + } + } + } + + build_header(linker, table_data, + (void *)(table_data->data + pptt_start), "PPTT", + table_data->len - pptt_start, 2, oem_id, oem_table_id); +} + /* build rev1/rev3/rev5.1 FADT */ void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f, const char *oem_id, const char *oem_table_id) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index f1024843dd..90d2176b35 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -698,13 +698,19 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuild= Tables *tables) dsdt =3D tables_blob->len; build_dsdt(tables_blob, tables->linker, vms); =20 - /* FADT MADT GTDT MCFG SPCR pointed to by RSDT */ + /* FADT MADT PPTT GTDT MCFG SPCR pointed to by RSDT */ acpi_add_table(table_offsets, tables_blob); build_fadt_rev5(tables_blob, tables->linker, vms, dsdt); =20 acpi_add_table(table_offsets, tables_blob); build_madt(tables_blob, tables->linker, vms); =20 + if (ms->expose_cpu_topology) { + acpi_add_table(table_offsets, tables_blob); + build_pptt(tables_blob, tables->linker, ms, vms->oem_id, + vms->oem_table_id); + } + acpi_add_table(table_offsets, tables_blob); build_gtdt(tables_blob, tables->linker, vms); =20 diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index ea74b8f6ed..6c29f853cd 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -466,6 +466,9 @@ void build_processor_hierarchy_node(GArray *tbl, uint32= _t flags, uint32_t parent, uint32_t id, uint32_t *priv_rsrc, uint32_t priv_num= ); =20 +void build_pptt(GArray *table_data, BIOSLinker *linker, MachineState *ms, + const char *oem_id, const char *oem_table_id); + void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f, const char *oem_id, const char *oem_table_id); =20 --=20 2.23.0