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[83.35.24.93]) by smtp.gmail.com with ESMTPSA id e17sm6947404wre.79.2021.06.17.10.49.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Jun 2021 10:49:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3cJHVP7PCPcnG9dBbz0rAw/mtV+g+hts+a+OLq73puU=; b=MNGqGwHoW/vP+zUZlny2AdixPoU5jkX2uqj7dg2S8MbGCPLjhwB1oGl4/r+t7nmGz4 2R2B4ekeBliFsDBNGhCsl7PpciPvCbT7+VyyzPtu0NEkRLS3Xxih2XjdR+ph5fRBLJS9 1j1xVbz61G7ZXe3Rwc6NfyXvmRgCCuyeGY8S/vdfw0tYmOn7a0pyw/9fvwCopK8QbNMJ XOjPNfJqimxhfhkUpuptJcuMTj96br67D9+7gEWuRY3PB1RNr1iC5lOvgFSsoHUajuQs G8dJtgTIBEw4K2f+RHCz2WWyKPVk3gCbV3pA+fRXwvzFWz165k/54QRktXiaqEweropI ZbZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=3cJHVP7PCPcnG9dBbz0rAw/mtV+g+hts+a+OLq73puU=; b=mEVTAqz3ELTBSi7Vp4zzhz6xyTeVeWXB0O+uwIILWejHIEBqUhWOszk85bZI1Y7hsT +O7fM/ZMINBL3Zlf7F95ZWQYcP02OuGU7NIZNR3LOXAxC6vgwqdyGendLiTxvJhcpadA RfRlC3c5PzZdkvFRag68lWxnztN8ahP748mRqBXCpMH5mp5172M5vAbRS5GEVTAcgbut D1+v88veD2PXBQ16p7/Zd6PKuLyNc81Zw6JPkfBCY1Ch74vhYTYPAYWSnV0rFmvQ+sga omBxsJbg2ouX7NA/gGcEtzFYhYNytj9UnMeNN0wsTVKOkb14uElRyUQM2FuRD4qtP4dn ByyA== X-Gm-Message-State: AOAM530c/nRCF9b4/i5Grm+wakC68O7YrlHsu2uMr+9tJfQ8gZxcJtIu QVEXqM9iZyN8x1+7YA5X0N8= X-Google-Smtp-Source: ABdhPJzWelY9HMhfn643SsMvxAX4n9qDHz2Mbx7qkmJty595B5lkPhsXEnnXRIVku4YDaSLaIYhtng== X-Received: by 2002:a5d:6882:: with SMTP id h2mr6080999wru.243.1623952168323; Thu, 17 Jun 2021 10:49:28 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Aleksandar Rikalo , Richard Henderson , Jiaxun Yang Subject: [PATCH 4/4] target/mips: Add declarations for generic DSP TCG helpers Date: Thu, 17 Jun 2021 19:49:07 +0200 Message-Id: <20210617174907.2904067-5-f4bug@amsat.org> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210617174907.2904067-1-f4bug@amsat.org> References: <20210617174907.2904067-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To be able to extract the DSP ASE translation routines to different source file, declare few TCG helpers, MASK_SPECIAL3 and a DSP register in "translate.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/mips/tcg/translate.h | 7 +++++++ target/mips/tcg/translate.c | 10 +++++----- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index c25fad597d5..c6f57de7e0d 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -52,6 +52,8 @@ typedef struct DisasContext { /* MIPS major opcodes */ #define MASK_OP_MAJOR(op) (op & (0x3F << 26)) =20 +#define MASK_SPECIAL3(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) + #define OPC_CP1 (0x11 << 26) =20 /* Coprocessor 1 (rs field) */ @@ -131,6 +133,10 @@ void check_cp1_64bitmode(DisasContext *ctx); void check_cp1_registers(DisasContext *ctx, int regs); void check_cop1x(DisasContext *ctx); =20 +void check_dsp(DisasContext *ctx); +void check_dsp_r2(DisasContext *ctx); +void check_dsp_r3(DisasContext *ctx); + void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offs= et); void gen_move_low32(TCGv ret, TCGv_i64 arg); void gen_move_high32(TCGv ret, TCGv_i64 arg); @@ -168,6 +174,7 @@ extern TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; extern TCGv_i32 fpu_fcr0, fpu_fcr31; extern TCGv_i64 fpu_f64[32]; extern TCGv bcond; +extern TCGv cpu_dspctrl; =20 #define LOG_DISAS(...) = \ do { = \ diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 7b173e2bd2f..97ef816e95f 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -374,7 +374,6 @@ enum { }; =20 /* Special3 opcodes */ -#define MASK_SPECIAL3(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) =20 enum { OPC_EXT =3D 0x00 | OPC_SPECIAL3, @@ -1227,8 +1226,9 @@ TCGv cpu_gpr[32], cpu_PC; */ TCGv_i64 cpu_gpr_hi[32]; TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; -static TCGv cpu_dspctrl, btarget; +static TCGv btarget; TCGv bcond; +TCGv cpu_dspctrl; static TCGv cpu_lladdr, cpu_llval; static TCGv_i32 hflags; TCGv_i32 fpu_fcr0, fpu_fcr31; @@ -1633,7 +1633,7 @@ void check_cp1_registers(DisasContext *ctx, int regs) * Verify that the processor is running with DSP instructions enabled. * This is enabled by CP0 Status register MX(24) bit. */ -static inline void check_dsp(DisasContext *ctx) +void check_dsp(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) { if (ctx->insn_flags & ASE_DSP) { @@ -1644,7 +1644,7 @@ static inline void check_dsp(DisasContext *ctx) } } =20 -static inline void check_dsp_r2(DisasContext *ctx) +void check_dsp_r2(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R2))) { if (ctx->insn_flags & ASE_DSP) { @@ -1655,7 +1655,7 @@ static inline void check_dsp_r2(DisasContext *ctx) } } =20 -static inline void check_dsp_r3(DisasContext *ctx) +void check_dsp_r3(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R3))) { if (ctx->insn_flags & ASE_DSP) { --=20 2.31.1