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v2: dropped the hw/acpi/ghes-stub.c changes, which produce a weird Meson error ("Tried to extract unknown source ghes-stub.c") which didn't happen on my local builds; I'll investigate later... -- PMM The following changes since commit 1ea06abceec61b6f3ab33dadb0510b6e09fb61e2: Merge remote-tracking branch 'remotes/berrange-gitlab/tags/misc-fixes-pull-request' into staging (2021-06-14 15:59:13 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210616 for you to fetch changes up to 703235a303d6862a7e3f5c6aa9eff7471cb138b2: include/qemu/int128.h: Add function to create Int128 from int64_t (2021-06-16 14:33:52 +0100) ---------------------------------------------------------------- target-arm queue: * hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes * handle some UNALLOCATED decode cases correctly rather than asserting * hw: virt: consider hw_compat_6_0 * hw/arm: add quanta-gbs-bmc machine * hw/intc/armv7m_nvic: Remove stale comment * target/arm: Fix mte page crossing test * hw/arm: quanta-q71l add pca954x muxes * target/arm: First few parts of MVE support ---------------------------------------------------------------- Heinrich Schuchardt (1): hw: virt: consider hw_compat_6_0 Jean-Philippe Brucker (1): hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes Patrick Venture (5): hw/arm: add quanta-gbs-bmc machine hw/arm: quanta-gbs-bmc add i2c comments hw/arm: gsj add i2c comments hw/arm: gsj add pca9548 hw/arm: quanta-q71l add pca954x muxes Peter Maydell (14): hw/intc/armv7m_nvic: Remove stale comment target/arm: Provide and use H8 and H1_8 macros target/arm: Enable FPSCR.QC bit for MVE target/arm: Handle VPR semantics in existing code target/arm: Add handling for PSR.ECI/ICI target/arm: Let vfp_access_check() handle late NOCP checks target/arm: Implement MVE LCTP target/arm: Implement MVE WLSTP insn target/arm: Implement MVE DLSTP target/arm: Implement MVE LETP insn target/arm: Add framework for MVE decode target/arm: Move expand_pred_b() data to vec_helper.c bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations include/qemu/int128.h: Add function to create Int128 from int64_t Richard Henderson (4): target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16 target/arm: Remove fprintf from disas_simd_mod_imm target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16 target/arm: Fix mte page crossing test include/qemu/bitops.h | 29 +++ include/qemu/int128.h | 10 + target/arm/translate-a32.h | 2 + target/arm/translate.h | 9 + target/arm/vec_internal.h | 9 + target/arm/mve.decode | 20 ++ target/arm/t32.decode | 15 +- hw/arm/aspeed.c | 11 +- hw/arm/npcm7xx_boards.c | 107 ++++++++++- hw/arm/virt.c | 2 + hw/intc/arm_gicv3_cpuif.c | 5 +- hw/intc/armv7m_nvic.c | 6 - target/arm/m_helper.c | 54 +++++- target/arm/mte_helper.c | 2 +- target/arm/sve_helper.c | 381 +++++++++++++------------------------- target/arm/translate-a64.c | 87 +++++---- target/arm/translate-m-nocp.c | 16 +- target/arm/translate-mve.c | 29 +++ target/arm/translate-vfp.c | 65 +++++-- target/arm/translate.c | 300 ++++++++++++++++++++++++++++-- target/arm/vec_helper.c | 116 +++++++++++- target/arm/vfp_helper.c | 3 +- tests/tcg/aarch64/mte-7.c | 31 ++++ hw/arm/Kconfig | 2 + target/arm/meson.build | 2 + tests/tcg/aarch64/Makefile.target | 2 +- 26 files changed, 967 insertions(+), 348 deletions(-) create mode 100644 target/arm/mve.decode create mode 100644 target/arm/translate-mve.c create mode 100644 tests/tcg/aarch64/mte-7.c
v3->v4: Windows headers define an INT type which clashed with an enum value name in arm_gicv3_its.c... The following changes since commit eae587e8e3694b1aceab23239493fb4c7e1a80f5: Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-09-13' into staging (2021-09-13 11:00:30 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210913-3 for you to fetch changes up to 28e987a7e7edaa3ca7feeac65edca26145df8814: hw/arm/mps2.c: Mark internal-only I2C buses as 'full' (2021-09-13 21:01:08 +0100) ---------------------------------------------------------------- target-arm queue: * mark MPS2/MPS3 board-internal i2c buses as 'full' so that command line user-created devices are not plugged into them * Take an exception if PSTATE.IL is set * Support an emulated ITS in the virt board * Add support for kudo-bmc board * Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM * cadence_uart: Fix clock handling issues that prevented u-boot from running ---------------------------------------------------------------- Bin Meng (6): hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase hw/char: cadence_uart: Disable transmit when input clock is disabled hw/char: cadence_uart: Move clock/reset check to uart_can_receive() hw/char: cadence_uart: Convert to memop_with_attrs() ops hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}() hw/char: cadence_uart: Log a guest error when device is unclocked or in reset Chris Rauer (1): hw/arm: Add support for kudo-bmc board. Marc Zyngier (1): hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM Peter Maydell (5): target/arm: Take an exception if PSTATE.IL is set qdev: Support marking individual buses as 'full' hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full' hw/arm/mps2.c: Mark internal-only I2C buses as 'full' Richard Henderson (1): target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn Shashi Mallela (9): hw/intc: GICv3 ITS initial framework hw/intc: GICv3 ITS register definitions added hw/intc: GICv3 ITS command queue framework hw/intc: GICv3 ITS Command processing hw/intc: GICv3 ITS Feature enablement hw/intc: GICv3 redistributor ITS processing tests/data/acpi/virt: Add IORT files for ITS hw/arm/virt: add ITS support in virt GIC tests/data/acpi/virt: Update IORT files for ITS docs/system/arm/nuvoton.rst | 1 + hw/intc/gicv3_internal.h | 188 ++++- include/hw/arm/virt.h | 2 + include/hw/intc/arm_gicv3_common.h | 13 + include/hw/intc/arm_gicv3_its_common.h | 32 +- include/hw/qdev-core.h | 24 + target/arm/cpu.h | 1 + target/arm/kvm_arm.h | 4 +- target/arm/syndrome.h | 5 + target/arm/translate.h | 2 + hw/arm/mps2-tz.c | 92 ++- hw/arm/mps2.c | 12 +- hw/arm/npcm7xx_boards.c | 34 + hw/arm/virt.c | 29 +- hw/char/cadence_uart.c | 61 +- hw/intc/arm_gicv3.c | 14 + hw/intc/arm_gicv3_common.c | 13 + hw/intc/arm_gicv3_cpuif.c | 7 +- hw/intc/arm_gicv3_dist.c | 5 +- hw/intc/arm_gicv3_its.c | 1322 ++++++++++++++++++++++++++++++++ hw/intc/arm_gicv3_its_common.c | 7 +- hw/intc/arm_gicv3_its_kvm.c | 2 +- hw/intc/arm_gicv3_redist.c | 153 +++- hw/misc/zynq_slcr.c | 31 +- softmmu/qdev-monitor.c | 7 +- target/arm/helper-a64.c | 1 + target/arm/helper.c | 8 + target/arm/kvm.c | 7 +- target/arm/translate-a64.c | 255 +++--- target/arm/translate.c | 21 + hw/intc/meson.build | 1 + tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes 35 files changed, 2144 insertions(+), 210 deletions(-) create mode 100644 hw/intc/arm_gicv3_its.c create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb