From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772044; cv=none; d=zohomail.com; s=zohoarc; b=aJzlGvOInyLYPlGaBco2MvhO+lPIugtrhH1V9no+EvATB2ZjmxwbloF0w+3ceGjksZZR38MRkU4plOdI/coQFnjzx+pltAGt2ZAsproHRYkgaZHXWSyo/vwD1vIidVeNrAntaurkQAATqzM5vGbp6gUW04mv24L/6rJgLrT9Ao8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623772044; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+s0Ios+D5dkrEfPv6sCqiAVhIA46kg1nWpoPxlRpszc=; b=nyjFHT7dBS398XuCKoOPsHV6lNWe9ZThMoKiL/B2WkDZkBknJXJ4ikrcCkOtncLoxBbokTs/8smWZ0yNtpnTMl1uLUGMaywVctPelTY+Yb86RMG5jiNLsPIG3H4F49SHdGBPuGcS5rSMXF3YCr3QbYJJrIqq3IvZihLK6EqB7vM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623772044736996.7183306995447; Tue, 15 Jun 2021 08:47:24 -0700 (PDT) Received: from localhost ([::1]:45630 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBHf-0000Ql-0x for importer@patchew.org; Tue, 15 Jun 2021 11:47:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42754) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBEo-0005nL-Gy for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:26 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:42935) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEa-0000ua-G4 for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:26 -0400 Received: by mail-wr1-x42a.google.com with SMTP id c5so18842530wrq.9 for ; Tue, 15 Jun 2021 08:44:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+s0Ios+D5dkrEfPv6sCqiAVhIA46kg1nWpoPxlRpszc=; b=hRnf08qKBWZYucbD1lq+pjk8QlyhDXeYi02ErSkhdhu8lcnnLL4EC3Fo/+JZzz3go2 3G/o76s8i+j9i8clV5qjiZ8rd0GLpX4FTyqBt1YUfzad8uVpZwLDsNuJW52qYw4rIona ze2rGvrwPmKB/vHzQrXghLroEvY9WbKk9d5mHalOcA+bKEdfslu0DPp3vAJ08Z5FFMIv AWNX2EmMaX8wAtyMmuUo/E8lM2++S8cDiDR/dznIKy0TiGPG8VxkHu5GoY7srV+TlBJx uFiNfr1aYmm9bUKIhI+oPdwK58M0jg56Nt0hYaQ+IaethxkRR/nJj3onnNl0U7nLzPwV RJXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+s0Ios+D5dkrEfPv6sCqiAVhIA46kg1nWpoPxlRpszc=; b=EkzzN8QxjWG4kiJrMAWNnx91muG7mB7rQum57z1bwcfsY4SnZO5lhhO/2y9MH8TIvy islvLvqwgdvcZtEJqeTxDHdPb/XVfisBZgLnqfZO4DRo4TjKjDfWyljBwBi+1BCc9oYW iF7nuIq2gfXpzOgBRHJDG8PI/rnWqtjzNr9d7bPpErJyWMvku66syImJ0fEzVCLbWob6 RMuI0kJbUDOLlB/N2b57hxAfPtLwZ0aHqdqEgn+7UyOppsakVy/hjZHf/Kvx7SKZWd8X fyX3GoFmcSgnmYvM+ZaqO+j5k1ClXm7VxcnWOU61IKJ3CS0b9jBgBbKsYLe17JQBcPC0 SV9Q== X-Gm-Message-State: AOAM530KrJoAkjsignn5cUAK13oQvMrXFzZgpJqRHkeA5rm8s7xe16/C Zxvu3EWlxyfSHnTuSXIIxiX7gHFardU9Jg== X-Google-Smtp-Source: ABdhPJz3NpYZCA0aA8fH8bWf7ZCtDpauv1qp9hbbHw+EUEZmFNu6BtKLHz+21LKpWFAO3gq4lRnw2Q== X-Received: by 2002:a5d:4f05:: with SMTP id c5mr25863073wru.341.1623771849593; Tue, 15 Jun 2021 08:44:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/28] hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes Date: Tue, 15 Jun 2021 16:43:38 +0100 Message-Id: <20210615154405.21399-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Jean-Philippe Brucker Commit 382c7160d1cd ("hw/intc/arm_gicv3_cpuif: Fix EOIR write access check logic") added an assert_not_reached() if the guest writes the EOIR register while no interrupt is active. It turns out some software does this: EDK2, in GicV3ExitBootServicesEvent(), unconditionally write EOIR for all interrupts that it manages. This now causes QEMU to abort when running UEFI on a VM with GICv3. Although it is UNPREDICTABLE behavior and EDK2 does need fixing, the punishment seems a little harsh, especially since icc_eoir_write() already tolerates writes of nonexistent interrupt numbers. Display a guest error and tolerate spurious EOIR writes. Fixes: 382c7160d1cd ("hw/intc/arm_gicv3_cpuif: Fix EOIR write access check = logic") Signed-off-by: Jean-Philippe Brucker Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e Message-id: 20210604130352.1887560-1-jean-philippe@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_cpuif.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 81f94c7f4ad..3e0641aff97 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -14,6 +14,7 @@ =20 #include "qemu/osdep.h" #include "qemu/bitops.h" +#include "qemu/log.h" #include "qemu/main-loop.h" #include "trace.h" #include "gicv3_internal.h" @@ -1357,7 +1358,9 @@ static void icc_eoir_write(CPUARMState *env, const AR= MCPRegInfo *ri, } break; default: - g_assert_not_reached(); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: IRQ %d isn't active\n", __func__, irq); + return; } =20 icc_drop_prio(cs, grp); --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772044; cv=none; d=zohomail.com; s=zohoarc; b=DuNi3qi26D50hJ8LLwUarz8QzoKvOqHEm0urVSj+2KyiDaDSfYx65wN6q5z3AbDObQSu4GJ6mV4Aiq+nmJro1wujNT5T4Wy6M4nw19kRh//kSYE6NvQ0NXPTdcHbXXrcNhAjhLVaVjY2fq/t2B651dN0g7aySCJwYZlOlQU6+uQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623772044; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2FN+DLCkRaewYYSAAvTveP7CUhTuCt0YRLwdFHpiWrg=; b=F2wAsbOHUIZA0Ftd3OhEORNU+C1ZpNtoq1HycgWPlsUIcRLksBZfMJMf527R703I5awFFuH229ksiQfbqGcHW/ckCDX3JeRSS+eEYhdPsVqnXLkerktfGqaHIZ0v4oHOiar3U9DSzSkyY4Q35dhrPHRnFIFeQXpvusClmwVIhmw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623772044667856.6632678869785; Tue, 15 Jun 2021 08:47:24 -0700 (PDT) Received: from localhost ([::1]:45624 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBHf-0000QW-9b for importer@patchew.org; Tue, 15 Jun 2021 11:47:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42814) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBEt-0005ou-Rp for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:35 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:38650) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEa-0000uj-Gm for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:31 -0400 Received: by mail-wr1-x432.google.com with SMTP id c9so18861664wrt.5 for ; Tue, 15 Jun 2021 08:44:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=2FN+DLCkRaewYYSAAvTveP7CUhTuCt0YRLwdFHpiWrg=; b=SwOZcToum7CpXllqNqZaO2CK3e5CMxqWfw+SGK3oRnN82zGIw6074AOVKYoOAgKgL6 +4gpEkln+B7GbiaBC2dK+7Kt5x+20Sot4jzu37fh3UCA1Z/n1zj8RXTlCn6lh7g0QTv2 YvCOS7wDDwBzaelaLlWaGOqnCpHQSqbSGKEqSQi4z7MRNe1vKzCZ2eUapHlhrIp0Z7ur wfQHP1yeigPJ9OJFbcekIlZxnqROm/a1tbwcBg20VUPISwoR9ytsrEyZTE531rlLGqxr FtooJVo3lD1KIeUWiOyjYk584ngdZu5LDgj5JCjRQleKxG5vqTrME/8pWUvhu3YZSCGV vXFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2FN+DLCkRaewYYSAAvTveP7CUhTuCt0YRLwdFHpiWrg=; b=l1Cecaic3CRKXq47NFLcZlqYSNFoEF22Z9JHOLARvVCmwyWvq4saBsUAqVxxEVcsFy tuhQhLDCt8H9HeonVQ7mJt/X9YFeLyPpNf3YtEGBNGX6zXWAUCky0iMW47IuUCtFStw8 AthqivMJvROTAm8rDgOoohBrCf/aAGj17Nlix5rwpwkQX+2aq1W1WJNiJ1EL9WGO5xEU eQW9th5qwNwlcvKZ5ySnfYbw02gP1h2yOgpyCoNBORl3sraVk9BrIfcTYE0Iz5GHExmc eHU7Fs8FTR2lK1XwYXwyJP2esA1LXfHikJmamHN8+SveDpVpzrzfoY6re9DQlhiw6rXb tbDw== X-Gm-Message-State: AOAM533WWOjatrdHvTa0Q6QWPAhsfUTF42OkkwAHSn7qSf16fjYr6HdQ sV3SuvgtzBk5FrDe5+KuGgG1TNui93JGVg== X-Google-Smtp-Source: ABdhPJx7CQTFmtXejD7c5dXSeogwDWgt9V9SJfGqBpE+EMsCM80AkYGrJlSCiLdh2B5r7hprEuNgMg== X-Received: by 2002:adf:ce90:: with SMTP id r16mr26696426wrn.146.1623771850334; Tue, 15 Jun 2021 08:44:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/28] target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16 Date: Tue, 15 Jun 2021 16:43:39 +0100 Message-Id: <20210615154405.21399-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson This fprintf+assert has been in place since the beginning. It is prior to the fp_access_check, so we're still good to raise sigill here. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/381 Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210604183506.916654-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 8713dfec174..2477b55c53a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13234,8 +13234,8 @@ static void disas_simd_two_reg_misc_fp16(DisasConte= xt *s, uint32_t insn) case 0x7f: /* FSQRT (vector) */ break; default: - fprintf(stderr, "%s: insn 0x%04x fpop 0x%2x\n", __func__, insn, fp= op); - g_assert_not_reached(); + unallocated_encoding(s); + return; } =20 =20 --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772425; cv=none; d=zohomail.com; s=zohoarc; b=eWamHfLzZF+ngXHVY5Osko/Ax0Yri3rctKjrB7MMowoeG8Z20Of9hnQzISOibfYu9DEZH5Eu4ZxlmJoCliR+S25GLjQ0huFE4dq7+zxE5jgTXlIGBHGT8EPVzZIQXxIkUmRfnUSXu8gPBvxv++3e9Qla9twPpSwBgaDX14Hi2Jg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623772425; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qhIXGkQ5B2f72hCsDiiPtZauaOm4OlOs0XmLE/HyYSI=; b=b0EKbTPkhRdjOjl4SH+SKbx434Mr1t9FdyxkGbYEeRGT495VR8GcWEeIxcXaGawpQ8Xpgi8/z5hKcZzE2mGqFZwc9sj/YMVGvSgar/oGGc98t7T6o3Dg3iJKN7MCVytvLjiymBY/g9eXpnv7/gWXaqu9B2ydPxGgXkK9KLehxQ8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623772425452948.5692299069652; Tue, 15 Jun 2021 08:53:45 -0700 (PDT) Received: from localhost ([::1]:34900 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBNo-0003xL-4i for importer@patchew.org; Tue, 15 Jun 2021 11:53:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42810) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBEt-0005om-PH for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:35 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:42936) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEa-0000v4-Go for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:30 -0400 Received: by mail-wm1-x32e.google.com with SMTP id l7-20020a05600c1d07b02901b0e2ebd6deso2301837wms.1 for ; Tue, 15 Jun 2021 08:44:12 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qhIXGkQ5B2f72hCsDiiPtZauaOm4OlOs0XmLE/HyYSI=; b=zM2+d5Q7C5gWWr83CsdJLYqWt3u7Cu8HYkcYkeMTmBjhX+XucYqaISIfgJCsoDS5LA ZhL54XywPB+Qkz4NHVf1PIfnJRKnkgolSU8+avHwsXx9axowL9fatdPlXLUyxkP3QA3n DNRkeUGDh+Y2lajGycZJsZkYnXDdOKEt9vZouFIKk96kcQ9IPmCnt802ZbVMXK8kb4Op XDGMHb1Z9DsFvffySZiDOuuiLde60kKSx6Sa4mP+57CsXFKxkxyEsPp2XUtnW0DtRGDQ uPIwPagXz4cFjy1HHlm4Jx2LBo0siGX4LSAcSfmS5nWut0nv7KwnJZLnjbxREVYODa8H asdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qhIXGkQ5B2f72hCsDiiPtZauaOm4OlOs0XmLE/HyYSI=; b=McT/MNES2Kv4GrD55XfpVX+xgiSV0y3ROmBsGpA02+GixsZUZMFBGJqiqNVWZy7GmL /NMEcLGHz4VvL066zNOyrk5bnc3QOfq1LoKa/FOESfWn0mSiKAm8Yj/cWZRLe6MbXmv1 3mEDl868WkyIhSLFvbfFgZD37V7AckURMBZs5wD+Y0lTV84LfxBP2Z2BYFuXOCu0k6jk PpdLzSefDovxeyYSU/VhpOVlZYmTYxbO8VWCyH6jIPeGwg09ryFaf3O2KJZsgFKuWL2W eDLk2J0bBwUIA7OYJJL2aBkXaaYja3Ou4bzm06kCqzhiG51VRwAB01GODMK9y0F6gw8b zyyA== X-Gm-Message-State: AOAM533CoICh78HCmtj+BahitcimSSnP8JatviNCeO0Z888orF3FRyuc eopFQ8ZUK84zRj23gPMD64il4o+tIGAaSw== X-Google-Smtp-Source: ABdhPJw5L6KWrbZiFGbQzAb0jbnFJ8PoEfmqHkm04ktk0UwytxQ2OOw713Arq2AhRQ74g567JJH5aQ== X-Received: by 2002:a1c:e91a:: with SMTP id q26mr6033687wmc.170.1623771850910; Tue, 15 Jun 2021 08:44:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/28] target/arm: Remove fprintf from disas_simd_mod_imm Date: Tue, 15 Jun 2021 16:43:40 +0100 Message-Id: <20210615154405.21399-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson The default of this switch is truly unreachable. The switch selector is 3 bits, and all 8 cases are present. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210604183506.916654-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2477b55c53a..9bb15ca6189 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -8291,7 +8291,6 @@ static void disas_simd_mod_imm(DisasContext *s, uint3= 2_t insn) } break; default: - fprintf(stderr, "%s: cmode_3_1: %x\n", __func__, cmode_3_1); g_assert_not_reached(); } =20 --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772045; cv=none; d=zohomail.com; s=zohoarc; b=LJXjVAUjhLJY+qURawBGp9am8YYJKaLp6T4Us+fOoG/VWyYAIoQpDfl4NLoaMhNHZ3lHoMzYFjaXMvItuSL9oywPv1otu80kEX0dNzxqLf3CgHEgDqC9BfxLyV+1DZej/44RVs7XRBdIAk4fdBQCi+AZ4gkGxC5NCVmm08D11Ng= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623772045; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PAJZt3oQr46El21qcu2kh9jE/StU5MJCbu3wcrVJdyg=; b=NfZjEiPoawKmj35LWUjy1s+pVtnaqGPQIftcfSr/mOqIiaGBkRynv0+Ngf8HwROWaUXPR7RRn6be5hKhWb69/KNepjYGno2yMXG6z2HrQUUohoqMDIgsGQmzT+ftFVLKkGW8wVcDN/VAtsl0kOXZMU6LXS4+DUWE72WrISzyQek= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623772045748743.7715961413932; Tue, 15 Jun 2021 08:47:25 -0700 (PDT) Received: from localhost ([::1]:45750 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBHf-0000Va-TA for importer@patchew.org; Tue, 15 Jun 2021 11:47:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBEv-0005p7-I4 for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:35 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:36736) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEa-0000vP-V2 for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:33 -0400 Received: by mail-wm1-x333.google.com with SMTP id h11-20020a05600c350bb02901b59c28e8b4so2106435wmq.1 for ; Tue, 15 Jun 2021 08:44:12 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=PAJZt3oQr46El21qcu2kh9jE/StU5MJCbu3wcrVJdyg=; b=VHdUZvhx00mF8DcSAmVUt1DOVCWEvexS3tzf1bAa8RIrrlKxMDeoBzp3/+/zcArhVC +aoqe+C5HXZcXwtUMI0oHvQMCShLqjTiUTCJaA4jOmritD6qdftuz00QELpk0s0kZZn1 5WzvHc0pY98r+SgEUY0NgN0TdPBrEsL1BWwHQWFHKrgM4klCf4ywBWXXLpD/ktu2zk5G /fqgwLh/6+T8BO2NNZtSmE2aVekubzGmm3+jGDgeeix3RLVhKfXgeyPYh7vlCZ5q/2Jf pU4fi3ZPGHXk1qVnI0yeJ1TR6rBkl2R8wC5vFvHqdESwQ0ZdNn2zz+JdIGZIFB6ZPYrc czdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PAJZt3oQr46El21qcu2kh9jE/StU5MJCbu3wcrVJdyg=; b=onebUZp3qHJFvCuSaVHoZ7zeJCKxPo+JoXl4wuhsSOcFGjUw+5F3g52Bo5dcNTUOcY pnn5wmyQde4RNbrrXdJdZrKJXWFxM1TYtWNeIgBSzhKZ+eFYuOoYj77rTFzpF2ZE8MfI 4N+8ggnG/driWkWw1Ck6jij2vrZIPRkpm1f2YZTUyFb9UDUF6dItebeEuukvowvP3n/M /DdOY3tabldEbzM6Pgsj1+iPTly66i4vycf7+vMl1mDuLrzjzgaPVmAun2YO9u8Bm/bp cO174L6+3XCAeRR/0XSBKUmNYA8abL+RqrJ8aGeY3KZYNW4YP4WNTgH8v3YPPn/ZLDw0 1i1A== X-Gm-Message-State: AOAM5329fGaV+fmkYlKWGl6ohauqXZIFXPx/bpjnm8od0o3yjXYY+Fzp ygb5EiU+1UU0SoGi3fz0WYUCHbcr+7pt0w== X-Google-Smtp-Source: ABdhPJxvHR7M9VF3PEqTBV4VFVbcnPftLr0afWu30aD74w66X9dXKiLaPcJqpOqne47MlteCR8L1Yw== X-Received: by 2002:a05:600c:35c1:: with SMTP id r1mr5949076wmq.181.1623771851651; Tue, 15 Jun 2021 08:44:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/28] target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16 Date: Tue, 15 Jun 2021 16:43:41 +0100 Message-Id: <20210615154405.21399-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson This fprintf+assert has been in place since the beginning. It is after to the fp_access_check, so we need to move the check up. Fold that in to the pairwise filter. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210604183506.916654-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 82 +++++++++++++++++++++++--------------- 1 file changed, 50 insertions(+), 32 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9bb15ca6189..7f74d0e81a9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11989,12 +11989,57 @@ static void disas_simd_three_reg_same(DisasContex= t *s, uint32_t insn) */ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) { - int opcode, fpopcode; - int is_q, u, a, rm, rn, rd; - int datasize, elements; - int pass; + int opcode =3D extract32(insn, 11, 3); + int u =3D extract32(insn, 29, 1); + int a =3D extract32(insn, 23, 1); + int is_q =3D extract32(insn, 30, 1); + int rm =3D extract32(insn, 16, 5); + int rn =3D extract32(insn, 5, 5); + int rd =3D extract32(insn, 0, 5); + /* + * For these floating point ops, the U, a and opcode bits + * together indicate the operation. + */ + int fpopcode =3D opcode | (a << 3) | (u << 4); + int datasize =3D is_q ? 128 : 64; + int elements =3D datasize / 16; + bool pairwise; TCGv_ptr fpst; - bool pairwise =3D false; + int pass; + + switch (fpopcode) { + case 0x0: /* FMAXNM */ + case 0x1: /* FMLA */ + case 0x2: /* FADD */ + case 0x3: /* FMULX */ + case 0x4: /* FCMEQ */ + case 0x6: /* FMAX */ + case 0x7: /* FRECPS */ + case 0x8: /* FMINNM */ + case 0x9: /* FMLS */ + case 0xa: /* FSUB */ + case 0xe: /* FMIN */ + case 0xf: /* FRSQRTS */ + case 0x13: /* FMUL */ + case 0x14: /* FCMGE */ + case 0x15: /* FACGE */ + case 0x17: /* FDIV */ + case 0x1a: /* FABD */ + case 0x1c: /* FCMGT */ + case 0x1d: /* FACGT */ + pairwise =3D false; + break; + case 0x10: /* FMAXNMP */ + case 0x12: /* FADDP */ + case 0x16: /* FMAXP */ + case 0x18: /* FMINNMP */ + case 0x1e: /* FMINP */ + pairwise =3D true; + break; + default: + unallocated_encoding(s); + return; + } =20 if (!dc_isar_feature(aa64_fp16, s)) { unallocated_encoding(s); @@ -12005,31 +12050,6 @@ static void disas_simd_three_reg_same_fp16(DisasCo= ntext *s, uint32_t insn) return; } =20 - /* For these floating point ops, the U, a and opcode bits - * together indicate the operation. - */ - opcode =3D extract32(insn, 11, 3); - u =3D extract32(insn, 29, 1); - a =3D extract32(insn, 23, 1); - is_q =3D extract32(insn, 30, 1); - rm =3D extract32(insn, 16, 5); - rn =3D extract32(insn, 5, 5); - rd =3D extract32(insn, 0, 5); - - fpopcode =3D opcode | (a << 3) | (u << 4); - datasize =3D is_q ? 128 : 64; - elements =3D datasize / 16; - - switch (fpopcode) { - case 0x10: /* FMAXNMP */ - case 0x12: /* FADDP */ - case 0x16: /* FMAXP */ - case 0x18: /* FMINNMP */ - case 0x1e: /* FMINP */ - pairwise =3D true; - break; - } - fpst =3D fpstatus_ptr(FPST_FPCR_F16); =20 if (pairwise) { @@ -12152,8 +12172,6 @@ static void disas_simd_three_reg_same_fp16(DisasCon= text *s, uint32_t insn) gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fps= t); break; default: - fprintf(stderr, "%s: insn 0x%04x, fpop 0x%2x @ 0x%" PRIx64= "\n", - __func__, insn, fpopcode, s->pc_curr); g_assert_not_reached(); } =20 --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772288; cv=none; d=zohomail.com; s=zohoarc; b=lO/vPhkfwO3pA3NGEAqvHl4bnfU1qI4uxCHvlpxmj5Nd9rb+n76QllPEBLEMPlw781A1HittU38AdwwSsDxWNBj3GskSDdCAC2uhw36zSWEohAaYxhF6TQy+URcdJCKiK/p1B+T1UXxDqAvtfR4hqoDpmQs96Q8PhV4u2KH5Wy0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623772288; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cipqIlsmLSO9u7dovDg0ywdZ2LzSLNBpLmnZFygx3Mg=; b=IoKmXdFMnHWfE8M0G3Yijejbjc5zDCwPGcEHMKrFVWapM0+h08SflaF3hSI+XY4C0KzHxcUjUQ3nAK+SkxB7FxRDUvtGI8UTXMcWE0NSaPbf1bc4V9sr822dzfOjKBJJfdYTJpG6srUmxmVkEMn4Nj8YveX4Ae8nSvsZvvF75IM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623772288241435.94297582233617; Tue, 15 Jun 2021 08:51:28 -0700 (PDT) Received: from localhost ([::1]:54242 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBLb-0006Oz-7j for importer@patchew.org; Tue, 15 Jun 2021 11:51:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42842) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBEx-0005pi-Sz for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:36 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:43957) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEb-0000vo-HR for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:35 -0400 Received: by mail-wr1-x430.google.com with SMTP id r9so18878380wrz.10 for ; Tue, 15 Jun 2021 08:44:13 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cipqIlsmLSO9u7dovDg0ywdZ2LzSLNBpLmnZFygx3Mg=; b=Odoo+RKdpvPGv1g6puYC3vqZB0y7yToaNrcK+Bzq2iUKOMrd9qHUGi9qP/eS2o6cvu v3GnkIYo7NmcxjdnbtF4WUeGHT/0AlAnTmsahAWHRzUrVe7ct+fNTN5qxm5HHowCUAWD dw9/XyPRVLTFU7XQJyb1DriEm8LcEC0Z/6DlgWilpiYvsDnU3IISYjCkC43tEJxD2SR5 Aq8SRwMmRzZ0k58zk4mBgivO/2pXS0qr6BbtdgSWQC9r1NFYdbGcriALk+RgEnELhMOD gakz0NRHldKYxaFo+GWkriwuRAvaIJJJd0XQHP+WH1wq7c5UsLwVSzW0ra9FRtQ1vQsG fTyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cipqIlsmLSO9u7dovDg0ywdZ2LzSLNBpLmnZFygx3Mg=; b=mofYYM+hKlngmMCGL0dN0y+2luJR26inTYcLJvtsBb2GbncH/uEYEb+MDkVwv2UBFF 7N4gGSDQ6SgStKPZ/QJGQhPDeZxkYJtHlLQTzPiuoQmrrLdhtmq1/bgtzegh7VfOMEDU J86jvpGMC+fBdyKSTZZFY2HMBI9l8UFQ+xF4lWv2rl7bGMJn4Qqvp3Eh6aMc9AYsm/XU oC4RtbQvzUFBRJCKeqjYLz3jqDbrIF9Orx5vO9Ts1H44OZ9omxO35YW+v6YL+532fb1H i25/Ny/YIWXMA6Nq3DyB3GDWJFmOexbzfscc4SbuFJ2iPDoGq9UAhban3sEs8aK3hWe+ /D+Q== X-Gm-Message-State: AOAM531HE50JkrMl8xqcu9o1S9ZayPRY1ogX42ZhpiiarAg/oHlYzHpn suORfRYZFRGxmrwB6sq8C6Vu90WKWxnSbQ== X-Google-Smtp-Source: ABdhPJwffP+GRLAdKaCM1lXZ3t7Pp2UtsKH8fSrhdHJTPtMJERm6+XQldzrA8nqs95mwLp/P/6cJqA== X-Received: by 2002:adf:b34a:: with SMTP id k10mr26182416wrd.333.1623771852287; Tue, 15 Jun 2021 08:44:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/28] hw: virt: consider hw_compat_6_0 Date: Tue, 15 Jun 2021 16:43:42 +0100 Message-Id: <20210615154405.21399-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Heinrich Schuchardt virt-6.0 must consider hw_compat_6_0. Fixes: da7e13c00b59 ("hw: add compat machines for 6.1") Signed-off-by: Heinrich Schuchardt Reviewed-by: Cornelia Huck Message-id: 20210610183500.54207-1-xypron.glpk@gmx.de Signed-off-by: Peter Maydell --- hw/arm/virt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 840758666d4..8bc3b408fe7 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2764,6 +2764,8 @@ DEFINE_VIRT_MACHINE_AS_LATEST(6, 1) =20 static void virt_machine_6_0_options(MachineClass *mc) { + virt_machine_6_1_options(mc); + compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); } DEFINE_VIRT_MACHINE(6, 0) =20 --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772564; cv=none; d=zohomail.com; s=zohoarc; b=CUDE18TxhwezM1138bg7kZwDKzuWzh+RtsZM2PsZ9FDKpFMRvT7aj3gaVluOkjQq4fOkQOqY2d8X/8hxom2jaUyCIyiwEmyVDsUMtJ7WVp5NSqTiF9lmbhQ7r2aiwLzjOsr7f5+tk6XQi3+sg96CV8i31/q8IIyCwxhTTFNnoV0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623772564; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=F40gxiYinenW+cm6aOgZ/x5eq1Jz1axR8fmmjJ+gQyk=; b=DSeFostlhJaNZRo6nqvuZnkTPP/YofHcKcciKXb7PISOP4jB041eY857P59aG269fQfv+V4NBOqKcOMXdV+y3TXI5cki5ZM7lQYYx4BiBKpQSNSXGA6RtCwUlDcHLduLwmZTNxQGw2g32AgNBawmnF0ZOPsm8mMNqOs9wOxuFOo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623772563971346.78460633561735; Tue, 15 Jun 2021 08:56:03 -0700 (PDT) Received: from localhost ([::1]:43672 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBQ2-0001R7-Sp for importer@patchew.org; Tue, 15 Jun 2021 11:56:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42888) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBF3-0005ug-4K for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:41 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:55864) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEc-0000wQ-6h for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:40 -0400 Received: by mail-wm1-x334.google.com with SMTP id c84so1675411wme.5 for ; Tue, 15 Jun 2021 08:44:13 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=F40gxiYinenW+cm6aOgZ/x5eq1Jz1axR8fmmjJ+gQyk=; b=L8Wwf3cWrYhKP2AOguzxjcP7vHVtUzFtdjVvCmaQHIQDKkyfpjQZulox4Hlv2RMyfK Jxi5oP9YdXuXxEiUNBsKiuNNWYmgrNpxEp0DeGRT2ZHsgTZ/5HkGH9srgyWC6n3Uj3Jp emseU5B1senj8jZR3bOdowlMtkU9EMx/yXhJkbFKk/K/4SBngiv3PheLRVjQSF9N6x6f JvtuSoIweKcP5/k2N20p0tHXSjWjlIB9SBFoVYwqf1op+6BnVOOjYzL8iDeSzYzKuHxl +kBVTHHTOBxhrHl8X8J0UlGwa7LrYVoHWdIWtDLaaLpkDsTf1Uysybimm+iXrNsyRf2G gUjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F40gxiYinenW+cm6aOgZ/x5eq1Jz1axR8fmmjJ+gQyk=; b=lMJnl+vktRV1CDBoG4XY9TLcKLBGYql/bJwFF1ztrF3sj2ju5q/wxn+BFpgaxzgPt6 g/mJ2XI8FZ2dTLjs/WAjEybWPGuULU67ixpFdywHjXdY7g/0vsr8cNjd78ZOnIFtden7 O892mV0I/50ZW+EWkahXRV86LhuHo+QHKD0FLmDpqzf2CNyMdKeBAS5LmF4ysxmoA5Mo 1Jfb/aDhDa+soX8wP+IR4wlD2cLsA9Df0k6sVqg4csO+TfPZd1kRfdHLIH0r/EtHBpCA rJWErFiDsClZzA4IFSMRaspYuhWw3MtYu57Y1B7fgtAWWgJY9Z43H6foHrL0ZCPKX13I vYGA== X-Gm-Message-State: AOAM533S4QzMVfur34o1WJxejznVe5Aq+Is+mZu0eI19DzZ3IdFoZcOM 7Ls8qt5cb2xDOaRFVgiKwW4hajN4mWpSsA== X-Google-Smtp-Source: ABdhPJyJnf6c8scSpRDpA49Ie6pck46YCx1Nwlp7+PKOk1axpUr1Yr46a2cb99sTLix36Q8VpaoHeA== X-Received: by 2002:a1c:1dd3:: with SMTP id d202mr23362508wmd.78.1623771852862; Tue, 15 Jun 2021 08:44:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/28] hw/arm: add quanta-gbs-bmc machine Date: Tue, 15 Jun 2021 16:43:43 +0100 Message-Id: <20210615154405.21399-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Patrick Venture Adds initial quanta-gbs-bmc machine support. Tested: Boots to userspace. Signed-off-by: Patrick Venture Reviewed-by: Brandon Kim Reviewed-by: Hao Wu Message-id: 20210608193605.2611114-2-venture@google.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/npcm7xx_boards.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 698be46d303..29026f0847b 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -29,6 +29,7 @@ =20 #define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7 #define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff +#define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff =20 static const char npcm7xx_default_bootrom[] =3D "npcm7xx_bootrom.bin"; =20 @@ -268,6 +269,22 @@ static void quanta_gsj_init(MachineState *machine) npcm7xx_load_kernel(machine, soc); } =20 +static void quanta_gbs_init(MachineState *machine) +{ + NPCM7xxState *soc; + + soc =3D npcm7xx_create_soc(machine, QUANTA_GBS_POWER_ON_STRAPS); + npcm7xx_connect_dram(soc, machine->ram); + qdev_realize(DEVICE(soc), NULL, &error_fatal); + + npcm7xx_load_bootrom(machine, soc); + + npcm7xx_connect_flash(&soc->fiu[0], 0, "mx66u51235f", + drive_get(IF_MTD, 0, 0)); + + npcm7xx_load_kernel(machine, soc); +} + static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *typ= e) { NPCM7xxClass *sc =3D NPCM7XX_CLASS(object_class_by_name(type)); @@ -316,6 +333,18 @@ static void gsj_machine_class_init(ObjectClass *oc, vo= id *data) mc->default_ram_size =3D 512 * MiB; }; =20 +static void gbs_bmc_machine_class_init(ObjectClass *oc, void *data) +{ + NPCM7xxMachineClass *nmc =3D NPCM7XX_MACHINE_CLASS(oc); + MachineClass *mc =3D MACHINE_CLASS(oc); + + npcm7xx_set_soc_type(nmc, TYPE_NPCM730); + + mc->desc =3D "Quanta GBS (Cortex-A9)"; + mc->init =3D quanta_gbs_init; + mc->default_ram_size =3D 1 * GiB; +} + static const TypeInfo npcm7xx_machine_types[] =3D { { .name =3D TYPE_NPCM7XX_MACHINE, @@ -332,6 +361,10 @@ static const TypeInfo npcm7xx_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("quanta-gsj"), .parent =3D TYPE_NPCM7XX_MACHINE, .class_init =3D gsj_machine_class_init, + }, { + .name =3D MACHINE_TYPE_NAME("quanta-gbs-bmc"), + .parent =3D TYPE_NPCM7XX_MACHINE, + .class_init =3D gbs_bmc_machine_class_init, }, }; =20 --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772299; cv=none; d=zohomail.com; s=zohoarc; b=eSD3tPpHYIzOIrTwr652jZEy2vTtXwxm/43NDfN6WKW5CNCmWqXci6ASChueB20hr04twO73FFUqUJlH/nA6TWcaGxoRCIRNTLTE7fNlHdQ2igeMR0Hda1XAEjZ3MXtI1jCiiVWJ45rvC2GntaKeieXt6Vo4l0o1HSrUZzkuOqM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623772299; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zVqxL3AKT7HZ7ZKqxjmZkK1Q7WRetlbNs3djp8Q49oc=; b=c2Kce2l0khpHuBwZEHa0pDsT7X7qlFaMveq+Q/zVmxNTEVpBx9d00lhTEAfOJhWGGFtcPWM4PmnQ+MQX3wujWR3g8JDJtDVdWtiaeU74jH23RQ1QnMd2SHev2k2JbdjEtE3msmo+5u/wkPWJWEmUAonZN/gYbZG61RGgZ+2LXKU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623772299621153.30423034025728; Tue, 15 Jun 2021 08:51:39 -0700 (PDT) Received: from localhost ([::1]:55316 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBLm-0007AL-Ij for importer@patchew.org; Tue, 15 Jun 2021 11:51:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42872) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBF1-0005t9-AK for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:40 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:37726) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEc-0000xC-PS for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:38 -0400 Received: by mail-wr1-x433.google.com with SMTP id i94so18825047wri.4 for ; Tue, 15 Jun 2021 08:44:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zVqxL3AKT7HZ7ZKqxjmZkK1Q7WRetlbNs3djp8Q49oc=; b=exA6F2u5xFVLcUOfrXk+GqsHeysJKzjbayqDgOmjKm8IziGMku+wc8skjM3PSSTJRY N3Y3bkmSEcJnxlO+qjfJSBVgmX9/1ZibjDkCvDuN+YBuiwylqxXf5nf86wPf2Ww1FwVV r97q8ph6I32WrDgx4lvEoIlvUKLGLZhgOicZTL4fGP94h7LSQ2FBOXjJcAKvc8mrCPyT oMfpOBJqr2znfq50rnu8DDTB7l0yfttELEJjqSIWwfySI4BQIBpef94y5CEwK81+cRPB MRJB2D/PwH23wRYNHuR4gbZCnMtxd92YPIfSEQ9cHn6EgMALj9WjyZuE/COY3IFAplf/ PLig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zVqxL3AKT7HZ7ZKqxjmZkK1Q7WRetlbNs3djp8Q49oc=; b=RT+CNO8eeriwbLZJMLjvJp6DABCre2y6XD12XJBU+j7sESh9lttr26Sv+enQTaI0YG 9LqcYm/VPELYe+YBwn6FCnt0y58ece9lWftbokloY2EWAGfqCu2bxsha+dxMyHgXpsA0 zWeRyhcKOD4FL/cKnzHmQDFUxe9Ak7x7DrIYhVZKNm5RyM9fiq1PMLYNw03e5AaclJk8 o/IJMcypbiWXwEBACdr6EF3RR/0kUg/hAQPv4A7Hdyu7Tw3BdkzZadc0lXyG1INEFW/6 R7CCVACj7doaOpF3Q9gas9v2qM1VYQelg1yv/+g6WvCidbimwOodbXDzQTrWRrwyFZaF mxsg== X-Gm-Message-State: AOAM53301bmPv/cWX/UtAQsOwAEEsGqFBfFRKtK4g8E+Lf4KBAUroj7m wV1Szpro81nyDUI4IorC76CHuq4leiBslQ== X-Google-Smtp-Source: ABdhPJwjnHZfUayo6+sIpCY5GyBzCr0whXqHzWyZlcCgETETMIwhBI/UwcyObY3Wnd/3Mw24ZFB/nA== X-Received: by 2002:a05:6000:2a3:: with SMTP id l3mr26056903wry.395.1623771853487; Tue, 15 Jun 2021 08:44:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/28] hw/arm: quanta-gbs-bmc add i2c comments Date: Tue, 15 Jun 2021 16:43:44 +0100 Message-Id: <20210615154405.21399-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Patrick Venture Add a comment and i2c method that describes the board layout. Tested: firmware booted to userspace. Signed-off-by: Patrick Venture Reviewed-by: Brandon Kim Reviewed-by: Hao Wu Message-id: 20210608193605.2611114-3-venture@google.com Signed-off-by: Peter Maydell --- hw/arm/npcm7xx_boards.c | 60 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 29026f0847b..bba23e24fae 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -238,6 +238,65 @@ static void quanta_gsj_fan_init(NPCM7xxMachine *machin= e, NPCM7xxState *soc) npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1); } =20 +static void quanta_gbs_i2c_init(NPCM7xxState *soc) +{ + /* + * i2c-0: + * pca9546@71 + * + * i2c-1: + * pca9535@24 + * pca9535@20 + * pca9535@21 + * pca9535@22 + * pca9535@23 + * pca9535@25 + * pca9535@26 + * + * i2c-2: + * sbtsi@4c + * + * i2c-5: + * atmel,24c64@50 mb_fru + * pca9546@71 + * - channel 0: max31725@54 + * - channel 1: max31725@55 + * - channel 2: max31725@5d + * atmel,24c64@51 fan_fru + * - channel 3: atmel,24c64@52 hsbp_fru + * + * i2c-6: + * pca9545@73 + * + * i2c-7: + * pca9545@72 + * + * i2c-8: + * adi,adm1272@10 + * + * i2c-9: + * pca9546@71 + * - channel 0: isil,isl68137@60 + * - channel 1: isil,isl68137@61 + * - channel 2: isil,isl68137@63 + * - channel 3: isil,isl68137@45 + * + * i2c-10: + * pca9545@71 + * + * i2c-11: + * pca9545@76 + * + * i2c-12: + * maxim,max34451@4e + * isil,isl68137@5d + * isil,isl68137@5e + * + * i2c-14: + * pca9545@70 + */ +} + static void npcm750_evb_init(MachineState *machine) { NPCM7xxState *soc; @@ -282,6 +341,7 @@ static void quanta_gbs_init(MachineState *machine) npcm7xx_connect_flash(&soc->fiu[0], 0, "mx66u51235f", drive_get(IF_MTD, 0, 0)); =20 + quanta_gbs_i2c_init(soc); npcm7xx_load_kernel(machine, soc); } =20 --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772440; cv=none; d=zohomail.com; s=zohoarc; b=M7PUWXTAfXl4fCEnR6BBE/d7bJbN7tT72EN83G7yDEx6sCQaZ7QzpFlfYXOVAvOE3owlw+YnE9d7Rjvnf50GO+PFyB/L/SLEnb47gWnlSormVZLtLdA529gd5x+ymDWUsbvCQHLkIlAcfN/7S/k/12HbbRfuEHugpl4JgiQbumY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623772440; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kXIsKDgX9ssnsNbMo4rVBql93KsOaMtjTcs6nFhPTv0=; b=FZ0QIDmQnJyT5Oz36IrqWalUSFvPdRIIXRg9N4NWeYUu+couJu/Em63m5EOp8KKXWsnzv2nMVAqzCgdFAB9If+1D7wqj6GE4mTjD5rGzagBUfAQTDvfA04Z8iigsn9ilfnFJXeHU3n0wTsCazDoyVY1XnRE7nTvfFbyTQkQKH54= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623772440238234.13826759865913; Tue, 15 Jun 2021 08:54:00 -0700 (PDT) Received: from localhost ([::1]:36138 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBO3-0004mX-21 for importer@patchew.org; Tue, 15 Jun 2021 11:53:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42922) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBF6-000619-E9 for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:46 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:38645) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEd-0000xf-IG for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:44 -0400 Received: by mail-wr1-x42c.google.com with SMTP id c9so18861900wrt.5 for ; Tue, 15 Jun 2021 08:44:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=kXIsKDgX9ssnsNbMo4rVBql93KsOaMtjTcs6nFhPTv0=; b=wTWhorC2Mi/M5zj1OeH0Zot59wbl8RdJLLmxXZN75Ny3JzSJcwmzhpYUUbm+XLzNJJ oCY1mDizSWoDS6ZODU2hjlInBJoBsvsZvBsCz9gxGUPs4xsc4zSd5ujkfcFWZb2D3JAE 5bwHhrJzU9fCw27mrcfUL/1GX+en39opeR5KUc8Qr62Li8igQ0HgDenUOMOnZetW9SDG xP1wdPQLa77p9uJEnqMvgKAjp0clGTpaPz18OkZCA5izvoOMu46r8xac2FedvWGJsK8K H4Xb3uuqMWN691rnRLvU+1yfJJUjS2L1fQ+Hb5+aVqaJyzztkVSDYIGLy6aUgZiqxY3W aGvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kXIsKDgX9ssnsNbMo4rVBql93KsOaMtjTcs6nFhPTv0=; b=NUGnROoiGi3S6wqVFjEQkEGiqF4gGjQ2DUA5MaA2PcSc+1KVKjRdR/1/FccBIkpopZ dZc3b30orW17VwB5aDQJdnDb7mvVx49MRZxjmZLu36xo+1I3YuOC3B39zAz3VJ29MeWi e2Wyqc/0vzchTY39uCxjZ8oINOn14cC9MIiXlywigwwovv6kAeVOpbPoDRLn2cURHhYG 38nfOudJzwTANtZlb/QyAHyfggm3PNUCSxdktYCNGML4iw/m0Tw1XEyZI0XMuH99LoBw IKSuma5U5jgCbxH5MOuTIXVTU5Q4NhIO78jp+0zm3htSttsZSH3PIf1TeLYUO+p2vBxJ 5dyA== X-Gm-Message-State: AOAM5329ffL6LIdF8c1dnuCDVQQf7iv9vPRPNvPadlKGC8RB4Mdaw921 C1w3lRJMTUUyA7kwVIPsPqTE1H7/axFk8g== X-Google-Smtp-Source: ABdhPJwCsVIBES18eqDIKoWf3yo6kLMEnoYCMx7yXZEjHwdfxV9bnlevWR3Cx+JIQ9lPolYW8f1whA== X-Received: by 2002:a5d:4c83:: with SMTP id z3mr26394549wrs.344.1623771854291; Tue, 15 Jun 2021 08:44:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/28] hw/intc/armv7m_nvic: Remove stale comment Date: Tue, 15 Jun 2021 16:43:45 +0100 Message-Id: <20210615154405.21399-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) In commit da6d674e509f0939b we split the NVIC code out from the GIC. This allowed us to specify the NVIC's default value for the num-irq property (64) in the usual way in its property list, and we deleted the previous hack where we updated the value in the state struct in the instance init function. Remove a stale comment about that hack which we forgot to delete at that time. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20210614161243.14211-1-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index c4287d82d81..94fe00235af 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2941,12 +2941,6 @@ static void armv7m_nvic_realize(DeviceState *dev, Er= ror **errp) =20 static void armv7m_nvic_instance_init(Object *obj) { - /* We have a different default value for the num-irq property - * than our superclass. This function runs after qdev init - * has set the defaults from the Property array and before - * any user-specified property setting, so just modify the - * value in the GICState struct. - */ DeviceState *dev =3D DEVICE(obj); NVICState *nvic =3D NVIC(obj); SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772893; cv=none; d=zohomail.com; s=zohoarc; b=m03jfXsPQUC+mazJgUUnpQYQt2SPi76PryRpOaN+COhHsub+bFUVrSQ+fC5L+2HTGSTgnf0RjwbnVfxMjAfhkFWVxtOwMPan+nVxEreTpELTPq44Bp6XtumYsCCFD+foCyBriv+8RxxZZlsii31o8hFsbg1HW02lhN0u3XY/iYM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623772893; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cyCGn2SVLHm0FcqfG3WrqBeex+FwY6W9NPYT/ExK5rY=; b=BrPO2L+cDRJlnc4R7Xn+g7I/MBRZqSq/7wFmv6nyquXvu8Yg8MrT7w4oVTEFdNy/lhZPCofp0blPiA8rILPdq0fAfdgB8+nAlWCl3UF0GNeIVUvzbPC81yWwn6s4oqbnUxnpGV+u2RrdI281n7vQvPpVbKa5D34jrl7PveAomQ0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623772893588125.38002617341931; Tue, 15 Jun 2021 09:01:33 -0700 (PDT) Received: from localhost ([::1]:33130 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBVK-0004xF-Qd for importer@patchew.org; Tue, 15 Jun 2021 12:01:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42968) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBFB-0006Ga-UA for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:50 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:45704) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEh-0000xt-VD for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:49 -0400 Received: by mail-wr1-x429.google.com with SMTP id z8so18868468wrp.12 for ; Tue, 15 Jun 2021 08:44:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cyCGn2SVLHm0FcqfG3WrqBeex+FwY6W9NPYT/ExK5rY=; b=RTIRZkFXYwNRvr8zYxRg40Y8AOx9ZvebiiHfTdf+WNE/8v2d2mQINPgeNMiqlIS+4+ xvKQSKTp2L3CNnojzSunMCWUm9wVS1FG8bV/9v4xrYgY96UaSD3u81jL3MRO/+qKJ9f8 Hs9PFKZ51gq2+hmBxzWFrhDzNGPYalQPj0lpNnbHa0Gsu66lzepp/AN6KUmYlN8FyuDM OvA8vFGPzKLR8XcVa3GQJRqRvcvuET/a3WmSosLgmdBeysJ/FcoxgiyPptpIBIWsk2Qm PKOprDccOu+Zz7v1wS9H37Km0z1Ql4SrqDQ9sRkEqPFMA8stBaqz00ROAAgZdA//3OJR FY3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cyCGn2SVLHm0FcqfG3WrqBeex+FwY6W9NPYT/ExK5rY=; b=PKq8huM7pJhrRzK3ufomfmnEs9wQ9r8ClB1TRErnBMHD48Q/yMpF9FykiQla+GhY1w B5d+XNcIPx96rfOyi8UJmz99YTssl/+k8GeMf28CaYHCRsSdSkfJLjT8oLj1maUaVX4T Ib6obOErh5f5yFjxGl8D3CTX1rpoTjJTjV/YBMi1bpasAfY++B16VnZ92nTcDjgILVkD I1pgku+fCN76E9/detdUe+vFRKoeOfDqOXAzoe7PcFbJdGjVS3jstMrpVMrr0FGWPOww flZMURdoqqWxks1OblbJG6CqaJK+GjhECiG+SArErG1OEwKw9mcFjClsl1AzJxDK+tN8 azsA== X-Gm-Message-State: AOAM531ZTKXyv0DjgZ9typYi2wmVLDrEJD4ARWbhrgBkljbqeo8WmYm6 4D/J/bK50DslrXDRqllyEesbFDYBfovlPg== X-Google-Smtp-Source: ABdhPJwo0t32WImYpQgkf4EnBqsqWHkbWoEUH11KK19J7SgEIqkf6MSHE3i8EBTKRC4ptYXbMTM+sA== X-Received: by 2002:adf:bd88:: with SMTP id l8mr25816320wrh.90.1623771854899; Tue, 15 Jun 2021 08:44:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/28] hw/acpi: Provide stub version of acpi_ghes_record_errors() Date: Tue, 15 Jun 2021 16:43:46 +0100 Message-Id: <20210615154405.21399-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Generic code in target/arm wants to call acpi_ghes_record_errors(); provide a stub version so that we don't fail to link when CONFIG_ACPI_APEI is not set. This requires us to add a new ghes-stub.c file to contain it and the meson.build mechanics to use it when appropriate. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Dongjiu Geng Message-id: 20210603171259.27962-2-peter.maydell@linaro.org --- hw/acpi/ghes-stub.c | 17 +++++++++++++++++ hw/acpi/meson.build | 6 +++--- 2 files changed, 20 insertions(+), 3 deletions(-) create mode 100644 hw/acpi/ghes-stub.c diff --git a/hw/acpi/ghes-stub.c b/hw/acpi/ghes-stub.c new file mode 100644 index 00000000000..9faba043b85 --- /dev/null +++ b/hw/acpi/ghes-stub.c @@ -0,0 +1,17 @@ +/* + * Support for generating APEI tables and recording CPER for Guests: + * stub functions. + * + * Copyright (c) 2021 Linaro, Ltd + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/acpi/ghes.h" + +int acpi_ghes_record_errors(uint8_t source_id, uint64_t physical_address) +{ + return -1; +} diff --git a/hw/acpi/meson.build b/hw/acpi/meson.build index dd69577212a..03ea43f8627 100644 --- a/hw/acpi/meson.build +++ b/hw/acpi/meson.build @@ -13,13 +13,13 @@ acpi_ss.add(when: 'CONFIG_ACPI_PCI', if_true: files('pc= i.c')) acpi_ss.add(when: 'CONFIG_ACPI_VMGENID', if_true: files('vmgenid.c')) acpi_ss.add(when: 'CONFIG_ACPI_HW_REDUCED', if_true: files('generic_event_= device.c')) acpi_ss.add(when: 'CONFIG_ACPI_HMAT', if_true: files('hmat.c')) -acpi_ss.add(when: 'CONFIG_ACPI_APEI', if_true: files('ghes.c')) +acpi_ss.add(when: 'CONFIG_ACPI_APEI', if_true: files('ghes.c'), if_false:(= 'ghes-stub.c')) acpi_ss.add(when: 'CONFIG_ACPI_X86', if_true: files('core.c', 'piix4.c', '= pcihp.c'), if_false: files('acpi-stub.c')) acpi_ss.add(when: 'CONFIG_ACPI_X86_ICH', if_true: files('ich9.c', 'tco.c')) acpi_ss.add(when: 'CONFIG_IPMI', if_true: files('ipmi.c'), if_false: files= ('ipmi-stub.c')) acpi_ss.add(when: 'CONFIG_PC', if_false: files('acpi-x86-stub.c')) acpi_ss.add(when: 'CONFIG_TPM', if_true: files('tpm.c')) -softmmu_ss.add(when: 'CONFIG_ACPI', if_false: files('acpi-stub.c', 'aml-bu= ild-stub.c')) +softmmu_ss.add(when: 'CONFIG_ACPI', if_false: files('acpi-stub.c', 'aml-bu= ild-stub.c', 'ghes-stub.c')) softmmu_ss.add_all(when: 'CONFIG_ACPI', if_true: acpi_ss) softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('acpi-stub.c', 'aml-buil= d-stub.c', - 'acpi-x86-stub.c', 'ipmi= -stub.c')) + 'acpi-x86-stub.c', 'ipmi= -stub.c', 'ghes-stub.c')) --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623773054; cv=none; d=zohomail.com; s=zohoarc; b=ntnDG3+VYhAeDEFxrikM6lX2+wYf22hi9+qKn27s8DRe7hHd3fTChXv3AOa8GcRpNpKO+G83zcwBXCGqfZ2jnWL8k6iKC8Rqj12O0XmBgStR5b1taXe+4pkqntqFJPfqDdQjt7deU+vhQt3pOsdaAxnfkKNTKKMtfcNuyLWoLIk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623773054; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mBhVixobv9evawUK2zvyZAJjFLCIliw3J90zk8FNS6M=; b=BYjmUDffdMEg7C5VcxoTft1eSL7LYtG7iLzPzPDyJ2UHyJp329Y3FvftB1jXd3yldk1RvD3MCrive3AhP5MU0K9+Lz7SMWwIqsQX+3JTS+m5aVkWBGA/nILYqahk1WqL64sPFcQssoE/epJgmJdyJvFFjsNbNdgLi0DYIhpI5Js= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623773054732140.39072514518193; Tue, 15 Jun 2021 09:04:14 -0700 (PDT) Received: from localhost ([::1]:41448 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBXx-0002T6-M4 for importer@patchew.org; Tue, 15 Jun 2021 12:04:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43006) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBFD-0006OC-S0 for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:51 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:37729) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEh-0000y6-Vs for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:51 -0400 Received: by mail-wr1-x436.google.com with SMTP id i94so18825167wri.4 for ; Tue, 15 Jun 2021 08:44:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=mBhVixobv9evawUK2zvyZAJjFLCIliw3J90zk8FNS6M=; b=Ytl6PqvZFuG4eCCcKPL7zweCPxKeDN54WUrgZrIAipFt/X2nmp/mXtLGGkL8nX6Ndg S2kP7//1GWevXRqjqc4/vQFYiwpoP5exNoJP79ACfb7qLhuAchGlfD4r2+NK1TFXGrAn L79Asnk9IYtV6pwUF1L3Mo6Tm+Ndy6czNENrHfhz2LKF1ggPQHrDU2acxscLs06OOA+2 fh1Uk/6a8rcW3wtUJoBSI4UQ+Ki3/FdjQeEvLaitbtF0ZYnCaCvu7BVOEvj9RY/N+vRj cDozlvXX0gamG3s6dEVZKRliUdD6uzMFrKu/XZGgBthd7m0mqqz35cWGRwhvmWgtbRSH TGxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mBhVixobv9evawUK2zvyZAJjFLCIliw3J90zk8FNS6M=; b=Nwfi47XwLL5WRyNuGmbm6noebSDUN+z3zyFY1moAMlO/sNIxzb/1jLq1Qur0AMGVZY WxC8STu71JDntUJIN3RTQGosw8mujlDoKmzAsal5iRijDQ6ngbVFvdCEudQvuK/HZ5AQ GUGVzI3RjvCEb4i2+d/tBJ5rJ2vD7NJfG9gyp6kBMazyW+G39jfNuoXQcD6mM6+avLn2 FyEazlc/NTMVu4VERwVmY722aS9GMPq1/6RwZ6DEyYPBZe7cuZ7NPdiKwvPWusuPQ5xX kiNitTCPuhSZoNdbjUMScNrGuVaWYdty8ys06WbzCwXsWA9/5UOcMXKvHE69TuvO0z0z 2yTw== X-Gm-Message-State: AOAM530iNv5BuSPbcT07qEuLNJH+o9kDSDYBJ8DVlimIvKXjDSokLOl7 DJSyL7U4Qh3wQKjuC87/MtBVwVYgrTON4Q== X-Google-Smtp-Source: ABdhPJzNT8utgfpfDdfvxwZ8Nvpt85j7miECx9lNEh52pxj7KHxxutR+OzrPGCf46hQYIfHJdgdDVg== X-Received: by 2002:adf:e0c7:: with SMTP id m7mr27092891wri.409.1623771855489; Tue, 15 Jun 2021 08:44:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/28] hw/acpi: Provide function acpi_ghes_present() Date: Tue, 15 Jun 2021 16:43:47 +0100 Message-Id: <20210615154405.21399-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Allow code elsewhere in the system to check whether the ACPI GHES table is present, so it can determine whether it is OK to try to record an error by calling acpi_ghes_record_errors(). (We don't need to migrate the new 'present' field in AcpiGhesState, because it is set once at system initialization and doesn't change.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Dongjiu Geng Message-id: 20210603171259.27962-3-peter.maydell@linaro.org --- include/hw/acpi/ghes.h | 9 +++++++++ hw/acpi/ghes-stub.c | 5 +++++ hw/acpi/ghes.c | 17 +++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h index 2ae8bc1ded3..674f6958e90 100644 --- a/include/hw/acpi/ghes.h +++ b/include/hw/acpi/ghes.h @@ -64,6 +64,7 @@ enum { =20 typedef struct AcpiGhesState { uint64_t ghes_addr_le; + bool present; /* True if GHES is present at all on this board */ } AcpiGhesState; =20 void build_ghes_error_table(GArray *hardware_errors, BIOSLinker *linker); @@ -72,4 +73,12 @@ void acpi_build_hest(GArray *table_data, BIOSLinker *lin= ker, void acpi_ghes_add_fw_cfg(AcpiGhesState *vms, FWCfgState *s, GArray *hardware_errors); int acpi_ghes_record_errors(uint8_t notify, uint64_t error_physical_addr); + +/** + * acpi_ghes_present: Report whether ACPI GHES table is present + * + * Returns: true if the system has an ACPI GHES table and it is + * safe to call acpi_ghes_record_errors() to record a memory error. + */ +bool acpi_ghes_present(void); #endif diff --git a/hw/acpi/ghes-stub.c b/hw/acpi/ghes-stub.c index 9faba043b85..c315de1802d 100644 --- a/hw/acpi/ghes-stub.c +++ b/hw/acpi/ghes-stub.c @@ -15,3 +15,8 @@ int acpi_ghes_record_errors(uint8_t source_id, uint64_t p= hysical_address) { return -1; } + +bool acpi_ghes_present(void) +{ + return false; +} diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c index a4dac6bf15e..a749b84d624 100644 --- a/hw/acpi/ghes.c +++ b/hw/acpi/ghes.c @@ -386,6 +386,8 @@ void acpi_ghes_add_fw_cfg(AcpiGhesState *ags, FWCfgStat= e *s, /* Create a read-write fw_cfg file for Address */ fw_cfg_add_file_callback(s, ACPI_GHES_DATA_ADDR_FW_CFG_FILE, NULL, NUL= L, NULL, &(ags->ghes_addr_le), sizeof(ags->ghes_addr_le), false); + + ags->present =3D true; } =20 int acpi_ghes_record_errors(uint8_t source_id, uint64_t physical_address) @@ -443,3 +445,18 @@ int acpi_ghes_record_errors(uint8_t source_id, uint64_= t physical_address) =20 return ret; } + +bool acpi_ghes_present(void) +{ + AcpiGedState *acpi_ged_state; + AcpiGhesState *ags; + + acpi_ged_state =3D ACPI_GED(object_resolve_path_type("", TYPE_ACPI_GED, + NULL)); + + if (!acpi_ged_state) { + return false; + } + ags =3D &acpi_ged_state->ghes_state; + return ags->present; +} --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772618; cv=none; d=zohomail.com; s=zohoarc; b=ONIRkHiLydZP24T2OEoFRt96xL+8S7sj5r2LyiOyGHHxsTofX0BNb7Ek/CtNjjG7b37FRmUNCDfHXsMIJC88Ewn4krNEe3SgyP9z+qrQJYUaZ4IjVoHj5ysrNo8JwBbGQ8qtJVwSswZ0AJ+n9CsbcbgENg48dxDK0fW7oa/F97w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623772618; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ye94kK+c9X5Qdb3oLfHimMsgJSBTnBwqNDEcye+BmeI=; b=VAv3UhRX0U1Nw2coy25Sr/s3u/pApNfexd0ZmiIak7GoDG8tsa95pw4AWxYn5GaltDuKqb+jsHSnE6oQ4D7W0dbPaL5H0gP1EjZiHGRfILqSoBJkIz2x/bHwHrzNPltjaFlbLxqGZG2kZDKU+G1nWf6GF0R9U3xWpNak/wj/0Os= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623772618536902.2688052868181; Tue, 15 Jun 2021 08:56:58 -0700 (PDT) Received: from localhost ([::1]:48166 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBQv-0004PK-B0 for importer@patchew.org; Tue, 15 Jun 2021 11:56:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42954) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBFB-0006Dx-7C for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:49 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:50721) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEi-0000yI-6w for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:48 -0400 Received: by mail-wm1-x32d.google.com with SMTP id d184so14438759wmd.0 for ; Tue, 15 Jun 2021 08:44:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Ye94kK+c9X5Qdb3oLfHimMsgJSBTnBwqNDEcye+BmeI=; b=zUDKzUg96lKBS+ea+oADsB4zFQev42TOYH+3dADxqndLJ7Rf4CdvGIxA8Is4/GftuI xFVRGHNXs+m3M3D/2bUtx+c1112aBeQMdO0DYmfUaOvhkE+qO8k/695TTFAebTSLQUSi IM6GX+bEu5kt6UTJVo+b1n4mBsKU/S4uDDmUn56XFUSGmra0CyTrNBDrQ+zLN9XpAPhq /Y5ePIwzzzi6hSYxom/fbkjzfGoEq7QREzFoRuuJlTWqDtZtn16DGXkCFyqGOeIdbMJN Gw+SIWfdU+R5MDWxggBz8DfnEcTdCaJvRd5v6JpfEkDUxYFztJF5ADkyuKs+4zlhZXLx 2tBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ye94kK+c9X5Qdb3oLfHimMsgJSBTnBwqNDEcye+BmeI=; b=h2luqmh84McoYyt5h3yTuTPNtmav4wJGV7FR6Q97tLs7a6c2L6zA2V/CJc0ZkiBUw5 sxncJaDXaW/hWCpaZ7r9qmH1qw15waKPrY0ASfVTKtLVXMypnxSXMiPUmAVgHqO0fFcB W/M4nO0onY5TS5DmX4tr6icbzTzPwjcFCCEOEjpEQE8PR8jdf/WGr8wPE2x0C1Ff6aVO Sp5/tRJu7PjUFjqnNvwCQUL/il4wQeJ2QpeBeYMP7oETxlgwV8rN0ZpB4psTDSCJHNp+ 22lKdb/AokP4Wogy9uPglbf9k/9XKQY5YlDJjCRaUXcS80mCQsydf45FJSPqikDUoz2Y m9rA== X-Gm-Message-State: AOAM532jgytpf0h0uH9OEbOygDvg1iazmgSlmhC0C/X5OHVSuJHyJ2nB R3ppXVfYo4OV0WHb2wPjB0mfMXoaqMSHHw== X-Google-Smtp-Source: ABdhPJws+trw+0vA78ec/xTdEX7WApxcph8AUN3eizGIguDtypMceNG4ns9YUSAbiUaj5Rrez/TUVg== X-Received: by 2002:a7b:cde1:: with SMTP id p1mr5846719wmj.13.1623771856066; Tue, 15 Jun 2021 08:44:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/28] target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors Date: Tue, 15 Jun 2021 16:43:48 +0100 Message-Id: <20210615154405.21399-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The virt_is_acpi_enabled() function is specific to the virt board, as is the check for its 'ras' property. Use the new acpi_ghes_present() function to check whether we should report memory errors via acpi_ghes_record_errors(). This avoids a link error if QEMU was built without support for the virt board, and provides a mechanism that can be used by any future board models that want to add ACPI memory error reporting support (they only need to call acpi_ghes_add_fw_cfg()). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Dongjiu Geng Message-id: 20210603171259.27962-4-peter.maydell@linaro.org --- target/arm/kvm64.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 37ceadd9a9d..59982d470d3 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -1410,14 +1410,10 @@ void kvm_arch_on_sigbus_vcpu(CPUState *c, int code,= void *addr) { ram_addr_t ram_addr; hwaddr paddr; - Object *obj =3D qdev_get_machine(); - VirtMachineState *vms =3D VIRT_MACHINE(obj); - bool acpi_enabled =3D virt_is_acpi_enabled(vms); =20 assert(code =3D=3D BUS_MCEERR_AR || code =3D=3D BUS_MCEERR_AO); =20 - if (acpi_enabled && addr && - object_property_get_bool(obj, "ras", NULL)) { + if (acpi_ghes_present() && addr) { ram_addr =3D qemu_ram_addr_from_host(addr); if (ram_addr !=3D RAM_ADDR_INVALID && kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)= ) { --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772427; cv=none; d=zohomail.com; s=zohoarc; b=RxhDb5hM0QxSar/LG/6yqpsMhtVlfckPhQTcZKxb03LNO7euWwyzFCscWlM/zSmHsUy9HdLR7/WKx9GGyyVjv88A48+0cv2lmvFMoMod07TtH8D6PAU6I78bk4g2khFP4OkUe7VR61sEsAEcBbPERxUI+/CxncFHLT1x6sY/Q6o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623772427; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=j0k9xnVMNuLNWBt5G9Ow8Dce+nq2YR61kkHpX3kHo9I=; b=Uc4lJOEWZb+vljHuibeJgsJrCCv1Co17YiBx7tfFxOneoQfpbc08auHiZVr/HGEa8VM4bkFWb3dNnq/YIhAs7f5ythzabPu3+4bsJsxtW/9veNwcpKjm0zod4LD4BhG0bncDl3qJ+Pdje2eyUnUW9r4ZzCXU9H+lYwshH+xP9b4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623772427766963.5859193413967; Tue, 15 Jun 2021 08:53:47 -0700 (PDT) Received: from localhost ([::1]:35008 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBNq-00041N-Bq for importer@patchew.org; Tue, 15 Jun 2021 11:53:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42944) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBF9-00066v-G7 for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:47 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:39610) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEh-0000yP-Vs for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:47 -0400 Received: by mail-wr1-x436.google.com with SMTP id v9so2581637wrx.6 for ; Tue, 15 Jun 2021 08:44:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=j0k9xnVMNuLNWBt5G9Ow8Dce+nq2YR61kkHpX3kHo9I=; b=vaiow/XCcqTTv4j3798VFKKrpiQb2ABddryKZ+FBEksSgBu/uL4y2awaCzaNqMWx5s WR3ez0D22npV6LfHEohA2BxU1j4BqFqjguFW36HLQ3jKWtbB6WJupCLhaqj9IcUgGvJ5 YAQOdPICdwqdAgdzYshCkiHiUjRPW2TyHAyoqRGHHxmzORCk5L3vymJFwe8lu5Y1peSs NkHo5BKMB0oi0qlYQcI+k40w+G6SDzXVLx7ZuYi8bLe0peOWu4p751RNHKrAIubBGHNV 0pu2Wi/cjC1eLdh8OFcXv+5KN0QOCsU+Unrpk0Pm0wo54WSWKSaLyJxxaZDcfR7ltvFY aiXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=j0k9xnVMNuLNWBt5G9Ow8Dce+nq2YR61kkHpX3kHo9I=; b=RfCKLRr9RK4ebawcwhjPc5xwot4lN3QIpzO4NOTBBcNJrJBtS1cHTSHMP876FdTCVz iEG5e2Unk6FSMcUxVuRjdk+OD6xm06Ck8N8r145fQiIbXnrkYxQeZQMddJ4vf3oIye+E zdY++SwyC9go74yinZKOLxureS3+lSf1TdKoVF140RyDfe7ADuui2JmDHG7FZDUY5uXe Vq9UQuK/OFEPgkw3YKFFfq6AYTfxfIa6RjkHlP51sJJxMgJJf9qAEiDpicrtMiPs63Hb JDSTB0c+2vohNVg+yOjkmxT4xdDYw1LW6SfV3xebap6mxuLWtRbAvDdmI9za7GE2Fbgz 0fdA== X-Gm-Message-State: AOAM533N1IMDiWbLs2X+DE75FtRkVh1uflUq3z1PGDb8vH+lUh7xP+7y zfLg6wg1NjcQ93oFJg4ZVbRtxkdkgAeh8Q== X-Google-Smtp-Source: ABdhPJzgyAlNqF+Ow3LNK1HKgcnDzAn5a/5ACSGYlhN5Ixl7RYEVmyYNiNsTSWAOicBekNnooSerVg== X-Received: by 2002:a5d:4401:: with SMTP id z1mr26399333wrq.149.1623771856693; Tue, 15 Jun 2021 08:44:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/28] target/arm: Fix mte page crossing test Date: Tue, 15 Jun 2021 16:43:49 +0100 Message-Id: <20210615154405.21399-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson The test was off-by-one, because tag_last points to the last byte of the tag to check, thus tag_last - prev_page will equal TARGET_PAGE_SIZE when we use the first byte of the next page. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/403 Reported-by: Peter Collingbourne Signed-off-by: Richard Henderson Message-id: 20210612195707.840217-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/mte_helper.c | 2 +- tests/tcg/aarch64/mte-7.c | 31 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 2 +- 3 files changed, 33 insertions(+), 2 deletions(-) create mode 100644 tests/tcg/aarch64/mte-7.c diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 166b9d260f8..9e615cc513c 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -730,7 +730,7 @@ static int mte_probe_int(CPUARMState *env, uint32_t des= c, uint64_t ptr, prev_page =3D ptr & TARGET_PAGE_MASK; next_page =3D prev_page + TARGET_PAGE_SIZE; =20 - if (likely(tag_last - prev_page <=3D TARGET_PAGE_SIZE)) { + if (likely(tag_last - prev_page < TARGET_PAGE_SIZE)) { /* Memory access stays on one page. */ tag_size =3D ((tag_byte_last - tag_byte_first) / (2 * TAG_GRANULE)= ) + 1; mem1 =3D allocation_tag_mem(env, mmu_idx, ptr, type, sizem1 + 1, diff --git a/tests/tcg/aarch64/mte-7.c b/tests/tcg/aarch64/mte-7.c new file mode 100644 index 00000000000..a981de62d4a --- /dev/null +++ b/tests/tcg/aarch64/mte-7.c @@ -0,0 +1,31 @@ +/* + * Memory tagging, unaligned access crossing pages. + * https://gitlab.com/qemu-project/qemu/-/issues/403 + * + * Copyright (c) 2021 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "mte.h" + +int main(int ac, char **av) +{ + void *p; + + enable_mte(PR_MTE_TCF_SYNC); + p =3D alloc_mte_mem(2 * 0x1000); + + /* Tag the pointer. */ + p =3D (void *)((unsigned long)p | (1ul << 56)); + + /* Store tag in sequential granules. */ + asm("stg %0, [%0]" : : "r"(p + 0x0ff0)); + asm("stg %0, [%0]" : : "r"(p + 0x1000)); + + /* + * Perform an unaligned store with tag 1 crossing the pages. + * Failure dies with SIGSEGV. + */ + asm("str %0, [%0]" : : "r"(p + 0x0ffc)); + return 0; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index 928357b10a9..2c05c90d170 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -37,7 +37,7 @@ AARCH64_TESTS +=3D bti-2 =20 # MTE Tests ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_ARMV8_MTE),) -AARCH64_TESTS +=3D mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 +AARCH64_TESTS +=3D mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-7 mte-%: CFLAGS +=3D -march=3Darmv8.5-a+memtag endif =20 --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772696; cv=none; d=zohomail.com; s=zohoarc; b=Vt4vpi3N+BioIdYmaiSqOIauw3euW7Etl1AQa7ExxfIrBt+vwozmVrCzu7x4MXjM7zYPNPyVCkw3pl0obD2iQUQ2D+rApZQHmiLRYRPq11OPY5sbqlFdn/VQGSvK3TmVYxc2/jSBh75vHeTlywsw46hG5LMzqPciNindJp6twPk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623772696; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ETK4THhT3bIw5g337eKbOGWg2S9a5ypkXL0/WklkD8s=; b=cODvZSqfbb0i2XFVlXOXSq127x0SkAEotciAmyiGrKrObkD416/s++oR6YGoD6spDB6bRc/PW+eUQOPK59tgKRauooDY87hDt5XBhs9/O4VHbQmMYcEzRq3XK2zF74dZy9fF+kYw9zNtGlnA1hTQBhQQ1CwAd64fwOkDQOqUovw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623772696506526.5010528221791; Tue, 15 Jun 2021 08:58:16 -0700 (PDT) Received: from localhost ([::1]:52712 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBSB-0007R8-3C for importer@patchew.org; Tue, 15 Jun 2021 11:58:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42962) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBFB-0006GP-OP for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:50 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:35333) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEi-0000yR-86 for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:49 -0400 Received: by mail-wr1-x431.google.com with SMTP id m18so18854080wrv.2 for ; Tue, 15 Jun 2021 08:44:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ETK4THhT3bIw5g337eKbOGWg2S9a5ypkXL0/WklkD8s=; b=cjwfLoZ63OQ0FOWBCg2j9CIPkRBVwhRc5lTF9KsLnwbr5Jm3B8+CYwuT85gBHehCUd nonEhsZxfeNOgSiJoPTpF7NEsJ8ZDnELWIF4RkzbgLUKBhb4EE8ksHuzJeY05ZVYbEAM 8FnlOCk/zFiAgJzPkBg8++/0KCEXuYKHlVd298/dqmqwxCq3W4HTfJbqqj7si2g+bDYA uOz5GMaUxK4//xUEp3XHFGvQukfG5FV1ZrA1zt91AqZhs39a2qwpWBJOBa/o5AOvkPSI YlZiaGvEncH5h7ni01PDReym8R3u4zc2rV24r3vkMEGKLumsoFKczcZoM7bU5cUmqOyg w0VQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ETK4THhT3bIw5g337eKbOGWg2S9a5ypkXL0/WklkD8s=; b=ttubV9IHUo/NdSTPDRUz7q74Bov0n94hAZLYYpgj0PnjxZN+iqvzCD1kfmlFdK/3jn UfbdCxWzGSdsrp8bNZLR8tczhSPeiJmR/BYoYKXIcBJoFRg1qaJHP/P7Llyck/NmDV6W JqV+HK6mLBSjWP/D+GepiVpzmDucpnCvinPF4PqAtSPgRwYiW0jWv6i084X/8vMXEaxX fO5CfvdcFABpvDwW9zRyFU6b8AOarny2xlGfTLsI71fFAGBihxTeXeK0amsbAS5O6eEK dZhpK/u6D1lO9wCbnvSjTwzxKilT4IIJagdEUNj69qyKJ5TOOO7/jkohFb0fescHDT2R DWVA== X-Gm-Message-State: AOAM533pvDS08yaK7jbff1XgkQ7YAP7juoetWr1wKbe7b/zCOBC6ylHS OkQ40w59qtfL71xfCmw1E99SKzmti9Z32Q== X-Google-Smtp-Source: ABdhPJzfEAoleojNWV/hTLb5QLJmJvdogzjCKOWd7E2T2xq5XBX3Blyml59dUphm/l6eA7EfxWQq8A== X-Received: by 2002:adf:ff88:: with SMTP id j8mr26068280wrr.10.1623771857341; Tue, 15 Jun 2021 08:44:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/28] hw/arm: gsj add i2c comments Date: Tue, 15 Jun 2021 16:43:50 +0100 Message-Id: <20210615154405.21399-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Patrick Venture Adds comments to the board init to identify missing i2c devices. Signed-off-by: Patrick Venture Reviewed-by: Hao Wu Reviewed-by: Joel Stanley Message-id: 20210608202522.2677850-2-venture@google.com Signed-off-by: Peter Maydell --- hw/arm/npcm7xx_boards.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index bba23e24fae..eed0da71b8a 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -221,7 +221,21 @@ static void quanta_gsj_i2c_init(NPCM7xxState *soc) at24c_eeprom_init(soc, 9, 0x55, 8192); at24c_eeprom_init(soc, 10, 0x55, 8192); =20 - /* TODO: Add additional i2c devices. */ + /* + * i2c-11: + * - power-brick@36: delta,dps800 + * - hotswap@15: ti,lm5066i + */ + + /* + * i2c-12: + * - ucd90160@6b + */ + + /* + * i2c-15: + * - pca9548@75 + */ } =20 static void quanta_gsj_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc) --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772290; cv=none; d=zohomail.com; s=zohoarc; b=jOCIqGryxgs1dj+J6IMYvA9jj9sAhVpwDhK5QbXFzXywZtjb9wmLEFEXCNBYUmgJbWUdBPw9akSRVikyakQXtnFJiVGwdbu+2KvdAeYx5QQoiliNgGaGNHLNpc2cXhdya2hNOzzLhAk6Su5euErjaa5U3j+WX7XvSXu2g6B6pSE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623772290; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CEA7FSbLGi5A6kATzg2rxoWerCKV1VDUeDfHJ0mPSiY=; b=GazoR+Q5fOBG54fIFbx7KMNe/O9jtANyaQEHS4Z4Ks7HkTBIb8TImFbKvlm42szxMO7od8ZDpcccr+mqFT7XV4uNHaB6pPIRaVgZBqdQH5F+jXPF+16axN3tiGApNyXyjee1U9O1rWFsR+d+ynK+a4SZTAMfIuXLEbGwFXfAWuM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623772290099933.8940555620862; Tue, 15 Jun 2021 08:51:30 -0700 (PDT) Received: from localhost ([::1]:54340 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBLc-0006Rz-V1 for importer@patchew.org; Tue, 15 Jun 2021 11:51:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42984) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBFC-0006JJ-MT for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:50 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:43956) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEh-0000yV-Vb for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:50 -0400 Received: by mail-wr1-x42e.google.com with SMTP id r9so18878688wrz.10 for ; Tue, 15 Jun 2021 08:44:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CEA7FSbLGi5A6kATzg2rxoWerCKV1VDUeDfHJ0mPSiY=; b=aISUVBwpi2rod3map28H3xJjU9CVW0IN0FturDGPMEVJLhU2UaIqog1xrJdnMyzntz eGLkVGEeYXvWeug0hqvaDCYNg9Glw3F9MXcj/pzf7FKj6bKK3b6Pu9oyTkdzHEArcRfB SCeUk87ANSrg3RJfJMy5bQ6nEIoIostpBsC3i6Cb/vqsr5GTx2txHsvq4TuF5LCVoNzJ JgN5GyNwQVPzV6PkaBqIgs9EWJVlrG5G0OtUa8yrPiekpkk24KluULG+itGuCyrtXaal WyfZ7n2sf3w+5+bUWfGzf30ImhbMgrn5q/Bm1R3tqzzjEQXpC08HtIwYuvuESIKqyvx/ 4Ohg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CEA7FSbLGi5A6kATzg2rxoWerCKV1VDUeDfHJ0mPSiY=; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Patrick Venture Tested: Quanta-gsj firmware booted. i2c /dev entries driver I2C init bus 1 freq 100000 I2C init bus 2 freq 100000 I2C init bus 3 freq 100000 I2C init bus 4 freq 100000 I2C init bus 8 freq 100000 I2C init bus 9 freq 100000 at24 9-0055: 8192 byte 24c64 EEPROM, writable, 1 bytes/write I2C init bus 10 freq 100000 at24 10-0055: 8192 byte 24c64 EEPROM, writable, 1 bytes/write I2C init bus 12 freq 100000 I2C init bus 15 freq 100000 i2c i2c-15: Added multiplexed i2c bus 16 i2c i2c-15: Added multiplexed i2c bus 17 i2c i2c-15: Added multiplexed i2c bus 18 i2c i2c-15: Added multiplexed i2c bus 19 i2c i2c-15: Added multiplexed i2c bus 20 i2c i2c-15: Added multiplexed i2c bus 21 i2c i2c-15: Added multiplexed i2c bus 22 i2c i2c-15: Added multiplexed i2c bus 23 pca954x 15-0075: registered 8 multiplexed busses for I2C switch pca9548 Signed-off-by: Patrick Venture Reviewed-by: Hao Wu Reviewed-by: Joel Stanley Message-id: 20210608202522.2677850-3-venture@google.com Signed-off-by: Peter Maydell --- hw/arm/npcm7xx_boards.c | 6 ++---- hw/arm/Kconfig | 1 + 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index eed0da71b8a..e5a32439954 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -18,6 +18,7 @@ =20 #include "hw/arm/npcm7xx.h" #include "hw/core/cpu.h" +#include "hw/i2c/i2c_mux_pca954x.h" #include "hw/i2c/smbus_eeprom.h" #include "hw/loader.h" #include "hw/qdev-core.h" @@ -232,10 +233,7 @@ static void quanta_gsj_i2c_init(NPCM7xxState *soc) * - ucd90160@6b */ =20 - /* - * i2c-15: - * - pca9548@75 - */ + i2c_slave_create_simple(npcm7xx_i2c_get_bus(soc, 15), "pca9548", 0x75); } =20 static void quanta_gsj_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 67723d9ea6a..8e7c9d22a45 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -378,6 +378,7 @@ config NPCM7XX select SERIAL select SSI select UNIMP + select PCA954X =20 config FSL_IMX25 bool --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772566; cv=none; d=zohomail.com; s=zohoarc; b=Rm0OohtxBTVswZoCNwjraLp2xcaEduxZRMNYICycYQ3ycA2lIFw+NPU9Dv4AtgO0SUVSr+BksYQg98PZ12+V+Nn7whuAcDZv7IZqskjTbZnhO5V0ALS5NcjHevxUoONc1xgML2i5/tgXdMnmkM+aIWeXJiHScy3LzChcOGPebtk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cx+nRZZDSzyxnSLiyezkFu0ca/l+cSVer7KxgYODaMI=; b=PHN4hTSTRgjsDJRvTwtF5HStTK607jbZ811W1OxZULPaFcjYg1j6Ajhne7sMsyeAtg Gjw9NODez5vSGDOGY0ij1enN08apGgdAoRGyyeCLdGJcrojavSvk2Ea0gvGZy4a2wkK6 rXeyIXacYgsNUMVCXIiZ+7qZor2eCjytzAN5pa9Av4qJuJAc+1/HObmaWYZM918luY1C yvUnIiUNs8GCZlGvhfAO9YWqbl2bE/tPS+dQGKsO8Uht2oB4x+cyDuK0c8vGIpsGeB1L bhK9CVUCxDVv4i8pomkGK/m9jrgM5WOGucSm5T5kp5e9tL0fUa+m5aYzHaZqOHDX474m 1x5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cx+nRZZDSzyxnSLiyezkFu0ca/l+cSVer7KxgYODaMI=; b=fnTjRBvly2agG00wRYXCwbW70K37NFrlUflSREKXOIHQc0Jg98VsAeFFk4XT1X4yhn g5+LCthjdfjf2q4aZJ+h6/DgssKMwBOND/pdGmCm159ZEm5D5/VJFq408wJCgn/aOEHg G2v0tLooYLH4dJLG/JA7dwiyPcGzQcClrIrHOVGjYOKY2NWYVVprW/xMgMMRrVL4A9E0 na6zM2iv8OKLbOjkuMwJiN1z78arDNBCCBv5NPLkE1XMoP2fYk/iF6xgOFH3d9nr/wtI CBDPQryYTBSPBkykX8McFanF1ZTcJx0vN4vAKsH3inQoBS8SXOFXaQBm0wqH6F20avMT djpQ== X-Gm-Message-State: AOAM532fzb3cokMC5BuS/LR2XUCKX/qrNSqWB2pZEYVQ/rFdViAmVSPD pFG/WDjgab2Fg9TEr5zYsClkK0lpm/WMqg== X-Google-Smtp-Source: ABdhPJwhR5hBD3uqrYwKNLmWyCzjGl//OeRWHIkgOOguI7TlFS73wffQN95ntKtaOAaC6nsZrtWYSg== X-Received: by 2002:a5d:4589:: with SMTP id p9mr845634wrq.30.1623771858522; Tue, 15 Jun 2021 08:44:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/28] hw/arm: quanta-q71l add pca954x muxes Date: Tue, 15 Jun 2021 16:43:52 +0100 Message-Id: <20210615154405.21399-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Patrick Venture Adds the pca954x muxes expected. Tested: Booted quanta-q71l image to userspace. Signed-off-by: Patrick Venture Reviewed-by: Hao Wu Reviewed-by: Joel Stanley Reviewed-by: C=C3=A9dric Le Goater Message-id: 20210608202522.2677850-4-venture@google.com Signed-off-by: Peter Maydell --- hw/arm/aspeed.c | 11 ++++++++--- hw/arm/Kconfig | 1 + 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 0eafc791540..1301e8fdffb 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -14,6 +14,7 @@ #include "hw/arm/boot.h" #include "hw/arm/aspeed.h" #include "hw/arm/aspeed_soc.h" +#include "hw/i2c/i2c_mux_pca954x.h" #include "hw/i2c/smbus_eeprom.h" #include "hw/misc/pca9552.h" #include "hw/misc/tmp105.h" @@ -461,14 +462,18 @@ static void quanta_q71l_bmc_i2c_init(AspeedMachineSta= te *bmc) /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ /* TODO: Add Memory Riser i2c mux and eeproms. */ =20 - /* TODO: i2c-2: pca9546@74 */ - /* TODO: i2c-2: pca9548@77 */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0= x74); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0= x77); + /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ - /* TODO: i2c-7: Add pca9546@70 */ + + /* i2c-7 */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0= x70); /* - i2c@0: pmbus@59 */ /* - i2c@1: pmbus@58 */ /* - i2c@2: pmbus@58 */ /* - i2c@3: pmbus@59 */ + /* TODO: i2c-7: Add PDB FRU eeprom@52 */ /* TODO: i2c-8: Add BMC FRU eeprom@50 */ } diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 8e7c9d22a45..647b5c8b43a 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -414,6 +414,7 @@ config ASPEED_SOC select PCA9552 select SERIAL select SMBUS_EEPROM + select PCA954X select SSI select SSI_M25P80 select TMP105 --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623773064; cv=none; d=zohomail.com; s=zohoarc; b=nk/UkI8dlknwNzqRQXRkRgwWOgMSI0JIW2zeh09PkcbM5JmyfkbO3OAHZ2QQOZlKmYEvkNgyvdtpBOSSbnqfH9abFSs1YoKmLC/WqeqyFptD2jTkQ4vLuALaZYW5qirZhjFpl9qCqisQEHZZGGOzCyom2eUGF1iAGdKknCT2m0M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623773064; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xMhwru3TqGBEQG1L+ZTXMD2uR6uQ/W/0vJzrOK+iROQ=; b=HQvFFnc067HsojDISupCnUn67IYYExzZvoR1PDc1LIXMDBTGs0n8rmy5ZAhmN20oxqasi67Ke8hIcvTg3kJaFyCnsbcWeARhUa9v/l0mdkPtt5gXrvH2weQEPa9Wu94vyjS20tYS2Lj+VaSL73VVpe6LlrzyTKSilpcaL76i8xk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623773064154360.8197361330389; Tue, 15 Jun 2021 09:04:24 -0700 (PDT) Received: from localhost ([::1]:42104 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBY6-0002tx-US for importer@patchew.org; Tue, 15 Jun 2021 12:04:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43162) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBFP-0006iz-RT for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:45:04 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:40576) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEj-0000z9-VA for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:45:03 -0400 Received: by mail-wr1-x435.google.com with SMTP id y7so18847397wrh.7 for ; Tue, 15 Jun 2021 08:44:20 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xMhwru3TqGBEQG1L+ZTXMD2uR6uQ/W/0vJzrOK+iROQ=; b=LWuHs4xC4dALxRlpAfxnUm9J81wjvwGxi32Hr8Fxcsi/FXyqVHJ6QqBs64nHoi+n0x sHpa5Ums59avhVRTTH1gAmNqMi1ZDfISaEi1p16HQZKKvfpsl1EN1mtem48QVHWNQn1c VSAPKeVeAOLzirnRuytlVRorpnlE45V2tIje81t1ofnQBq00yVvA6h8Mrj6RhINbN9vD jhoDizMdRX+ESNz8rg621+9Ocn6LaxUzoKgjIZvjY6uj4/1pzeAYLlOYIITveHv5BtTv QybpHtlpUtYPCowITzLp6B+BD2a8G6MSC0tYVzbCLMdwehKI4mA7eo2suoC3CqHEoV0K mJCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xMhwru3TqGBEQG1L+ZTXMD2uR6uQ/W/0vJzrOK+iROQ=; b=WQljir6gouZGTiwjyuNw7rsigLpGyIdWjyuDJn9FYkRElVG/i6BOZQ/FuPL9KUTxjf YwHh43w47KE4cgcCaHLuD0rCX8m9JUj1wE6Mgrz/8pFGvnMXDyCuIck1RTTZvk11rpMK VaM+w6/msxScoeCtbdf7pS6VAioLm40NIFuMiln/TgZn6GMJOKSI51OcbJibvZ2+rYS9 Wz50XY4VGM/nbELRJxL0KNmKIZd9Qlnz33g4WY2XPfLj2U4xwRVzHdiBLrJlG4mtyDsA 2CNv7Rw8PXa6uScBCirjeKL62y9DGhg3fNqdlW6gmPexK8494UC1CjRIVnwJvS0oR33C FbxQ== X-Gm-Message-State: AOAM533aKGqUbzLlIv9gL6i6Tuxomcc0yNiDa5SBJzJGX7EsIx4DEgaG VhmurVrYxsUkf3vdOW84gE9od70SBwJe/Q== X-Google-Smtp-Source: ABdhPJzDfzqWjeOkVpUOvlRCgebrgdfV0lyhsSw1Oa03uDnSsgxHa4xmjR6oLS532rTBmSvuji9d/w== X-Received: by 2002:a5d:6daf:: with SMTP id u15mr26137120wrs.400.1623771859898; Tue, 15 Jun 2021 08:44:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/28] target/arm: Provide and use H8 and H1_8 macros Date: Tue, 15 Jun 2021 16:43:53 +0100 Message-Id: <20210615154405.21399-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Currently we provide Hn and H1_n macros for accessing the correct data within arrays of vector elements of size 1, 2 and 4, accounting for host endianness. We don't provide any macros for elements of size 8 because there the host endianness doesn't matter. However, this does result in awkwardness where we need to pass empty arguments to macros, because checkpatch complains about them. The empty argument is a little confusing for humans to read as well. Add H8() and H1_8() macros and use them where we were previously passing empty arguments to macros. Suggested-by: Richard Henderson Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20210614151007.4545-2-peter.maydell@linaro.org Message-id: 20210610132505.5827-1-peter.maydell@linaro.org --- target/arm/vec_internal.h | 8 +- target/arm/sve_helper.c | 258 +++++++++++++++++++------------------- target/arm/vec_helper.c | 14 +-- 3 files changed, 143 insertions(+), 137 deletions(-) diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h index dba481e0012..613f3421b9c 100644 --- a/target/arm/vec_internal.h +++ b/target/arm/vec_internal.h @@ -42,7 +42,13 @@ #define H2(x) (x) #define H4(x) (x) #endif - +/* + * Access to 64-bit elements isn't host-endian dependent; we provide H8 + * and H1_8 so that when a function is being generated from a macro we + * can pass these rather than an empty macro argument, for clarity. + */ +#define H8(x) (x) +#define H1_8(x) (x) =20 static inline void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) { diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 46a957b6fb0..a373f8c573e 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -905,23 +905,23 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void = *vg, \ =20 DO_ZPZZ_PAIR_FP(sve2_faddp_zpzz_h, float16, H1_2, float16_add) DO_ZPZZ_PAIR_FP(sve2_faddp_zpzz_s, float32, H1_4, float32_add) -DO_ZPZZ_PAIR_FP(sve2_faddp_zpzz_d, float64, , float64_add) +DO_ZPZZ_PAIR_FP(sve2_faddp_zpzz_d, float64, H1_8, float64_add) =20 DO_ZPZZ_PAIR_FP(sve2_fmaxnmp_zpzz_h, float16, H1_2, float16_maxnum) DO_ZPZZ_PAIR_FP(sve2_fmaxnmp_zpzz_s, float32, H1_4, float32_maxnum) -DO_ZPZZ_PAIR_FP(sve2_fmaxnmp_zpzz_d, float64, , float64_maxnum) +DO_ZPZZ_PAIR_FP(sve2_fmaxnmp_zpzz_d, float64, H1_8, float64_maxnum) =20 DO_ZPZZ_PAIR_FP(sve2_fminnmp_zpzz_h, float16, H1_2, float16_minnum) DO_ZPZZ_PAIR_FP(sve2_fminnmp_zpzz_s, float32, H1_4, float32_minnum) -DO_ZPZZ_PAIR_FP(sve2_fminnmp_zpzz_d, float64, , float64_minnum) +DO_ZPZZ_PAIR_FP(sve2_fminnmp_zpzz_d, float64, H1_8, float64_minnum) =20 DO_ZPZZ_PAIR_FP(sve2_fmaxp_zpzz_h, float16, H1_2, float16_max) DO_ZPZZ_PAIR_FP(sve2_fmaxp_zpzz_s, float32, H1_4, float32_max) -DO_ZPZZ_PAIR_FP(sve2_fmaxp_zpzz_d, float64, , float64_max) +DO_ZPZZ_PAIR_FP(sve2_fmaxp_zpzz_d, float64, H1_8, float64_max) =20 DO_ZPZZ_PAIR_FP(sve2_fminp_zpzz_h, float16, H1_2, float16_min) DO_ZPZZ_PAIR_FP(sve2_fminp_zpzz_s, float32, H1_4, float32_min) -DO_ZPZZ_PAIR_FP(sve2_fminp_zpzz_d, float64, , float64_min) +DO_ZPZZ_PAIR_FP(sve2_fminp_zpzz_d, float64, H1_8, float64_min) =20 #undef DO_ZPZZ_PAIR_FP =20 @@ -1171,35 +1171,35 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uin= t32_t desc) \ =20 DO_ZZZ_TB(sve2_saddl_h, int16_t, int8_t, H1_2, H1, DO_ADD) DO_ZZZ_TB(sve2_saddl_s, int32_t, int16_t, H1_4, H1_2, DO_ADD) -DO_ZZZ_TB(sve2_saddl_d, int64_t, int32_t, , H1_4, DO_ADD) +DO_ZZZ_TB(sve2_saddl_d, int64_t, int32_t, H1_8, H1_4, DO_ADD) =20 DO_ZZZ_TB(sve2_ssubl_h, int16_t, int8_t, H1_2, H1, DO_SUB) DO_ZZZ_TB(sve2_ssubl_s, int32_t, int16_t, H1_4, H1_2, DO_SUB) -DO_ZZZ_TB(sve2_ssubl_d, int64_t, int32_t, , H1_4, DO_SUB) +DO_ZZZ_TB(sve2_ssubl_d, int64_t, int32_t, H1_8, H1_4, DO_SUB) =20 DO_ZZZ_TB(sve2_sabdl_h, int16_t, int8_t, H1_2, H1, DO_ABD) DO_ZZZ_TB(sve2_sabdl_s, int32_t, int16_t, H1_4, H1_2, DO_ABD) -DO_ZZZ_TB(sve2_sabdl_d, int64_t, int32_t, , H1_4, DO_ABD) +DO_ZZZ_TB(sve2_sabdl_d, int64_t, int32_t, H1_8, H1_4, DO_ABD) =20 DO_ZZZ_TB(sve2_uaddl_h, uint16_t, uint8_t, H1_2, H1, DO_ADD) DO_ZZZ_TB(sve2_uaddl_s, uint32_t, uint16_t, H1_4, H1_2, DO_ADD) -DO_ZZZ_TB(sve2_uaddl_d, uint64_t, uint32_t, , H1_4, DO_ADD) +DO_ZZZ_TB(sve2_uaddl_d, uint64_t, uint32_t, H1_8, H1_4, DO_ADD) =20 DO_ZZZ_TB(sve2_usubl_h, uint16_t, uint8_t, H1_2, H1, DO_SUB) DO_ZZZ_TB(sve2_usubl_s, uint32_t, uint16_t, H1_4, H1_2, DO_SUB) -DO_ZZZ_TB(sve2_usubl_d, uint64_t, uint32_t, , H1_4, DO_SUB) +DO_ZZZ_TB(sve2_usubl_d, uint64_t, uint32_t, H1_8, H1_4, DO_SUB) =20 DO_ZZZ_TB(sve2_uabdl_h, uint16_t, uint8_t, H1_2, H1, DO_ABD) DO_ZZZ_TB(sve2_uabdl_s, uint32_t, uint16_t, H1_4, H1_2, DO_ABD) -DO_ZZZ_TB(sve2_uabdl_d, uint64_t, uint32_t, , H1_4, DO_ABD) +DO_ZZZ_TB(sve2_uabdl_d, uint64_t, uint32_t, H1_8, H1_4, DO_ABD) =20 DO_ZZZ_TB(sve2_smull_zzz_h, int16_t, int8_t, H1_2, H1, DO_MUL) DO_ZZZ_TB(sve2_smull_zzz_s, int32_t, int16_t, H1_4, H1_2, DO_MUL) -DO_ZZZ_TB(sve2_smull_zzz_d, int64_t, int32_t, , H1_4, DO_MUL) +DO_ZZZ_TB(sve2_smull_zzz_d, int64_t, int32_t, H1_8, H1_4, DO_MUL) =20 DO_ZZZ_TB(sve2_umull_zzz_h, uint16_t, uint8_t, H1_2, H1, DO_MUL) DO_ZZZ_TB(sve2_umull_zzz_s, uint32_t, uint16_t, H1_4, H1_2, DO_MUL) -DO_ZZZ_TB(sve2_umull_zzz_d, uint64_t, uint32_t, , H1_4, DO_MUL) +DO_ZZZ_TB(sve2_umull_zzz_d, uint64_t, uint32_t, H1_8, H1_4, DO_MUL) =20 /* Note that the multiply cannot overflow, but the doubling can. */ static inline int16_t do_sqdmull_h(int16_t n, int16_t m) @@ -1222,7 +1222,7 @@ static inline int64_t do_sqdmull_d(int64_t n, int64_t= m) =20 DO_ZZZ_TB(sve2_sqdmull_zzz_h, int16_t, int8_t, H1_2, H1, do_sqdmull_h) DO_ZZZ_TB(sve2_sqdmull_zzz_s, int32_t, int16_t, H1_4, H1_2, do_sqdmull_s) -DO_ZZZ_TB(sve2_sqdmull_zzz_d, int64_t, int32_t, , H1_4, do_sqdmull_d) +DO_ZZZ_TB(sve2_sqdmull_zzz_d, int64_t, int32_t, H1_8, H1_4, do_sqdmull_d) =20 #undef DO_ZZZ_TB =20 @@ -1240,19 +1240,19 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uin= t32_t desc) \ =20 DO_ZZZ_WTB(sve2_saddw_h, int16_t, int8_t, H1_2, H1, DO_ADD) DO_ZZZ_WTB(sve2_saddw_s, int32_t, int16_t, H1_4, H1_2, DO_ADD) -DO_ZZZ_WTB(sve2_saddw_d, int64_t, int32_t, , H1_4, DO_ADD) +DO_ZZZ_WTB(sve2_saddw_d, int64_t, int32_t, H1_8, H1_4, DO_ADD) =20 DO_ZZZ_WTB(sve2_ssubw_h, int16_t, int8_t, H1_2, H1, DO_SUB) DO_ZZZ_WTB(sve2_ssubw_s, int32_t, int16_t, H1_4, H1_2, DO_SUB) -DO_ZZZ_WTB(sve2_ssubw_d, int64_t, int32_t, , H1_4, DO_SUB) +DO_ZZZ_WTB(sve2_ssubw_d, int64_t, int32_t, H1_8, H1_4, DO_SUB) =20 DO_ZZZ_WTB(sve2_uaddw_h, uint16_t, uint8_t, H1_2, H1, DO_ADD) DO_ZZZ_WTB(sve2_uaddw_s, uint32_t, uint16_t, H1_4, H1_2, DO_ADD) -DO_ZZZ_WTB(sve2_uaddw_d, uint64_t, uint32_t, , H1_4, DO_ADD) +DO_ZZZ_WTB(sve2_uaddw_d, uint64_t, uint32_t, H1_8, H1_4, DO_ADD) =20 DO_ZZZ_WTB(sve2_usubw_h, uint16_t, uint8_t, H1_2, H1, DO_SUB) DO_ZZZ_WTB(sve2_usubw_s, uint32_t, uint16_t, H1_4, H1_2, DO_SUB) -DO_ZZZ_WTB(sve2_usubw_d, uint64_t, uint32_t, , H1_4, DO_SUB) +DO_ZZZ_WTB(sve2_usubw_d, uint64_t, uint32_t, H1_8, H1_4, DO_SUB) =20 #undef DO_ZZZ_WTB =20 @@ -1272,7 +1272,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uint3= 2_t desc) \ DO_ZZZ_NTB(sve2_eoril_b, uint8_t, H1, DO_EOR) DO_ZZZ_NTB(sve2_eoril_h, uint16_t, H1_2, DO_EOR) DO_ZZZ_NTB(sve2_eoril_s, uint32_t, H1_4, DO_EOR) -DO_ZZZ_NTB(sve2_eoril_d, uint64_t, , DO_EOR) +DO_ZZZ_NTB(sve2_eoril_d, uint64_t, H1_8, DO_EOR) =20 #undef DO_ZZZ_NTB =20 @@ -1291,29 +1291,29 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, voi= d *va, uint32_t desc) \ =20 DO_ZZZW_ACC(sve2_sabal_h, int16_t, int8_t, H1_2, H1, DO_ABD) DO_ZZZW_ACC(sve2_sabal_s, int32_t, int16_t, H1_4, H1_2, DO_ABD) -DO_ZZZW_ACC(sve2_sabal_d, int64_t, int32_t, , H1_4, DO_ABD) +DO_ZZZW_ACC(sve2_sabal_d, int64_t, int32_t, H1_8, H1_4, DO_ABD) =20 DO_ZZZW_ACC(sve2_uabal_h, uint16_t, uint8_t, H1_2, H1, DO_ABD) DO_ZZZW_ACC(sve2_uabal_s, uint32_t, uint16_t, H1_4, H1_2, DO_ABD) -DO_ZZZW_ACC(sve2_uabal_d, uint64_t, uint32_t, , H1_4, DO_ABD) +DO_ZZZW_ACC(sve2_uabal_d, uint64_t, uint32_t, H1_8, H1_4, DO_ABD) =20 DO_ZZZW_ACC(sve2_smlal_zzzw_h, int16_t, int8_t, H1_2, H1, DO_MUL) DO_ZZZW_ACC(sve2_smlal_zzzw_s, int32_t, int16_t, H1_4, H1_2, DO_MUL) -DO_ZZZW_ACC(sve2_smlal_zzzw_d, int64_t, int32_t, , H1_4, DO_MUL) +DO_ZZZW_ACC(sve2_smlal_zzzw_d, int64_t, int32_t, H1_8, H1_4, DO_MUL) =20 DO_ZZZW_ACC(sve2_umlal_zzzw_h, uint16_t, uint8_t, H1_2, H1, DO_MUL) DO_ZZZW_ACC(sve2_umlal_zzzw_s, uint32_t, uint16_t, H1_4, H1_2, DO_MUL) -DO_ZZZW_ACC(sve2_umlal_zzzw_d, uint64_t, uint32_t, , H1_4, DO_MUL) +DO_ZZZW_ACC(sve2_umlal_zzzw_d, uint64_t, uint32_t, H1_8, H1_4, DO_MUL) =20 #define DO_NMUL(N, M) -(N * M) =20 DO_ZZZW_ACC(sve2_smlsl_zzzw_h, int16_t, int8_t, H1_2, H1, DO_NMUL) DO_ZZZW_ACC(sve2_smlsl_zzzw_s, int32_t, int16_t, H1_4, H1_2, DO_NMUL) -DO_ZZZW_ACC(sve2_smlsl_zzzw_d, int64_t, int32_t, , H1_4, DO_NMUL) +DO_ZZZW_ACC(sve2_smlsl_zzzw_d, int64_t, int32_t, H1_8, H1_4, DO_NMUL) =20 DO_ZZZW_ACC(sve2_umlsl_zzzw_h, uint16_t, uint8_t, H1_2, H1, DO_NMUL) DO_ZZZW_ACC(sve2_umlsl_zzzw_s, uint32_t, uint16_t, H1_4, H1_2, DO_NMUL) -DO_ZZZW_ACC(sve2_umlsl_zzzw_d, uint64_t, uint32_t, , H1_4, DO_NMUL) +DO_ZZZW_ACC(sve2_umlsl_zzzw_d, uint64_t, uint32_t, H1_8, H1_4, DO_NMUL) =20 #undef DO_ZZZW_ACC =20 @@ -1425,14 +1425,14 @@ DO_SQDMLAL(sve2_sqdmlal_zzzw_h, int16_t, int8_t, H1= _2, H1, do_sqdmull_h, DO_SQADD_H) DO_SQDMLAL(sve2_sqdmlal_zzzw_s, int32_t, int16_t, H1_4, H1_2, do_sqdmull_s, DO_SQADD_S) -DO_SQDMLAL(sve2_sqdmlal_zzzw_d, int64_t, int32_t, , H1_4, +DO_SQDMLAL(sve2_sqdmlal_zzzw_d, int64_t, int32_t, H1_8, H1_4, do_sqdmull_d, do_sqadd_d) =20 DO_SQDMLAL(sve2_sqdmlsl_zzzw_h, int16_t, int8_t, H1_2, H1, do_sqdmull_h, DO_SQSUB_H) DO_SQDMLAL(sve2_sqdmlsl_zzzw_s, int32_t, int16_t, H1_4, H1_2, do_sqdmull_s, DO_SQSUB_S) -DO_SQDMLAL(sve2_sqdmlsl_zzzw_d, int64_t, int32_t, , H1_4, +DO_SQDMLAL(sve2_sqdmlsl_zzzw_d, int64_t, int32_t, H1_8, H1_4, do_sqdmull_d, do_sqsub_d) =20 #undef DO_SQDMLAL @@ -1460,7 +1460,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void = *va, uint32_t desc) \ DO_CMLA_FUNC(sve2_cmla_zzzz_b, uint8_t, H1, DO_CMLA) DO_CMLA_FUNC(sve2_cmla_zzzz_h, uint16_t, H2, DO_CMLA) DO_CMLA_FUNC(sve2_cmla_zzzz_s, uint32_t, H4, DO_CMLA) -DO_CMLA_FUNC(sve2_cmla_zzzz_d, uint64_t, , DO_CMLA) +DO_CMLA_FUNC(sve2_cmla_zzzz_d, uint64_t, H8, DO_CMLA) =20 #define DO_SQRDMLAH_B(N, M, A, S) \ do_sqrdmlah_b(N, M, A, S, true) @@ -1474,7 +1474,7 @@ DO_CMLA_FUNC(sve2_cmla_zzzz_d, uint64_t, , DO_CMLA) DO_CMLA_FUNC(sve2_sqrdcmlah_zzzz_b, int8_t, H1, DO_SQRDMLAH_B) DO_CMLA_FUNC(sve2_sqrdcmlah_zzzz_h, int16_t, H2, DO_SQRDMLAH_H) DO_CMLA_FUNC(sve2_sqrdcmlah_zzzz_s, int32_t, H4, DO_SQRDMLAH_S) -DO_CMLA_FUNC(sve2_sqrdcmlah_zzzz_d, int64_t, , DO_SQRDMLAH_D) +DO_CMLA_FUNC(sve2_sqrdcmlah_zzzz_d, int64_t, H8, DO_SQRDMLAH_D) =20 #define DO_CMLA_IDX_FUNC(NAME, TYPE, H, OP) \ void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, uint32_t desc) = \ @@ -1632,7 +1632,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void = *va, uint32_t desc) \ =20 DO_ZZXZ(sve2_sqrdmlah_idx_h, int16_t, H2, DO_SQRDMLAH_H) DO_ZZXZ(sve2_sqrdmlah_idx_s, int32_t, H4, DO_SQRDMLAH_S) -DO_ZZXZ(sve2_sqrdmlah_idx_d, int64_t, , DO_SQRDMLAH_D) +DO_ZZXZ(sve2_sqrdmlah_idx_d, int64_t, H8, DO_SQRDMLAH_D) =20 #define DO_SQRDMLSH_H(N, M, A) \ ({ uint32_t discard; do_sqrdmlah_h(N, M, A, true, true, &discard); }) @@ -1642,7 +1642,7 @@ DO_ZZXZ(sve2_sqrdmlah_idx_d, int64_t, , DO_SQRDMLAH= _D) =20 DO_ZZXZ(sve2_sqrdmlsh_idx_h, int16_t, H2, DO_SQRDMLSH_H) DO_ZZXZ(sve2_sqrdmlsh_idx_s, int32_t, H4, DO_SQRDMLSH_S) -DO_ZZXZ(sve2_sqrdmlsh_idx_d, int64_t, , DO_SQRDMLSH_D) +DO_ZZXZ(sve2_sqrdmlsh_idx_d, int64_t, H8, DO_SQRDMLSH_D) =20 #undef DO_ZZXZ =20 @@ -1665,28 +1665,28 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, voi= d *va, uint32_t desc) \ #define DO_MLA(N, M, A) (A + N * M) =20 DO_ZZXW(sve2_smlal_idx_s, int32_t, int16_t, H1_4, H1_2, DO_MLA) -DO_ZZXW(sve2_smlal_idx_d, int64_t, int32_t, , H1_4, DO_MLA) +DO_ZZXW(sve2_smlal_idx_d, int64_t, int32_t, H1_8, H1_4, DO_MLA) DO_ZZXW(sve2_umlal_idx_s, uint32_t, uint16_t, H1_4, H1_2, DO_MLA) -DO_ZZXW(sve2_umlal_idx_d, uint64_t, uint32_t, , H1_4, DO_MLA) +DO_ZZXW(sve2_umlal_idx_d, uint64_t, uint32_t, H1_8, H1_4, DO_MLA) =20 #define DO_MLS(N, M, A) (A - N * M) =20 DO_ZZXW(sve2_smlsl_idx_s, int32_t, int16_t, H1_4, H1_2, DO_MLS) -DO_ZZXW(sve2_smlsl_idx_d, int64_t, int32_t, , H1_4, DO_MLS) +DO_ZZXW(sve2_smlsl_idx_d, int64_t, int32_t, H1_8, H1_4, DO_MLS) DO_ZZXW(sve2_umlsl_idx_s, uint32_t, uint16_t, H1_4, H1_2, DO_MLS) -DO_ZZXW(sve2_umlsl_idx_d, uint64_t, uint32_t, , H1_4, DO_MLS) +DO_ZZXW(sve2_umlsl_idx_d, uint64_t, uint32_t, H1_8, H1_4, DO_MLS) =20 #define DO_SQDMLAL_S(N, M, A) DO_SQADD_S(A, do_sqdmull_s(N, M)) #define DO_SQDMLAL_D(N, M, A) do_sqadd_d(A, do_sqdmull_d(N, M)) =20 DO_ZZXW(sve2_sqdmlal_idx_s, int32_t, int16_t, H1_4, H1_2, DO_SQDMLAL_S) -DO_ZZXW(sve2_sqdmlal_idx_d, int64_t, int32_t, , H1_4, DO_SQDMLAL_D) +DO_ZZXW(sve2_sqdmlal_idx_d, int64_t, int32_t, H1_8, H1_4, DO_SQDMLAL_D) =20 #define DO_SQDMLSL_S(N, M, A) DO_SQSUB_S(A, do_sqdmull_s(N, M)) #define DO_SQDMLSL_D(N, M, A) do_sqsub_d(A, do_sqdmull_d(N, M)) =20 DO_ZZXW(sve2_sqdmlsl_idx_s, int32_t, int16_t, H1_4, H1_2, DO_SQDMLSL_S) -DO_ZZXW(sve2_sqdmlsl_idx_d, int64_t, int32_t, , H1_4, DO_SQDMLSL_D) +DO_ZZXW(sve2_sqdmlsl_idx_d, int64_t, int32_t, H1_8, H1_4, DO_SQDMLSL_D) =20 #undef DO_MLA #undef DO_MLS @@ -1708,13 +1708,13 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uin= t32_t desc) \ } =20 DO_ZZX(sve2_sqdmull_idx_s, int32_t, int16_t, H1_4, H1_2, do_sqdmull_s) -DO_ZZX(sve2_sqdmull_idx_d, int64_t, int32_t, , H1_4, do_sqdmull_d) +DO_ZZX(sve2_sqdmull_idx_d, int64_t, int32_t, H1_8, H1_4, do_sqdmull_d) =20 DO_ZZX(sve2_smull_idx_s, int32_t, int16_t, H1_4, H1_2, DO_MUL) -DO_ZZX(sve2_smull_idx_d, int64_t, int32_t, , H1_4, DO_MUL) +DO_ZZX(sve2_smull_idx_d, int64_t, int32_t, H1_8, H1_4, DO_MUL) =20 DO_ZZX(sve2_umull_idx_s, uint32_t, uint16_t, H1_4, H1_2, DO_MUL) -DO_ZZX(sve2_umull_idx_d, uint64_t, uint32_t, , H1_4, DO_MUL) +DO_ZZX(sve2_umull_idx_d, uint64_t, uint32_t, H1_8, H1_4, DO_MUL) =20 #undef DO_ZZX =20 @@ -1824,12 +1824,12 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uin= t32_t desc) \ DO_CADD(sve2_cadd_b, int8_t, H1, DO_ADD, DO_SUB) DO_CADD(sve2_cadd_h, int16_t, H1_2, DO_ADD, DO_SUB) DO_CADD(sve2_cadd_s, int32_t, H1_4, DO_ADD, DO_SUB) -DO_CADD(sve2_cadd_d, int64_t, , DO_ADD, DO_SUB) +DO_CADD(sve2_cadd_d, int64_t, H1_8, DO_ADD, DO_SUB) =20 DO_CADD(sve2_sqcadd_b, int8_t, H1, DO_SQADD_B, DO_SQSUB_B) DO_CADD(sve2_sqcadd_h, int16_t, H1_2, DO_SQADD_H, DO_SQSUB_H) DO_CADD(sve2_sqcadd_s, int32_t, H1_4, DO_SQADD_S, DO_SQSUB_S) -DO_CADD(sve2_sqcadd_d, int64_t, , do_sqadd_d, do_sqsub_d) +DO_CADD(sve2_sqcadd_d, int64_t, H1_8, do_sqadd_d, do_sqsub_d) =20 #undef DO_CADD =20 @@ -1847,11 +1847,11 @@ void HELPER(NAME)(void *vd, void *vn, uint32_t desc= ) \ =20 DO_ZZI_SHLL(sve2_sshll_h, int16_t, int8_t, H1_2, H1) DO_ZZI_SHLL(sve2_sshll_s, int32_t, int16_t, H1_4, H1_2) -DO_ZZI_SHLL(sve2_sshll_d, int64_t, int32_t, , H1_4) +DO_ZZI_SHLL(sve2_sshll_d, int64_t, int32_t, H1_8, H1_4) =20 DO_ZZI_SHLL(sve2_ushll_h, uint16_t, uint8_t, H1_2, H1) DO_ZZI_SHLL(sve2_ushll_s, uint32_t, uint16_t, H1_4, H1_2) -DO_ZZI_SHLL(sve2_ushll_d, uint64_t, uint32_t, , H1_4) +DO_ZZI_SHLL(sve2_ushll_d, uint64_t, uint32_t, H1_8, H1_4) =20 #undef DO_ZZI_SHLL =20 @@ -2289,7 +2289,7 @@ DO_SHRNB(sve2_shrnb_d, uint64_t, uint32_t, DO_SHR) =20 DO_SHRNT(sve2_shrnt_h, uint16_t, uint8_t, H1_2, H1, DO_SHR) DO_SHRNT(sve2_shrnt_s, uint32_t, uint16_t, H1_4, H1_2, DO_SHR) -DO_SHRNT(sve2_shrnt_d, uint64_t, uint32_t, , H1_4, DO_SHR) +DO_SHRNT(sve2_shrnt_d, uint64_t, uint32_t, H1_8, H1_4, DO_SHR) =20 DO_SHRNB(sve2_rshrnb_h, uint16_t, uint8_t, do_urshr) DO_SHRNB(sve2_rshrnb_s, uint32_t, uint16_t, do_urshr) @@ -2297,7 +2297,7 @@ DO_SHRNB(sve2_rshrnb_d, uint64_t, uint32_t, do_urshr) =20 DO_SHRNT(sve2_rshrnt_h, uint16_t, uint8_t, H1_2, H1, do_urshr) DO_SHRNT(sve2_rshrnt_s, uint32_t, uint16_t, H1_4, H1_2, do_urshr) -DO_SHRNT(sve2_rshrnt_d, uint64_t, uint32_t, , H1_4, do_urshr) +DO_SHRNT(sve2_rshrnt_d, uint64_t, uint32_t, H1_8, H1_4, do_urshr) =20 #define DO_SQSHRUN_H(x, sh) do_sat_bhs((int64_t)(x) >> sh, 0, UINT8_MAX) #define DO_SQSHRUN_S(x, sh) do_sat_bhs((int64_t)(x) >> sh, 0, UINT16_MAX) @@ -2310,7 +2310,7 @@ DO_SHRNB(sve2_sqshrunb_d, int64_t, uint32_t, DO_SQSHR= UN_D) =20 DO_SHRNT(sve2_sqshrunt_h, int16_t, uint8_t, H1_2, H1, DO_SQSHRUN_H) DO_SHRNT(sve2_sqshrunt_s, int32_t, uint16_t, H1_4, H1_2, DO_SQSHRUN_S) -DO_SHRNT(sve2_sqshrunt_d, int64_t, uint32_t, , H1_4, DO_SQSHRUN_D) +DO_SHRNT(sve2_sqshrunt_d, int64_t, uint32_t, H1_8, H1_4, DO_SQSHRUN_D) =20 #define DO_SQRSHRUN_H(x, sh) do_sat_bhs(do_srshr(x, sh), 0, UINT8_MAX) #define DO_SQRSHRUN_S(x, sh) do_sat_bhs(do_srshr(x, sh), 0, UINT16_MAX) @@ -2322,7 +2322,7 @@ DO_SHRNB(sve2_sqrshrunb_d, int64_t, uint32_t, DO_SQRS= HRUN_D) =20 DO_SHRNT(sve2_sqrshrunt_h, int16_t, uint8_t, H1_2, H1, DO_SQRSHRUN_H) DO_SHRNT(sve2_sqrshrunt_s, int32_t, uint16_t, H1_4, H1_2, DO_SQRSHRUN_S) -DO_SHRNT(sve2_sqrshrunt_d, int64_t, uint32_t, , H1_4, DO_SQRSHRUN_D) +DO_SHRNT(sve2_sqrshrunt_d, int64_t, uint32_t, H1_8, H1_4, DO_SQRSHRUN_D) =20 #define DO_SQSHRN_H(x, sh) do_sat_bhs(x >> sh, INT8_MIN, INT8_MAX) #define DO_SQSHRN_S(x, sh) do_sat_bhs(x >> sh, INT16_MIN, INT16_MAX) @@ -2334,7 +2334,7 @@ DO_SHRNB(sve2_sqshrnb_d, int64_t, uint32_t, DO_SQSHRN= _D) =20 DO_SHRNT(sve2_sqshrnt_h, int16_t, uint8_t, H1_2, H1, DO_SQSHRN_H) DO_SHRNT(sve2_sqshrnt_s, int32_t, uint16_t, H1_4, H1_2, DO_SQSHRN_S) -DO_SHRNT(sve2_sqshrnt_d, int64_t, uint32_t, , H1_4, DO_SQSHRN_D) +DO_SHRNT(sve2_sqshrnt_d, int64_t, uint32_t, H1_8, H1_4, DO_SQSHRN_D) =20 #define DO_SQRSHRN_H(x, sh) do_sat_bhs(do_srshr(x, sh), INT8_MIN, INT8_MAX) #define DO_SQRSHRN_S(x, sh) do_sat_bhs(do_srshr(x, sh), INT16_MIN, INT16_M= AX) @@ -2346,7 +2346,7 @@ DO_SHRNB(sve2_sqrshrnb_d, int64_t, uint32_t, DO_SQRSH= RN_D) =20 DO_SHRNT(sve2_sqrshrnt_h, int16_t, uint8_t, H1_2, H1, DO_SQRSHRN_H) DO_SHRNT(sve2_sqrshrnt_s, int32_t, uint16_t, H1_4, H1_2, DO_SQRSHRN_S) -DO_SHRNT(sve2_sqrshrnt_d, int64_t, uint32_t, , H1_4, DO_SQRSHRN_D) +DO_SHRNT(sve2_sqrshrnt_d, int64_t, uint32_t, H1_8, H1_4, DO_SQRSHRN_D) =20 #define DO_UQSHRN_H(x, sh) MIN(x >> sh, UINT8_MAX) #define DO_UQSHRN_S(x, sh) MIN(x >> sh, UINT16_MAX) @@ -2358,7 +2358,7 @@ DO_SHRNB(sve2_uqshrnb_d, uint64_t, uint32_t, DO_UQSHR= N_D) =20 DO_SHRNT(sve2_uqshrnt_h, uint16_t, uint8_t, H1_2, H1, DO_UQSHRN_H) DO_SHRNT(sve2_uqshrnt_s, uint32_t, uint16_t, H1_4, H1_2, DO_UQSHRN_S) -DO_SHRNT(sve2_uqshrnt_d, uint64_t, uint32_t, , H1_4, DO_UQSHRN_D) +DO_SHRNT(sve2_uqshrnt_d, uint64_t, uint32_t, H1_8, H1_4, DO_UQSHRN_D) =20 #define DO_UQRSHRN_H(x, sh) MIN(do_urshr(x, sh), UINT8_MAX) #define DO_UQRSHRN_S(x, sh) MIN(do_urshr(x, sh), UINT16_MAX) @@ -2370,7 +2370,7 @@ DO_SHRNB(sve2_uqrshrnb_d, uint64_t, uint32_t, DO_UQRS= HRN_D) =20 DO_SHRNT(sve2_uqrshrnt_h, uint16_t, uint8_t, H1_2, H1, DO_UQRSHRN_H) DO_SHRNT(sve2_uqrshrnt_s, uint32_t, uint16_t, H1_4, H1_2, DO_UQRSHRN_S) -DO_SHRNT(sve2_uqrshrnt_d, uint64_t, uint32_t, , H1_4, DO_UQRSHRN_D) +DO_SHRNT(sve2_uqrshrnt_d, uint64_t, uint32_t, H1_8, H1_4, DO_UQRSHRN_D) =20 #undef DO_SHRNB #undef DO_SHRNT @@ -2408,7 +2408,7 @@ DO_BINOPNB(sve2_addhnb_d, uint64_t, uint32_t, 32, DO_= ADDHN) =20 DO_BINOPNT(sve2_addhnt_h, uint16_t, uint8_t, 8, H1_2, H1, DO_ADDHN) DO_BINOPNT(sve2_addhnt_s, uint32_t, uint16_t, 16, H1_4, H1_2, DO_ADDHN) -DO_BINOPNT(sve2_addhnt_d, uint64_t, uint32_t, 32, , H1_4, DO_ADDHN) +DO_BINOPNT(sve2_addhnt_d, uint64_t, uint32_t, 32, H1_8, H1_4, DO_ADDHN) =20 DO_BINOPNB(sve2_raddhnb_h, uint16_t, uint8_t, 8, DO_RADDHN) DO_BINOPNB(sve2_raddhnb_s, uint32_t, uint16_t, 16, DO_RADDHN) @@ -2416,7 +2416,7 @@ DO_BINOPNB(sve2_raddhnb_d, uint64_t, uint32_t, 32, DO= _RADDHN) =20 DO_BINOPNT(sve2_raddhnt_h, uint16_t, uint8_t, 8, H1_2, H1, DO_RADDHN) DO_BINOPNT(sve2_raddhnt_s, uint32_t, uint16_t, 16, H1_4, H1_2, DO_RADDHN) -DO_BINOPNT(sve2_raddhnt_d, uint64_t, uint32_t, 32, , H1_4, DO_RADDHN) +DO_BINOPNT(sve2_raddhnt_d, uint64_t, uint32_t, 32, H1_8, H1_4, DO_RADDHN) =20 DO_BINOPNB(sve2_subhnb_h, uint16_t, uint8_t, 8, DO_SUBHN) DO_BINOPNB(sve2_subhnb_s, uint32_t, uint16_t, 16, DO_SUBHN) @@ -2424,7 +2424,7 @@ DO_BINOPNB(sve2_subhnb_d, uint64_t, uint32_t, 32, DO_= SUBHN) =20 DO_BINOPNT(sve2_subhnt_h, uint16_t, uint8_t, 8, H1_2, H1, DO_SUBHN) DO_BINOPNT(sve2_subhnt_s, uint32_t, uint16_t, 16, H1_4, H1_2, DO_SUBHN) -DO_BINOPNT(sve2_subhnt_d, uint64_t, uint32_t, 32, , H1_4, DO_SUBHN) +DO_BINOPNT(sve2_subhnt_d, uint64_t, uint32_t, 32, H1_8, H1_4, DO_SUBHN) =20 DO_BINOPNB(sve2_rsubhnb_h, uint16_t, uint8_t, 8, DO_RSUBHN) DO_BINOPNB(sve2_rsubhnb_s, uint32_t, uint16_t, 16, DO_RSUBHN) @@ -2432,7 +2432,7 @@ DO_BINOPNB(sve2_rsubhnb_d, uint64_t, uint32_t, 32, DO= _RSUBHN) =20 DO_BINOPNT(sve2_rsubhnt_h, uint16_t, uint8_t, 8, H1_2, H1, DO_RSUBHN) DO_BINOPNT(sve2_rsubhnt_s, uint32_t, uint16_t, 16, H1_4, H1_2, DO_RSUBHN) -DO_BINOPNT(sve2_rsubhnt_d, uint64_t, uint32_t, 32, , H1_4, DO_RSUBHN) +DO_BINOPNT(sve2_rsubhnt_d, uint64_t, uint32_t, 32, H1_8, H1_4, DO_RSUBHN) =20 #undef DO_RSUBHN #undef DO_SUBHN @@ -3040,7 +3040,7 @@ void HELPER(NAME)(void *vd, void *vn, uint64_t val, u= int32_t desc) \ DO_INSR(sve_insr_b, uint8_t, H1) DO_INSR(sve_insr_h, uint16_t, H1_2) DO_INSR(sve_insr_s, uint32_t, H1_4) -DO_INSR(sve_insr_d, uint64_t, ) +DO_INSR(sve_insr_d, uint64_t, H1_8) =20 #undef DO_INSR =20 @@ -3159,7 +3159,7 @@ void HELPER(sve2_tbx_##SUFF)(void *vd, void *vn, void= *vm, uint32_t desc) \ DO_TB(b, uint8_t, H1) DO_TB(h, uint16_t, H2) DO_TB(s, uint32_t, H4) -DO_TB(d, uint64_t, ) +DO_TB(d, uint64_t, H8) =20 #undef DO_TB =20 @@ -3180,11 +3180,11 @@ void HELPER(NAME)(void *vd, void *vn, uint32_t desc= ) \ =20 DO_UNPK(sve_sunpk_h, int16_t, int8_t, H2, H1) DO_UNPK(sve_sunpk_s, int32_t, int16_t, H4, H2) -DO_UNPK(sve_sunpk_d, int64_t, int32_t, , H4) +DO_UNPK(sve_sunpk_d, int64_t, int32_t, H8, H4) =20 DO_UNPK(sve_uunpk_h, uint16_t, uint8_t, H2, H1) DO_UNPK(sve_uunpk_s, uint32_t, uint16_t, H4, H2) -DO_UNPK(sve_uunpk_d, uint64_t, uint32_t, , H4) +DO_UNPK(sve_uunpk_d, uint64_t, uint32_t, H8, H4) =20 #undef DO_UNPK =20 @@ -3519,7 +3519,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uint3= 2_t desc) \ DO_ZIP(sve_zip_b, uint8_t, H1) DO_ZIP(sve_zip_h, uint16_t, H1_2) DO_ZIP(sve_zip_s, uint32_t, H1_4) -DO_ZIP(sve_zip_d, uint64_t, ) +DO_ZIP(sve_zip_d, uint64_t, H1_8) DO_ZIP(sve2_zip_q, Int128, ) =20 #define DO_UZP(NAME, TYPE, H) \ @@ -3548,7 +3548,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uint3= 2_t desc) \ DO_UZP(sve_uzp_b, uint8_t, H1) DO_UZP(sve_uzp_h, uint16_t, H1_2) DO_UZP(sve_uzp_s, uint32_t, H1_4) -DO_UZP(sve_uzp_d, uint64_t, ) +DO_UZP(sve_uzp_d, uint64_t, H1_8) DO_UZP(sve2_uzp_q, Int128, ) =20 #define DO_TRN(NAME, TYPE, H) \ @@ -3571,7 +3571,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uint3= 2_t desc) \ DO_TRN(sve_trn_b, uint8_t, H1) DO_TRN(sve_trn_h, uint16_t, H1_2) DO_TRN(sve_trn_s, uint32_t, H1_4) -DO_TRN(sve_trn_d, uint64_t, ) +DO_TRN(sve_trn_d, uint64_t, H1_8) DO_TRN(sve2_trn_q, Int128, ) =20 #undef DO_ZIP @@ -3766,7 +3766,7 @@ uint32_t HELPER(NAME)(void *vd, void *vn, void *vm, v= oid *vg, uint32_t desc) \ #define DO_CMP_PPZZ_S(NAME, TYPE, OP) \ DO_CMP_PPZZ(NAME, TYPE, OP, H1_4, 0x1111111111111111ull) #define DO_CMP_PPZZ_D(NAME, TYPE, OP) \ - DO_CMP_PPZZ(NAME, TYPE, OP, , 0x0101010101010101ull) + DO_CMP_PPZZ(NAME, TYPE, OP, H1_8, 0x0101010101010101ull) =20 DO_CMP_PPZZ_B(sve_cmpeq_ppzz_b, uint8_t, =3D=3D) DO_CMP_PPZZ_H(sve_cmpeq_ppzz_h, uint16_t, =3D=3D) @@ -3911,7 +3911,7 @@ uint32_t HELPER(NAME)(void *vd, void *vn, void *vg, u= int32_t desc) \ #define DO_CMP_PPZI_S(NAME, TYPE, OP) \ DO_CMP_PPZI(NAME, TYPE, OP, H1_4, 0x1111111111111111ull) #define DO_CMP_PPZI_D(NAME, TYPE, OP) \ - DO_CMP_PPZI(NAME, TYPE, OP, , 0x0101010101010101ull) + DO_CMP_PPZI(NAME, TYPE, OP, H1_8, 0x0101010101010101ull) =20 DO_CMP_PPZI_B(sve_cmpeq_ppzi_b, uint8_t, =3D=3D) DO_CMP_PPZI_H(sve_cmpeq_ppzi_h, uint16_t, =3D=3D) @@ -4331,24 +4331,24 @@ uint64_t HELPER(NAME)(void *vn, void *vg, void *vs,= uint32_t desc) \ =20 DO_REDUCE(sve_faddv_h, float16, H1_2, add, float16_zero) DO_REDUCE(sve_faddv_s, float32, H1_4, add, float32_zero) -DO_REDUCE(sve_faddv_d, float64, , add, float64_zero) +DO_REDUCE(sve_faddv_d, float64, H1_8, add, float64_zero) =20 /* Identity is floatN_default_nan, without the function call. */ DO_REDUCE(sve_fminnmv_h, float16, H1_2, minnum, 0x7E00) DO_REDUCE(sve_fminnmv_s, float32, H1_4, minnum, 0x7FC00000) -DO_REDUCE(sve_fminnmv_d, float64, , minnum, 0x7FF8000000000000ULL) +DO_REDUCE(sve_fminnmv_d, float64, H1_8, minnum, 0x7FF8000000000000ULL) =20 DO_REDUCE(sve_fmaxnmv_h, float16, H1_2, maxnum, 0x7E00) DO_REDUCE(sve_fmaxnmv_s, float32, H1_4, maxnum, 0x7FC00000) -DO_REDUCE(sve_fmaxnmv_d, float64, , maxnum, 0x7FF8000000000000ULL) +DO_REDUCE(sve_fmaxnmv_d, float64, H1_8, maxnum, 0x7FF8000000000000ULL) =20 DO_REDUCE(sve_fminv_h, float16, H1_2, min, float16_infinity) DO_REDUCE(sve_fminv_s, float32, H1_4, min, float32_infinity) -DO_REDUCE(sve_fminv_d, float64, , min, float64_infinity) +DO_REDUCE(sve_fminv_d, float64, H1_8, min, float64_infinity) =20 DO_REDUCE(sve_fmaxv_h, float16, H1_2, max, float16_chs(float16_infinity)) DO_REDUCE(sve_fmaxv_s, float32, H1_4, max, float32_chs(float32_infinity)) -DO_REDUCE(sve_fmaxv_d, float64, , max, float64_chs(float64_infinity)) +DO_REDUCE(sve_fmaxv_d, float64, H1_8, max, float64_chs(float64_infinity)) =20 #undef DO_REDUCE =20 @@ -4432,35 +4432,35 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, voi= d *vg, \ =20 DO_ZPZZ_FP(sve_fadd_h, uint16_t, H1_2, float16_add) DO_ZPZZ_FP(sve_fadd_s, uint32_t, H1_4, float32_add) -DO_ZPZZ_FP(sve_fadd_d, uint64_t, , float64_add) +DO_ZPZZ_FP(sve_fadd_d, uint64_t, H1_8, float64_add) =20 DO_ZPZZ_FP(sve_fsub_h, uint16_t, H1_2, float16_sub) DO_ZPZZ_FP(sve_fsub_s, uint32_t, H1_4, float32_sub) -DO_ZPZZ_FP(sve_fsub_d, uint64_t, , float64_sub) +DO_ZPZZ_FP(sve_fsub_d, uint64_t, H1_8, float64_sub) =20 DO_ZPZZ_FP(sve_fmul_h, uint16_t, H1_2, float16_mul) DO_ZPZZ_FP(sve_fmul_s, uint32_t, H1_4, float32_mul) -DO_ZPZZ_FP(sve_fmul_d, uint64_t, , float64_mul) +DO_ZPZZ_FP(sve_fmul_d, uint64_t, H1_8, float64_mul) =20 DO_ZPZZ_FP(sve_fdiv_h, uint16_t, H1_2, float16_div) DO_ZPZZ_FP(sve_fdiv_s, uint32_t, H1_4, float32_div) -DO_ZPZZ_FP(sve_fdiv_d, uint64_t, , float64_div) +DO_ZPZZ_FP(sve_fdiv_d, uint64_t, H1_8, float64_div) =20 DO_ZPZZ_FP(sve_fmin_h, uint16_t, H1_2, float16_min) DO_ZPZZ_FP(sve_fmin_s, uint32_t, H1_4, float32_min) -DO_ZPZZ_FP(sve_fmin_d, uint64_t, , float64_min) +DO_ZPZZ_FP(sve_fmin_d, uint64_t, H1_8, float64_min) =20 DO_ZPZZ_FP(sve_fmax_h, uint16_t, H1_2, float16_max) DO_ZPZZ_FP(sve_fmax_s, uint32_t, H1_4, float32_max) -DO_ZPZZ_FP(sve_fmax_d, uint64_t, , float64_max) +DO_ZPZZ_FP(sve_fmax_d, uint64_t, H1_8, float64_max) =20 DO_ZPZZ_FP(sve_fminnum_h, uint16_t, H1_2, float16_minnum) DO_ZPZZ_FP(sve_fminnum_s, uint32_t, H1_4, float32_minnum) -DO_ZPZZ_FP(sve_fminnum_d, uint64_t, , float64_minnum) +DO_ZPZZ_FP(sve_fminnum_d, uint64_t, H1_8, float64_minnum) =20 DO_ZPZZ_FP(sve_fmaxnum_h, uint16_t, H1_2, float16_maxnum) DO_ZPZZ_FP(sve_fmaxnum_s, uint32_t, H1_4, float32_maxnum) -DO_ZPZZ_FP(sve_fmaxnum_d, uint64_t, , float64_maxnum) +DO_ZPZZ_FP(sve_fmaxnum_d, uint64_t, H1_8, float64_maxnum) =20 static inline float16 abd_h(float16 a, float16 b, float_status *s) { @@ -4479,7 +4479,7 @@ static inline float64 abd_d(float64 a, float64 b, flo= at_status *s) =20 DO_ZPZZ_FP(sve_fabd_h, uint16_t, H1_2, abd_h) DO_ZPZZ_FP(sve_fabd_s, uint32_t, H1_4, abd_s) -DO_ZPZZ_FP(sve_fabd_d, uint64_t, , abd_d) +DO_ZPZZ_FP(sve_fabd_d, uint64_t, H1_8, abd_d) =20 static inline float64 scalbn_d(float64 a, int64_t b, float_status *s) { @@ -4489,11 +4489,11 @@ static inline float64 scalbn_d(float64 a, int64_t b= , float_status *s) =20 DO_ZPZZ_FP(sve_fscalbn_h, int16_t, H1_2, float16_scalbn) DO_ZPZZ_FP(sve_fscalbn_s, int32_t, H1_4, float32_scalbn) -DO_ZPZZ_FP(sve_fscalbn_d, int64_t, , scalbn_d) +DO_ZPZZ_FP(sve_fscalbn_d, int64_t, H1_8, scalbn_d) =20 DO_ZPZZ_FP(sve_fmulx_h, uint16_t, H1_2, helper_advsimd_mulxh) DO_ZPZZ_FP(sve_fmulx_s, uint32_t, H1_4, helper_vfp_mulxs) -DO_ZPZZ_FP(sve_fmulx_d, uint64_t, , helper_vfp_mulxd) +DO_ZPZZ_FP(sve_fmulx_d, uint64_t, H1_8, helper_vfp_mulxd) =20 #undef DO_ZPZZ_FP =20 @@ -4521,15 +4521,15 @@ void HELPER(NAME)(void *vd, void *vn, void *vg, uin= t64_t scalar, \ =20 DO_ZPZS_FP(sve_fadds_h, float16, H1_2, float16_add) DO_ZPZS_FP(sve_fadds_s, float32, H1_4, float32_add) -DO_ZPZS_FP(sve_fadds_d, float64, , float64_add) +DO_ZPZS_FP(sve_fadds_d, float64, H1_8, float64_add) =20 DO_ZPZS_FP(sve_fsubs_h, float16, H1_2, float16_sub) DO_ZPZS_FP(sve_fsubs_s, float32, H1_4, float32_sub) -DO_ZPZS_FP(sve_fsubs_d, float64, , float64_sub) +DO_ZPZS_FP(sve_fsubs_d, float64, H1_8, float64_sub) =20 DO_ZPZS_FP(sve_fmuls_h, float16, H1_2, float16_mul) DO_ZPZS_FP(sve_fmuls_s, float32, H1_4, float32_mul) -DO_ZPZS_FP(sve_fmuls_d, float64, , float64_mul) +DO_ZPZS_FP(sve_fmuls_d, float64, H1_8, float64_mul) =20 static inline float16 subr_h(float16 a, float16 b, float_status *s) { @@ -4548,23 +4548,23 @@ static inline float64 subr_d(float64 a, float64 b, = float_status *s) =20 DO_ZPZS_FP(sve_fsubrs_h, float16, H1_2, subr_h) DO_ZPZS_FP(sve_fsubrs_s, float32, H1_4, subr_s) -DO_ZPZS_FP(sve_fsubrs_d, float64, , subr_d) +DO_ZPZS_FP(sve_fsubrs_d, float64, H1_8, subr_d) =20 DO_ZPZS_FP(sve_fmaxnms_h, float16, H1_2, float16_maxnum) DO_ZPZS_FP(sve_fmaxnms_s, float32, H1_4, float32_maxnum) -DO_ZPZS_FP(sve_fmaxnms_d, float64, , float64_maxnum) +DO_ZPZS_FP(sve_fmaxnms_d, float64, H1_8, float64_maxnum) =20 DO_ZPZS_FP(sve_fminnms_h, float16, H1_2, float16_minnum) DO_ZPZS_FP(sve_fminnms_s, float32, H1_4, float32_minnum) -DO_ZPZS_FP(sve_fminnms_d, float64, , float64_minnum) +DO_ZPZS_FP(sve_fminnms_d, float64, H1_8, float64_minnum) =20 DO_ZPZS_FP(sve_fmaxs_h, float16, H1_2, float16_max) DO_ZPZS_FP(sve_fmaxs_s, float32, H1_4, float32_max) -DO_ZPZS_FP(sve_fmaxs_d, float64, , float64_max) +DO_ZPZS_FP(sve_fmaxs_d, float64, H1_8, float64_max) =20 DO_ZPZS_FP(sve_fmins_h, float16, H1_2, float16_min) DO_ZPZS_FP(sve_fmins_s, float32, H1_4, float32_min) -DO_ZPZS_FP(sve_fmins_d, float64, , float64_min) +DO_ZPZS_FP(sve_fmins_d, float64, H1_8, float64_min) =20 /* Fully general two-operand expander, controlled by a predicate, * With the extra float_status parameter. @@ -4709,58 +4709,58 @@ static inline uint64_t vfp_float64_to_uint64_rtz(fl= oat64 f, float_status *s) DO_ZPZ_FP(sve_fcvt_sh, uint32_t, H1_4, sve_f32_to_f16) DO_ZPZ_FP(sve_fcvt_hs, uint32_t, H1_4, sve_f16_to_f32) DO_ZPZ_FP(sve_bfcvt, uint32_t, H1_4, float32_to_bfloat16) -DO_ZPZ_FP(sve_fcvt_dh, uint64_t, , sve_f64_to_f16) -DO_ZPZ_FP(sve_fcvt_hd, uint64_t, , sve_f16_to_f64) -DO_ZPZ_FP(sve_fcvt_ds, uint64_t, , float64_to_float32) -DO_ZPZ_FP(sve_fcvt_sd, uint64_t, , float32_to_float64) +DO_ZPZ_FP(sve_fcvt_dh, uint64_t, H1_8, sve_f64_to_f16) +DO_ZPZ_FP(sve_fcvt_hd, uint64_t, H1_8, sve_f16_to_f64) +DO_ZPZ_FP(sve_fcvt_ds, uint64_t, H1_8, float64_to_float32) +DO_ZPZ_FP(sve_fcvt_sd, uint64_t, H1_8, float32_to_float64) =20 DO_ZPZ_FP(sve_fcvtzs_hh, uint16_t, H1_2, vfp_float16_to_int16_rtz) DO_ZPZ_FP(sve_fcvtzs_hs, uint32_t, H1_4, helper_vfp_tosizh) DO_ZPZ_FP(sve_fcvtzs_ss, uint32_t, H1_4, helper_vfp_tosizs) -DO_ZPZ_FP(sve_fcvtzs_hd, uint64_t, , vfp_float16_to_int64_rtz) -DO_ZPZ_FP(sve_fcvtzs_sd, uint64_t, , vfp_float32_to_int64_rtz) -DO_ZPZ_FP(sve_fcvtzs_ds, uint64_t, , helper_vfp_tosizd) -DO_ZPZ_FP(sve_fcvtzs_dd, uint64_t, , vfp_float64_to_int64_rtz) +DO_ZPZ_FP(sve_fcvtzs_hd, uint64_t, H1_8, vfp_float16_to_int64_rtz) +DO_ZPZ_FP(sve_fcvtzs_sd, uint64_t, H1_8, vfp_float32_to_int64_rtz) +DO_ZPZ_FP(sve_fcvtzs_ds, uint64_t, H1_8, helper_vfp_tosizd) +DO_ZPZ_FP(sve_fcvtzs_dd, uint64_t, H1_8, vfp_float64_to_int64_rtz) =20 DO_ZPZ_FP(sve_fcvtzu_hh, uint16_t, H1_2, vfp_float16_to_uint16_rtz) DO_ZPZ_FP(sve_fcvtzu_hs, uint32_t, H1_4, helper_vfp_touizh) DO_ZPZ_FP(sve_fcvtzu_ss, uint32_t, H1_4, helper_vfp_touizs) -DO_ZPZ_FP(sve_fcvtzu_hd, uint64_t, , vfp_float16_to_uint64_rtz) -DO_ZPZ_FP(sve_fcvtzu_sd, uint64_t, , vfp_float32_to_uint64_rtz) -DO_ZPZ_FP(sve_fcvtzu_ds, uint64_t, , helper_vfp_touizd) -DO_ZPZ_FP(sve_fcvtzu_dd, uint64_t, , vfp_float64_to_uint64_rtz) +DO_ZPZ_FP(sve_fcvtzu_hd, uint64_t, H1_8, vfp_float16_to_uint64_rtz) +DO_ZPZ_FP(sve_fcvtzu_sd, uint64_t, H1_8, vfp_float32_to_uint64_rtz) +DO_ZPZ_FP(sve_fcvtzu_ds, uint64_t, H1_8, helper_vfp_touizd) +DO_ZPZ_FP(sve_fcvtzu_dd, uint64_t, H1_8, vfp_float64_to_uint64_rtz) =20 DO_ZPZ_FP(sve_frint_h, uint16_t, H1_2, helper_advsimd_rinth) DO_ZPZ_FP(sve_frint_s, uint32_t, H1_4, helper_rints) -DO_ZPZ_FP(sve_frint_d, uint64_t, , helper_rintd) +DO_ZPZ_FP(sve_frint_d, uint64_t, H1_8, helper_rintd) =20 DO_ZPZ_FP(sve_frintx_h, uint16_t, H1_2, float16_round_to_int) DO_ZPZ_FP(sve_frintx_s, uint32_t, H1_4, float32_round_to_int) -DO_ZPZ_FP(sve_frintx_d, uint64_t, , float64_round_to_int) +DO_ZPZ_FP(sve_frintx_d, uint64_t, H1_8, float64_round_to_int) =20 DO_ZPZ_FP(sve_frecpx_h, uint16_t, H1_2, helper_frecpx_f16) DO_ZPZ_FP(sve_frecpx_s, uint32_t, H1_4, helper_frecpx_f32) -DO_ZPZ_FP(sve_frecpx_d, uint64_t, , helper_frecpx_f64) +DO_ZPZ_FP(sve_frecpx_d, uint64_t, H1_8, helper_frecpx_f64) =20 DO_ZPZ_FP(sve_fsqrt_h, uint16_t, H1_2, float16_sqrt) DO_ZPZ_FP(sve_fsqrt_s, uint32_t, H1_4, float32_sqrt) -DO_ZPZ_FP(sve_fsqrt_d, uint64_t, , float64_sqrt) +DO_ZPZ_FP(sve_fsqrt_d, uint64_t, H1_8, float64_sqrt) =20 DO_ZPZ_FP(sve_scvt_hh, uint16_t, H1_2, int16_to_float16) DO_ZPZ_FP(sve_scvt_sh, uint32_t, H1_4, int32_to_float16) DO_ZPZ_FP(sve_scvt_ss, uint32_t, H1_4, int32_to_float32) -DO_ZPZ_FP(sve_scvt_sd, uint64_t, , int32_to_float64) -DO_ZPZ_FP(sve_scvt_dh, uint64_t, , int64_to_float16) -DO_ZPZ_FP(sve_scvt_ds, uint64_t, , int64_to_float32) -DO_ZPZ_FP(sve_scvt_dd, uint64_t, , int64_to_float64) +DO_ZPZ_FP(sve_scvt_sd, uint64_t, H1_8, int32_to_float64) +DO_ZPZ_FP(sve_scvt_dh, uint64_t, H1_8, int64_to_float16) +DO_ZPZ_FP(sve_scvt_ds, uint64_t, H1_8, int64_to_float32) +DO_ZPZ_FP(sve_scvt_dd, uint64_t, H1_8, int64_to_float64) =20 DO_ZPZ_FP(sve_ucvt_hh, uint16_t, H1_2, uint16_to_float16) DO_ZPZ_FP(sve_ucvt_sh, uint32_t, H1_4, uint32_to_float16) DO_ZPZ_FP(sve_ucvt_ss, uint32_t, H1_4, uint32_to_float32) -DO_ZPZ_FP(sve_ucvt_sd, uint64_t, , uint32_to_float64) -DO_ZPZ_FP(sve_ucvt_dh, uint64_t, , uint64_to_float16) -DO_ZPZ_FP(sve_ucvt_ds, uint64_t, , uint64_to_float32) -DO_ZPZ_FP(sve_ucvt_dd, uint64_t, , uint64_to_float64) +DO_ZPZ_FP(sve_ucvt_sd, uint64_t, H1_8, uint32_to_float64) +DO_ZPZ_FP(sve_ucvt_dh, uint64_t, H1_8, uint64_to_float16) +DO_ZPZ_FP(sve_ucvt_ds, uint64_t, H1_8, uint64_to_float32) +DO_ZPZ_FP(sve_ucvt_dd, uint64_t, H1_8, uint64_to_float64) =20 static int16_t do_float16_logb_as_int(float16 a, float_status *s) { @@ -4848,7 +4848,7 @@ static int64_t do_float64_logb_as_int(float64 a, floa= t_status *s) =20 DO_ZPZ_FP(flogb_h, float16, H1_2, do_float16_logb_as_int) DO_ZPZ_FP(flogb_s, float32, H1_4, do_float32_logb_as_int) -DO_ZPZ_FP(flogb_d, float64, , do_float64_logb_as_int) +DO_ZPZ_FP(flogb_d, float64, H1_8, do_float64_logb_as_int) =20 #undef DO_ZPZ_FP =20 @@ -5026,7 +5026,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void = *vg, \ #define DO_FPCMP_PPZZ_S(NAME, OP) \ DO_FPCMP_PPZZ(NAME##_s, float32, H1_4, OP) #define DO_FPCMP_PPZZ_D(NAME, OP) \ - DO_FPCMP_PPZZ(NAME##_d, float64, , OP) + DO_FPCMP_PPZZ(NAME##_d, float64, H1_8, OP) =20 #define DO_FPCMP_PPZZ_ALL(NAME, OP) \ DO_FPCMP_PPZZ_H(NAME, OP) \ @@ -5087,7 +5087,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vg, = \ #define DO_FPCMP_PPZ0_S(NAME, OP) \ DO_FPCMP_PPZ0(NAME##_s, float32, H1_4, OP) #define DO_FPCMP_PPZ0_D(NAME, OP) \ - DO_FPCMP_PPZ0(NAME##_d, float64, , OP) + DO_FPCMP_PPZ0(NAME##_d, float64, H1_8, OP) =20 #define DO_FPCMP_PPZ0_ALL(NAME, OP) \ DO_FPCMP_PPZ0_H(NAME, OP) \ @@ -5467,8 +5467,8 @@ DO_LD_PRIM_1(ld1bhu, H1_2, uint16_t, uint8_t) DO_LD_PRIM_1(ld1bhs, H1_2, uint16_t, int8_t) DO_LD_PRIM_1(ld1bsu, H1_4, uint32_t, uint8_t) DO_LD_PRIM_1(ld1bss, H1_4, uint32_t, int8_t) -DO_LD_PRIM_1(ld1bdu, , uint64_t, uint8_t) -DO_LD_PRIM_1(ld1bds, , uint64_t, int8_t) +DO_LD_PRIM_1(ld1bdu, H1_8, uint64_t, uint8_t) +DO_LD_PRIM_1(ld1bds, H1_8, uint64_t, int8_t) =20 #define DO_ST_PRIM_1(NAME, H, TE, TM) \ DO_ST_HOST(st1##NAME, H, TE, TM, stb_p) \ @@ -5477,7 +5477,7 @@ DO_LD_PRIM_1(ld1bds, , uint64_t, int8_t) DO_ST_PRIM_1(bb, H1, uint8_t, uint8_t) DO_ST_PRIM_1(bh, H1_2, uint16_t, uint8_t) DO_ST_PRIM_1(bs, H1_4, uint32_t, uint8_t) -DO_ST_PRIM_1(bd, , uint64_t, uint8_t) +DO_ST_PRIM_1(bd, H1_8, uint64_t, uint8_t) =20 #define DO_LD_PRIM_2(NAME, H, TE, TM, LD) \ DO_LD_HOST(ld1##NAME##_be, H, TE, TM, LD##_be_p) \ @@ -5494,22 +5494,22 @@ DO_ST_PRIM_1(bd, , uint64_t, uint8_t) DO_LD_PRIM_2(hh, H1_2, uint16_t, uint16_t, lduw) DO_LD_PRIM_2(hsu, H1_4, uint32_t, uint16_t, lduw) DO_LD_PRIM_2(hss, H1_4, uint32_t, int16_t, lduw) -DO_LD_PRIM_2(hdu, , uint64_t, uint16_t, lduw) -DO_LD_PRIM_2(hds, , uint64_t, int16_t, lduw) +DO_LD_PRIM_2(hdu, H1_8, uint64_t, uint16_t, lduw) +DO_LD_PRIM_2(hds, H1_8, uint64_t, int16_t, lduw) =20 DO_ST_PRIM_2(hh, H1_2, uint16_t, uint16_t, stw) DO_ST_PRIM_2(hs, H1_4, uint32_t, uint16_t, stw) -DO_ST_PRIM_2(hd, , uint64_t, uint16_t, stw) +DO_ST_PRIM_2(hd, H1_8, uint64_t, uint16_t, stw) =20 DO_LD_PRIM_2(ss, H1_4, uint32_t, uint32_t, ldl) -DO_LD_PRIM_2(sdu, , uint64_t, uint32_t, ldl) -DO_LD_PRIM_2(sds, , uint64_t, int32_t, ldl) +DO_LD_PRIM_2(sdu, H1_8, uint64_t, uint32_t, ldl) +DO_LD_PRIM_2(sds, H1_8, uint64_t, int32_t, ldl) =20 DO_ST_PRIM_2(ss, H1_4, uint32_t, uint32_t, stl) -DO_ST_PRIM_2(sd, , uint64_t, uint32_t, stl) +DO_ST_PRIM_2(sd, H1_8, uint64_t, uint32_t, stl) =20 -DO_LD_PRIM_2(dd, , uint64_t, uint64_t, ldq) -DO_ST_PRIM_2(dd, , uint64_t, uint64_t, stq) +DO_LD_PRIM_2(dd, H1_8, uint64_t, uint64_t, ldq) +DO_ST_PRIM_2(dd, H1_8, uint64_t, uint64_t, stq) =20 #undef DO_LD_TLB #undef DO_ST_TLB @@ -7743,7 +7743,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vg, void = *status, uint32_t desc) \ =20 DO_FCVTNT(sve_bfcvtnt, uint32_t, uint16_t, H1_4, H1_2, float32_to_bfloa= t16) DO_FCVTNT(sve2_fcvtnt_sh, uint32_t, uint16_t, H1_4, H1_2, sve_f32_to_f16) -DO_FCVTNT(sve2_fcvtnt_ds, uint64_t, uint32_t, , H1_4, float64_to_float= 32) +DO_FCVTNT(sve2_fcvtnt_ds, uint64_t, uint32_t, H1_8, H1_4, float64_to_float= 32) =20 #define DO_FCVTLT(NAME, TYPEW, TYPEN, HW, HN, OP) = \ void HELPER(NAME)(void *vd, void *vn, void *vg, void *status, uint32_t des= c) \ @@ -7763,7 +7763,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vg, void = *status, uint32_t desc) \ } =20 DO_FCVTLT(sve2_fcvtlt_hs, uint32_t, uint16_t, H1_4, H1_2, sve_f16_to_f32) -DO_FCVTLT(sve2_fcvtlt_sd, uint64_t, uint32_t, , H1_4, float32_to_float= 64) +DO_FCVTLT(sve2_fcvtlt_sd, uint64_t, uint32_t, H1_8, H1_4, float32_to_float= 64) =20 #undef DO_FCVTLT #undef DO_FCVTNT diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 5862f187cdc..e8138d3d222 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -589,8 +589,8 @@ DO_DOT_IDX(gvec_sdot_idx_b, int32_t, int8_t, int8_t, H4) DO_DOT_IDX(gvec_udot_idx_b, uint32_t, uint8_t, uint8_t, H4) DO_DOT_IDX(gvec_sudot_idx_b, int32_t, int8_t, uint8_t, H4) DO_DOT_IDX(gvec_usdot_idx_b, int32_t, uint8_t, int8_t, H4) -DO_DOT_IDX(gvec_sdot_idx_h, int64_t, int16_t, int16_t, ) -DO_DOT_IDX(gvec_udot_idx_h, uint64_t, uint16_t, uint16_t, ) +DO_DOT_IDX(gvec_sdot_idx_h, int64_t, int16_t, int16_t, H8) +DO_DOT_IDX(gvec_udot_idx_h, uint64_t, uint16_t, uint16_t, H8) =20 void HELPER(gvec_fcaddh)(void *vd, void *vn, void *vm, void *vfpst, uint32_t desc) @@ -1226,7 +1226,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, uint3= 2_t desc) \ =20 DO_MUL_IDX(gvec_mul_idx_h, uint16_t, H2) DO_MUL_IDX(gvec_mul_idx_s, uint32_t, H4) -DO_MUL_IDX(gvec_mul_idx_d, uint64_t, ) +DO_MUL_IDX(gvec_mul_idx_d, uint64_t, H8) =20 #undef DO_MUL_IDX =20 @@ -1248,11 +1248,11 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, voi= d *va, uint32_t desc) \ =20 DO_MLA_IDX(gvec_mla_idx_h, uint16_t, +, H2) DO_MLA_IDX(gvec_mla_idx_s, uint32_t, +, H4) -DO_MLA_IDX(gvec_mla_idx_d, uint64_t, +, ) +DO_MLA_IDX(gvec_mla_idx_d, uint64_t, +, H8) =20 DO_MLA_IDX(gvec_mls_idx_h, uint16_t, -, H2) DO_MLA_IDX(gvec_mls_idx_s, uint32_t, -, H4) -DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -, ) +DO_MLA_IDX(gvec_mls_idx_d, uint64_t, -, H8) =20 #undef DO_MLA_IDX =20 @@ -1279,7 +1279,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void = *stat, uint32_t desc) \ =20 DO_FMUL_IDX(gvec_fmul_idx_h, nop, float16, H2) DO_FMUL_IDX(gvec_fmul_idx_s, nop, float32, H4) -DO_FMUL_IDX(gvec_fmul_idx_d, nop, float64, ) +DO_FMUL_IDX(gvec_fmul_idx_d, nop, float64, H8) =20 /* * Non-fused multiply-accumulate operations, for Neon. NB that unlike @@ -1317,7 +1317,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void = *va, \ =20 DO_FMLA_IDX(gvec_fmla_idx_h, float16, H2) DO_FMLA_IDX(gvec_fmla_idx_s, float32, H4) -DO_FMLA_IDX(gvec_fmla_idx_d, float64, ) +DO_FMLA_IDX(gvec_fmla_idx_d, float64, H8) =20 #undef DO_FMLA_IDX =20 --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772752; cv=none; d=zohomail.com; s=zohoarc; b=iZEmbfkc++ujmQMg+k7B7HyljQ9+QWbosz70PWwxdnsnejvtAP0MFkAgCurk8aSJUlkgw2oRzEomyPYFd20OB3ENKJ2C7L98bbKJbp1lItlcW4HA0Xpp9WwNTJU3B8IaMQiBjkhW36fcrMwbdfiGs5lVqmK9wnjWeL64ujWjIy0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623772752; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dtHPlAMnuNbx8TL22PoH6JwnBqAMfrMcVsXNwlYCfRE=; b=Exlv573xdcqMCd+x1QVGgIZU14w/QvZHrLZx5k3+m0OgAOMiOeLCimSPodf0b/VZPYZdADEBiaFj3fXfmVAtke2b6JP+/4375/M5cJGGCM9X3cwji3cSl5QGNgW+0aeDMGI52l1hFrxNBXCp1hdq0qJiqyEkgsd4sR5jpKETIGI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162377275267465.94315611998002; Tue, 15 Jun 2021 08:59:12 -0700 (PDT) Received: from localhost ([::1]:57036 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBT5-0001rb-1j for importer@patchew.org; Tue, 15 Jun 2021 11:59:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43098) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBFK-0006ZM-PP for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:58 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:46675) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEj-0000zE-Ud for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:58 -0400 Received: by mail-wr1-x42f.google.com with SMTP id a11so18852505wrt.13 for ; Tue, 15 Jun 2021 08:44:21 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=dtHPlAMnuNbx8TL22PoH6JwnBqAMfrMcVsXNwlYCfRE=; b=Tff1KRpTD+7Dud2cPiK02DGH0D86bnJlSObKKF064JPAKgKfQRzaCJLpprKp+TNFPx o8jwDyYDL/zZj+F/VrBCAc01Yj/dDRsgaW3VlQWsc/Fk7HI5LTkejcacwHFYdDw8vmQY t6r4Q/Y0x3jpSen1nRrXVN4qOoDHTBJ5SYNcjTmrReP+xD6Ncq1PMnYrvmDQdQrXZpAB bpEZS42mvsOoBjCqEfY4z0BenM1BArYEBnpMb6407Ss5cf9OtmxiAQJujqUCOYWsjW1c jTFpmobye9G/bazo8toOpjswO96ndW9Opi+e1MkYobXiWf/36voY3JPvkVY/i+SD9qmW nB8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dtHPlAMnuNbx8TL22PoH6JwnBqAMfrMcVsXNwlYCfRE=; b=LUdLtPyIegXVpgmU61sAGsd6tus6IZOLSEN+UFtYww1yxUOEe9Y8oK/dZ1lmLF5l6O uZ5cC3nLcmULdpLIOkB+vyV/QIJU4AKR563EnSoukBOlQdVV5G397lPy7zm/MLWlUcQs Bw/lcZmENmFneK7nLQ/nTz7Kvdq7bQWPd6yWMw7LEEuZ3Z4IFs8SkHRBS2nf0fLnt8Xy TvvRemQksPKvcCoWqEG9sn5UtjYmGemfJ6U72ftJKLUkLArYaH35fVbR9ipo7YPNxDfb EZkA/+01roUw6GY3BahDGXOC6DNBptflGGMd/7UDiwo5bNnqs3gDddj82Y8IzoqSvGXa YEpQ== X-Gm-Message-State: AOAM530pCk0RCncY4MPOC9PQx8Md+ZhDr6S7zCd8xFoTipEOaxbAS2Dj T5KGW9gXo8zcTAdYmGDl8soWctNnGAtARA== X-Google-Smtp-Source: ABdhPJxgyPeVdsajBeIGBmzFpL2JDSuGR6YFwYa77HTSSMg95OuQlso9n7PFjt1Zs1k6tECvlKs4Gg== X-Received: by 2002:a5d:4c4b:: with SMTP id n11mr26251217wrt.269.1623771860541; Tue, 15 Jun 2021 08:44:20 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/28] target/arm: Enable FPSCR.QC bit for MVE Date: Tue, 15 Jun 2021 16:43:54 +0100 Message-Id: <20210615154405.21399-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" MVE has an FPSCR.QC bit similar to the A-profile Neon one; when MVE is implemented make the bit writeable, both in the generic "load and store FPSCR" helper functions and in the code for handling the NZCVQC sysreg which we had previously left as "TODO when we implement MVE". Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210614151007.4545-3-peter.maydell@linaro.org --- target/arm/translate-vfp.c | 30 +++++++++++++++++++++--------- target/arm/vfp_helper.c | 3 ++- 2 files changed, 23 insertions(+), 10 deletions(-) diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index d01e465821b..728856dfd45 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -784,10 +784,17 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, in= t regno, { TCGv_i32 fpscr; tmp =3D loadfn(s, opaque); - /* - * TODO: when we implement MVE, write the QC bit. - * For non-MVE, QC is RES0. - */ + if (dc_isar_feature(aa32_mve, s)) { + /* QC is only present for MVE; otherwise RES0 */ + TCGv_i32 qc =3D tcg_temp_new_i32(); + tcg_gen_andi_i32(qc, tmp, FPCR_QC); + /* + * The 4 vfp.qc[] fields need only be "zero" vs "non-zero"; + * here writing the same value into all elements is simplest. + */ + tcg_gen_gvec_dup_i32(MO_32, offsetof(CPUARMState, vfp.qc), + 16, 16, qc); + } tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); fpscr =3D load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK); @@ -869,6 +876,11 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int = regno, break; } =20 + if (regno =3D=3D ARM_VFP_FPSCR_NZCVQC && !dc_isar_feature(aa32_mve, s)= ) { + /* QC is RES0 without MVE, so NZCVQC simplifies to NZCV */ + regno =3D QEMU_VFP_FPSCR_NZCV; + } + switch (regno) { case ARM_VFP_FPSCR: tmp =3D tcg_temp_new_i32(); @@ -876,11 +888,11 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int= regno, storefn(s, opaque, tmp); break; case ARM_VFP_FPSCR_NZCVQC: - /* - * TODO: MVE has a QC bit, which we probably won't store - * in the xregs[] field. For non-MVE, where QC is RES0, - * we can just fall through to the FPSCR_NZCV case. - */ + tmp =3D tcg_temp_new_i32(); + gen_helper_vfp_get_fpscr(tmp, cpu_env); + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCVQC_MASK); + storefn(s, opaque, tmp); + break; case QEMU_VFP_FPSCR_NZCV: /* * Read just NZCV; this is a special case to avoid the diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 496f0034772..8a716600592 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -220,7 +220,8 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t v= al) FPCR_LTPSIZE_LENGTH); } =20 - if (arm_feature(env, ARM_FEATURE_NEON)) { + if (arm_feature(env, ARM_FEATURE_NEON) || + cpu_isar_feature(aa32_mve, cpu)) { /* * The bit we set within fpscr_q is arbitrary; the register as a * whole being zero/non-zero is what counts. --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772900; cv=none; d=zohomail.com; s=zohoarc; b=gz/cZVCWp5VgnjT5wSd+tb7RBYUbV0KvM+NW8/LfPyI1/QtmjU5Zu3zs1GZrerDSDW5VedIn18qGHvpCsrfhaV9D9myIa1zI4CugD4MnW0sKcKLqg/1Q6OgiqPY62O4uszF9uQv3vht7JQx77W5C0R1U4fGr9V47T/0TKif0aDc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623772900; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=a+GQNN1UL8NRKk5tFdcVGCreZz6GM8M7oR4GW+pM1Jw=; b=c8mEDqM2964qTczxqo7CnCKO8coHH4EhBu2zYWpX6TzrkEHHVaMZYv3wRYj8goQyXnbS5AXvXVpkrWb5J9Vd79T02C5sfM6MlskUIEykiD4CxxCYBEua0cPion/G2qUnApN6LvnUoijC7tWVcPcWl538/dZBkdJG6qeq7dpzj3k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623772900320858.2757078569497; Tue, 15 Jun 2021 09:01:40 -0700 (PDT) Received: from localhost ([::1]:33398 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBVS-00057T-Vf for importer@patchew.org; Tue, 15 Jun 2021 12:01:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43062) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBFJ-0006Wz-3Z for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:57 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:33393) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEl-0000zM-Nz for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:56 -0400 Received: by mail-wr1-x42d.google.com with SMTP id a20so18906913wrc.0 for ; Tue, 15 Jun 2021 08:44:22 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=a+GQNN1UL8NRKk5tFdcVGCreZz6GM8M7oR4GW+pM1Jw=; b=B1l6rsS0aTKySmY/naIsis7oUgJyzX7n8VLNKqJXmAlmPKeg94aK0uX7itixVQH2D0 Bu4EW3JSujwMBhYsyv1hcht+wBkQIFkMRCddnYBponjxph1oV9jvT/Fhj6IBOe24biLo a917ScW4k87C6L+GekwU7RuMWy9CeL7NlV8rq9VNqxnGRCqrze4nY507ajv2XN/8PvGJ ckbHm6fwl2GRz/GOQHugsOLhBXFQ6w3+5xVF24LYyAhCTLFerwYWnNx/4YMwAnjW/4G+ zFk7X40BiInwFWDsL529I0+HQ83XrJ/T78I0K4d1E+rdgfD5yiiFyFBSkT0U5xBFlt8Y Fp+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a+GQNN1UL8NRKk5tFdcVGCreZz6GM8M7oR4GW+pM1Jw=; b=adPXVbAzSj/K7fgyiTLd9XXIsezRfbsQhHikoeCuzfDugC9WF2cQSQZ9hOx0TT6lJG dzcqBtCqCH9CclmOJ2wTQF0nJH6KqWFqwwxEQsRTAs0kP2bPYy2lXFVvgXP0041vva1q Qh3R7y2KOX+n/f/vvXxzAtAa4fsw3zv7nDvu6krtdu3G3FrMvw2kkJTvKpB7DoZYjmiv nxmhLnrd3ZEbZKgCKMyZR/y+11RhTiv5MmA7efm2YzWry11WJ7s7zeZl5TOwo+de1WXP JNhzX7BATerd8IVrnQNHkf2l7EOPcuVKM5go+zXDe/3Z16Uax2vi11CtjbSu+egB5akl nWtA== X-Gm-Message-State: AOAM530UXvK1y8ES4w8TVhHBzaNmlq8O/u+jlXFEfmXtAtMuQktnH7gR Gmt8l0/TPS/5YE6tr6tFGaL2IHPGQ+wxdA== X-Google-Smtp-Source: ABdhPJy3q5IPsWT2RL/d8WU4ATwWS+++ZIsXwOLN6j74g3r0gzpgr1VThDQFF4T26ZOjbuahUmoz+A== X-Received: by 2002:adf:ed8d:: with SMTP id c13mr26700076wro.164.1623771861277; Tue, 15 Jun 2021 08:44:21 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/28] target/arm: Handle VPR semantics in existing code Date: Tue, 15 Jun 2021 16:43:55 +0100 Message-Id: <20210615154405.21399-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" When MVE is supported, the VPR register has a place on the exception stack frame in a previously reserved slot just above the FPSCR. It must also be zeroed in various situations when we invalidate FPU context. Update the code which handles the stack frames (exception entry and exit code, VLLDM, and VLSTM) to save/restore VPR. Update code which invalidates FP registers (mostly also exception entry and exit code, but also VSCCLRM and the code in full_vfp_access_check() that corresponds to the ExecuteFPCheck() pseudocode) to zero VPR. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210614151007.4545-4-peter.maydell@linaro.org --- target/arm/m_helper.c | 54 +++++++++++++++++++++++++++++------ target/arm/translate-m-nocp.c | 5 +++- target/arm/translate-vfp.c | 9 ++++-- 3 files changed, 57 insertions(+), 11 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 074c5434550..7a1e35ab5b6 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -378,7 +378,7 @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env) uint32_t shi =3D extract64(dn, 32, 32); =20 if (i >=3D 16) { - faddr +=3D 8; /* skip the slot for the FPSCR */ + faddr +=3D 8; /* skip the slot for the FPSCR/VPR */ } stacked_ok =3D stacked_ok && v7m_stack_write(cpu, faddr, slo, mmu_idx, STACK_LAZYFP) && @@ -388,6 +388,11 @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env) stacked_ok =3D stacked_ok && v7m_stack_write(cpu, fpcar + 0x40, vfp_get_fpscr(env), mmu_idx, STACK_LAZYFP); + if (cpu_isar_feature(aa32_mve, cpu)) { + stacked_ok =3D stacked_ok && + v7m_stack_write(cpu, fpcar + 0x44, + env->v7m.vpr, mmu_idx, STACK_LAZYFP); + } } =20 /* @@ -410,16 +415,19 @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env) env->v7m.fpccr[is_secure] &=3D ~R_V7M_FPCCR_LSPACT_MASK; =20 if (ts) { - /* Clear s0 to s31 and the FPSCR */ + /* Clear s0 to s31 and the FPSCR and VPR */ int i; =20 for (i =3D 0; i < 32; i +=3D 2) { *aa32_vfp_dreg(env, i / 2) =3D 0; } vfp_set_fpscr(env, 0); + if (cpu_isar_feature(aa32_mve, cpu)) { + env->v7m.vpr =3D 0; + } } /* - * Otherwise s0 to s15 and FPSCR are UNKNOWN; we choose to leave them + * Otherwise s0 to s15, FPSCR and VPR are UNKNOWN; we choose to leave = them * unchanged. */ } @@ -1044,6 +1052,7 @@ static void v7m_update_fpccr(CPUARMState *env, uint32= _t frameptr, void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) { /* fptr is the value of Rn, the frame pointer we store the FP regs to = */ + ARMCPU *cpu =3D env_archcpu(env); bool s =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; bool lspact =3D env->v7m.fpccr[s] & R_V7M_FPCCR_LSPACT_MASK; uintptr_t ra =3D GETPC(); @@ -1092,9 +1101,12 @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fp= tr) cpu_stl_data_ra(env, faddr + 4, shi, ra); } cpu_stl_data_ra(env, fptr + 0x40, vfp_get_fpscr(env), ra); + if (cpu_isar_feature(aa32_mve, cpu)) { + cpu_stl_data_ra(env, fptr + 0x44, env->v7m.vpr, ra); + } =20 /* - * If TS is 0 then s0 to s15 and FPSCR are UNKNOWN; we choose to + * If TS is 0 then s0 to s15, FPSCR and VPR are UNKNOWN; we choose= to * leave them unchanged, matching our choice in v7m_preserve_fp_st= ate. */ if (ts) { @@ -1102,6 +1114,9 @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fpt= r) *aa32_vfp_dreg(env, i / 2) =3D 0; } vfp_set_fpscr(env, 0); + if (cpu_isar_feature(aa32_mve, cpu)) { + env->v7m.vpr =3D 0; + } } } else { v7m_update_fpccr(env, fptr, false); @@ -1112,6 +1127,7 @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fpt= r) =20 void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr) { + ARMCPU *cpu =3D env_archcpu(env); uintptr_t ra =3D GETPC(); =20 /* fptr is the value of Rn, the frame pointer we load the FP regs from= */ @@ -1144,7 +1160,7 @@ void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fpt= r) uint32_t faddr =3D fptr + 4 * i; =20 if (i >=3D 16) { - faddr +=3D 8; /* skip the slot for the FPSCR */ + faddr +=3D 8; /* skip the slot for the FPSCR and VPR */ } =20 slo =3D cpu_ldl_data_ra(env, faddr, ra); @@ -1155,6 +1171,9 @@ void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fpt= r) } fpscr =3D cpu_ldl_data_ra(env, fptr + 0x40, ra); vfp_set_fpscr(env, fpscr); + if (cpu_isar_feature(aa32_mve, cpu)) { + env->v7m.vpr =3D cpu_ldl_data_ra(env, fptr + 0x44, ra); + } } =20 env->v7m.control[M_REG_S] |=3D R_V7M_CONTROL_FPCA_MASK; @@ -1298,7 +1317,7 @@ static bool v7m_push_stack(ARMCPU *cpu) uint32_t shi =3D extract64(dn, 32, 32); =20 if (i >=3D 16) { - faddr +=3D 8; /* skip the slot for the FPSCR */ + faddr +=3D 8; /* skip the slot for the FPSCR and V= PR */ } stacked_ok =3D stacked_ok && v7m_stack_write(cpu, faddr, slo, @@ -1309,11 +1328,19 @@ static bool v7m_push_stack(ARMCPU *cpu) stacked_ok =3D stacked_ok && v7m_stack_write(cpu, frameptr + 0x60, vfp_get_fpscr(env), mmu_idx, STACK_NOR= MAL); + if (cpu_isar_feature(aa32_mve, cpu)) { + stacked_ok =3D stacked_ok && + v7m_stack_write(cpu, frameptr + 0x64, + env->v7m.vpr, mmu_idx, STACK_NORMA= L); + } if (cpacr_pass) { for (i =3D 0; i < ((framesize =3D=3D 0xa8) ? 32 : 16);= i +=3D 2) { *aa32_vfp_dreg(env, i / 2) =3D 0; } vfp_set_fpscr(env, 0); + if (cpu_isar_feature(aa32_mve, cpu)) { + env->v7m.vpr =3D 0; + } } } else { /* Lazy stacking enabled, save necessary info to stack lat= er */ @@ -1536,13 +1563,16 @@ static void do_v7m_exception_exit(ARMCPU *cpu) v7m_exception_taken(cpu, excret, true, false); } } - /* Clear s0..s15 and FPSCR; TODO also VPR when MVE is implemen= ted */ + /* Clear s0..s15, FPSCR and VPR */ int i; =20 for (i =3D 0; i < 16; i +=3D 2) { *aa32_vfp_dreg(env, i / 2) =3D 0; } vfp_set_fpscr(env, 0); + if (cpu_isar_feature(aa32_mve, cpu)) { + env->v7m.vpr =3D 0; + } } } =20 @@ -1771,7 +1801,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) uint32_t faddr =3D frameptr + 0x20 + 4 * i; =20 if (i >=3D 16) { - faddr +=3D 8; /* Skip the slot for the FPSCR */ + faddr +=3D 8; /* Skip the slot for the FPSCR and V= PR */ } =20 pop_ok =3D pop_ok && @@ -1790,6 +1820,11 @@ static void do_v7m_exception_exit(ARMCPU *cpu) if (pop_ok) { vfp_set_fpscr(env, fpscr); } + if (cpu_isar_feature(aa32_mve, cpu)) { + pop_ok =3D pop_ok && + v7m_stack_read(cpu, &env->v7m.vpr, + frameptr + 0x64, mmu_idx); + } if (!pop_ok) { /* * These regs are 0 if security extension present; @@ -1799,6 +1834,9 @@ static void do_v7m_exception_exit(ARMCPU *cpu) *aa32_vfp_dreg(env, i / 2) =3D 0; } vfp_set_fpscr(env, 0); + if (cpu_isar_feature(aa32_mve, cpu)) { + env->v7m.vpr =3D 0; + } } } } diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c index d47eb8e1535..365810e582d 100644 --- a/target/arm/translate-m-nocp.c +++ b/target/arm/translate-m-nocp.c @@ -173,7 +173,10 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM= *a) btmreg++; } assert(btmreg =3D=3D topreg + 1); - /* TODO: when MVE is implemented, zero VPR here */ + if (dc_isar_feature(aa32_mve, s)) { + TCGv_i32 z32 =3D tcg_const_i32(0); + store_cpu_field(z32, v7m.vpr); + } return true; } =20 diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 728856dfd45..49f44347ad9 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -180,8 +180,8 @@ static bool full_vfp_access_check(DisasContext *s, bool= ignore_vfp_enabled) =20 if (s->v7m_new_fp_ctxt_needed) { /* - * Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA - * and the FPSCR. + * Create new FP context by updating CONTROL.FPCA, CONTROL.SFP= A, + * the FPSCR, and VPR. */ TCGv_i32 control, fpscr; uint32_t bits =3D R_V7M_CONTROL_FPCA_MASK; @@ -189,6 +189,11 @@ static bool full_vfp_access_check(DisasContext *s, boo= l ignore_vfp_enabled) fpscr =3D load_cpu_field(v7m.fpdscr[s->v8m_secure]); gen_helper_vfp_set_fpscr(cpu_env, fpscr); tcg_temp_free_i32(fpscr); + if (dc_isar_feature(aa32_mve, s)) { + TCGv_i32 z32 =3D tcg_const_i32(0); + store_cpu_field(z32, v7m.vpr); + } + /* * We don't need to arrange to end the TB, because the only * parts of FPSCR which we cache in the TB flags are the VECLEN --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772428; cv=none; d=zohomail.com; s=zohoarc; b=edbo7+eWkBXfrc4BOzL6S0tTg6Sfkq7KqrnpM5n7flfY6ePk8xLVdAnLbcedx7SiOQKAtRro4qGWIv1L3v0NykwRf4B0Y83IFziPYQbSqY3k5AK9TVxWK/Llf3Ozt29tKA1JIx/SgKcxhvXZluq9aK0/fPQOveAm9uYoDq414Bg= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=fmoe88j2BjlAkr54G4AmGKFzL0Fblx4LyHgbg6kEfmg=; b=hauI+NrPzUsTqwpevBB++V/IxbRY1W2JnQoPIRVpwSOJhrJYd9RCXbvhfzpDbt9/PY iuDD2qfRfiDq3dGN0yUFrhLAJJkmY2NlVk+K+qUlA2kTXDCA0o5vrB//1HuThltmwYq1 asJ2Gcf3Bm8vuy+bj91ySIxnCAxPTfewo7Tfok+6ajvz8EFFdye4fefGu9XnzD4zrNVI xfGYkhzSxSE++n4JOwnFWbrstdRfA+OeEL5Yw67YEWhsVgeK7P8GNmNTjPT0l7nr+1rr 2V41v34Pml6LPSkZKpVmNm519P5JnVgqTzjIdgyJnTSJcoOKdcT3QamyhT0DIY5APlk8 SJ7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fmoe88j2BjlAkr54G4AmGKFzL0Fblx4LyHgbg6kEfmg=; b=FW4pWBdjNQ4EmSkYVCg3gZ8xAsHCEClxryvmLZDTwIgoUFFNGqGSEvciHrXkwNgDbD dQ1W2jqcV8GnBv0Bt08/ThYBh0x4A6vOl82/oZOIEYh7AaztxEHWs6KRR5UdTuY/Tizo MPat2byzA2kWG/C3gPPk61Km110dn57aCZzh2xAaSBHF1Us+F1UEXH9DXIzH9OUX8eW8 jnLUeo0/5QMV8iGolQS5uyGxFaeEpWM4Rk741Do1rd6xjUZ60XPchZOxsyOdfkEmBj0c 2Qmz8ORmjgR5rZxwSUd5AL/HARypZeZrt+8IQWU648kMVIPJ5SZpY+qOP/SyIk/Y2Pis VLDQ== X-Gm-Message-State: AOAM5316vpd/8Bk1iFPfh9QFEkhIMFrO5j7QLhAUOqSsLtfBTqlGEZGT hBziAcmom9H38UKrZ18T4lelFtL8JgEhLA== X-Google-Smtp-Source: ABdhPJwUPHhSiyGZItPiEsW3ktPQCvDcFe5dEwhEg6yU1vj8vHAdpcSE1C8YW0o1HxXRgJafHtVaAw== X-Received: by 2002:a5d:4f05:: with SMTP id c5mr25864084wru.341.1623771862116; Tue, 15 Jun 2021 08:44:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/28] target/arm: Add handling for PSR.ECI/ICI Date: Tue, 15 Jun 2021 16:43:56 +0100 Message-Id: <20210615154405.21399-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" On A-profile, PSR bits [15:10][26:25] are always the IT state bits. On M-profile, some of the reserved encodings of the IT state are used to instead indicate partial progress through instructions that were interrupted partway through by an exception and can be resumed. These resumable instructions fall into two categories: (1) load/store multiple instructions, where these bits are called "ICI" and specify the register in the ldm/stm list where execution should resume. (Specifically: LDM, STM, VLDM, VSTM, VLLDM, VLSTM, CLRM, VSCCLRM.) (2) MVE instructions subject to beatwise execution, where these bits are called "ECI" and specify which beats in this and possibly also the following MVE insn have been executed. There are also a few insns (LE, LETP, and BKPT) which do not use the ICI/ECI bits but must leave them alone. Otherwise, we should raise an INVSTATE UsageFault for any attempt to execute an insn with non-zero ICI/ECI bits. So far we have been able to ignore ECI/ICI, because the architecture allows the IMPDEF choice of "always restart load/store multiple from the beginning regardless of ICI state", so the only thing we have been missing is that we don't raise the INVSTATE fault for bad guest code. However, MVE requires that we honour ECI bits and do not rexecute beats of an insn that have already been executed. Add the support in the decoder for handling ECI/ICI: * identify the ECI/ICI case in the CONDEXEC TB flags * when a load/store multiple insn succeeds, it updates the ECI/ICI state (both in DisasContext and in the CPU state), and sets a flag to say that the ECI/ICI state was handled * if we find that the insn we just decoded did not handle the ECI/ICI state, we delete all the code that we just generated for it and instead emit the code to raise the INVFAULT. This allows us to avoid having to update every non-MVE non-LDM/STM insn to make it check for "is ECI/ICI set?". We continue with our existing IMPDEF choice of not caring about the ICI state for the load/store multiples and simply restarting them from the beginning. Because we don't allow interrupts in the middle of an insn, the only way we would see this state is if the guest set ICI manually on return from an exception handler, so it's a corner case which doesn't merit optimisation. ICI update for LDM/STM is simple -- it always zeroes the state. ECI update for MVE beatwise insns will be a little more complex, since the ECI state may include information for the following insn. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210614151007.4545-5-peter.maydell@linaro.org --- target/arm/translate-a32.h | 1 + target/arm/translate.h | 9 +++ target/arm/translate-m-nocp.c | 11 ++++ target/arm/translate-vfp.c | 6 ++ target/arm/translate.c | 111 ++++++++++++++++++++++++++++++++-- 5 files changed, 133 insertions(+), 5 deletions(-) diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index c997f4e3216..c946ac440ce 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -44,6 +44,7 @@ long vfp_reg_offset(bool dp, unsigned reg); long neon_full_reg_offset(unsigned reg); long neon_element_offset(int reg, int element, MemOp memop); void gen_rev16(TCGv_i32 dest, TCGv_i32 var); +void clear_eci_state(DisasContext *s); =20 static inline TCGv_i32 load_cpu_offset(int offset) { diff --git a/target/arm/translate.h b/target/arm/translate.h index 12c28b0d32c..2821b325e33 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -21,6 +21,15 @@ typedef struct DisasContext { /* Thumb-2 conditional execution bits. */ int condexec_mask; int condexec_cond; + /* M-profile ECI/ICI exception-continuable instruction state */ + int eci; + /* + * trans_ functions for insns which are continuable should set this tr= ue + * after decode (ie after any UNDEF checks) + */ + bool eci_handled; + /* TCG op to rewind to if this turns out to be an invalid ECI state */ + TCGOp *insn_eci_rewind; int thumb; int sctlr_b; MemOp be_data; diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c index 365810e582d..09b3be4ed31 100644 --- a/target/arm/translate-m-nocp.c +++ b/target/arm/translate-m-nocp.c @@ -75,8 +75,12 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM= _VLSTM *a) unallocated_encoding(s); return true; } + + s->eci_handled =3D true; + /* If no fpu, NOP. */ if (!dc_isar_feature(aa32_vfp, s)) { + clear_eci_state(s); return true; } =20 @@ -88,6 +92,8 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_= VLSTM *a) } tcg_temp_free_i32(fptr); =20 + clear_eci_state(s); + /* End the TB, because we have updated FP control bits */ s->base.is_jmp =3D DISAS_UPDATE_EXIT; return true; @@ -110,8 +116,11 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM= *a) return true; } =20 + s->eci_handled =3D true; + if (!dc_isar_feature(aa32_vfp_simd, s)) { /* NOP if we have neither FP nor MVE */ + clear_eci_state(s); return true; } =20 @@ -177,6 +186,8 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM = *a) TCGv_i32 z32 =3D tcg_const_i32(0); store_cpu_field(z32, v7m.vpr); } + + clear_eci_state(s); return true; } =20 diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 49f44347ad9..2e12c694edc 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -1562,6 +1562,8 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_V= LDM_VSTM_sp *a) return false; } =20 + s->eci_handled =3D true; + if (!vfp_access_check(s)) { return true; } @@ -1611,6 +1613,7 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_V= LDM_VSTM_sp *a) tcg_temp_free_i32(addr); } =20 + clear_eci_state(s); return true; } =20 @@ -1645,6 +1648,8 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_V= LDM_VSTM_dp *a) return false; } =20 + s->eci_handled =3D true; + if (!vfp_access_check(s)) { return true; } @@ -1701,6 +1706,7 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_V= LDM_VSTM_dp *a) tcg_temp_free_i32(addr); } =20 + clear_eci_state(s); return true; } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 8e0e55c1e0f..f1c2074fa4a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -309,6 +309,19 @@ static inline bool is_singlestepping(DisasContext *s) return s->base.singlestep_enabled || s->ss_active; } =20 +void clear_eci_state(DisasContext *s) +{ + /* + * Clear any ECI/ICI state: used when a load multiple/store + * multiple insn executes. + */ + if (s->eci) { + TCGv_i32 tmp =3D tcg_const_i32(0); + store_cpu_field(tmp, condexec_bits); + s->eci =3D 0; + } +} + static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) { TCGv_i32 tmp1 =3D tcg_temp_new_i32(); @@ -6203,6 +6216,8 @@ static bool trans_BKPT(DisasContext *s, arg_BKPT *a) if (!ENABLE_ARCH_5) { return false; } + /* BKPT is OK with ECI set and leaves it untouched */ + s->eci_handled =3D true; if (arm_dc_feature(s, ARM_FEATURE_M) && semihosting_enabled() && #ifndef CONFIG_USER_ONLY @@ -7767,6 +7782,8 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a= , int min_n) return true; } =20 + s->eci_handled =3D true; + addr =3D op_addr_block_pre(s, a, n); mem_idx =3D get_mem_index(s); =20 @@ -7793,6 +7810,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a= , int min_n) } =20 op_addr_block_post(s, a, addr, n); + clear_eci_state(s); return true; } =20 @@ -7847,6 +7865,8 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a= , int min_n) return true; } =20 + s->eci_handled =3D true; + addr =3D op_addr_block_pre(s, a, n); mem_idx =3D get_mem_index(s); loaded_base =3D false; @@ -7897,6 +7917,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a= , int min_n) /* Must exit loop to check un-masked IRQs */ s->base.is_jmp =3D DISAS_EXIT; } + clear_eci_state(s); return true; } =20 @@ -7952,6 +7973,8 @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a) return false; } =20 + s->eci_handled =3D true; + zero =3D tcg_const_i32(0); for (i =3D 0; i < 15; i++) { if (extract32(a->list, i, 1)) { @@ -7969,6 +7992,7 @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a) tcg_temp_free_i32(maskreg); } tcg_temp_free_i32(zero); + clear_eci_state(s); return true; } =20 @@ -8150,6 +8174,9 @@ static bool trans_LE(DisasContext *s, arg_LE *a) return false; } =20 + /* LE/LETP is OK with ECI set and leaves it untouched */ + s->eci_handled =3D true; + if (!a->f) { /* Not loop-forever. If LR <=3D 1 this is the last loop: do nothin= g. */ arm_gen_condlabel(s); @@ -8775,8 +8802,28 @@ static void arm_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) dc->thumb =3D EX_TBFLAG_AM32(tb_flags, THUMB); dc->be_data =3D EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; condexec =3D EX_TBFLAG_AM32(tb_flags, CONDEXEC); - dc->condexec_mask =3D (condexec & 0xf) << 1; - dc->condexec_cond =3D condexec >> 4; + /* + * the CONDEXEC TB flags are CPSR bits [15:10][26:25]. On A-profile th= is + * is always the IT bits. On M-profile, some of the reserved encodings + * of IT are used instead to indicate either ICI or ECI, which + * indicate partial progress of a restartable insn that was interrupted + * partway through by an exception: + * * if CONDEXEC[3:0] !=3D 0b0000 : CONDEXEC is IT bits + * * if CONDEXEC[3:0] =3D=3D 0b0000 : CONDEXEC is ICI or ECI bits + * In all cases CONDEXEC =3D=3D 0 means "not in IT block or restartable + * insn, behave normally". + */ + dc->eci =3D dc->condexec_mask =3D dc->condexec_cond =3D 0; + dc->eci_handled =3D false; + dc->insn_eci_rewind =3D NULL; + if (condexec & 0xf) { + dc->condexec_mask =3D (condexec & 0xf) << 1; + dc->condexec_cond =3D condexec >> 4; + } else { + if (arm_feature(env, ARM_FEATURE_M)) { + dc->eci =3D condexec >> 4; + } + } =20 core_mmu_idx =3D EX_TBFLAG_ANY(tb_flags, MMUIDX); dc->mmu_idx =3D core_to_arm_mmu_idx(env, core_mmu_idx); @@ -8898,10 +8945,19 @@ static void arm_tr_tb_start(DisasContextBase *dcbas= e, CPUState *cpu) static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); + /* + * The ECI/ICI bits share PSR bits with the IT bits, so we + * need to reconstitute the bits from the split-out DisasContext + * fields here. + */ + uint32_t condexec_bits; =20 - tcg_gen_insn_start(dc->base.pc_next, - (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), - 0); + if (dc->eci) { + condexec_bits =3D dc->eci << 4; + } else { + condexec_bits =3D (dc->condexec_cond << 4) | (dc->condexec_mask >>= 1); + } + tcg_gen_insn_start(dc->base.pc_next, condexec_bits, 0); dc->insn_start =3D tcg_last_op(); } =20 @@ -9067,6 +9123,40 @@ static void thumb_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) } dc->insn =3D insn; =20 + if (dc->eci) { + /* + * For M-profile continuable instructions, ECI/ICI handling + * falls into these cases: + * - interrupt-continuable instructions + * These are the various load/store multiple insns (both + * integer and fp). The ICI bits indicate the register + * where the load/store can resume. We make the IMPDEF + * choice to always do "instruction restart", ie ignore + * the ICI value and always execute the ldm/stm from the + * start. So all we need to do is zero PSR.ICI if the + * insn executes. + * - MVE instructions subject to beat-wise execution + * Here the ECI bits indicate which beats have already been + * executed, and we must honour this. Each insn of this + * type will handle it correctly. We will update PSR.ECI + * in the helper function for the insn (some ECI values + * mean that the following insn also has been partially + * executed). + * - Special cases which don't advance ECI + * The insns LE, LETP and BKPT leave the ECI/ICI state + * bits untouched. + * - all other insns (the common case) + * Non-zero ECI/ICI means an INVSTATE UsageFault. + * We place a rewind-marker here. Insns in the previous + * three categories will set a flag in the DisasContext. + * If the flag isn't set after we call disas_thumb_insn() + * or disas_thumb2_insn() then we know we have a "some other + * insn" case. We will rewind to the marker (ie throwing away + * all the generated code) and instead emit "take exception". + */ + dc->insn_eci_rewind =3D tcg_last_op(); + } + if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) { uint32_t cond =3D dc->condexec_cond; =20 @@ -9095,6 +9185,17 @@ static void thumb_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) } } =20 + if (dc->eci && !dc->eci_handled) { + /* + * Insn wasn't valid for ECI/ICI at all: undo what we + * just generated and instead emit an exception + */ + tcg_remove_ops_after(dc->insn_eci_rewind); + dc->condjmp =3D 0; + gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategoriz= ed(), + default_exception_el(dc)); + } + arm_post_translate_insn(dc); =20 /* Thumb is a variable-length ISA. Stop translation when the next insn --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772697; cv=none; d=zohomail.com; s=zohoarc; b=nXZvhBcjTHXoexp7/9DRVwHSHdNss9sIDH1EBHbp5JHIYdgMxIVIH7UxBXVAkNWWdYoNur+GeIS1fZcjKtZ4Gw7amUue4BSKAZuwrS/RxfARW3KvBanmF4PixwaoXyb6BsrB4pa8OAtOumRZnLi79dkOA7bZSH2RibNKpAwYIjA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623772697; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8vabLcCtrF8uUUIQZDanF4/sCkub8suDllFj2RsW/JU=; b=LcsK6/sr/QNeMfyvEU2UXCkkfZXps+YkpVayKKep+Rr0XcaF9VOyAN4w6QbG8UBP+cGZ0g9tSbL9rJAJhkhdVSwn7RDTGEdLaFC/6b2QFe36iGUfER0ucEdy34e7AKflgicwNRfQx147exqJ5qe4Hi2ImVcaQCUhsh5C/37mewU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623772697381154.98064362206776; Tue, 15 Jun 2021 08:58:17 -0700 (PDT) Received: from localhost ([::1]:52820 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBSC-0007Ux-6h for importer@patchew.org; Tue, 15 Jun 2021 11:58:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43054) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBFI-0006WP-Qr for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:56 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:36492) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEl-0000zk-RC for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:56 -0400 Received: by mail-wr1-x42b.google.com with SMTP id n7so12688555wri.3 for ; Tue, 15 Jun 2021 08:44:23 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8vabLcCtrF8uUUIQZDanF4/sCkub8suDllFj2RsW/JU=; b=aPRpdzllKkGN17tateaaXG/4dKBTJorY/n8BdrgmJlzfSM7DaH90w+MH5txpUIpV+v DtIR/G5n7k8h7P5fjcKPhQRcTB/AQ1TWCeSbmmCUVlrhoY46t28vufBdhGyM51V6KvRp kM4wSup7pR+kMbGMN7ebHpR/PKwy2hIFNUZjpflYjaWumNvds0WCpuVu4g6Q0qBEG0mM SUNONo8Ri5RJVsRJFVvWM9AYiEMZ0Yi/durXU7jnU+bgQIlZhMwhmReOXU+iiAkKdEaf 80dvIxREojexu4M9v0quwpXWsNi5WtcULXj1+mJeWM7cQ3tynvib/ijGWZpn8Wh75lpy 9abg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8vabLcCtrF8uUUIQZDanF4/sCkub8suDllFj2RsW/JU=; b=YJRzyTqwMKX9RurfmUlnWTkXRf6zZFt+JUWYSxWdWkem0za3lew+NvztAnH5Vm2DXs lzEqxTLF0bH4QRaW8/8ZNu+xYX1aMgLOrVyQ/JpDpyCumMW+sX0PfF7s6yfP/EWE1JIz Sh8ZG0LaRrR04RrBDJ5JpCDncEEXChX5SBQwbVEjTaTAgnPogZxMXMP0or9jgXGMeYEV +foA7zoa0NKKj1Xhrj+ZmP/0w3ATutMxjzIvBwCuXZYsNwnJ0Ev18dymZ3iLRN0PiVki HGuvq+ua+WMvd1C4lG5C59OCPa40cBQA35JPBF5FSuWdnqYaquRD93f0LpCM2f8vP2n1 jO+Q== X-Gm-Message-State: AOAM5329aIGbleRuMSXyIvF+MiMnLoPQHj/ipLLYfJHEW/HUE+08i3pj P7aPGgvzp3u6v50mlHpkaKP/6DF4t+Absw== X-Google-Smtp-Source: ABdhPJwPNQHKVcfSEpYHwEJlPx4U+CqkkBXfh6IPju90fu8APCYI+WnK4JmJ+RoueaFzmauiOmAhVA== X-Received: by 2002:adf:ed03:: with SMTP id a3mr26161647wro.166.1623771862716; Tue, 15 Jun 2021 08:44:22 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/28] target/arm: Let vfp_access_check() handle late NOCP checks Date: Tue, 15 Jun 2021 16:43:57 +0100 Message-Id: <20210615154405.21399-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In commit a3494d4671797c we reworked the M-profile handling of its checks for when the NOCP exception should be raised because the FPU is disabled, so that (in line with the architecture) the NOCP check is done early over a large range of the encoding space, and takes precedence over UNDEF exceptions. As part of this, we removed the code from full_vfp_access_check() which raised an exception there for M-profile with the FPU disabled, because it was no longer reachable. For MVE, some instructions which are outside the "coprocessor space" region of the encoding space must nonetheless do "is the FPU enabled" checks and possibly raise a NOCP exception. (In particular this covers the MVE-specific low-overhead branch insns LCTP, DLSTP and WLSTP.) To support these insns, reinstate the code in full_vfp_access_check(), so that their trans functions can call vfp_access_check() and get the correct behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210614151007.4545-6-peter.maydell@linaro.org --- target/arm/translate-vfp.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 2e12c694edc..01e26a246d6 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -143,11 +143,21 @@ static void gen_preserve_fp_state(DisasContext *s) static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) { if (s->fp_excp_el) { - /* M-profile handled this earlier, in disas_m_nocp() */ - assert (!arm_dc_feature(s, ARM_FEATURE_M)); - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), - s->fp_excp_el); + if (arm_dc_feature(s, ARM_FEATURE_M)) { + /* + * M-profile mostly catches the "FPU disabled" case early, in + * disas_m_nocp(), but a few insns (eg LCTP, WLSTP, DLSTP) + * which do coprocessor-checks are outside the large ranges of + * the encoding space handled by the patterns in m-nocp.decode, + * and for them we may need to raise NOCP here. + */ + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); + } else { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_fp_access_trap(1, 0xe, false), + s->fp_excp_el); + } return false; } =20 --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772987; cv=none; d=zohomail.com; s=zohoarc; b=BuUmSERiFTXyQtDVuuxvTyFbjG9PIotm0NFUQcCF0yjQQcazry2ZU5VJkimPkSIsHWF4XMI40d10qZ7QLf2CaKwwWMSBH7RtEUgTEROsdNHXFY8xNr68V6iilQWI3eFL4t9QElrP0pRzFKS5pRegocrF7Oz7oBk1RcQE6Y5nPa8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623772987; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8QKmbmV6XEUKXJYuU9zzx7R9/w2OYAkbxEJxTOUJAys=; b=hDMgn4BIgBRnd5w3ZTRS0Rq8Xj8BzavkwFgW31mOtcpYAuud9j548CehI+74hcF1n+eLFlf0g74tqQFJm3gs0TIsO/ZV9KTiFetVs7LCmb5kpt/6BJExBg6dlsYZ9SnCTZ1tafLexNlGulsMc3B5J2HMPISU6utpnVwYL+l+DuY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623772987554323.6150871214785; Tue, 15 Jun 2021 09:03:07 -0700 (PDT) Received: from localhost ([::1]:37234 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBWs-0007xp-DA for importer@patchew.org; Tue, 15 Jun 2021 12:03:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43102) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBFL-0006Zu-2o for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:59 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:43538) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEn-0000zq-8R for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:44:58 -0400 Received: by mail-wm1-x32c.google.com with SMTP id 3-20020a05600c0243b029019f2f9b2b8aso2304411wmj.2 for ; Tue, 15 Jun 2021 08:44:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8QKmbmV6XEUKXJYuU9zzx7R9/w2OYAkbxEJxTOUJAys=; b=QjTUu+Z3uHOzCJTjJZYxZaifD9mbPSX960A9lbSFjOtypnCnTJgQJzhr0PFgCD8ZN0 EY8WglN8VYtX8K8TdsgDU8wQurKbdwoHxQiEhmbziyMvuJWpL4Diht1roeXgR2UqO0D5 wQD0FtgGWHbNAEqCwcTnDOEyWdYT2e04z2e1JTrTEpW4H94+OpXQz0l0ZQjVagYDLUcr 9MtC67+nOUzLfJ1gQgzE+WQvnzdkjbckNvxmLmOGW6tYvi5Rt3yawx6JTehC9GYlnsdX UR3IOubfv9CZCce24GouLyN/qysxVVncftc+KnN5uqkcw7mZ6uZYBNyQrAEjw3mudH/s LHQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8QKmbmV6XEUKXJYuU9zzx7R9/w2OYAkbxEJxTOUJAys=; b=k76ih8ZtQtQMilD3yiQUtYbC2CP5+jGGJQ2T6vlczyHU3euFW48HlsTAScESQFwwNW xtMh+ugruSXaLo+SI8iWrW58EuDIEALnXhbTGLVaKRJO/5z6IHsVKqPhQQZ22jVuG1AZ wFdHnbZc0/a901RNPbh2pp7by+kKDYH2OYwiXwXsLsFWr7+4e6BTIVJ2eYMrWi5LIdly F7Q+Pc2WYwT0/clhv2pfXm9Ghgw6eZ1roYUWYKvkeLnbqmmO3IyoYsKbhwETnvBPgAQb 3dW7QxfO+9orr7/qZ5aJmnsCJBWbjLWaNEy10ja4PUUWhbDF8Dan9J++qic3y4PWhNku ctWw== X-Gm-Message-State: AOAM5321u0NkX89A5qTUrGlvFTIz1IuT8GqEKDo7p5tv7XOZViP5vIc3 pfVLBtdsRiqVULrKkPmclBLJVXgPvqcbpQ== X-Google-Smtp-Source: ABdhPJyTHFVF+cC714n4ozz9dknqo6p0RmZl93kMo69UE21wwTSy/SijIxZQM1vZGFGpty4fXD7QHQ== X-Received: by 2002:a05:600c:35c3:: with SMTP id r3mr5970735wmq.169.1623771863289; Tue, 15 Jun 2021 08:44:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/28] target/arm: Implement MVE LCTP Date: Tue, 15 Jun 2021 16:43:58 +0100 Message-Id: <20210615154405.21399-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE LCTP instruction. We put its decode and implementation with the other low-overhead-branch insns because although it is only present if MVE is implemented it is logically in the same group as the other LOB insns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210614151007.4545-7-peter.maydell@linaro.org --- target/arm/t32.decode | 2 ++ target/arm/translate.c | 24 ++++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 8b2c487fa7a..087e514e0ac 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -674,5 +674,7 @@ BL 1111 0. .......... 11.1 ............ = @branch24 DLS 1111 0 0000 100 rn:4 1110 0000 0000 0001 WLS 1111 0 0000 100 rn:4 1100 . .......... 1 imm=3D%lob_i= mm LE 1111 0 0000 0 f:1 0 1111 1100 . .......... 1 imm=3D%lob_i= mm + + LCTP 1111 0 0000 000 1111 1110 0000 0000 0001 ] } diff --git a/target/arm/translate.c b/target/arm/translate.c index f1c2074fa4a..c49561590c9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8191,6 +8191,30 @@ static bool trans_LE(DisasContext *s, arg_LE *a) return true; } =20 +static bool trans_LCTP(DisasContext *s, arg_LCTP *a) +{ + /* + * M-profile Loop Clear with Tail Predication. Since our implementation + * doesn't cache branch information, all we need to do is reset + * FPSCR.LTPSIZE to 4. + */ + TCGv_i32 ltpsize; + + if (!dc_isar_feature(aa32_lob, s) || + !dc_isar_feature(aa32_mve, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + ltpsize =3D tcg_const_i32(4); + store_cpu_field(ltpsize, v7m.ltpsize); + return true; +} + + static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half) { TCGv_i32 addr, tmp; --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772566; cv=none; d=zohomail.com; s=zohoarc; b=jTaXov3s7zsXd+byvom1Pun5VdASJzibMlsPhTYLJ+tLbbwKB7xnZM+Xd8OLHPZhXnw6vUKI9GIL5DOFptc334U4PQL19pkTJRyfYHzJ4PMZbeWKMEjgCtm6z0W6i6rMYEWUSdzS9+AeUCgU6M8or0tirkmoXeFwICacfCMtMdw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623772566; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gmfa6QuGhqnYPIJbw9iaiqNwq7wBN009XaKddbtNFCk=; b=ivt6GssH6S3c7jBcqJWg5+IG1hoTUD3k2M5+7BeajC9h5LmdWH2atiBpQNXspqT55+wi2IR0rd8pinoyFg/m6Xm3qXjwmq59lrOYq2RuRW5IJx/MdG4a+MHhFymclPOsukysMy+BZMI27Os5pY4Ma0gdH+o39GLCsSNgxKKGFXA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623772566759479.01686249097645; Tue, 15 Jun 2021 08:56:06 -0700 (PDT) Received: from localhost ([::1]:43976 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBQ5-0001cc-OA for importer@patchew.org; Tue, 15 Jun 2021 11:56:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43114) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBFM-0006bu-8v for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:45:00 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:46682) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEn-00010A-9D for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:45:00 -0400 Received: by mail-wr1-x436.google.com with SMTP id a11so18852703wrt.13 for ; Tue, 15 Jun 2021 08:44:24 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=gmfa6QuGhqnYPIJbw9iaiqNwq7wBN009XaKddbtNFCk=; b=lhKcAingNmdVKh8IzHU2wqosm7ss226Qf/9o8z1BFQwQ3dHJ6+CZv8fXeiygxknF5i mBVmSoqp5S/QiQ/7b13iwye7JcBhgy7tOh4FZwP3A0SnRvDHhDoof7IlQ34V5g8oKoaM dt11yHKW3Mhi/QzZNizQyJjQKTJlDD1jqFLqV/6mEbCCgLK3Vk+jeu7e3HXOrv3Qj+Oc haxCHd5X1ODfxKp8Jo7x23A33B9Vs9QkMY3vXUINey73UPAVgCWKINZKQLTE27JxPbNg W9RdxCXyGpZw9qwgzk9ZE+YusvJPw24zgsC6GNcRKwiNnOvuDceM7jB69S44Yo0e0xLq j39g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gmfa6QuGhqnYPIJbw9iaiqNwq7wBN009XaKddbtNFCk=; b=MBS6IxRbHQebq0ZrWGGHyqFUPPsgTQ7diOBkrwM9N7msjXfQrQxBtvr2mYCqSxKx2M kQhy6sxecffgFC0spYWhVNndJ46iHlcA7YYGv3aHiuaqVE1qvTw9kKnY10t0zCepjVkC K3r/tlm/GK//Qmedkx7XLuedtC50kHLX5j+hGIAcG6BK3PPHm1YJeUltqHVKXpIESCHi WcfevR534qSTCkJz7fxG5zX2gWaX5JUZhA44yf4m+ygoGCe6kjd1yX2pEMyN51SPEZGH ta7qLlJgkVNoUBPGzHah3/QQbbKSL74usUsOfuDuUTkjjKN1a7rWsUbyFvVtdl+Eh4n2 dkBA== X-Gm-Message-State: AOAM53374z0HNk44PtFk7IV+K/LRFoEwCZ9oEGzjW/zdZhsY+2sfppBI aJwY/GeIAFau4Xi7WNZDUDrr5JjF+MYQww== X-Google-Smtp-Source: ABdhPJzy36yXws3ZJTABl+8yDIUtlcFTatmahmNm7oHOKzYSP7IXFp2U9iU+qxE67Lxyg2in5M5X3g== X-Received: by 2002:a5d:540b:: with SMTP id g11mr26879466wrv.390.1623771863886; Tue, 15 Jun 2021 08:44:23 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/28] target/arm: Implement MVE WLSTP insn Date: Tue, 15 Jun 2021 16:43:59 +0100 Message-Id: <20210615154405.21399-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE WLSTP insn; this is like the existing WLS insn, except that it specifies a size value which is used to set FPSCR.LTPSIZE. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210614151007.4545-8-peter.maydell@linaro.org --- target/arm/t32.decode | 8 ++++++-- target/arm/translate.c | 37 ++++++++++++++++++++++++++++++++++++- 2 files changed, 42 insertions(+), 3 deletions(-) diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 087e514e0ac..6906829265f 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -672,8 +672,12 @@ BL 1111 0. .......... 11.1 ............ = @branch24 %lob_imm 1:10 11:1 !function=3Dtimes_2 =20 DLS 1111 0 0000 100 rn:4 1110 0000 0000 0001 - WLS 1111 0 0000 100 rn:4 1100 . .......... 1 imm=3D%lob_i= mm - LE 1111 0 0000 0 f:1 0 1111 1100 . .......... 1 imm=3D%lob_i= mm + WLS 1111 0 0000 100 rn:4 1100 . .......... 1 imm=3D%lob_i= mm size=3D4 + { + LE 1111 0 0000 0 f:1 0 1111 1100 . .......... 1 imm=3D%lob_i= mm + # This is WLSTP + WLS 1111 0 0000 0 size:2 rn:4 1100 . .......... 1 imm=3D%lob_= imm + } =20 LCTP 1111 0 0000 000 1111 1110 0000 0000 0001 ] diff --git a/target/arm/translate.c b/target/arm/translate.c index c49561590c9..78878e9b194 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8134,7 +8134,11 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a) return false; } if (a->rn =3D=3D 13 || a->rn =3D=3D 15) { - /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */ + /* + * For WLSTP rn =3D=3D 15 is a related encoding (LE); the + * other cases caught by this condition are all + * CONSTRAINED UNPREDICTABLE: we choose to UNDEF + */ return false; } if (s->condexec_mask) { @@ -8147,10 +8151,41 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a) */ return false; } + if (a->size !=3D 4) { + /* WLSTP */ + if (!dc_isar_feature(aa32_mve, s)) { + return false; + } + /* + * We need to check that the FPU is enabled here, but mustn't + * call vfp_access_check() to do that because we don't want to + * do the lazy state preservation in the "loop count is zero" case. + * Do the check-and-raise-exception by hand. + */ + if (s->fp_excp_el) { + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); + return true; + } + } + nextlabel =3D gen_new_label(); tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_R[a->rn], 0, nextlabel); tmp =3D load_reg(s, a->rn); store_reg(s, 14, tmp); + if (a->size !=3D 4) { + /* + * WLSTP: set FPSCR.LTPSIZE. This requires that we do the + * lazy state preservation, new FP context creation, etc, + * that vfp_access_check() does. We know that the actual + * access check will succeed (ie it won't generate code that + * throws an exception) because we did that check by hand earlier. + */ + bool ok =3D vfp_access_check(s); + assert(ok); + tmp =3D tcg_const_i32(a->size); + store_cpu_field(tmp, v7m.ltpsize); + } gen_jmp_tb(s, s->base.pc_next, 1); =20 gen_set_label(nextlabel); --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623773250; cv=none; d=zohomail.com; s=zohoarc; b=ZAlo9MeG4Mqu7s+rr2CB2A7ZIlSOWEoMQKL5gDJltPn5TD+P+Q83zkttlikZth9rn+MKgmnkRa/jtxFKSEGS/w09cojBsJGNbLYKRxg13fjjqUK6gPhW9dm+gUhqMa8iQQQ99Fncddi6LLVieoCfjwIMIotT/S0YZp4qn+DlqXA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623773250; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fMuKWHdkuM/4hkeCSU4QtVyaP/N9W3vegrM1ehuyoIo=; b=oHHokaAAAbJKM6c6wwRy2q8hsOpDQDdPldfrUKIkjA5jBzH1XOTauowT6kQ4t25g7WvUot5A4bsW8bcUdpbuTdoLCkgr9qY6ZvPYloM/63HTrYWefN5sp8xcyQfaO5wszGEKWKU+iV5iDenkQdtcH//cIOqS0UgR/hl7UvO4d7k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623773250638944.1201476053283; Tue, 15 Jun 2021 09:07:30 -0700 (PDT) Received: from localhost ([::1]:49626 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBb7-0008MX-GU for importer@patchew.org; Tue, 15 Jun 2021 12:07:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43118) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBFM-0006e5-VV for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:45:02 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:42947) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEo-00010Z-2N for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:45:00 -0400 Received: by mail-wr1-x435.google.com with SMTP id c5so18843349wrq.9 for ; Tue, 15 Jun 2021 08:44:25 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=fMuKWHdkuM/4hkeCSU4QtVyaP/N9W3vegrM1ehuyoIo=; b=zQf9vrUINjtUmsIL88ISDn/VE4kpcg/doYy72HyI2jXHgbiBs6r4BjE1PNFHOgZU04 R3E+tqPqaZPUMLPrdXcHdhQqSm43i3elT1d7W8quCEP2s5vtbaOx/UUy5j+JSA08mX4j lwEs17iAxprahoXnIUYaiNqdkix+vPX+QJsMh12TkKXKNQ3roO8O+GEhjXAgqJtLMQJg IeppPPuPXiVgk1q+996yrwRv03ThhbJt9S4kd9OdO+aaUFpVYhmmATgzkOc7OQMIf2CJ 3tnyUpX2xP3On0ybVTviYFKPgc5OlKI20QSt1cRj4E/pYREzKqCcp6qXOcYdrFaQaUaT xMlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fMuKWHdkuM/4hkeCSU4QtVyaP/N9W3vegrM1ehuyoIo=; b=A0OHkrh5KtIbfdsO0SfMMx3gcmHvBepu0s4TvoWFCqt3zZPJoIwAhjt5r7+5EhnggO beSrxWmwl24dG1ic7Su4jCW/fYR49c6++LE9hy7Vz1OKMrAzg1GTUhhkSxSX8Tu/RVtv rvE9TBEYbCJqdMTTISCUWRseD5ffruDErtkAoUgH7d4yShuvvhNy2y4C9tQa481pqOMs zpYvYwPRtN3QX78/26hE4bpfR3spWgbLRjU+wNaXct+i6jd3CuLMZoGFbYJpMuxuU0Zc f5VMbRd1nGGyMWfYUFVvhKFyluSxjOJBgm3272wANYYzXfIWojnfH9H1F50/4vCbNX+o dslw== X-Gm-Message-State: AOAM5302xH1FVH1TMnHQOQs4YL/v4Gn12QpPthlHbj1CRoFm4oZ+Z+WV EzTpfb4TD/wfY2o7GTei1PFStZnvIhWkPQ== X-Google-Smtp-Source: ABdhPJwDEAqnMpLkldVNM6pmfjHog3P8hmX9wldqdoOACnVeQXRhNwsjJ6lR2MA7xh3gC8jmPMFOWw== X-Received: by 2002:adf:b34a:: with SMTP id k10mr26183409wrd.333.1623771864537; Tue, 15 Jun 2021 08:44:24 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/28] target/arm: Implement MVE DLSTP Date: Tue, 15 Jun 2021 16:44:00 +0100 Message-Id: <20210615154405.21399-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE DLSTP insn; this is like the existing DLS insn, except that it must do an FPU access check and it sets LTPSIZE to the value specified in the insn. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210614151007.4545-9-peter.maydell@linaro.org --- target/arm/t32.decode | 9 ++++++--- target/arm/translate.c | 23 +++++++++++++++++++++-- 2 files changed, 27 insertions(+), 5 deletions(-) diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 6906829265f..1b75db50658 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -671,14 +671,17 @@ BL 1111 0. .......... 11.1 ............= @branch24 # LE and WLS immediate %lob_imm 1:10 11:1 !function=3Dtimes_2 =20 - DLS 1111 0 0000 100 rn:4 1110 0000 0000 0001 + DLS 1111 0 0000 100 rn:4 1110 0000 0000 0001 size=3D4 WLS 1111 0 0000 100 rn:4 1100 . .......... 1 imm=3D%lob_i= mm size=3D4 { LE 1111 0 0000 0 f:1 0 1111 1100 . .......... 1 imm=3D%lob_i= mm # This is WLSTP WLS 1111 0 0000 0 size:2 rn:4 1100 . .......... 1 imm=3D%lob_= imm } - - LCTP 1111 0 0000 000 1111 1110 0000 0000 0001 + { + LCTP 1111 0 0000 000 1111 1110 0000 0000 0001 + # This is DLSTP + DLS 1111 0 0000 0 size:2 rn:4 1110 0000 0000 0001 + } ] } diff --git a/target/arm/translate.c b/target/arm/translate.c index 78878e9b194..1ad0e61fac6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8114,13 +8114,32 @@ static bool trans_DLS(DisasContext *s, arg_DLS *a) return false; } if (a->rn =3D=3D 13 || a->rn =3D=3D 15) { - /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */ + /* + * For DLSTP rn =3D=3D 15 is a related encoding (LCTP); the + * other cases caught by this condition are all + * CONSTRAINED UNPREDICTABLE: we choose to UNDEF + */ return false; } =20 - /* Not a while loop, no tail predication: just set LR to the count */ + if (a->size !=3D 4) { + /* DLSTP */ + if (!dc_isar_feature(aa32_mve, s)) { + return false; + } + if (!vfp_access_check(s)) { + return true; + } + } + + /* Not a while loop: set LR to the count, and set LTPSIZE for DLSTP */ tmp =3D load_reg(s, a->rn); store_reg(s, 14, tmp); + if (a->size !=3D 4) { + /* DLSTP: set FPSCR.LTPSIZE */ + tmp =3D tcg_const_i32(a->size); + store_cpu_field(tmp, v7m.ltpsize); + } return true; } =20 --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623773177; cv=none; d=zohomail.com; s=zohoarc; b=lWUhdqZPiV9aM091PrrZ8VEK+4Mz5EKSQlSKHMCPSJiC4Et7e5/HY6JCFFv93ceGhs2SF21wPJRNtLnrLfPWYjiBPCE/dtQcbnXOTb/CDoQ2Qkbin8YIWBqNpNF+jQ1FykEg0XlssHxL+UwpFdIPHLA2BhRtzOQoXu5/vkWfkmM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623773177; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1sln18kQtoUp6vqSnuDDuj3jsPTEO4Z4a1YkId39aHg=; b=G7zPvotT6fkIEfYt+hnR55hNVbqIBlQSdv0gJQzSTa2WyY6+WrT8OZeg7WjTb8qDCAiY9jFT4p62PCIGo3Sp9ily6sM/OsxqdJj0c+mJ9Sr34I9kiIGPLg/xoqbtJwOleJhFggU/EU/eXOajrQ8qMKjhUUuJKHobT6Egc2ZhwQI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623773177541941.9269260192023; Tue, 15 Jun 2021 09:06:17 -0700 (PDT) Received: from localhost ([::1]:45480 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBZv-0005Ho-NJ for importer@patchew.org; Tue, 15 Jun 2021 12:06:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43138) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBFO-0006ey-5n for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:45:02 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:33314) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEo-00011H-Mg for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:45:01 -0400 Received: by mail-wm1-x32d.google.com with SMTP id t11-20020a1cc30b0000b02901cec841b6a0so1131076wmf.0 for ; Tue, 15 Jun 2021 08:44:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1sln18kQtoUp6vqSnuDDuj3jsPTEO4Z4a1YkId39aHg=; b=yZOV1uBSWF7PWoqv4JciVEjdPXDt/06j+wjD916ICOc/62hLPIocvVOvb72E357/5y 7FjpaNqo6jWa6kDppFvLqGh1RGIxlA9cTtEGe/KbZVDvm+lYOlhV8VPIRKxAkR2R+q8t JZqyV1w9X960k+ltVcDbFnstE2e4FRGl6NuQXdtywm103WY8G3pkEsWrxuQM131G+q2C 4U5McvGIAVlPB3OStglWrenOvyZ0VotaN+nEelMWqSlvbGw/fyAfwhO9IKcAuQX2IUBx MyPyUeYVyYaoFC29xMlbSWKb9Z2YZa0WC6spLvXuyQoOMVNUFkeyr5L3r+k01vyH7JxN 1Lvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1sln18kQtoUp6vqSnuDDuj3jsPTEO4Z4a1YkId39aHg=; b=mIxCFoWi7F09Ar3GxyLgVd3/tOaFnF5ZsKWVwsGxYD+vNiTtSikpYn6mmo//xLY007 oZ9rdeAznpgniVfuoVs05Ij1fyeP0yH4X1s9XlYcWKRyFl9VpDBR7I/LVig4bWoNMi4H Wr/u6GiYxRdkZ0F7fZs/asSrX+9V+QJfhnLsdlLPOc9uqpFZev7pa/wkSOpSJ68XddL6 /Yr40auE+Qj1jmzfaccPIIw5R1i7HYGJjdYs2da5Jkbxpyboip4/wramY3bVwP6chuhK UNCWi4W6JslwHGloLujvJrvFG85LLXp5PJ2AyCN8Qq5zf3Nsfxr1FQI++cDmMr3fPpBH xlmg== X-Gm-Message-State: AOAM532sDHbjycNU+fu+3BPo1WPslBtdoud4JanJftVD3Oj5PdXNi5fW yEemZe1M34lqiU6fwFwuel5gbzBzhSB+sg== X-Google-Smtp-Source: ABdhPJy56oB722QwVzaU9lUbecde38m9A1xXap7ci+L7AgsLSLj2n6haZJPcoWZ2q40FF16FcY6J8Q== X-Received: by 2002:a05:600c:2298:: with SMTP id 24mr5797215wmf.173.1623771865316; Tue, 15 Jun 2021 08:44:25 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/28] target/arm: Implement MVE LETP insn Date: Tue, 15 Jun 2021 16:44:01 +0100 Message-Id: <20210615154405.21399-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE LETP insn. This is like the existing LE loop-end insn, but it must perform an FPU-enabled check, and on loop-exit it resets LTPSIZE to 4. To accommodate the requirement to do something on loop-exit, we drop the use of condlabel and instead manage both the TB exits manually, in the same way we already do in trans_WLS(). The other MVE-specific change to the LE insn is that we must raise an INVSTATE UsageFault insn if LTPSIZE is not 4. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210614151007.4545-10-peter.maydell@linaro.org --- target/arm/t32.decode | 2 +- target/arm/translate.c | 104 +++++++++++++++++++++++++++++++++++++---- 2 files changed, 97 insertions(+), 9 deletions(-) diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 1b75db50658..0f9326c724b 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -674,7 +674,7 @@ BL 1111 0. .......... 11.1 ............ = @branch24 DLS 1111 0 0000 100 rn:4 1110 0000 0000 0001 size=3D4 WLS 1111 0 0000 100 rn:4 1100 . .......... 1 imm=3D%lob_i= mm size=3D4 { - LE 1111 0 0000 0 f:1 0 1111 1100 . .......... 1 imm=3D%lob_i= mm + LE 1111 0 0000 0 f:1 tp:1 1111 1100 . .......... 1 imm=3D%lo= b_imm # This is WLSTP WLS 1111 0 0000 0 size:2 rn:4 1100 . .......... 1 imm=3D%lob_= imm } diff --git a/target/arm/translate.c b/target/arm/translate.c index 1ad0e61fac6..a51e882b867 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8223,25 +8223,113 @@ static bool trans_LE(DisasContext *s, arg_LE *a) * any faster. */ TCGv_i32 tmp; + TCGLabel *loopend; + bool fpu_active; =20 if (!dc_isar_feature(aa32_lob, s)) { return false; } + if (a->f && a->tp) { + return false; + } + if (s->condexec_mask) { + /* + * LE in an IT block is CONSTRAINED UNPREDICTABLE; + * we choose to UNDEF, because otherwise our use of + * gen_goto_tb(1) would clash with the use of TB exit 1 + * in the dc->condjmp condition-failed codepath in + * arm_tr_tb_stop() and we'd get an assertion. + */ + return false; + } + if (a->tp) { + /* LETP */ + if (!dc_isar_feature(aa32_mve, s)) { + return false; + } + if (!vfp_access_check(s)) { + s->eci_handled =3D true; + return true; + } + } =20 /* LE/LETP is OK with ECI set and leaves it untouched */ s->eci_handled =3D true; =20 - if (!a->f) { - /* Not loop-forever. If LR <=3D 1 this is the last loop: do nothin= g. */ - arm_gen_condlabel(s); - tcg_gen_brcondi_i32(TCG_COND_LEU, cpu_R[14], 1, s->condlabel); - /* Decrement LR */ - tmp =3D load_reg(s, 14); - tcg_gen_addi_i32(tmp, tmp, -1); - store_reg(s, 14, tmp); + /* + * With MVE, LTPSIZE might not be 4, and we must emit an INVSTATE + * UsageFault exception for the LE insn in that case. Note that we + * are not directly checking FPSCR.LTPSIZE but instead check the + * pseudocode LTPSIZE() function, which returns 4 if the FPU is + * not currently active (ie ActiveFPState() returns false). We + * can identify not-active purely from our TB state flags, as the + * FPU is active only if: + * the FPU is enabled + * AND lazy state preservation is not active + * AND we do not need a new fp context (this is the ASPEN/FPCA check) + * + * Usually we don't need to care about this distinction between + * LTPSIZE and FPSCR.LTPSIZE, because the code in vfp_access_check() + * will either take an exception or clear the conditions that make + * the FPU not active. But LE is an unusual case of a non-FP insn + * that looks at LTPSIZE. + */ + fpu_active =3D !s->fp_excp_el && !s->v7m_lspact && !s->v7m_new_fp_ctxt= _needed; + + if (!a->tp && dc_isar_feature(aa32_mve, s) && fpu_active) { + /* Need to do a runtime check for LTPSIZE !=3D 4 */ + TCGLabel *skipexc =3D gen_new_label(); + tmp =3D load_cpu_field(v7m.ltpsize); + tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc); + tcg_temp_free_i32(tmp); + gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized= (), + default_exception_el(s)); + gen_set_label(skipexc); + } + + if (a->f) { + /* Loop-forever: just jump back to the loop start */ + gen_jmp(s, read_pc(s) - a->imm); + return true; + } + + /* + * Not loop-forever. If LR <=3D loop-decrement-value this is the last = loop. + * For LE, we know at this point that LTPSIZE must be 4 and the + * loop decrement value is 1. For LETP we need to calculate the decrem= ent + * value from LTPSIZE. + */ + loopend =3D gen_new_label(); + if (!a->tp) { + tcg_gen_brcondi_i32(TCG_COND_LEU, cpu_R[14], 1, loopend); + tcg_gen_addi_i32(cpu_R[14], cpu_R[14], -1); + } else { + /* + * Decrement by 1 << (4 - LTPSIZE). We need to use a TCG local + * so that decr stays live after the brcondi. + */ + TCGv_i32 decr =3D tcg_temp_local_new_i32(); + TCGv_i32 ltpsize =3D load_cpu_field(v7m.ltpsize); + tcg_gen_sub_i32(decr, tcg_constant_i32(4), ltpsize); + tcg_gen_shl_i32(decr, tcg_constant_i32(1), decr); + tcg_temp_free_i32(ltpsize); + + tcg_gen_brcond_i32(TCG_COND_LEU, cpu_R[14], decr, loopend); + + tcg_gen_sub_i32(cpu_R[14], cpu_R[14], decr); + tcg_temp_free_i32(decr); } /* Jump back to the loop start */ gen_jmp(s, read_pc(s) - a->imm); + + gen_set_label(loopend); + if (a->tp) { + /* Exits from tail-pred loops must reset LTPSIZE to 4 */ + tmp =3D tcg_const_i32(4); + store_cpu_field(tmp, v7m.ltpsize); + } + /* End TB, continuing to following insn */ + gen_jmp_tb(s, s->base.pc_next, 1); return true; } =20 --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623772700; cv=none; d=zohomail.com; s=zohoarc; b=cuS5IGd/L4ye2XVp1dh4Nraak2Cd1sjRbgCXsxOSgggs7s2vd53NaE8jIdV7eOiBY3Op8ITmwUEUG/TVLxLFDKanf/Qnx/SNttxsG56do6PMOwQCLkXKvMk8VCsnZd96+gWXb6WraPxLOOTpk2D4QCuqd8XTj7YxNS/O8LKcWAA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623772700; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MNp+WE77dI/aNUnA4anWraPCPQQMJEMwYy4X2xAfAd4=; b=YiAZywXqwRAZ251k48JlHoQzo3lgdvxn0R6OtSj0704Zj/iiFNC3yMvfbkI82s77FDTWyo6T+xFyBgiL+WdDYage3LulnwIA1/SNAAWO9KpDYmdet2O3WyYSlVZMXpBlwKb0jxA5SrtTk9EtsEFUfUq0HwYgbE0kuGZmnDzHsAM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623772700394269.72032811832014; Tue, 15 Jun 2021 08:58:20 -0700 (PDT) Received: from localhost ([::1]:53064 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBSF-0007dw-1Z for importer@patchew.org; Tue, 15 Jun 2021 11:58:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43276) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBFc-0006vp-KK for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:45:16 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:45718) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEs-00011b-Io for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:45:13 -0400 Received: by mail-wr1-x436.google.com with SMTP id z8so18869154wrp.12 for ; Tue, 15 Jun 2021 08:44:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=MNp+WE77dI/aNUnA4anWraPCPQQMJEMwYy4X2xAfAd4=; b=GlDx6PqB3lazQx/Sxo8CmzfmJM12yb4YY90ipp3OgqJnGrV225wYAeWqpdkFEdeFI3 k/t1by8ZydWToRMlUXPhdt1wkrgxaSW2kSB/WuJH13O+L9bB3nn0YUGepENFQ7871xJv W88IAm3lKRFDqxhuH+1DCCsdmyWsrW55dEfPMHVrh4QvK5VdQsOlJIj3tue4NVqmjrI0 Xi5ayKouevW9o8zTn9yx8/O4aVHugTXhbWmdKBybKGK9xFQiU3gb15kL7xlBTkEU2TSY cEUhE8+a4fyTuoy3fGLw3pAWOC/ZHdB7EvAxH8KCdNth2A9mkmABtSrw+o9JpEgSBLfo AmwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MNp+WE77dI/aNUnA4anWraPCPQQMJEMwYy4X2xAfAd4=; b=Cu1WDWF2Zid7DOuC3mgJJWWP2kppQ2NfDtQdjSb6fTmIWIXRpXXQQ5vzHDBwSOBVcI fKoIC+8EsiR7yBylbvH8Dr7FfcJSmQbXfSKINgcFBT/VzKan8CcpA78ts0xAKG4owPW/ 98LwCe1MgCqghsT0q5LJCewT6ifTEV7yVO0HcboeY94p46JkotWujckkjASKOsQ/0c+8 9nvM+n27Te3+wHZeUnqgC+KX81N/AfOoYzrhGdy/tRZbDrsavhbkFTjUPA2qBK8mucg0 JVTJzmUvyxpdIYnznlKRTlWW7Zc3S/dsaprNZsRQgbw3lyu3xzZKYMeM3XvHQfe4YJsF XmEA== X-Gm-Message-State: AOAM53110tMYGDpEkx6hCjuHoNtIJzohYo12ETCJVCOV1DHk09hsd9Ua ujppCiDCCgiUR/JnJyr38pfAYTujIV8Klw== X-Google-Smtp-Source: ABdhPJwCUQcvY8RMS2VTrDAKHxY4Z+Esa56ZlJ4c7AzMRG42V+6CcrmQVihUMswdKmRFa891Ckx1rg== X-Received: by 2002:a5d:4401:: with SMTP id z1mr26400130wrq.149.1623771866009; Tue, 15 Jun 2021 08:44:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/28] target/arm: Add framework for MVE decode Date: Tue, 15 Jun 2021 16:44:02 +0100 Message-Id: <20210615154405.21399-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Add the framework for decoding MVE insns, with the necessary new files and the meson.build rules, but no actual content yet. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210614151007.4545-11-peter.maydell@linaro.org --- target/arm/translate-a32.h | 1 + target/arm/mve.decode | 20 ++++++++++++++++++++ target/arm/translate-mve.c | 29 +++++++++++++++++++++++++++++ target/arm/translate.c | 1 + target/arm/meson.build | 2 ++ 5 files changed, 53 insertions(+) create mode 100644 target/arm/mve.decode create mode 100644 target/arm/translate-mve.c diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index c946ac440ce..0a0053949f5 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -22,6 +22,7 @@ =20 /* Prototypes for autogenerated disassembler functions */ bool disas_m_nocp(DisasContext *dc, uint32_t insn); +bool disas_mve(DisasContext *dc, uint32_t insn); bool disas_vfp(DisasContext *s, uint32_t insn); bool disas_vfp_uncond(DisasContext *s, uint32_t insn); bool disas_neon_dp(DisasContext *s, uint32_t insn); diff --git a/target/arm/mve.decode b/target/arm/mve.decode new file mode 100644 index 00000000000..c8492bb5763 --- /dev/null +++ b/target/arm/mve.decode @@ -0,0 +1,20 @@ +# M-profile MVE instruction descriptions +# +# Copyright (c) 2021 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c new file mode 100644 index 00000000000..e91f526a1a8 --- /dev/null +++ b/target/arm/translate-mve.c @@ -0,0 +1,29 @@ +/* + * ARM translation: M-profile MVE instructions + * + * Copyright (c) 2021 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" +#include "exec/exec-all.h" +#include "exec/gen-icount.h" +#include "translate.h" +#include "translate-a32.h" + +/* Include the generated decoder */ +#include "decode-mve.c.inc" diff --git a/target/arm/translate.c b/target/arm/translate.c index a51e882b867..9e2cca77077 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8919,6 +8919,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32= _t insn) if (disas_t32(s, insn) || disas_vfp_uncond(s, insn) || disas_neon_shared(s, insn) || + disas_mve(s, insn) || ((insn >> 28) =3D=3D 0xe && disas_vfp(s, insn))) { return; } diff --git a/target/arm/meson.build b/target/arm/meson.build index 5bfaf43b500..2b50be3f862 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -6,6 +6,7 @@ gen =3D [ decodetree.process('vfp.decode', extra_args: '--decode=3Ddisas_vfp'), decodetree.process('vfp-uncond.decode', extra_args: '--decode=3Ddisas_vf= p_uncond'), decodetree.process('m-nocp.decode', extra_args: '--decode=3Ddisas_m_nocp= '), + decodetree.process('mve.decode', extra_args: '--decode=3Ddisas_mve'), decodetree.process('a32.decode', extra_args: '--static-decode=3Ddisas_a3= 2'), decodetree.process('a32-uncond.decode', extra_args: '--static-decode=3Dd= isas_a32_uncond'), decodetree.process('t32.decode', extra_args: '--static-decode=3Ddisas_t3= 2'), @@ -27,6 +28,7 @@ arm_ss.add(files( 'tlb_helper.c', 'translate.c', 'translate-m-nocp.c', + 'translate-mve.c', 'translate-neon.c', 'translate-vfp.c', 'vec_helper.c', --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623773300; cv=none; d=zohomail.com; s=zohoarc; b=m2RlHphYs9WxppDtuf8tJ+lM4C0lJSFoWOIzhZmfNKr95HW2sVP5KOXvzDEOMMMhan1cV6a6XbKgYV4mFFFSCxEbGvGYQT68nZn561biyKlCwn1NdB4+pa1B2pPhW/6vlj46xJMd6A3TZZgMkZIxRSYmec0rgzBMyK6F4StgH9w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623773300; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lnpAiuumFLFRimuw8m1WKT2cwizHzY2FLR7sJtzZvao=; b=NxvEeTlDd+BRjxb1cd7S3IC+B6wMlKRYWNljWlK1D+ahyCQ4kWC/zexTqdKkvzD6Ik0sCw/WoeptkuazJoZUe8fkdSkntypfMTq0cLd3a6mvtxIXiDFKDsHc/0gzBisPeeSFV8BVG44RWSS00lP5DWHdpKuQaxwd6NootkZooqQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623773300917319.8846936626172; Tue, 15 Jun 2021 09:08:20 -0700 (PDT) Received: from localhost ([::1]:52796 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBbw-00027P-23 for importer@patchew.org; Tue, 15 Jun 2021 12:08:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43166) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBFQ-0006jJ-7T for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:45:04 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:44584) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEs-00012G-Iw for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:45:03 -0400 Received: by mail-wm1-x332.google.com with SMTP id m41-20020a05600c3b29b02901b9e5d74f02so2300126wms.3 for ; Tue, 15 Jun 2021 08:44:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=lnpAiuumFLFRimuw8m1WKT2cwizHzY2FLR7sJtzZvao=; b=rHwui8hnyEvABpdwSRJLANuRKD5Vk2Mx/YZOkU/RJ0whzaVtpox6VwHAERtoxu86w6 mXQkNv2Jgon1C4EbZZ8Vf8eb6YHa8blc223bYxtaRfQ/lEO6/9ABs3tCK9Gu9yAxXdFS aRPlduRRveim8LErZwzunT2leChcWjORJDe+eVXixsGQVjjOYzHrQ2v8Nf8O+1kgc+EJ oaZS26ecSWic9EAftIG37SAMWxaWNikPX9vvZJBTWmzsrtHRL4HmmpdLZ3EQGUqJk1qP ZqAlY9pYeNYkuvnP8y5b7RENWuuP13jvx0cUFqFoF/Ab0AkgjNDNUZ5r96oyvHuFJdIw 9HGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lnpAiuumFLFRimuw8m1WKT2cwizHzY2FLR7sJtzZvao=; b=sjGWHhqAWoUil8YrsjVKXnMEnO7emQIkXfCxh1kDVZdPjenJ2XONjJoWvfraPoawCg B0cL9gnRlcHgnjNDcBYAwDkh/d0UUo6s13k97CKFm4fy8G4BHDRsmGAB3cgtnLGlem1x RpYyaZU3vuDoTeXeC665ptO5xT2SlUXdGXbD7DMafJ3cj4O7rJw94APncby+FFyx4HXb RnWuD1v1anBTKP5dP8g50CeWgdsQEK5EZzVXF5AfljD0T+8TpQCSI7mLVKoaf1nHg5vD N79hiz0DVfQK/6RI30SJGS+7pfGLQAv7O2Q+Qodlwqlo6Uv7AWhUPCDGRt5vVteH2DP0 jfTQ== X-Gm-Message-State: AOAM531gevDFkimXZlt9rJ4RsQgj4s7wEmyEnUnDHx4NGUbVUAqOyFUe Uioq1bi86VothW2w1pVzw9PxIP93XBmztQ== X-Google-Smtp-Source: ABdhPJz7tYByhQYewJw02Pq/naZ6CsFuh2CKKuYhpwOtI0NQ+zigEgUjFbHCpCgNVZjBY2rfVztXow== X-Received: by 2002:a05:600c:4ecc:: with SMTP id g12mr6127022wmq.40.1623771866782; Tue, 15 Jun 2021 08:44:26 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/28] target/arm: Move expand_pred_b() data to vec_helper.c Date: Tue, 15 Jun 2021 16:44:03 +0100 Message-Id: <20210615154405.21399-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For MVE, we want to re-use the large data table from expand_pred_b(). Move the data table to vec_helper.c so it is no longer in an SVE specific source file. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20210614151007.4545-14-peter.maydell@linaro.org --- target/arm/vec_internal.h | 3 ++ target/arm/sve_helper.c | 103 ++------------------------------------ target/arm/vec_helper.c | 102 +++++++++++++++++++++++++++++++++++++ 3 files changed, 109 insertions(+), 99 deletions(-) diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h index 613f3421b9c..865d2139447 100644 --- a/target/arm/vec_internal.h +++ b/target/arm/vec_internal.h @@ -50,6 +50,9 @@ #define H8(x) (x) #define H1_8(x) (x) =20 +/* Data for expanding active predicate bits to bytes, for byte elements. */ +extern const uint64_t expand_pred_b_data[256]; + static inline void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) { uint64_t *d =3D vd + opr_sz; diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index a373f8c573e..321098e2651 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -103,108 +103,13 @@ uint32_t HELPER(sve_predtest)(void *vd, void *vg, ui= nt32_t words) return flags; } =20 -/* Expand active predicate bits to bytes, for byte elements. - * for (i =3D 0; i < 256; ++i) { - * unsigned long m =3D 0; - * for (j =3D 0; j < 8; j++) { - * if ((i >> j) & 1) { - * m |=3D 0xfful << (j << 3); - * } - * } - * printf("0x%016lx,\n", m); - * } +/* + * Expand active predicate bits to bytes, for byte elements. + * (The data table itself is in vec_helper.c as MVE also needs it.) */ static inline uint64_t expand_pred_b(uint8_t byte) { - static const uint64_t word[256] =3D { - 0x0000000000000000, 0x00000000000000ff, 0x000000000000ff00, - 0x000000000000ffff, 0x0000000000ff0000, 0x0000000000ff00ff, - 0x0000000000ffff00, 0x0000000000ffffff, 0x00000000ff000000, - 0x00000000ff0000ff, 0x00000000ff00ff00, 0x00000000ff00ffff, - 0x00000000ffff0000, 0x00000000ffff00ff, 0x00000000ffffff00, - 0x00000000ffffffff, 0x000000ff00000000, 0x000000ff000000ff, - 0x000000ff0000ff00, 0x000000ff0000ffff, 0x000000ff00ff0000, - 0x000000ff00ff00ff, 0x000000ff00ffff00, 0x000000ff00ffffff, - 0x000000ffff000000, 0x000000ffff0000ff, 0x000000ffff00ff00, - 0x000000ffff00ffff, 0x000000ffffff0000, 0x000000ffffff00ff, - 0x000000ffffffff00, 0x000000ffffffffff, 0x0000ff0000000000, - 0x0000ff00000000ff, 0x0000ff000000ff00, 0x0000ff000000ffff, - 0x0000ff0000ff0000, 0x0000ff0000ff00ff, 0x0000ff0000ffff00, - 0x0000ff0000ffffff, 0x0000ff00ff000000, 0x0000ff00ff0000ff, - 0x0000ff00ff00ff00, 0x0000ff00ff00ffff, 0x0000ff00ffff0000, - 0x0000ff00ffff00ff, 0x0000ff00ffffff00, 0x0000ff00ffffffff, - 0x0000ffff00000000, 0x0000ffff000000ff, 0x0000ffff0000ff00, - 0x0000ffff0000ffff, 0x0000ffff00ff0000, 0x0000ffff00ff00ff, - 0x0000ffff00ffff00, 0x0000ffff00ffffff, 0x0000ffffff000000, - 0x0000ffffff0000ff, 0x0000ffffff00ff00, 0x0000ffffff00ffff, - 0x0000ffffffff0000, 0x0000ffffffff00ff, 0x0000ffffffffff00, - 0x0000ffffffffffff, 0x00ff000000000000, 0x00ff0000000000ff, - 0x00ff00000000ff00, 0x00ff00000000ffff, 0x00ff000000ff0000, - 0x00ff000000ff00ff, 0x00ff000000ffff00, 0x00ff000000ffffff, - 0x00ff0000ff000000, 0x00ff0000ff0000ff, 0x00ff0000ff00ff00, - 0x00ff0000ff00ffff, 0x00ff0000ffff0000, 0x00ff0000ffff00ff, - 0x00ff0000ffffff00, 0x00ff0000ffffffff, 0x00ff00ff00000000, - 0x00ff00ff000000ff, 0x00ff00ff0000ff00, 0x00ff00ff0000ffff, - 0x00ff00ff00ff0000, 0x00ff00ff00ff00ff, 0x00ff00ff00ffff00, - 0x00ff00ff00ffffff, 0x00ff00ffff000000, 0x00ff00ffff0000ff, - 0x00ff00ffff00ff00, 0x00ff00ffff00ffff, 0x00ff00ffffff0000, - 0x00ff00ffffff00ff, 0x00ff00ffffffff00, 0x00ff00ffffffffff, - 0x00ffff0000000000, 0x00ffff00000000ff, 0x00ffff000000ff00, - 0x00ffff000000ffff, 0x00ffff0000ff0000, 0x00ffff0000ff00ff, - 0x00ffff0000ffff00, 0x00ffff0000ffffff, 0x00ffff00ff000000, - 0x00ffff00ff0000ff, 0x00ffff00ff00ff00, 0x00ffff00ff00ffff, - 0x00ffff00ffff0000, 0x00ffff00ffff00ff, 0x00ffff00ffffff00, - 0x00ffff00ffffffff, 0x00ffffff00000000, 0x00ffffff000000ff, - 0x00ffffff0000ff00, 0x00ffffff0000ffff, 0x00ffffff00ff0000, - 0x00ffffff00ff00ff, 0x00ffffff00ffff00, 0x00ffffff00ffffff, - 0x00ffffffff000000, 0x00ffffffff0000ff, 0x00ffffffff00ff00, - 0x00ffffffff00ffff, 0x00ffffffffff0000, 0x00ffffffffff00ff, - 0x00ffffffffffff00, 0x00ffffffffffffff, 0xff00000000000000, - 0xff000000000000ff, 0xff0000000000ff00, 0xff0000000000ffff, - 0xff00000000ff0000, 0xff00000000ff00ff, 0xff00000000ffff00, - 0xff00000000ffffff, 0xff000000ff000000, 0xff000000ff0000ff, - 0xff000000ff00ff00, 0xff000000ff00ffff, 0xff000000ffff0000, - 0xff000000ffff00ff, 0xff000000ffffff00, 0xff000000ffffffff, - 0xff0000ff00000000, 0xff0000ff000000ff, 0xff0000ff0000ff00, - 0xff0000ff0000ffff, 0xff0000ff00ff0000, 0xff0000ff00ff00ff, - 0xff0000ff00ffff00, 0xff0000ff00ffffff, 0xff0000ffff000000, - 0xff0000ffff0000ff, 0xff0000ffff00ff00, 0xff0000ffff00ffff, - 0xff0000ffffff0000, 0xff0000ffffff00ff, 0xff0000ffffffff00, - 0xff0000ffffffffff, 0xff00ff0000000000, 0xff00ff00000000ff, - 0xff00ff000000ff00, 0xff00ff000000ffff, 0xff00ff0000ff0000, - 0xff00ff0000ff00ff, 0xff00ff0000ffff00, 0xff00ff0000ffffff, - 0xff00ff00ff000000, 0xff00ff00ff0000ff, 0xff00ff00ff00ff00, - 0xff00ff00ff00ffff, 0xff00ff00ffff0000, 0xff00ff00ffff00ff, - 0xff00ff00ffffff00, 0xff00ff00ffffffff, 0xff00ffff00000000, - 0xff00ffff000000ff, 0xff00ffff0000ff00, 0xff00ffff0000ffff, - 0xff00ffff00ff0000, 0xff00ffff00ff00ff, 0xff00ffff00ffff00, - 0xff00ffff00ffffff, 0xff00ffffff000000, 0xff00ffffff0000ff, - 0xff00ffffff00ff00, 0xff00ffffff00ffff, 0xff00ffffffff0000, - 0xff00ffffffff00ff, 0xff00ffffffffff00, 0xff00ffffffffffff, - 0xffff000000000000, 0xffff0000000000ff, 0xffff00000000ff00, - 0xffff00000000ffff, 0xffff000000ff0000, 0xffff000000ff00ff, - 0xffff000000ffff00, 0xffff000000ffffff, 0xffff0000ff000000, - 0xffff0000ff0000ff, 0xffff0000ff00ff00, 0xffff0000ff00ffff, - 0xffff0000ffff0000, 0xffff0000ffff00ff, 0xffff0000ffffff00, - 0xffff0000ffffffff, 0xffff00ff00000000, 0xffff00ff000000ff, - 0xffff00ff0000ff00, 0xffff00ff0000ffff, 0xffff00ff00ff0000, - 0xffff00ff00ff00ff, 0xffff00ff00ffff00, 0xffff00ff00ffffff, - 0xffff00ffff000000, 0xffff00ffff0000ff, 0xffff00ffff00ff00, - 0xffff00ffff00ffff, 0xffff00ffffff0000, 0xffff00ffffff00ff, - 0xffff00ffffffff00, 0xffff00ffffffffff, 0xffffff0000000000, - 0xffffff00000000ff, 0xffffff000000ff00, 0xffffff000000ffff, - 0xffffff0000ff0000, 0xffffff0000ff00ff, 0xffffff0000ffff00, - 0xffffff0000ffffff, 0xffffff00ff000000, 0xffffff00ff0000ff, - 0xffffff00ff00ff00, 0xffffff00ff00ffff, 0xffffff00ffff0000, - 0xffffff00ffff00ff, 0xffffff00ffffff00, 0xffffff00ffffffff, - 0xffffffff00000000, 0xffffffff000000ff, 0xffffffff0000ff00, - 0xffffffff0000ffff, 0xffffffff00ff0000, 0xffffffff00ff00ff, - 0xffffffff00ffff00, 0xffffffff00ffffff, 0xffffffffff000000, - 0xffffffffff0000ff, 0xffffffffff00ff00, 0xffffffffff00ffff, - 0xffffffffffff0000, 0xffffffffffff00ff, 0xffffffffffffff00, - 0xffffffffffffffff, - }; - return word[byte]; + return expand_pred_b_data[byte]; } =20 /* Similarly for half-word elements. diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index e8138d3d222..034f6b84f78 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -25,6 +25,108 @@ #include "qemu/int128.h" #include "vec_internal.h" =20 +/* + * Data for expanding active predicate bits to bytes, for byte elements. + * + * for (i =3D 0; i < 256; ++i) { + * unsigned long m =3D 0; + * for (j =3D 0; j < 8; j++) { + * if ((i >> j) & 1) { + * m |=3D 0xfful << (j << 3); + * } + * } + * printf("0x%016lx,\n", m); + * } + */ +const uint64_t expand_pred_b_data[256] =3D { + 0x0000000000000000, 0x00000000000000ff, 0x000000000000ff00, + 0x000000000000ffff, 0x0000000000ff0000, 0x0000000000ff00ff, + 0x0000000000ffff00, 0x0000000000ffffff, 0x00000000ff000000, + 0x00000000ff0000ff, 0x00000000ff00ff00, 0x00000000ff00ffff, + 0x00000000ffff0000, 0x00000000ffff00ff, 0x00000000ffffff00, + 0x00000000ffffffff, 0x000000ff00000000, 0x000000ff000000ff, + 0x000000ff0000ff00, 0x000000ff0000ffff, 0x000000ff00ff0000, + 0x000000ff00ff00ff, 0x000000ff00ffff00, 0x000000ff00ffffff, + 0x000000ffff000000, 0x000000ffff0000ff, 0x000000ffff00ff00, + 0x000000ffff00ffff, 0x000000ffffff0000, 0x000000ffffff00ff, + 0x000000ffffffff00, 0x000000ffffffffff, 0x0000ff0000000000, + 0x0000ff00000000ff, 0x0000ff000000ff00, 0x0000ff000000ffff, + 0x0000ff0000ff0000, 0x0000ff0000ff00ff, 0x0000ff0000ffff00, + 0x0000ff0000ffffff, 0x0000ff00ff000000, 0x0000ff00ff0000ff, + 0x0000ff00ff00ff00, 0x0000ff00ff00ffff, 0x0000ff00ffff0000, + 0x0000ff00ffff00ff, 0x0000ff00ffffff00, 0x0000ff00ffffffff, + 0x0000ffff00000000, 0x0000ffff000000ff, 0x0000ffff0000ff00, + 0x0000ffff0000ffff, 0x0000ffff00ff0000, 0x0000ffff00ff00ff, + 0x0000ffff00ffff00, 0x0000ffff00ffffff, 0x0000ffffff000000, + 0x0000ffffff0000ff, 0x0000ffffff00ff00, 0x0000ffffff00ffff, + 0x0000ffffffff0000, 0x0000ffffffff00ff, 0x0000ffffffffff00, + 0x0000ffffffffffff, 0x00ff000000000000, 0x00ff0000000000ff, + 0x00ff00000000ff00, 0x00ff00000000ffff, 0x00ff000000ff0000, + 0x00ff000000ff00ff, 0x00ff000000ffff00, 0x00ff000000ffffff, + 0x00ff0000ff000000, 0x00ff0000ff0000ff, 0x00ff0000ff00ff00, + 0x00ff0000ff00ffff, 0x00ff0000ffff0000, 0x00ff0000ffff00ff, + 0x00ff0000ffffff00, 0x00ff0000ffffffff, 0x00ff00ff00000000, + 0x00ff00ff000000ff, 0x00ff00ff0000ff00, 0x00ff00ff0000ffff, + 0x00ff00ff00ff0000, 0x00ff00ff00ff00ff, 0x00ff00ff00ffff00, + 0x00ff00ff00ffffff, 0x00ff00ffff000000, 0x00ff00ffff0000ff, + 0x00ff00ffff00ff00, 0x00ff00ffff00ffff, 0x00ff00ffffff0000, + 0x00ff00ffffff00ff, 0x00ff00ffffffff00, 0x00ff00ffffffffff, + 0x00ffff0000000000, 0x00ffff00000000ff, 0x00ffff000000ff00, + 0x00ffff000000ffff, 0x00ffff0000ff0000, 0x00ffff0000ff00ff, + 0x00ffff0000ffff00, 0x00ffff0000ffffff, 0x00ffff00ff000000, + 0x00ffff00ff0000ff, 0x00ffff00ff00ff00, 0x00ffff00ff00ffff, + 0x00ffff00ffff0000, 0x00ffff00ffff00ff, 0x00ffff00ffffff00, + 0x00ffff00ffffffff, 0x00ffffff00000000, 0x00ffffff000000ff, + 0x00ffffff0000ff00, 0x00ffffff0000ffff, 0x00ffffff00ff0000, + 0x00ffffff00ff00ff, 0x00ffffff00ffff00, 0x00ffffff00ffffff, + 0x00ffffffff000000, 0x00ffffffff0000ff, 0x00ffffffff00ff00, + 0x00ffffffff00ffff, 0x00ffffffffff0000, 0x00ffffffffff00ff, + 0x00ffffffffffff00, 0x00ffffffffffffff, 0xff00000000000000, + 0xff000000000000ff, 0xff0000000000ff00, 0xff0000000000ffff, + 0xff00000000ff0000, 0xff00000000ff00ff, 0xff00000000ffff00, + 0xff00000000ffffff, 0xff000000ff000000, 0xff000000ff0000ff, + 0xff000000ff00ff00, 0xff000000ff00ffff, 0xff000000ffff0000, + 0xff000000ffff00ff, 0xff000000ffffff00, 0xff000000ffffffff, + 0xff0000ff00000000, 0xff0000ff000000ff, 0xff0000ff0000ff00, + 0xff0000ff0000ffff, 0xff0000ff00ff0000, 0xff0000ff00ff00ff, + 0xff0000ff00ffff00, 0xff0000ff00ffffff, 0xff0000ffff000000, + 0xff0000ffff0000ff, 0xff0000ffff00ff00, 0xff0000ffff00ffff, + 0xff0000ffffff0000, 0xff0000ffffff00ff, 0xff0000ffffffff00, + 0xff0000ffffffffff, 0xff00ff0000000000, 0xff00ff00000000ff, + 0xff00ff000000ff00, 0xff00ff000000ffff, 0xff00ff0000ff0000, + 0xff00ff0000ff00ff, 0xff00ff0000ffff00, 0xff00ff0000ffffff, + 0xff00ff00ff000000, 0xff00ff00ff0000ff, 0xff00ff00ff00ff00, + 0xff00ff00ff00ffff, 0xff00ff00ffff0000, 0xff00ff00ffff00ff, + 0xff00ff00ffffff00, 0xff00ff00ffffffff, 0xff00ffff00000000, + 0xff00ffff000000ff, 0xff00ffff0000ff00, 0xff00ffff0000ffff, + 0xff00ffff00ff0000, 0xff00ffff00ff00ff, 0xff00ffff00ffff00, + 0xff00ffff00ffffff, 0xff00ffffff000000, 0xff00ffffff0000ff, + 0xff00ffffff00ff00, 0xff00ffffff00ffff, 0xff00ffffffff0000, + 0xff00ffffffff00ff, 0xff00ffffffffff00, 0xff00ffffffffffff, + 0xffff000000000000, 0xffff0000000000ff, 0xffff00000000ff00, + 0xffff00000000ffff, 0xffff000000ff0000, 0xffff000000ff00ff, + 0xffff000000ffff00, 0xffff000000ffffff, 0xffff0000ff000000, + 0xffff0000ff0000ff, 0xffff0000ff00ff00, 0xffff0000ff00ffff, + 0xffff0000ffff0000, 0xffff0000ffff00ff, 0xffff0000ffffff00, + 0xffff0000ffffffff, 0xffff00ff00000000, 0xffff00ff000000ff, + 0xffff00ff0000ff00, 0xffff00ff0000ffff, 0xffff00ff00ff0000, + 0xffff00ff00ff00ff, 0xffff00ff00ffff00, 0xffff00ff00ffffff, + 0xffff00ffff000000, 0xffff00ffff0000ff, 0xffff00ffff00ff00, + 0xffff00ffff00ffff, 0xffff00ffffff0000, 0xffff00ffffff00ff, + 0xffff00ffffffff00, 0xffff00ffffffffff, 0xffffff0000000000, + 0xffffff00000000ff, 0xffffff000000ff00, 0xffffff000000ffff, + 0xffffff0000ff0000, 0xffffff0000ff00ff, 0xffffff0000ffff00, + 0xffffff0000ffffff, 0xffffff00ff000000, 0xffffff00ff0000ff, + 0xffffff00ff00ff00, 0xffffff00ff00ffff, 0xffffff00ffff0000, + 0xffffff00ffff00ff, 0xffffff00ffffff00, 0xffffff00ffffffff, + 0xffffffff00000000, 0xffffffff000000ff, 0xffffffff0000ff00, + 0xffffffff0000ffff, 0xffffffff00ff0000, 0xffffffff00ff00ff, + 0xffffffff00ffff00, 0xffffffff00ffffff, 0xffffffffff000000, + 0xffffffffff0000ff, 0xffffffffff00ff00, 0xffffffffff00ffff, + 0xffffffffffff0000, 0xffffffffffff00ff, 0xffffffffffffff00, + 0xffffffffffffffff, +}; + /* Signed saturating rounding doubling multiply-accumulate high half, 8-bi= t */ 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6qIWcsIdyvd/WEXoemLtY0kI6ipgVyVMlOE8Et+PoWA=; b=tkuBvrqTkCrM1EFLqjHBrRQbyzLWDhilmJ5QkfuDk4n6uUQIflF/g6lKdj0LfHzH/6 jZEE3UK09n7tPB404ZuMkVAm3tVMTTCPiQRRM/edEIeS83ieQo2vGBYBpKLXH5y1kzEz gXx49ojsWXwXIaCyX4QRAdtRuiDg9mPzg4BMvp/+tnsnYPZ+HOqdj76KVai9OEIhrpR3 n0tSXSHbUIGwrKGYLvas7RIsw2T84f7nOoN3W9F8oiDYn8WtyU9z/aMh/ETfy+81T1QD 4WLtAQin347eDFOu4TQapUJUpEBn10gNBW1bydB5Vc4UAM/94CN5bRV1i8RDRAI4Z+mX 7frw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6qIWcsIdyvd/WEXoemLtY0kI6ipgVyVMlOE8Et+PoWA=; b=jePUnnV6Kvaq0eLVNXAZbFL9aHjiQZZQ/yvzNIp1ILpOoG5iXkVf08p879cgv5WqJs ayobIU8+GHWhI0ZY/JomlR+CmCW3kiuBClSP9K/XWgD4+xD3xydR7vVJMXm5If+1tqxc w4vYR7I4+J1urc6dYvyt9h4dsBrIuiDdvnWS8XnkcCHYh/XzIYAG+R/OI4/WO3ZnOmaY GQs6148Gg2EeyQjI9UUatY7SL9D/WZ05wIavYjA97FMYlxLIbLZIhBFay6oXb6QGZP95 1OgcLZEAUTJT45NZV/JDGfqh7zDW6DT29ZUBnVmNLuT4j8SUPVInBIzLMz2FPpMLWymD HFlA== X-Gm-Message-State: AOAM533Xlk04kcMZehqUdY4FQlfATaB206eK3VfEolJsHPgsvxQfOarU Wir1+1EkSqh0LFQuim1xsgk1Qx7gdnIVqw== X-Google-Smtp-Source: ABdhPJzQpUCz7iIV6XZmJ4Izu7N0abR9bCn/XaZlPtRBxVyLBvG1AeXojjbM+MDG0qL2ClRb2z+hUA== X-Received: by 2002:adf:ef06:: with SMTP id e6mr26123947wro.393.1623771867432; Tue, 15 Jun 2021 08:44:27 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/28] bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations Date: Tue, 15 Jun 2021 16:44:04 +0100 Message-Id: <20210615154405.21399-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Currently the ARM SVE helper code defines locally some utility functions for swapping 16-bit halfwords within 32-bit or 64-bit values and for swapping 32-bit words within 64-bit values, parallel to the byte-swapping bswap16/32/64 functions. We want these also for the ARM MVE code, and they're potentially generally useful for other targets, so move them to bitops.h. (We don't put them in bswap.h with the bswap* functions because they are implemented in terms of the rotate operations also defined in bitops.h, and including bitops.h from bswap.h seems better avoided.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210614151007.4545-17-peter.maydell@linaro.org --- include/qemu/bitops.h | 29 +++++++++++++++++++++++++++++ target/arm/sve_helper.c | 20 -------------------- 2 files changed, 29 insertions(+), 20 deletions(-) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index a72f69fea85..03213ce952c 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -291,6 +291,35 @@ static inline uint64_t ror64(uint64_t word, unsigned i= nt shift) return (word >> shift) | (word << ((64 - shift) & 63)); } =20 +/** + * hswap32 - swap 16-bit halfwords within a 32-bit value + * @h: value to swap + */ +static inline uint32_t hswap32(uint32_t h) +{ + return rol32(h, 16); +} + +/** + * hswap64 - swap 16-bit halfwords within a 64-bit value + * @h: value to swap + */ +static inline uint64_t hswap64(uint64_t h) +{ + uint64_t m =3D 0x0000ffff0000ffffull; + h =3D rol64(h, 32); + return ((h & m) << 16) | ((h >> 16) & m); +} + +/** + * wswap64 - swap 32-bit words within a 64-bit value + * @h: value to swap + */ +static inline uint64_t wswap64(uint64_t h) +{ + return rol64(h, 32); +} + /** * extract32: * @value: the value to extract the bit field from diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 321098e2651..dab5f1d1cda 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -152,26 +152,6 @@ static inline uint64_t expand_pred_s(uint8_t byte) return word[byte & 0x11]; } =20 -/* Swap 16-bit words within a 32-bit word. */ -static inline uint32_t hswap32(uint32_t h) -{ - return rol32(h, 16); -} - -/* Swap 16-bit words within a 64-bit word. */ -static inline uint64_t hswap64(uint64_t h) -{ - uint64_t m =3D 0x0000ffff0000ffffull; - h =3D rol64(h, 32); - return ((h & m) << 16) | ((h >> 16) & m); -} - -/* Swap 32-bit words within a 64-bit word. */ -static inline uint64_t wswap64(uint64_t h) -{ - return rol64(h, 32); -} - #define LOGICAL_PPPP(NAME, FUNC) \ void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \ { \ --=20 2.20.1 From nobody Wed May 22 00:49:11 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623773416; cv=none; d=zohomail.com; s=zohoarc; b=V9kuBq6OwBn9E8fjMXhsmeB7fPFJiHJ+kdjl/PcuzVqb0pHy1YDNFQNKwGNkZriIxS/df4Bp8LuK7neuRkMC9k/6aWzBSika2lB1KCOnZ2slsA5YmIoiVx/7BXsrrxdkdeCE3N6eoCV/Oy+PFoXXvSL0SaAvQgd8YInOiVszfVE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623773416; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WrtQX3pfoBGhC0F6GqQ6Vwb/f3HNcfAIpvyb+RrPbHE=; b=WoY8BaeDP+RaDWyYRA7ZV6HVnak49lHNFPoLMVdPknWJ9Asv4MY5nYG4tuLbxakadwaRURnfe4RKP8BCPBu08GfsEOcAMTbEmRJu6igcWFt3tgM1n00ydPxqpKtZ8txO7JbQAzZixHOB8fY6VsyZ5yKoO8iUXhegMtOXGlu/bMY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623773416939688.4475523993503; Tue, 15 Jun 2021 09:10:16 -0700 (PDT) Received: from localhost ([::1]:59016 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ltBdo-0006Wp-93 for importer@patchew.org; Tue, 15 Jun 2021 12:10:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43172) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ltBFQ-0006k5-FY for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:45:04 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:54147) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ltBEs-00012n-Iy for qemu-devel@nongnu.org; Tue, 15 Jun 2021 11:45:04 -0400 Received: by mail-wm1-x334.google.com with SMTP id b205so9711338wmb.3 for ; Tue, 15 Jun 2021 08:44:28 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id d15sm18985662wri.58.2021.06.15.08.44.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Jun 2021 08:44:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=WrtQX3pfoBGhC0F6GqQ6Vwb/f3HNcfAIpvyb+RrPbHE=; b=EOLFIYQhu5HMyXO2RQ1N8JLWZivfcFef5VcwlarS+WFL6mYsyIw8emHXFMEREUE/n5 yRmtEQWVkICmfbA1qAp/CdTPDegzcbHG/6xjCBmJDXQkhEve9qiuqnIRpT2BDMMl9IqE eWXHE0prWQvjkf3gv8EGE4r2k6GI+pG9PUFA61RmTPx5bE96d8bZvS4TYensE/gVszrb NkCat2HlI5aHK+hfsL1rb5SuhYKChRD20jQQYaEoiIQrozVtgNgHsxAmnwZDpWCMk9Ya zblo3b6V8ZrktwoBn0IJaUZedlO2uOah/R+3xOQ8t+G8qYqK/K37EZCld4Mmc37/tiZl vsYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WrtQX3pfoBGhC0F6GqQ6Vwb/f3HNcfAIpvyb+RrPbHE=; b=olRNEOBo1gvFrPeUv6GG3aozPhnQ1sJZX2wRB+k2JKiDx5jPf+4LpWdQgGBepjGfLP xbCZ47yw4CGUnySm6K0zyijK8lIXfHhkmsvVaYiHjFljjZMP5/BeGvijjzcwYtvZ2/FD nn89wGm66DluigKTuq0TKJlejYTRtudQbBSgDr6FMQuip9YNIqnUrEc3i/O2yxzdMxIe xYYPonxLuUyIZmqNmjPPSTYBRXhUxyS8wQ98ogifu9YM+YJE/wUAmbzo5F9G10qx2xs4 Rh+H9ZNIzgJKmUYyQyazsMZWeFkEYx/Kj0Z27ORBvMmoOJWWrUYccqftVFyPydQ29/M+ FhZQ== X-Gm-Message-State: AOAM5312V/6LL0/Xn6r36FtengYkYgTVrIWm4dBer/uVBf9Pebpzn3om 5M1/wt27b1HkGeAZQV/fG44Z/e/lKiYgFQ== X-Google-Smtp-Source: ABdhPJwYHTxFi/ZMNZ2o6hNuT3kMRsLai+7YDqlscXBm0/QgSKYilPnjO8yeDZ5CuA2CvkcIetfVgw== X-Received: by 2002:a1c:35c2:: with SMTP id c185mr4723952wma.126.1623771868000; Tue, 15 Jun 2021 08:44:28 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/28] include/qemu/int128.h: Add function to create Int128 from int64_t Date: Tue, 15 Jun 2021 16:44:05 +0100 Message-Id: <20210615154405.21399-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210615154405.21399-1-peter.maydell@linaro.org> References: <20210615154405.21399-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) int128_make64() creates an Int128 from an unsigned 64 bit value; add a function int128_makes64() creating an Int128 from a signed 64 bit value. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210614151007.4545-34-peter.maydell@linaro.org --- include/qemu/int128.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/qemu/int128.h b/include/qemu/int128.h index 52fc2384211..64500385e37 100644 --- a/include/qemu/int128.h +++ b/include/qemu/int128.h @@ -11,6 +11,11 @@ static inline Int128 int128_make64(uint64_t a) return a; } =20 +static inline Int128 int128_makes64(int64_t a) +{ + return a; +} + static inline Int128 int128_make128(uint64_t lo, uint64_t hi) { return (__uint128_t)hi << 64 | lo; @@ -167,6 +172,11 @@ static inline Int128 int128_make64(uint64_t a) return (Int128) { a, 0 }; } =20 +static inline Int128 int128_makes64(int64_t a) +{ + return (Int128) { a, a >> 63 }; +} + static inline Int128 int128_make128(uint64_t lo, uint64_t hi) { return (Int128) { lo, hi }; --=20 2.20.1