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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U3o+F7dXXTuRNIJT1bjRgyFBMN63vTycsmuk+MLAR1w=; b=jWoYWYco0+YDUugtGfd3I7WLDBKPJYUQP/13p6ddmHaadMMb0C5N3g2fXdNIECbbgv s8KdTqo1CojnOPYIhtkiPPiHblZUALVWkRZGfrP7lux5e7hkssj8P6OS65pEB1Lfq96F k4FpC3/PgGIIbSysrZcIxVRZjXsBksorq3KXI4YAtvBv3eEta1xhLKy0hPVlecDIf7kb CFUz2xkP+6Ro6nm7Aktw8GFOEfx4TztvbJ3WMjYm4WQPA4Wzg+ENof3YiIv+cfP8wdjU QR3SHQjk8fRmcChdl1hZHz349JX7MHpmrTssqCrKsNuky0TDGco+4Y0y+OWIvo3ykfsK 5wiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U3o+F7dXXTuRNIJT1bjRgyFBMN63vTycsmuk+MLAR1w=; b=aC9PHghQ3VmS9FKe/zzsIENazcf2J3fwwX+N4P7sDzQ+TXvFmvDb45DhEXw5xe1/7R EmiU15bFN+HuZro4JABTnD55eU9WFHVvnr28tAiMAKXQ0xtU9DbILYYsfrHoAuyPD+EH J1+ju/M8o0B3kT+V1zpGJqkslqWzKdYwwPuC0joDBFmujVrnW3nX3+1Vc6EIFCocQxpm gImCHTiZaJIjCArf3ZGwnXNGhg0g/CPivcnkHn2lKx+dlb3bPNohU5bz/jl2oPyUDQzz xAP8OIqsGEHcFQQVIiWJbZQZfYfBUw0lnbWje5cavzH3QV9V46OukuUGhmzYTgv7AXyV wiaQ== X-Gm-Message-State: AOAM531IWgzLDPZwN0pPsaIW8yzdO7IxPwfT9cgBX/66osqJrngo25Pw IK0IFJD5P6Nmd0SyxbcSKVflQRPrEpl3JFgZ X-Google-Smtp-Source: ABdhPJy6B4ikOAphFhFSunKGgC+kVp9sv+ESBT4KynQdQDV2ngGPBV+DLhX5AYSI4o5Gktl5fYMfXQ== X-Received: by 2002:adf:e943:: with SMTP id m3mr18064269wrn.384.1623085104944; Mon, 07 Jun 2021 09:58:24 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 01/55] tcg: Introduce tcg_remove_ops_after Date: Mon, 7 Jun 2021 17:57:27 +0100 Message-Id: <20210607165821.9892-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Introduce a function to remove everything emitted since a given point. Cc: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20210604212747.959028-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/tcg/tcg.h | 1 + tcg/tcg.c | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 74cb3453083..6895246fab5 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -1081,6 +1081,7 @@ TCGOp *tcg_emit_op(TCGOpcode opc); void tcg_op_remove(TCGContext *s, TCGOp *op); TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc); TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc); +void tcg_remove_ops_after(TCGOp *op); =20 void tcg_optimize(TCGContext *s); =20 diff --git a/tcg/tcg.c b/tcg/tcg.c index 0dc271aac9f..262dbba1fde 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2649,6 +2649,19 @@ void tcg_op_remove(TCGContext *s, TCGOp *op) #endif } =20 +void tcg_remove_ops_after(TCGOp *op) +{ + TCGContext *s =3D tcg_ctx; + + while (true) { + TCGOp *last =3D tcg_last_op(); + if (last =3D=3D op) { + return; + } + tcg_op_remove(s, last); + } +} + static TCGOp *tcg_op_alloc(TCGOpcode opc) { TCGContext *s =3D tcg_ctx; --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623085583; cv=none; d=zohomail.com; s=zohoarc; b=K5wYg1p8q9p752bQlYQBxmCGqxa1BRWBVm2YiztisV6mQBzWESOk0BuYFUa9xWSrrM04RdZkBrW7oaMPguFpG+DsDH6JWY2DKEnlUbAOiaqlegAh8JP5KJor6WB7hBa5AODyF/DzMTc2mVWxLyFxSPgnDZC9Qjht7vHAf0dM3J8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623085583; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CIujDDcNE7g7Qj8fbS4YkgLm8m2I7lwGWPWf6+KDpnk=; b=TUB/STWT8h8j1OwEHZ7N/WxvCuzmcd7h07EHBut4Z9GdE3cRrvskRM8D88dWoiSJdD4SipTUty19ijkiSR/PAHXE/4R44WWNMtIvF2K4ZyMAxsc0xsjrQs4QXgl1TQMAenn8trYGxhdk9SGdMlgIaFXl5G4VNdu/OT+tGQ+604Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623085583428147.90842273692; Mon, 7 Jun 2021 10:06:23 -0700 (PDT) Received: from localhost ([::1]:51268 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqIhi-00005k-C1 for importer@patchew.org; Mon, 07 Jun 2021 13:06:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58918) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIa5-0006vs-Jm for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:29 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:44658) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIa3-0007qc-7X for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:29 -0400 Received: by mail-wr1-x431.google.com with SMTP id f2so18390601wri.11 for ; Mon, 07 Jun 2021 09:58:26 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CIujDDcNE7g7Qj8fbS4YkgLm8m2I7lwGWPWf6+KDpnk=; b=x8Qc1BMwrOmydxqbBntBqF2ycgQMPCSpfI2fmXOOit4XEzc0qYIykTOjKCM8jWwWap UJ2g4bjYQRJ95TXN1BBsY4HFAKQ1X+Z5IobV77bZKoiJ61bAmxHhSwPI1Xi/REWeaRzd XNYG4xqZXso+SehdVME1Rx+tf4alc6rbfMfnwLSe0Wpnff5qPt+kIONJW6u8ruLq4D5+ USYlbx9Mgc9LhEVb3wn9I6hCNelyrWl/DqKheSeh1aAGsOlN8CyqK0UQNptZRbvL3uLS bpw4R/8Ap0VNDTcTeCK8r5ZhUCKdT0LowWPbzw2ueo8xXP7QUThE3boOYD/ngx3Htahw vdFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CIujDDcNE7g7Qj8fbS4YkgLm8m2I7lwGWPWf6+KDpnk=; b=SDLZ4G8X1s+ncP5iJ8c9Gc/SbNvhsbMBg9O7TBQN/SigMjA1k0NDNpaJJyPwYiJwTU YcVkYdzO7NLXnSc9PPfiMGppgDJHw7qHSs6/aafiZMTVJqPIg7ZFrkRNESC5iOlAVfd/ BAwSPCiaZm46Or5cT8bIgU8wc7GT93RpQbA6cn+1+bi0diLSeiYtbg6I2RQ6sOrW/pKB 1a5FF5siHOfj7wIaYd/msoNfMuwGMUzXIlhhGNe8oeBBc/RKtgGSOOcbiYhDmKaXF89I gfegfSyd3W4kFiiGEFQfkX/o5Mqg2DstboeDoj5navml646sXochkqm40rMTNq4yex9X yZdQ== X-Gm-Message-State: AOAM530Zeu3Nfq7lPOIAdfofd/666mfC2er3FM3Y96UqXewkIZWnL6Zu VufHmERGy1h7vvu6eZCUIOnCfbTaMNbjU0xO X-Google-Smtp-Source: ABdhPJzimc4ILLc97koVNzWXNuc3E0+dB8OTDNZVk1x54C4zJkiA71s9/kKl1izNAOhv6WauZov7yg== X-Received: by 2002:a5d:5243:: with SMTP id k3mr18357427wrc.19.1623085105917; Mon, 07 Jun 2021 09:58:25 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 02/55] target/arm: Enable FPSCR.QC bit for MVE Date: Mon, 7 Jun 2021 17:57:28 +0100 Message-Id: <20210607165821.9892-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" MVE has an FPSCR.QC bit similar to the A-profile Neon one; when MVE is implemented make the bit writeable, both in the generic "load and store FPSCR" helper functions and in the code for handling the NZCVQC sysreg which we had previously left as "TODO when we implement MVE". Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.c | 32 +++++++++++++++++++++++--------- target/arm/vfp_helper.c | 3 ++- 2 files changed, 25 insertions(+), 10 deletions(-) diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index d01e465821b..22a619eb2c5 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -784,10 +784,19 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, in= t regno, { TCGv_i32 fpscr; tmp =3D loadfn(s, opaque); - /* - * TODO: when we implement MVE, write the QC bit. - * For non-MVE, QC is RES0. - */ + if (dc_isar_feature(aa32_mve, s)) { + /* QC is only present for MVE; otherwise RES0 */ + TCGv_i32 qc =3D tcg_temp_new_i32(); + TCGv_i32 zero; + tcg_gen_andi_i32(qc, tmp, FPCR_QC); + store_cpu_field(qc, vfp.qc[0]); + zero =3D tcg_const_i32(0); + store_cpu_field(zero, vfp.qc[1]); + zero =3D tcg_const_i32(0); + store_cpu_field(zero, vfp.qc[2]); + zero =3D tcg_const_i32(0); + store_cpu_field(zero, vfp.qc[3]); + } tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); fpscr =3D load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK); @@ -869,6 +878,11 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int = regno, break; } =20 + if (regno =3D=3D ARM_VFP_FPSCR_NZCVQC && !dc_isar_feature(aa32_mve, s)= ) { + /* QC is RES0 without MVE, so NZCVQC simplifies to NZCV */ + regno =3D QEMU_VFP_FPSCR_NZCV; + } + switch (regno) { case ARM_VFP_FPSCR: tmp =3D tcg_temp_new_i32(); @@ -876,11 +890,11 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int= regno, storefn(s, opaque, tmp); break; case ARM_VFP_FPSCR_NZCVQC: - /* - * TODO: MVE has a QC bit, which we probably won't store - * in the xregs[] field. For non-MVE, where QC is RES0, - * we can just fall through to the FPSCR_NZCV case. - */ + tmp =3D tcg_temp_new_i32(); + gen_helper_vfp_get_fpscr(tmp, cpu_env); + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCVQC_MASK); + storefn(s, opaque, tmp); + break; case QEMU_VFP_FPSCR_NZCV: /* * Read just NZCV; this is a special case to avoid the diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 496f0034772..8a716600592 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -220,7 +220,8 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t v= al) FPCR_LTPSIZE_LENGTH); } =20 - if (arm_feature(env, ARM_FEATURE_NEON)) { + if (arm_feature(env, ARM_FEATURE_NEON) || + cpu_isar_feature(aa32_mve, cpu)) { /* * The bit we set within fpscr_q is arbitrary; the register as a * whole being zero/non-zero is what counts. --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623085731; cv=none; d=zohomail.com; s=zohoarc; b=YEJqe4ZX/Zr6Nxjh25U4umUXgMRLfG+YuqjZI65qMYdwl2nCcibARXgShP7yVVpJyrKxgQfgLW3TtFTuRki8kK7WdKv1mHJXkH8sF6cCY/spGqW6ua8v1L+R+Ps6JzvdfC0LbpYA5mTGVBep1EpaHX8Q9uLrWS27LTP2zqqbxw4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623085731; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=d0cq2glmaOXLFFMAcMfsHZ1d9+vbQKJMxSiU/M7kWqw=; b=XOkO/On8xiq+bhsqE3tnrU+ZmkS3xuWpU8AEHp3LlrrEOlsylpthelsRVAkpe4fbCB5akHF1LwJm5DHTZ+P+upCQXStmoD7+rYai7ZPtKfRTdkTH/xHWiZuioerLi/zxrfS6eudFmoya/pyoxOMqEIxZRmcy6Kmh5LeZIdVOhlE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623085731521602.6311160198678; Mon, 7 Jun 2021 10:08:51 -0700 (PDT) Received: from localhost ([::1]:60002 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqIk6-0005xp-LG for importer@patchew.org; Mon, 07 Jun 2021 13:08:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58934) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIa6-0006wn-5x for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:30 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:41799) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIa4-0007r8-1s for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:29 -0400 Received: by mail-wr1-x436.google.com with SMTP id o3so38326wri.8 for ; Mon, 07 Jun 2021 09:58:27 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d0cq2glmaOXLFFMAcMfsHZ1d9+vbQKJMxSiU/M7kWqw=; b=pZuUBspDQnoaGEZ7RQoaMpW2nH3luK/HfKTdB2xn4D22GUbz5EuXZGVqyTjf5LeXGy skyWX3gNhS+YlorF7UeuVTZJlm9VgJpbxW/sX1gDgYtWNv09TNkOSLEzhHVNPWmDe9oP 2YXz6CfCzlAdhwaBl1Qug9EQRHJt+k1ZgT7fWPuD/CPLnrXbOX8R55ozob99ghDiIioY IBrV/oLzI8ixpzmoQL4ZGjtHl3kHftjEsh9ghHk2Rz/plYYoNu1bAY6VKV7UDM1kHaWC 4AQkd2vVnjqBPLtHCxNdbIQ0e2yIbZYt6+jC7UbNK+bqUv/6kwU+r7p8Zff6uPNEJX1K gUrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d0cq2glmaOXLFFMAcMfsHZ1d9+vbQKJMxSiU/M7kWqw=; b=WLS/fPkjXXNCL59AwEhdX0AvYcl/opKgekPrcO9YKmcTA8+6VI4oeE3xc5fbcimkYA TAVKoc7+pzCYiHxG4r354gDPoVhlBQteYViELqPEq1pESPGFLu3FVtNrC1kVI4C43VKY b6vgv19R259s9GTl96NEeJagITXRtSB4zx/M40ZaiL+3ly/4kGSSFcy4ts1SASDGiEv2 sUwhMhI4eKCDTQjjpcw24beOlpZEuuvev9fTAh3b+Uqe9dRfiwa/PW0Y0PFf6gEOWWoV GMybOuElzXX0yd7L4IhZy+fPq642VWejg1B/gO3vd4IKxaXxOrmUDM2thg0qMUh97wqO vzzA== X-Gm-Message-State: AOAM530c2T+swv5IbxwebzYRN+S64wzjf+XDZx/7sWcjKRSv6QHyghV4 zvS0ULZh/tqNdfenohdkltScBA== X-Google-Smtp-Source: ABdhPJxnrNFL4q8FmcvlPVvBTeMZjULog/S0dudWHBKDbpnmiQDm3zbCdnG3b2BfN1gOxDErbmy1hw== X-Received: by 2002:a5d:6111:: with SMTP id v17mr8369421wrt.20.1623085106737; Mon, 07 Jun 2021 09:58:26 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 03/55] target/arm: Handle VPR semantics in existing code Date: Mon, 7 Jun 2021 17:57:29 +0100 Message-Id: <20210607165821.9892-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" When MVE is supported, the VPR register has a place on the exception stack frame in a previously reserved slot just above the FPSCR. It must also be zeroed in various situations when we invalidate FPU context. Update the code which handles the stack frames (exception entry and exit code, VLLDM, and VLSTM) to save/restore VPR. Update code which invalidates FP registers (mostly also exception entry and exit code, but also VSCCLRM and the code in full_vfp_access_check() that corresponds to the ExecuteFPCheck() pseudocode) to zero VPR. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/m_helper.c | 54 +++++++++++++++++++++++++++++------ target/arm/translate-m-nocp.c | 5 +++- target/arm/translate-vfp.c | 9 ++++-- 3 files changed, 57 insertions(+), 11 deletions(-) diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 074c5434550..7a1e35ab5b6 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -378,7 +378,7 @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env) uint32_t shi =3D extract64(dn, 32, 32); =20 if (i >=3D 16) { - faddr +=3D 8; /* skip the slot for the FPSCR */ + faddr +=3D 8; /* skip the slot for the FPSCR/VPR */ } stacked_ok =3D stacked_ok && v7m_stack_write(cpu, faddr, slo, mmu_idx, STACK_LAZYFP) && @@ -388,6 +388,11 @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env) stacked_ok =3D stacked_ok && v7m_stack_write(cpu, fpcar + 0x40, vfp_get_fpscr(env), mmu_idx, STACK_LAZYFP); + if (cpu_isar_feature(aa32_mve, cpu)) { + stacked_ok =3D stacked_ok && + v7m_stack_write(cpu, fpcar + 0x44, + env->v7m.vpr, mmu_idx, STACK_LAZYFP); + } } =20 /* @@ -410,16 +415,19 @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env) env->v7m.fpccr[is_secure] &=3D ~R_V7M_FPCCR_LSPACT_MASK; =20 if (ts) { - /* Clear s0 to s31 and the FPSCR */ + /* Clear s0 to s31 and the FPSCR and VPR */ int i; =20 for (i =3D 0; i < 32; i +=3D 2) { *aa32_vfp_dreg(env, i / 2) =3D 0; } vfp_set_fpscr(env, 0); + if (cpu_isar_feature(aa32_mve, cpu)) { + env->v7m.vpr =3D 0; + } } /* - * Otherwise s0 to s15 and FPSCR are UNKNOWN; we choose to leave them + * Otherwise s0 to s15, FPSCR and VPR are UNKNOWN; we choose to leave = them * unchanged. */ } @@ -1044,6 +1052,7 @@ static void v7m_update_fpccr(CPUARMState *env, uint32= _t frameptr, void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) { /* fptr is the value of Rn, the frame pointer we store the FP regs to = */ + ARMCPU *cpu =3D env_archcpu(env); bool s =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; bool lspact =3D env->v7m.fpccr[s] & R_V7M_FPCCR_LSPACT_MASK; uintptr_t ra =3D GETPC(); @@ -1092,9 +1101,12 @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fp= tr) cpu_stl_data_ra(env, faddr + 4, shi, ra); } cpu_stl_data_ra(env, fptr + 0x40, vfp_get_fpscr(env), ra); + if (cpu_isar_feature(aa32_mve, cpu)) { + cpu_stl_data_ra(env, fptr + 0x44, env->v7m.vpr, ra); + } =20 /* - * If TS is 0 then s0 to s15 and FPSCR are UNKNOWN; we choose to + * If TS is 0 then s0 to s15, FPSCR and VPR are UNKNOWN; we choose= to * leave them unchanged, matching our choice in v7m_preserve_fp_st= ate. */ if (ts) { @@ -1102,6 +1114,9 @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fpt= r) *aa32_vfp_dreg(env, i / 2) =3D 0; } vfp_set_fpscr(env, 0); + if (cpu_isar_feature(aa32_mve, cpu)) { + env->v7m.vpr =3D 0; + } } } else { v7m_update_fpccr(env, fptr, false); @@ -1112,6 +1127,7 @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fpt= r) =20 void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr) { + ARMCPU *cpu =3D env_archcpu(env); uintptr_t ra =3D GETPC(); =20 /* fptr is the value of Rn, the frame pointer we load the FP regs from= */ @@ -1144,7 +1160,7 @@ void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fpt= r) uint32_t faddr =3D fptr + 4 * i; =20 if (i >=3D 16) { - faddr +=3D 8; /* skip the slot for the FPSCR */ + faddr +=3D 8; /* skip the slot for the FPSCR and VPR */ } =20 slo =3D cpu_ldl_data_ra(env, faddr, ra); @@ -1155,6 +1171,9 @@ void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fpt= r) } fpscr =3D cpu_ldl_data_ra(env, fptr + 0x40, ra); vfp_set_fpscr(env, fpscr); + if (cpu_isar_feature(aa32_mve, cpu)) { + env->v7m.vpr =3D cpu_ldl_data_ra(env, fptr + 0x44, ra); + } } =20 env->v7m.control[M_REG_S] |=3D R_V7M_CONTROL_FPCA_MASK; @@ -1298,7 +1317,7 @@ static bool v7m_push_stack(ARMCPU *cpu) uint32_t shi =3D extract64(dn, 32, 32); =20 if (i >=3D 16) { - faddr +=3D 8; /* skip the slot for the FPSCR */ + faddr +=3D 8; /* skip the slot for the FPSCR and V= PR */ } stacked_ok =3D stacked_ok && v7m_stack_write(cpu, faddr, slo, @@ -1309,11 +1328,19 @@ static bool v7m_push_stack(ARMCPU *cpu) stacked_ok =3D stacked_ok && v7m_stack_write(cpu, frameptr + 0x60, vfp_get_fpscr(env), mmu_idx, STACK_NOR= MAL); + if (cpu_isar_feature(aa32_mve, cpu)) { + stacked_ok =3D stacked_ok && + v7m_stack_write(cpu, frameptr + 0x64, + env->v7m.vpr, mmu_idx, STACK_NORMA= L); + } if (cpacr_pass) { for (i =3D 0; i < ((framesize =3D=3D 0xa8) ? 32 : 16);= i +=3D 2) { *aa32_vfp_dreg(env, i / 2) =3D 0; } vfp_set_fpscr(env, 0); + if (cpu_isar_feature(aa32_mve, cpu)) { + env->v7m.vpr =3D 0; + } } } else { /* Lazy stacking enabled, save necessary info to stack lat= er */ @@ -1536,13 +1563,16 @@ static void do_v7m_exception_exit(ARMCPU *cpu) v7m_exception_taken(cpu, excret, true, false); } } - /* Clear s0..s15 and FPSCR; TODO also VPR when MVE is implemen= ted */ + /* Clear s0..s15, FPSCR and VPR */ int i; =20 for (i =3D 0; i < 16; i +=3D 2) { *aa32_vfp_dreg(env, i / 2) =3D 0; } vfp_set_fpscr(env, 0); + if (cpu_isar_feature(aa32_mve, cpu)) { + env->v7m.vpr =3D 0; + } } } =20 @@ -1771,7 +1801,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) uint32_t faddr =3D frameptr + 0x20 + 4 * i; =20 if (i >=3D 16) { - faddr +=3D 8; /* Skip the slot for the FPSCR */ + faddr +=3D 8; /* Skip the slot for the FPSCR and V= PR */ } =20 pop_ok =3D pop_ok && @@ -1790,6 +1820,11 @@ static void do_v7m_exception_exit(ARMCPU *cpu) if (pop_ok) { vfp_set_fpscr(env, fpscr); } + if (cpu_isar_feature(aa32_mve, cpu)) { + pop_ok =3D pop_ok && + v7m_stack_read(cpu, &env->v7m.vpr, + frameptr + 0x64, mmu_idx); + } if (!pop_ok) { /* * These regs are 0 if security extension present; @@ -1799,6 +1834,9 @@ static void do_v7m_exception_exit(ARMCPU *cpu) *aa32_vfp_dreg(env, i / 2) =3D 0; } vfp_set_fpscr(env, 0); + if (cpu_isar_feature(aa32_mve, cpu)) { + env->v7m.vpr =3D 0; + } } } } diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c index d47eb8e1535..365810e582d 100644 --- a/target/arm/translate-m-nocp.c +++ b/target/arm/translate-m-nocp.c @@ -173,7 +173,10 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM= *a) btmreg++; } assert(btmreg =3D=3D topreg + 1); - /* TODO: when MVE is implemented, zero VPR here */ + if (dc_isar_feature(aa32_mve, s)) { + TCGv_i32 z32 =3D tcg_const_i32(0); + store_cpu_field(z32, v7m.vpr); + } return true; } =20 diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 22a619eb2c5..c3504bd3b86 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -180,8 +180,8 @@ static bool full_vfp_access_check(DisasContext *s, bool= ignore_vfp_enabled) =20 if (s->v7m_new_fp_ctxt_needed) { /* - * Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA - * and the FPSCR. + * Create new FP context by updating CONTROL.FPCA, CONTROL.SFP= A, + * the FPSCR, and VPR. */ TCGv_i32 control, fpscr; uint32_t bits =3D R_V7M_CONTROL_FPCA_MASK; @@ -189,6 +189,11 @@ static bool full_vfp_access_check(DisasContext *s, boo= l ignore_vfp_enabled) fpscr =3D load_cpu_field(v7m.fpdscr[s->v8m_secure]); gen_helper_vfp_set_fpscr(cpu_env, fpscr); tcg_temp_free_i32(fpscr); + if (dc_isar_feature(aa32_mve, s)) { + TCGv_i32 z32 =3D tcg_const_i32(0); + store_cpu_field(z32, v7m.vpr); + } + /* * We don't need to arrange to end the TB, because the only * parts of FPSCR which we cache in the TB flags are the VECLEN --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623085588; cv=none; d=zohomail.com; s=zohoarc; b=JbYLuERnc5ZZ1gDtwPnr6FOr+mjxEQC2vUUcFhso8YhyLebmtu8CzJWSPkoNZlUIjL8Rc7YAJadfHn5/zkbjLNedh+1U+mYrvKUq1og73wzijpBgXI+6GI5SHXMS9G4k8/u2EY5IJl72lgeHAb7OrIV/hYSaNNL+0gROKVnzuzU= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ux9NZyolwz8PxrWquRBwBSFjhHX2d5U3HDl8/CMxLK8=; b=NRvcRQzFRZkPw1dlTaesV5rbCqSODsokM8pMMMnlq0WX3k99RQ5xYF93cOKuZAVso9 6UvH809VR7gV7OPVH5y43T2eV7SWfvrvWkgbkXeQdD/85tq+fotc97MenIWoaibLrLw0 JN5SoAXzu6sGNZJmYOuNTg0jPExNJ5WCGaezDcsc4Qjv+md9yssLDA12E0hokMigxMWV Q1IvtTr3piRuPRuxICB54M+PzUR4NaV+lzhv2KUI6TIlnm2LpYX0Qc3qz6GOnrUBZO/O Oqrb/XoNDPtDSXeM/ojOMy7jewoAn+bqNbkT6/dEuRgkgKBNibuHAC2fPzIs/ZpFoEBU jAHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ux9NZyolwz8PxrWquRBwBSFjhHX2d5U3HDl8/CMxLK8=; b=W5nDWdwOuS1l9nu/ArFWNO36V9FrF8RLgESBLJpWV6RO/GgPwmieh7/uVpiZJo5+8J rLj+LXw5bkHmr50QCLFDw5S/qJQAJF+qYm8Ph6Ee5Bk/JfTX11skCslMpG8hx5ZrLX10 6WiIMWQ4hC8rhRuLp43RV+r14Wn9a4HSAQ+HoIQbiGsIaaBcbSfOyvcySpUIeB7lWidq Zwcw8bDElwh2OhBk3+XzMi3Dsr5zikIwKZCKKfJDTneaRZ5H3+vESk1aX2oQ/mAA3Mgy OnVA8ImveLxUpF/DNagduqM2JnxghqM7Zf8dQKf/rIQU6K0V4W5T6B5CsxqBGiMHVaKL yM8g== X-Gm-Message-State: AOAM533CUO5XurdWwTQgEFvA2hzN2so+zaip6qr4/J/w/nhLJzGt93At jXXCNrrfVjDTp8x3FD/eoKrtRuaojDCAjz89 X-Google-Smtp-Source: ABdhPJzyiP5XmxOsgz+t7zbl7Pa5ZVEUJnJ0mU/g5zVo1XCNSF9JsdlwsXwE3tcfXmVR3fMwgMaWWw== X-Received: by 2002:a5d:6382:: with SMTP id p2mr18887654wru.338.1623085107659; Mon, 07 Jun 2021 09:58:27 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 04/55] target/arm: Add handling for PSR.ECI/ICI Date: Mon, 7 Jun 2021 17:57:30 +0100 Message-Id: <20210607165821.9892-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" On A-profile, PSR bits [15:10][26:25] are always the IT state bits. On M-profile, some of the reserved encodings of the IT state are used to instead indicate partial progress through instructions that were interrupted partway through by an exception and can be resumed. These resumable instructions fall into two categories: (1) load/store multiple instructions, where these bits are called "ICI" and specify the register in the ldm/stm list where execution should resume. (Specifically: LDM, STM, VLDM, VSTM, VLLDM, VLSTM, CLRM, VSCCLRM.) (2) MVE instructions subject to beatwise execution, where these bits are called "ECI" and specify which beats in this and possibly also the following MVE insn have been executed. There are also a few insns (LE, LETP, and BKPT) which do not use the ICI/ECI bits but must leave them alone. Otherwise, we should raise an INVSTATE UsageFault for any attempt to execute an insn with non-zero ICI/ECI bits. So far we have been able to ignore ECI/ICI, because the architecture allows the IMPDEF choice of "always restart load/store multiple from the beginning regardless of ICI state", so the only thing we have been missing is that we don't raise the INVSTATE fault for bad guest code. However, MVE requires that we honour ECI bits and do not rexecute beats of an insn that have already been executed. Add the support in the decoder for handling ECI/ICI: * identify the ECI/ICI case in the CONDEXEC TB flags * when a load/store multiple insn succeeds, it updates the ECI/ICI state (both in DisasContext and in the CPU state), and sets a flag to say that the ECI/ICI state was handled * if we find that the insn we just decoded did not handle the ECI/ICI state, we delete all the code that we just generated for it and instead emit the code to raise the INVFAULT. This allows us to avoid having to update every non-MVE non-LDM/STM insn to make it check for "is ECI/ICI set?". We continue with our existing IMPDEF choice of not caring about the ICI state for the load/store multiples and simply restarting them from the beginning. Because we don't allow interrupts in the middle of an insn, the only way we would see this state is if the guest set ICI manually on return from an exception handler, so it's a corner case which doesn't merit optimisation. ICI update for LDM/STM is simple -- it always zeroes the state. ECI update for MVE beatwise insns will be a little more complex, since the ECI state may include information for the following insn. Signed-off-by: Peter Maydell --- target/arm/translate-a32.h | 1 + target/arm/translate.h | 9 +++ target/arm/translate-m-nocp.c | 11 ++++ target/arm/translate-vfp.c | 6 ++ target/arm/translate.c | 113 ++++++++++++++++++++++++++++++++-- 5 files changed, 135 insertions(+), 5 deletions(-) diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index c997f4e3216..c946ac440ce 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -44,6 +44,7 @@ long vfp_reg_offset(bool dp, unsigned reg); long neon_full_reg_offset(unsigned reg); long neon_element_offset(int reg, int element, MemOp memop); void gen_rev16(TCGv_i32 dest, TCGv_i32 var); +void clear_eci_state(DisasContext *s); =20 static inline TCGv_i32 load_cpu_offset(int offset) { diff --git a/target/arm/translate.h b/target/arm/translate.h index 12c28b0d32c..2821b325e33 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -21,6 +21,15 @@ typedef struct DisasContext { /* Thumb-2 conditional execution bits. */ int condexec_mask; int condexec_cond; + /* M-profile ECI/ICI exception-continuable instruction state */ + int eci; + /* + * trans_ functions for insns which are continuable should set this tr= ue + * after decode (ie after any UNDEF checks) + */ + bool eci_handled; + /* TCG op to rewind to if this turns out to be an invalid ECI state */ + TCGOp *insn_eci_rewind; int thumb; int sctlr_b; MemOp be_data; diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c index 365810e582d..09b3be4ed31 100644 --- a/target/arm/translate-m-nocp.c +++ b/target/arm/translate-m-nocp.c @@ -75,8 +75,12 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM= _VLSTM *a) unallocated_encoding(s); return true; } + + s->eci_handled =3D true; + /* If no fpu, NOP. */ if (!dc_isar_feature(aa32_vfp, s)) { + clear_eci_state(s); return true; } =20 @@ -88,6 +92,8 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_= VLSTM *a) } tcg_temp_free_i32(fptr); =20 + clear_eci_state(s); + /* End the TB, because we have updated FP control bits */ s->base.is_jmp =3D DISAS_UPDATE_EXIT; return true; @@ -110,8 +116,11 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM= *a) return true; } =20 + s->eci_handled =3D true; + if (!dc_isar_feature(aa32_vfp_simd, s)) { /* NOP if we have neither FP nor MVE */ + clear_eci_state(s); return true; } =20 @@ -177,6 +186,8 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM = *a) TCGv_i32 z32 =3D tcg_const_i32(0); store_cpu_field(z32, v7m.vpr); } + + clear_eci_state(s); return true; } =20 diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index c3504bd3b86..3a56639e708 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -1564,6 +1564,8 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_V= LDM_VSTM_sp *a) return false; } =20 + s->eci_handled =3D true; + if (!vfp_access_check(s)) { return true; } @@ -1613,6 +1615,7 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_V= LDM_VSTM_sp *a) tcg_temp_free_i32(addr); } =20 + clear_eci_state(s); return true; } =20 @@ -1647,6 +1650,8 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_V= LDM_VSTM_dp *a) return false; } =20 + s->eci_handled =3D true; + if (!vfp_access_check(s)) { return true; } @@ -1703,6 +1708,7 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_V= LDM_VSTM_dp *a) tcg_temp_free_i32(addr); } =20 + clear_eci_state(s); return true; } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 8e0e55c1e0f..1a7a32c1be4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -309,6 +309,20 @@ static inline bool is_singlestepping(DisasContext *s) return s->base.singlestep_enabled || s->ss_active; } =20 +void clear_eci_state(DisasContext *s) +{ + /* + * Clear any ECI/ICI state: used when a load multiple/store + * multiple insn executes. + */ + if (s->eci) { + TCGv_i32 tmp =3D tcg_temp_new_i32(); + tcg_gen_movi_i32(tmp, 0); + store_cpu_field(tmp, condexec_bits); + s->eci =3D 0; + } +} + static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) { TCGv_i32 tmp1 =3D tcg_temp_new_i32(); @@ -6203,6 +6217,8 @@ static bool trans_BKPT(DisasContext *s, arg_BKPT *a) if (!ENABLE_ARCH_5) { return false; } + /* BKPT is OK with ECI set and leaves it untouched */ + s->eci_handled =3D true; if (arm_dc_feature(s, ARM_FEATURE_M) && semihosting_enabled() && #ifndef CONFIG_USER_ONLY @@ -7767,6 +7783,8 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a= , int min_n) return true; } =20 + s->eci_handled =3D true; + addr =3D op_addr_block_pre(s, a, n); mem_idx =3D get_mem_index(s); =20 @@ -7793,6 +7811,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a= , int min_n) } =20 op_addr_block_post(s, a, addr, n); + clear_eci_state(s); return true; } =20 @@ -7847,6 +7866,8 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a= , int min_n) return true; } =20 + s->eci_handled =3D true; + addr =3D op_addr_block_pre(s, a, n); mem_idx =3D get_mem_index(s); loaded_base =3D false; @@ -7897,6 +7918,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a= , int min_n) /* Must exit loop to check un-masked IRQs */ s->base.is_jmp =3D DISAS_EXIT; } + clear_eci_state(s); return true; } =20 @@ -7952,6 +7974,8 @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a) return false; } =20 + s->eci_handled =3D true; + zero =3D tcg_const_i32(0); for (i =3D 0; i < 15; i++) { if (extract32(a->list, i, 1)) { @@ -7969,6 +7993,7 @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a) tcg_temp_free_i32(maskreg); } tcg_temp_free_i32(zero); + clear_eci_state(s); return true; } =20 @@ -8150,6 +8175,9 @@ static bool trans_LE(DisasContext *s, arg_LE *a) return false; } =20 + /* LE/LETP is OK with ECI set and leaves it untouched */ + s->eci_handled =3D true; + if (!a->f) { /* Not loop-forever. If LR <=3D 1 this is the last loop: do nothin= g. */ arm_gen_condlabel(s); @@ -8775,8 +8803,28 @@ static void arm_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) dc->thumb =3D EX_TBFLAG_AM32(tb_flags, THUMB); dc->be_data =3D EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE; condexec =3D EX_TBFLAG_AM32(tb_flags, CONDEXEC); - dc->condexec_mask =3D (condexec & 0xf) << 1; - dc->condexec_cond =3D condexec >> 4; + /* + * the CONDEXEC TB flags are CPSR bits [15:10][26:25]. On A-profile th= is + * is always the IT bits. On M-profile, some of the reserved encodings + * of IT are used instead to indicate either ICI or ECI, which + * indicate partial progress of a restartable insn that was interrupted + * partway through by an exception: + * * if CONDEXEC[3:0] !=3D 0b0000 : CONDEXEC is IT bits + * * if CONDEXEC[3:0] =3D=3D 0b0000 : CONDEXEC is ICI or ECI bits + * In all cases CONDEXEC =3D=3D 0 means "not in IT block or restartable + * insn, behave normally". + */ + if (condexec & 0xf) { + dc->condexec_mask =3D (condexec & 0xf) << 1; + dc->condexec_cond =3D condexec >> 4; + dc->eci =3D 0; + } else { + dc->condexec_mask =3D 0; + dc->condexec_cond =3D 0; + if (arm_feature(env, ARM_FEATURE_M)) { + dc->eci =3D condexec >> 4; + } + } =20 core_mmu_idx =3D EX_TBFLAG_ANY(tb_flags, MMUIDX); dc->mmu_idx =3D core_to_arm_mmu_idx(env, core_mmu_idx); @@ -8898,10 +8946,19 @@ static void arm_tr_tb_start(DisasContextBase *dcbas= e, CPUState *cpu) static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); + /* + * The ECI/ICI bits share PSR bits with the IT bits, so we + * need to reconstitute the bits from the split-out DisasContext + * fields here. + */ + uint32_t condexec_bits; =20 - tcg_gen_insn_start(dc->base.pc_next, - (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), - 0); + if (dc->eci) { + condexec_bits =3D dc->eci << 4; + } else { + condexec_bits =3D (dc->condexec_cond << 4) | (dc->condexec_mask >>= 1); + } + tcg_gen_insn_start(dc->base.pc_next, condexec_bits, 0); dc->insn_start =3D tcg_last_op(); } =20 @@ -9067,6 +9124,41 @@ static void thumb_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) } dc->insn =3D insn; =20 + if (dc->eci) { + /* + * For M-profile continuable instructions, ECI/ICI handling + * falls into these cases: + * - interrupt-continuable instructions + * These are the various load/store multiple insns (both + * integer and fp). The ICI bits indicate the register + * where the load/store can resume. We make the IMPDEF + * choice to always do "instruction restart", ie ignore + * the ICI value and always execute the ldm/stm from the + * start. So all we need to do is zero PSR.ICI if the + * insn executes. + * - MVE instructions subject to beat-wise execution + * Here the ECI bits indicate which beats have already been + * executed, and we must honour this. Each insn of this + * type will handle it correctly. We will update PSR.ECI + * in the helper function for the insn (some ECI values + * mean that the following insn also has been partially + * executed). + * - Special cases which don't advance ECI + * The insns LE, LETP and BKPT leave the ECI/ICI state + * bits untouched. + * - all other insns (the common case) + * Non-zero ECI/ICI means an INVSTATE UsageFault. + * We place a rewind-marker here. Insns in the previous + * three categories will set a flag in the DisasContext. + * If the flag isn't set after we call disas_thumb_insn() + * or disas_thumb2_insn() then we know we have a "some other + * insn" case. We will rewind to the marker (ie throwing away + * all the generated code) and instead emit "take exception". + */ + dc->eci_handled =3D false; + dc->insn_eci_rewind =3D tcg_last_op(); + } + if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) { uint32_t cond =3D dc->condexec_cond; =20 @@ -9095,6 +9187,17 @@ static void thumb_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) } } =20 + if (dc->eci && !dc->eci_handled) { + /* + * Insn wasn't valid for ECI/ICI at all: undo what we + * just generated and instead emit an exception + */ + tcg_remove_ops_after(dc->insn_eci_rewind); + dc->condjmp =3D 0; + gen_exception_insn(dc, dc->pc_curr, EXCP_INVSTATE, syn_uncategoriz= ed(), + default_exception_el(dc)); + } + arm_post_translate_insn(dc); =20 /* Thumb is a variable-length ISA. Stop translation when the next insn --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623085383; cv=none; d=zohomail.com; s=zohoarc; b=k82I6YsLccuCBV9L0zc6r1UFQE9A7ICSjsBXI8YQdp0+OFppWYdyA+OXzS4VELu8iHbH9bjBCPniVvbfW0g06c31Vk5sD40DYQ5KbADqJkU1OsBm42Dk0zaLTXDwgqJynHmAJBy4RNCPggjlDGoD0oDAVwZrncbkpzJXsvEqUgg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623085383; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WP6bAnl0XFv6sI86ENYvVNq1701QvYCzpF74EEud+5Y=; b=HrS/ZxRKxtIAMZljIs7uGMeLHzYWy3OzTcd/F0DoRFulOFdvNODqPZ8Hljnwu/G6KJsKqGNopchiF1vIOyonwhyy4sQckHE0VA5JfvMU0ha6ZOJ4hrNjg9WK8NuJENh9xgW4A779wWXxw0dXckq3q4G0r+VPjjD2A+/Y/I69uBI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623085383290982.3902056258902; Mon, 7 Jun 2021 10:03:03 -0700 (PDT) Received: from localhost ([::1]:42998 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqIeU-0002wM-2a for importer@patchew.org; Mon, 07 Jun 2021 13:03:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58990) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIa7-000702-F8 for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:31 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:36848) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIa5-0007rk-Nn for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:31 -0400 Received: by mail-wr1-x42b.google.com with SMTP id e11so8224794wrg.3 for ; Mon, 07 Jun 2021 09:58:29 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WP6bAnl0XFv6sI86ENYvVNq1701QvYCzpF74EEud+5Y=; b=PhaTLgSi9W/p1rUl17LGICLkRVA6OEDyFY+ha4IUQMDRY8aX1k41a0O+PafXpU5jgL gOhGDF3wcxFsEn9o5oluvuFBQ3iA78D6dQnKfWMrZoLzsSipUGqm2fpqClCwn9JHeUoP Zj8wCBbtbhpEati67SPRddT9jetpLNfkHbWHbeATMqPz5mDIU0zk0nyz8QpM6ZfmKAS5 rGW6KsalHae7dFjPsSYXnvU+sX3d80WrxUJ82JpI0jIb32ixvw9md+VOXDuZR6B1WZPp J3r5aDoeLQgRq1w1KftFWgs3u+RmvJ7i5RBO5ae4IVfTRHlS9k01pP4MgW38veDdbbcS nFkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WP6bAnl0XFv6sI86ENYvVNq1701QvYCzpF74EEud+5Y=; b=SGgxPZ7APMoXRcXlDqlxbPanRC60RQOWGkSMVX5ohRQSLX4cNBfbWcWr/AMvOkf8/b P7CTU/g/66ADDrXRofBEQWinAiBAk8iadlGCp+8uUJ2n4jMTtZBnoa/w0iJwf1q4HMTa pCgGUrCchzCYDs81vsyQxe5m2TWTBTmpwAU9fdFwAQ43QexW50J/rB7dH5E/W0Ly3nmv 0z2PTqEKtL0lFx2KlLp4oEK2rVGa5SvtysNKzmLL9VLOMwxWzUwuRfcCe+vSUdmgjmLb 78zBWDPtXGmZ+i20iOQNExz4vdafh/uYaMZhpnUYVSCdsqoM5umcsXv7ovN1aZw2q01s dYeg== X-Gm-Message-State: AOAM531CiLz8/3TH4zt36mubnR7szoercdELwBPhWryaXxU+bFRVdeXS Zva0azAEX/CMOLwEUWkl0AFa3Q== X-Google-Smtp-Source: ABdhPJwLfzfmcBGuJ0MwLBV2fydRrylfiXBqiYHzA/A/nyRFz2W3omrTY/A5cYdvZnm84RZtSnN+dw== X-Received: by 2002:a5d:4f12:: with SMTP id c18mr18613626wru.242.1623085108405; Mon, 07 Jun 2021 09:58:28 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 05/55] target/arm: Let vfp_access_check() handle late NOCP checks Date: Mon, 7 Jun 2021 17:57:31 +0100 Message-Id: <20210607165821.9892-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In commit a3494d4671797c we reworked the M-profile handling of its checks for when the NOCP exception should be raised because the FPU is disabled, so that (in line with the architecture) the NOCP check is done early over a large range of the encoding space, and takes precedence over UNDEF exceptions. As part of this, we removed the code from full_vfp_access_check() which raised an exception there for M-profile with the FPU disabled, because it was no longer reachable. For MVE, some instructions which are outside the "coprocessor space" region of the encoding space must nonetheless do "is the FPU enabled" checks and possibly raise a NOCP exception. (In particular this covers the MVE-specific low-overhead branch insns LCTP, DLSTP and WLSTP.) To support these insns, reinstate the code in full_vfp_access_check(), so that their trans functions can call vfp_access_check() and get the correct behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-vfp.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 3a56639e708..6a572591ce9 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -143,11 +143,21 @@ static void gen_preserve_fp_state(DisasContext *s) static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) { if (s->fp_excp_el) { - /* M-profile handled this earlier, in disas_m_nocp() */ - assert (!arm_dc_feature(s, ARM_FEATURE_M)); - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, - syn_fp_access_trap(1, 0xe, false), - s->fp_excp_el); + if (arm_dc_feature(s, ARM_FEATURE_M)) { + /* + * M-profile mostly catches the "FPU disabled" case early, in + * disas_m_nocp(), but a few insns (eg LCTP, WLSTP, DLSTP) + * which do coprocessor-checks are outside the large ranges of + * the encoding space handled by the patterns in m-nocp.decode, + * and for them we may need to raise NOCP here. + */ + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); + } else { + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, + syn_fp_access_trap(1, 0xe, false), + s->fp_excp_el); + } return false; } =20 --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623085944; cv=none; d=zohomail.com; s=zohoarc; b=NuvRcX7RktZqDLThRKdSNDMPbqnxlnNp8pwZGTATwnVT4d5LSHNtT5cst771zhRi17hZVaWBpgfJCMx9+XkWLF6ogtetiUv5S3+6LmkNk+K8wRbQgSHtCk0TAqK0sFkn4ENrX2T86iMKiYpe/KnNwPtIJ9lqb08i09jfr0F3ABs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623085944; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=liF1YOsdelJng9PAu4BBSFSGov6zweQvfaGcLTYKw1Y=; b=BbKBoqzUwCGNILyELTYejpIRvSDbApry9FfiqoE7KrxO2l2ARv5vQg8b0/x4ortNSm66vAe4pMs5FxLxNOtp0327cSNZYvEu1iYNbuVWF5klGjZLMQ8WuGdXhNAvv0QAdcAtSc5RlWtTRNb9jMyOJRBb7Lcy78XxarLuQeknS/8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623085944553762.0752142723187; Mon, 7 Jun 2021 10:12:24 -0700 (PDT) Received: from localhost ([::1]:40450 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqInX-0003XY-QC for importer@patchew.org; Mon, 07 Jun 2021 13:12:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59068) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIaA-00078W-6G for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:34 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:44984) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIa6-0007se-Is for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:33 -0400 Received: by mail-wm1-x32e.google.com with SMTP id p13-20020a05600c358db029019f44afc845so50655wmq.3 for ; Mon, 07 Jun 2021 09:58:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=liF1YOsdelJng9PAu4BBSFSGov6zweQvfaGcLTYKw1Y=; b=rqamJsXfqBLDaGOlJsBlI7/bL/aogn9k9OG2cM2YzPSHHb789uWaYx1MZdpFHbUl10 TsuvPmANNmDi4VpmBhAAkE1D2C04PU7MLca87vRCeXkbfeOlu+dNXtplgJxVaDsdZoBu N8ZdxqyUid9AXQRC82CmmJimOdXPYNlaWYHh77O/Xho8z8KSfzmaH6Y9ZtpJXGuYJdZn HF4uhrxpufBKkkSSjKtUimlu8p+kye7f+BK+spawy86ytf8CjBkaGbNaNV0CBRTbWiWt tXN01ZuwLAZN95RRQeFOR9Giq263xZnzOXyti8HpaiZAaItHihKqXAguQYoCJZ0XaCt4 FLow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=liF1YOsdelJng9PAu4BBSFSGov6zweQvfaGcLTYKw1Y=; b=bMJm1x+h0jAtOH03PUPW+1cTI8c9I93CkPV6M1P0RYr0iP5ys8A+gI1CuCswowHgJG s+Tyx7tbrxQ0RXgP/PaFPjfz0q6zOU1zoqwFvrzd6eVdTFg7MM09yysYJTN5yaev1P8g p9jWvNS+Bh6Vud4vxx8qfaZw5bbV4bkUwJ7EGXq9hhmUKCjoQNzEoy41TXW0oiJvaM5m I84ORkcvJtLDIxgGtU6Pwe0ajSK9zHRpzAxI0TxPWPLaSHYJM2QP3urae+Ndcj8OnFYb sa/twW//KuVLuhTXx00DxK5Y5zgoX+4IZXaevYPPb6bNvHmfk0hf0kFG/lrBzd97OKRy uPgA== X-Gm-Message-State: AOAM532ntrcwMC1vH/gETgb4JBEh2W8Lnh47Xg+6H540ShQxTUonApEZ 1ve35LmI/fme9PhhgKvCNvdE7g== X-Google-Smtp-Source: ABdhPJydk7mjZD3GAuTkX4ZF80gSyutQ/AQ+s2AFDU7R2rTWIlb5pzk1QvW1VKfUtGOUJsn5EZl5Sw== X-Received: by 2002:a05:600c:190c:: with SMTP id j12mr18269843wmq.42.1623085109209; Mon, 07 Jun 2021 09:58:29 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 06/55] target/arm: Implement MVE LCTP Date: Mon, 7 Jun 2021 17:57:32 +0100 Message-Id: <20210607165821.9892-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE LCTP instruction. We put its decode and implementation with the other low-overhead-branch insns because although it is only present if MVE is implemented it is logically in the same group as the other LOB insns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/t32.decode | 2 ++ target/arm/translate.c | 24 ++++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 8b2c487fa7a..087e514e0ac 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -674,5 +674,7 @@ BL 1111 0. .......... 11.1 ............ = @branch24 DLS 1111 0 0000 100 rn:4 1110 0000 0000 0001 WLS 1111 0 0000 100 rn:4 1100 . .......... 1 imm=3D%lob_i= mm LE 1111 0 0000 0 f:1 0 1111 1100 . .......... 1 imm=3D%lob_i= mm + + LCTP 1111 0 0000 000 1111 1110 0000 0000 0001 ] } diff --git a/target/arm/translate.c b/target/arm/translate.c index 1a7a32c1be4..2f6c012f672 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8192,6 +8192,30 @@ static bool trans_LE(DisasContext *s, arg_LE *a) return true; } =20 +static bool trans_LCTP(DisasContext *s, arg_LCTP *a) +{ + /* + * M-profile Loop Clear with Tail Predication. Since our implementation + * doesn't cache branch information, all we need to do is reset + * FPSCR.LTPSIZE to 4. + */ + TCGv_i32 ltpsize; + + if (!dc_isar_feature(aa32_lob, s) || + !dc_isar_feature(aa32_mve, s)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + ltpsize =3D tcg_const_i32(4); + store_cpu_field(ltpsize, v7m.ltpsize); + return true; +} + + static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half) { TCGv_i32 addr, tmp; --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623086129; cv=none; d=zohomail.com; s=zohoarc; b=idVUob6dO9TeiZh2aFEgSyNGNnB7oTretjM1sOcIOkIFZmJxcMHFN+Z/8AHlbJnAinsktwN7LBdyHtUbMkCTdooxwh9co2PX29bf/Phyc0wMCduwmHnmCIJUnjzcsAKMs8/C1WnE8hVFxLEBBkXTTwCogD9lRQDckvLI/UzO1xs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623086129; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qXvH1vi1pgLZA0WzTFhBoxaYbsc0kgsAP29TskDY8yA=; b=iTbI2jSI3jSU6vrXP23yjSLCMOYreTSrxZLLGXEg0FRUBS8xTsYj3l25kYMHQiY36AftBADcI3BJDX/bD3yO33lB6ACjXDK+CZ0WxmTJdCuznr9pg+K1b5xpvcD4vT3loHWuCI+cI541ErlXv+6P3vqAuvFI2z4xA2rS8ObBzrc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623086129234419.90534106413213; Mon, 7 Jun 2021 10:15:29 -0700 (PDT) Received: from localhost ([::1]:51204 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqIqW-0002IA-Cq for importer@patchew.org; Mon, 07 Jun 2021 13:15:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59138) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIaC-0007Hi-GH for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:36 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:36852) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIa7-0007tA-6Q for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:36 -0400 Received: by mail-wr1-x42f.google.com with SMTP id e11so8224865wrg.3 for ; Mon, 07 Jun 2021 09:58:30 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qXvH1vi1pgLZA0WzTFhBoxaYbsc0kgsAP29TskDY8yA=; b=el2Ylv4+ZokDTvENqLinVNrcmlHyNM5+qdpwTk+SlKvOEehpu3N5nsIHJfrAOSIeHt q/VgSuwBe5/7pE8ZtAQ5LhEQh34AftGOHnU1j4OkzMgY08ljafCkT6fsx+hwDT2g5eqk BM4E9UDvqQ4J6XY+mpbJn1Z8qBZaj52FFOMo8rcGlzAsD4Kt3ZHyB5l3V3FCxadGz+AY LstDkr2Bx4bEdoTvUpjTxEEGuO3bTWBm3cTHHYTzmyXBJNs8Wd01QPG9UvadcJk9Yq5f wmFLgrac3yWvkdVTs7G+enMXYnMMVqz70S18qfB7/AergeKnmgyusrxtMjI+hxlB5PP+ 7ehw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qXvH1vi1pgLZA0WzTFhBoxaYbsc0kgsAP29TskDY8yA=; b=NMp/v30FqvZ+lH7keEb1DrEY+Dx/8k3R+ieS9QW/SFgEbQ0s8k0uV8+8UM1rQR31B5 Q/WO3QBfzloAdHaWFXfynYSohT+JTbCIcehXsdAeDnn8g3cp76xy2PZBh3uhHrvh2Bxn XUHcFZEUh+4VYuclEtfdqzLD6XiKbbbQ1XLTCzBch2Mod8XIT8INQIwQE1CIxeKCnLQU DmPu0tP6IY8V1FA1a15jGiC+KaHDW9ItvF2bMZdmUfGgaFxmkMrsRkiz/DRHU8lokFX5 LfHTFZd7JCTEAqP+SnGVP54pLiWN0ZWAbuPPrNRUe3l9UqSiZ4ig/8Mq16kAPp887CYJ m0eg== X-Gm-Message-State: AOAM530P+f31ncW4SgoUM4sIrwCBxUQn0g1jUjU0YzRDjr+hbJb+aqhW k6ybhPHnlFvD09OmHOXkx5wcQg== X-Google-Smtp-Source: ABdhPJziFgT0s9iY2HaaXhtBmc03R5KI5CtaLHErMovBs9b6m2svMXH2TOrj3/SyKBBmTbOO4Qb1hg== X-Received: by 2002:adf:e5c7:: with SMTP id a7mr17870285wrn.117.1623085109965; Mon, 07 Jun 2021 09:58:29 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 07/55] target/arm: Implement MVE WLSTP insn Date: Mon, 7 Jun 2021 17:57:33 +0100 Message-Id: <20210607165821.9892-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE WLSTP insn; this is like the existing WLS insn, except that it specifies a size value which is used to set FPSCR.LTPSIZE. Signed-off-by: Peter Maydell --- target/arm/t32.decode | 8 ++++++-- target/arm/translate.c | 36 +++++++++++++++++++++++++++++++++++- 2 files changed, 41 insertions(+), 3 deletions(-) diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 087e514e0ac..4f0c686a3c3 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -672,8 +672,12 @@ BL 1111 0. .......... 11.1 ............ = @branch24 %lob_imm 1:10 11:1 !function=3Dtimes_2 =20 DLS 1111 0 0000 100 rn:4 1110 0000 0000 0001 - WLS 1111 0 0000 100 rn:4 1100 . .......... 1 imm=3D%lob_i= mm - LE 1111 0 0000 0 f:1 0 1111 1100 . .......... 1 imm=3D%lob_i= mm + WLS 1111 0 0000 100 rn:4 1100 . .......... 1 imm=3D%lob_i= mm size=3D4 + { + # This is WLSTP + WLS 1111 0 0000 0 size:2 rn:4 1100 . .......... 1 imm=3D%lob_= imm + LE 1111 0 0000 0 f:1 0 1111 1100 . .......... 1 imm=3D%lob_i= mm + } =20 LCTP 1111 0 0000 000 1111 1110 0000 0000 0001 ] diff --git a/target/arm/translate.c b/target/arm/translate.c index 2f6c012f672..79ec185dd83 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8135,7 +8135,11 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a) return false; } if (a->rn =3D=3D 13 || a->rn =3D=3D 15) { - /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */ + /* + * For WLSTP rn =3D=3D 15 is a related encoding (LE); the + * other cases caught by this condition are all + * CONSTRAINED UNPREDICTABLE: we choose to UNDEF + */ return false; } if (s->condexec_mask) { @@ -8148,10 +8152,40 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a) */ return false; } + if (a->size !=3D 4) { + /* WLSTP */ + if (!dc_isar_feature(aa32_mve, s)) { + return false; + } + /* + * We need to check that the FPU is enabled here, but mustn't + * call vfp_access_check() to do that because we don't want to + * do the lazy state preservation in the "loop count is zero" case. + * Do the check-and-raise-exception by hand. + */ + if (s->fp_excp_el) { + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), s->fp_excp_el); + } + } + nextlabel =3D gen_new_label(); tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_R[a->rn], 0, nextlabel); tmp =3D load_reg(s, a->rn); store_reg(s, 14, tmp); + if (a->size !=3D 4) { + /* + * WLSTP: set FPSCR.LTPSIZE. This requires that we do the + * lazy state preservation, new FP context creation, etc, + * that vfp_access_check() does. We know that the actual + * access check will succeed (ie it won't generate code that + * throws an exception) because we did that check by hand earlier. + */ + bool ok =3D vfp_access_check(s); + assert(ok); + tmp =3D tcg_const_i32(a->size); + store_cpu_field(tmp, v7m.ltpsize); + } gen_jmp_tb(s, s->base.pc_next, 1); =20 gen_set_label(nextlabel); --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623085441; cv=none; d=zohomail.com; s=zohoarc; b=g7Wo1DvZTRPauFUr9NqXqrLUMhpGaNhtPVKniOukWGOMvg50gQ6ZIMq9McfNmSFoKod+7yr+GZ/QtkDoNOHF9qQs3W/HDGUm+F3R3jemTFWBf+tFj8kzQvGCKD+pa0Ic2DCadAOPwcdWqNp2kGccOwUEnaETE7g5McfZQTg9Ll4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623085441; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=67M3g+mTaDGBPPPiAyLgANuoYcm+1J1sPesRc7OWVmw=; b=Cn91Qes6cCJqz15eBZxWY3L2nqK4UhKQxhQtLCXq/gUHiStDzDHYQ461B9gcUQX9uNK1w+AeyikCIytkQ+gzltmY+ul2i9ks7SRJe08VRm9N+aBYZF8dLIpJLv1JaBEFEf9P+Lq3tjDCVjLUKG99W0ZJmfT5vFaraRsEII91weM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623085441242456.6533444440862; Mon, 7 Jun 2021 10:04:01 -0700 (PDT) Received: from localhost ([::1]:45276 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqIfP-0004S8-VN for importer@patchew.org; Mon, 07 Jun 2021 13:03:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59124) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIaC-0007GK-5y for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:36 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:43639) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIa7-0007tU-Ri for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:35 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 3-20020a05600c0243b029019f2f9b2b8aso53747wmj.2 for ; Mon, 07 Jun 2021 09:58:31 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=67M3g+mTaDGBPPPiAyLgANuoYcm+1J1sPesRc7OWVmw=; b=aZVveoi0p073kvWK8ecixYWnttRPFU746VWzUUNoKEbi4zkz1XDXoSwVlwE533SjoX AWZgiy7jantPu1znHj1P3KkTNvse5mrViZpGiPiVo3Zdi5y+kMsrjD856pYCGbxBGqc8 EEaAkAimlSWAsLevhT4h/8iNmcnmkMSKyLI6hFjEW4+GAm8PHPBOw9dKuol5XvzkbGuM 5m7XxckIGXUeAW9ZZ3NgUd3WZfUFOPLeTbsQn5CP+/YZ++6UYnXZVhBgSAqg2UGaVTKE qPskvzW+/dHhsvw/WQynK5OXjDTHBeCE00N/gqvwsZaKY8RCOGlDQyoadvkuQAxf3X7Q 1Lmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=67M3g+mTaDGBPPPiAyLgANuoYcm+1J1sPesRc7OWVmw=; b=rYDTBjlYclv0kz/bN7JdjGmfElNDnwj8QJd/iEiGYQT/Buk9r+5oJbyiTtnJ7h5AxU 16WDc9mGcU08e8pU97OfBp5wItYIuCJBYgHAPisSiiR9F/WNOCx5dNLcQb+frR5m4kzT NpuTzQMIeeg1YlcZ6OaMk6f5jRCjXWIhhaF68y2dCsKoVrmL4V8ybW7GgHV+NHQUKUlM CeqcDlM8SJc+HUuRI75k1SgZ1z0vfjmjLxKXahkGiiI1k3ckysE/qaDwCd2xKjY2o6Mo u/nerpLvs4QTmO1UNIcucoF83N7PFLnu/QaIkfHzbpaQT0UxqWaQYA+E/s1rRwH+RPpP gCfQ== X-Gm-Message-State: AOAM530hzxoe1xIXeFH69FZNwXrpSZRqA7fVhwDJYrinREZ5r2zq2MFx saDRTH5ePPcGoO1EJRBgCMyK8x17xnZCju73 X-Google-Smtp-Source: ABdhPJznXsXBwR2pXrRL8n6PLlqcRcaiCY4/eIgwuqB8F3NvX/Bxy/aprFYELptSxCH3e2MlHp1ovg== X-Received: by 2002:a05:600c:1ca2:: with SMTP id k34mr9727601wms.145.1623085110664; Mon, 07 Jun 2021 09:58:30 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/55] target/arm: Implement MVE DLSTP Date: Mon, 7 Jun 2021 17:57:34 +0100 Message-Id: <20210607165821.9892-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE DLSTP insn; this is like the existing DLS insn, except that it must do an FPU access check and it sets LTPSIZE to the value specified in the insn. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/t32.decode | 9 ++++++--- target/arm/translate.c | 23 +++++++++++++++++++++-- 2 files changed, 27 insertions(+), 5 deletions(-) diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 4f0c686a3c3..8e1ca7d64a9 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -671,14 +671,17 @@ BL 1111 0. .......... 11.1 ............= @branch24 # LE and WLS immediate %lob_imm 1:10 11:1 !function=3Dtimes_2 =20 - DLS 1111 0 0000 100 rn:4 1110 0000 0000 0001 + DLS 1111 0 0000 100 rn:4 1110 0000 0000 0001 size=3D4 WLS 1111 0 0000 100 rn:4 1100 . .......... 1 imm=3D%lob_i= mm size=3D4 { # This is WLSTP WLS 1111 0 0000 0 size:2 rn:4 1100 . .......... 1 imm=3D%lob_= imm LE 1111 0 0000 0 f:1 0 1111 1100 . .......... 1 imm=3D%lob_i= mm } - - LCTP 1111 0 0000 000 1111 1110 0000 0000 0001 + { + # This is DLSTP + DLS 1111 0 0000 0 size:2 rn:4 1110 0000 0000 0001 + LCTP 1111 0 0000 000 1111 1110 0000 0000 0001 + } ] } diff --git a/target/arm/translate.c b/target/arm/translate.c index 79ec185dd83..976c665be9c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8115,13 +8115,32 @@ static bool trans_DLS(DisasContext *s, arg_DLS *a) return false; } if (a->rn =3D=3D 13 || a->rn =3D=3D 15) { - /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */ + /* + * For DLSTP rn =3D=3D 15 is a related encoding (LCTP); the + * other cases caught by this condition are all + * CONSTRAINED UNPREDICTABLE: we choose to UNDEF + */ return false; } =20 - /* Not a while loop, no tail predication: just set LR to the count */ + if (a->size !=3D 4) { + /* DLSTP */ + if (!dc_isar_feature(aa32_mve, s)) { + return false; + } + if (!vfp_access_check(s)) { + return true; + } + } + + /* Not a while loop: set LR to the count, and set LTPSIZE for DLSTP */ tmp =3D load_reg(s, a->rn); store_reg(s, 14, tmp); + if (a->size !=3D 4) { + /* DLSTP: set FPSCR.LTPSIZE */ + tmp =3D tcg_const_i32(a->size); + store_cpu_field(tmp, v7m.ltpsize); + } return true; } =20 --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623086273; cv=none; d=zohomail.com; s=zohoarc; b=lS/FyXoZjEeDMiAIi/07XxAjqY/dydKxhnzeW8vC1YerZjTKOy8u1DF7+tOLMeCgaYhiw447qKcFMd6jRC8pbo7Rskj56bcapSyAa1fVyUZGnU9ShzzfZWerQEyVFUrutJGLuHIiYm5hLb6hk4Q8Ln1+sx8qA41jVHxE3s2MAgQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623086273; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LKqmv0MgdApn4ZHvXGc8SemnH+SSJM42zZ7JcZtsFWE=; b=b3beV964G2DDZA3oMihCUnvtm9w4UQbMqzY25EnDdkiqTRzsOPavRrz/zwdDWaG9ZL83RaF6pJIfDmV2fISItG4RX0ppkIoHBSd0gm3xHIAriSC8cL+ixr5lDYP+npSv4CNYHYc34JKd+I8yfJZfrJSBWfN2we+iUb1Vs9T3iW0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623086273117759.2413518333776; Mon, 7 Jun 2021 10:17:53 -0700 (PDT) Received: from localhost ([::1]:59928 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqIsp-0008Ae-HT for importer@patchew.org; Mon, 07 Jun 2021 13:17:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59166) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIaD-0007LO-Gj for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:37 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:38789) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIa8-0007tv-OK for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:37 -0400 Received: by mail-wm1-x32e.google.com with SMTP id t4-20020a1c77040000b029019d22d84ebdso106071wmi.3 for ; Mon, 07 Jun 2021 09:58:32 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LKqmv0MgdApn4ZHvXGc8SemnH+SSJM42zZ7JcZtsFWE=; b=wyI18BeCVmi4d8sDs/M8rseTGlKY94y+I3Rs2pH3w5XuEiCx/U5PCxz02Q2qpWqhBE iOnei8ZsNB0RFuu3Vvq1dkPvgbhb7zAbet5PEXr0vERNpqI1KhaoQ/nxBjIhQxIZ0YZI Nbr6lGfCC6GAc9EARBKeqgNcgzJc3udY1KAQhzacbfai+rtObcxTgrBxBvDPdzWVlmO6 wnfucW4Nh6CBgwkoxppoTVB2ZyqiiDbYBPjhmgdVbS+O3KLfcwK9zh39HEHKqmw8k1V/ eOUlxQBup1No6MTFHB4N6hTWrIp/JO541cPe9UussKXF/3EVg6ICc6Iu63xog7R43uDZ cQnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LKqmv0MgdApn4ZHvXGc8SemnH+SSJM42zZ7JcZtsFWE=; b=fp3O4ZaHpGQ8VNX4kuR4DD2lJ4La0YaqukFmq4PHW8oP4faRKfrVbpi1t+8McjKOsY lOFvFu3lALDYzsZPkdi46PiBN+rLmIfNjqWB/GgoIMdmk2sVUr0ZRYTO0zFd1dMv7wQR oI3/TorhPy7Nx9pqBhHgAG4hO6FdcpqnVAjmHTUrJZsqd5KnRFYW4F45fbS3NHKrPYZb p1OdiTq84nFGuzBNMz/aZM6KfwmwhXqZHl89A590J6sI3eQIZwLbf9DkpQRy04upXFF6 63qQIXvMmUSUJSxjsvq2og40Li30HXZ5Hq56GYeU/dgBsBK5DciunZPLSf4Ysu9Wqn2/ xhcg== X-Gm-Message-State: AOAM530ZFIoEJ6rrGzlX15gT4fJIKq18C0hHxJmdwge4kpqqZA2Ae+2E oY3x9XMQoaNqQMVfiYSiGF5NXA== X-Google-Smtp-Source: ABdhPJzOUq/4QMOobgENZOwdZ5b6Rg4W7Ul8Vlbwzz36YWNjMfFga+f9Luf/JYMEjRJCcSMKYdOsww== X-Received: by 2002:a1c:e907:: with SMTP id q7mr70588wmc.1.1623085111449; Mon, 07 Jun 2021 09:58:31 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 09/55] target/arm: Implement MVE LETP insn Date: Mon, 7 Jun 2021 17:57:35 +0100 Message-Id: <20210607165821.9892-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE LETP insn. This is like the existing LE loop-end insn, but it must perform an FPU-enabled check, and on loop-exit it resets LTPSIZE to 4. To accommodate the requirement to do something on loop-exit, we drop the use of condlabel and instead manage both the TB exits manually, in the same way we already do in trans_WLS(). The other MVE-specific change to the LE insn is that we must raise an INVSTATE UsageFault insn if LTPSIZE is not 4. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- This amounts to a complete rewrite of trans_LE()... --- target/arm/t32.decode | 2 +- target/arm/translate.c | 104 +++++++++++++++++++++++++++++++++++++---- 2 files changed, 97 insertions(+), 9 deletions(-) diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 8e1ca7d64a9..4115e08ce99 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -676,7 +676,7 @@ BL 1111 0. .......... 11.1 ............ = @branch24 { # This is WLSTP WLS 1111 0 0000 0 size:2 rn:4 1100 . .......... 1 imm=3D%lob_= imm - LE 1111 0 0000 0 f:1 0 1111 1100 . .......... 1 imm=3D%lob_i= mm + LE 1111 0 0000 0 f:1 tp:1 1111 1100 . .......... 1 imm=3D%lo= b_imm } { # This is DLSTP diff --git a/target/arm/translate.c b/target/arm/translate.c index 976c665be9c..6d70c89961a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8223,25 +8223,113 @@ static bool trans_LE(DisasContext *s, arg_LE *a) * any faster. */ TCGv_i32 tmp; + TCGLabel *loopend; + bool fpu_active; =20 if (!dc_isar_feature(aa32_lob, s)) { return false; } + if (a->f && a->tp) { + return false; + } + if (s->condexec_mask) { + /* + * LE in an IT block is CONSTRAINED UNPREDICTABLE; + * we choose to UNDEF, because otherwise our use of + * gen_goto_tb(1) would clash with the use of TB exit 1 + * in the dc->condjmp condition-failed codepath in + * arm_tr_tb_stop() and we'd get an assertion. + */ + return false; + } + if (a->tp) { + /* LETP */ + if (!dc_isar_feature(aa32_mve, s)) { + return false; + } + if (!vfp_access_check(s)) { + s->eci_handled =3D true; + return true; + } + } =20 /* LE/LETP is OK with ECI set and leaves it untouched */ s->eci_handled =3D true; =20 - if (!a->f) { - /* Not loop-forever. If LR <=3D 1 this is the last loop: do nothin= g. */ - arm_gen_condlabel(s); - tcg_gen_brcondi_i32(TCG_COND_LEU, cpu_R[14], 1, s->condlabel); - /* Decrement LR */ - tmp =3D load_reg(s, 14); - tcg_gen_addi_i32(tmp, tmp, -1); - store_reg(s, 14, tmp); + /* + * With MVE, LTPSIZE might not be 4, and we must emit an INVSTATE + * UsageFault exception for the LE insn in that case. Note that we + * are not directly checking FPSCR.LTPSIZE but instead check the + * pseudocode LTPSIZE() function, which returns 4 if the FPU is + * not currently active (ie ActiveFPState() returns false). We + * can identify not-active purely from our TB state flags, as the + * FPU is active only if: + * the FPU is enabled + * AND lazy state preservation is not active + * AND we do not need a new fp context (this is the ASPEN/FPCA check) + * + * Usually we don't need to care about this distinction between + * LTPSIZE and FPSCR.LTPSIZE, because the code in vfp_access_check() + * will either take an exception or clear the conditions that make + * the FPU not active. But LE is an unusual case of a non-FP insn + * that looks at LTPSIZE. + */ + fpu_active =3D !s->fp_excp_el && !s->v7m_lspact && !s->v7m_new_fp_ctxt= _needed; + + if (!a->tp && dc_isar_feature(aa32_mve, s) && fpu_active) { + /* Need to do a runtime check for LTPSIZE !=3D 4 */ + TCGLabel *skipexc =3D gen_new_label(); + tmp =3D load_cpu_field(v7m.ltpsize); + tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc); + tcg_temp_free_i32(tmp); + gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized= (), + default_exception_el(s)); + gen_set_label(skipexc); + } + + if (a->f) { + /* Loop-forever: just jump back to the loop start */ + gen_jmp(s, read_pc(s) - a->imm); + return true; + } + + /* + * Not loop-forever. If LR <=3D loop-decrement-value this is the last = loop. + * For LE, we know at this point that LTPSIZE must be 4 and the + * loop decrement value is 1. For LETP we need to calculate the decrem= ent + * value from LTPSIZE. + */ + loopend =3D gen_new_label(); + if (!a->tp) { + tcg_gen_brcondi_i32(TCG_COND_LEU, cpu_R[14], 1, loopend); + tcg_gen_addi_i32(cpu_R[14], cpu_R[14], -1); + } else { + /* + * Decrement by 1 << (4 - LTPSIZE). We need to use a TCG local + * so that decr stays live after the brcondi. + */ + TCGv_i32 decr =3D tcg_temp_local_new_i32(); + TCGv_i32 ltpsize =3D load_cpu_field(v7m.ltpsize); + tcg_gen_sub_i32(decr, tcg_constant_i32(4), ltpsize); + tcg_gen_shl_i32(decr, tcg_constant_i32(1), decr); + tcg_temp_free_i32(ltpsize); + + tcg_gen_brcond_i32(TCG_COND_LEU, cpu_R[14], decr, loopend); + + tcg_gen_sub_i32(cpu_R[14], cpu_R[14], decr); + tcg_temp_free_i32(decr); } /* Jump back to the loop start */ gen_jmp(s, read_pc(s) - a->imm); + + gen_set_label(loopend); + if (a->tp) { + /* Exits from tail-pred loops must reset LTPSIZE to 4 */ + tmp =3D tcg_const_i32(4); + store_cpu_field(tmp, v7m.ltpsize); + } + /* End TB, continuing to following insn */ + gen_jmp_tb(s, s->base.pc_next, 1); return true; } =20 --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623085646; cv=none; d=zohomail.com; s=zohoarc; b=fr0oVBqFDfdiUxEYnqxi/mn9aLrMsFgD1tMxUrMGsFemF6IGoSBGhRfXJFyGraHMeZWOw7ZOS0piOyof5dvPL1onDtgl93C/6xD/LO/O2XV52R+o/5oQcT4padx9zgij7PSDKYL6pnAm8OR3zhYVbXQvONRrLs95gNko+qcWJdQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623085646; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iY76aJwB+mbu7BatyWo5ZgTCehVn9Ly4x7fuNCDZ8aY=; b=AT1oijAuSHNlSkAUIIOPtj+bdG0CD61tpvZD9m+z0Yt40Sp+kPcGmizIZ9d/UlPM0A12Cr4UZpniuotNi0S+9UvW42LDuTM4Dr0MjbprkYGzUUsTe/sFgbiq7LgxZv/6Cs+HSgo9jiWCLZAyMtwXPU0a5pRWergCkUEauHWADMo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623085646400257.47672694643813; Mon, 7 Jun 2021 10:07:26 -0700 (PDT) Received: from localhost ([::1]:51692 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqIhl-0000SX-Qc for importer@patchew.org; Mon, 07 Jun 2021 13:06:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59186) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIaE-0007NO-2Y for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:38 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:43689) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIa9-0007u8-Gb for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:37 -0400 Received: by mail-wr1-x42c.google.com with SMTP id r9so1729922wrz.10 for ; Mon, 07 Jun 2021 09:58:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iY76aJwB+mbu7BatyWo5ZgTCehVn9Ly4x7fuNCDZ8aY=; b=mmSf0YpJOSVmFPcnPudPRbUA92RsY8I4CXrmsiaPOBipmqa4Mvi2ZATM7TItBzDTCx 1OaokDzvR5jHk9BCCjq8iEjTEWy31qNbrxHCuokh0liRSYHv5J2Fat5wislQLhvU3882 OcD4cmXuinV29E40Y0Yhduc4EfMCoW4OfSzYQMyBvBT4czDMgoxBNmA4TP58R9Z3+kij t188MRrT1xko9YthKzzO27yJtPiXxd7NmlsDUHs62zg9OgbvsSO6I8Ayztye5W4kUxBi bT0OF2Dz90hzidC4SO8ALJbfLhXPTxLMq4Cs+T3WdWzX4YVXo6ZaCQYNgX2k9TOHHx3p Rveg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iY76aJwB+mbu7BatyWo5ZgTCehVn9Ly4x7fuNCDZ8aY=; b=tbE/UclZiS8Y/mP0GUsVqkQZCQzDRn7EAAdlEoo6PcHy5sJfW5TcWCfaKlDNI5cUOo 2lrtUqoBKvPREsr0Lc5d8YJ1wfn1x9ZwcRWXXD4fj2yu3i+nc7XQpQTPS6S/qiRaCjjU j3RQT1U/fDyOyXcVRoj6sQQvQySUw3Znyk40nwoSNAdU1mLIVO9y6NWaDratyp7VmMa3 2xkIBejKVzJ52JjyEz9cTR3RAJKOlaJI8MZ5UWTFBEho4lcKswyMJ+LnRty+bVbr8XQf jdI2KVr7N8NxCLgJUoZXOJaoZK5k1EdFmOF1c3qmmTf4TGOIwQvaMOxG6b4du47cKNAR K1Og== X-Gm-Message-State: AOAM531cHCqkHjzSv0MMq4j8IuPoz98C7JCZMNdkLOELwRDV5x1Mz1Dg vtyvGGJZqS8Mog2RYjoxPbpENg== X-Google-Smtp-Source: ABdhPJwG8fXrCERhT5HUPv3LScMjhy7Ps2mgw+ITOclLkL5kpKd/tZvhgKXpQ2M0WW6y2G1kUYyvrA== X-Received: by 2002:a05:6000:1849:: with SMTP id c9mr18484206wri.140.1623085112233; Mon, 07 Jun 2021 09:58:32 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 10/55] target/arm: Add framework for MVE decode Date: Mon, 7 Jun 2021 17:57:36 +0100 Message-Id: <20210607165821.9892-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Add the framework for decoding MVE insns, with the necessary new files and the meson.build rules, but no actual content yet. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-a32.h | 1 + target/arm/mve.decode | 20 ++++++++++++++++++++ target/arm/translate-mve.c | 29 +++++++++++++++++++++++++++++ target/arm/translate.c | 1 + target/arm/meson.build | 2 ++ 5 files changed, 53 insertions(+) create mode 100644 target/arm/mve.decode create mode 100644 target/arm/translate-mve.c diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index c946ac440ce..0a0053949f5 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -22,6 +22,7 @@ =20 /* Prototypes for autogenerated disassembler functions */ bool disas_m_nocp(DisasContext *dc, uint32_t insn); +bool disas_mve(DisasContext *dc, uint32_t insn); bool disas_vfp(DisasContext *s, uint32_t insn); bool disas_vfp_uncond(DisasContext *s, uint32_t insn); bool disas_neon_dp(DisasContext *s, uint32_t insn); diff --git a/target/arm/mve.decode b/target/arm/mve.decode new file mode 100644 index 00000000000..c8492bb5763 --- /dev/null +++ b/target/arm/mve.decode @@ -0,0 +1,20 @@ +# M-profile MVE instruction descriptions +# +# Copyright (c) 2021 Linaro, Ltd +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2.1 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . + +# +# This file is processed by scripts/decodetree.py +# diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c new file mode 100644 index 00000000000..c54d5cb7305 --- /dev/null +++ b/target/arm/translate-mve.c @@ -0,0 +1,29 @@ +/* + * ARM translation: M-profile MVE instructions + + * Copyright (c) 2021 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" +#include "exec/exec-all.h" +#include "exec/gen-icount.h" +#include "translate.h" +#include "translate-a32.h" + +/* Include the generated decoder */ +#include "decode-mve.c.inc" diff --git a/target/arm/translate.c b/target/arm/translate.c index 6d70c89961a..ee17125465b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8919,6 +8919,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32= _t insn) if (disas_t32(s, insn) || disas_vfp_uncond(s, insn) || disas_neon_shared(s, insn) || + disas_mve(s, insn) || ((insn >> 28) =3D=3D 0xe && disas_vfp(s, insn))) { return; } diff --git a/target/arm/meson.build b/target/arm/meson.build index 5bfaf43b500..2b50be3f862 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -6,6 +6,7 @@ gen =3D [ decodetree.process('vfp.decode', extra_args: '--decode=3Ddisas_vfp'), decodetree.process('vfp-uncond.decode', extra_args: '--decode=3Ddisas_vf= p_uncond'), decodetree.process('m-nocp.decode', extra_args: '--decode=3Ddisas_m_nocp= '), + decodetree.process('mve.decode', extra_args: '--decode=3Ddisas_mve'), decodetree.process('a32.decode', extra_args: '--static-decode=3Ddisas_a3= 2'), decodetree.process('a32-uncond.decode', extra_args: '--static-decode=3Dd= isas_a32_uncond'), decodetree.process('t32.decode', extra_args: '--static-decode=3Ddisas_t3= 2'), @@ -27,6 +28,7 @@ arm_ss.add(files( 'tlb_helper.c', 'translate.c', 'translate-m-nocp.c', + 'translate-mve.c', 'translate-neon.c', 'translate-vfp.c', 'vec_helper.c', --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623085813; cv=none; d=zohomail.com; s=zohoarc; b=l7IXUHp5WEwdogTHRuBX3daYH63c6019cNJYeVBaIIvh42WDS2H/Q2YQh8qnXblhWPeDLAEtYzcjKIk2mJLIJB8DHJZ4XetVgXuPZNGOy3gAo7fGmrAot65sbQm6ovlKdbF6joq7aOdTHxFQyvlE0RC63efbSrRhNsUm6BgSYzA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623085813; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=B/ouubpcq2OKp6jcrkf6PegX0zSxS4BaQ07JU1gDbks=; b=TfbpLHAPGGGpGv4Zy7eplc+oAsAIY7dFPlSWaPOLVERo3cJ4rdmUTuO97G02IGgq1pu1gkNRLVG20xdfs0fF76JN/Cepw5xHvclieWMXJE3IuXEFBVa8NgNRZ8Xgulr+j5r0bsf013FYEDwJTK2LmpcSdMaQQ1yv5dRtWt5/beg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623085813640254.38361736311765; Mon, 7 Jun 2021 10:10:13 -0700 (PDT) Received: from localhost ([::1]:34850 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqIlQ-0008Aa-ST for importer@patchew.org; Mon, 07 Jun 2021 13:10:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59354) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIaS-0007Ua-4H for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:54 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:41800) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIaA-0007uc-N0 for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:48 -0400 Received: by mail-wr1-x436.google.com with SMTP id o3so38696wri.8 for ; Mon, 07 Jun 2021 09:58:34 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B/ouubpcq2OKp6jcrkf6PegX0zSxS4BaQ07JU1gDbks=; b=K50uImrFhNC8jNJtQkQfKKNRfyC39VUKzlUix8tteXHc37NOX9s0HLCit2ziL5RDkc +9Xpy5tXFu3aaT5g2rF8nffz8ICDA7PRrPCMO5lGdR58ygsvC0NIKDphfV4HW2AN8MJJ 61A0mBH8WUo9kOewVjSmNmaz1lkh4cJD+F1s+pTNwzB0eHF/wQ58j4mKrmS2FqVtj4Bh YleMPBmmUENvF2q9MqOPbRKuMCsJWg+9yEHRqya+npQe+AVr8Gu2M8Gr72GJc64ykGtH SKn9wc2CyS9+H+MYMC+FsUDCPtvzU7cG+7OMV5rqyYBiQUPYJTFu83+/N/SlilV0XNme +vIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B/ouubpcq2OKp6jcrkf6PegX0zSxS4BaQ07JU1gDbks=; b=eQQNwHSOJEPHT2oPctxEOedtz0x437/Zb+CGoz6EGifxZQz3o1Am4JpWfu4KQ8k7hp YQeWeh0rncqj1KpSWLMJVeAkWLDN3fDS6E6zYHR5a6EzwkPvZ5yLwG1kZhpZGMTZUmpi WPMuDCsQSaX3wD8XTyzuy35TaRCUL/WGjeEwLj3UYNDwrCCD4SYk3Mv3ccJT00wuvxAH jWlNQNWIxVuX7pJJhtzwVRJDvxhmvcEMWS3K4e24YTdi1qSTB3fkeEXy7WWzIKZfo+UL RCW2QPyNwGj9nmgdePg7UMI+hezMCUjbywRpz3lbIdqHnMzJd5zBifyjC1OnJkSkbCcK WSWg== X-Gm-Message-State: AOAM530kcdXYKktbkmJbeaqR7uqwCaAMEMtI5RAhq4kKjprkCjZCg90y 3oHcOwFhiO2M5JXv3/CccTm0RA== X-Google-Smtp-Source: ABdhPJzewPct13W0rUU972oRbST1avchhyGT0P5ayTbS76n5u2quZ6rh3xpDdkNno1qK/OHQ50m8fg== X-Received: by 2002:adf:8bc7:: with SMTP id w7mr18995192wra.198.1623085113248; Mon, 07 Jun 2021 09:58:33 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 11/55] target/arm: Implement MVE VLDR/VSTR (non-widening forms) Date: Mon, 7 Jun 2021 17:57:37 +0100 Message-Id: <20210607165821.9892-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the forms of the MVE VLDR and VSTR insns which perform non-widening loads of bytes, halfwords or words from memory into vector elements of the same width (encodings T5, T6, T7). (At the moment we know for MVE and M-profile in general that vfp_access_check() can never return false, but we include the conventional return-true-on-failure check for consistency with non-M-profile translation code.) Signed-off-by: Peter Maydell --- target/arm/{translate-mve.c =3D> helper-mve.h} | 21 +-- target/arm/helper.h | 2 + target/arm/internals.h | 11 ++ target/arm/mve.decode | 22 +++ target/arm/mve_helper.c | 188 +++++++++++++++++++ target/arm/translate-mve.c | 124 +++++++++++- target/arm/meson.build | 1 + 7 files changed, 355 insertions(+), 14 deletions(-) copy target/arm/{translate-mve.c =3D> helper-mve.h} (61%) create mode 100644 target/arm/mve_helper.c diff --git a/target/arm/translate-mve.c b/target/arm/helper-mve.h similarity index 61% copy from target/arm/translate-mve.c copy to target/arm/helper-mve.h index c54d5cb7305..9e3b0b09afd 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/helper-mve.h @@ -1,6 +1,6 @@ /* - * ARM translation: M-profile MVE instructions - + * M-profile MVE specific helper definitions + * * Copyright (c) 2021 Linaro, Ltd. * * This library is free software; you can redistribute it and/or @@ -16,14 +16,9 @@ * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see . */ - -#include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "exec/exec-all.h" -#include "exec/gen-icount.h" -#include "translate.h" -#include "translate-a32.h" - -/* Include the generated decoder */ -#include "decode-mve.c.inc" +DEF_HELPER_FLAGS_3(mve_vldrb, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vldrh, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vldrw, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vstrb, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vstrh, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vstrw, TCG_CALL_NO_WG, void, env, ptr, i32) diff --git a/target/arm/helper.h b/target/arm/helper.h index dc6eb96d439..db87d7d5376 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1019,3 +1019,5 @@ DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG, #include "helper-a64.h" #include "helper-sve.h" #endif + +#include "helper-mve.h" diff --git a/target/arm/internals.h b/target/arm/internals.h index 886db56b580..3ba86e8af81 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1202,4 +1202,15 @@ static inline uint64_t useronly_maybe_clean_ptr(uint= 32_t desc, uint64_t ptr) return ptr; } =20 +/* Values for M-profile PSR.ECI for MVE insns */ +enum MVEECIState { + ECI_NONE =3D 0, /* No completed beats */ + ECI_A0 =3D 1, /* Completed: A0 */ + ECI_A0A1 =3D 2, /* Completed: A0, A1 */ + /* 3 is reserved */ + ECI_A0A1A2 =3D 4, /* Completed: A0, A1, A2 */ + ECI_A0A1A2B0 =3D 5, /* Completed: A0, A1, A2, B0 */ + /* All other values reserved */ +}; + #endif diff --git a/target/arm/mve.decode b/target/arm/mve.decode index c8492bb5763..858a161fd7e 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -18,3 +18,25 @@ # # This file is processed by scripts/decodetree.py # + +%qd 22:1 13:3 + +&vldr_vstr rn qd imm p a w size l + +@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=3D%qd + +# Vector loads and stores + +# Non-widening loads/stores (P=3D0 W=3D0 is 'related encoding') +VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111100 ....... @vldr_vst= r \ + size=3D0 p=3D0 w=3D1 +VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111101 ....... @vldr_vst= r \ + size=3D1 p=3D0 w=3D1 +VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111110 ....... @vldr_vst= r \ + size=3D2 p=3D0 w=3D1 +VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111100 ....... @vldr_vst= r \ + size=3D0 p=3D1 +VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111101 ....... @vldr_vst= r \ + size=3D1 p=3D1 +VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vst= r \ + size=3D2 p=3D1 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c new file mode 100644 index 00000000000..575afce8fee --- /dev/null +++ b/target/arm/mve_helper.c @@ -0,0 +1,188 @@ +/* + * M-profile MVE Operations + * + * Copyright (c) 2021 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/helper-proto.h" +#include "exec/cpu_ldst.h" +#include "exec/exec-all.h" + +/* + * Note that vector data is stored in host-endian 64-bit chunks, + * so addressing units smaller than that needs a host-endian fixup. + */ +#ifdef HOST_WORDS_BIGENDIAN +#define H1(x) ((x) ^ 7) +#define H2(x) ((x) ^ 3) +#define H4(x) ((x) ^ 1) +#else +#define H1(x) (x) +#define H2(x) (x) +#define H4(x) (x) +#endif + +static uint16_t mve_element_mask(CPUARMState *env) +{ + /* + * Return the mask of which elements in the MVE vector should be + * updated. This is a combination of multiple things: + * (1) by default, we update every lane in the vector + * (2) VPT predication stores its state in the VPR register; + * (3) low-overhead-branch tail predication will mask out part + * the vector on the final iteration of the loop + * (4) if EPSR.ECI is set then we must execute only some beats + * of the insn + * We combine all these into a 16-bit result with the same semantics + * as VPR.P0: 0 to mask the lane, 1 if it is active. + * 8-bit vector ops will look at all bits of the result; + * 16-bit ops will look at bits 0, 2, 4, ...; + * 32-bit ops will look at bits 0, 4, 8 and 12. + * Compare pseudocode GetCurInstrBeat(), though that only returns + * the 4-bit slice of the mask corresponding to a single beat. + */ + uint16_t mask =3D extract32(env->v7m.vpr, R_V7M_VPR_P0_SHIFT, + R_V7M_VPR_P0_LENGTH); + + if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) { + mask |=3D 0xff; + } + if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) { + mask |=3D 0xff00; + } + + if (env->v7m.ltpsize < 4 && + env->regs[14] <=3D (1 << (4 - env->v7m.ltpsize))) { + /* + * Tail predication active, and this is the last loop iteration. + * The element size is (1 << ltpsize), and we only want to process + * loopcount elements, so we want to retain the least significant + * (loopcount * esize) predicate bits and zero out bits above that. + */ + int masklen =3D env->regs[14] << env->v7m.ltpsize; + assert(masklen <=3D 16); + mask &=3D MAKE_64BIT_MASK(0, masklen); + } + + if ((env->condexec_bits & 0xf) =3D=3D 0) { + /* + * ECI bits indicate which beats are already executed; + * we handle this by effectively predicating them out. + */ + int eci =3D env->condexec_bits >> 4; + switch (eci) { + case ECI_NONE: + break; + case ECI_A0: + mask &=3D 0xfff0; + break; + case ECI_A0A1: + mask &=3D 0xff00; + break; + case ECI_A0A1A2: + case ECI_A0A1A2B0: + mask &=3D 0xf000; + break; + default: + g_assert_not_reached(); + } + } + + return mask; +} + +static void mve_advance_vpt(CPUARMState *env) +{ + /* Advance the VPT and ECI state if necessary */ + uint32_t vpr =3D env->v7m.vpr; + unsigned mask01, mask23; + + if ((env->condexec_bits & 0xf) =3D=3D 0) { + env->condexec_bits =3D (env->condexec_bits =3D=3D (ECI_A0A1A2B0 <<= 4)) ? + (ECI_A0 << 4) : (ECI_NONE << 4); + } + + if (!(vpr & (R_V7M_VPR_MASK01_MASK | R_V7M_VPR_MASK23_MASK))) { + /* VPT not enabled, nothing to do */ + return; + } + + mask01 =3D extract32(vpr, R_V7M_VPR_MASK01_SHIFT, R_V7M_VPR_MASK01_LEN= GTH); + mask23 =3D extract32(vpr, R_V7M_VPR_MASK23_SHIFT, R_V7M_VPR_MASK23_LEN= GTH); + if (mask01 > 8) { + /* high bit set, but not 0b1000: invert the relevant half of P0 */ + vpr ^=3D 0xff; + } + if (mask23 > 8) { + /* high bit set, but not 0b1000: invert the relevant half of P0 */ + vpr ^=3D 0xff00; + } + vpr =3D deposit32(vpr, R_V7M_VPR_MASK01_SHIFT, R_V7M_VPR_MASK01_LENGTH, + mask01 << 1); + vpr =3D deposit32(vpr, R_V7M_VPR_MASK23_SHIFT, R_V7M_VPR_MASK23_LENGTH, + mask23 << 1); + env->v7m.vpr =3D vpr; +} + + +#define DO_VLDR(OP, ESIZE, LDTYPE, TYPE, H) \ + void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ + { \ + TYPE *d =3D vd; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned b, e; \ + /* \ + * R_SXTM allows the dest reg to become UNKNOWN for abandoned \ + * beats so we don't care if we update part of the dest and \ + * then take an exception. \ + */ \ + for (b =3D 0, e =3D 0; b < 16; b +=3D ESIZE, e++) { = \ + if (mask & (1 << b)) { \ + d[H(e)] =3D cpu_##LDTYPE##_data_ra(env, addr, GETPC()); \ + addr +=3D ESIZE; \ + } \ + } \ + mve_advance_vpt(env); \ + } + +#define DO_VSTR(OP, ESIZE, STTYPE, TYPE, H) \ + void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ + { \ + TYPE *d =3D vd; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned b, e; \ + for (b =3D 0, e =3D 0; b < 16; b +=3D ESIZE, e++) { = \ + if (mask & (1 << b)) { \ + cpu_##STTYPE##_data_ra(env, addr, d[H(e)], GETPC()); \ + addr +=3D ESIZE; \ + } \ + } \ + mve_advance_vpt(env); \ + } + +DO_VLDR(vldrb, 1, ldub, uint8_t, H1) +DO_VLDR(vldrh, 2, lduw, uint16_t, H2) +DO_VLDR(vldrw, 4, ldl, uint32_t, H4) + +DO_VSTR(vstrb, 1, stb, uint8_t, H1) +DO_VSTR(vstrh, 2, stw, uint16_t, H2) +DO_VSTR(vstrw, 4, stl, uint32_t, H4) + +#undef DO_VLDR +#undef DO_VSTR diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index c54d5cb7305..e8bb2372ad9 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -1,6 +1,6 @@ /* * ARM translation: M-profile MVE instructions - + * * Copyright (c) 2021 Linaro, Ltd. * * This library is free software; you can redistribute it and/or @@ -27,3 +27,125 @@ =20 /* Include the generated decoder */ #include "decode-mve.c.inc" + +typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); + +/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) = */ +static inline long mve_qreg_offset(unsigned reg) +{ + return offsetof(CPUARMState, vfp.zregs[reg].d[0]); +} + +static TCGv_ptr mve_qreg_ptr(unsigned reg) +{ + TCGv_ptr ret =3D tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ret, cpu_env, mve_qreg_offset(reg)); + return ret; +} + +static bool mve_eci_check(DisasContext *s) +{ + /* + * This is a beatwise insn: check that ECI is valid (not a + * reserved value) and note that we are handling it. + * Return true if OK, false if we generated an exception. + */ + s->eci_handled =3D true; + switch (s->eci) { + case ECI_NONE: + case ECI_A0: + case ECI_A0A1: + case ECI_A0A1A2: + case ECI_A0A1A2B0: + return true; + default: + /* Reserved value: INVSTATE UsageFault */ + gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized= (), + default_exception_el(s)); + return false; + } +} + +static void mve_update_eci(DisasContext *s) +{ + /* + * The helper function will always update the CPUState field, + * so we only need to update the DisasContext field. + */ + if (s->eci) { + s->eci =3D (s->eci =3D=3D ECI_A0A1A2B0) ? ECI_A0 : ECI_NONE; + } +} + +static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn) +{ + TCGv_i32 addr; + uint32_t offset; + TCGv_ptr qreg; + + if (!dc_isar_feature(aa32_mve, s)) { + return false; + } + + if (a->qd > 7 || !fn) { + return false; + } + + /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */ + if (a->rn =3D=3D 15 || (a->rn =3D=3D 13 && a->w)) { + return false; + } + + if (!mve_eci_check(s)) { + return true; + } + + if (!vfp_access_check(s)) { + return true; + } + + offset =3D a->imm << a->size; + if (!a->a) { + offset =3D -offset; + } + addr =3D load_reg(s, a->rn); + if (a->p) { + tcg_gen_addi_i32(addr, addr, offset); + } + + qreg =3D mve_qreg_ptr(a->qd); + fn(cpu_env, qreg, addr); + tcg_temp_free_ptr(qreg); + + /* + * Writeback always happens after the last beat of the insn, + * regardless of predication + */ + if (a->w) { + if (!a->p) { + tcg_gen_addi_i32(addr, addr, offset); + } + store_reg(s, a->rn, addr); + } else { + tcg_temp_free_i32(addr); + } + mve_update_eci(s); + return true; +} + +static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a) +{ + MVEGenLdStFn *ldfns[] =3D { + gen_helper_mve_vldrb, + gen_helper_mve_vldrh, + gen_helper_mve_vldrw, + NULL, + }; + MVEGenLdStFn *stfns[] =3D { + gen_helper_mve_vstrb, + gen_helper_mve_vstrh, + gen_helper_mve_vstrw, + NULL, + }; + return do_ldst(s, a, a->l ? ldfns[a->size] : stfns[a->size]); +} diff --git a/target/arm/meson.build b/target/arm/meson.build index 2b50be3f862..25a02bf2769 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -23,6 +23,7 @@ arm_ss.add(files( 'helper.c', 'iwmmxt_helper.c', 'm_helper.c', + 'mve_helper.c', 'neon_helper.c', 'op_helper.c', 'tlb_helper.c', --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623085624; cv=none; d=zohomail.com; s=zohoarc; b=g5tX4n7nZvwooDEl+tuEYY6mOq4/+7q907MhEsaMpicy4MWvpsdqmM8jW/P4+xbOPUdGASB09vV6izl1+4aGZ+dZbFIlrlbf0W0XclS4EyhuPOcHesh4OBdFgc/BzpP1IUxcUSwvaqkt6SLIXrro9LI90Fc3joLMMSnPwXwFRXE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623085624; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=utjJqfqjsvt6vOT/iEMzhSJNuKimAFESDmEerqjSl9E=; b=WaWGDvLQC2o1PP5e19QI/pW0uSm0S6GJE+e5r91t1xtRKJlxTiXnj6rkITvRGIUtp42msRUycrr0UmG++1nI+5ZOvrzajjlzmDFfq9HLNPRqTy9HbLJ+OIXWkrCfnup7RkPgb1Fm2czsDgG/NbnH3F6pG1qQspSxvT1TvsAkt9M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623085624102673.6500390767434; Mon, 7 Jun 2021 10:07:04 -0700 (PDT) Received: from localhost ([::1]:54926 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqIiN-0002dB-3Z for importer@patchew.org; Mon, 07 Jun 2021 13:07:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59308) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIaN-0007TN-UP for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:48 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:41616) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIaB-0007va-B4 for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:43 -0400 Received: by mail-wm1-x330.google.com with SMTP id l11-20020a05600c4f0bb029017a7cd488f5so81672wmq.0 for ; Mon, 07 Jun 2021 09:58:34 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=utjJqfqjsvt6vOT/iEMzhSJNuKimAFESDmEerqjSl9E=; b=fNWJgCUkrNlayNYAA57g84uWCEV3NZ25Lfez5fxk0Aykh3L9+XPIYB+xt/+hkxef7d 41cA3xM4sbbK/TMMwn1ItmTzSr6blaugtVPYdAj7oCm+QPS7B2JsrD28gPmGmabzic83 ARp2AMGmcQB9mkbSuxv7HX1d6EcCWOU3psE88CFS3zBH+7SoVUB9w4b/xM7vPxV3rhNm 8r1vpFutJ0opwclT7ENYoAz5aM5nTkFCgzCVfHh2pidNDukR/6QGB0GNCb+7xGtPx5es HtoCsXRX1k66fXEGDwbMdwqnL1vPVkD9Vp7a3lL9BF8mOyBZXjVo6uxd49prqDHwXzjA 1xQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=utjJqfqjsvt6vOT/iEMzhSJNuKimAFESDmEerqjSl9E=; b=ftXMZdAg9B+r7mQviDsBBGsVlu1bLNnHd/jMzfZap5r04YSefFjVtLJDxTAMHbyVU2 pAKFRtKfxpDgLDVVeq77hmWNQlgLnJc2Z4M4SA2edeuDBtsjGkR6xr6+JBasexXu8Z7V Z1rNARkvyXQ8ZpedDlQ6j7MPB9VwTLhBLo+XwZqgJsh1DjCYu6dWwskimPLublUTElTS Tkvop7QZlfRkEE5UvgdYyxzR573du7OrzAWGYgJ/DWhDul50vhWrRzFpRNdjQCxLu5uZ W/pzgOZ5GqGE3JqBRLlzk6iRv6/SsTqL5ufbfs0Sk4Du1a9JkkVe+od/7hVVJazO6Vy/ jk4A== X-Gm-Message-State: AOAM5318NmwyPrvVI6/60UpaFhJWyl9Sfkg+Rc6iuJ1IYyLAP01cRqw0 f3aLmrlHwxfx7mUZeFdsDvzttQ== X-Google-Smtp-Source: ABdhPJwH6XOseUEZGt5Zt1uRAAwM5Vv5e2MbW8NbI165Rk1Jm+uh0ibr5lDNEvvlP0n+ND1u6W5GJw== X-Received: by 2002:a1c:9a84:: with SMTP id c126mr17828337wme.160.1623085113984; Mon, 07 Jun 2021 09:58:33 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 12/55] target/arm: Implement widening/narrowing MVE VLDR/VSTR insns Date: Mon, 7 Jun 2021 17:57:38 +0100 Message-Id: <20210607165821.9892-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the variants of MVE VLDR (encodings T1, T2) which perform "widening" loads where bytes or halfwords are loaded from memory and zero or sign-extended into halfword or word length vector elements, and the narrowing MVE VSTR (encodings T1, T2) where bytes or halfwords are stored from halfword or word elements. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 10 ++++++++++ target/arm/mve.decode | 25 +++++++++++++++++++++++-- target/arm/mve_helper.c | 10 ++++++++++ target/arm/translate-mve.c | 18 ++++++++++++++++++ 4 files changed, 61 insertions(+), 2 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 9e3b0b09afd..e47d4164ae7 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -22,3 +22,13 @@ DEF_HELPER_FLAGS_3(mve_vldrw, TCG_CALL_NO_WG, void, env,= ptr, i32) DEF_HELPER_FLAGS_3(mve_vstrb, TCG_CALL_NO_WG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vstrh, TCG_CALL_NO_WG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vstrw, TCG_CALL_NO_WG, void, env, ptr, i32) + +DEF_HELPER_FLAGS_3(mve_vldrb_sh, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vldrb_sw, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vldrb_uh, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vldrb_uw, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vldrh_sw, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vldrh_uw, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vstrb_h, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vstrb_w, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vstrh_w, TCG_CALL_NO_WG, void, env, ptr, i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 858a161fd7e..3bc5f034531 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -21,12 +21,33 @@ =20 %qd 22:1 13:3 =20 -&vldr_vstr rn qd imm p a w size l +&vldr_vstr rn qd imm p a w size l u =20 -@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=3D%qd +@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=3D%qd u= =3D0 +# Note that both Rn and Qd are 3 bits only (no D bit) +@vldst_wn ... u:1 ... . . . . l:1 . rn:3 qd:3 . ... .. imm:7 &vldr_vstr =20 # Vector loads and stores =20 +# Widening loads and narrowing stores: +# for these P=3D0 W=3D0 is 'related encoding'; sz=3D11 is 'related encodin= g' +# This means we need to expand out to multiple patterns for P, W, SZ. +# For stores the U bit must be 0 but we catch that in the trans_ function. +# The naming scheme here is "VLDSTB_H =3D=3D in-memory byte load/store to/= from +# signed halfword element in register", etc. +VLDSTB_H 111 . 110 0 a:1 0 1 . 0 ... ... 0 111 01 ....... @vldst= _wn \ + p=3D0 w=3D1 size=3D1 +VLDSTB_H 111 . 110 1 a:1 0 w:1 . 0 ... ... 0 111 01 ....... @vldst= _wn \ + p=3D1 size=3D1 +VLDSTB_W 111 . 110 0 a:1 0 1 . 0 ... ... 0 111 10 ....... @vldst= _wn \ + p=3D0 w=3D1 size=3D2 +VLDSTB_W 111 . 110 1 a:1 0 w:1 . 0 ... ... 0 111 10 ....... @vldst= _wn \ + p=3D1 size=3D2 +VLDSTH_W 111 . 110 0 a:1 0 1 . 1 ... ... 0 111 10 ....... @vldst= _wn \ + p=3D0 w=3D1 size=3D2 +VLDSTH_W 111 . 110 1 a:1 0 w:1 . 1 ... ... 0 111 10 ....... @vldst= _wn \ + p=3D1 size=3D2 + # Non-widening loads/stores (P=3D0 W=3D0 is 'related encoding') VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111100 ....... @vldr_vst= r \ size=3D0 p=3D0 w=3D1 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 575afce8fee..6a2fc1c37cd 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -180,9 +180,19 @@ DO_VLDR(vldrb, 1, ldub, uint8_t, H1) DO_VLDR(vldrh, 2, lduw, uint16_t, H2) DO_VLDR(vldrw, 4, ldl, uint32_t, H4) =20 +DO_VLDR(vldrb_sh, 2, ldsb, int16_t, H2) +DO_VLDR(vldrb_sw, 4, ldsb, int32_t, H4) +DO_VLDR(vldrb_uh, 2, ldub, uint16_t, H2) +DO_VLDR(vldrb_uw, 4, ldub, uint32_t, H4) +DO_VLDR(vldrh_sw, 4, ldsw, int32_t, H4) +DO_VLDR(vldrh_uw, 4, lduw, uint32_t, H4) + DO_VSTR(vstrb, 1, stb, uint8_t, H1) DO_VSTR(vstrh, 2, stw, uint16_t, H2) DO_VSTR(vstrw, 4, stl, uint32_t, H4) +DO_VSTR(vstrb_h, 2, stb, int16_t, H2) +DO_VSTR(vstrb_w, 4, stb, int32_t, H4) +DO_VSTR(vstrh_w, 4, stw, int32_t, H4) =20 #undef DO_VLDR #undef DO_VSTR diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index e8bb2372ad9..14206893d5f 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -149,3 +149,21 @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_= VSTR *a) }; return do_ldst(s, a, a->l ? ldfns[a->size] : stfns[a->size]); } + +#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \ + static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \ + { \ + MVEGenLdStFn *ldfns[] =3D { \ + gen_helper_mve_##SLD, \ + gen_helper_mve_##ULD, \ + }; \ + MVEGenLdStFn *stfns[] =3D { \ + gen_helper_mve_##ST, \ + NULL, \ + }; \ + return do_ldst(s, a, a->l ? ldfns[a->u] : stfns[a->u]); \ + } + +DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h) +DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w) +DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623085810; cv=none; d=zohomail.com; s=zohoarc; b=K4N9i+bYEhGbWJmyDz5KbKPi2npetF6JFVfjL7rdDEVeu2yy+Smrnp9ww9xqF5yYC1e0yAoRDgKWYW48FWHnu7/exctZN3Y0kdfxSGqLHsMJGSSuFs78LzBkeBfPuJiCiwBGabGDjxdvYmov4XTEsz2w8kFtwMR1y0p7T/FmOZ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623085810; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=x6vOOVgQ4YobSFgYhZ+zoWMkCw7inNQqjouGvEkHSxI=; b=F54/9o+LH8PaaOOdgpsXtVWJAwklIWR/E+hXPdFM9p6N0bnObmHMd5ZdhUyx6P4KvkYW5w0tNgokbb0QJOAFC5p0U3+5p9uvMxMQYWivjU4HRQlgKeeMT54ErR4zP3M7m4PTqBiFBnkJuCu6pJbouSp3k85g00CSz2kzumBMMxo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162308581010345.13919374657337; Mon, 7 Jun 2021 10:10:10 -0700 (PDT) Received: from localhost ([::1]:34572 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqIlN-0007yf-6f for importer@patchew.org; Mon, 07 Jun 2021 13:10:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59378) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIaS-0007Ub-Cy for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:55 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:46849) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIaC-0007vx-6A for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:51 -0400 Received: by mail-wm1-x32a.google.com with SMTP id h22-20020a05600c3516b02901a826f84095so45708wmq.5 for ; Mon, 07 Jun 2021 09:58:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=x6vOOVgQ4YobSFgYhZ+zoWMkCw7inNQqjouGvEkHSxI=; b=VMuAZtmFkhWwpS6dVETPt7Cv9/QYAdyCJuF87+E3Mlnl+2rUx5ZyKiljsTqiAeQ0Ym CtM8IuSOWCtyMlAYtbcrlHppYmuEOE8rrEpGXgd4p7PHUSQQ1n1jKANpYzg26yBnvz14 rTj2h5zDcDrlY7BL2tTafbZuvvfxEoUrrtox+CaLUWbHq9npsydAHb9piONnlUYWzklb ZV9/VctCzq3u5YVXKgA63AU6Gdmj8D2uZ28kXMxv5bIzKQ1SIwlrAoxOMFiFraz2U4vJ fh7QoU2F8SnUieOaxmffHFkfN/gMclNmc3vhu6i1h9b2weNsd59jbztHUYpeybvf0OVg vWng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x6vOOVgQ4YobSFgYhZ+zoWMkCw7inNQqjouGvEkHSxI=; b=HkJn5esGsGIYNR+jy0tDJuZfg1EJUGz2V2m5RfHEJoNoyJziN4DlacC4J9KrktIudI KBXyNbA4hG28FA8tXZvzmWnVN58ovWyLsq0L2B8JbCU7yAhazS2n5kkarV2Uaa0p6kul JjpDtGde4kLOdbe7KJfoNHPiEfqlpNnWVGfUyXYjKb8BPdpzkfko6af5a/vpWl6pV8Wg ta1ZjZp4QQI7qXe32Ey6dDdIFKbU96qBH0UGEaMXJv9svK6L6qBgtGo/O+oh8uYk5G0W F6qZE2k0thxv0w4uRE7f9yKuRioUBMsOXgtBitTpIsFlw/QQLzqjCC9fWQfFxM0znq6X 2Fbg== X-Gm-Message-State: AOAM533lzbpORfJzUh80lZLjKvjzyZxw8MOAjhIJ2IycUzYkguvu3MpN VHgD6ybRCxeg1upt1RUv3/VG3uNrFa3OHtEp X-Google-Smtp-Source: ABdhPJxaguVQiglvNpnEY0u4WY95h+5qqXMRXNpBO1nF19p2Xt16anrpXWu/tKDwY8nN69NbG+/jOg== X-Received: by 2002:a05:600c:19d1:: with SMTP id u17mr68719wmq.31.1623085114773; Mon, 07 Jun 2021 09:58:34 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 13/55] target/arm: Implement MVE VCLZ Date: Mon, 7 Jun 2021 17:57:39 +0100 Message-Id: <20210607165821.9892-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VCLZ insn (and the necessary machinery for MVE 1-input vector ops). Note that for non-load instructions predication is always performed at a byte level granularity regardless of element size (R_ZLSJ), and so the masking logic here differs from that used in the VLDR and VSTR helpers. Signed-off-by: Peter Maydell --- target/arm/helper-mve.h | 4 ++++ target/arm/mve.decode | 8 +++++++ target/arm/mve_helper.c | 48 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 43 ++++++++++++++++++++++++++++++++++ 4 files changed, 103 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index e47d4164ae7..c5c1315b161 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -32,3 +32,7 @@ DEF_HELPER_FLAGS_3(mve_vldrh_uw, TCG_CALL_NO_WG, void, en= v, ptr, i32) DEF_HELPER_FLAGS_3(mve_vstrb_h, TCG_CALL_NO_WG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vstrb_w, TCG_CALL_NO_WG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vstrh_w, TCG_CALL_NO_WG, void, env, ptr, i32) + +DEF_HELPER_FLAGS_3(mve_vclzb, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vclzh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vclzw, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 3bc5f034531..24999bf703e 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -20,13 +20,17 @@ # =20 %qd 22:1 13:3 +%qm 5:1 1:3 =20 &vldr_vstr rn qd imm p a w size l u +&1op qd qm size =20 @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=3D%qd u= =3D0 # Note that both Rn and Qd are 3 bits only (no D bit) @vldst_wn ... u:1 ... . . . . l:1 . rn:3 qd:3 . ... .. imm:7 &vldr_vstr =20 +@1op .... .... .... size:2 .. .... .... .... .... &1op qd=3D%qd qm=3D%qm + # Vector loads and stores =20 # Widening loads and narrowing stores: @@ -61,3 +65,7 @@ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111101 ..= ..... @vldr_vstr \ size=3D1 p=3D1 VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vst= r \ size=3D2 p=3D1 + +# Vector miscellaneous + +VCLZ 1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 6a2fc1c37cd..b7c44f57c09 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -196,3 +196,51 @@ DO_VSTR(vstrh_w, 4, stw, int32_t, H4) =20 #undef DO_VLDR #undef DO_VSTR + +/* + * Take the bottom bits of mask (which is 1 bit per lane) and + * convert to a mask which has 1s in each byte which is predicated. + */ +static uint8_t mask_to_bytemask1(uint16_t mask) +{ + return (mask & 1) ? 0xff : 0; +} + +static uint16_t mask_to_bytemask2(uint16_t mask) +{ + static const uint16_t masks[] =3D { 0x0000, 0x00ff, 0xff00, 0xffff }; + return masks[mask & 3]; +} + +static uint32_t mask_to_bytemask4(uint16_t mask) +{ + static const uint32_t masks[] =3D { + 0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff, + 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff, + 0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff, + 0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff, + }; + return masks[mask & 0xf]; +} + +#define DO_1OP(OP, ESIZE, TYPE, H, FN) \ + void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ + { \ + TYPE *d =3D vd, *m =3D vm; = \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + TYPE r =3D FN(m[H(e)]); \ + uint64_t bytemask =3D mask_to_bytemask##ESIZE(mask); \ + d[H(e)] &=3D ~bytemask; \ + d[H(e)] |=3D (r & bytemask); \ + } \ + mve_advance_vpt(env); \ + } + +#define DO_CLZ_B(N) (clz32(N) - 24) +#define DO_CLZ_H(N) (clz32(N) - 16) + +DO_1OP(vclzb, 1, uint8_t, H1, DO_CLZ_B) +DO_1OP(vclzh, 2, uint16_t, H2, DO_CLZ_H) +DO_1OP(vclzw, 4, uint32_t, H4, clz32) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 14206893d5f..6bbc2df35c1 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -29,6 +29,7 @@ #include "decode-mve.c.inc" =20 typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); +typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); =20 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) = */ static inline long mve_qreg_offset(unsigned reg) @@ -167,3 +168,45 @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_= VSTR *a) DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h) DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w) DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w) + +static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) +{ + TCGv_ptr qd, qm; + + if (!dc_isar_feature(aa32_mve, s)) { + return false; + } + if (a->qd > 7 || a->qm > 7 || !fn) { + return false; + } + + if (!mve_eci_check(s)) { + return true; + } + + if (!vfp_access_check(s)) { + return true; + } + + qd =3D mve_qreg_ptr(a->qd); + qm =3D mve_qreg_ptr(a->qm); + fn(cpu_env, qd, qm); + tcg_temp_free_ptr(qd); + tcg_temp_free_ptr(qm); + mve_update_eci(s); + return true; +} + +#define DO_1OP(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_1op *a) \ + { \ + MVEGenOneOpFn *fns[] =3D { \ + gen_helper_mve_##FN##b, \ + gen_helper_mve_##FN##h, \ + gen_helper_mve_##FN##w, \ + NULL, \ + }; \ + return do_1op(s, a, fns[a->size]); \ + } + +DO_1OP(VCLZ, vclz) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623085830; cv=none; d=zohomail.com; s=zohoarc; b=Js4zPCkCsc2AS9STfbOt0OxNmbNufVdVVEXd/DFTLLExWGpYEmaNPr35fwuSObLxZ/cb2YtPY49jQOdVfYLtldqxLJotldmpCeW8wGN3bs5xADSTpnC3q0Xpd0iYq+SJBJUs6ZSihVkbrOOp48OcQKSkWzCIQYc26aAGHt/9pms= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623085830; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dsfWk4RgZnVdekDcntrGGEvaZTH7s3WlSeioagute4g=; b=RhDn9cSF8zK8mvCkpabU0bpXdatxR1EggX1I7X2kDJVTasaLkzOD+0mpjnSK9MQ5kTi9ctsQ4Df0ldMSlb2V1DD2vSpQyzjeW7rVUFVNEzYIgBgWDc7LXyxt4oM7AKTiVKFSXG5Utd9RMo5qXWpsRPX2O4qClPVYhd7ZA8uEUhs= ARC-Authentication-Results: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dsfWk4RgZnVdekDcntrGGEvaZTH7s3WlSeioagute4g=; b=cK86Jo3xRhQT6CF8lT4IxxG60z5N5laORThXccw+US46zbH/nItWq3NTCYjrI6M6eI 2GPJDFhx3C+MtzVAXlwHLJMYATwRq0ho0u1PE9IuVj1FQfucwHV6JRX9xzCAPUvnEeNS CY7pDxgFtTRhepiB3LRSL5hmdXE0Or0Da1lHuIfwf6D6NWA0yf/jKV5PHQoWWjf5p3/4 98C0/QYakgAu/AaxDF5WabV84Oq9F1QOH9WqVTHEr+Q8xTIJwB3JywLnk82JqVuizrgR tz2J8kDipsauNJZbkjLH05xriY9m8E+cYAj2WxF7qRRIXobOqMm+4Gc1uq7L0vaGc8Qf RUdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dsfWk4RgZnVdekDcntrGGEvaZTH7s3WlSeioagute4g=; b=JqoQb2LnP/NKQofZGA/pfyGiood1GTDdY6XihuL3/6lDbC+wT4fUqY4JDzP0zIxyil Od5ToGQho0p7aQxjWWsbO1tJp3O5mx9ic3tP2yej2uVXZ6p4SSVHRafpg/MiCExh2ef8 5BA96x1LC8vY1BH0jdBrQx2THo3uX1LKkDXoohOFFvZJaULVa0nkrFaBc30eoB3CbTUQ +dn2Zpj4tSdd8BP2t0VqDLugCVpfiUwkn8QeuESMgfTDsW2NLt9KXJe5SvolqGSPBM7b AveLVCukqLsdfR3SWbaoXLhV4zCYypIMncf7JFISURTq9SsnHGyp7gjNSCSwIbieoDHP Mf0A== X-Gm-Message-State: AOAM532XDX7qRJcc/ssixY18SW8QjI1PucabYYMtbY+O6FGBkUB18KFv YwlVQ2ETPc2Az62CEzYaDIL2zQ== X-Google-Smtp-Source: ABdhPJxH/WoqyrlA+wFfQXwMcRL5BElpHEOdpPCmgdxBZnO/HMahrNpbnV2DLxfg4Yca4pH4uTyJMg== X-Received: by 2002:a05:600c:4ec8:: with SMTP id g8mr93120wmq.62.1623085115455; Mon, 07 Jun 2021 09:58:35 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 14/55] target/arm: Implement MVE VCLS Date: Mon, 7 Jun 2021 17:57:40 +0100 Message-Id: <20210607165821.9892-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VCLS insn. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 4 ++++ target/arm/mve.decode | 1 + target/arm/mve_helper.c | 7 +++++++ target/arm/translate-mve.c | 1 + 4 files changed, 13 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index c5c1315b161..bdd6675ea14 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -33,6 +33,10 @@ DEF_HELPER_FLAGS_3(mve_vstrb_h, TCG_CALL_NO_WG, void, en= v, ptr, i32) DEF_HELPER_FLAGS_3(mve_vstrb_w, TCG_CALL_NO_WG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vstrh_w, TCG_CALL_NO_WG, void, env, ptr, i32) =20 +DEF_HELPER_FLAGS_3(mve_vclsb, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vclsh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vclsw, TCG_CALL_NO_WG, void, env, ptr, ptr) + DEF_HELPER_FLAGS_3(mve_vclzb, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vclzh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vclzw, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 24999bf703e..adceef91597 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -68,4 +68,5 @@ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ..= ..... @vldr_vstr \ =20 # Vector miscellaneous =20 +VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op VCLZ 1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index b7c44f57c09..071c9070593 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -238,6 +238,13 @@ static uint32_t mask_to_bytemask4(uint16_t mask) mve_advance_vpt(env); \ } =20 +#define DO_CLS_B(N) (clrsb32(N) - 24) +#define DO_CLS_H(N) (clrsb32(N) - 16) + +DO_1OP(vclsb, 1, int8_t, H1, DO_CLS_B) +DO_1OP(vclsh, 2, int16_t, H2, DO_CLS_H) +DO_1OP(vclsw, 4, int32_t, H4, clrsb32) + #define DO_CLZ_B(N) (clz32(N) - 24) #define DO_CLZ_H(N) (clz32(N) - 16) =20 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 6bbc2df35c1..3c6897548a2 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -210,3 +210,4 @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGenO= neOpFn fn) } =20 DO_1OP(VCLZ, vclz) +DO_1OP(VCLS, vcls) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623086052; cv=none; d=zohomail.com; s=zohoarc; b=IPnQE0hPQZy3M3PIYHSPAXzruHmoXsfv/zii4tdZOUUDIrl51Z/z9+4YOUNtxEEKITVNXt8kGdM6658MqmsK/ibk2sDeTID+/LD53rW3NBVkjxGUnlJ8bdiYkB5Foy8hUcwNS73eG+f36M+c2aHlxNwZnd43v8csWA14uDqVtb8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623086052; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8Vw8HCdQuc72QNtYY1HMST7xyxh7hPAptN30nR4g61U=; b=I2G+sM4Vuh4c8v0tDI0lXkoLe8W1yiMrPH4kpp9FIpmCD3c1rocNP0KqrRmknqUj/RghmF39HqLGfbIIt03/YgaTf7Mta0reKoZv9ftV+HQYrnNd2LmCYxQmkD01V/1DsgHuQedHhW8xevJfDE71ZKiVWfJnPzBWaHXIeC5/vSw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623086052732312.53941909387345; Mon, 7 Jun 2021 10:14:12 -0700 (PDT) Received: from localhost ([::1]:46644 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqIpH-0007fj-St for importer@patchew.org; Mon, 07 Jun 2021 13:14:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59580) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIaa-0007Xs-1m for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:01 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:46671) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIaD-0007wS-IS for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:58 -0400 Received: by mail-wr1-x42a.google.com with SMTP id a11so16558638wrt.13 for ; Mon, 07 Jun 2021 09:58:37 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8Vw8HCdQuc72QNtYY1HMST7xyxh7hPAptN30nR4g61U=; b=wnrZ6aVy4zPhteDx0VrTiqe1YlYNzPQpHwQB4hFa4mDgqHEB63JRYpd72ahDzJl+BG lSNpIVLyQDCr1HEHl6d7o0VQ9evodMFL0w0mfFxVJ10LEO1c9RfyENbQnAMhg89aszRf bz3/BanB5AXuAOrAr+cbnLl5QArtGhdi01+MLbRWzMdx2Cl8YP/AzKRoYHm7bFmrxo1s IjLjXF3LOTzVfHTh5FfN9vAZRejkwB4SoMeKQEOHNo9q5obIpJjdEgfWTwM3EBuDCop4 1AZH+RQ4ruMqejZS2YVAODSXlOx5pGl8Yq5A6SIZGZr2kr4eFYtlWT6FaXUtBS6/g3hS 4mcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8Vw8HCdQuc72QNtYY1HMST7xyxh7hPAptN30nR4g61U=; b=ZgZ4kl8KIN3SLew2SKf35dUUDAEPa4nMalrqeq/409BgOmuxoZf4MSCMVUVfmis7QH nvmECDZ8eQmCPse4ewS3NPpAOR5WZkW1wtOBv5gBJeoXAQ3BSCICXJngrrYitrQA8ecx z5WZIKlefeKT6hQpQJ/BluQKNvrVPWsII3iTAlB3qHUkYxTQUJDVH2F9YihmcPC1f4Um kJJ5MD0eqFNKCKUyj3o+2jnwDGHtdiYslKEulei0wBEzcrDRCRQeTlUTUhHalD7jJZDF s5Tl7kpiUE3d4oDjAyD1SpZnwvJDuCNoDveTuBVO7Xl/tPpPPgmwcldkBNL1LUBbL8D7 ELkA== X-Gm-Message-State: AOAM5304vqZhq5KuxrLe+GVjucnttV6YOnG8d8B465Ixp3Y2Vazng8X9 I1nzJMhhV8ErMLAU6nj/wUmgxQ== X-Google-Smtp-Source: ABdhPJw4Eh7RgwIPsVeroSlKapK7cwPlx5qgZpxRLQtg6x4GAr+D7D3tlztrLRLiSQnFsaxF7CTyOQ== X-Received: by 2002:a5d:5243:: with SMTP id k3mr18358046wrc.19.1623085116139; Mon, 07 Jun 2021 09:58:36 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 15/55] bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations Date: Mon, 7 Jun 2021 17:57:41 +0100 Message-Id: <20210607165821.9892-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Currently the ARM SVE helper code defines locally some utility functions for swapping 16-bit halfwords within 32-bit or 64-bit values and for swapping 32-bit words within 64-bit values, parallel to the byte-swapping bswap16/32/64 functions. We want these also for the ARM MVE code, and they're potentially generally useful for other targets, so move them to bitops.h. (We don't put them in bswap.h with the bswap* functions because they are implemented in terms of the rotate operations also defined in bitops.h, and including bitops.h from bswap.h seems better avoided.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/qemu/bitops.h | 29 +++++++++++++++++++++++++++++ target/arm/sve_helper.c | 20 -------------------- 2 files changed, 29 insertions(+), 20 deletions(-) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index a72f69fea85..03213ce952c 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -291,6 +291,35 @@ static inline uint64_t ror64(uint64_t word, unsigned i= nt shift) return (word >> shift) | (word << ((64 - shift) & 63)); } =20 +/** + * hswap32 - swap 16-bit halfwords within a 32-bit value + * @h: value to swap + */ +static inline uint32_t hswap32(uint32_t h) +{ + return rol32(h, 16); +} + +/** + * hswap64 - swap 16-bit halfwords within a 64-bit value + * @h: value to swap + */ +static inline uint64_t hswap64(uint64_t h) +{ + uint64_t m =3D 0x0000ffff0000ffffull; + h =3D rol64(h, 32); + return ((h & m) << 16) | ((h >> 16) & m); +} + +/** + * wswap64 - swap 32-bit words within a 64-bit value + * @h: value to swap + */ +static inline uint64_t wswap64(uint64_t h) +{ + return rol64(h, 32); +} + /** * extract32: * @value: the value to extract the bit field from diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 46a957b6fb0..15aa0a74982 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -247,26 +247,6 @@ static inline uint64_t expand_pred_s(uint8_t byte) return word[byte & 0x11]; } =20 -/* Swap 16-bit words within a 32-bit word. */ -static inline uint32_t hswap32(uint32_t h) -{ - return rol32(h, 16); -} - -/* Swap 16-bit words within a 64-bit word. */ -static inline uint64_t hswap64(uint64_t h) -{ - uint64_t m =3D 0x0000ffff0000ffffull; - h =3D rol64(h, 32); - return ((h & m) << 16) | ((h >> 16) & m); -} - -/* Swap 32-bit words within a 64-bit word. */ -static inline uint64_t wswap64(uint64_t h) -{ - return rol64(h, 32); -} - #define LOGICAL_PPPP(NAME, FUNC) \ void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \ { \ --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623086006; cv=none; d=zohomail.com; s=zohoarc; b=H3kSCoTuJR3hX52O+9JJydSWty0xVyDu7v6GZBJTEvubQMVpRb3WpHUCUDYmmbvn9BdMzmtQScFG8rgJ+BP5f5i+dtRMDrfn+QIMqOfyNPEsEHvbOYVjWyKYq6EyVq2ZNP4NUYdyVx3AIimgz7fT+RoCYqwtKDcNUnHUbhhbVPQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623086006; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6Rsk/f9XH2z8c09SGzGh+1Fe4wrjJ7bWOiZfaWKb1t0=; b=MHk6Jir7BxbsNf7+U5nuMa2yqrBJcbA54dZVAg+4U9nL//nvZFzqvGsKqkjbSj3zGIySPboeOWIrBA6T35a4DsoFN2U/eUZ+kscBxGN7maU+al2vRoqXX1iFaGmKUKVxlSBtUVkI/fm6BsEFS3NAEy1GDcQV8RQ9xycleT9CQB0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623086005995672.329277484862; Mon, 7 Jun 2021 10:13:25 -0700 (PDT) Received: from localhost ([::1]:44112 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqIoW-0005zb-Qu for importer@patchew.org; Mon, 07 Jun 2021 13:13:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59502) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIaY-0007Vp-3b for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:59 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:45819) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIaE-0007ww-6G for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:56 -0400 Received: by mail-wr1-x432.google.com with SMTP id z8so18395247wrp.12 for ; Mon, 07 Jun 2021 09:58:37 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6Rsk/f9XH2z8c09SGzGh+1Fe4wrjJ7bWOiZfaWKb1t0=; b=Lnw5acNAA77FaJwe5vk//7apexfmOLXlGLi7qnQCczuNAqzR/HIjVtldo9oNJ3UZEM USDx/2FCkPZp2all0U4IGLLVlu4NaOpemLTINk9tjR14OyRzauVNgJbSgIveSGFbRBEl ZAxnvdqm+ugV97Kx+Um65h4Bc7Psu3bVVyw18Me+Fzet4i8AaPiken6+7yb+kynx2rvP Zbgb1Z5728xVMIPsrML/UFQgC2iSlmtJ8qNGUTxPdDD7pbb7Utw0wSHRMF6vzxVsTp8v p9+X/WmwPu/J40CgpvIMAhamlKOua7BXCyK6SSKpYVWoJgi5IGzw5i2CFFL2zhMsmZqC vUYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6Rsk/f9XH2z8c09SGzGh+1Fe4wrjJ7bWOiZfaWKb1t0=; b=RWj9SoJ3q6eStdy+VY3HOvzrc0P/AfGnuV1C2s+Z6EtVLvHItK/5ntrwsig/d/uOG0 BL9sTG/nptFeCEHQyhyjfK/xp0iB4B+F3nqYv6ONidYD4oSgY6qdBIyH2j0Ya6gHE/fp NzjmeE5GN10g1ltVenIRAK6CZmR/D3FQK5NHVa1W5+RV0weIAG0e3fJuYaLzQ8DYmCpD wZQwqL1IJq5bo2Rqozzznvy5exBfbGn+U98V4ciGUp4Qvm5U4FZfLJCbM466wFTixPCi zml6VJFo1epmq8P7msFdO78pu33o9DRSxsIwHP5/AXbxOE3iJ4yoJBe4Ai8J8Wn/gu0/ MI3w== X-Gm-Message-State: AOAM530ZCjN5n23GHzDmTEPF+vsrn8YhXa7gmS1pish3KfMY3qnmuXn+ 7W5iULkJb4LGnahbFh3fVV4+6Q== X-Google-Smtp-Source: ABdhPJwkUBeFcBkdzZKbeq2ZLN5lGEHyiFhDNQCuWd4fq0iaPhUZxnnLfXAk92a61eCDn9ayes9cmw== X-Received: by 2002:a5d:484b:: with SMTP id n11mr11450912wrs.34.1623085116923; Mon, 07 Jun 2021 09:58:36 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 16/55] target/arm: Implement MVE VREV16, VREV32, VREV64 Date: Mon, 7 Jun 2021 17:57:42 +0100 Message-Id: <20210607165821.9892-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE instructions VREV16, VREV32 and VREV64. Signed-off-by: Peter Maydell --- target/arm/helper-mve.h | 7 +++++++ target/arm/mve.decode | 4 ++++ target/arm/mve_helper.c | 13 +++++++++++++ target/arm/translate-mve.c | 33 +++++++++++++++++++++++++++++++++ 4 files changed, 57 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index bdd6675ea14..4c89387587d 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -40,3 +40,10 @@ DEF_HELPER_FLAGS_3(mve_vclsw, TCG_CALL_NO_WG, void, env,= ptr, ptr) DEF_HELPER_FLAGS_3(mve_vclzb, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vclzh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vclzw, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vrev16b, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vrev32b, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vrev32h, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vrev64b, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vrev64h, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vrev64w, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index adceef91597..16ee511a5cb 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -70,3 +70,7 @@ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ..= ..... @vldr_vstr \ =20 VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op VCLZ 1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0 ... 0 @1op + +VREV16 1111 1111 1 . 11 .. 00 ... 0 0001 01 . 0 ... 0 @1op +VREV32 1111 1111 1 . 11 .. 00 ... 0 0000 11 . 0 ... 0 @1op +VREV64 1111 1111 1 . 11 .. 00 ... 0 0000 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 071c9070593..055606b905f 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -223,6 +223,12 @@ static uint32_t mask_to_bytemask4(uint16_t mask) return masks[mask & 0xf]; } =20 +static uint64_t mask_to_bytemask8(uint16_t mask) +{ + return mask_to_bytemask4(mask) | + ((uint64_t)mask_to_bytemask4(mask >> 4) << 32); +} + #define DO_1OP(OP, ESIZE, TYPE, H, FN) \ void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ { \ @@ -251,3 +257,10 @@ DO_1OP(vclsw, 4, int32_t, H4, clrsb32) DO_1OP(vclzb, 1, uint8_t, H1, DO_CLZ_B) DO_1OP(vclzh, 2, uint16_t, H2, DO_CLZ_H) DO_1OP(vclzw, 4, uint32_t, H4, clz32) + +DO_1OP(vrev16b, 2, uint16_t, H2, bswap16) +DO_1OP(vrev32b, 4, uint32_t, H4, bswap32) +DO_1OP(vrev32h, 4, uint32_t, H4, hswap32) +DO_1OP(vrev64b, 8, uint64_t, , bswap64) +DO_1OP(vrev64h, 8, uint64_t, , hswap64) +DO_1OP(vrev64w, 8, uint64_t, , wswap64) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 3c6897548a2..6f3d4796072 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -211,3 +211,36 @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGen= OneOpFn fn) =20 DO_1OP(VCLZ, vclz) DO_1OP(VCLS, vcls) + +static bool trans_VREV16(DisasContext *s, arg_1op *a) +{ + MVEGenOneOpFn *fns[] =3D { + gen_helper_mve_vrev16b, + NULL, + NULL, + NULL, + }; + return do_1op(s, a, fns[a->size]); +} + +static bool trans_VREV32(DisasContext *s, arg_1op *a) +{ + MVEGenOneOpFn *fns[] =3D { + gen_helper_mve_vrev32b, + gen_helper_mve_vrev32h, + NULL, + NULL, + }; + return do_1op(s, a, fns[a->size]); +} + +static bool trans_VREV64(DisasContext *s, arg_1op *a) +{ + MVEGenOneOpFn *fns[] =3D { + gen_helper_mve_vrev64b, + gen_helper_mve_vrev64h, + gen_helper_mve_vrev64w, + NULL, + }; + return do_1op(s, a, fns[a->size]); +} --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623086318; cv=none; d=zohomail.com; s=zohoarc; b=KLCBNp80g6e/5G/uy8S/JlPQIdq+fvWCC8UV3vLTZyBr2Ji62fLP3VsmU7577ZDi3+XXLYGQz2Eq7P82So+BHVuD4x0VYWze4ZnqjVS6LkLOCvBmAQq/0i5I7d6Den2ure3+gqbpaGao32RKhe/aIN8QNqM371o95eK8eeItAgI= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=H19RDZJNg8cq62khuNWsX5QbG2di80hVtTkNupGoEFg=; b=nvNL5c1jh19l6gL9bQO/lwmKWi+3vHwPtCgomvG93WLwrfzQ8q78GuUbV8OJYlGHgZ 8FkyF+ppFvJx4/VWQhxzSTrDsd2CcFH7J30AAFQ41c1CcylJTBS/3lFKm9dVv+twNUBL p0V58ywOW6e8KE5PrdnmbCqO1XCf4AGYgBrJ0zNUb8haxDP0WSsIFPEKJBmCNzasrZBT 3NL2xHT8CWSKSyxxRRRRFNJFIUG6cq4d1UdGIfuevFzX77EzxNZrFA9CIWUYvHpQj2Ko iI7XtRnR5XpnzMsQUMhIiPlh28G4mP3Sxtz9yznLxjRRBl3Hj922wdEc9otqhC+voXXE ppjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H19RDZJNg8cq62khuNWsX5QbG2di80hVtTkNupGoEFg=; b=ZTjyREJJtzbgk4PYd8nF++tx3pIQJ4jsPVvVLzWxwL75z9qPVpwMJe62X5O7FVImXA hTZ/oW1SoXeIcLe3WR1vJH3Lnnl9Y4YZtfuioPTCttLSeaM3iJt7gmOjTGyfriDEdR04 73swWXi4JVGJL2itpRR40Dva/3fIVrFAaJ6v1XgA7tpImqaCDziupAJ7+nc2rmZtnRkm nSFkMIahYOQnSt7IqABceqXlcHghXGsKKJZEBxx99umPlzp07uMITpt0cznUgy5CC6JX UTa4//YUIkCcZiBNctUvYywPfyBqiV5pEmOVLHkZCMis6cl3x3hwavh06anTTDSGx67j GdCw== X-Gm-Message-State: AOAM531zInJEekS8M5n8Qm0PRQZdyl5+8z4tJjrHXTHZHAcDtqptdH0e dv424JGwwoBD0wxqnNtOWu/uWg== X-Google-Smtp-Source: ABdhPJxdAVGHVCf7HMkQAXUm91pkGOGHXIbmWoSectS4tJ7qqHqOJjzNJvuOOXF8yKoigsjs8JRB2Q== X-Received: by 2002:a7b:c206:: with SMTP id x6mr99907wmi.26.1623085117675; Mon, 07 Jun 2021 09:58:37 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 17/55] target/arm: Implement MVE VMVN (register) Date: Mon, 7 Jun 2021 17:57:43 +0100 Message-Id: <20210607165821.9892-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VMVN(register) operation. Note that for predication this operation is byte-by-byte. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 2 ++ target/arm/mve.decode | 3 +++ target/arm/mve_helper.c | 4 ++++ target/arm/translate-mve.c | 5 +++++ 4 files changed, 14 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 4c89387587d..f1dc52f7a50 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -47,3 +47,5 @@ DEF_HELPER_FLAGS_3(mve_vrev32h, TCG_CALL_NO_WG, void, env= , ptr, ptr) DEF_HELPER_FLAGS_3(mve_vrev64b, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vrev64h, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vrev64w, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vmvn, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 16ee511a5cb..ff8afb682fb 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -30,6 +30,7 @@ @vldst_wn ... u:1 ... . . . . l:1 . rn:3 qd:3 . ... .. imm:7 &vldr_vstr =20 @1op .... .... .... size:2 .. .... .... .... .... &1op qd=3D%qd qm=3D%qm +@1op_nosz .... .... .... .... .... .... .... .... &1op qd=3D%qd qm=3D%qm s= ize=3D0 =20 # Vector loads and stores =20 @@ -74,3 +75,5 @@ VCLZ 1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0= ... 0 @1op VREV16 1111 1111 1 . 11 .. 00 ... 0 0001 01 . 0 ... 0 @1op VREV32 1111 1111 1 . 11 .. 00 ... 0 0000 11 . 0 ... 0 @1op VREV64 1111 1111 1 . 11 .. 00 ... 0 0000 01 . 0 ... 0 @1op + +VMVN 1111 1111 1 . 11 00 00 ... 0 0101 11 . 0 ... 0 @1op_nosz diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 055606b905f..2aacc733166 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -264,3 +264,7 @@ DO_1OP(vrev32h, 4, uint32_t, H4, hswap32) DO_1OP(vrev64b, 8, uint64_t, , bswap64) DO_1OP(vrev64h, 8, uint64_t, , hswap64) DO_1OP(vrev64w, 8, uint64_t, , wswap64) + +#define DO_NOT(N) (~(N)) + +DO_1OP(vmvn, 1, uint8_t, H1, DO_NOT) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 6f3d4796072..6e5c3df7179 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -244,3 +244,8 @@ static bool trans_VREV64(DisasContext *s, arg_1op *a) }; return do_1op(s, a, fns[a->size]); } + +static bool trans_VMVN(DisasContext *s, arg_1op *a) +{ + return do_1op(s, a, gen_helper_mve_vmvn); +} --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623086164; cv=none; d=zohomail.com; s=zohoarc; b=PZ6J8h6rm8baqt6k+KRuZq2f/F32p9URLE+qozRh0IgbbfC73Aj35ueTUJWPdzOyyO52YM4HahmKE4LSGm48/yKJHLzqzJ+P8pSskdY8kPufiE9ThIluOevoiLLD7JaAQ/p7iPmdj98W1d+38Iy7BrymMCZUAw66UODO00On8pk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623086164; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=c6Jj1IYb7LDFf56c8r659bwDvpRJPFejbh93NlcP4KI=; b=VgEGGprUiCa58vHkxXT9QXqKJiY3UJMyhYd1skqd1/JLjR1tyoy1zpUFkASGlVYarbnBJKUhz4j6ZKZsaVjo99V8g35pUnlc+J+R+c2RyiRA98PGd3KmCUrZICK+qtasN79yFDXJQZRnImJ5SOkTXt7wZb0HmA9QOEjdPJzGYdk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623086164085984.2793967554686; Mon, 7 Jun 2021 10:16:04 -0700 (PDT) Received: from localhost ([::1]:52834 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqIr5-0003MU-8P for importer@patchew.org; Mon, 07 Jun 2021 13:16:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59586) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIaa-0007Xv-66 for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:01 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:39511) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIaG-0007yI-Aj for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:58:59 -0400 Received: by mail-wr1-x42c.google.com with SMTP id l2so18465510wrw.6 for ; Mon, 07 Jun 2021 09:58:39 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=c6Jj1IYb7LDFf56c8r659bwDvpRJPFejbh93NlcP4KI=; b=BzjO+Nl1u8/aYhF7ocCCNCv9EErz76xrAkSZVUp16jk/3V0P39u+h21u04+DQQdQvb 3UQgraKKt4e0nDbRpcgjS9DvICpBS2pAHGMlI3qTQ2XPUy6rp15Qb5g0Bly9JujtyIbu RkQuE+FQprNRWjE0wFPKE+d8JuzlN7VZ/jNYuVPSaj1G6SK0pwqJ2a8wpI/xUIXfsmEw 6L4AIMLboAGWXdQWT3NDOCV7LGPCvTZNjZR/XNRpfVn54/oEgyQIrHdTT5wkJTmqt1Xb dBj9fcUkAgyBzQyouC2oMphg4Sjkklots4jWpWcKnDfjfSgOb54ZmXLl4cPAS2iY0KRz nubQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c6Jj1IYb7LDFf56c8r659bwDvpRJPFejbh93NlcP4KI=; b=AmOFrzzzAhT7xDOKfLtGZo3NWg/8o7bG75aYiItXNpHUR0QEnoLdaZ1GSoFTWivGNg shgcTvjkNLBffjMvvlddYgqVcIn5glG6YjehGi4uWNkm5Du0aruGNnBenLGe+6Oxlcjx erzvNqxcGLJww88pTnznuK51L3hX/218gGmdMWUImwNoIUxJyUDGeNWhyqoIUrK5EmeD xMQcnzCb2FdghE/Oae3NgiueP6XZEubQEI6uEaKEgk/IG4nftBn/zAQjQ5sdRuGZjT1P Fb36xZbprCFwp4hTjpL7d2Nu2PPa6MJ83vFfUUqi6Nefjxo4dlL/rdprU9ZsYA9f2CMK KSNA== X-Gm-Message-State: AOAM532EXGQVYjlrqnxEP/TtpYVyy2Zh84+IYOJSa/AkgcT9aHo9RqJh 4sMeJC5vfpag8Ol9xhX1Ewf+BfMyGjM1MIdk X-Google-Smtp-Source: ABdhPJyOtewLGNqzNNDk6i6DbTmQdHygn02zkVx3a6H9yLQLoNo7aJdIMaQuefFy7CUdgS7x8+9Qqw== X-Received: by 2002:a05:6000:1acd:: with SMTP id i13mr9833901wry.327.1623085118426; Mon, 07 Jun 2021 09:58:38 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 18/55] target/arm: Implement MVE VABS Date: Mon, 7 Jun 2021 17:57:44 +0100 Message-Id: <20210607165821.9892-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VABS functions (both integer and floating point). Signed-off-by: Peter Maydell --- target/arm/helper-mve.h | 6 ++++++ target/arm/mve.decode | 3 +++ target/arm/mve_helper.c | 10 ++++++++++ target/arm/translate-mve.c | 15 +++++++++++++++ 4 files changed, 34 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index f1dc52f7a50..76508d5dd71 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -49,3 +49,9 @@ DEF_HELPER_FLAGS_3(mve_vrev64h, TCG_CALL_NO_WG, void, env= , ptr, ptr) DEF_HELPER_FLAGS_3(mve_vrev64w, TCG_CALL_NO_WG, void, env, ptr, ptr) =20 DEF_HELPER_FLAGS_3(mve_vmvn, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vabsb, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vabsh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vabsw, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vfabsh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vfabss, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index ff8afb682fb..66963dc1847 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -77,3 +77,6 @@ VREV32 1111 1111 1 . 11 .. 00 ... 0 0000 11 . 0= ... 0 @1op VREV64 1111 1111 1 . 11 .. 00 ... 0 0000 01 . 0 ... 0 @1op =20 VMVN 1111 1111 1 . 11 00 00 ... 0 0101 11 . 0 ... 0 @1op_nosz + +VABS 1111 1111 1 . 11 .. 01 ... 0 0011 01 . 0 ... 0 @1op +VABS_fp 1111 1111 1 . 11 .. 01 ... 0 0111 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 2aacc733166..2ab05e66dfc 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -268,3 +268,13 @@ DO_1OP(vrev64w, 8, uint64_t, , wswap64) #define DO_NOT(N) (~(N)) =20 DO_1OP(vmvn, 1, uint8_t, H1, DO_NOT) + +#define DO_ABS(N) ((N) < 0 ? -(N) : (N)) +#define DO_FABS(N) (N & ((__typeof(N))-1 >> 1)) + +DO_1OP(vabsb, 1, int8_t, H1, DO_ABS) +DO_1OP(vabsh, 2, int16_t, H2, DO_ABS) +DO_1OP(vabsw, 4, int32_t, H4, DO_ABS) + +DO_1OP(vfabsh, 2, uint16_t, H2, DO_FABS) +DO_1OP(vfabss, 4, uint32_t, H4, DO_FABS) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 6e5c3df7179..badd4da2cbf 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -211,6 +211,7 @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGenO= neOpFn fn) =20 DO_1OP(VCLZ, vclz) DO_1OP(VCLS, vcls) +DO_1OP(VABS, vabs) =20 static bool trans_VREV16(DisasContext *s, arg_1op *a) { @@ -249,3 +250,17 @@ static bool trans_VMVN(DisasContext *s, arg_1op *a) { return do_1op(s, a, gen_helper_mve_vmvn); } + +static bool trans_VABS_fp(DisasContext *s, arg_1op *a) +{ + MVEGenOneOpFn *fns[] =3D { + NULL, + gen_helper_mve_vfabsh, + gen_helper_mve_vfabss, + NULL, + }; + if (!dc_isar_feature(aa32_mve_fp, s)) { + return false; + } + return do_1op(s, a, fns[a->size]); +} --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623086241; cv=none; d=zohomail.com; s=zohoarc; b=BiZwW47fed/+2eDJ64v6CSxapA3Bee3sEViPrOJy1ewUBGtm+JuI+ysNpwrKQWIx4SMfSx39TGi/JhrCCGqY2qRgEfYHtgWxwGL4HBjK/GMzTZX8ShC8WuMFYXmvyJo9C93xyDjz+EehlerIoukolPwtBJUyjbofe/hNDxW3nco= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623086241; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UKObK+AC5cnOXlKUFJTRnyweOq/BU34z8pGGhw+DG7o=; b=hsb2LN79oxtRZ8chgzMGjW9s/G7C8wgDnsw1MkK+zh56rOo7CbxTNAt+ZcMpgkxx5bUfkin1d5s+dTAgBsQ75bOSy+Ftp9dIrIsFr3/3YEPqu1Dpg9kex/Ah3GFDqs1ua2ih09/RuBEdVgEoeirJmcxwNnpjjmBh3+oa6bVB3wU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623086241083772.9945499326849; Mon, 7 Jun 2021 10:17:21 -0700 (PDT) Received: from localhost ([::1]:57568 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqIsK-0006bN-9h for importer@patchew.org; Mon, 07 Jun 2021 13:17:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59698) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIag-0007aG-Sq for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:07 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:43635) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIaG-0007yY-Dz for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:06 -0400 Received: by mail-wm1-x329.google.com with SMTP id 3-20020a05600c0243b029019f2f9b2b8aso53977wmj.2 for ; Mon, 07 Jun 2021 09:58:40 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UKObK+AC5cnOXlKUFJTRnyweOq/BU34z8pGGhw+DG7o=; b=nKDtM0iDMHHQ9Wtdl3RF5d9fdL4DCOMI7b65mPebD0izlxrheqvkcHgdDaQ8Zk4eA7 5Ox8dJbo7Vi7tEeZXyOJbACITYavKu/pqAyG1y/XrR/ed1Ll8NrsOaIH3L2OlginAxWi DwDghPNTSO3M1LlGb7L11Vah5yVyIetBTMx02pGLcxnFM6z81Z4Iked7qjXkNSYnqEg9 8dD4i0J6DqKFbzCkL+VBpEVgmMiYHl56gsYInb44ihLZ6KoNfaZ3T83EhDcCIr1y3FmS eEBEE9eWcUIEI0VLKqj6dOJbMFu38et4jBhEGE/U5xz2MDqnpDrSijVq2b0bpyCMKf64 O8pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UKObK+AC5cnOXlKUFJTRnyweOq/BU34z8pGGhw+DG7o=; b=W7jQIupFID5YQx6eMGqC5GWxAL1tVI8A8OupYT2eWHqrMJ4gsP1A+h4KhZNil7eEZ7 qX3OsuWA2R4gKkwadxCVhhgfBhYG4jbkXVfHQ+SaDKgy4IUOj3W7qSck5u3pYZ7mLCrz O1Rm8qLb3vYvNRarlaqVCzHjI4pKPQXSv2qQuzHe55u9yKOk50/4VTFypIiSaO2WVPz9 3LC/nUIsxJEsmA92v4DYgCwi2NKjNQUzafXZ5wYmvvyqjfT3QgMDPK0nykfEveR+Q9z6 4mFNhdrGLUB/xeQt5uDOv9979QkIJD3/S0oaidtEvycyZg62FyLUR2IlzVkuF1fHUtR+ T+cQ== X-Gm-Message-State: AOAM533oZLTroIXWBW135XvAzl3UThGH3vfz8t2KMuL5N3d6LyYa0Zq/ YpZpdjEzhcfcUFucl4e/tRg64A== X-Google-Smtp-Source: ABdhPJx/CVqwYSVKqZ/Zt0hXdgVq3KWapfkdFA4J+uWFR5Y4a8fc7LZ1dg8+T0dozsVzjXi3fCDebg== X-Received: by 2002:a05:600c:2284:: with SMTP id 4mr17790198wmf.146.1623085119147; Mon, 07 Jun 2021 09:58:39 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 19/55] target/arm: Implement MVE VNEG Date: Mon, 7 Jun 2021 17:57:45 +0100 Message-Id: <20210607165821.9892-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VNEG insn (both integer and floating point forms). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 6 ++++++ target/arm/mve.decode | 2 ++ target/arm/mve_helper.c | 10 ++++++++++ target/arm/translate-mve.c | 15 +++++++++++++++ 4 files changed, 33 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 76508d5dd71..733a54d2e3c 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -55,3 +55,9 @@ DEF_HELPER_FLAGS_3(mve_vabsh, TCG_CALL_NO_WG, void, env, = ptr, ptr) DEF_HELPER_FLAGS_3(mve_vabsw, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vfabsh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vfabss, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_3(mve_vnegb, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vnegh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vnegw, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vfnegh, TCG_CALL_NO_WG, void, env, ptr, ptr) +DEF_HELPER_FLAGS_3(mve_vfnegs, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 66963dc1847..82cc0abcb82 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -80,3 +80,5 @@ VMVN 1111 1111 1 . 11 00 00 ... 0 0101 11 . 0= ... 0 @1op_nosz =20 VABS 1111 1111 1 . 11 .. 01 ... 0 0011 01 . 0 ... 0 @1op VABS_fp 1111 1111 1 . 11 .. 01 ... 0 0111 01 . 0 ... 0 @1op +VNEG 1111 1111 1 . 11 .. 01 ... 0 0011 11 . 0 ... 0 @1op +VNEG_fp 1111 1111 1 . 11 .. 01 ... 0 0111 11 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 2ab05e66dfc..b14826c05a7 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -278,3 +278,13 @@ DO_1OP(vabsw, 4, int32_t, H4, DO_ABS) =20 DO_1OP(vfabsh, 2, uint16_t, H2, DO_FABS) DO_1OP(vfabss, 4, uint32_t, H4, DO_FABS) + +#define DO_NEG(N) (-(N)) +#define DO_FNEG(N) ((N) ^ ~((__typeof(N))-1 >> 1)) + +DO_1OP(vnegb, 1, int8_t, H1, DO_NEG) +DO_1OP(vnegh, 2, int16_t, H2, DO_NEG) +DO_1OP(vnegw, 4, int32_t, H4, DO_NEG) + +DO_1OP(vfnegh, 2, uint16_t, H2, DO_FNEG) +DO_1OP(vfnegs, 4, uint32_t, H4, DO_FNEG) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index badd4da2cbf..086cac9f0cd 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -212,6 +212,7 @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGenO= neOpFn fn) DO_1OP(VCLZ, vclz) DO_1OP(VCLS, vcls) DO_1OP(VABS, vabs) +DO_1OP(VNEG, vneg) =20 static bool trans_VREV16(DisasContext *s, arg_1op *a) { @@ -264,3 +265,17 @@ static bool trans_VABS_fp(DisasContext *s, arg_1op *a) } return do_1op(s, a, fns[a->size]); } + +static bool trans_VNEG_fp(DisasContext *s, arg_1op *a) +{ + MVEGenOneOpFn *fns[] =3D { + NULL, + gen_helper_mve_vfnegh, + gen_helper_mve_vfnegs, + NULL, + }; + if (!dc_isar_feature(aa32_mve_fp, s)) { + return false; + } + return do_1op(s, a, fns[a->size]); +} --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623086582; cv=none; d=zohomail.com; s=zohoarc; b=htDVhL4GtYZU6c4A97edgnR6Oo0h28FOJ3lvVcJnV7GMZME6kezsL+aqnjNwioelO9/GYJJ1+7I5n+/NNsEX8abECZaz15qq8AbxuP2VzPOy+ipSGtitBtUi8ltczvtRbq29XZIt3y0g87wxkzuG0f1ALL6Aqv0whFCV1qWDxCs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623086582; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P1dhj6mrnoek8Fce40UwWHHwtE6XODzzwCB8ycxcBbg=; b=QVfQOlTwm4rA6hD6vAbxVqCtwullJMPeLMd52YnJ+1q4nqatMGRlgNcshmtyaOvrnq MPUcZn3rz1PwFgClPVcLn/dLCdyLfXTa5D8rThB8AdgryFkDkDziCiUDvG9/I2npPLdT hw3ukrLgzkHj2JTO9p8h23BuWulsENniNlKHdsGsvx44EvEghJXoNS/RT8oxhLM1G6m+ HAF90RS84MGhvTFKxh5w4ujgFGUJr1Cdvib63g0JJtKw10AT6Rqek0DijY6J4pxETBeU 1CAuk+noH+Y3dtcxpbESR8r7oPumaRZysVZ0KeLwc6s82TZ0powFvEVjR6WJuYT8kbMb NpMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P1dhj6mrnoek8Fce40UwWHHwtE6XODzzwCB8ycxcBbg=; b=n2hAs35/0jvwLzZwy9m5dz4kv+vTbQ8hkEROT3fhkPkRxtoIGb3yUyLD61ggbmzQ3Z 9QHMUULUZ0tg1IXKhqrb3lGvV6HFlXBpFl3Wz/PdPkIyJzxJjM5Hz9+6KIRHE4PCwTF9 2WOapZCQekX3B48TITINnoeYBcfibSbvFwDuldQXmKwUBKeWv0ABaMH5RZep2lw/qtKA ifV5x4uGIzHEN7EcYDfoJoJYnLJrTB2tOQ30WcjL9r/PMr3VkVyyD8mIreqs1ww4D7h4 w30C8H+EZBRSVehNt1Bw0QQy8MbrclIkUvkW9zj0hyZHyYy3X8SzuLYtqj00gDopxr2N 9j+g== X-Gm-Message-State: AOAM5314VcWBFtFiKVExhGzO5jtqEtkwdivOz7Sr0cXkYTdZQH9ylaNR RI/JDwW5CSEr5ZI8INfXxohjUw== X-Google-Smtp-Source: ABdhPJxnA8oe0t4M3sFBu6zaafwnZ+bHp8KEgK9upsDRcdyKw6gJsjI2IZAExF1NVs3catY0DfpiZg== X-Received: by 2002:a1c:ed10:: with SMTP id l16mr102405wmh.8.1623085119905; Mon, 07 Jun 2021 09:58:39 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 20/55] target/arm: Implement MVE VDUP Date: Mon, 7 Jun 2021 17:57:46 +0100 Message-Id: <20210607165821.9892-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VDUP insn, which duplicates a value from a general-purpose register into every lane of a vector register (subject to predication). Signed-off-by: Peter Maydell --- target/arm/helper-mve.h | 4 ++++ target/arm/mve.decode | 10 +++++++++ target/arm/mve_helper.c | 18 ++++++++++++++++ target/arm/translate-mve.c | 43 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 75 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 733a54d2e3c..ece9c481367 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -33,6 +33,10 @@ DEF_HELPER_FLAGS_3(mve_vstrb_h, TCG_CALL_NO_WG, void, en= v, ptr, i32) DEF_HELPER_FLAGS_3(mve_vstrb_w, TCG_CALL_NO_WG, void, env, ptr, i32) DEF_HELPER_FLAGS_3(mve_vstrh_w, TCG_CALL_NO_WG, void, env, ptr, i32) =20 +DEF_HELPER_FLAGS_3(mve_vdupb, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vduph, TCG_CALL_NO_WG, void, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vdupw, TCG_CALL_NO_WG, void, env, ptr, i32) + DEF_HELPER_FLAGS_3(mve_vclsb, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vclsh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vclsw, TCG_CALL_NO_WG, void, env, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 82cc0abcb82..09849917f5a 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -21,6 +21,7 @@ =20 %qd 22:1 13:3 %qm 5:1 1:3 +%qn 7:1 17:3 =20 &vldr_vstr rn qd imm p a w size l u &1op qd qm size @@ -82,3 +83,12 @@ VABS 1111 1111 1 . 11 .. 01 ... 0 0011 01 . = 0 ... 0 @1op VABS_fp 1111 1111 1 . 11 .. 01 ... 0 0111 01 . 0 ... 0 @1op VNEG 1111 1111 1 . 11 .. 01 ... 0 0011 11 . 0 ... 0 @1op VNEG_fp 1111 1111 1 . 11 .. 01 ... 0 0111 11 . 0 ... 0 @1op + +&vdup qd rt size +# Qd is in the fields usually named Qn +@vdup .... .... . . .. ... . rt:4 .... . . . . .... qd=3D%qn &v= dup + +# B and E bits encode size, which we decode here to the usual size values +VDUP 1110 1110 1 1 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size= =3D0 +VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 1 1 0000 @vdup size= =3D1 +VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size= =3D2 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index b14826c05a7..a5ed4e01e33 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -229,6 +229,24 @@ static uint64_t mask_to_bytemask8(uint16_t mask) ((uint64_t)mask_to_bytemask4(mask >> 4) << 32); } =20 +#define DO_VDUP(OP, ESIZE, TYPE, H) \ + void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t val) \ + { \ + TYPE *d =3D vd; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + uint64_t bytemask =3D mask_to_bytemask##ESIZE(mask); \ + d[H(e)] &=3D ~bytemask; \ + d[H(e)] |=3D (val & bytemask); \ + } \ + mve_advance_vpt(env); \ + } + +DO_VDUP(vdupb, 1, uint8_t, H1) +DO_VDUP(vduph, 2, uint16_t, H2) +DO_VDUP(vdupw, 4, uint32_t, H4) + #define DO_1OP(OP, ESIZE, TYPE, H, FN) \ void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ { \ diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 086cac9f0cd..b4fc4054fe1 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -169,6 +169,49 @@ DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vst= rb_h) DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w) DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w) =20 +static bool trans_VDUP(DisasContext *s, arg_VDUP *a) +{ + TCGv_ptr qd; + TCGv_i32 rt; + + if (!dc_isar_feature(aa32_mve, s)) { + return false; + } + if (a->qd > 7) { + return false; + } + if (a->rt =3D=3D 13 || a->rt =3D=3D 15) { + /* UNPREDICTABLE; we choose to UNDEF */ + return false; + } + if (!mve_eci_check(s)) { + return true; + } + if (!vfp_access_check(s)) { + return true; + } + + qd =3D mve_qreg_ptr(a->qd); + rt =3D load_reg(s, a->rt); + switch (a->size) { + case 0: + gen_helper_mve_vdupb(cpu_env, qd, rt); + break; + case 1: + gen_helper_mve_vduph(cpu_env, qd, rt); + break; + case 2: + gen_helper_mve_vdupw(cpu_env, qd, rt); + break; + default: + g_assert_not_reached(); + } + tcg_temp_free_ptr(qd); + tcg_temp_free_i32(rt); + mve_update_eci(s); + return true; +} + static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) { TCGv_ptr qd, qm; --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9rdP9+7JlYEzrxLr9eGsR6KrxjEDczbLT9FYDCtT1so=; b=XmLZzoQELFuox6ArF7gy+F0Q/p0LW8EkD78YLbPPXfumchL4qBJ4udyhuRnHSpKWK/ ve+u7esFsOTX4AZ4O4D/GW7MkCWh1vT4IAg87tobidzcqHTlHWzPGXHV6QsWQpjNUYar C7KSdJQD2Lpj21Jy33jKbMtSlHW3UwzsrAZEFQh6y5EWJOlayF9NSVSMHGcXmclLgutD wVKCljiIi8Biv24X5UruDVHJ5Zddu5hHuHaLnDBXKrfLiltnM6k6+dTiscEstigQs19R hlGDFYkvU0XwJYQPOJFXVjvg+grCcvq+MLg9ZlDvS9OfXKmSiVw96A8NvIzVDc2g5ULs o4ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9rdP9+7JlYEzrxLr9eGsR6KrxjEDczbLT9FYDCtT1so=; b=i8CI8WvBXZXZ8vrrQEOm+Jw6oET/fFlhHLdU0HKKgKZkQEnd053l8l2g9sqfeVxNFY 965DnKBU6Qk/7yXQfKBtOWDlEVGlnOnDfZbdh3g/kls06r7dYiuP9Muz7rJnaIQ0mSu/ oi6io9Xie2/o8i6aAjgtQmDZyt0qsxAl2iozF5Fv/JAgtmVWAFDGsPKdlppnG1m7IAjo DYXt2Iu9kGaYX65EwMMrUn7HUhrIHMN61udHNSo9SdG4FfzWMZ0rZcEKbrUGCjiUeQ/1 ElErm4Psmzgj97/wKN93ENKnHDiRivxBPkt6e/tCltQtGld7bQlxeDD1SryLsnIbv9OP PJsg== X-Gm-Message-State: AOAM531psDC3zdorjp5cgmU1uqd+a/aVohDZY2Jovyd96WJj4V018y7i jI/IRs6iiwKqu3Ab7vKIfkHQHA== X-Google-Smtp-Source: ABdhPJzUZOjTbehyfAIrldpUcl87Gpg1vKLRbnJ7R6Q+COA2LEE/ezFBkety5z8qGPtnFICvP4veoQ== X-Received: by 2002:a7b:cf18:: with SMTP id l24mr73613wmg.160.1623085120671; Mon, 07 Jun 2021 09:58:40 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 21/55] target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR Date: Mon, 7 Jun 2021 17:57:47 +0100 Message-Id: <20210607165821.9892-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE vector logical operations operating on two registers. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 6 ++++++ target/arm/mve.decode | 9 +++++++++ target/arm/mve_helper.c | 28 ++++++++++++++++++++++++++ target/arm/translate-mve.c | 41 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 84 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index ece9c481367..ad09170c9cf 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -65,3 +65,9 @@ DEF_HELPER_FLAGS_3(mve_vnegh, TCG_CALL_NO_WG, void, env, = ptr, ptr) DEF_HELPER_FLAGS_3(mve_vnegw, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vfnegh, TCG_CALL_NO_WG, void, env, ptr, ptr) DEF_HELPER_FLAGS_3(mve_vfnegs, TCG_CALL_NO_WG, void, env, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vand, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vbic, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vorr, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vorn, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_veor, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 09849917f5a..332e0b8d1d6 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -25,6 +25,7 @@ =20 &vldr_vstr rn qd imm p a w size l u &1op qd qm size +&2op qd qm qn size =20 @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=3D%qd u= =3D0 # Note that both Rn and Qd are 3 bits only (no D bit) @@ -32,6 +33,7 @@ =20 @1op .... .... .... size:2 .. .... .... .... .... &1op qd=3D%qd qm=3D%qm @1op_nosz .... .... .... .... .... .... .... .... &1op qd=3D%qd qm=3D%qm s= ize=3D0 +@2op_nosz .... .... .... .... .... .... .... .... &2op qd=3D%qd qm=3D%qm q= n=3D%qn size=3D0 =20 # Vector loads and stores =20 @@ -68,6 +70,13 @@ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111101 .= ...... @vldr_vstr \ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vst= r \ size=3D2 p=3D1 =20 +# Vector 2-op +VAND 1110 1111 0 . 00 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz +VBIC 1110 1111 0 . 01 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz +VORR 1110 1111 0 . 10 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz +VORN 1110 1111 0 . 11 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz +VEOR 1111 1111 0 . 00 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz + # Vector miscellaneous =20 VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index a5ed4e01e33..6b3d4dbf2da 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -306,3 +306,31 @@ DO_1OP(vnegw, 4, int32_t, H4, DO_NEG) =20 DO_1OP(vfnegh, 2, uint16_t, H2, DO_FNEG) DO_1OP(vfnegs, 4, uint32_t, H4, DO_FNEG) + +#define DO_2OP(OP, ESIZE, TYPE, H, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, \ + void *vd, void *vn, void *vm) \ + { \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + TYPE r =3D FN(n[H(e)], m[H(e)]); \ + uint64_t bytemask =3D mask_to_bytemask##ESIZE(mask); \ + d[H(e)] &=3D ~bytemask; \ + d[H(e)] |=3D (r & bytemask); \ + } \ + mve_advance_vpt(env); \ + } + +#define DO_AND(N, M) ((N) & (M)) +#define DO_BIC(N, M) ((N) & ~(M)) +#define DO_ORR(N, M) ((N) | (M)) +#define DO_ORN(N, M) ((N) | ~(M)) +#define DO_EOR(N, M) ((N) ^ (M)) + +DO_2OP(vand, 1, uint8_t, H1, DO_AND) +DO_2OP(vbic, 1, uint8_t, H1, DO_BIC) +DO_2OP(vorr, 1, uint8_t, H1, DO_ORR) +DO_2OP(vorn, 1, uint8_t, H1, DO_ORN) +DO_2OP(veor, 1, uint8_t, H1, DO_EOR) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index b4fc4054fe1..0e0fa252364 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -30,6 +30,7 @@ =20 typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); +typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); =20 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) = */ static inline long mve_qreg_offset(unsigned reg) @@ -322,3 +323,43 @@ static bool trans_VNEG_fp(DisasContext *s, arg_1op *a) } return do_1op(s, a, fns[a->size]); } + +static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn) +{ + TCGv_ptr qd, qn, qm; + + if (!dc_isar_feature(aa32_mve, s)) { + return false; + } + if (a->qd > 7 || a->qn > 7 || a->qm > 7 || !fn) { + return false; + } + if (!mve_eci_check(s)) { + return true; + } + if (!vfp_access_check(s)) { + return true; + } + + qd =3D mve_qreg_ptr(a->qd); + qn =3D mve_qreg_ptr(a->qn); + qm =3D mve_qreg_ptr(a->qm); + fn(cpu_env, qd, qn, qm); + tcg_temp_free_ptr(qd); + tcg_temp_free_ptr(qn); + tcg_temp_free_ptr(qm); + mve_update_eci(s); + return true; +} + +#define DO_LOGIC(INSN, HELPER) \ + static bool trans_##INSN(DisasContext *s, arg_2op *a) \ + { \ + return do_2op(s, a, HELPER); \ + } + +DO_LOGIC(VAND, gen_helper_mve_vand) +DO_LOGIC(VBIC, gen_helper_mve_vbic) +DO_LOGIC(VORR, gen_helper_mve_vorr) +DO_LOGIC(VORN, gen_helper_mve_vorn) +DO_LOGIC(VEOR, gen_helper_mve_veor) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v6w6D3n71RpoUYab/m0xGRbMyYPeb8rynJ5A3BjU3ls=; b=EsEkyYC7Ayih1klwF1CkLCtrmCF7DH00AqEtcgitdJ1pHv5hqNGE5MVwlwOE3zi+oM lOUtBHubeQiAkyW6/BaiYo6tG7/lVZ6l6zVAQmgq0ww/HXzGAWjd551YzYvYczCJJy+N IYNljMbn+D0N6aLRncLdW5x3gu7VyBq97P0RFqRf3Aa2gPMnziRHaRZhDfUIvgJ+U3v/ dHUP0MAMv3mNnIC3ermJC/LRV79qy8fQmZdYBVbbyEBeL9zeZWAyP/G1Mbe3uxVh69zA G9zdPV974BRdTrfXKxR3OkU83zPD6rEbtjSG0ledb7dyTw2U1/hFG9JcQ7dbyQTNtnwv sRbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v6w6D3n71RpoUYab/m0xGRbMyYPeb8rynJ5A3BjU3ls=; b=tesMd2KJVbUJQ+DetljlzwVjcb2+G5BvQke1X/dkFdNL5mzcFG7LLCNjdbeF8xrqtB 0uGRytqo3CpNK2HNckXzz5V4WTPqT76S8H9lJ/bWgCbpD7fd1u2E2YMsEcT93mfOVBop GHnl3vTGGJDTRPxpOeAwq+Cg6GcL+w5Tp1VJvrDzDzoxyiaBK1TdX/0kzmRW3G8thD6h 1uGhIQFQjwkd9CbmCOBX2l3ZFhjgJF7RFQymZhiykuVK/imN/j//wai+A7Nv+Xdv9vBg 2kdXXDRU9P3z7jJCL+FVne+nUq/y/JJzvrpz+W0G6Q9KCOiwPGGRfNpSUDSIXJwpz9xj 8h3A== X-Gm-Message-State: AOAM532S5gNKSuG0Jy7/3ZpvYDVeIL1IdPZaB1xoIxYcTXYEJxZoZMje guO2/PHUT6izzWjRQrmfTqfQ/A== X-Google-Smtp-Source: ABdhPJxpR4Jk7zg598YFP7sQiMEyz7gtLNo5eRci2f/PpFnIIwLm83esk73lL/plUJk6caolOQDp2A== X-Received: by 2002:adf:cd82:: with SMTP id q2mr11678942wrj.258.1623085121510; Mon, 07 Jun 2021 09:58:41 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 22/55] target/arm: Implement MVE VADD, VSUB, VMUL Date: Mon, 7 Jun 2021 17:57:48 +0100 Message-Id: <20210607165821.9892-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VADD, VSUB and VMUL insns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 12 ++++++++++++ target/arm/mve.decode | 5 +++++ target/arm/mve_helper.c | 14 ++++++++++++++ target/arm/translate-mve.c | 16 ++++++++++++++++ 4 files changed, 47 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index ad09170c9cf..b7e9af2461e 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -71,3 +71,15 @@ DEF_HELPER_FLAGS_4(mve_vbic, TCG_CALL_NO_WG, void, env, = ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vorr, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vorn, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_veor, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vaddb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vaddh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vaddw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vsubb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vsubh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vsubw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vmulb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmulh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmulw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 332e0b8d1d6..f7d1d303f17 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -33,6 +33,7 @@ =20 @1op .... .... .... size:2 .. .... .... .... .... &1op qd=3D%qd qm=3D%qm @1op_nosz .... .... .... .... .... .... .... .... &1op qd=3D%qd qm=3D%qm s= ize=3D0 +@2op .... .... .. size:2 .... .... .... .... .... &2op qd=3D%qd qm=3D%qm q= n=3D%qn @2op_nosz .... .... .... .... .... .... .... .... &2op qd=3D%qd qm=3D%qm q= n=3D%qn size=3D0 =20 # Vector loads and stores @@ -77,6 +78,10 @@ VORR 1110 1111 0 . 10 ... 0 ... 0 0001 . 1 .= 1 ... 0 @2op_nosz VORN 1110 1111 0 . 11 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz VEOR 1111 1111 0 . 00 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz =20 +VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op +VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op +VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op + # Vector miscellaneous =20 VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 6b3d4dbf2da..39ab684c0c3 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -323,6 +323,12 @@ DO_1OP(vfnegs, 4, uint32_t, H4, DO_FNEG) mve_advance_vpt(env); \ } =20 +/* provide unsigned 2-op helpers for all sizes */ +#define DO_2OP_U(OP, FN) \ + DO_2OP(OP##b, 1, uint8_t, H1, FN) \ + DO_2OP(OP##h, 2, uint16_t, H2, FN) \ + DO_2OP(OP##w, 4, uint32_t, H4, FN) + #define DO_AND(N, M) ((N) & (M)) #define DO_BIC(N, M) ((N) & ~(M)) #define DO_ORR(N, M) ((N) | (M)) @@ -334,3 +340,11 @@ DO_2OP(vbic, 1, uint8_t, H1, DO_BIC) DO_2OP(vorr, 1, uint8_t, H1, DO_ORR) DO_2OP(vorn, 1, uint8_t, H1, DO_ORN) DO_2OP(veor, 1, uint8_t, H1, DO_EOR) + +#define DO_ADD(N, M) ((N) + (M)) +#define DO_SUB(N, M) ((N) - (M)) +#define DO_MUL(N, M) ((N) * (M)) + +DO_2OP_U(vadd, DO_ADD) +DO_2OP_U(vsub, DO_SUB) +DO_2OP_U(vmul, DO_MUL) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 0e0fa252364..1b2c8cd5ff7 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -363,3 +363,19 @@ DO_LOGIC(VBIC, gen_helper_mve_vbic) DO_LOGIC(VORR, gen_helper_mve_vorr) DO_LOGIC(VORN, gen_helper_mve_vorn) DO_LOGIC(VEOR, gen_helper_mve_veor) + +#define DO_2OP(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_2op *a) \ + { \ + MVEGenTwoOpFn *fns[] =3D { \ + gen_helper_mve_##FN##b, \ + gen_helper_mve_##FN##h, \ + gen_helper_mve_##FN##w, \ + NULL, \ + }; \ + return do_2op(s, a, fns[a->size]); \ + } + +DO_2OP(VADD, vadd) +DO_2OP(VSUB, vsub) +DO_2OP(VMUL, vmul) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623086007; cv=none; d=zohomail.com; s=zohoarc; b=gCDAIU2yfwQAtvKxTi4njXsgKbdve5zx3g02eFzUAqWl06yk2zKdU0dDcV1GEU/x3K5Mb1EA3239ugefqC7sXzk43E/FpGP2E/iZ2CVMMFJb+xkJ9StB8U9NhBv+3Z9cytJMWALYONbeFSG1YtD49W3H29uKu7wozw5A9mqjR4M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623086007; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Xwwgs1VhJ5RkuyQYCzmhNdM2vmJ3pzIoFzlXTB6yBCY=; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Xwwgs1VhJ5RkuyQYCzmhNdM2vmJ3pzIoFzlXTB6yBCY=; b=PU0NJv8O6iL49QbGc99d+NiIO9nZZwMi2J0WynTbPEPPt/z5zAQbQGnjaLxSpzc6o1 bf73ccqZ4ZHEU+jRT0Z9+TAKJUgMOKuJf0gvL8/tXWiZrNJB48Klmh2T0Lcm91SFPEvv zv8groHBmXgDCR42wXWUooFSjZ0Jxs/fDgsYopPUbmd72jES+sxSeWsbF6IOsIo3ZzA6 YHBtplDjJe3ps6vtgd7+F/bKSDTpHWXNBMrnoXa6/QXoCB1JLSirsnRaYD+WHSzgdSCp f8zU7Xja/d7QtTJs6rOvQhwXGlAtR+8bJQ1g7N5udvmN7n4pnjKCsbD5DJyEAOOK83IG Rs2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Xwwgs1VhJ5RkuyQYCzmhNdM2vmJ3pzIoFzlXTB6yBCY=; b=gjszTnz5Y7Ot8ev+tzmWod9P6JGO/PlqPqadLetESSkp6mW5YPxvJAbpcxQIaAboJ5 DUzx0E/7gis+l9SjRnG8Ckqh8HBXeqGY0KK9ZGPp+hbwHq7tnXsfZFytLjBpYM7aO88u +oGhVLD4l49f5QWN5/MH3gmk0XectnLeR66LAPx7hBFE3xGC4tuPtz2nB7LZMo/YSR7c arIN7ElZrTbjjwwL/Dz5vB0lThX5slOU1slrMna1ioe7xM82MhHxVY5AQxL/VPOt6sm4 2OVcG+itYKi3+Qy8cU3nxmrc6l1Vczz+vBBmJIpdXmGua6XmSxzqz+EbHVq5f0Y2OwEj YvQA== X-Gm-Message-State: AOAM533YvpixCQfXHToCv13wAjWFeujCA8AVuwX+FFywhRDzJhrTW+CN WKpYxwh6XYHkt8LUhhCtVMSS7Q== X-Google-Smtp-Source: ABdhPJw1wEeNB3r7fJ9LxE3cHlLQ1YshfMr7V64LcEfETg49y6jYZEItxFTGsWxCzFMbFft4H7Z9OQ== X-Received: by 2002:a05:600c:190c:: with SMTP id j12mr18270629wmq.42.1623085122199; Mon, 07 Jun 2021 09:58:42 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 23/55] target/arm: Implement MVE VMULH Date: Mon, 7 Jun 2021 17:57:49 +0100 Message-Id: <20210607165821.9892-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VMULH insn, which performs a vector multiply and returns the high half of the result. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 7 +++++++ target/arm/mve.decode | 3 +++ target/arm/mve_helper.c | 26 ++++++++++++++++++++++++++ target/arm/translate-mve.c | 2 ++ 4 files changed, 38 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index b7e9af2461e..17219df3159 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -83,3 +83,10 @@ DEF_HELPER_FLAGS_4(mve_vsubw, TCG_CALL_NO_WG, void, env,= ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vmulb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vmulh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vmulw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vmulhsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmulhsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmulhsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmulhub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmulhuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmulhuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index f7d1d303f17..ca4c27209da 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -82,6 +82,9 @@ VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . = 0 ... 0 @2op VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op =20 +VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op +VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op + # Vector miscellaneous =20 VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 39ab684c0c3..45b1b121ce6 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -348,3 +348,29 @@ DO_2OP(veor, 1, uint8_t, H1, DO_EOR) DO_2OP_U(vadd, DO_ADD) DO_2OP_U(vsub, DO_SUB) DO_2OP_U(vmul, DO_MUL) + +/* + * Because the computation type is at least twice as large as required, + * these work for both signed and unsigned source types. + */ +static inline uint8_t do_mulh_b(int32_t n, int32_t m) +{ + return (n * m) >> 8; +} + +static inline uint16_t do_mulh_h(int32_t n, int32_t m) +{ + return (n * m) >> 16; +} + +static inline uint32_t do_mulh_w(int64_t n, int64_t m) +{ + return (n * m) >> 32; +} + +DO_2OP(vmulhsb, 1, int8_t, H1, do_mulh_b) +DO_2OP(vmulhsh, 2, int16_t, H2, do_mulh_h) +DO_2OP(vmulhsw, 4, int32_t, H4, do_mulh_w) +DO_2OP(vmulhub, 1, uint8_t, H1, do_mulh_b) +DO_2OP(vmulhuh, 2, uint16_t, H2, do_mulh_h) +DO_2OP(vmulhuw, 4, uint32_t, H4, do_mulh_w) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 1b2c8cd5ff7..edea30ba1d7 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -379,3 +379,5 @@ DO_LOGIC(VEOR, gen_helper_mve_veor) DO_2OP(VADD, vadd) DO_2OP(VSUB, vsub) DO_2OP(VMUL, vmul) +DO_2OP(VMULH_S, vmulhs) +DO_2OP(VMULH_U, vmulhu) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xM1/IljcmeixGn7/ya3GpB0ZkMzTXbAaR9fyni5YxU4=; b=QxOhZDGNlJu69mR/ZAdppK6LVebKgg6rk7YA8BQxLN+nTQI7eqvhdXZRbX0M/G3XEK SCmlRcvND2S56SUWQchIKrmLSdFSnlhIj3NxyaoeIy7I51qslIwyTow0bZPTqtWxto0M RjDs1nsIpwsdj7jH0p9mfw7SpLQZJkR7F9IvRpB+M4fgm9b79iFREGTRhGrhwqupXadh Fy0jHy/WtjHCSkbccYI8zf7yvSwfKdwkNzGUT1n7STavePdmU7V1rE46YfBZRqM++jUe YLmqp2XMPrQrv2ptn4ODavlUIJAXVJwQiV2OUZkPReF9EbtgOYv+d3CR5e5+xewCPDcb DMgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xM1/IljcmeixGn7/ya3GpB0ZkMzTXbAaR9fyni5YxU4=; b=enmDaCjnjz+kCCdD8ayamEjsFX/vrM5kSURgkeKrJziHlN3Jk582NPdL4DqQsBuVJw vJ0gUUFDNlqFCKaVPhF+PBWwIQym6+SV8EMyDLo4tlb1DtMZ7WN+Rg83Fa4Z2IcXJMgq ibNEXOClOI6QNYTHBS1E4LVN9DqDQ25NCaIohKtMu9yYq2/RMB8ZG9GzRM0CVV73CrVw KTB3PzcmKY/C55/RMmArzOiQucyKzmtAn7/xOZuVA89xuIL0gFad6/O6OC/2MvTUkISD zbJtrjRrsPyArwfVnTQ0RMS1TLgv5l01A4DJKDTu6l5xsdJryAa5SC2CfWh/cMw01NRM ZKBw== X-Gm-Message-State: AOAM532lP/cUPiKpM4AMzZTlHMOJ/GUvBaNi3wt2/9nOT1tlvjA25Zrp WHKe6NzK6p432S88YgWhvOYNUp9EfrVU7qtr X-Google-Smtp-Source: ABdhPJz5ScJBcfckq2iTczMuXD1ynDnZzWCupxfLUdpEm1oth7yBZgnr/raK5Hc35YhrYGY6JRZhGA== X-Received: by 2002:a05:600c:1ca2:: with SMTP id k34mr9728310wms.145.1623085122966; Mon, 07 Jun 2021 09:58:42 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 24/55] target/arm: Implement MVE VRMULH Date: Mon, 7 Jun 2021 17:57:50 +0100 Message-Id: <20210607165821.9892-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VRMULH insn, which performs a rounding multiply and then returns the high half. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 7 +++++++ target/arm/mve.decode | 3 +++ target/arm/mve_helper.c | 22 ++++++++++++++++++++++ target/arm/translate-mve.c | 2 ++ 4 files changed, 34 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 17219df3159..38d084429b8 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -90,3 +90,10 @@ DEF_HELPER_FLAGS_4(mve_vmulhsw, TCG_CALL_NO_WG, void, en= v, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vmulhub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vmulhuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vmulhuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vrmulhsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vrmulhsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vrmulhsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vrmulhub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vrmulhuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vrmulhuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index ca4c27209da..4ab6c9dba90 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -85,6 +85,9 @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . = 1 ... 0 @2op VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op =20 +VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op +VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op + # Vector miscellaneous =20 VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 45b1b121ce6..20d96b86f5a 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -368,9 +368,31 @@ static inline uint32_t do_mulh_w(int64_t n, int64_t m) return (n * m) >> 32; } =20 +static inline uint8_t do_rmulh_b(int32_t n, int32_t m) +{ + return (n * m + (1U << 7)) >> 8; +} + +static inline uint16_t do_rmulh_h(int32_t n, int32_t m) +{ + return (n * m + (1U << 15)) >> 16; +} + +static inline uint32_t do_rmulh_w(int64_t n, int64_t m) +{ + return (n * m + (1U << 31)) >> 32; +} + DO_2OP(vmulhsb, 1, int8_t, H1, do_mulh_b) DO_2OP(vmulhsh, 2, int16_t, H2, do_mulh_h) DO_2OP(vmulhsw, 4, int32_t, H4, do_mulh_w) DO_2OP(vmulhub, 1, uint8_t, H1, do_mulh_b) DO_2OP(vmulhuh, 2, uint16_t, H2, do_mulh_h) DO_2OP(vmulhuw, 4, uint32_t, H4, do_mulh_w) + +DO_2OP(vrmulhsb, 1, int8_t, H1, do_rmulh_b) +DO_2OP(vrmulhsh, 2, int16_t, H2, do_rmulh_h) +DO_2OP(vrmulhsw, 4, int32_t, H4, do_rmulh_w) +DO_2OP(vrmulhub, 1, uint8_t, H1, do_rmulh_b) +DO_2OP(vrmulhuh, 2, uint16_t, H2, do_rmulh_h) +DO_2OP(vrmulhuw, 4, uint32_t, H4, do_rmulh_w) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index edea30ba1d7..7e9d852c6ff 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -381,3 +381,5 @@ DO_2OP(VSUB, vsub) DO_2OP(VMUL, vmul) DO_2OP(VMULH_S, vmulhs) DO_2OP(VMULH_U, vmulhu) +DO_2OP(VRMULH_S, vrmulhs) +DO_2OP(VRMULH_U, vrmulhu) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Lmitx3Cr0jgwChXHcEsjI6tKva1OYZOq2ukb+k0uZ1A=; b=O/U0EZM7TpiX0bCY+g2CUvmd1NQWPFhTAdTTJ84lU5Tf+IHNcFICtn0MPI5AMoy4As FHYl2gQ+sbunN4+Z/KrLuxp5uswpDmMSZVJBjU05q2rafdqrlnIwTGXjcVLr5N8nCHYr jGzKM4xoITtNQycoJugvGmgzwNZhWeDBDNxyDmD8KPIqFTjWNRgzSAzbUxqsGScclDYY BrPxPSheXRqXUlTrdpZ0iLMrvVNzBHjXBogN/zM+E9b8U5+JBGtSmfai4WMPxbhzBFqO dQ5qNNBIO3G908F5R4UP2d8dFIHq25E2CjeIcBRf4fjOPZTKScHVkE8JDchUNmPlRgfK btww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Lmitx3Cr0jgwChXHcEsjI6tKva1OYZOq2ukb+k0uZ1A=; b=ie5hvTviO8MyqD0fNcFXNVLD0wmyLNcVwpFvz98y99IuNK7dzoeMg8VoKmULDxXTuF tJteyNEGRmq9itru96Hd/ZLyj4czqggYE3ryDdZs0cc8ockQbuniTe8Q64z+6CJ5Gpkz ke2exh0mAoClv9re2mKB4hxUwCLJVfI4J87fjnkh4THgvZoie/7n2xe1cFuOh9XEyYyo YB1koVsKRDy7lR8FMjuoj+7DblTM5/DdBv2uk9zOdVBrv8R/AZ35JXZuzUjJatJhC0Mw 8Ja9qUhutZYdeVcQwXgRP8sMIdOnv5GXyXW1X9sfBvpyeISvZds9u1BjHgnXN6262B4r SpOg== X-Gm-Message-State: AOAM530lWYrAkWCaAepydcNajuWzR9YbgH0f3+/SB+Li5onG1YXVWlXB EA8Bdb6qdDlO30RNgzLqNAzfwV7GGpE7Q22S X-Google-Smtp-Source: ABdhPJw6A//oogvrern6k5lzoTzLx7fMRxyvc0A+WnKxoorLfUsDQEMCheOGVkLm4dkSPwldSXqnPg== X-Received: by 2002:a5d:6382:: with SMTP id p2mr18888638wru.338.1623085123788; Mon, 07 Jun 2021 09:58:43 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 25/55] target/arm: Implement MVE VMAX, VMIN Date: Mon, 7 Jun 2021 17:57:51 +0100 Message-Id: <20210607165821.9892-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VMAX and VMIN insns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 14 ++++++++++++++ target/arm/mve.decode | 5 +++++ target/arm/mve_helper.c | 14 ++++++++++++++ target/arm/translate-mve.c | 4 ++++ 4 files changed, 37 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 38d084429b8..bc9dcde5dba 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -97,3 +97,17 @@ DEF_HELPER_FLAGS_4(mve_vrmulhsw, TCG_CALL_NO_WG, void, e= nv, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vrmulhub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vrmulhuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vrmulhuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vmaxsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmaxsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmaxsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmaxub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmaxuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmaxuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vminsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vminsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vminsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vminub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vminuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vminuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 4ab6c9dba90..42d5504500c 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -88,6 +88,11 @@ VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 .= 0 ... 1 @2op VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op =20 +VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op +VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op +VMIN_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 1 ... 0 @2op +VMIN_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 1 ... 0 @2op + # Vector miscellaneous =20 VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 20d96b86f5a..f53551c7de5 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -329,6 +329,12 @@ DO_1OP(vfnegs, 4, uint32_t, H4, DO_FNEG) DO_2OP(OP##h, 2, uint16_t, H2, FN) \ DO_2OP(OP##w, 4, uint32_t, H4, FN) =20 +/* provide signed 2-op helpers for all sizes */ +#define DO_2OP_S(OP, FN) \ + DO_2OP(OP##b, 1, int8_t, H1, FN) \ + DO_2OP(OP##h, 2, int16_t, H2, FN) \ + DO_2OP(OP##w, 4, int32_t, H4, FN) + #define DO_AND(N, M) ((N) & (M)) #define DO_BIC(N, M) ((N) & ~(M)) #define DO_ORR(N, M) ((N) | (M)) @@ -396,3 +402,11 @@ DO_2OP(vrmulhsw, 4, int32_t, H4, do_rmulh_w) DO_2OP(vrmulhub, 1, uint8_t, H1, do_rmulh_b) DO_2OP(vrmulhuh, 2, uint16_t, H2, do_rmulh_h) DO_2OP(vrmulhuw, 4, uint32_t, H4, do_rmulh_w) + +#define DO_MAX(N, M) ((N) >=3D (M) ? (N) : (M)) +#define DO_MIN(N, M) ((N) >=3D (M) ? (M) : (N)) + +DO_2OP_S(vmaxs, DO_MAX) +DO_2OP_U(vmaxu, DO_MAX) +DO_2OP_S(vmins, DO_MIN) +DO_2OP_U(vminu, DO_MIN) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 7e9d852c6ff..c12b0174b82 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -383,3 +383,7 @@ DO_2OP(VMULH_S, vmulhs) DO_2OP(VMULH_U, vmulhu) DO_2OP(VRMULH_S, vrmulhs) DO_2OP(VRMULH_U, vrmulhu) +DO_2OP(VMAX_S, vmaxs) +DO_2OP(VMAX_U, vmaxu) +DO_2OP(VMIN_S, vmins) +DO_2OP(VMIN_U, vminu) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623086641; cv=none; d=zohomail.com; s=zohoarc; b=BaqjJxLFnsL6SWIY7GFjJgMF3d4cHinCDoJCpMVdXDbCO7bXlpH/VKNC49DQyis21y8ht1GKUcq1AUNDKOZJXV9G+u0h9OVJ7mVKV0WKSsf4pg6dFAS6fCxzVZkZISsDlw1xACNtm6Ep+nhuopx/i5v86bAiVE3s3iHW6kRw6Uo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623086641; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WttECluiQs8PiWTuhXDPR0B557G5Nz9drpIG9WwzYtA=; b=KRe8l6nTXdinsv/FiycNxQfV2JM3hPXEeVy5nZ807IoQkA7RgzxGtmoXYfXqyPULZjoZykDr5vmiD5cHYfBRxaQFS2fEbJJQjhlpFdaf0hQWA3jE65nbauCvysNwilfHrrGLD1MchQ7/n2OimtJqmEcPEBWGAHvO/RbGGpAZO/Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162308664101175.77594988073258; Mon, 7 Jun 2021 10:24:01 -0700 (PDT) Received: from localhost ([::1]:48078 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqIyl-0002WS-QX for importer@patchew.org; Mon, 07 Jun 2021 13:23:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59876) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIaw-0007ig-BX for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:22 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:42857) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIaR-0007zn-Qe for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:22 -0400 Received: by mail-wr1-x42b.google.com with SMTP id c5so18397531wrq.9 for ; Mon, 07 Jun 2021 09:58:45 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WttECluiQs8PiWTuhXDPR0B557G5Nz9drpIG9WwzYtA=; b=FTruKnZsF7qHB7367HBbzjV6fBJhdMkK9o1Q7SUNLDLvakQuuamnVIH1YK9f+OEqi3 vJGXJx2d4TD0IViborbMQnWrXv405KaidA2R/lreHj+nhyoqHL3Kf3LZGyserTXBW70w cJsBmQRqMu0GCfiPmxvT1mAGzWfq5Mp/ST6oeJnylSHvV+eUPI7VvcnpB2wUB6gQuvc+ 1diOMfxKsRHz8ZOs7/Nonmsxd9pRarL4w9wwuUTx1+0K5tE9c+oQja86NfCXDebpAwOM Ea/weMkTzJU0YWLNOSCJJGG1F6vnhkwFNR3yrU4LeWfr/+4IrXh1kcZF0sM3MGn5q47F 5o5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WttECluiQs8PiWTuhXDPR0B557G5Nz9drpIG9WwzYtA=; b=X3ntA6huXW3siNtox6OIySLCXP2o975gFqxcBXLgTid3TsqBdLM8qDyFJ/j+uX8PDb nLlZV68jM3VMmj+HGUeLpCRpJiAWVXn4wih0nCHqV/AuRREnNFmhc+zWI67zxFu+AYXV 58oApHbmOtasW5vcgxL4Pfpw22e4jxFzrwD6B9Cj9u+0vAPcp2qUAxiT8LZR0S92X2dm l3xmGyJBfX8b8WkBgz2bzL3P69eiWFvOhDBCTNaOwR8dLJ5Eca9LFL6m7prCMhE/C39x Efr/oVIyUFQXy7kI29RxXF7wzyq3wvEPxw8MbshUM+GFI/q24qVeyoGLBOgS4oB/tRXf CU/w== X-Gm-Message-State: AOAM531VKtv6QRRY0mcjDJeH9xdicFsCrb6ZGmG9XZQEtNsoqyy2l/S2 QoYqelutI/5Lh5F5gLbpLJ1W+A== X-Google-Smtp-Source: ABdhPJydfRYx+L0uY8UPiUhsdT7+tr4YT3VBbV1VVfIoDuIJRXfafZeMU6yRpHLMl2PgDCW0FdYmdg== X-Received: by 2002:a5d:504d:: with SMTP id h13mr18081765wrt.133.1623085124610; Mon, 07 Jun 2021 09:58:44 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 26/55] target/arm: Implement MVE VABD Date: Mon, 7 Jun 2021 17:57:52 +0100 Message-Id: <20210607165821.9892-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VABD insn. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 7 +++++++ target/arm/mve.decode | 3 +++ target/arm/mve_helper.c | 5 +++++ target/arm/translate-mve.c | 2 ++ 4 files changed, 17 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index bc9dcde5dba..bfe2057592f 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -111,3 +111,10 @@ DEF_HELPER_FLAGS_4(mve_vminsw, TCG_CALL_NO_WG, void, e= nv, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vminub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vminuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vminuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vabdsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vabdsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vabdsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vabdub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vabduh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vabduw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 42d5504500c..087d3db2a31 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -93,6 +93,9 @@ VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 .= 0 ... 0 @2op VMIN_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 1 ... 0 @2op VMIN_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 1 ... 0 @2op =20 +VABD_S 111 0 1111 0 . .. ... 0 ... 0 0111 . 1 . 0 ... 0 @2op +VABD_U 111 1 1111 0 . .. ... 0 ... 0 0111 . 1 . 0 ... 0 @2op + # Vector miscellaneous =20 VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index f53551c7de5..f026a9969d6 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -410,3 +410,8 @@ DO_2OP_S(vmaxs, DO_MAX) DO_2OP_U(vmaxu, DO_MAX) DO_2OP_S(vmins, DO_MIN) DO_2OP_U(vminu, DO_MIN) + +#define DO_ABD(N, M) ((N) >=3D (M) ? (N) - (M) : (M) - (N)) + +DO_2OP_S(vabds, DO_ABD) +DO_2OP_U(vabdu, DO_ABD) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index c12b0174b82..a732612a86f 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -387,3 +387,5 @@ DO_2OP(VMAX_S, vmaxs) DO_2OP(VMAX_U, vmaxu) DO_2OP(VMIN_S, vmins) DO_2OP(VMIN_U, vminu) +DO_2OP(VABD_S, vabds) +DO_2OP(VABD_U, vabdu) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623086618; cv=none; d=zohomail.com; s=zohoarc; b=ckMPXtt8Kd/SEmh0eHfjvQ7gy67bkdnJLZC+MxFCGgF9gSwscPeXL9nbIYIG0tjhRI0yjpE75GtKsiVTAoxhSBFXszS50jCETF2us6wuHovJHP1dBCAl0DIdIHS5ErgWz6qIvS3wN73Ukcub+JYhBJPwVRDlIlhlxDSF8/akW3Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623086618; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CNvU9z65691m9PWY2OvQX5jqP+5ASM9qcKv6+gK5fnE=; b=N4Xh87GRFtHgZ3HnZHFumvA8wYYGX0f+/AbgWvg426zO5m3muXrpEvqB+FgJgJ8oH8jDBb+veOpLG+nyo/FI5OkdDFJQde5KW4bEm26UyLxjxTuDzybAZobXQP1VboREuVkqxcRN2alGVX3Sn0dRvVDZGtLXf8TbzrSBXqPXUW0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623086618248567.7770030041314; Mon, 7 Jun 2021 10:23:38 -0700 (PDT) Received: from localhost ([::1]:46812 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqIyI-0001eQ-VX for importer@patchew.org; Mon, 07 Jun 2021 13:23:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60110) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIb9-00084L-0e for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:35 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:45814) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIaX-0007zz-TG for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:34 -0400 Received: by mail-wr1-x42b.google.com with SMTP id z8so18395631wrp.12 for ; Mon, 07 Jun 2021 09:58:46 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CNvU9z65691m9PWY2OvQX5jqP+5ASM9qcKv6+gK5fnE=; b=hIEpDHZQJTr1nN5X+qBvvlsqz5gFhQEt4wtSsZwd6OtoUwWAbu8DLyNnEtFxj8rAPK I4CScxlfWIc1u1zN6qIz/SOZ+C1uXsrgDlby7xAvXr0kFC1HJwtnChj//u8tX3YWgqA9 wntQwk8VBxxjU8k4YoVM614OWyt6QqRI7La7YX95JtOn2pLflIzLxMzUt4Zk5SVPdokw bjzZs2Al7d08Y+hWegUbXOYGYlsp9fYr0+YTI+/AtO2nXP4/PD6uuCZccmMGSGCiv2Lz D9iZVefuPoP7Y8Xpw2ac9BUyY/S2YEa0mFGrooqgAaakmx+W/OUMOfVP2kwPIZkOepym nD6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CNvU9z65691m9PWY2OvQX5jqP+5ASM9qcKv6+gK5fnE=; b=YZhPJGmhhtNHl5UHgjfXnvWer981ENKpGY3yv46gKGk24FLzYbBWi8HotiyoxrNjK4 Wws9oj+I04sAD72litBbRpA3g243WzcSiIZA7SLxSf+m/aiV1IqnLQ9WiGvjbyA1ZlIa m6s0Zwn7i16uLErscBBUYoUgQk7IZhsimKFHVffTfioxPHuDIWLqtiwcjnKjwMy0T/UG 63KSdJLzUG5eMU6T/zpdpaYya/6XPDQdjh5NXuSWmCfbvdOY/8NFbgWgR7sYfl3whpU6 qZZRi6P4SlNCihFgAgjODUB4Fnq7ROA81GyLlI87GZx74xoDY3unDPoVvQ3VHseo878q /tBg== X-Gm-Message-State: AOAM533v/0WxH8b9y/hWKLQbHHEq0jrmv8aZdIyPajrzqzOwbtzNcgTa wkPd8stdfuDj7gnzprfcdYy/0A== X-Google-Smtp-Source: ABdhPJxn1F+s2S4RgE3BHcpZWjQophKA9K7E0RSGzX7uOTmwejH22sNmXO2NuTGC5MUf0O60QTHW1Q== X-Received: by 2002:a5d:64a5:: with SMTP id m5mr17668999wrp.182.1623085125395; Mon, 07 Jun 2021 09:58:45 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 27/55] target/arm: Implement MVE VHADD, VHSUB Date: Mon, 7 Jun 2021 17:57:53 +0100 Message-Id: <20210607165821.9892-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement MVE VHADD and VHSUB insns, which perform an addition or subtraction and then halve the result. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 14 ++++++++++++++ target/arm/mve.decode | 5 +++++ target/arm/mve_helper.c | 25 +++++++++++++++++++++++++ target/arm/translate-mve.c | 4 ++++ 4 files changed, 48 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index bfe2057592f..7b22990c3ba 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -118,3 +118,17 @@ DEF_HELPER_FLAGS_4(mve_vabdsw, TCG_CALL_NO_WG, void, e= nv, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vabdub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vabduh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vabduw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vhaddsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vhaddsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vhaddsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vhaddub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vhadduh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vhadduw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vhsubsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vhsubsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vhsubsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vhsubub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vhsubuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vhsubuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 087d3db2a31..241d1c44c19 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -96,6 +96,11 @@ VMIN_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 = . 1 ... 0 @2op VABD_S 111 0 1111 0 . .. ... 0 ... 0 0111 . 1 . 0 ... 0 @2op VABD_U 111 1 1111 0 . .. ... 0 ... 0 0111 . 1 . 0 ... 0 @2op =20 +VHADD_S 111 0 1111 0 . .. ... 0 ... 0 0000 . 1 . 0 ... 0 @2op +VHADD_U 111 1 1111 0 . .. ... 0 ... 0 0000 . 1 . 0 ... 0 @2op +VHSUB_S 111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op +VHSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op + # Vector miscellaneous =20 VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index f026a9969d6..5982f6bf5eb 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -415,3 +415,28 @@ DO_2OP_U(vminu, DO_MIN) =20 DO_2OP_S(vabds, DO_ABD) DO_2OP_U(vabdu, DO_ABD) + +static inline uint32_t do_vhadd_u(uint32_t n, uint32_t m) +{ + return ((uint64_t)n + m) >> 1; +} + +static inline int32_t do_vhadd_s(int32_t n, int32_t m) +{ + return ((int64_t)n + m) >> 1; +} + +static inline uint32_t do_vhsub_u(uint32_t n, uint32_t m) +{ + return ((uint64_t)n - m) >> 1; +} + +static inline int32_t do_vhsub_s(int32_t n, int32_t m) +{ + return ((int64_t)n - m) >> 1; +} + +DO_2OP_S(vhadds, do_vhadd_s) +DO_2OP_U(vhaddu, do_vhadd_u) +DO_2OP_S(vhsubs, do_vhsub_s) +DO_2OP_U(vhsubu, do_vhsub_u) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index a732612a86f..c22b739f36e 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -389,3 +389,7 @@ DO_2OP(VMIN_S, vmins) DO_2OP(VMIN_U, vminu) DO_2OP(VABD_S, vabds) DO_2OP(VABD_U, vabdu) +DO_2OP(VHADD_S, vhadds) +DO_2OP(VHADD_U, vhaddu) +DO_2OP(VHSUB_S, vhsubs) +DO_2OP(VHSUB_U, vhsubu) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rYQ4/VTW64aDOScj4zmfC/qPGaCb6zVYq6DVXxcIMj0=; b=IdPa92XYm9opfhjrbDAoTAKTYk2OLGvmo02oYMs5OipiUJlNSeGLgUm57JriV+pAju 0/MarxIQ0fp3K25VESwyLR9aySo8fpQNvTnyJxYjGnIhbbIM8Kvk1xc/L2qGR3+cGJN7 OUreKJo2unB3tY/bxldhtq81dz7He5DJV1H4Gjgv9RXnsO06WTGLbHA/tlcnNz1Zh6Y5 dQSCtfyxSleeVJBiyNV12WuvBc4+iQWyenBdwVVMEg2YB/MftMwQDvyVFOxa3Gst3xoC P0eA7VtHeGbZH5KSEwDQqxB77tdekrTVJID8SvIVmw9m/Soj2GNfIPZr0UhHGZBe501H aYEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rYQ4/VTW64aDOScj4zmfC/qPGaCb6zVYq6DVXxcIMj0=; b=E1Up/rfoiKFAK+VZax8QQ7RQ+rlkgfW/Wde3URbbke5WLPO9mLwi+xcWAiDBZDaiz9 JMs92d5YUagHlQk4z3bP6L/CVCd+6ZfsmdQMBe69TGwbzInG90uPy50OA6D1sL6p1MAV pcDGZ4aqfZig6KN3Avw5eRsu6vAsblpcaC5Kt1JX2Oo2tESE7FnKKW6A+d/lDYHFYRq7 b0xe6RoBB6oM2WxwA3LtLna3uoN6T9jBSjyC42cPKjx1Mm3Kz3hKERR6I2H+Hspe8mOW HY0O+1rgtu4gvcqXyWYaLmcpoxcIHvKkTEhKpD/L+Ft5LnzD7IF12biz0oBrVlMfGZku dl4A== X-Gm-Message-State: AOAM5320C5glSvWND5haTCT4l63tmc9yQmKnD7bYnJhihs27zeD+lDVW lwJxPOumKka69AlM+VBYpARCUA== X-Google-Smtp-Source: ABdhPJzRvsII9G6tY3qI0RfIloaNLZTlNy8C8e4vwmZejVZwySMiGsoYn5TSlEeXqdKHxMJBxyqapQ== X-Received: by 2002:a05:6000:1849:: with SMTP id c9mr18485006wri.140.1623085126106; Mon, 07 Jun 2021 09:58:46 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 28/55] target/arm: Implement MVE VMULL Date: Mon, 7 Jun 2021 17:57:54 +0100 Message-Id: <20210607165821.9892-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VMULL insn, which multiplies two single width integer elements to produce a double width result. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 14 ++++++++++++++ target/arm/mve.decode | 5 +++++ target/arm/mve_helper.c | 35 +++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 4 ++++ 4 files changed, 58 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 7b22990c3ba..66d31633cef 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -132,3 +132,17 @@ DEF_HELPER_FLAGS_4(mve_vhsubsw, TCG_CALL_NO_WG, void, = env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vhsubub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vhsubuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vhsubuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vmullbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmullbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmullbsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmullbub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmullbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmullbuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vmulltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmulltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmulltsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmulltub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmulltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vmulltuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 241d1c44c19..5a480d61cd6 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -101,6 +101,11 @@ VHADD_U 111 1 1111 0 . .. ... 0 ... 0 0000 . = 1 . 0 ... 0 @2op VHSUB_S 111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op VHSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op =20 +VMULL_BS 111 0 1110 0 . .. ... 1 ... 0 1110 . 0 . 0 ... 0 @2op +VMULL_BU 111 1 1110 0 . .. ... 1 ... 0 1110 . 0 . 0 ... 0 @2op +VMULL_TS 111 0 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op +VMULL_TU 111 1 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op + # Vector miscellaneous =20 VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 5982f6bf5eb..2d0c6998caa 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -335,6 +335,27 @@ DO_1OP(vfnegs, 4, uint32_t, H4, DO_FNEG) DO_2OP(OP##h, 2, int16_t, H2, FN) \ DO_2OP(OP##w, 4, int32_t, H4, FN) =20 +/* + * "Long" operations where two half-sized inputs (taken from either the + * top or the bottom of the input vector) produce a double-width result. + * Here TYPE and H are for the input, and LESIZE, LTYPE, LH for the output. + */ +#define DO_2OP_L(OP, TOP, TYPE, H, LESIZE, LTYPE, LH, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void= *vm) \ + { \ + LTYPE *d =3D vd; \ + TYPE *n =3D vn, *m =3D vm; = \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned le; \ + for (le =3D 0; le < 16 / LESIZE; le++, mask >>=3D LESIZE) { = \ + LTYPE r =3D FN((LTYPE)n[H(le * 2 + TOP)], m[H(le * 2 + TOP)]);= \ + uint64_t bytemask =3D mask_to_bytemask##LESIZE(mask); \ + d[LH(le)] &=3D ~bytemask; \ + d[LH(le)] |=3D (r & bytemask); \ + } \ + mve_advance_vpt(env); \ + } + #define DO_AND(N, M) ((N) & (M)) #define DO_BIC(N, M) ((N) & ~(M)) #define DO_ORR(N, M) ((N) | (M)) @@ -355,6 +376,20 @@ DO_2OP_U(vadd, DO_ADD) DO_2OP_U(vsub, DO_SUB) DO_2OP_U(vmul, DO_MUL) =20 +DO_2OP_L(vmullbsb, 0, int8_t, H1, 2, int16_t, H2, DO_MUL) +DO_2OP_L(vmullbsh, 0, int16_t, H2, 4, int32_t, H4, DO_MUL) +DO_2OP_L(vmullbsw, 0, int32_t, H4, 8, int64_t, , DO_MUL) +DO_2OP_L(vmullbub, 0, uint8_t, H1, 2, uint16_t, H2, DO_MUL) +DO_2OP_L(vmullbuh, 0, uint16_t, H2, 4, uint32_t, H4, DO_MUL) +DO_2OP_L(vmullbuw, 0, uint32_t, H4, 8, uint64_t, , DO_MUL) + +DO_2OP_L(vmulltsb, 1, int8_t, H1, 2, int16_t, H2, DO_MUL) +DO_2OP_L(vmulltsh, 1, int16_t, H2, 4, int32_t, H4, DO_MUL) +DO_2OP_L(vmulltsw, 1, int32_t, H4, 8, int64_t, , DO_MUL) +DO_2OP_L(vmulltub, 1, uint8_t, H1, 2, uint16_t, H2, DO_MUL) +DO_2OP_L(vmulltuh, 1, uint16_t, H2, 4, uint32_t, H4, DO_MUL) +DO_2OP_L(vmulltuw, 1, uint32_t, H4, 8, uint64_t, , DO_MUL) + /* * Because the computation type is at least twice as large as required, * these work for both signed and unsigned source types. diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index c22b739f36e..ccff7fc0ecf 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -393,3 +393,7 @@ DO_2OP(VHADD_S, vhadds) DO_2OP(VHADD_U, vhaddu) DO_2OP(VHSUB_S, vhsubs) DO_2OP(VHSUB_U, vhsubu) +DO_2OP(VMULL_BS, vmullbs) +DO_2OP(VMULL_BU, vmullbu) +DO_2OP(VMULL_TS, vmullts) +DO_2OP(VMULL_TU, vmulltu) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=s95am2RS5wuKuDufDPVA8xoCCTBnZq6S8YI67WY9T8o=; b=kXrgKgVVM5k5n+hixEgchF7AhXmzWlVK3j6aJbgnqe1xyCd/BNIPyqoC+gx4Rj9f43 10Q4jz42FvkjLlkktOX0PhRhDOlZ+QU+aDntgJjPFYQdp4fJEXQnyWqHqYAq8mRQIVbS YH4G/OAoaeHZoeuhPvo59YryL00SLVvnltfOziqe4NVaUdiX+0ieUxhtRjnCjT0M/R5F yQShXpCHLH9+VjIcF5VNZmjSaWtrHbTiWohi/rOdDDBwL/uuEeEsGNBkqRslgoH/QZOy cn6RIjswzjoILAXF7ann2WOi241vuts1L0caKgdcRY2v8SKTX66BB1+K7vX/1UJqrFVM Vcxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=s95am2RS5wuKuDufDPVA8xoCCTBnZq6S8YI67WY9T8o=; b=FAva+YnALHhMDJaMkiKa9kv91i6e5XJVOFkXt/RU8wz7B0GMjMQxJIiuyojvq1m2Ye 9FQO44oQFVew4Z1YL/ewTNI2nD0mBd14PWWBX93np9L/JdYH3P4LwEuTNQ+qvK96jozR yQxV39LYglkv4gboCCootuDAFnGgC1e5Xk3x6xtilN++9ec0pAJyJPNgi8RF++3fL0Bg a/Uagtb8YY2FsmUNFqaRyiCPn8bP38e9h/KduW37OV1I8DeERtFF5MEFyZ/yieE3MstC ya5eHHAY9pHRmp/nxgv6rqhCjk3plz+LDz60XtyZ2sh4uYEukeUpqqpSTOb67WWjHa3j tcew== X-Gm-Message-State: AOAM532LNa+eSJfSI5c+oBXYBueUCjOJeLgZaq+t2pAYl4oCGV0PQJQD zuEU1xnlQb0r53/KAC7nhXZIxBG0uODj3pL4 X-Google-Smtp-Source: ABdhPJzndyevAyN671Il90xRzKgDw8JclPAm5KjI+mvrqsFdUSPePUD50Tfj0SonoL45cjmcplACTA== X-Received: by 2002:adf:8bc7:: with SMTP id w7mr18995999wra.198.1623085126876; Mon, 07 Jun 2021 09:58:46 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 29/55] target/arm: Implement MVE VMLALDAV Date: Mon, 7 Jun 2021 17:57:55 +0100 Message-Id: <20210607165821.9892-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VMLALDAV insn, which multiplies pairs of integer elements, accumulating them into a 64-bit result in a pair of general-purpose registers. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 8 +++ target/arm/translate.h | 10 ++++ target/arm/mve.decode | 15 ++++++ target/arm/mve_helper.c | 32 ++++++++++++ target/arm/translate-mve.c | 100 +++++++++++++++++++++++++++++++++++++ 5 files changed, 165 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 66d31633cef..1013f6912da 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -146,3 +146,11 @@ DEF_HELPER_FLAGS_4(mve_vmulltsw, TCG_CALL_NO_WG, void,= env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vmulltub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vmulltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vmulltuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) +DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) +DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i6= 4) +DEF_HELPER_FLAGS_4(mve_vmlaldavxsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i6= 4) + +DEF_HELPER_FLAGS_4(mve_vmlaldavuh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) +DEF_HELPER_FLAGS_4(mve_vmlaldavuw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) diff --git a/target/arm/translate.h b/target/arm/translate.h index 2821b325e33..99c917c571a 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -136,6 +136,11 @@ static inline int negate(DisasContext *s, int x) return -x; } =20 +static inline int plus_1(DisasContext *s, int x) +{ + return x + 1; +} + static inline int plus_2(DisasContext *s, int x) { return x + 2; @@ -151,6 +156,11 @@ static inline int times_4(DisasContext *s, int x) return x * 4; } =20 +static inline int times_2_plus_1(DisasContext *s, int x) +{ + return x * 2 + 1; +} + static inline int arm_dc_feature(DisasContext *dc, int feature) { return (dc->features & (1ULL << feature)) !=3D 0; diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 5a480d61cd6..bde54d05bb9 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -130,3 +130,18 @@ VNEG_fp 1111 1111 1 . 11 .. 01 ... 0 0111 11 = . 0 ... 0 @1op VDUP 1110 1110 1 1 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size= =3D0 VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 1 1 0000 @vdup size= =3D1 VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size= =3D2 + +# multiply-add long dual accumulate +# rdahi: bits [3:1] from insn, bit 0 is 1 +# rdalo: bits [3:1] from insn, bit 0 is 0 +%rdahi 20:3 !function=3Dtimes_2_plus_1 +%rdalo 13:3 !function=3Dtimes_2 +# size bit is 0 for 16 bit, 1 for 32 bit +%size_16 16:1 !function=3Dplus_1 + +&vmlaldav rdahi rdalo size qn qm x a + +@vmlaldav .... .... . ... ... . ... . .... .... qm:3 . \ + qn=3D%qn rdahi=3D%rdahi rdalo=3D%rdalo size=3D%size_16 &v= mlaldav +VMLALDAV_S 1110 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlal= dav +VMLALDAV_U 1111 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlal= dav diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 2d0c6998caa..3c7a0bac3c7 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -475,3 +475,35 @@ DO_2OP_S(vhadds, do_vhadd_s) DO_2OP_U(vhaddu, do_vhadd_u) DO_2OP_S(vhsubs, do_vhsub_s) DO_2OP_U(vhsubu, do_vhsub_u) + + +/* + * Multiply add long dual accumulate ops. + */ +#define DO_LDAV(OP, ESIZE, TYPE, H, XCHG, EVENACC, ODDACC) \ + uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ + void *vm, uint64_t a) \ + { \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + TYPE *n =3D vn, *m =3D vm; = \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + if (mask & 1) { \ + if (e & 1) { \ + a ODDACC (int64_t)n[H(e - 1 * XCHG)] * m[H(e)]; \ + } else { \ + a EVENACC (int64_t)n[H(e + 1 * XCHG)] * m[H(e)]; \ + } \ + } \ + } \ + mve_advance_vpt(env); \ + return a; \ + } + +DO_LDAV(vmlaldavsh, 2, int16_t, H2, false, +=3D, +=3D) +DO_LDAV(vmlaldavxsh, 2, int16_t, H2, true, +=3D, +=3D) +DO_LDAV(vmlaldavsw, 4, int32_t, H4, false, +=3D, +=3D) +DO_LDAV(vmlaldavxsw, 4, int32_t, H4, true, +=3D, +=3D) + +DO_LDAV(vmlaldavuh, 2, uint16_t, H2, false, +=3D, +=3D) +DO_LDAV(vmlaldavuw, 4, uint32_t, H4, false, +=3D, +=3D) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index ccff7fc0ecf..03d9496f17d 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -31,6 +31,7 @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); +typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCG= v_i64); =20 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) = */ static inline long mve_qreg_offset(unsigned reg) @@ -79,6 +80,22 @@ static void mve_update_eci(DisasContext *s) } } =20 +static bool mve_skip_first_beat(DisasContext *s) +{ + /* Return true if PSR.ECI says we must skip the first beat of this ins= n */ + switch (s->eci) { + case ECI_NONE: + return false; + case ECI_A0: + case ECI_A0A1: + case ECI_A0A1A2: + case ECI_A0A1A2B0: + return true; + default: + g_assert_not_reached(); + } +} + static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn) { TCGv_i32 addr; @@ -397,3 +414,86 @@ DO_2OP(VMULL_BS, vmullbs) DO_2OP(VMULL_BU, vmullbu) DO_2OP(VMULL_TS, vmullts) DO_2OP(VMULL_TU, vmulltu) + +static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, + MVEGenDualAccOpFn *fn) +{ + TCGv_ptr qn, qm; + TCGv_i64 rda; + TCGv_i32 rdalo, rdahi; + + if (!fn || !dc_isar_feature(aa32_mve, s)) { + return false; + } + /* + * rdahi =3D=3D 13 is UNPREDICTABLE; rdahi =3D=3D 15 is a related + * encoding; rdalo always has bit 0 clear so cannot be 13 or 15. + */ + if (a->rdahi =3D=3D 13 || a->rdahi =3D=3D 15) { + return false; + } + if (a->qn > 7 || a->qm > 7) { + return false; + } + if (!mve_eci_check(s)) { + return true; + } + if (!vfp_access_check(s)) { + return true; + } + + qn =3D mve_qreg_ptr(a->qn); + qm =3D mve_qreg_ptr(a->qm); + + /* + * This insn is subject to beat-wise execution. Partial execution + * of an A=3D0 (no-accumulate) insn which does not execute the first + * beat must start with the current rda value, not 0. + */ + if (a->a || mve_skip_first_beat(s)) { + rda =3D tcg_temp_new_i64(); + rdalo =3D load_reg(s, a->rdalo); + rdahi =3D load_reg(s, a->rdahi); + tcg_gen_concat_i32_i64(rda, rdalo, rdahi); + tcg_temp_free_i32(rdalo); + tcg_temp_free_i32(rdahi); + } else { + rda =3D tcg_const_i64(0); + } + + fn(rda, cpu_env, qn, qm, rda); + tcg_temp_free_ptr(qn); + tcg_temp_free_ptr(qm); + + rdalo =3D tcg_temp_new_i32(); + rdahi =3D tcg_temp_new_i32(); + tcg_gen_extrl_i64_i32(rdalo, rda); + tcg_gen_extrh_i64_i32(rdahi, rda); + store_reg(s, a->rdalo, rdalo); + store_reg(s, a->rdahi, rdahi); + tcg_temp_free_i64(rda); + mve_update_eci(s); + return true; +} + +static bool trans_VMLALDAV_S(DisasContext *s, arg_vmlaldav *a) +{ + MVEGenDualAccOpFn *fns[4][2] =3D { + { NULL, NULL }, + { gen_helper_mve_vmlaldavsh, gen_helper_mve_vmlaldavxsh }, + { gen_helper_mve_vmlaldavsw, gen_helper_mve_vmlaldavxsw }, + { NULL, NULL }, + }; + return do_long_dual_acc(s, a, fns[a->size][a->x]); +} + +static bool trans_VMLALDAV_U(DisasContext *s, arg_vmlaldav *a) +{ + MVEGenDualAccOpFn *fns[4][2] =3D { + { NULL, NULL }, + { gen_helper_mve_vmlaldavuh, NULL }, + { gen_helper_mve_vmlaldavuw, NULL }, + { NULL, NULL }, + }; + return do_long_dual_acc(s, a, fns[a->size][a->x]); +} --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623088008; cv=none; d=zohomail.com; s=zohoarc; b=FhElVBNOo5sFPTL0OrA0vDes861otgslYgR6zPvXA4Mcqa1ac8RHN7b3zMv9Ysr+kYf9NHFzaR+Lwj12izzgZtmIV3usK0Av29gEel4+vqUCZWWOjmlmBcczbTDKxbem5n4jaFz6HcXzNmsg6DmUz5bsPUqFIQxli2agjXiEGBw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623088008; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Lri0jwug/Qcj4uQxmZ9BHJPP5okkwUiX+tQt61XPaUA=; b=EYE2j29jWqfBXFACpnbiNYs4x2+7jqlMuRhVW3+N2inRxMJbx1ncntpxsjXbf1ci9E5LQu9qiQS89K4SAdcy7CcJ0095iwtWDyRhb3lZVJnjVFegKiG0k0xgMJI60o764mmi4A2yES/VFl9zsMQZ3zYFMjifiuFUo86uT+KU2yA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623088008314266.1993958869905; Mon, 7 Jun 2021 10:46:48 -0700 (PDT) Received: from localhost ([::1]:51068 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqJKp-0002MZ-5b for importer@patchew.org; Mon, 07 Jun 2021 13:46:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60078) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIb7-00082S-FK for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:33 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:43693) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIaX-00080h-Tc for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:33 -0400 Received: by mail-wr1-x42e.google.com with SMTP id r9so1730741wrz.10 for ; Mon, 07 Jun 2021 09:58:48 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Lri0jwug/Qcj4uQxmZ9BHJPP5okkwUiX+tQt61XPaUA=; b=UQ3J8ncUsvbhWWj50rtxAjXmAqjqSdoyr0OSF26f7i/v9qZRJRrQaDYR1mpal1Rt/U 53vXZzkScqTcB9Mci04uIiIURgaHr94bw5AuMFAQZ2Wi9BrxpDjZkaN0JvCXxwonqfun NTOQK2nfa5z4Q2PapT5P7Ku3aq4lJGOAG00EEPs6Y7dIyozbc8AGB6OjnRSobSk0r+4+ I6CLU9a0BZHDP7Ng+9iKzm8mqZrq32Af/twdGkLdYzNgWRAkFTa/s3sKDXAd0QD9RSIB p8KyGokhgLuoYJJkQ9TzTWx3oTumGrVB+5JWs20bSdBsM9Oev3Ih+jCTAVPMyMzBY7mL xBRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Lri0jwug/Qcj4uQxmZ9BHJPP5okkwUiX+tQt61XPaUA=; b=TsQgYY8m63FHsf/titayoRM917ltYZhf8vT9zkZzY1B/8I3DY+F4+HqfCN5mFcPPEv 6LiUm1jHR7akyDLcTyD52WzEu8K3jETArefB6Ykp4k7exF2UHixgakUzPEAb1/YQWhvE Zsf3ixSZ+Q+ftkr0CLXK+JIOIC8qcRBRwIVcMeBWgLfcfILgv6slf3kg1BQCFWKjngoJ gENT31BfdpJzJUj9EATB9Jr4K/6tIV/ifdGP0QXBGp4IS8YIxfUzmYxIhxMYUliRV8lC 3b1edf65gJPeDkqDpimbgqHkLy+hM2aQUvUrf0RPbrPGTTq1t/kIeqkW8+kgRiHwQQnq o5Og== X-Gm-Message-State: AOAM532fcYyfNzXUEmoM7QwGuDywoOczyZAogOjSVWr5kkWAlSr2iLHk TdG65hT/u4+fnpS0L7s2G87Oag== X-Google-Smtp-Source: ABdhPJyJBZfG2yFyDFwCDrj2VBBblm+9pyo9oT/yX3xw1jPs+FeJYhbMNwiQwcsio/q14vLU2q8nPg== X-Received: by 2002:adf:e943:: with SMTP id m3mr18065542wrn.384.1623085127611; Mon, 07 Jun 2021 09:58:47 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 30/55] target/arm: Implement MVE VMLSLDAV Date: Mon, 7 Jun 2021 17:57:56 +0100 Message-Id: <20210607165821.9892-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE insn VMLSLDAV, which multiplies source elements, alternately adding and subtracting them, and accumulates into a 64-bit result in a pair of general purpose registers. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 5 +++++ target/arm/mve.decode | 2 ++ target/arm/mve_helper.c | 5 +++++ target/arm/translate-mve.c | 11 +++++++++++ 4 files changed, 23 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 1013f6912da..7789da1986b 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -154,3 +154,8 @@ DEF_HELPER_FLAGS_4(mve_vmlaldavxsw, TCG_CALL_NO_WG, i64= , env, ptr, ptr, i64) =20 DEF_HELPER_FLAGS_4(mve_vmlaldavuh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vmlaldavuw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) + +DEF_HELPER_FLAGS_4(mve_vmlsldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) +DEF_HELPER_FLAGS_4(mve_vmlsldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) +DEF_HELPER_FLAGS_4(mve_vmlsldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i6= 4) +DEF_HELPER_FLAGS_4(mve_vmlsldavxsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i6= 4) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index bde54d05bb9..1be2d6b270f 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -145,3 +145,5 @@ VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 0= 1 0000 @vdup size=3D2 qn=3D%qn rdahi=3D%rdahi rdalo=3D%rdalo size=3D%size_16 &v= mlaldav VMLALDAV_S 1110 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlal= dav VMLALDAV_U 1111 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlal= dav + +VMLSLDAV 1110 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 1 @vmlal= dav diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 3c7a0bac3c7..1c22e2777d9 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -507,3 +507,8 @@ DO_LDAV(vmlaldavxsw, 4, int32_t, H4, true, +=3D, +=3D) =20 DO_LDAV(vmlaldavuh, 2, uint16_t, H2, false, +=3D, +=3D) DO_LDAV(vmlaldavuw, 4, uint32_t, H4, false, +=3D, +=3D) + +DO_LDAV(vmlsldavsh, 2, int16_t, H2, false, +=3D, -=3D) +DO_LDAV(vmlsldavxsh, 2, int16_t, H2, true, +=3D, -=3D) +DO_LDAV(vmlsldavsw, 4, int32_t, H4, false, +=3D, -=3D) +DO_LDAV(vmlsldavxsw, 4, int32_t, H4, true, +=3D, -=3D) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 03d9496f17d..66d713a24e2 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -497,3 +497,14 @@ static bool trans_VMLALDAV_U(DisasContext *s, arg_vmla= ldav *a) }; return do_long_dual_acc(s, a, fns[a->size][a->x]); } + +static bool trans_VMLSLDAV(DisasContext *s, arg_vmlaldav *a) +{ + MVEGenDualAccOpFn *fns[4][2] =3D { + { NULL, NULL }, + { gen_helper_mve_vmlsldavsh, gen_helper_mve_vmlsldavxsh }, + { gen_helper_mve_vmlsldavsw, gen_helper_mve_vmlsldavxsw }, + { NULL, NULL }, + }; + return do_long_dual_acc(s, a, fns[a->size][a->x]); +} --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623087314; cv=none; d=zohomail.com; s=zohoarc; b=DwDr3Gx+GKFiglaaUBeBRwKDNwH0Xupl7v16fj2VLQGcOgRRGA2gcdhTz+tG7Lsv2lXtazvLfCvoJnnd3kheq2oZakver+m2fkJGhrmUNXccmhCKCyV2UJ5Ua+zWkgNjyDwy++zJoEug9Wabs/CRv2aGC7KzAZkwP3q3h3MfaK0= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RzQMU2S0MPi6LG0qvbJo0z1iKKPaC9Dm6mwYYso4zvc=; b=xNHOg2DMteh7TAdIVmaWYo+X/GeDt60xODrAWEl9jKHSEcQigtJL4ufd5TB8jNwUp2 dlE6ofWdhj+DnercmQyrJGlt0hF23HaGHGwTBUbA6ad3sbDtq7rVNnM6UZJd4jQxXj1M lo523l3NpmJwDB1RRBFDSzEP3zsr9SvsZeY/jm6yywBLZ9Jllp+M9+ziDWWZcD6ZTIuz 4oeVDDsn1uSG1zhAjybfulFhlHozSAohQVyzxAo1Py/3NQqhCO+ocTVFdtTwMm3qIup5 VPUJfTwJyUgWKEWjUmdnRZeMwNPhpmT1G/txXIlSpunUYQYgKnEwjcQzgLJRWSr2DVTi ZCCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RzQMU2S0MPi6LG0qvbJo0z1iKKPaC9Dm6mwYYso4zvc=; b=j+6LXxEYKvMQ+zpGoAkeiWRoJjxbbnRxrHpTZCfOeyzHMPF4q/oFwiWw4iWJqrLFxX +cQG5EFYoUkeoOg/uPN/P/VjjhL2O1AZMJudvBSB5nz/bw+kGWW6t6BXsniKis2JDmxD BGdK2UxOK7/s0cL+Sab4SIyEJTFt9ExV8Y0ytBdIPN/qmJIfq1XrtlYXZJGl5d3R3te7 SpUI3MS5vsNOfgnczWHv/FLJe7Alu0nq6tq3iO2xMi3lqS3k4c/OSqRoq5d/wLKKI+RX yAKY3X43xdR2Lv0+PufgJ2S6LnV9X/EnQRV8r1ONWm+sU+NwkxY+/+MilYkkWejDqMRj 0+mQ== X-Gm-Message-State: AOAM531Zcw1pCBqHzLCXFPfCGrWNcSKJmkdo1/BHXhjELH+ifMxVEKTJ m6+mo+yVhMVr2Zo7uzce7aeC5Q== X-Google-Smtp-Source: ABdhPJwDTuv0HawLnD1CACEFY2E+PN/UxAVNU55U+eX+ehQvqraMBj/A8ELiivJa+OVjYiscfkWMsg== X-Received: by 2002:a05:600c:4ec8:: with SMTP id g8mr93878wmq.62.1623085128256; Mon, 07 Jun 2021 09:58:48 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 31/55] include/qemu/int128.h: Add function to create Int128 from int64_t Date: Mon, 7 Jun 2021 17:57:57 +0100 Message-Id: <20210607165821.9892-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" int128_make64() creates an Int128 from an unsigned 64 bit value; add a function int128_makes64() creating an Int128 from a signed 64 bit value. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/qemu/int128.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/qemu/int128.h b/include/qemu/int128.h index 52fc2384211..64500385e37 100644 --- a/include/qemu/int128.h +++ b/include/qemu/int128.h @@ -11,6 +11,11 @@ static inline Int128 int128_make64(uint64_t a) return a; } =20 +static inline Int128 int128_makes64(int64_t a) +{ + return a; +} + static inline Int128 int128_make128(uint64_t lo, uint64_t hi) { return (__uint128_t)hi << 64 | lo; @@ -167,6 +172,11 @@ static inline Int128 int128_make64(uint64_t a) return (Int128) { a, 0 }; } =20 +static inline Int128 int128_makes64(int64_t a) +{ + return (Int128) { a, a >> 63 }; +} + static inline Int128 int128_make128(uint64_t lo, uint64_t hi) { return (Int128) { lo, hi }; --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623086392; cv=none; d=zohomail.com; s=zohoarc; b=Sr67hIC7CgJMAphKvqU+RUGP7UI1aTpxzCHrxb7PQU+2GZoncw3xkywYVGFf9X8yLjHOifLLKxG4IRf6f5RNTFmKRwa7AH7O2Wtt0FXyHSXgJtx40opAwHdj+3Qy56heOjVSSzrXdN2k5rbutv98jjYeJaNh9KFOccHEYWXDD7c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623086392; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2uRhRiYsk/oV1HZWvgmDQagAPohNvG21ydMlcZh3lyY=; b=daw8GoH4TNfPUjuiq69v7quJE4xfgLznvJNuUeJZi8W5yE/eCP9VFxMZf+a4E8j7B4V9DDebnnQMXPJbu/KfeUvPRuT371YDr7jw6BJN/4bkQjBZjhqH2BQwdHWh0rlBv1hRyKc1zhevHidaolqlaEvqJtHe/cTan/3iPKQuVSU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623086392266810.5435275043023; Mon, 7 Jun 2021 10:19:52 -0700 (PDT) Received: from localhost ([::1]:37928 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqIuk-0003wc-Fy for importer@patchew.org; Mon, 07 Jun 2021 13:19:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59810) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIap-0007fT-0r for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:16 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:44655) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIaR-00081l-Pr for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:14 -0400 Received: by mail-wr1-x42a.google.com with SMTP id f2so18391713wri.11 for ; Mon, 07 Jun 2021 09:58:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2uRhRiYsk/oV1HZWvgmDQagAPohNvG21ydMlcZh3lyY=; b=j5CViCGoU27XFw57vNeW6osWidwWV22HlGM1jItUjAHTMTL5kF0rguwOl2VDJQvAiR zP4xxPvMaJcy1jDbAb+2QTcTDO38zDNRdE1uIBpG7h16dply2GwlsMV+XsXuvaGgTpaD t5DxyN/v7dqzoqn3cLsMRziGQFDys2R2+HtxuzLIqO+DQjD4ZB1opblEqZ8cvLK5HGVU LvG82cS5of5geTdLwi6nEDj7bZUGMmCPPSYBQs4QiV0l7cqr5ry2V2OWDtPM6JaWzAEa u7QFfmVWF0cpAtePhkRmXzB+AG7OtdeAF9C6FAiEeRCBERuCpyK1rMtqpzHhFect8iss AXMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2uRhRiYsk/oV1HZWvgmDQagAPohNvG21ydMlcZh3lyY=; b=pg9Kdm1B++txJwHiDRn1msyq+Ufmz94Ibkp238WmLLMXNLhwN6fK71fI+OJehqX4Og KenTqPSPcrEgPjrk9Zo6EjEVBFfPjtAwFRgEhpps8GI04oNPsxTUW7WwhQPpgk55b+Db PhnUglhFipw02tQzhfO569Sj1FtnRuFft3kA+SAnLYqdE6wVHoEwrH6Mzm6cFsP9Wz1Y 3TxjN+0syaEaQEFcCrVMN4HFlVZqQ7XiccA0CUh9+taDH2at9NJh9q2JBgklqWYz9ptX vopT/e3fhIj0DITARHqVvrcZMKgMRGS+b3bszjPw1L4+U1IKpprU62fp6zrbD757wgE/ Xhow== X-Gm-Message-State: AOAM531y4RP3xZdApdrKSfkLI8Er/FQb7giI1UjBZvYTacbA+GJbR99g MJLd7uzpUtNG4Dh82MpuY3THH0FvmTocU9cv X-Google-Smtp-Source: ABdhPJxDRR7tJdea6+pl4buOw0orYmug1bYpRb70fuZTgbCE4ANYJ/uFJJ5ZfCYq/Q/y10OAIoYOkg== X-Received: by 2002:a5d:484b:: with SMTP id n11mr11451588wrs.34.1623085128978; Mon, 07 Jun 2021 09:58:48 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 32/55] target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH Date: Mon, 7 Jun 2021 17:57:58 +0100 Message-Id: <20210607165821.9892-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VRMLALDAVH and VRMLSLDAVH insns, which accumulate the results of a rounded multiply of pairs of elements into a 72-bit accumulator, returning the top 64 bits in a pair of general purpose registers. Signed-off-by: Peter Maydell --- target/arm/helper-mve.h | 8 ++++++++ target/arm/mve.decode | 7 +++++++ target/arm/mve_helper.c | 35 +++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 24 ++++++++++++++++++++++++ 4 files changed, 74 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 7789da1986b..723bef4a83a 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -159,3 +159,11 @@ DEF_HELPER_FLAGS_4(mve_vmlsldavsh, TCG_CALL_NO_WG, i64= , env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vmlsldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vmlsldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i6= 4) DEF_HELPER_FLAGS_4(mve_vmlsldavxsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i6= 4) + +DEF_HELPER_FLAGS_4(mve_vrmlaldavhsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i= 64) +DEF_HELPER_FLAGS_4(mve_vrmlaldavhxsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, = i64) + +DEF_HELPER_FLAGS_4(mve_vrmlaldavhuw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i= 64) + +DEF_HELPER_FLAGS_4(mve_vrmlsldavhsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i= 64) +DEF_HELPER_FLAGS_4(mve_vrmlsldavhxsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, = i64) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 1be2d6b270f..ac68f072bbe 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -143,7 +143,14 @@ VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 = 0 1 0000 @vdup size=3D2 =20 @vmlaldav .... .... . ... ... . ... . .... .... qm:3 . \ qn=3D%qn rdahi=3D%rdahi rdalo=3D%rdalo size=3D%size_16 &v= mlaldav +@vmlaldav_nosz .... .... . ... ... . ... . .... .... qm:3 . \ + qn=3D%qn rdahi=3D%rdahi rdalo=3D%rdalo size=3D0 &vmlaldav VMLALDAV_S 1110 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlal= dav VMLALDAV_U 1111 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlal= dav =20 VMLSLDAV 1110 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 1 @vmlal= dav + +VRMLALDAVH_S 1110 1110 1 ... ... 0 ... x:1 1111 . 0 a:1 0 ... 0 @vmlal= dav_nosz +VRMLALDAVH_U 1111 1110 1 ... ... 0 ... x:1 1111 . 0 a:1 0 ... 0 @vmlal= dav_nosz + +VRMLSLDAVH 1111 1110 1 ... ... 0 ... x:1 1110 . 0 a:1 0 ... 1 @vmlal= dav_nosz diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 1c22e2777d9..b22a7535308 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -18,6 +18,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/int128.h" #include "cpu.h" #include "internals.h" #include "exec/helper-proto.h" @@ -512,3 +513,37 @@ DO_LDAV(vmlsldavsh, 2, int16_t, H2, false, +=3D, -=3D) DO_LDAV(vmlsldavxsh, 2, int16_t, H2, true, +=3D, -=3D) DO_LDAV(vmlsldavsw, 4, int32_t, H4, false, +=3D, -=3D) DO_LDAV(vmlsldavxsw, 4, int32_t, H4, true, +=3D, -=3D) + +/* + * Rounding multiply add long dual accumulate high: we must keep + * a 72-bit internal accumulator value and return the top 64 bits. + */ +#define DO_LDAVH(OP, ESIZE, TYPE, H, XCHG, EVENACC, ODDACC, TO128) \ + uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ + void *vm, uint64_t a) \ + { \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + TYPE *n =3D vn, *m =3D vm; = \ + Int128 acc =3D TO128(a); \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + if (mask & 1) { \ + if (e & 1) { \ + acc =3D ODDACC(acc, TO128(n[H(e - 1 * XCHG)] * m[H(e)]= )); \ + } else { \ + acc =3D EVENACC(acc, TO128(n[H(e + 1 * XCHG)] * m[H(e)= ])); \ + } \ + acc =3D int128_add(acc, 1 << 7); \ + } \ + } \ + mve_advance_vpt(env); \ + return int128_getlo(int128_rshift(acc, 8)); \ + } + +DO_LDAVH(vrmlaldavhsw, 4, int32_t, H4, false, int128_add, int128_add, int1= 28_makes64) +DO_LDAVH(vrmlaldavhxsw, 4, int32_t, H4, true, int128_add, int128_add, int1= 28_makes64) + +DO_LDAVH(vrmlaldavhuw, 4, uint32_t, H4, false, int128_add, int128_add, int= 128_make64) + +DO_LDAVH(vrmlsldavhsw, 4, int32_t, H4, false, int128_add, int128_sub, int1= 28_makes64) +DO_LDAVH(vrmlsldavhxsw, 4, int32_t, H4, true, int128_add, int128_sub, int1= 28_makes64) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 66d713a24e2..6792fca798d 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -508,3 +508,27 @@ static bool trans_VMLSLDAV(DisasContext *s, arg_vmlald= av *a) }; return do_long_dual_acc(s, a, fns[a->size][a->x]); } + +static bool trans_VRMLALDAVH_S(DisasContext *s, arg_vmlaldav *a) +{ + MVEGenDualAccOpFn *fns[] =3D { + gen_helper_mve_vrmlaldavhsw, gen_helper_mve_vrmlaldavhxsw, + }; + return do_long_dual_acc(s, a, fns[a->x]); +} + +static bool trans_VRMLALDAVH_U(DisasContext *s, arg_vmlaldav *a) +{ + MVEGenDualAccOpFn *fns[] =3D { + gen_helper_mve_vrmlaldavhuw, NULL, + }; + return do_long_dual_acc(s, a, fns[a->x]); +} + +static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a) +{ + MVEGenDualAccOpFn *fns[] =3D { + gen_helper_mve_vrmlsldavhsw, gen_helper_mve_vrmlsldavhxsw, + }; + return do_long_dual_acc(s, a, fns[a->x]); +} --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iG+V472YKemSSADYbYtYqkhlhqc8Dpeb6zyxo7Ks0x8=; b=wu980KzSVq27gEqlIvfWXtQiLgFeXuGBN4gy70Z98XHA3DlHxdnXcdbUNPCEL+8OXz N2wJYKBev98UvcumkePT+dtp1BlFUSt+hpIHfoduW7zAiZpM65eHPCqAtNFNk2CVc29l EvOXhVAUaaCxQHW4Wwr10uGbS8APhknnQtm6No0v2yPCFPnP+d6PGtGgGDZKPv4X1JeL ypGvJ5TG1NGnqGl0n2bvCAEM8qisGFLYZGb3S5yu9gdGHzYHzkjwKA3hEnzYLWy6y1F8 2yChqQzxawo0m01Au9J+tJDekd/gDky+Vemd/WGktJ3IMp3pekgbEXD1FvgTitv9ozu3 fWOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iG+V472YKemSSADYbYtYqkhlhqc8Dpeb6zyxo7Ks0x8=; b=GMGGJlAXmsET9c0lXrLSZsY/S0p3//O2hLFLCJftNeBgQFjwaXSU5oQqfMhZCZ8RqY OoQGqNrl6dQEtugmsB5Rwa0XGZyWId2hTfkGq9rZXzvvHrBaJ6iIU13kYix9qOb6IMqO Y7gNTHumgBYg+l4QPrr3KX7pntPXdV6jyD2Kot8o588ngZbz50/hvrYn1rw3ERG+dAGo +ASY6lW8ZVwMcBpKWZyDfeqkHnaPPPvZNGGz9mN5yk4jVTI4kjCPXDPc3Sp9pjt9z5Ps GYmFSg8KeBdC18HzwwjfFW65vcI9UtQshDYP73k636luad1NKdJ2/ByIYWPKMIzzKP/U 4amA== X-Gm-Message-State: AOAM533iDS69OBn0TrShwSnjOBeQdbfSXzrkmiX0ln+r3ioDVFpT3K21 kS1cs9BIa/jkHe2HC/TVtnMnBQ== X-Google-Smtp-Source: ABdhPJwT3yvGSdG056CdsrKliEVQv1QiMADTaf3MHZhr2mNZ7uPbgwzo8J0er1O7KghtlXmEs/vX9A== X-Received: by 2002:a5d:6111:: with SMTP id v17mr8370728wrt.20.1623085129843; Mon, 07 Jun 2021 09:58:49 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 33/55] target/arm: Implement MVE VADD (scalar) Date: Mon, 7 Jun 2021 17:57:59 +0100 Message-Id: <20210607165821.9892-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the scalar form of the MVE VADD insn. This takes the scalar operand from a general purpose register. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 4 ++++ target/arm/mve.decode | 7 ++++++ target/arm/mve_helper.c | 25 +++++++++++++++++++ target/arm/translate-mve.c | 49 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 85 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 723bef4a83a..d2626810aaf 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -147,6 +147,10 @@ DEF_HELPER_FLAGS_4(mve_vmulltub, TCG_CALL_NO_WG, void,= env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vmulltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vmulltuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) +DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) +DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) + DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i6= 4) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index ac68f072bbe..0ee7a727081 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -26,6 +26,7 @@ &vldr_vstr rn qd imm p a w size l u &1op qd qm size &2op qd qm qn size +&2scalar qd qn rm size =20 @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=3D%qd u= =3D0 # Note that both Rn and Qd are 3 bits only (no D bit) @@ -36,6 +37,8 @@ @2op .... .... .. size:2 .... .... .... .... .... &2op qd=3D%qd qm=3D%qm q= n=3D%qn @2op_nosz .... .... .... .... .... .... .... .... &2op qd=3D%qd qm=3D%qm q= n=3D%qn size=3D0 =20 +@2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=3D%qd qn= =3D%qn + # Vector loads and stores =20 # Widening loads and narrowing stores: @@ -154,3 +157,7 @@ VRMLALDAVH_S 1110 1110 1 ... ... 0 ... x:1 1111 . 0= a:1 0 ... 0 @vmlaldav_no VRMLALDAVH_U 1111 1110 1 ... ... 0 ... x:1 1111 . 0 a:1 0 ... 0 @vmlal= dav_nosz =20 VRMLSLDAVH 1111 1110 1 ... ... 0 ... x:1 1110 . 0 a:1 0 ... 1 @vmlal= dav_nosz + +# Scalar operations + +VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index b22a7535308..8d9811c5473 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -478,6 +478,31 @@ DO_2OP_S(vhsubs, do_vhsub_s) DO_2OP_U(vhsubu, do_vhsub_u) =20 =20 +#define DO_2OP_SCALAR(OP, ESIZE, TYPE, H, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ + uint32_t rm) \ + { \ + TYPE *d =3D vd, *n =3D vn; = \ + TYPE m =3D rm; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + TYPE r =3D FN(n[H(e)], m); \ + uint64_t bytemask =3D mask_to_bytemask##ESIZE(mask); \ + d[H(e)] &=3D ~bytemask; \ + d[H(e)] |=3D (r & bytemask); \ + } \ + mve_advance_vpt(env); \ + } + +/* provide unsigned 2-op scalar helpers for all sizes */ +#define DO_2OP_SCALAR_U(OP, FN) \ + DO_2OP_SCALAR(OP##b, 1, uint8_t, H1, FN) \ + DO_2OP_SCALAR(OP##h, 2, uint16_t, H2, FN) \ + DO_2OP_SCALAR(OP##w, 4, uint32_t, H4, FN) + +DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) + /* * Multiply add long dual accumulate ops. */ diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 6792fca798d..89e5aa50284 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -31,6 +31,7 @@ typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); +typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCG= v_i64); =20 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) = */ @@ -415,6 +416,54 @@ DO_2OP(VMULL_BU, vmullbu) DO_2OP(VMULL_TS, vmullts) DO_2OP(VMULL_TU, vmulltu) =20 +static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, + MVEGenTwoOpScalarFn fn) +{ + TCGv_ptr qd, qn; + TCGv_i32 rm; + + if (!dc_isar_feature(aa32_mve, s)) { + return false; + } + if (a->qd > 7 || a->qn > 7 || !fn) { + return false; + } + if (a->rm =3D=3D 13 || a->rm =3D=3D 15) { + /* UNPREDICTABLE */ + return false; + } + if (!mve_eci_check(s)) { + return true; + } + if (!vfp_access_check(s)) { + return true; + } + + qd =3D mve_qreg_ptr(a->qd); + qn =3D mve_qreg_ptr(a->qn); + rm =3D load_reg(s, a->rm); + fn(cpu_env, qd, qn, rm); + tcg_temp_free_i32(rm); + tcg_temp_free_ptr(qd); + tcg_temp_free_ptr(qn); + mve_update_eci(s); + return true; +} + +#define DO_2OP_SCALAR(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_2scalar *a) \ + { \ + MVEGenTwoOpScalarFn *fns[] =3D { \ + gen_helper_mve_##FN##b, \ + gen_helper_mve_##FN##h, \ + gen_helper_mve_##FN##w, \ + NULL, \ + }; \ + return do_2op_scalar(s, a, fns[a->size]); \ + } + +DO_2OP_SCALAR(VADD_scalar, vadd_scalar) + static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, MVEGenDualAccOpFn *fn) { --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623087063; cv=none; d=zohomail.com; s=zohoarc; b=nb1GjrMRDnbMF5W/WK8KzkY7YNCEJsDxLEqQ/bk4Kx/xbCgYffMCcHF6cf5bUknL+WLptVuKEUoHLpDoLe1knqYgXgWgjn3C/QaygG/eXcNEXnio3zRRSzx+sMq4E6WW3R4u2XaQ351fjMTfKgbmqmBv2AAPhWAzcZFrWpWWMZw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623087063; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=I4u5O/+URPY2YX5g4RVQ1o01+GIgpzy68B0lmOEsuVk=; b=tVFFxt7IwfqTA0Ji2z1XWjZZHWW9NUL3K6tUSAwjVw6WdTJzeBz2+rqT/xluaszq3T a/ew5g/TGk+Eyani2+zdgrYExBH9tlnmBDGNzhxDceXWs1xpV5ZmBxqOpL2U7t8o50Ks njmUkPqfPykMdIlWmvpFn8us5d+aosYa/kTU52pRDkja0TwA8qsLZ1atigPmWWTmgDg2 sXKGFCAdHqUqcbwIb99D7CK9m1cJcVTD+/xqGmPCsbD1KZDa4C8v+p7QWfEq2ko+9Bl4 HiO9HWNRlzxSQhW/pv0QrF3yaCSo9mWiu4fQN27KtamHlCzfUfPwhG7qoMeG1NaGqpI0 ZB9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=I4u5O/+URPY2YX5g4RVQ1o01+GIgpzy68B0lmOEsuVk=; b=uApxZKHTa6sv4Y5WtfaLbET5mZii14WZUABm2trnqgKivgRMDdXE57XzBqSqianvtQ BDa8LZ8Ss8w0TJlQlFDyElY6wxtNjo0LmwDolkfdyJAxNp/oA4f7hLtALNuIrxeSXgMm R8YvAXIeOKyFQQK/2fu/fDmSLYBJAFDj8yoiaB/6xltYafNwym949dspBZW9oJMSMqJl op6BR/+GXciqsENxusAdBitYjsvZ1QGU2ShkTZxMyqnb5YQc9o05mpZGJMDOfbERalsj vcsydYlWV+BxWQ1p862jHMaQiMgg0Am6ACETY7hUBrk93jTmCQet9HNvzwrY7arLaWba QwNQ== X-Gm-Message-State: AOAM533zktaR9IPlX6UgJbVegF4fTXO9DsWBI23YcYnkPDRjMxlb0Wkt Hg9AkB2fvObFa6gWo3oTOQFj1Q== X-Google-Smtp-Source: ABdhPJyTpS7l8CFUIRhRE5VGNVkq8oI5r1AjrEZKdxvypZ0ixOeFy0HJPxeTp5ovHr/T+3endfBVVw== X-Received: by 2002:a05:6000:1acd:: with SMTP id i13mr9834582wry.327.1623085130572; Mon, 07 Jun 2021 09:58:50 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 34/55] target/arm: Implement MVE VSUB, VMUL (scalar) Date: Mon, 7 Jun 2021 17:58:00 +0100 Message-Id: <20210607165821.9892-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the scalar forms of the MVE VSUB and VMUL insns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 8 ++++++++ target/arm/mve.decode | 2 ++ target/arm/mve_helper.c | 2 ++ target/arm/translate-mve.c | 2 ++ 4 files changed, 14 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index d2626810aaf..4d39527e201 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -151,6 +151,14 @@ DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, v= oid, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) =20 +DEF_HELPER_FLAGS_4(mve_vsub_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) +DEF_HELPER_FLAGS_4(mve_vsub_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) +DEF_HELPER_FLAGS_4(mve_vsub_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) + +DEF_HELPER_FLAGS_4(mve_vmul_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) +DEF_HELPER_FLAGS_4(mve_vmul_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) +DEF_HELPER_FLAGS_4(mve_vmul_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) + DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i6= 4) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 0ee7a727081..af5fba78ce2 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -161,3 +161,5 @@ VRMLSLDAVH 1111 1110 1 ... ... 0 ... x:1 1110 . 0= a:1 0 ... 1 @vmlaldav_no # Scalar operations =20 VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar +VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 100 .... @2scalar +VMUL_scalar 1110 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 8d9811c5473..8892a713287 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -502,6 +502,8 @@ DO_2OP_U(vhsubu, do_vhsub_u) DO_2OP_SCALAR(OP##w, 4, uint32_t, H4, FN) =20 DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) +DO_2OP_SCALAR_U(vsub_scalar, DO_SUB) +DO_2OP_SCALAR_U(vmul_scalar, DO_MUL) =20 /* * Multiply add long dual accumulate ops. diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 89e5aa50284..c03528d1973 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -463,6 +463,8 @@ static bool do_2op_scalar(DisasContext *s, arg_2scalar = *a, } =20 DO_2OP_SCALAR(VADD_scalar, vadd_scalar) +DO_2OP_SCALAR(VSUB_scalar, vsub_scalar) +DO_2OP_SCALAR(VMUL_scalar, vmul_scalar) =20 static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, MVEGenDualAccOpFn *fn) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dnwdQ48Evvu95KjTeddCpWFog36QsW/ysrhnli1x9Gw=; b=VSj6+zJeueCCL6fs7PAsarBsjsDCjs5nTGfVrcvx7xBM25QEhSYb/Qjj+9waOe+UXm mEEQ62BO/ww7osGTEmI1n89Q0xdaedQkjYBtkwVh2xzwtygUvqD/j9XK63JJp316t0ac DCP2Cl0cc1KY2AP/fhg6UDssXs3KHHdP/yKAp8GKTRoRm4Ce+OAJG8VSGAcy6VvQO05W L/VTOiZzkP23KrFRhweFIjnLdwKvnoFy95tZCUgVveb50h2Rdg2h7YXXSBiOHhaAzBMr aChBO3wgIz1PRHi1KoSwnVfB7Er3RvP8+KOG7yOMZloswo97rNW9+FId66PIo2wMvM34 jXUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dnwdQ48Evvu95KjTeddCpWFog36QsW/ysrhnli1x9Gw=; b=T94XG/d+3jkJVLT7+TQH7iT9ZXFOId79Evh+JWOgCwByZw7mxeAtltjyaDjqSkT13N FkarjbauLzgE0qlMyl4S9kPPs7M6CYwzlY2VPg0KNlcv4AgPG2vSV2fZ6iUcClEw2E/i fce13B8M/T3O9ekRId+lAyMB+3t8eqPzyGeAn2Ski9Lc/0Yw3as3ArueE8n5WM2G2Gdc SvecgYSP3Pe9dnpQkX/JSJifEVpALqPoydXuK5Lce+7MwhIvEMReuYIaAGnvheFDslfz CyXVnHnGYP7Ab2zjV/LgzcyblR00StFUxH3zaFEhKJg5OIwMc/cZvGxj0E5fiBjUIikL GXUA== X-Gm-Message-State: AOAM530viJs9kVQNjPXPhpEN+6L4o62S1+BafxkHzFKMxi9EHkrlGMuL uE02WPZwFGS49Aoa26kyU+CHJMmqE+e09rah X-Google-Smtp-Source: ABdhPJwIzLbIJ0xnlkmGNwdAFXY5SUyoPHYWg9KJc3Z1usqbws0M8OmbspmEegfI8KwcfzlVM+W93g== X-Received: by 2002:a1c:7ec3:: with SMTP id z186mr17606561wmc.102.1623085131313; Mon, 07 Jun 2021 09:58:51 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 35/55] target/arm: Implement MVE VHADD, VHSUB (scalar) Date: Mon, 7 Jun 2021 17:58:01 +0100 Message-Id: <20210607165821.9892-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the scalar variants of the MVE VHADD and VHSUB insns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 16 ++++++++++++++++ target/arm/mve.decode | 4 ++++ target/arm/mve_helper.c | 8 ++++++++ target/arm/translate-mve.c | 4 ++++ 4 files changed, 32 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 4d39527e201..5853bd34687 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -159,6 +159,22 @@ DEF_HELPER_FLAGS_4(mve_vmul_scalarb, TCG_CALL_NO_WG, v= oid, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vmul_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vmul_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) =20 +DEF_HELPER_FLAGS_4(mve_vhadds_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vhadds_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vhadds_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) + +DEF_HELPER_FLAGS_4(mve_vhaddu_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vhaddu_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vhaddu_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) + +DEF_HELPER_FLAGS_4(mve_vhsubs_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vhsubs_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vhsubs_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) + +DEF_HELPER_FLAGS_4(mve_vhsubu_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vhsubu_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vhsubu_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) + DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i6= 4) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index af5fba78ce2..5c332b04a7c 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -163,3 +163,7 @@ VRMLSLDAVH 1111 1110 1 ... ... 0 ... x:1 1110 . 0= a:1 0 ... 1 @vmlaldav_no VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 100 .... @2scalar VMUL_scalar 1110 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar +VHADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar +VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar +VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar +VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 8892a713287..dbcf4c24949 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -500,10 +500,18 @@ DO_2OP_U(vhsubu, do_vhsub_u) DO_2OP_SCALAR(OP##b, 1, uint8_t, H1, FN) \ DO_2OP_SCALAR(OP##h, 2, uint16_t, H2, FN) \ DO_2OP_SCALAR(OP##w, 4, uint32_t, H4, FN) +#define DO_2OP_SCALAR_S(OP, FN) \ + DO_2OP_SCALAR(OP##b, 1, int8_t, H1, FN) \ + DO_2OP_SCALAR(OP##h, 2, int16_t, H2, FN) \ + DO_2OP_SCALAR(OP##w, 4, int32_t, H4, FN) =20 DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) DO_2OP_SCALAR_U(vsub_scalar, DO_SUB) DO_2OP_SCALAR_U(vmul_scalar, DO_MUL) +DO_2OP_SCALAR_S(vhadds_scalar, do_vhadd_s) +DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u) +DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s) +DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u) =20 /* * Multiply add long dual accumulate ops. diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index c03528d1973..8dfc52d8027 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -465,6 +465,10 @@ static bool do_2op_scalar(DisasContext *s, arg_2scalar= *a, DO_2OP_SCALAR(VADD_scalar, vadd_scalar) DO_2OP_SCALAR(VSUB_scalar, vsub_scalar) DO_2OP_SCALAR(VMUL_scalar, vmul_scalar) +DO_2OP_SCALAR(VHADD_S_scalar, vhadds_scalar) +DO_2OP_SCALAR(VHADD_U_scalar, vhaddu_scalar) +DO_2OP_SCALAR(VHSUB_S_scalar, vhsubs_scalar) +DO_2OP_SCALAR(VHSUB_U_scalar, vhsubu_scalar) =20 static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, MVEGenDualAccOpFn *fn) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4NcL5xtEouw+Mk0EZO835y5LYH7TGW2TpYkGpEcSuXE=; b=ebQCYNA6C8ZF2Bz7qLnNmKjo0yVCj8xdKpQrRGNQpNQGxfRaZgHwBDpxtofu2BF8p2 focuWu2DmGiyx8EKut6DJhBKf3XXFuRM6yfakGAB4zqg+3LFVE58XR0TxEPREQrNU8jJ hrm2waVKnyPYoX7CqOyPHr1mauX2TkExggnrR/pEQ8uuJXLO5U+ToxW6XORjOtufvj/s 34dLY/tp/wT1p9IninydSE9oYyNEOn9FEx9RXfo0wsT/ftOXV2UgmBEgbGvGszqEbG+6 5Ynb8ZsPHp2zag64pM9LK1JKgF7RJyT8UI2YE9Zr0F5YJyT2JprC9uf7hv2o9ZjG/Kul U+9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4NcL5xtEouw+Mk0EZO835y5LYH7TGW2TpYkGpEcSuXE=; b=YF5hO65Yo8clQwj7ZnOmt+YECbAbISnmPrENzMPv+jN/QF0YbzXwDmd8UUa3MTT8Q+ c+BxlZJN9pyPcjPca/eMGqROtvEmOfVCTMIrN9PJEA8lDK0cum7spaYZE7i05bfRtSK9 s+EpQ04p1kzDqJXMqiIWJWHlfIesnUYfMcXqs/gSBQ4qgPnI1am5WBQYtXFzHrA6fBeo f7IVAk92eVLVn0iLVnmyEpbV/h4fU40okGTbLN9hcsMXkcBPfwwM4gK+w8rCMENG+vtl 3m7S02vljSC/KqQJub0fqOLiZD1r0lJlSJk8VwErvcPyyOJsL2Jku15oKVEW0WQCPdci Hypw== X-Gm-Message-State: AOAM530KbndhfKHvc/o5I2ZGNqv4QKpmHzVmTwoJdKwxFXsG6lMuz+Jk e/m2w13oDP7C+nR90RXBnV+4n55PAanlCbLN X-Google-Smtp-Source: ABdhPJw6O/Wvv/EsqRWWRlP6qTO0VU+QAcufKti2aMISrNyAVqepb9E1NDxid5+UgW00BiaGSB6yTw== X-Received: by 2002:a7b:c206:: with SMTP id x6mr100705wmi.26.1623085132209; Mon, 07 Jun 2021 09:58:52 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 36/55] target/arm: Implement MVE VBRSR Date: Mon, 7 Jun 2021 17:58:02 +0100 Message-Id: <20210607165821.9892-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VBRSR insn, which reverses a specified number of bits in each element, setting the rest to zero. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 4 ++++ target/arm/mve.decode | 1 + target/arm/mve_helper.c | 43 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 1 + 4 files changed, 49 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 5853bd34687..1f77a661b9b 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -175,6 +175,10 @@ DEF_HELPER_FLAGS_4(mve_vhsubu_scalarb, TCG_CALL_NO_WG,= void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vhsubu_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) DEF_HELPER_FLAGS_4(mve_vhsubu_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) =20 +DEF_HELPER_FLAGS_4(mve_vbrsrb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vbrsrh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(mve_vbrsrw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i6= 4) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 5c332b04a7c..a3dbdb72a5c 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -167,3 +167,4 @@ VHADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 10= 0 .... @2scalar VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar +VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index dbcf4c24949..25426fae992 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -513,6 +513,49 @@ DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u) DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s) DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u) =20 +static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) +{ + m &=3D 0xff; + if (m =3D=3D 0) { + return 0; + } + n =3D revbit8(n); + if (m < 8) { + n >>=3D 8 - m; + } + return n; +} + +static inline uint32_t do_vbrsrh(uint32_t n, uint32_t m) +{ + m &=3D 0xff; + if (m =3D=3D 0) { + return 0; + } + n =3D revbit16(n); + if (m < 16) { + n >>=3D 16 - m; + } + return n; +} + +static inline uint32_t do_vbrsrw(uint32_t n, uint32_t m) +{ + m &=3D 0xff; + if (m =3D=3D 0) { + return 0; + } + n =3D revbit32(n); + if (m < 32) { + n >>=3D 32 - m; + } + return n; +} + +DO_2OP_SCALAR(vbrsrb, 1, uint8_t, H1, do_vbrsrb) +DO_2OP_SCALAR(vbrsrh, 2, uint16_t, H2, do_vbrsrh) +DO_2OP_SCALAR(vbrsrw, 4, uint32_t, H4, do_vbrsrw) + /* * Multiply add long dual accumulate ops. */ diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 8dfc52d8027..b7bf7d0960f 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -469,6 +469,7 @@ DO_2OP_SCALAR(VHADD_S_scalar, vhadds_scalar) DO_2OP_SCALAR(VHADD_U_scalar, vhaddu_scalar) DO_2OP_SCALAR(VHSUB_S_scalar, vhsubs_scalar) DO_2OP_SCALAR(VHSUB_U_scalar, vhsubu_scalar) +DO_2OP_SCALAR(VBRSR, vbrsr) =20 static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, MVEGenDualAccOpFn *fn) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yIO+GTjjJFTfowgWAGdpZDjVj4UT+8w5uZyCGycr9fY=; b=Wkj+sKHHq5bWGaInTflCFuQzdIoV8qb5b9gEhttXqCrcF0/U7wSqh3HlOdDYIx1Rsp /xEOF5YdLtw/y/yw5o1CaQb+AuICWwjDPy99KI9eKqNllxsvXSXo2eOH/tVpLLazdsrM KbvyiRVaFedAq/t34DtT0AIywxI3qYzCnNR2QlJubYlPgVO/Oon7AINkUpgoZ84hJehV kStqW5dsevZr8v1WT+FLmqUW0o2iRpg757hyOv+1Eis7VczcqhhLV9i5AKnb1Q4ZzVX1 dSPpUgZh3AOfAoB+dkAodrmbNHx20tWM5iAJ00sRGAuAaml5rUzm/nBbjOZliLQC3/vI il0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yIO+GTjjJFTfowgWAGdpZDjVj4UT+8w5uZyCGycr9fY=; b=Ky99BpfYfZMQ8PtOoxqkxM5aJCdILnM4W97FrpO/QajMIqc+H/+Fuqsu6auADiNJJ7 37vZdufPYf2OUrGVCzzb9c3jaC/Aic4ZMuuFxdxoMlCZwKUp6NEMurqQEUwoRskhjgZ9 d4wwqVZWJELgJS3M463xDIowfwpFOSAZHBJ9NLMHbbT9A8ajV948wf4NX2NKKjQB+Erg s+V6/6SSCuMVJlvD5nmZOlNW5FyAaYLjMAoM6WS9QE34+woQDkXeTEC55HBm4F53V5Y0 5mtx440Kr26lcre8V1M8uryscWXPWmJ6UVK2Bwto6XG4/VfeCHGk8xrbqXspoYGbjfO5 l3bw== X-Gm-Message-State: AOAM533KGfeaZW27BnHV0RUl20GIfvKW4Qi1BuFE0V5Y7K9NKofJZSPW sSguxNBNDR0YezLovyf3Od6C+Q== X-Google-Smtp-Source: ABdhPJxK8pMAatqwfLWC9wRtNiLVVTy2URXH45imniF3mLGC7UHANbKcVmM6E9tbE3GPWrcnuRphEA== X-Received: by 2002:a5d:6382:: with SMTP id p2mr18889190wru.338.1623085132944; Mon, 07 Jun 2021 09:58:52 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 37/55] target/arm: Implement MVE VPST Date: Mon, 7 Jun 2021 17:58:03 +0100 Message-Id: <20210607165821.9892-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VPST insn, which sets the predicate mask fields in the VPR to the immediate value encoded in the insn. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/mve.decode | 4 +++ target/arm/translate-mve.c | 59 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index a3dbdb72a5c..e189e2de648 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -168,3 +168,7 @@ VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 10= 0 .... @2scalar VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar + +# Predicate operations +%mask_22_13 22:1 13:3 +VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=3D%mask_= 22_13 diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index b7bf7d0960f..45a71a22853 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -588,3 +588,62 @@ static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmla= ldav *a) }; return do_long_dual_acc(s, a, fns[a->x]); } + +static bool trans_VPST(DisasContext *s, arg_VPST *a) +{ + TCGv_i32 vpr, mask; + + /* mask =3D=3D 0 is a "related encoding" */ + if (!dc_isar_feature(aa32_mve, s) || !a->mask) { + return false; + } + if (!mve_eci_check(s)) { + return true; + } + if (!vfp_access_check(s)) { + return true; + } + /* + * Set the VPR mask fields. We take advantage of MASK01 and MASK23 + * being adjacent fields in the register. + * + * This insn is not predicated, but it is subject to beat-wise + * execution, and the mask is updated on the odd-numbered beats. + * So if PSR.ECI says we should skip beat 1, we mustn't update the + * 01 mask field. + */ + vpr =3D load_cpu_field(v7m.vpr); + switch (s->eci) { + case ECI_NONE: + case ECI_A0: + /* Update both 01 and 23 fields */ + mask =3D tcg_const_i32(a->mask | (a->mask << 4)); + tcg_gen_deposit_i32(vpr, vpr, mask, R_V7M_VPR_MASK01_SHIFT, + R_V7M_VPR_MASK01_LENGTH + R_V7M_VPR_MASK23_LEN= GTH); + break; + case ECI_A0A1: + case ECI_A0A1A2: + case ECI_A0A1A2B0: + /* Update only the 23 mask field */ + mask =3D tcg_const_i32(a->mask); + tcg_gen_deposit_i32(vpr, vpr, mask, R_V7M_VPR_MASK23_SHIFT, + R_V7M_VPR_MASK23_LENGTH); + break; + default: + g_assert_not_reached(); + } + store_cpu_field(vpr, v7m.vpr); + tcg_temp_free_i32(mask); + + if (s->eci) { + TCGv_i32 eci; + mve_update_eci(s); + /* + * Update ECI in CPUState (since we didn't call a helper + * that will call mve_advance_vpt()). + */ + eci =3D tcg_const_i32(s->eci << 4); + store_cpu_field(eci, condexec_bits); + } + return true; +} --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623086243; cv=none; d=zohomail.com; s=zohoarc; b=XdWb/XvmPxDaU9pIoKK3LYf+OANfpmCN5X1UHSMw90mmrYpfNjJrED+hCzO5B/RcPFycbtObvMFKWFmln/MRsFjq3usalJGWJsIXRo+B2kUndTtotheTGQ5bnravDMXH6YLrcy/C6O68lDVm7L/ylQdUFewlRDdHrnZLCHAXdfQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623086243; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gAJbwUpQBJlwWgZB9PVIfQPSDW4ziRgxMQ3yiyqe2ao=; b=dTIqFhD+Uw//0uFhmbJlhlVONsNbC/79srYcb4/RmAAeZ9l510JLcCwjNyjO1eVOIFrpKz7QWM5MHmTSCJlhzZ2pZGvKBLtEXzmK8IB5xn6j3EvMOYhKUZhk2DG/kEQaJKGzCJ3O3PMHq1mGSQq3OvzTiKpan1zVJwuMWldEl4o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623086243428103.05222716473588; Mon, 7 Jun 2021 10:17:23 -0700 (PDT) Received: from localhost ([::1]:57734 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqIsM-0006i6-7U for importer@patchew.org; Mon, 07 Jun 2021 13:17:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60046) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIb3-0007wK-Hc for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:29 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:44993) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIaX-000831-Qv for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:29 -0400 Received: by mail-wm1-x335.google.com with SMTP id p13-20020a05600c358db029019f44afc845so51469wmq.3 for ; Mon, 07 Jun 2021 09:58:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gAJbwUpQBJlwWgZB9PVIfQPSDW4ziRgxMQ3yiyqe2ao=; b=aUmxFFtZQWJo5CTaV9SLT3Wnif6/6MGQ/QMfscFfpC0FK1vqatawqoC/KiELenVhBL oBuC/3UAwlXgnuAE/iXF8pH+umTxhCyTAlg36C9S6GQbENj1wsSlhFqv8aw7SpY3ID+N DcgOJR0ynyxZ5WXnsqLCrGPoGYvtVHn9yz1pea4dLPKcyHcos6ZYaIuYkdmpQhGcFzkp 2+RrNxROpSRmWD+8yi6y7cHtRnP0Pp7eHnpmQHYzAD/adx7iF922aSLjafyO7AURZ4tA 6gkLrG/bMCup0gNUOK2rmM6snrM1WMle63g1XB6tpwigA5m99mU07lNiUdUgtUmPE1H/ jayg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gAJbwUpQBJlwWgZB9PVIfQPSDW4ziRgxMQ3yiyqe2ao=; b=XPOw/cGkx1+wLPIKZnxY4BvntAJwDS5MHMcrtVdqGGozmMWvtKZTX9MJaXPYZ5A3Wc fYcdQdGyR5gs+pKfV/CkepYgTVSKFY3xypAtOOjdqQ2VATrneSiun4O9KjUlvjsyKjXD 6k8kOM70SzvA0/dxwWu2jJ8zLv31plIE5QK5u3+hc9oOkJRLWldrbSnJwq/wWJOBg4XT CV+pLakMKcNvydcJxm7OoQLnaD2GxOH/maiQDmz2aXcNQY41fedcXOlSmo2JCKy7iMmg IH8zxok4hFrJflDZ6pTNK/thqpTrqBM2qKToSrOIXtR6xLTl+9nuk1JuLYJ7f6sIjH2X 50ng== X-Gm-Message-State: AOAM531IKNGmldqtzWqIA5ozwFW77wg7AkwN5BrXW4RWaJlJHVRf59sV bFZEh1ZFvR1YF25mvXt89Md28JPy4fv14sHI X-Google-Smtp-Source: ABdhPJxl/+YUo2QUoaZuv/eE1fiSOIEgSZR9nyQI6gZfZRqH6i6rn6+SBitkMYPNWEHxCTn/gHNWeg== X-Received: by 2002:a7b:cc8f:: with SMTP id p15mr57730wma.111.1623085133706; Mon, 07 Jun 2021 09:58:53 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 38/55] target/arm: Implement MVE VQADD and VQSUB Date: Mon, 7 Jun 2021 17:58:04 +0100 Message-Id: <20210607165821.9892-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VQADD and VQSUB insns, which perform saturating addition of a scalar to each element. Note that individual bytes of each result element are used or discarded according to the predicate mask, but FPSCR.QC is only set if the predicate mask for the lowest byte of the element is set. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 16 ++++++++++ target/arm/mve.decode | 5 +++ target/arm/mve_helper.c | 62 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 4 +++ 4 files changed, 87 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 1f77a661b9b..a1acc44e40e 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -175,6 +175,22 @@ DEF_HELPER_FLAGS_4(mve_vhsubu_scalarb, TCG_CALL_NO_WG,= void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vhsubu_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) DEF_HELPER_FLAGS_4(mve_vhsubu_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) =20 +DEF_HELPER_FLAGS_4(mve_vqadds_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vqadds_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vqadds_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) + +DEF_HELPER_FLAGS_4(mve_vqaddu_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vqaddu_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vqaddu_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) + +DEF_HELPER_FLAGS_4(mve_vqsubs_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vqsubs_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vqsubs_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) + +DEF_HELPER_FLAGS_4(mve_vqsubu_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vqsubu_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) +DEF_HELPER_FLAGS_4(mve_vqsubu_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) + DEF_HELPER_FLAGS_4(mve_vbrsrb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vbrsrh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vbrsrw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index e189e2de648..c85227c675a 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -167,6 +167,11 @@ VHADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 1= 00 .... @2scalar VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar + +VQADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 110 .... @2scalar +VQADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 110 .... @2scalar +VQSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 110 .... @2scalar +VQSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 110 .... @2scalar VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar =20 # Predicate operations diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 25426fae992..41c4f2033f6 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -477,6 +477,33 @@ DO_2OP_U(vhaddu, do_vhadd_u) DO_2OP_S(vhsubs, do_vhsub_s) DO_2OP_U(vhsubu, do_vhsub_u) =20 +static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bo= ol *s) +{ + if (val > max) { + *s =3D true; + return max; + } else if (val < min) { + *s =3D true; + return min; + } + return val; +} + +#define DO_SQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, INT8_MIN, INT8_MAX,= s) +#define DO_SQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, INT16_MIN, INT16_MA= X, s) +#define DO_SQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, INT32_MIN, INT32_MA= X, s) + +#define DO_UQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT8_MAX, s) +#define DO_UQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT16_MAX, s) +#define DO_UQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT32_MAX, s) + +#define DO_SQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, INT8_MIN, INT8_MAX,= s) +#define DO_SQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, INT16_MIN, INT16_MA= X, s) +#define DO_SQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, INT32_MIN, INT32_MA= X, s) + +#define DO_UQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT8_MAX, s) +#define DO_UQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT16_MAX, s) +#define DO_UQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT32_MAX, s) =20 #define DO_2OP_SCALAR(OP, ESIZE, TYPE, H, FN) \ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ @@ -495,6 +522,27 @@ DO_2OP_U(vhsubu, do_vhsub_u) mve_advance_vpt(env); \ } =20 +#define DO_2OP_SAT_SCALAR(OP, ESIZE, TYPE, H, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ + uint32_t rm) \ + { \ + TYPE *d =3D vd, *n =3D vn; = \ + TYPE m =3D rm; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + bool sat =3D false; \ + TYPE r =3D FN(n[H(e)], m, &sat); \ + uint64_t bytemask =3D mask_to_bytemask##ESIZE(mask); \ + d[H(e)] &=3D ~bytemask; \ + d[H(e)] |=3D (r & bytemask); \ + if (sat && (mask & 1)) { \ + env->vfp.qc[0] =3D 1; \ + } \ + } \ + mve_advance_vpt(env); \ + } + /* provide unsigned 2-op scalar helpers for all sizes */ #define DO_2OP_SCALAR_U(OP, FN) \ DO_2OP_SCALAR(OP##b, 1, uint8_t, H1, FN) \ @@ -513,6 +561,20 @@ DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u) DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s) DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u) =20 +DO_2OP_SAT_SCALAR(vqaddu_scalarb, 1, uint8_t, H1, DO_UQADD_B) +DO_2OP_SAT_SCALAR(vqaddu_scalarh, 2, uint16_t, H2, DO_UQADD_H) +DO_2OP_SAT_SCALAR(vqaddu_scalarw, 4, uint32_t, H4, DO_UQADD_W) +DO_2OP_SAT_SCALAR(vqadds_scalarb, 1, int8_t, H1, DO_SQADD_B) +DO_2OP_SAT_SCALAR(vqadds_scalarh, 2, int16_t, H2, DO_SQADD_H) +DO_2OP_SAT_SCALAR(vqadds_scalarw, 4, int32_t, H4, DO_SQADD_W) + +DO_2OP_SAT_SCALAR(vqsubu_scalarb, 1, uint8_t, H1, DO_UQSUB_B) +DO_2OP_SAT_SCALAR(vqsubu_scalarh, 2, uint16_t, H2, DO_UQSUB_H) +DO_2OP_SAT_SCALAR(vqsubu_scalarw, 4, uint32_t, H4, DO_UQSUB_W) +DO_2OP_SAT_SCALAR(vqsubs_scalarb, 1, int8_t, H1, DO_SQSUB_B) +DO_2OP_SAT_SCALAR(vqsubs_scalarh, 2, int16_t, H2, DO_SQSUB_H) +DO_2OP_SAT_SCALAR(vqsubs_scalarw, 4, int32_t, H4, DO_SQSUB_W) + static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) { m &=3D 0xff; diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 45a71a22853..254ff2a01b2 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -469,6 +469,10 @@ DO_2OP_SCALAR(VHADD_S_scalar, vhadds_scalar) DO_2OP_SCALAR(VHADD_U_scalar, vhaddu_scalar) DO_2OP_SCALAR(VHSUB_S_scalar, vhsubs_scalar) DO_2OP_SCALAR(VHSUB_U_scalar, vhsubu_scalar) +DO_2OP_SCALAR(VQADD_S_scalar, vqadds_scalar) +DO_2OP_SCALAR(VQADD_U_scalar, vqaddu_scalar) +DO_2OP_SCALAR(VQSUB_S_scalar, vqsubs_scalar) +DO_2OP_SCALAR(VQSUB_U_scalar, vqsubu_scalar) DO_2OP_SCALAR(VBRSR, vbrsr) =20 static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zIwanJ3AQdDQdQ1ALSTjRK7X+97mJn2Se8diVqTisuk=; b=MrgTTp1t7XftpPzgJSCedOUijNGkGUPIdSOM3QVD86TLoZGFdr5qEFuTm6LB6+ZJhi /3p9ScWndW9BBK1lzEbYFYUnVE5+k01d6v4niKA2g7iLqGLoXCLtOhgFOkLBmEAOEF5O nWwbptE0ql9kvE8fBqO5FrrIuibsOT0Y6p33TMnT97TBy93bfh5fQmSJZmIbChAFSUs/ 3HyZ5cJN7s0auQit1EOaxjlkOaL2FhO93ldtL0aneBmndlEFjIteALfZsozI8fTVZIGq AzJK+rv9tQ93ebZP8h0wpO2C5mRcWLcYFuLiKVJ5SpEXvIdr+UTLHBZspkQT0NmiEXdW 8C4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zIwanJ3AQdDQdQ1ALSTjRK7X+97mJn2Se8diVqTisuk=; b=PzdityQHQvUkqgtOLIO4t3ybQ5SIGPcIS8iRsQeKP11rIv2w9FMixwOVmWHZDCAle4 nkGHNFMik0mzLr82pJ6po2vhgBbsR9e28ilVqMGeb2zhtHYmlKuvmxitbrb6vYW/kEOj XlLGyhr3M/O7klvGCHEm41JVBG1aDzkZuEWLU8m1Dq7HvPj1DqjEGj1wvhLoNKJ72d4e aWdq3lhwdNaOpiX9yHaBl61MhdAUcZdZY6yDqOlzEX9/V5TnzLwVoEwcmA1oHiP0tcRx anEagbZqFU5Mhi+cPt6aMRtF0NbeZeXSsRAFOi47TrPw3pH5yRVWK6+2uQfQl/XtBIIX S1YQ== X-Gm-Message-State: AOAM53374zURKJpzo0Rlc8b+/68TdKbYvX4SBt7aJUzdVoWzA23LjQ82 kcEm4xRqFKqOCGfr8aHNqo+2DhqQMtA/DXYi X-Google-Smtp-Source: ABdhPJzaJvxKKVYsgmQyR6s247Xid6dIQhBQSOBM6B39uTIr97LjiOxZTCSq33LTVlQHiMUQn3GlMQ== X-Received: by 2002:a7b:cf18:: with SMTP id l24mr74397wmg.160.1623085134420; Mon, 07 Jun 2021 09:58:54 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 39/55] target/arm: Implement MVE VQDMULH and VQRDMULH (scalar) Date: Mon, 7 Jun 2021 17:58:05 +0100 Message-Id: <20210607165821.9892-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VQDMULH and VQRDMULH scalar insns, which multiply elements by the scalar, double, possibly round, take the high half and saturate. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 8 ++++++++ target/arm/mve.decode | 3 +++ target/arm/mve_helper.c | 25 +++++++++++++++++++++++++ target/arm/translate-mve.c | 2 ++ 4 files changed, 38 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index a1acc44e40e..9bab04305a7 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -191,6 +191,14 @@ DEF_HELPER_FLAGS_4(mve_vqsubu_scalarb, TCG_CALL_NO_WG,= void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vqsubu_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) DEF_HELPER_FLAGS_4(mve_vqsubu_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr= , i32) =20 +DEF_HELPER_FLAGS_4(mve_vqdmulh_scalarb, TCG_CALL_NO_WG, void, env, ptr, pt= r, i32) +DEF_HELPER_FLAGS_4(mve_vqdmulh_scalarh, TCG_CALL_NO_WG, void, env, ptr, pt= r, i32) +DEF_HELPER_FLAGS_4(mve_vqdmulh_scalarw, TCG_CALL_NO_WG, void, env, ptr, pt= r, i32) + +DEF_HELPER_FLAGS_4(mve_vqrdmulh_scalarb, TCG_CALL_NO_WG, void, env, ptr, p= tr, i32) +DEF_HELPER_FLAGS_4(mve_vqrdmulh_scalarh, TCG_CALL_NO_WG, void, env, ptr, p= tr, i32) +DEF_HELPER_FLAGS_4(mve_vqrdmulh_scalarw, TCG_CALL_NO_WG, void, env, ptr, p= tr, i32) + DEF_HELPER_FLAGS_4(mve_vbrsrb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vbrsrh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vbrsrw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index c85227c675a..47ce6ebb83b 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -174,6 +174,9 @@ VQSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 11= 0 .... @2scalar VQSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 110 .... @2scalar VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar =20 +VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar +VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar + # Predicate operations %mask_22_13 22:1 13:3 VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=3D%mask_= 22_13 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 41c4f2033f6..6e2da6ac8bc 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -505,6 +505,24 @@ static inline int32_t do_sat_bhw(int64_t val, int64_t = min, int64_t max, bool *s) #define DO_UQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT16_MAX, s) #define DO_UQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT32_MAX, s) =20 +/* + * For QDMULH and QRDMULH we simplify "double and shift by esize" into + * "shift by esize-1", adjusting the QRDMULH rounding constant to match. + */ +#define DO_QDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m) >> 7, \ + INT8_MIN, INT8_MAX, s) +#define DO_QDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m) >> 15, \ + INT16_MIN, INT16_MAX, s) +#define DO_QDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m) >> 31, \ + INT32_MIN, INT32_MAX, s) + +#define DO_QRDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 6)) >> 7,= \ + INT8_MIN, INT8_MAX, s) +#define DO_QRDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 14)) >> 1= 5, \ + INT16_MIN, INT16_MAX, s) +#define DO_QRDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 30)) >> 3= 1, \ + INT32_MIN, INT32_MAX, s) + #define DO_2OP_SCALAR(OP, ESIZE, TYPE, H, FN) \ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ uint32_t rm) \ @@ -575,6 +593,13 @@ DO_2OP_SAT_SCALAR(vqsubs_scalarb, 1, int8_t, H1, DO_SQ= SUB_B) DO_2OP_SAT_SCALAR(vqsubs_scalarh, 2, int16_t, H2, DO_SQSUB_H) DO_2OP_SAT_SCALAR(vqsubs_scalarw, 4, int32_t, H4, DO_SQSUB_W) =20 +DO_2OP_SAT_SCALAR(vqdmulh_scalarb, 1, int8_t, H1, DO_QDMULH_B) +DO_2OP_SAT_SCALAR(vqdmulh_scalarh, 2, int16_t, H2, DO_QDMULH_H) +DO_2OP_SAT_SCALAR(vqdmulh_scalarw, 4, int32_t, H4, DO_QDMULH_W) +DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, H1, DO_QRDMULH_B) +DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, H2, DO_QRDMULH_H) +DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, H4, DO_QRDMULH_W) + static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) { m &=3D 0xff; diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 254ff2a01b2..4d08067c1e2 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -473,6 +473,8 @@ DO_2OP_SCALAR(VQADD_S_scalar, vqadds_scalar) DO_2OP_SCALAR(VQADD_U_scalar, vqaddu_scalar) DO_2OP_SCALAR(VQSUB_S_scalar, vqsubs_scalar) DO_2OP_SCALAR(VQSUB_U_scalar, vqsubu_scalar) +DO_2OP_SCALAR(VQDMULH_scalar, vqdmulh_scalar) +DO_2OP_SCALAR(VQRDMULH_scalar, vqrdmulh_scalar) DO_2OP_SCALAR(VBRSR, vbrsr) =20 static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623087479; cv=none; d=zohomail.com; s=zohoarc; b=kELIRTkNuNbodz44taDYt4JjcC081oKJ3PbNk0LiBmzC/DYrEBaeNPxMkvKOMcfRBjxKdrDxJnbPU/B0GqV07qv1EvEJBiPsW8lkphb5BuQWhj+lcA6ZLQDN/kvesMKSc7Z48bxYcFVvpEJgA0cLDd6itnZ5/5+hkmeLjd15AA4= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=anbdlQ0MeG9A8VNndTUQIgTacTr2CcYrD7NBwwj0pVc=; b=F6kk+G8nCkPGnZWPcvhrtySV8it7V5gdd1EnpmqfJIH8dVWWOYXSLdjcJg/ljhYoXW eNuaJoY29WM7HbulJccPd6WpAkJg5oJLavkYcr8AT/xkXiRIEMHe0ruYAkTU3xoUFtR+ cUntiSb4tIYjwkbn6UvouBuSO4AKc1c7H4UBA0U0vmtGRzRCGx8jpLRM5Qx9GfJghchY cZRXHRVPY2wbfi5f3GzRTVwUFWOO2Vk2NldCxpD7XgsBbc6uwB2G6Du2ygW56x8o1rGw t/TVrgcyVMQ66SHeT85ZNfDjip85GJJ4ynK4sdTbPae+IliQARM/b5Vzk95hRBS++bFf V5Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=anbdlQ0MeG9A8VNndTUQIgTacTr2CcYrD7NBwwj0pVc=; b=Z0gL7BNpJ/P/pbva0/HOaO2kM1AhejORGqBG1QQB8IMmVVls4Hn0FlK4QmO1xfnZB/ vnH+eArTVSn3wHeBLS2bCg4hqo8huELsaZJ0LPCzqGk85o43MojcPx1Q/7CH5eM9OxQl 7m52X3VA7AgxSXfugbstT4vQKGQHXnsErgLGT2Yo4FCwI8GIJ30x7u3MVAnpFHZ+xXf1 pqBjqxsT2loJ5crK5xtNpCqD8ZSw7Ut+vN/smdRdaBCWIRxYUsROdONyH+n1Q8idsojn ePeh2ayJwufbZsH7W1CKS+mk8we+mnlxUeYSMNptHh9pLH3ySKu12dxvJJHwJ8GOCRBz hbvA== X-Gm-Message-State: AOAM533bX4YyfPdPrzrDdiitUFV1O7IBaQnkrEPZBQ7o6QEMpy/fysSa KnrzqvXc8ZxrXYWS+O+EewiPMgIw3/fp6ZFS X-Google-Smtp-Source: ABdhPJw4jZ4yvkFgWcmhfJ59nxJClVSMFS3tyYOKMAIt2s16ePTCudiThcnLzMXvEEg0VQH4pmMTyg== X-Received: by 2002:a7b:c2e8:: with SMTP id e8mr13194594wmk.41.1623085135212; Mon, 07 Jun 2021 09:58:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 40/55] target/arm: Implement MVE VQDMULL scalar Date: Mon, 7 Jun 2021 17:58:06 +0100 Message-Id: <20210607165821.9892-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VQDMULL scalar insn. This multiplies the top or bottom half of each element by the scalar, doubles and saturates to a double-width result. Note that this encoding overlaps with VQADD and VQSUB; it uses what in VQADD and VQSUB would be the 'size=3D0b11' encoding. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 5 +++ target/arm/mve.decode | 23 +++++++++++--- target/arm/mve_helper.c | 65 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 30 ++++++++++++++++++ 4 files changed, 119 insertions(+), 4 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 9bab04305a7..55c4e41deff 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -203,6 +203,11 @@ DEF_HELPER_FLAGS_4(mve_vbrsrb, TCG_CALL_NO_WG, void, e= nv, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vbrsrh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) DEF_HELPER_FLAGS_4(mve_vbrsrw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(mve_vqdmullb_scalarh, TCG_CALL_NO_WG, void, env, ptr, p= tr, i32) +DEF_HELPER_FLAGS_4(mve_vqdmullb_scalarw, TCG_CALL_NO_WG, void, env, ptr, p= tr, i32) +DEF_HELPER_FLAGS_4(mve_vqdmullt_scalarh, TCG_CALL_NO_WG, void, env, ptr, p= tr, i32) +DEF_HELPER_FLAGS_4(mve_vqdmullt_scalarw, TCG_CALL_NO_WG, void, env, ptr, p= tr, i32) + DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i6= 4) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 47ce6ebb83b..a71ad7252bf 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -23,6 +23,9 @@ %qm 5:1 1:3 %qn 7:1 17:3 =20 +# VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit +%size_28 28:1 !function=3Dplus_1 + &vldr_vstr rn qd imm p a w size l u &1op qd qm size &2op qd qm qn size @@ -38,6 +41,7 @@ @2op_nosz .... .... .... .... .... .... .... .... &2op qd=3D%qd qm=3D%qm q= n=3D%qn size=3D0 =20 @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=3D%qd qn= =3D%qn +@2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=3D%qd qn= =3D%qn =20 # Vector loads and stores =20 @@ -168,15 +172,26 @@ VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . = 100 .... @2scalar VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar =20 -VQADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 110 .... @2scalar -VQADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 110 .... @2scalar -VQSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 110 .... @2scalar -VQSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 110 .... @2scalar +{ + VQADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 110 .... @2scalar + VQADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 110 .... @2scalar + VQDMULLB_scalar 111 . 1110 0 . 11 ... 0 ... 0 1111 . 110 .... @2scalar_n= osz \ + size=3D%size_28 +} + +{ + VQSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 110 .... @2scalar + VQSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 110 .... @2scalar + VQDMULLT_scalar 111 . 1110 0 . 11 ... 0 ... 1 1111 . 110 .... @2scalar_n= osz \ + size=3D%size_28 +} + VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar =20 VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar =20 + # Predicate operations %mask_22_13 22:1 13:3 VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=3D%mask_= 22_13 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 6e2da6ac8bc..97529531ed0 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -600,6 +600,71 @@ DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, H1, DO_= QRDMULH_B) DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, H2, DO_QRDMULH_H) DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, H4, DO_QRDMULH_W) =20 +/* + * Long saturating scalar ops. As with DO_2OP_L, TYPE and H are for the + * input (smaller) type and LESIZE, LTYPE, LH for the output (long) type. + * SATMASK specifies which bits of the predicate mask matter for determini= ng + * whether to propagate a saturation indication into FPSCR.QC -- for + * the 16x16->32 case we must check only the bit corresponding to the T or= B + * half that we used, but for the 32x32->64 case we propagate if the mask + * bit is set for either half. + */ +#define DO_2OP_SAT_SCALAR_L(OP, TOP, TYPE, H, LESIZE, LTYPE, LH, FN, SATMA= SK) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ + uint32_t rm) \ + { \ + LTYPE *d =3D vd; \ + TYPE *n =3D vn; \ + TYPE m =3D rm; \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned le; \ + for (le =3D 0; le < 16 / LESIZE; le++, mask >>=3D LESIZE) { = \ + bool sat =3D false; \ + LTYPE r =3D FN((LTYPE)n[H(le * 2 + TOP)], m, &sat); \ + uint64_t bytemask =3D mask_to_bytemask##LESIZE(mask); \ + d[LH(le)] &=3D ~bytemask; \ + d[LH(le)] |=3D (r & bytemask); \ + if (sat && (mask & SATMASK)) { \ + env->vfp.qc[0] =3D 1; \ + } \ + } \ + mve_advance_vpt(env); \ + } + +static inline int32_t do_qdmullh(int16_t n, int16_t m, bool *sat) +{ + int64_t r =3D ((int64_t)n * m) * 2; + return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat); +} + +static inline int64_t do_qdmullw(int32_t n, int32_t m, bool *sat) +{ + /* The multiply can't overflow, but the doubling might */ + int64_t r =3D (int64_t)n * m; + if (r > INT64_MAX / 2) { + *sat =3D true; + return INT64_MAX; + } else if (r < INT64_MIN / 2) { + *sat =3D true; + return INT64_MIN; + } else { + return r * 2; + } +} + +#define SATMASK16B 1 +#define SATMASK16T (1 << 2) +#define SATMASK32 ((1 << 4) | 1) + +DO_2OP_SAT_SCALAR_L(vqdmullb_scalarh, 0, int16_t, H2, 4, int32_t, H4, \ + do_qdmullh, SATMASK16B) +DO_2OP_SAT_SCALAR_L(vqdmullb_scalarw, 0, int32_t, H4, 8, int64_t, , \ + do_qdmullw, SATMASK32) +DO_2OP_SAT_SCALAR_L(vqdmullt_scalarh, 1, int16_t, H2, 4, int32_t, H4, \ + do_qdmullh, SATMASK16T) +DO_2OP_SAT_SCALAR_L(vqdmullt_scalarw, 1, int32_t, H4, 8, int64_t, , \ + do_qdmullw, SATMASK32) + static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) { m &=3D 0xff; diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 4d08067c1e2..2bb7482e6af 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -477,6 +477,36 @@ DO_2OP_SCALAR(VQDMULH_scalar, vqdmulh_scalar) DO_2OP_SCALAR(VQRDMULH_scalar, vqrdmulh_scalar) DO_2OP_SCALAR(VBRSR, vbrsr) =20 +static bool trans_VQDMULLB_scalar(DisasContext *s, arg_2scalar *a) +{ + MVEGenTwoOpScalarFn *fns[] =3D { + NULL, + gen_helper_mve_vqdmullb_scalarh, + gen_helper_mve_vqdmullb_scalarw, + NULL, + }; + if (a->qd =3D=3D a->qn && a->size =3D=3D MO_32) { + /* UNPREDICTABLE; we choose to undef */ + return false; + } + return do_2op_scalar(s, a, fns[a->size]); +} + +static bool trans_VQDMULLT_scalar(DisasContext *s, arg_2scalar *a) +{ + MVEGenTwoOpScalarFn *fns[] =3D { + NULL, + gen_helper_mve_vqdmullt_scalarh, + gen_helper_mve_vqdmullt_scalarw, + NULL, + }; + if (a->qd =3D=3D a->qn && a->size =3D=3D MO_32) { + /* UNPREDICTABLE; we choose to undef */ + return false; + } + return do_2op_scalar(s, a, fns[a->size]); +} + static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, MVEGenDualAccOpFn *fn) { --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623088147; cv=none; d=zohomail.com; s=zohoarc; b=fNplI1YB6bH+jlXRb9rxYIpnZIwmnieTN2iiXOoyMqOtJr4tgIlDizgpAYYh0lN/EvCFRPTnj8D4c9QEH6wfxZIOc9Z4RUiWGWQ7zjIyBMnMqYldwEO2FzffFbwVRhYDK37FCgzJwHIjgiMzprmDfNUOtwLcTyzCeQOlAQ69OUs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623088147; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1WD5R16SCIkydee14wkB4oUuOr6qYBE+bCok0uIGeuo=; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1WD5R16SCIkydee14wkB4oUuOr6qYBE+bCok0uIGeuo=; b=r071pn/D6zqXKvFKFgzX/p1/Z6w3tE054xAmt4Ps7O9t0d2pFvNW6x12mRwRzkY3v4 hHoK3uQ3o7li+vBBzZv0mXgRuEh8FwQr63AupLlbq9IDtvM2juqttwXFjRbprMm+ebnL qU/kuG/gA4vy+HEOqAIo5b0d4l+WGhxKZYIeyzJ+sESVMSy4WZcTAZdi2N//AZwyb/6s Pnmp10lPjwx3S2x0fG4egWe6L/oXNBZRjoueMFhmw2N4yathE78Xt271fkQzGKjAtQtZ ClBaEjtwLrIsRjFa0MCmtwX/75hjiOf1Ncs4eMUVK5BquFVclndmm1lKm9/AcvMljJvF 1gQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1WD5R16SCIkydee14wkB4oUuOr6qYBE+bCok0uIGeuo=; b=mAu6Vm4FZqXR//E2soL6moWVDRMoxH4JfvRrD1CSD1hDlyqk7Co5dXo8GMEqX/OsCR T1Y8j595A/cLjsMRZael4JBv/0MsKynxNgXDpTvPh8m0dsUKXkeLlF6wx0FT+OqVg6PC X3CzNqvRtpkcS42vDPtDSryo9xfGvvMVTjJYUjFSrrkdNY+N99gU8fqFxe3qfGigKWl7 zKwP9tckQN9XN5f3ZFfm3cRge75Aj3eh7GratI6KhvJcZPV+IPhZb9rUFuv4z5SgAiic 1AQmZLIjrawOrBwV5D+y8exqtn6lfk6GBV2HifEY5WN7lA1G2OJ7Q1AfpGXLdBQH4lT0 cpmg== X-Gm-Message-State: AOAM533HEq14Mhtfnn7XaqtyVtAN+gWqTJiIhkOqu+BtQLUkhV4+MhP9 SSfqMFZORIfIX0xam9ijHd7Y/WiENxt0pTSF X-Google-Smtp-Source: ABdhPJxoM/cwaKYHJZelpZxqZh+7+oVIv1tMUZII9PX9hhIGRDn5oRh4tYxkF3zfdd278Wwl+dR05w== X-Received: by 2002:a05:600c:3790:: with SMTP id o16mr65164wmr.41.1623085136048; Mon, 07 Jun 2021 09:58:56 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 41/55] target/arm: Implement MVE VQDMULH, VQRDMULH (vector) Date: Mon, 7 Jun 2021 17:58:07 +0100 Message-Id: <20210607165821.9892-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the vector forms of the MVE VQDMULH and VQRDMULH insns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 8 ++++++++ target/arm/mve.decode | 3 +++ target/arm/mve_helper.c | 27 +++++++++++++++++++++++++++ target/arm/translate-mve.c | 2 ++ 4 files changed, 40 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 55c4e41deff..a7eddf3d488 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -147,6 +147,14 @@ DEF_HELPER_FLAGS_4(mve_vmulltub, TCG_CALL_NO_WG, void,= env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vmulltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vmulltuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vqdmulhb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqdmulhh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqdmulhw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vqrdmulhb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqrdmulhh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqrdmulhw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index a71ad7252bf..9860d43f73c 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -113,6 +113,9 @@ VMULL_BU 111 1 1110 0 . .. ... 1 ... 0 1110 . 0= . 0 ... 0 @2op VMULL_TS 111 0 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op VMULL_TU 111 1 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op =20 +VQDMULH 1110 1111 0 . .. ... 0 ... 0 1011 . 1 . 0 ... 0 @2op +VQRDMULH 1111 1111 0 . .. ... 0 ... 0 1011 . 1 . 0 ... 0 @2op + # Vector miscellaneous =20 VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 97529531ed0..7d65bcef56c 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -357,6 +357,25 @@ DO_1OP(vfnegs, 4, uint32_t, H4, DO_FNEG) mve_advance_vpt(env); \ } =20 +#define DO_2OP_SAT(OP, ESIZE, TYPE, H, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void= *vm) \ + { \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + bool sat =3D false; \ + TYPE r =3D FN(n[H(e)], m[H(e)], &sat); \ + uint64_t bytemask =3D mask_to_bytemask##ESIZE(mask); \ + d[H(e)] &=3D ~bytemask; \ + d[H(e)] |=3D (r & bytemask); \ + if (sat && (mask & 1)) { \ + env->vfp.qc[0] =3D 1; \ + } \ + } \ + mve_advance_vpt(env); \ + } + #define DO_AND(N, M) ((N) & (M)) #define DO_BIC(N, M) ((N) & ~(M)) #define DO_ORR(N, M) ((N) | (M)) @@ -523,6 +542,14 @@ static inline int32_t do_sat_bhw(int64_t val, int64_t = min, int64_t max, bool *s) #define DO_QRDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 30)) >> 3= 1, \ INT32_MIN, INT32_MAX, s) =20 +DO_2OP_SAT(vqdmulhb, 1, int8_t, H1, DO_QDMULH_B) +DO_2OP_SAT(vqdmulhh, 2, int16_t, H2, DO_QDMULH_H) +DO_2OP_SAT(vqdmulhw, 4, int32_t, H4, DO_QDMULH_W) + +DO_2OP_SAT(vqrdmulhb, 1, int8_t, H1, DO_QRDMULH_B) +DO_2OP_SAT(vqrdmulhh, 2, int16_t, H2, DO_QRDMULH_H) +DO_2OP_SAT(vqrdmulhw, 4, int32_t, H4, DO_QRDMULH_W) + #define DO_2OP_SCALAR(OP, ESIZE, TYPE, H, FN) \ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ uint32_t rm) \ diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 2bb7482e6af..213a90b59b6 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -415,6 +415,8 @@ DO_2OP(VMULL_BS, vmullbs) DO_2OP(VMULL_BU, vmullbu) DO_2OP(VMULL_TS, vmullts) DO_2OP(VMULL_TU, vmulltu) +DO_2OP(VQDMULH, vqdmulh) +DO_2OP(VQRDMULH, vqrdmulh) =20 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DDQF52g8vN6c9/t7lxs56B/f0m6nbSLusEKrn4THl4Q=; b=V6RMZq4WHuj9V/RXel7MSYYzZRmpfcPwOFBL9ZPvM/kfecF5gpYdPRNx9NV80EQOlY i8EHwxIcdEErJYwg4y6XaTvncZedxAehSn3obNahBtGnILkCb6poXO3BzyC5PCkL8zo1 bNIVthdAY1cwxKj3/uMNf1D69YL376uFSNzTBxMYmMZUMY4rDQjRIkqUKjSNq9K4/E57 xt8kjN1svgrZWyu7OQkQlSKpi2tYvRUQJvNT3UpEekrEWF4iRnOz1HMmccRj0yj6bSHC gubaTu6VbOJABHhQwhrJZAEG7Xlux4zpOAbkd3xsvhV8WvP5WVN69sEJAtv26IqOg2Qk qYDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DDQF52g8vN6c9/t7lxs56B/f0m6nbSLusEKrn4THl4Q=; b=ghxpTJjl313lWwctQQ75/d2rWuGBrGvJYk6ktJ9/WYC/YyX/eS3v765YsUL2ayYTwk PIycaxgue8KBAl9dwk8lnvh6tveGLHi5VNKu1OZJAUhrM85xZLsjhU5G2bBSfAxOk2hu NXBtHvGPguBFIybrjolFRx3S+L9RzACBW/1mdxeOZptoynz1C2VNw1RKXLwVxMTAdZWk DjBMPmlZk8T61czhOtxWKYUK+cQk8QC+sEhoLDHImtVnNp3ke0D6+9LlvqW5vZ+km32k FXzN0/Z3sfOOJtryTO+aI7c3nExCB/CvlhTJXN/A4Ce6vdqcwDsJhxRkdbM1KUVbw1Zy Wbcw== X-Gm-Message-State: AOAM5333X9sBq+LgbGYJuQC3ndoJO/vsN+rWgfQySGkYibc2orwpd2cm j1rUk7LdAvsgNfOp/MGLoB7JGg== X-Google-Smtp-Source: ABdhPJzdUHqNRDt8XXVXxpy8qy1oiRA5+LL1dmbuWvcXizuXP3r+3FIoATrV6BzUnelq/o3vGWzVvw== X-Received: by 2002:a5d:5388:: with SMTP id d8mr17602901wrv.423.1623085136758; Mon, 07 Jun 2021 09:58:56 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 42/55] target/arm: Implement MVE VQADD, VQSUB (vector) Date: Mon, 7 Jun 2021 17:58:08 +0100 Message-Id: <20210607165821.9892-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the vector forms of the MVE VQADD and VQSUB insns. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 16 ++++++++++++++++ target/arm/mve.decode | 5 +++++ target/arm/mve_helper.c | 14 ++++++++++++++ target/arm/translate-mve.c | 4 ++++ 4 files changed, 39 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index a7eddf3d488..9801a39a984 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -155,6 +155,22 @@ DEF_HELPER_FLAGS_4(mve_vqrdmulhb, TCG_CALL_NO_WG, void= , env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqrdmulhh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqrdmulhw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vqaddsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqaddsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqaddsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vqaddub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqadduh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqadduw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vqsubsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqsubsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqsubsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vqsubub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqsubuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqsubuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 9860d43f73c..80fa647c08f 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -116,6 +116,11 @@ VMULL_TU 111 1 1110 0 . .. ... 1 ... 1 1110 . = 0 . 0 ... 0 @2op VQDMULH 1110 1111 0 . .. ... 0 ... 0 1011 . 1 . 0 ... 0 @2op VQRDMULH 1111 1111 0 . .. ... 0 ... 0 1011 . 1 . 0 ... 0 @2op =20 +VQADD_S 111 0 1111 0 . .. ... 0 ... 0 0000 . 1 . 1 ... 0 @2op +VQADD_U 111 1 1111 0 . .. ... 0 ... 0 0000 . 1 . 1 ... 0 @2op +VQSUB_S 111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op +VQSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op + # Vector miscellaneous =20 VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 7d65bcef56c..d3562f80026 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -550,6 +550,20 @@ DO_2OP_SAT(vqrdmulhb, 1, int8_t, H1, DO_QRDMULH_B) DO_2OP_SAT(vqrdmulhh, 2, int16_t, H2, DO_QRDMULH_H) DO_2OP_SAT(vqrdmulhw, 4, int32_t, H4, DO_QRDMULH_W) =20 +DO_2OP_SAT(vqaddub, 1, uint8_t, H1, DO_UQADD_B) +DO_2OP_SAT(vqadduh, 2, uint16_t, H2, DO_UQADD_H) +DO_2OP_SAT(vqadduw, 4, uint32_t, H4, DO_UQADD_W) +DO_2OP_SAT(vqaddsb, 1, int8_t, H1, DO_SQADD_B) +DO_2OP_SAT(vqaddsh, 2, int16_t, H2, DO_SQADD_H) +DO_2OP_SAT(vqaddsw, 4, int32_t, H4, DO_SQADD_W) + +DO_2OP_SAT(vqsubub, 1, uint8_t, H1, DO_UQSUB_B) +DO_2OP_SAT(vqsubuh, 2, uint16_t, H2, DO_UQSUB_H) +DO_2OP_SAT(vqsubuw, 4, uint32_t, H4, DO_UQSUB_W) +DO_2OP_SAT(vqsubsb, 1, int8_t, H1, DO_SQSUB_B) +DO_2OP_SAT(vqsubsh, 2, int16_t, H2, DO_SQSUB_H) +DO_2OP_SAT(vqsubsw, 4, int32_t, H4, DO_SQSUB_W) + #define DO_2OP_SCALAR(OP, ESIZE, TYPE, H, FN) \ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ uint32_t rm) \ diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 213a90b59b6..957e7e48fab 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -417,6 +417,10 @@ DO_2OP(VMULL_TS, vmullts) DO_2OP(VMULL_TU, vmulltu) DO_2OP(VQDMULH, vqdmulh) DO_2OP(VQRDMULH, vqrdmulh) +DO_2OP(VQADD_S, vqadds) +DO_2OP(VQADD_U, vqaddu) +DO_2OP(VQSUB_S, vqsubs) +DO_2OP(VQSUB_U, vqsubu) =20 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M/dbcaZ35VQzjGpYiGimMfbRRlmi/LegWLbSCLBzEsU=; b=ckDAKhYSQBLEHp+PgdJs+oTxk/8JahS9RzVq58iiAfEgbafTG/AAu5rVYIP+PM0K3z bTIs9RbsMWEzqX3+6XnhD3+1iofwA3p1+sY/NmGFRBhz2i2l6HQZT5vcmBIpYw3lWgb5 vPjHw3M0tPncaccjx3F70zj60/gWLOhK5xqa3nThJD5bkGito2RUjaR6/DEdR4mWtc4k PWwZ9otNlRC8a3NtGQJoi6DOFsBSqflzyp6Tv04MLyqfyG9Cl0yam6kQ5EzDtWc8wspc 6IpMc5nSDnY4Arg7Rn4kqKfWVdAg059H0ELwSnQQm9PvE8BcLkxRN4/LoHA8uCeTqhs3 GJTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M/dbcaZ35VQzjGpYiGimMfbRRlmi/LegWLbSCLBzEsU=; b=eay+VKmcCaeIGrA2o7zp9AgPmUvb0ZBzTZWf6KMRUhwyxgsmxJa14zFrrJJSTJVAzN weoYe9+MfWiJakdyqusp9BHEm4fokREQTcfRyG3M7el2aboOsCpMR0usl4c8IxkDhoif k5joc+zudQtL85CWaDetxm/gsJfYEizg3FgF5Jv4yN97Eh1pD+yyiDLB/6vljEQCJteR EyB3Z/SUy/36Da/PuQNyS7m3idrUmCdDhKFKlRw04WsEj2KdDrnPzO3JEcatOUtus6tY 1Ax219oMWEOOl1N1lWk/W3L6lR+G5STyP9vFNT4sWBfIwGal8D9BfpZitB+qgngvy1mx H7Sg== X-Gm-Message-State: AOAM532h0BET9LiFmQEItBf41KM8FC4Q/mnAkf3kCzKg5DuoMMpqG3wU Tp07D4B4vRPAo14jgmUmkPQhCQ== X-Google-Smtp-Source: ABdhPJzVAppxoN6P9xtLw34zd1qJbvgQFnc7c0nEwMXjvrbPOXQfCFjVRVL8lRtTk/VANiXEyswdcg== X-Received: by 2002:a05:600c:190c:: with SMTP id j12mr18271551wmq.42.1623085137502; Mon, 07 Jun 2021 09:58:57 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 43/55] target/arm: Implement MVE VQSHL (vector) Date: Mon, 7 Jun 2021 17:58:09 +0100 Message-Id: <20210607165821.9892-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VQSHL insn (encoding T4, which is the vector-shift-by-vector version). The DO_SQSHL_OP and DO_UQSHL_OP macros here are derived from the neon_helper.c code for qshl_u{8,16,32} and qshl_s{8,16,32}. Signed-off-by: Peter Maydell --- target/arm/helper-mve.h | 8 +++++ target/arm/mve.decode | 12 +++++++ target/arm/mve_helper.c | 73 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 2 ++ 4 files changed, 95 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 9801a39a984..352b6a46a5e 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -171,6 +171,14 @@ DEF_HELPER_FLAGS_4(mve_vqsubub, TCG_CALL_NO_WG, void, = env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqsubuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqsubuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vqshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vqshlub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 80fa647c08f..2c37e265765 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -40,6 +40,15 @@ @2op .... .... .. size:2 .... .... .... .... .... &2op qd=3D%qd qm=3D%qm q= n=3D%qn @2op_nosz .... .... .... .... .... .... .... .... &2op qd=3D%qd qm=3D%qm q= n=3D%qn size=3D0 =20 +# The _rev suffix indicates that Vn and Vm are reversed. This is +# the case for shifts. In the Arm ARM these insns are documented +# with the Vm and Vn fields in their usual places, but in the +# assembly the operands are listed "backwards", ie in the order +# Qd, Qm, Qn where other insns use Qd, Qn, Qm. For QEMU we choose +# to consider Vm and Vn as being in different fields in the insn. +# This gives us consistency with A64 and Neon. +@2op_rev .... .... .. size:2 .... .... .... .... .... &2op qd=3D%qd qm=3D%= qn qn=3D%qm + @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=3D%qd qn= =3D%qn @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=3D%qd qn= =3D%qn =20 @@ -121,6 +130,9 @@ VQADD_U 111 1 1111 0 . .. ... 0 ... 0 0000 . 1= . 1 ... 0 @2op VQSUB_S 111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op VQSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op =20 +VQSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev +VQSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev + # Vector miscellaneous =20 VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index d3562f80026..7ac41cb1460 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -376,6 +376,18 @@ DO_1OP(vfnegs, 4, uint32_t, H4, DO_FNEG) mve_advance_vpt(env); \ } =20 +/* provide unsigned 2-op helpers for all sizes */ +#define DO_2OP_SAT_U(OP, FN) \ + DO_2OP_SAT(OP##b, 1, uint8_t, H1, FN) \ + DO_2OP_SAT(OP##h, 2, uint16_t, H2, FN) \ + DO_2OP_SAT(OP##w, 4, uint32_t, H4, FN) + +/* provide signed 2-op helpers for all sizes */ +#define DO_2OP_SAT_S(OP, FN) \ + DO_2OP_SAT(OP##b, 1, int8_t, H1, FN) \ + DO_2OP_SAT(OP##h, 2, int16_t, H2, FN) \ + DO_2OP_SAT(OP##w, 4, int32_t, H4, FN) + #define DO_AND(N, M) ((N) & (M)) #define DO_BIC(N, M) ((N) & ~(M)) #define DO_ORR(N, M) ((N) | (M)) @@ -564,6 +576,67 @@ DO_2OP_SAT(vqsubsb, 1, int8_t, H1, DO_SQSUB_B) DO_2OP_SAT(vqsubsh, 2, int16_t, H2, DO_SQSUB_H) DO_2OP_SAT(vqsubsw, 4, int32_t, H4, DO_SQSUB_W) =20 +#define DO_SQSHL_OP(src1, src2, satp) \ + ({ \ + int8_t tmp; \ + typeof(src1) dest; \ + tmp =3D (int8_t)src2; \ + if (tmp >=3D (ssize_t)sizeof(src1) * 8) { \ + if (src1) { \ + *satp =3D true; \ + dest =3D (uint32_t)(1 << (sizeof(src1) * 8 - 1)); \ + if (src1 > 0) { \ + dest--; \ + } \ + } else { \ + dest =3D src1; \ + } \ + } else if (tmp <=3D -(ssize_t)sizeof(src1) * 8) { \ + dest =3D src1 >> 31; \ + } else if (tmp < 0) { \ + dest =3D src1 >> -tmp; \ + } else { \ + dest =3D src1 << tmp; \ + if ((dest >> tmp) !=3D src1) { \ + *satp =3D true; \ + dest =3D (uint32_t)(1 << (sizeof(src1) * 8 - 1)); \ + if (src1 > 0) { \ + dest--; \ + } \ + } \ + } \ + dest; \ + }) + +#define DO_UQSHL_OP(src1, src2, satp) \ + ({ \ + int8_t tmp; \ + typeof(src1) dest; \ + tmp =3D (int8_t)src2; \ + if (tmp >=3D (ssize_t)sizeof(src1) * 8) { \ + if (src1) { \ + *satp =3D true; \ + dest =3D ~0; \ + } else { \ + dest =3D 0; \ + } \ + } else if (tmp <=3D -(ssize_t)sizeof(src1) * 8) { \ + dest =3D 0; \ + } else if (tmp < 0) { \ + dest =3D src1 >> -tmp; \ + } else { \ + dest =3D src1 << tmp; \ + if ((dest >> tmp) !=3D src1) { \ + *satp =3D true; \ + dest =3D ~0; \ + } \ + } \ + dest; \ + }) + +DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) +DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) + #define DO_2OP_SCALAR(OP, ESIZE, TYPE, H, FN) \ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ uint32_t rm) \ diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 957e7e48fab..998f47fb94e 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -421,6 +421,8 @@ DO_2OP(VQADD_S, vqadds) DO_2OP(VQADD_U, vqaddu) DO_2OP(VQSUB_S, vqsubs) DO_2OP(VQSUB_U, vqsubu) +DO_2OP(VQSHL_S, vqshls) +DO_2OP(VQSHL_U, vqshlu) =20 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/fWwPQAC4aq9xoHiTtby2IWMhKyN2zKoRtXbTKjUTOA=; b=jaHvWyFhn8vjP7YmpkL86PzOnN82P831HLaqqlYvcToeAkokxFfN9187uC7zNygzN3 jXigS7YBEJj1fPddtyXbqD8pgWai+/+JSJy/uytnpq4loSbmzVDVlElaz1dTNcz2xzvp 48gf6zkIH+9CT8BTj7uPD3T+Z3gmuvFwSNS7FYJMsAIqhC3Nwbazz9iE5h6yI4jf5QTA 2Ps82nQ9ugdyzktzzLn0cQGFYQS1h2//ss2O5OWCSB3uLTksYDJnekr4m0QFgDa8Uwff AzbauzbJciFKPJAM2htsSj05Njx5x1ofRzV86ur3qzA10I9xHSuFl8NvhyQCejL2ikLY kLKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/fWwPQAC4aq9xoHiTtby2IWMhKyN2zKoRtXbTKjUTOA=; b=DsdszL4gf71QEVV/RHQY57lnpnEQ9KDx+uLXmT6D3/7FV7Tz0+V16NKNw3GphnlMRz FBMWsPDWCezUZccdXzNtOCod+z18WfxFN6c2oaqG8UNiDrIsBu22clR5+48JIdsuWkIn YUPg/Aw3/oEAkUJCVBhJvRadXZC22aWdrSea+HoLyno0hhUF9v4Pdo6ZbPic1xQK5EbT eYrIOh3jRZVYicURiWwyMEXb51gWFV6SnYYN4neErRKi7320gXSZulqr9LnY6qYELbT8 i2EQ7TkQRxHer/AXyol5UiR07YpoTF3qU5J1tsmBIC/QMHMPTxFS3L7yahmjM/TuSWUv TN5A== X-Gm-Message-State: AOAM533T6yJqOdxX6FOe1upErY+k/Gpy0EGpbjy6KFHQ3S068pXF7Dbm Jm/zeDYonqKy6npS/swLBdKN4A== X-Google-Smtp-Source: ABdhPJxJcm6dUtQZMROfHOaGTlQZ7aP8zefJQLQV8hcN7QGkcWuOl8bs/ZDnhuUdWfJ2lkzc5kQy1g== X-Received: by 2002:a05:600c:1ca2:: with SMTP id k34mr9729184wms.145.1623085138404; Mon, 07 Jun 2021 09:58:58 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 44/55] target/arm: Implement MVE VQRSHL Date: Mon, 7 Jun 2021 17:58:10 +0100 Message-Id: <20210607165821.9892-45-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MV VQRSHL (vector) insn. Again, the code to perform the actual shifts is borrowed from neon_helper.c. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 8 +++ target/arm/mve.decode | 3 + target/arm/mve_helper.c | 127 +++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 2 + 4 files changed, 140 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 352b6a46a5e..a2f9916b24e 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -179,6 +179,14 @@ DEF_HELPER_FLAGS_4(mve_vqshlub, TCG_CALL_NO_WG, void, = env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vqrshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqrshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqrshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vqrshlub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqrshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqrshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 2c37e265765..e78eab6d659 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -133,6 +133,9 @@ VQSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1= . 1 ... 0 @2op VQSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev VQSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev =20 +VQRSHL_S 111 0 1111 0 . .. ... 0 ... 0 0101 . 1 . 1 ... 0 @2op_rev +VQRSHL_U 111 1 1111 0 . .. ... 0 ... 0 0101 . 1 . 1 ... 0 @2op_rev + # Vector miscellaneous =20 VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 7ac41cb1460..b7f9af4067b 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -637,6 +637,133 @@ DO_2OP_SAT(vqsubsw, 4, int32_t, H4, DO_SQSUB_W) DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) =20 +#define DO_UQRSHL_OP(src1, src2, satp) \ + ({ \ + int8_t tmp; \ + typeof(src1) dest; \ + tmp =3D (int8_t)src2; \ + if (tmp >=3D (ssize_t)sizeof(src1) * 8) { \ + if (src1) { \ + *satp =3D true; \ + dest =3D ~0; \ + } else { \ + dest =3D 0; \ + } \ + } else if (tmp < -(ssize_t)sizeof(src1) * 8) { \ + dest =3D 0; \ + } else if (tmp =3D=3D -(ssize_t)sizeof(src1) * 8) { \ + dest =3D src1 >> (sizeof(src1) * 8 - 1); \ + } else if (tmp < 0) { \ + dest =3D (src1 + (1 << (-1 - tmp))) >> -tmp; \ + } else { \ + dest =3D src1 << tmp; \ + if ((dest >> tmp) !=3D src1) { \ + *satp =3D true; \ + dest =3D ~0; \ + } \ + } \ + dest; \ + }) + +/* + * The addition of the rounding constant may overflow, so we use an + * intermediate 64 bit accumulator for the 32-bit version. + */ +#define DO_UQRSHL32_OP(src1, src2, satp) \ + ({ \ + uint32_t dest; \ + uint32_t val =3D src1; \ + int8_t shift =3D (int8_t)src2; \ + if (shift >=3D 32) { \ + if (val) { \ + *satp =3D true; \ + dest =3D ~0; \ + } else { \ + dest =3D 0; \ + } \ + } else if (shift < -32) { \ + dest =3D 0; \ + } else if (shift =3D=3D -32) { = \ + dest =3D val >> 31; \ + } else if (shift < 0) { \ + uint64_t big_dest =3D ((uint64_t)val + (1 << (-1 - shift))); \ + dest =3D big_dest >> -shift; \ + } else { \ + dest =3D val << shift; \ + if ((dest >> shift) !=3D val) { \ + *satp =3D true; \ + dest =3D ~0; \ + } \ + } \ + dest; \ + }) + +#define DO_SQRSHL_OP(src1, src2, satp) \ + ({ \ + int8_t tmp; \ + typeof(src1) dest; \ + tmp =3D (int8_t)src2; \ + if (tmp >=3D (ssize_t)sizeof(src1) * 8) { \ + if (src1) { \ + *satp =3D true; \ + dest =3D (typeof(dest))(1 << (sizeof(src1) * 8 - 1)); \ + if (src1 > 0) { \ + dest--; \ + } \ + } else { \ + dest =3D 0; \ + } \ + } else if (tmp <=3D -(ssize_t)sizeof(src1) * 8) { \ + dest =3D 0; \ + } else if (tmp < 0) { \ + dest =3D (src1 + (1 << (-1 - tmp))) >> -tmp; \ + } else { \ + dest =3D src1 << tmp; \ + if ((dest >> tmp) !=3D src1) { \ + *satp =3D true; \ + dest =3D (uint32_t)(1 << (sizeof(src1) * 8 - 1)); \ + if (src1 > 0) { \ + dest--; \ + } \ + } \ + } \ + dest; \ + }) + +#define DO_SQRSHL32_OP(src1, src2, satp) \ + ({ \ + int32_t dest; \ + int32_t val =3D (int32_t)src1; \ + int8_t shift =3D (int8_t)src2; \ + if (shift >=3D 32) { \ + if (val) { \ + *satp =3D true; \ + dest =3D (val >> 31) ^ ~(1U << 31); \ + } else { \ + dest =3D 0; \ + } \ + } else if (shift <=3D -32) { \ + dest =3D 0; \ + } else if (shift < 0) { \ + int64_t big_dest =3D ((int64_t)val + (1 << (-1 - shift))); \ + dest =3D big_dest >> -shift; \ + } else { \ + dest =3D val << shift; \ + if ((dest >> shift) !=3D val) { \ + *satp =3D true; \ + dest =3D (val >> 31) ^ ~(1U << 31); \ + } \ + } \ + dest; \ + }) + +DO_2OP_SAT(vqrshlub, 1, uint8_t, H1, DO_UQRSHL_OP) +DO_2OP_SAT(vqrshluh, 2, uint16_t, H2, DO_UQRSHL_OP) +DO_2OP_SAT(vqrshluw, 4, uint32_t, H4, DO_UQRSHL32_OP) +DO_2OP_SAT(vqrshlsb, 1, int8_t, H1, DO_SQRSHL_OP) +DO_2OP_SAT(vqrshlsh, 2, int16_t, H2, DO_SQRSHL_OP) +DO_2OP_SAT(vqrshlsw, 4, int32_t, H4, DO_SQRSHL32_OP) + #define DO_2OP_SCALAR(OP, ESIZE, TYPE, H, FN) \ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ uint32_t rm) \ diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 998f47fb94e..bea561726ea 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -423,6 +423,8 @@ DO_2OP(VQSUB_S, vqsubs) DO_2OP(VQSUB_U, vqsubu) DO_2OP(VQSHL_S, vqshls) DO_2OP(VQSHL_U, vqshlu) +DO_2OP(VQRSHL_S, vqrshls) +DO_2OP(VQRSHL_U, vqrshlu) =20 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fGbsL0Vwzsphqd9BOE+K3Cgyjkt5iafRzopECzKXlTk=; b=rtCN42k1YLcAp1p5WQY/xVy7uP2dRGuuQrWjywpQub8YgmxfGPUiHU7v4m3D6ylSfi aUQlAqCHyNNvIV0Iwv5EnqXq97Qm3lOqTfLcvPew4DSUZUs75dg9p+RUBfUmKDw71LLR QXO6ebnRWVQAk3J+SWBz+tvULPsAI7CWUD3PIlGAjqFBh4B1L98pjT1LuYWeO0tjE8Ar WzNq1hCO1t4GhBpYtPATj+bGqPerHCx6NqxKnVt0ATvXgbF1Px1O+1XLzmZhZHLhw4Ve h1YJUhzd39wwVRWo/n3Tcf2XOqmfqyOfRWDvTdtmk4FK4DvpbAwHymxaQ88M0t49lukK Ch/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fGbsL0Vwzsphqd9BOE+K3Cgyjkt5iafRzopECzKXlTk=; b=jVoVyuW54Qqr82Pdz+evaHfp0t9vsMGjRxifIUwjmMNaQyvar73khKUiylrRtIyqqN eVIV6jl3ACZKqCQCS68xMW+zzZGyXvtp+thNOpL65c9bvD7ZjOlPXydeAggcdbx+RThq phDHQKBaSRueJgiDvjQDex9vregj1w2u/gvdBjzUcju6slrs5JUwCtQvVvm3OY51G/Dt IQOptqrjJed6DNPMUzZiiaIH2AOGkzs0sqhVdAmrJKN6lCA+4YALeeCusxv36zpSPYJL bRAe0ybWHreN76Jz3eTxb3kx+F2ytEFPSaKuRWWX9bH56cmTCXybnz9AxdSUGqtbftAM 3i7g== X-Gm-Message-State: AOAM531QMLHCpc/shFsxAWDC7hCJoChpRO+vgvfiWte7ygjGhDm7lLa7 IHAi+qP78bHRLBdpS8rX1Q6/mQ== X-Google-Smtp-Source: ABdhPJyWJVnBQfAPSwU9JrSi3LP08ZxRJuw1K7iB7gXSgirMH5DMErk+si2FwFprXw4Vrapp/MErnA== X-Received: by 2002:a05:6000:1563:: with SMTP id 3mr17686776wrz.59.1623085139104; Mon, 07 Jun 2021 09:58:59 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 45/55] target/arm: Implement MVE VSHL insn Date: Mon, 7 Jun 2021 17:58:11 +0100 Message-Id: <20210607165821.9892-46-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VSHL insn (vector form). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 8 ++++++++ target/arm/mve.decode | 3 +++ target/arm/mve_helper.c | 30 ++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 2 ++ 4 files changed, 43 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index a2f9916b24e..6ef01d367b4 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -171,6 +171,14 @@ DEF_HELPER_FLAGS_4(mve_vqsubub, TCG_CALL_NO_WG, void, = env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqsubuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqsubuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vshlub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vqshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index e78eab6d659..ebf156b46b5 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -130,6 +130,9 @@ VQADD_U 111 1 1111 0 . .. ... 0 ... 0 0000 . 1= . 1 ... 0 @2op VQSUB_S 111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op VQSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op =20 +VSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 0 ... 0 @2op_rev +VSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 0 ... 0 @2op_rev + VQSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev VQSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev =20 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index b7f9af4067b..c95d5a0fd8e 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -508,6 +508,36 @@ DO_2OP_U(vhaddu, do_vhadd_u) DO_2OP_S(vhsubs, do_vhsub_s) DO_2OP_U(vhsubu, do_vhsub_u) =20 +static inline uint32_t do_ushl(uint32_t n, int8_t shift, int esize) +{ + if (shift >=3D esize || shift <=3D -esize) { + return 0; + } else if (shift < 0) { + return n >> -shift; + } else { + return n << shift; + } +} + +static inline int32_t do_sshl(int32_t n, int8_t shift, int esize) +{ + if (shift >=3D esize) { + return 0; + } else if (shift <=3D -esize) { + return n >> (esize - 1); + } else if (shift < 0) { + return n >> -shift; + } else { + return n << shift; + } +} + +#define DO_VSHLS(N, M) do_sshl(N, M, sizeof(N) * 8) +#define DO_VSHLU(N, M) do_ushl(N, M, sizeof(N) * 8) + +DO_2OP_S(vshls, DO_VSHLS) +DO_2OP_U(vshlu, DO_VSHLU) + static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bo= ol *s) { if (val > max) { diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index bea561726ea..6eaa99bc0f5 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -421,6 +421,8 @@ DO_2OP(VQADD_S, vqadds) DO_2OP(VQADD_U, vqaddu) DO_2OP(VQSUB_S, vqsubs) DO_2OP(VQSUB_U, vqsubu) +DO_2OP(VSHL_S, vshls) +DO_2OP(VSHL_U, vshlu) DO_2OP(VQSHL_S, vqshls) DO_2OP(VQSHL_U, vqshlu) DO_2OP(VQRSHL_S, vqrshls) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:58:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Mhk9x1c71fMqboSe7SlWTDZQhCtwoaWMB3BCsBAcMv0=; b=Nqcn7YGC0ANNmjIVahcRhjlElrdgcr7/KqdMUhZ8ikhYDqSaxXM1rNM2YEvJ5XmT42 2rfuPotSJEOYKnf5zbhReAb7A7IAqeCSjwlDloqXqcDvJMlTQBYtzbxIDlrsbe2HToRS xml2sMFMvHYJGd7V7e9rYAzqapRaJWKWkodbcEAHrZkDz51at5XZEYf0QroewNmc5IU7 d3fVYi1gEdVJPDM5vOlULikmMCwNNHzLesepOnaa92F4K89pT+miUrq4fSOfLMyxuIfz FLlBwR0iqKM0U25zihzNY6gmycruuFGLCXeiATrqE8AUoh3BQz7nJh7+Fn3fgdiLr0HN 1UtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Mhk9x1c71fMqboSe7SlWTDZQhCtwoaWMB3BCsBAcMv0=; b=IglVLhkLMumtCsFCWlrXEtPPsHsU3MQoVnEBckCRBxS8dw8oWgSIczaEJ64TFjRfvP LT3hF/peLyd+NLL5wSQ3OXRHIh9hIus8q1rR9DjBSKgjHMESMuN1EXG7tHl4FoHIiH26 aC4DxIefqHkIdFkzRtmfUESxEgqiKhNPFUW+rw+n+Qk4ASYI14iEtWKzkn28y8PvMRgD tD83yz2AAy0TiTCZG2p5UE2jvc6CHBN1SyElwgM2CRNTriegmHtCF9s5Iv//eLaj/G+4 bp26yhfRiuZSzegrg1HnhbAgR7AsFwDsT3XwN9pHQ8PBKOiswUzjdepVfBdxuPkz17Yo /mLA== X-Gm-Message-State: AOAM533H/JvVWTFxaFFNU+bvPvV6bcvJSjR2fs93a8fRftnq6qw7+OxV PLX+F1gx+B+ZD7CxjyQzsersvLz+ss913WHq X-Google-Smtp-Source: ABdhPJyksZ7jbJuYxU+UDVAoQZ2u2CkFmGR3ZdEt52rQQzLf3P6iVkX6KqDKJZ6+7A/THFMrln1ToA== X-Received: by 2002:a5d:64a5:: with SMTP id m5mr17669832wrp.182.1623085139851; Mon, 07 Jun 2021 09:58:59 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 46/55] target/arm: Implement MVE VRSHL Date: Mon, 7 Jun 2021 17:58:12 +0100 Message-Id: <20210607165821.9892-47-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VRSHL insn (vector form). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 8 ++++++++ target/arm/mve.decode | 3 +++ target/arm/mve_helper.c | 36 ++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 2 ++ 4 files changed, 49 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 6ef01d367b4..6939cf84c57 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -179,6 +179,14 @@ DEF_HELPER_FLAGS_4(mve_vshlub, TCG_CALL_NO_WG, void, e= nv, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vrshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vrshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vrshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vrshlub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vrshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vrshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vqshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index ebf156b46b5..c30fb2c1536 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -133,6 +133,9 @@ VQSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1= . 1 ... 0 @2op VSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 0 ... 0 @2op_rev VSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 0 ... 0 @2op_rev =20 +VRSHL_S 111 0 1111 0 . .. ... 0 ... 0 0101 . 1 . 0 ... 0 @2op_rev +VRSHL_U 111 1 1111 0 . .. ... 0 ... 0 0101 . 1 . 0 ... 0 @2op_rev + VQSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev VQSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev =20 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index c95d5a0fd8e..9c23e6b9b28 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -538,6 +538,42 @@ static inline int32_t do_sshl(int32_t n, int8_t shift,= int esize) DO_2OP_S(vshls, DO_VSHLS) DO_2OP_U(vshlu, DO_VSHLU) =20 +static inline uint32_t do_urshl(uint32_t n, int8_t shift, int esize) +{ + if (shift >=3D esize || shift < -esize) { + return 0; + } else if (shift =3D=3D -esize) { + return n >> (-esize - 1); + } else if (shift < 0) { + /* Use 64 bit intermediate: adding the rounding const might overfl= ow */ + uint64_t r =3D (uint64_t)n + (1 << (-1 - shift)); + return r >> -shift; + } else { + return n << shift; + } +} + +static inline int32_t do_srshl(int32_t n, int8_t shift, int esize) +{ + if (shift >=3D esize || shift <=3D -esize) { + return 0; + } else if (shift =3D=3D -esize) { + return n >> (-esize - 1); + } else if (shift < 0) { + /* Use 64 bit intermediate: adding the rounding const might overfl= ow */ + int64_t r =3D (int64_t)n + (1 << (-1 - shift)); + return r >> -shift; + } else { + return n << shift; + } +} + +#define DO_VRSHLS(N, M) do_srshl(N, M, sizeof(N) * 8) +#define DO_VRSHLU(N, M) do_urshl(N, M, sizeof(N) * 8) + +DO_2OP_S(vrshls, DO_VRSHLS) +DO_2OP_U(vrshlu, DO_VRSHLU) + static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bo= ol *s) { if (val > max) { diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 6eaa99bc0f5..6bc32379172 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -423,6 +423,8 @@ DO_2OP(VQSUB_S, vqsubs) DO_2OP(VQSUB_U, vqsubu) DO_2OP(VSHL_S, vshls) DO_2OP(VSHL_U, vshlu) +DO_2OP(VRSHL_S, vrshls) +DO_2OP(VRSHL_U, vrshlu) DO_2OP(VQSHL_S, vqshls) DO_2OP(VQSHL_U, vqshlu) DO_2OP(VQRSHL_S, vqrshls) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.58.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:59:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O5QkF3qGfRO7IFJppquy5uIhGZiL/TMkugt4cNNnqJY=; b=eTWaYIRqPA7qO40AOuSL7WPpLPyosKXNlp9O6nSL0Mx6BfMkN7sKiGUf/JQmmKNrA+ yZMi8+V3I4upEUMd/7ShdRnWOqAKrRMLqGdWSvJcMNx3ZBrTx5dIQ2YlxVNmtJCZ7R1M XtVzf+EBv2Fkf2OjPPHfcCvfsmgQGiuUx5ZfqtUKpDy8JYvwJoHAjkKrO8VcHbkOK8og ZC0bvD1pjOavre2c2elCJyqZrJH89LE8PBRLrcH/yutF/lGJoXOLxEkKUn03Ezy9TFQN oatfpgfJZzXDVTGEAiC0Ek4hD51ncGEuVbo23PE4xytFXbOE/n0ALzgMd9Hnfllsb+4A hOfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O5QkF3qGfRO7IFJppquy5uIhGZiL/TMkugt4cNNnqJY=; b=i3we+NQvobt7AZhIEUe97EOa+yS+oxIWtNfdhrFo4QWvvYqMqb2wtegANzEqFJBDZ/ 3W2U/m+iJQ3U228r4OjUcLc0nKqTNM0/AGWSQXcsdmBgR3VrkdFNp/Q7yMlJtJ0QHcno yJAfIM1R0oFFhLrmSLe2lcmoTyiw/4Y8fY/p4GbMrOwvfKw0HGEjCRXMjmiq9ysmb0CF 5LjaeRSMRhiuJ61rhbjcg3ZPs5CxhgLdZYs592omAsEcjiF8JjKcABJBYPiXiianS/xU 4EYzKRVkl2D0xdn/4wvpNxTtfSqY3EEq+tfljMeMLtNQKMo0Fvv3nimiEt7p6QZ4dbAP 2ixg== X-Gm-Message-State: AOAM531LZQ2OvL2ayUVr+p4EHOKAv94lu0a52ezn2XW9G5ohIypM3ZmA 4t8pllT7n0/gadGP4t2zFEBN18Y5fcOWNMmd X-Google-Smtp-Source: ABdhPJyv84HABvj6Ce/eS1vf2h+LInllLmxml5RjyEguqs4D24WdZNSmJZYQxOlVlhSxHEM9Gwt4iw== X-Received: by 2002:a5d:58c1:: with SMTP id o1mr17769535wrf.420.1623085140657; Mon, 07 Jun 2021 09:59:00 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 47/55] target/arm: Implement MVE VQDMLADH and VQRDMLADH Date: Mon, 7 Jun 2021 17:58:13 +0100 Message-Id: <20210607165821.9892-48-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VQDMLADH and VQRDMLADH insns. These multiply elements, and then add pairs of products, double, possibly round, saturate and return the high half of the result. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 16 +++++++ target/arm/mve.decode | 5 +++ target/arm/mve_helper.c | 87 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 4 ++ 4 files changed, 112 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 6939cf84c57..c62066d94aa 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -203,6 +203,22 @@ DEF_HELPER_FLAGS_4(mve_vqrshlub, TCG_CALL_NO_WG, void,= env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqrshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqrshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vqdmladhb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqdmladhh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqdmladhw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vqdmladhxb, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) +DEF_HELPER_FLAGS_4(mve_vqdmladhxh, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) +DEF_HELPER_FLAGS_4(mve_vqdmladhxw, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) + +DEF_HELPER_FLAGS_4(mve_vqrdmladhb, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) +DEF_HELPER_FLAGS_4(mve_vqrdmladhh, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) +DEF_HELPER_FLAGS_4(mve_vqrdmladhw, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) + +DEF_HELPER_FLAGS_4(mve_vqrdmladhxb, TCG_CALL_NO_WG, void, env, ptr, ptr, p= tr) +DEF_HELPER_FLAGS_4(mve_vqrdmladhxh, TCG_CALL_NO_WG, void, env, ptr, ptr, p= tr) +DEF_HELPER_FLAGS_4(mve_vqrdmladhxw, TCG_CALL_NO_WG, void, env, ptr, ptr, p= tr) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index c30fb2c1536..d267c8838eb 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -142,6 +142,11 @@ VQSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . = 1 . 1 ... 0 @2op_rev VQRSHL_S 111 0 1111 0 . .. ... 0 ... 0 0101 . 1 . 1 ... 0 @2op_rev VQRSHL_U 111 1 1111 0 . .. ... 0 ... 0 0101 . 1 . 1 ... 0 @2op_rev =20 +VQDMLADH 1110 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 0 @2op +VQDMLADHX 1110 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 0 @2op +VQRDMLADH 1110 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op +VQRDMLADHX 1110 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op + # Vector miscellaneous =20 VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 9c23e6b9b28..03701d32dcb 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -830,6 +830,93 @@ DO_2OP_SAT(vqrshlsb, 1, int8_t, H1, DO_SQRSHL_OP) DO_2OP_SAT(vqrshlsh, 2, int16_t, H2, DO_SQRSHL_OP) DO_2OP_SAT(vqrshlsw, 4, int32_t, H4, DO_SQRSHL32_OP) =20 +/* + * Multiply add dual returning high half + * The 'FN' here takes four inputs A, B, C, D, a 0/1 indicator of + * whether to add the rounding constant, and the pointer to the + * saturation flag, and should do "(A * B + C * D) * 2 + rounding constant= ", + * saturate to twice the input size and return the high half; or + * (A * B - C * D) etc for VQDMLSDH. + */ +#define DO_VQDMLADH_OP(OP, ESIZE, TYPE, H, XCHG, ROUND, FN) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ + void *vm) \ + { \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + bool sat =3D false; \ + if ((e & 1) =3D=3D XCHG) { = \ + TYPE r =3D FN(n[H(e)], m[H(e - XCHG)], \ + n[H(e + (1 - 2 * XCHG))], m[H(e + (1 - XCHG))]= , \ + ROUND, &sat); \ + uint64_t bytemask =3D mask_to_bytemask##ESIZE(mask); \ + d[H(e)] &=3D ~bytemask; \ + d[H(e)] |=3D (r & bytemask); \ + if (sat && (mask & 1)) { \ + env->vfp.qc[0] =3D 1; \ + } \ + } \ + } \ + mve_advance_vpt(env); \ + } + +static int8_t do_vqdmladh_b(int8_t a, int8_t b, int8_t c, int8_t d, + int round, bool *sat) +{ + int64_t r =3D ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 7); + return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; +} + +static int16_t do_vqdmladh_h(int16_t a, int16_t b, int16_t c, int16_t d, + int round, bool *sat) +{ + int64_t r =3D ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 15); + return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; +} + +static int32_t do_vqdmladh_w(int32_t a, int32_t b, int32_t c, int32_t d, + int round, bool *sat) +{ + int64_t m1 =3D (int64_t)a * b; + int64_t m2 =3D (int64_t)c * d; + int64_t r; + /* + * Architecturally we should do the entire add, double, round + * and then check for saturation. We do three saturating adds, + * but we need to be careful about the order. If the first + * m1 + m2 saturates then it's impossible for the *2+rc to + * bring it back into the non-saturated range. However, if + * m1 + m2 is negative then it's possible that doing the doubling + * would take the intermediate result below INT64_MAX and the + * addition of the rounding constant then brings it back in range. + * So we add half the rounding constant before doubling rather + * than adding the rounding constant after the doubling. + */ + if (sadd64_overflow(m1, m2, &r) || + sadd64_overflow(r, (round << 30), &r) || + sadd64_overflow(r, r, &r)) { + *sat =3D true; + return r < 0 ? INT32_MAX : INT32_MIN; + } + return r >> 32; +} + +DO_VQDMLADH_OP(vqdmladhb, 1, int8_t, H1, 0, 0, do_vqdmladh_b) +DO_VQDMLADH_OP(vqdmladhh, 2, int16_t, H2, 0, 0, do_vqdmladh_h) +DO_VQDMLADH_OP(vqdmladhw, 4, int32_t, H4, 0, 0, do_vqdmladh_w) +DO_VQDMLADH_OP(vqdmladhxb, 1, int8_t, H1, 1, 0, do_vqdmladh_b) +DO_VQDMLADH_OP(vqdmladhxh, 2, int16_t, H2, 1, 0, do_vqdmladh_h) +DO_VQDMLADH_OP(vqdmladhxw, 4, int32_t, H4, 1, 0, do_vqdmladh_w) + +DO_VQDMLADH_OP(vqrdmladhb, 1, int8_t, H1, 0, 1, do_vqdmladh_b) +DO_VQDMLADH_OP(vqrdmladhh, 2, int16_t, H2, 0, 1, do_vqdmladh_h) +DO_VQDMLADH_OP(vqrdmladhw, 4, int32_t, H4, 0, 1, do_vqdmladh_w) +DO_VQDMLADH_OP(vqrdmladhxb, 1, int8_t, H1, 1, 1, do_vqdmladh_b) +DO_VQDMLADH_OP(vqrdmladhxh, 2, int16_t, H2, 1, 1, do_vqdmladh_h) +DO_VQDMLADH_OP(vqrdmladhxw, 4, int32_t, H4, 1, 1, do_vqdmladh_w) + #define DO_2OP_SCALAR(OP, ESIZE, TYPE, H, FN) \ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ uint32_t rm) \ diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 6bc32379172..7c25802bf53 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -429,6 +429,10 @@ DO_2OP(VQSHL_S, vqshls) DO_2OP(VQSHL_U, vqshlu) DO_2OP(VQRSHL_S, vqrshls) DO_2OP(VQRSHL_U, vqrshlu) +DO_2OP(VQDMLADH, vqdmladh) +DO_2OP(VQDMLADHX, vqdmladhx) +DO_2OP(VQRDMLADH, vqrdmladh) +DO_2OP(VQRDMLADHX, vqrdmladhx) =20 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623087231; cv=none; d=zohomail.com; s=zohoarc; b=Def9nJ8YoTIqgrblNJ6y7a53IbXLfBrjKWWb33TIkwOPFRXcsbCYHvQDhEWQSG42KTx+flSBXufSq+jOEDgW6bZBFgMnpVc2muVm3bpmmnQJRGVWyhhDfEB8U83O7V2cKNccgtW7ja7c4pwE1yWMpOmG5HPmin3HB8hldZHbWsg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623087231; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3nA16a0wbwNZedQGtA5Byawf7/on8UyQP7L5tEao8zI=; b=AksbHE5zfDISxOHozjFMKPdTfWjuR7R5AoNRVqsnC+b3N5O9txBZ+OQDI110RFt+ir2tljBFO2SeIchBYUuDzQnP5v2Zv92hxigHbEj8asGjidv33koj19WcAmXbeFbJPLkUHbaXk0lADzQ7iSwBkC8bCVuCi74aWnhhDYJtpnM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623087231098302.95873446133123; Mon, 7 Jun 2021 10:33:51 -0700 (PDT) Received: from localhost ([::1]:45814 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqJ8H-000418-L6 for importer@patchew.org; Mon, 07 Jun 2021 13:33:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60356) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIbK-0000Cd-Bs for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:46 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:55868) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIae-00086f-Is for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:46 -0400 Received: by mail-wm1-x335.google.com with SMTP id g204so85555wmf.5 for ; Mon, 07 Jun 2021 09:59:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.59.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:59:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3nA16a0wbwNZedQGtA5Byawf7/on8UyQP7L5tEao8zI=; b=kaxkfAjfbb0LQJSUY4exMGwTRJUa0Tg5of53qxdQsoZ/a6kcNAElNOMK+XvcEXjn3H Jb26DLQoCE5fs6cLGYz0ge+exfJYkAC1bxB02jSkDHx57FewTHPrYj2kRqp+bE5deQAO Q000qkyxdqDp6T/fjfRyrVWziT1Ql5XPA41OhjVdjIcoD85XLcYjHQwKYI1Sril7yxNb jqOUSHTL16VxKprNXLpv9b4c39UTUT9dLtWmPtWFksrUhqiQQK3m9NCrVgkOoF3eY9fO gAEPRsDloeuFwpK3jH/95ZynOCfTRYlXYkmcytHLlDXQhRPWI5XT0k4UUYI8+xx30HyX EfPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3nA16a0wbwNZedQGtA5Byawf7/on8UyQP7L5tEao8zI=; b=HO5C4jqppyatTG3G9r2NxLW9NtL7Ie9azs8nKv1n6ZdHLgwQ6R6UgHTw8q/mPCB4ql 5PilQNYXhEW5VbIBv+0jK0vwdh+gX90H7kbsOtvCQCfIYbTXirFmKVhobfNJoez7SvOD KpmqGBYIXxwxeVkItHS2ob/yuxg17tJrMXkmXepP3NvvKDLSBVpkM9hB8HbaO28cRSI6 8QgozJ/GKn5EKO3goh3q5tW6CqyLHSGpL8Ajvtnp/OFRWOWq/WDE2/GmE5JuQbIQUZUk yaLsMfSPDf7x1UOxOxiWXVfY4Vs+bQ3rzGE691mgU8+4/j7cTJ0UymwdY0Avr2cuSMf3 XatQ== X-Gm-Message-State: AOAM533w8w0MqgUPDmh8cd4P/EuLCItWFM1yxu72JlGa1JKfeAy0oy+h msvdR0/Nwwy34k06NOQjcLycf4C2JGefzD2w X-Google-Smtp-Source: ABdhPJzmdwWsI9zqGxf6OWO5rB5AF7FkGXL+WdaAoKNWAgyN4mTf7yxxAXAez0bJiBiBgyvbTjNIIw== X-Received: by 2002:a1c:2142:: with SMTP id h63mr18050247wmh.84.1623085141465; Mon, 07 Jun 2021 09:59:01 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 48/55] target/arm: Implement MVE VQDMLSDH and VQRDMLSDH Date: Mon, 7 Jun 2021 17:58:14 +0100 Message-Id: <20210607165821.9892-49-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VQDMLSDH and VQRDMLSDH insns, which are like VQDMLADH and VQRDMLADH except that products are subtracted rather than added. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 16 ++++++++++++++ target/arm/mve.decode | 5 +++++ target/arm/mve_helper.c | 44 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 4 ++++ 4 files changed, 69 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index c62066d94aa..e25299b229e 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -219,6 +219,22 @@ DEF_HELPER_FLAGS_4(mve_vqrdmladhxb, TCG_CALL_NO_WG, vo= id, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqrdmladhxh, TCG_CALL_NO_WG, void, env, ptr, ptr, p= tr) DEF_HELPER_FLAGS_4(mve_vqrdmladhxw, TCG_CALL_NO_WG, void, env, ptr, ptr, p= tr) =20 +DEF_HELPER_FLAGS_4(mve_vqdmlsdhb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqdmlsdhh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqdmlsdhw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vqdmlsdhxb, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) +DEF_HELPER_FLAGS_4(mve_vqdmlsdhxh, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) +DEF_HELPER_FLAGS_4(mve_vqdmlsdhxw, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) + +DEF_HELPER_FLAGS_4(mve_vqrdmlsdhb, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) +DEF_HELPER_FLAGS_4(mve_vqrdmlsdhh, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) +DEF_HELPER_FLAGS_4(mve_vqrdmlsdhw, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) + +DEF_HELPER_FLAGS_4(mve_vqrdmlsdhxb, TCG_CALL_NO_WG, void, env, ptr, ptr, p= tr) +DEF_HELPER_FLAGS_4(mve_vqrdmlsdhxh, TCG_CALL_NO_WG, void, env, ptr, ptr, p= tr) +DEF_HELPER_FLAGS_4(mve_vqrdmlsdhxw, TCG_CALL_NO_WG, void, env, ptr, ptr, p= tr) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index d267c8838eb..fa4fb1b2038 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -147,6 +147,11 @@ VQDMLADHX 1110 1110 0 . .. ... 0 ... 1 1110 . 0= . 0 ... 0 @2op VQRDMLADH 1110 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op VQRDMLADHX 1110 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op =20 +VQDMLSDH 1111 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 0 @2op +VQDMLSDHX 1111 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 0 @2op +VQRDMLSDH 1111 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op +VQRDMLSDHX 1111 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op + # Vector miscellaneous =20 VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 03701d32dcb..ed0da8097dc 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -903,6 +903,36 @@ static int32_t do_vqdmladh_w(int32_t a, int32_t b, int= 32_t c, int32_t d, return r >> 32; } =20 +static int8_t do_vqdmlsdh_b(int8_t a, int8_t b, int8_t c, int8_t d, + int round, bool *sat) +{ + int64_t r =3D ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 7); + return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; +} + +static int16_t do_vqdmlsdh_h(int16_t a, int16_t b, int16_t c, int16_t d, + int round, bool *sat) +{ + int64_t r =3D ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 15); + return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; +} + +static int32_t do_vqdmlsdh_w(int32_t a, int32_t b, int32_t c, int32_t d, + int round, bool *sat) +{ + int64_t m1 =3D (int64_t)a * b; + int64_t m2 =3D (int64_t)c * d; + int64_t r; + /* The same ordering issue as in do_vqdmladh_w applies here too */ + if (ssub64_overflow(m1, m2, &r) || + sadd64_overflow(r, (round << 30), &r) || + sadd64_overflow(r, r, &r)) { + *sat =3D true; + return r < 0 ? INT32_MAX : INT32_MIN; + } + return r >> 32; +} + DO_VQDMLADH_OP(vqdmladhb, 1, int8_t, H1, 0, 0, do_vqdmladh_b) DO_VQDMLADH_OP(vqdmladhh, 2, int16_t, H2, 0, 0, do_vqdmladh_h) DO_VQDMLADH_OP(vqdmladhw, 4, int32_t, H4, 0, 0, do_vqdmladh_w) @@ -917,6 +947,20 @@ DO_VQDMLADH_OP(vqrdmladhxb, 1, int8_t, H1, 1, 1, do_vq= dmladh_b) DO_VQDMLADH_OP(vqrdmladhxh, 2, int16_t, H2, 1, 1, do_vqdmladh_h) DO_VQDMLADH_OP(vqrdmladhxw, 4, int32_t, H4, 1, 1, do_vqdmladh_w) =20 +DO_VQDMLADH_OP(vqdmlsdhb, 1, int8_t, H1, 0, 0, do_vqdmlsdh_b) +DO_VQDMLADH_OP(vqdmlsdhh, 2, int16_t, H2, 0, 0, do_vqdmlsdh_h) +DO_VQDMLADH_OP(vqdmlsdhw, 4, int32_t, H4, 0, 0, do_vqdmlsdh_w) +DO_VQDMLADH_OP(vqdmlsdhxb, 1, int8_t, H1, 1, 0, do_vqdmlsdh_b) +DO_VQDMLADH_OP(vqdmlsdhxh, 2, int16_t, H2, 1, 0, do_vqdmlsdh_h) +DO_VQDMLADH_OP(vqdmlsdhxw, 4, int32_t, H4, 1, 0, do_vqdmlsdh_w) + +DO_VQDMLADH_OP(vqrdmlsdhb, 1, int8_t, H1, 0, 1, do_vqdmlsdh_b) +DO_VQDMLADH_OP(vqrdmlsdhh, 2, int16_t, H2, 0, 1, do_vqdmlsdh_h) +DO_VQDMLADH_OP(vqrdmlsdhw, 4, int32_t, H4, 0, 1, do_vqdmlsdh_w) +DO_VQDMLADH_OP(vqrdmlsdhxb, 1, int8_t, H1, 1, 1, do_vqdmlsdh_b) +DO_VQDMLADH_OP(vqrdmlsdhxh, 2, int16_t, H2, 1, 1, do_vqdmlsdh_h) +DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, H4, 1, 1, do_vqdmlsdh_w) + #define DO_2OP_SCALAR(OP, ESIZE, TYPE, H, FN) \ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ uint32_t rm) \ diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 7c25802bf53..0048aec1e9e 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -433,6 +433,10 @@ DO_2OP(VQDMLADH, vqdmladh) DO_2OP(VQDMLADHX, vqdmladhx) DO_2OP(VQRDMLADH, vqrdmladh) DO_2OP(VQRDMLADHX, vqrdmladhx) +DO_2OP(VQDMLSDH, vqdmlsdh) +DO_2OP(VQDMLSDHX, vqdmlsdhx) +DO_2OP(VQRDMLSDH, vqrdmlsdh) +DO_2OP(VQRDMLSDHX, vqrdmlsdhx) =20 static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623087989; cv=none; d=zohomail.com; s=zohoarc; b=JNt/KbU9s+vy5VcH0XW11yON7dojHv70ZX3PELdEEIylgqFCjpNy4F5K021CxP6fDU37T6hnOA/kAFKN3YGUCHglQpb3TG40VqPUio2zhv7KJrOa5K6fhrFbbMnfezxYPgzFQIHg4xdwUtXkPGlTZeiWqW576N3jew2E2SJ1UEw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623087989; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ll1o4H4hjGJjZN7SasnUUT+6rPv7CGDnQZjVe64C6OU=; b=Gd3bkMFGosMn+MHMuO8dAO5HhFkDST/Ug/qZulDV3L+B7bmKocPt74OM3cUJLMeAeGFEIH6d1IfcEDiX8nOdhhhJJllx653w2cibStimNQqDASW40K0juHregGK+2Dz0XGt2WGYnWyATCFh0AAgQ7rU/t1IpYXisv3W28luObeQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162308798945492.09566249879492; Mon, 7 Jun 2021 10:46:29 -0700 (PDT) Received: from localhost ([::1]:50286 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqJKU-0001rW-98 for importer@patchew.org; Mon, 07 Jun 2021 13:46:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60346) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIbJ-0000Ai-Dk for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:45 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:44659) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIae-00086u-JL for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:45 -0400 Received: by mail-wr1-x42c.google.com with SMTP id f2so18392370wri.11 for ; Mon, 07 Jun 2021 09:59:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.59.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:59:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ll1o4H4hjGJjZN7SasnUUT+6rPv7CGDnQZjVe64C6OU=; b=gfc82jKaIMjqR+9xRWBxCCcsocYykY8Xysq8Ggxx1Jwqx7myk7faJDBVFOviK04jlM HRuIMz2RwAwvEsIn7ZnKkCcTo17H0PBAussoBH/2JUf8UGaSTrkfr67zl20Tr7p2irgF lfe3loeSZQZn5EJGZlv3Wax8RY3aPLrQ7iCZbvpL1qA7V9M9Qkv/Wt2IxBsOcmC3twVd POalNE9TSHMIqI5NwyEQ0xoTfd+Bwb+95vx00VQNM1c45YThq3bPwqx35pdxp68NEaQq AKF2KQ7zhrkPmqwSrFC5FvqMeEBtIEmjOeZgEqKgJmjGrrU05zXG5YVoRDjPkstkGixf ceyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ll1o4H4hjGJjZN7SasnUUT+6rPv7CGDnQZjVe64C6OU=; b=VNwSe1HvQC/5usxWflLNPU676B9eZuKlxO56eijF2lAuv6rdBLFxUqsBprJxM3TeC0 BRoZAyzJoW8EgDXDZtqPKqBQF1rV0P9itat4cLNTgOsTvPyLc2FqBKsC2f6/o2rBtr7o 0nVhHM3XXuRwjfMIWRXunRqwqmH7F9ftDu1kax5/2GC2i8OgnUFxDTO75Obopzxu2niC mPOkTWXHMOAG1I8dURHgedHuDV748GG6l5tw68lYOcYklU/HL0jCdcLb5+KHTR8sT5i9 n5VOP1TFMu8eyxjEFLtF4Zj2KvDhYGP/sF1PRuSrLx1/YQZrQdix2MEBMA824POp1YfC 51LA== X-Gm-Message-State: AOAM531iUzSD2HlQzsZkZmxNncM5DsMTXxgYqLHs+IXNy0Y52GoRQHw7 2tq3iHhuZPtcltf6aXYpDf0KUQ== X-Google-Smtp-Source: ABdhPJyCBbSHo/7XdEEirrbdPP5IHOwHZ7TpLhzc7HBZ7dUXspEoMYLxp6yFVGLRXuyws/z2JKihoQ== X-Received: by 2002:adf:8bc9:: with SMTP id w9mr17826751wra.378.1623085142327; Mon, 07 Jun 2021 09:59:02 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 49/55] target/arm: Implement MVE VQDMULL (vector) Date: Mon, 7 Jun 2021 17:58:15 +0100 Message-Id: <20210607165821.9892-50-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the vector form of the MVE VQDMULL insn. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 5 +++++ target/arm/mve.decode | 5 +++++ target/arm/mve_helper.c | 30 ++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++ 4 files changed, 70 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index e25299b229e..ffddbd72377 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -235,6 +235,11 @@ DEF_HELPER_FLAGS_4(mve_vqrdmlsdhxb, TCG_CALL_NO_WG, vo= id, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqrdmlsdhxh, TCG_CALL_NO_WG, void, env, ptr, ptr, p= tr) DEF_HELPER_FLAGS_4(mve_vqrdmlsdhxw, TCG_CALL_NO_WG, void, env, ptr, ptr, p= tr) =20 +DEF_HELPER_FLAGS_4(mve_vqdmullbh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqdmullbw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqdmullth, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vqdmulltw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index fa4fb1b2038..3a2a7e75a3a 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -39,6 +39,8 @@ @1op_nosz .... .... .... .... .... .... .... .... &1op qd=3D%qd qm=3D%qm s= ize=3D0 @2op .... .... .. size:2 .... .... .... .... .... &2op qd=3D%qd qm=3D%qm q= n=3D%qn @2op_nosz .... .... .... .... .... .... .... .... &2op qd=3D%qd qm=3D%qm q= n=3D%qn size=3D0 +@2op_sz28 .... .... .... .... .... .... .... .... &2op qd=3D%qd qm=3D%qm q= n=3D%qn \ + size=3D%size_28 =20 # The _rev suffix indicates that Vn and Vm are reversed. This is # the case for shifts. In the Arm ARM these insns are documented @@ -152,6 +154,9 @@ VQDMLSDHX 1111 1110 0 . .. ... 0 ... 1 1110 . 0 = . 0 ... 0 @2op VQRDMLSDH 1111 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op VQRDMLSDHX 1111 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op =20 +VQDMULLB 111 . 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 1 @2op_sz28 +VQDMULLT 111 . 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 1 @2op_sz28 + # Vector miscellaneous =20 VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index ed0da8097dc..68a2339feae 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -1103,6 +1103,36 @@ DO_2OP_SAT_SCALAR_L(vqdmullt_scalarh, 1, int16_t, H2= , 4, int32_t, H4, \ DO_2OP_SAT_SCALAR_L(vqdmullt_scalarw, 1, int32_t, H4, 8, int64_t, , \ do_qdmullw, SATMASK32) =20 +/* + * Long saturating ops + */ +#define DO_2OP_SAT_L(OP, TOP, TYPE, H, LESIZE, LTYPE, LH, FN, SATMASK) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ + void *vm) \ + { \ + LTYPE *d =3D vd; \ + TYPE *n =3D vn, *m =3D vm; = \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned le; \ + for (le =3D 0; le < 16 / LESIZE; le++, mask >>=3D LESIZE) { = \ + bool sat =3D false; \ + LTYPE op1 =3D n[H(le * 2 + TOP)], op2 =3D m[H(le * 2 + TOP)]; = \ + LTYPE r =3D FN(op1, op2, &sat); \ + uint64_t bytemask =3D mask_to_bytemask##LESIZE(mask); \ + d[LH(le)] &=3D ~bytemask; \ + d[LH(le)] |=3D (r & bytemask); \ + if (sat && (mask & SATMASK)) { \ + env->vfp.qc[0] =3D 1; \ + } \ + } \ + mve_advance_vpt(env); \ + } + +DO_2OP_SAT_L(vqdmullbh, 0, int16_t, H2, 4, int32_t, H4, do_qdmullh, SATMAS= K16B) +DO_2OP_SAT_L(vqdmullbw, 0, int32_t, H4, 8, int64_t, , do_qdmullw, SATMASK3= 2) +DO_2OP_SAT_L(vqdmullth, 1, int16_t, H2, 4, int32_t, H4, do_qdmullh, SATMAS= K16T) +DO_2OP_SAT_L(vqdmulltw, 1, int32_t, H4, 8, int64_t, , do_qdmullw, SATMASK3= 2) + static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) { m &=3D 0xff; diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 0048aec1e9e..b227b72e5b6 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -438,6 +438,36 @@ DO_2OP(VQDMLSDHX, vqdmlsdhx) DO_2OP(VQRDMLSDH, vqrdmlsdh) DO_2OP(VQRDMLSDHX, vqrdmlsdhx) =20 +static bool trans_VQDMULLB(DisasContext *s, arg_2op *a) +{ + MVEGenTwoOpFn *fns[] =3D { + NULL, + gen_helper_mve_vqdmullbh, + gen_helper_mve_vqdmullbw, + NULL, + }; + if (a->size =3D=3D MO_32 && (a->qd =3D=3D a->qm || a->qd =3D=3D a->qn)= ) { + /* UNPREDICTABLE; we choose to undef */ + return false; + } + return do_2op(s, a, fns[a->size]); +} + +static bool trans_VQDMULLT(DisasContext *s, arg_2op *a) +{ + MVEGenTwoOpFn *fns[] =3D { + NULL, + gen_helper_mve_vqdmullth, + gen_helper_mve_vqdmulltw, + NULL, + }; + if (a->size =3D=3D MO_32 && (a->qd =3D=3D a->qm || a->qd =3D=3D a->qn)= ) { + /* UNPREDICTABLE; we choose to undef */ + return false; + } + return do_2op(s, a, fns[a->size]); +} + static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) { --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623088441; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.59.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:59:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MtUWIrOwARNN+B35zuZj2IuA3K1qcjuz/iaWJMrCiDM=; b=WUszFXbzhOx0qvh67xbSjDEy/SBMJE5J7mP+xDMtDdS7Bl1xf6MaWdqEV2S3KlixZn imxQW89lpBCb+TTGY7Z1apQA+a3GgapgpUQmqvN8Ckhsw4DfLL1l2+hInlvBQODuc0Zn vWtmnDWmOIc1TYCqJjy9JOByFpu9zGQnUTmBRu3HrpiRRzwv7apYHl0LdlBdyHF+KjIs ZY1OIZJ/PjsBXnhPHsVyE8ov5zI3OhoS2ZtzqhdiL9Hwmie28HiNcTfsdUjKtP+9krWb KwnUnMuoUSN+xByeaZglvk+etevV0/q0UnXYnTrehESs4MuUfMTzOIMPiBxUgoaHNS+j J51A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MtUWIrOwARNN+B35zuZj2IuA3K1qcjuz/iaWJMrCiDM=; b=hqPeC1VcStqjMMJfLKrMvIL3z8OkUDQ6SpZ6BR1krTvekbSd+RLbDZ5g4DnYPGSBWh vboE6j3ySnRe4q6ntmwZ1M5RZ0IyUIyRc1dNqBpEKNrMJ+Do0wK7HwBcCfF6ECttMPU7 dwccnrSCiF/IYoiVawDir72ZffOrqb2MeafRemKcfR6PqA7WZA0bYQjW6HTFQFfgVuQf cKYZnZFxp1rbuM87J46EvoTktUVnTpN5BT2NvV9E5xojcO8RE+V7+zHJfMBrbg/lMIH7 HEcnSFUILSwZ+I18dOHSquf8XbpoZTWVqQ/psF6zqxmo5YmHMFF9+Bep2Yni3wKCwd4u uQLA== X-Gm-Message-State: AOAM530/0wuEsJKvpDnAM1+vTW1mkVREW3uVQO9x65dV3JTKsrgk82V7 Pa4gbiT8JnzNzOOYX+dJlQS+Gg== X-Google-Smtp-Source: ABdhPJyz0v5P56LKVPRX9Zw44RYNm2Ofb+k2ljXIJM7zyZWdVIcMnHASKKGOF+84JBevrU7iXIr2yQ== X-Received: by 2002:a5d:5243:: with SMTP id k3mr18359569wrc.19.1623085143072; Mon, 07 Jun 2021 09:59:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 50/55] target/arm: Implement MVE VRHADD Date: Mon, 7 Jun 2021 17:58:16 +0100 Message-Id: <20210607165821.9892-51-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VRHADD insn, which performs a rounded halving addition. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 8 ++++++++ target/arm/mve.decode | 3 +++ target/arm/mve_helper.c | 6 ++++++ target/arm/translate-mve.c | 2 ++ 4 files changed, 19 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index ffddbd72377..cd2cc6252f8 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -240,6 +240,14 @@ DEF_HELPER_FLAGS_4(mve_vqdmullbw, TCG_CALL_NO_WG, void= , env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqdmullth, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vqdmulltw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vrhaddsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vrhaddsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vrhaddsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vrhaddub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vrhadduh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vrhadduw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 3a2a7e75a3a..6b969902df0 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -157,6 +157,9 @@ VQRDMLSDHX 1111 1110 0 . .. ... 0 ... 1 1110 . 0 = . 0 ... 1 @2op VQDMULLB 111 . 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 1 @2op_sz28 VQDMULLT 111 . 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 1 @2op_sz28 =20 +VRHADD_S 111 0 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op +VRHADD_U 111 1 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op + # Vector miscellaneous =20 VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 68a2339feae..c9434479604 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -574,6 +574,12 @@ static inline int32_t do_srshl(int32_t n, int8_t shift= , int esize) DO_2OP_S(vrshls, DO_VRSHLS) DO_2OP_U(vrshlu, DO_VRSHLU) =20 +#define DO_RHADD_S(N, M) (((int64_t)(N) + (M) + 1) >> 1) +#define DO_RHADD_U(N, M) (((uint64_t)(N) + (M) + 1) >> 1) + +DO_2OP_S(vrhadds, DO_RHADD_S) +DO_2OP_U(vrhaddu, DO_RHADD_U) + static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bo= ol *s) { if (val > max) { diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index b227b72e5b6..9a88583385f 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -437,6 +437,8 @@ DO_2OP(VQDMLSDH, vqdmlsdh) DO_2OP(VQDMLSDHX, vqdmlsdhx) DO_2OP(VQRDMLSDH, vqrdmlsdh) DO_2OP(VQRDMLSDHX, vqrdmlsdhx) +DO_2OP(VRHADD_S, vrhadds) +DO_2OP(VRHADD_U, vrhaddu) =20 static bool trans_VQDMULLB(DisasContext *s, arg_2op *a) { --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.59.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:59:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=42h1syOUzxLZUA1XvuU+cSxInBYhE+Glir21t9O+DZY=; b=xA6ZkOgvzwx7cTE6WMwhT0EtuQD85vbOKaodkUJoqlwxWYWpEx38NYTP6EEvuUUAzp y+kqKzLHAGLmPpiLix8MsQE56o6wwVos0e0d1bRdGize3xnvEuIzTqTMbEJKWZqD3ELs tJujSUZzGFa4uH42uxTEBsqMNsraxG/zhucJmSBwoSpHTPYGoSi5PAm5b3x6uvQqf6HG fXpZHRQ7hXBLJz8cIcnMQa/8LrMlEbi/Yp9cIJ5hfFAXprn0YFg1OI71B7+viZFVGTIk m6b1KKsBCD6NBVX/PlyaemwPLl9w0NI2t5IBh/TLfLlxAxJnNUSJwLQK1Sl3t/3sVCQO 9bxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=42h1syOUzxLZUA1XvuU+cSxInBYhE+Glir21t9O+DZY=; b=PVwTHQdvtq/yzrtDA1NYaIGc9pwpsPfK+mwdTqLHvJPbeGxUSs3eer5CjpelYQFraV 60Pmz5nxDnq6yro3rFnA3XYuzB1rlE4Yk15fVQOBHtQAT+Hp75nF0rvnGTolIeKohA+L DMdNvtB8bYXZpiMaLfL7wTGooX6SN87iBjx0Titsmd6p6pPDGNJJo8FZralcaVtZQF5G EhpJqKv35x68C8NOgLfb0jO2mXBgfWG9yFnQpCSpYVUcMWjOXlm/ymZRtLrWXN/nyZkJ JFa15JaHW/dARNf4x6ftYielv+WjaHLHfd0tjhIgtMOFMYlDrsJ48cxR2MsLO2AvsTPr BtmQ== X-Gm-Message-State: AOAM53386JJhQaArYnGkMQr2gVJD1ER6w4IAz9Su2ZuINBOk2kmBW5lJ vROvLDW/9LAH9NjPQ4xADZbrTQ== X-Google-Smtp-Source: ABdhPJzelOuYvG62PrURa3ktgNuFV00R/40ciF1FndV1xJ1ZZDvxW4eSqMSO25Hj6RWuV02CBWDA8Q== X-Received: by 2002:a05:600c:4f94:: with SMTP id n20mr53591wmq.121.1623085143850; Mon, 07 Jun 2021 09:59:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 51/55] target/arm: Implement MVE VADC, VSBC Date: Mon, 7 Jun 2021 17:58:17 +0100 Message-Id: <20210607165821.9892-52-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VADC and VSBC insns. These perform an add-with-carry or subtract-with-carry of the 32-bit elements in each lane of the input vectors, where the carry-out of each add is the carry-in of the next. The initial carry input is either 1 or is from FPSCR.C; the carry out at the end is written back to FPSCR.C. Signed-off-by: Peter Maydell --- target/arm/helper-mve.h | 3 ++ target/arm/mve.decode | 6 ++++ target/arm/mve_helper.c | 30 +++++++++++++++++ target/arm/translate-mve.c | 69 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 108 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index cd2cc6252f8..686e5d9a39b 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -248,6 +248,9 @@ DEF_HELPER_FLAGS_4(mve_vrhaddub, TCG_CALL_NO_WG, void, = env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vrhadduh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vrhadduw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_5(mve_vadc, TCG_CALL_NO_WG, i32, env, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(mve_vsbc, TCG_CALL_NO_WG, i32, env, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 6b969902df0..6a4aae7a1fc 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -30,6 +30,7 @@ &1op qd qm size &2op qd qm qn size &2scalar qd qn rm size +&vadc qd qm qn i =20 @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=3D%qd u= =3D0 # Note that both Rn and Qd are 3 bits only (no D bit) @@ -42,6 +43,8 @@ @2op_sz28 .... .... .... .... .... .... .... .... &2op qd=3D%qd qm=3D%qm q= n=3D%qn \ size=3D%size_28 =20 +@vadc .... .... .... .... ... i:1 .... .... .... &vadc qd=3D%qd qm=3D%qm q= n=3D%qn + # The _rev suffix indicates that Vn and Vm are reversed. This is # the case for shifts. In the Arm ARM these insns are documented # with the Vm and Vn fields in their usual places, but in the @@ -160,6 +163,9 @@ VQDMULLT 111 . 1110 0 . 11 ... 0 ... 1 1111 . 0= . 0 ... 1 @2op_sz28 VRHADD_S 111 0 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op VRHADD_U 111 1 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op =20 +VADC 1110 1110 0 . 11 ... 0 ... . 1111 . 0 . 0 ... 0 @vadc +VSBC 1111 1110 0 . 11 ... 0 ... . 1111 . 0 . 0 ... 0 @vadc + # Vector miscellaneous =20 VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index c9434479604..e07f12c8389 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -580,6 +580,36 @@ DO_2OP_U(vrshlu, DO_VRSHLU) DO_2OP_S(vrhadds, DO_RHADD_S) DO_2OP_U(vrhaddu, DO_RHADD_U) =20 +#define DO_VADC(OP, INV) \ + uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, \ + void *vn, void *vm, uint32_t nzcv) \ + { \ + uint32_t *d =3D vd, *n =3D vn, *m =3D vm; = \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + int carry =3D (nzcv & FPCR_C) ? 1 : 0; \ + /* If we do no additions at all the flags are preserved */ \ + bool updates_flags =3D (mask & 0x1111) !=3D 0; = \ + for (e =3D 0; e < 16 / 4; e++, mask >>=3D 4) { = \ + uint64_t r =3D (uint64_t)n[H4(e)] + INV(m[H4(e)]) + carry; \ + if (mask & 1) { \ + carry =3D r >> 32; \ + } \ + uint64_t bytemask =3D mask_to_bytemask4(mask); \ + d[H4(e)] &=3D ~bytemask; \ + d[H4(e)] |=3D (r & bytemask); \ + } \ + mve_advance_vpt(env); \ + if (updates_flags) { \ + nzcv =3D carry ? FPCR_C : 0; \ + } \ + return nzcv; \ + } + +/* VSBC differs only in inverting op2 before the additiona */ +DO_VADC(vadc, ) +DO_VADC(vsbc, DO_NOT) + static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bo= ol *s) { if (val > max) { diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 9a88583385f..2ed499a6de2 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -33,6 +33,7 @@ typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCG= v_i64); +typedef void MVEGenADCFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,= TCGv_i32); =20 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) = */ static inline long mve_qreg_offset(unsigned reg) @@ -737,3 +738,71 @@ static bool trans_VPST(DisasContext *s, arg_VPST *a) } return true; } + +static bool do_vadc(DisasContext *s, arg_vadc *a, MVEGenADCFn fn, + uint32_t fixed_carry) +{ + /* + * VADC and VSBC: these perform an add-with-carry or subtract-with-car= ry + * of the 32-bit elements in each lane of the input vectors, where the + * carry-out of each add is the carry-in of the next. The initial car= ry + * input is either fixed (for the I variant: 0 for VADCI, 1 for VSBCI, + * passed in as fixed_carry) or is from FPSCR.C; the carry out at the + * end is written back to FPSCR.C. + */ + + TCGv_ptr qd, qn, qm; + TCGv_i32 nzcv, fpscr; + + if (!dc_isar_feature(aa32_mve, s)) { + return false; + } + if (a->qd > 7 || a->qn > 7 || a->qm > 7 || !fn) { + return false; + } + if (!mve_eci_check(s)) { + return true; + } + if (!vfp_access_check(s)) { + return true; + } + + /* + * This insn is subject to beat-wise execution. Partial execution + * of an I=3D1 (initial carry input fixed) insn which does not + * execute the first beat must start with the current FPSCR.NZCV + * value, not the fixed constant input. + */ + if (a->i && !mve_skip_first_beat(s)) { + /* Carry input is 0 (VADCI) or 1 (VSBCI), NZV zeroed */ + nzcv =3D tcg_const_i32(fixed_carry); + } else { + /* Carry input from existing NZCV flag values */ + nzcv =3D load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); + tcg_gen_andi_i32(nzcv, nzcv, FPCR_NZCV_MASK); + } + qd =3D mve_qreg_ptr(a->qd); + qn =3D mve_qreg_ptr(a->qn); + qm =3D mve_qreg_ptr(a->qm); + fn(nzcv, cpu_env, qd, qn, qm, nzcv); + fpscr =3D load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); + tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK); + tcg_gen_or_i32(fpscr, fpscr, nzcv); + store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]); + tcg_temp_free_i32(nzcv); + tcg_temp_free_ptr(qd); + tcg_temp_free_ptr(qn); + tcg_temp_free_ptr(qm); + mve_update_eci(s); + return true; +} + +static bool trans_VADC(DisasContext *s, arg_vadc *a) +{ + return do_vadc(s, a, gen_helper_mve_vadc, 0); +} + +static bool trans_VSBC(DisasContext *s, arg_vadc *a) +{ + return do_vadc(s, a, gen_helper_mve_vsbc, FPCR_C); +} --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623088518; cv=none; d=zohomail.com; s=zohoarc; b=Q+zLXgLIufEdLnBVhUp9cKjFE2UfoP5CG0Y8JqY+idPyhs1tlTLOdNqx/gvsDCBQPv58/9Rmbs1Y0WhO1ZaCkgwIrpc21gCgShc6qSPQL/PlPZ5kLVvrygPDht4n2MN++o6eXx+xMbCfoxjsD4Gyjcbasaaz6fcmxhgVdpTJ6MQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623088518; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2oJrX54+hHuJxkwNX+ULxYMNiVeTFery1qUjoDjgSmg=; b=XI603MthK0GBKeQuXKmfhhmmpUqXcc+4H+qZQAxG4yJHNcdIE8xAR97H4JHHPfYMy4cH6sdZmjqhlFbZZHFGW5iIx7+GMeIBsw7feLp4G+SK8akWDc97hy3IyvRb7uXd6FRWVnUVwyew/4mnI7BdnV/gmWnfFalcMJOjHUJ0zeg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623088518852207.0040063917313; Mon, 7 Jun 2021 10:55:18 -0700 (PDT) Received: from localhost ([::1]:51880 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqJT3-0004rH-Jg for importer@patchew.org; Mon, 07 Jun 2021 13:55:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60446) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIbP-0000Qz-SV for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:52 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:36448) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIag-00087i-GH for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:51 -0400 Received: by mail-wm1-x32c.google.com with SMTP id n17-20020a7bc5d10000b0290169edfadac9so126875wmk.1 for ; Mon, 07 Jun 2021 09:59:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.59.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:59:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2oJrX54+hHuJxkwNX+ULxYMNiVeTFery1qUjoDjgSmg=; b=uliYyc0urce3GNKzw8b7WmAfbZjYNj3o+fRRdI0WkiSRgZKHwnlceOjApEH+qn+B5I TLY8M1yVhTpF9gx1qZ78Jmu0qJFg9Yo0wAATBVqZIiIELYVWMO8RR0YW8AswcJZq5znr OZkVmh99Fw/RQssVgm/WWs7ERPagI/tMuEnZE1yOMdRjBY5axQhD/IDaQtUE7zHJx11m 1lefekegqupng0w9I8igyhr4CJsq/bNf3zCqzbugET4hjGIWeDBuxwlrE0C5NaIAzvGf SRg4sXfXrQvMHQ8BdqEpJ3125BVQoBuDwdbFsTSn9ePB82Uf/TVcPAMZU+VD5RhcPp9f XOBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2oJrX54+hHuJxkwNX+ULxYMNiVeTFery1qUjoDjgSmg=; b=D3zzPL6qhjhIRi4hqnDZ74xKVX6cPdmFirU7Njc2nzmk6aqYqdZBnP81XdMTJejhcZ HybCD5SuisSUYK2ShBNwNA60KQYqV+eqpn2ImyMZs8iw9Lw2UGl4fnexyLagkoFKE9dY 2p6GOqbAUuJS/mTbBMFeiJFIVA6Q8Gk14NnWpgzz6FquTY8npoTQIyPgC6Of9AMFgByo egs1fZzZcg6H0OZkuUSy2MxUpZeZ3bnIzlTuJqdvmjhSWP0dqzBxDYIS7+FgCrU+1XxH RQV8NS0RlKfnkpgU8Trj/D+XoqO0FMI27G66i6uvmcou0/Yatn7Pc10X3KWzGu4R79rx b5bQ== X-Gm-Message-State: AOAM533vKIw843HR91+4XiJlSQQ8w8tf8TjR5uQ+ZIqS2+K/Da2Qppf4 xd9UjL6H1/ibHGAG6YmdUBWpSQ== X-Google-Smtp-Source: ABdhPJz0ZEHgWD3LoF55JaTgoCy01U6qHHHDNGHHUZDX4OIBx2y3VSV6wwancGcBba3EJXwGrx5Z1Q== X-Received: by 2002:a05:600c:2284:: with SMTP id 4mr17791680wmf.146.1623085144615; Mon, 07 Jun 2021 09:59:04 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 52/55] target/arm: Implement MVE VCADD Date: Mon, 7 Jun 2021 17:58:18 +0100 Message-Id: <20210607165821.9892-53-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VCADD insn, which performs a complex add with rotate. Note that the size=3D0b11 encoding is VSBC. The architecture grants some leeway for the "destination and Vm source overlap" case for the size MO_32 case, but we choose not to make use of it, instead always calculating all 16 bytes worth of results before setting the destination register. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 8 ++++++++ target/arm/mve.decode | 7 ++++++- target/arm/mve_helper.c | 31 +++++++++++++++++++++++++++++++ target/arm/translate-mve.c | 7 +++++++ 4 files changed, 52 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 686e5d9a39b..6e345470cbb 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -251,6 +251,14 @@ DEF_HELPER_FLAGS_4(mve_vrhadduw, TCG_CALL_NO_WG, void,= env, ptr, ptr, ptr) DEF_HELPER_FLAGS_5(mve_vadc, TCG_CALL_NO_WG, i32, env, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(mve_vsbc, TCG_CALL_NO_WG, i32, env, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(mve_vcadd90b, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcadd90h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcadd90w, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vcadd270b, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcadd270h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vcadd270w, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 6a4aae7a1fc..c0979f3941b 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -164,7 +164,12 @@ VRHADD_S 111 0 1111 0 . .. ... 0 ... 0 0001 . = 1 . 0 ... 0 @2op VRHADD_U 111 1 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op =20 VADC 1110 1110 0 . 11 ... 0 ... . 1111 . 0 . 0 ... 0 @vadc -VSBC 1111 1110 0 . 11 ... 0 ... . 1111 . 0 . 0 ... 0 @vadc + +{ + VCADD90 1111 1110 0 . .. ... 0 ... 0 1111 . 0 . 0 ... 0 @2op + VCADD270 1111 1110 0 . .. ... 0 ... 1 1111 . 0 . 0 ... 0 @2op + VSBC 1111 1110 0 . 11 ... 0 ... . 1111 . 0 . 0 ... 0 @vadc +} =20 # Vector miscellaneous =20 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index e07f12c8389..2c8ef25b208 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -610,6 +610,37 @@ DO_2OP_U(vrhaddu, DO_RHADD_U) DO_VADC(vadc, ) DO_VADC(vsbc, DO_NOT) =20 +#define DO_VCADD(OP, ESIZE, TYPE, H, FN0, FN1) \ + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void= *vm) \ + { \ + TYPE *d =3D vd, *n =3D vn, *m =3D vm; = \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + TYPE r[16 / ESIZE]; \ + /* Calculate all results first to avoid overwriting inputs */ \ + for (e =3D 0; e < 16 / ESIZE; e++) { \ + if (!(e & 1)) { \ + r[e] =3D FN0(n[H(e)], m[H(e + 1)]); \ + } else { \ + r[e] =3D FN1(n[H(e)], m[H(e - 1)]); \ + } \ + } \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { = \ + uint64_t bytemask =3D mask_to_bytemask##ESIZE(mask); \ + d[H(e)] &=3D ~bytemask; \ + d[H(e)] |=3D (r[e] & bytemask); \ + } \ + mve_advance_vpt(env); \ + } + +#define DO_VCADD_ALL(OP, FN0, FN1) \ + DO_VCADD(OP##b, 1, int8_t, H1, FN0, FN1) \ + DO_VCADD(OP##h, 2, int16_t, H1, FN0, FN1) \ + DO_VCADD(OP##w, 4, int32_t, H1, FN0, FN1) + +DO_VCADD_ALL(vcadd90, DO_SUB, DO_ADD) +DO_VCADD_ALL(vcadd270, DO_ADD, DO_SUB) + static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bo= ol *s) { if (val > max) { diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 2ed499a6de2..8e3989b0176 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -440,6 +440,13 @@ DO_2OP(VQRDMLSDH, vqrdmlsdh) DO_2OP(VQRDMLSDHX, vqrdmlsdhx) DO_2OP(VRHADD_S, vrhadds) DO_2OP(VRHADD_U, vrhaddu) +/* + * VCADD Qd =3D=3D Qm at size MO_32 is UNPREDICTABLE; we choose not to dia= gnose + * so we can reuse the DO_2OP macro. (Our implementation calculates the + * "expected" results in this case.) + */ +DO_2OP(VCADD90, vcadd90) +DO_2OP(VCADD270, vcadd270) =20 static bool trans_VQDMULLB(DisasContext *s, arg_2op *a) { --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623087997; cv=none; d=zohomail.com; s=zohoarc; b=RifJfi5DanJhZEKHo6mGEX0B+aLY5HoXEStcNnjZE/Iyvjh44WPSGBxzPN5FHorZpuoPZgs9yMgQ0UpqiB4KlYhyL5/pS1Y9HkABeivjJ4VTzr0AB5aaQbcsk/yGE3rpM3+EGZ4fLonr+G02akVy4ANs4q8hX3m2KMyPhvPU1zA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623087997; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZpgHoqnBmOkzqr58mneEyeBuRbOpEZqrC/tcPvjTIAc=; b=PpmveOouuvEwLPVE0QC+N0lJFYHlPJ/BIcKLgv/DS3kGw3QGCV11Hj4Dyn8DhbicTaJHqLj4HBNRZKmQi7bhJbH/NYTfVC5zg5NkoaeIRnSHgEOD1GxxVNjiGgkOf9sqp1iF0Vklh02B+ZEzdLL6DMJwTxl6LHtJiaLeoDNpQgo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623087997005185.27271317228974; Mon, 7 Jun 2021 10:46:37 -0700 (PDT) Received: from localhost ([::1]:50686 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqJKd-00027n-SO for importer@patchew.org; Mon, 07 Jun 2021 13:46:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60490) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIbT-0000Vj-1C for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:57 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:39864) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIag-00088S-Th for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:54 -0400 Received: by mail-wm1-x32c.google.com with SMTP id l18-20020a1ced120000b029014c1adff1edso103391wmh.4 for ; Mon, 07 Jun 2021 09:59:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.59.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:59:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZpgHoqnBmOkzqr58mneEyeBuRbOpEZqrC/tcPvjTIAc=; b=zaDcXdZYuPaLxXrc8+yy6DvgriO/W8e23iDmNoDp5l+ibmuEO+LdFl5wweyaXLk/JT U2TixxRJCVoCI98o3w8eIzK7peftEUroOB/+666N/pMnJZ+ASEMSLWTRZ9suAfV5643G FyW6ft9UMDSrFRPwXvFOTJBeTewtCc0QgRZSS28aikJ20hQpw/V67JO4uISBl6Gm0xCv ZtljD3faPR3XNdVH52G31GfxGNByna7SymPm52LxnJWvadbeQJix5tmgtkfDM6H+RXa9 SkH1jmAbmEFOE0eCWkblCzjlDtvBWw6ItCxtypLj3knb7wRR3PckJa/A3NE0sMmJpCng EPtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZpgHoqnBmOkzqr58mneEyeBuRbOpEZqrC/tcPvjTIAc=; b=C4u5HDHBavhJG9FPI5g5lM6AF9oakndCeNZ29k9NHjLJk//lS3371Nal3MtnNNVndW kl+2k0X2Z4XTOaCtmTMSXKoaPgN6i+VNdKQfRcGA0uvLwlrh/SNKO4PIXNUv4syIL/1x Hzv7S/AxuIG5R0H7k1vt7Lsl+pFnJnxpUVaaFcwKeIhMP5pqcR6iU5TnFtwVx7QmVOwF fc3atrmQUTNQ0CmtOHwYUeiFCpuKOYbyfzst0c1poUol/rC/A2ajoTTaKxpE2gWcrXdO KHtBdVdeXPKxghanSowOGmIWmIJzOMWJJW0o0LOOGVJYy4g7xJqFcxQAW0p8BNzETrkF 2Irg== X-Gm-Message-State: AOAM531QNvqbNhTIoFTb0h0JHVAsRkRK0tt7l4NMHZUG2SpoOkd5YP2+ WEGRAmnBKjqojDRp/3bBYw6lEQ== X-Google-Smtp-Source: ABdhPJyDQKqx0vdVxxzh/c5jU1Ic8/n2+CUXS1zHJO9bu67D5d2nW80H6H+QKUtQN9otIS0SYL0Eng== X-Received: by 2002:a1c:ed10:: with SMTP id l16mr103897wmh.8.1623085145328; Mon, 07 Jun 2021 09:59:05 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 53/55] target/arm: Implement MVE VHCADD Date: Mon, 7 Jun 2021 17:58:19 +0100 Message-Id: <20210607165821.9892-54-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VHCADD insn, which is similar to VCADD but performs a halving step. This one overlaps with VADC. Signed-off-by: Peter Maydell --- target/arm/helper-mve.h | 8 ++++++++ target/arm/mve.decode | 6 +++++- target/arm/mve_helper.c | 5 +++++ target/arm/translate-mve.c | 4 +++- 4 files changed, 21 insertions(+), 2 deletions(-) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 6e345470cbb..3f056e67871 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -259,6 +259,14 @@ DEF_HELPER_FLAGS_4(mve_vcadd270b, TCG_CALL_NO_WG, void= , env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vcadd270h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) DEF_HELPER_FLAGS_4(mve_vcadd270w, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) =20 +DEF_HELPER_FLAGS_4(mve_vhcadd90b, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vhcadd90h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) +DEF_HELPER_FLAGS_4(mve_vhcadd90w, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) + +DEF_HELPER_FLAGS_4(mve_vhcadd270b, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) +DEF_HELPER_FLAGS_4(mve_vhcadd270h, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) +DEF_HELPER_FLAGS_4(mve_vhcadd270w, TCG_CALL_NO_WG, void, env, ptr, ptr, pt= r) + DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, = i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index c0979f3941b..23ae12b7a38 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -163,7 +163,11 @@ VQDMULLT 111 . 1110 0 . 11 ... 0 ... 1 1111 . = 0 . 0 ... 1 @2op_sz28 VRHADD_S 111 0 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op VRHADD_U 111 1 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op =20 -VADC 1110 1110 0 . 11 ... 0 ... . 1111 . 0 . 0 ... 0 @vadc +{ + VHCADD90 1110 1110 0 . .. ... 0 ... 0 1111 . 0 . 0 ... 0 @2op + VHCADD270 1110 1110 0 . .. ... 0 ... 1 1111 . 0 . 0 ... 0 @2op + VADC 1110 1110 0 . 11 ... 0 ... . 1111 . 0 . 0 ... 0 @vadc +} =20 { VCADD90 1111 1110 0 . .. ... 0 ... 0 1111 . 0 . 0 ... 0 @2op diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 2c8ef25b208..3477d2bb191 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -638,8 +638,13 @@ DO_VADC(vsbc, DO_NOT) DO_VCADD(OP##h, 2, int16_t, H1, FN0, FN1) \ DO_VCADD(OP##w, 4, int32_t, H1, FN0, FN1) =20 +#define DO_HADD(N, M) (((int64_t)(N) + (int64_t)(M)) >> 1) +#define DO_HSUB(N, M) (((int64_t)(N) - (int64_t)(M)) >> 1) + DO_VCADD_ALL(vcadd90, DO_SUB, DO_ADD) DO_VCADD_ALL(vcadd270, DO_ADD, DO_SUB) +DO_VCADD_ALL(vhcadd90, DO_HSUB, DO_HADD) +DO_VCADD_ALL(vhcadd270, DO_HADD, DO_HSUB) =20 static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bo= ol *s) { diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 8e3989b0176..b2020bd90b1 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -443,10 +443,12 @@ DO_2OP(VRHADD_U, vrhaddu) /* * VCADD Qd =3D=3D Qm at size MO_32 is UNPREDICTABLE; we choose not to dia= gnose * so we can reuse the DO_2OP macro. (Our implementation calculates the - * "expected" results in this case.) + * "expected" results in this case.) Similarly for VHCADD. */ DO_2OP(VCADD90, vcadd90) DO_2OP(VCADD270, vcadd270) +DO_2OP(VHCADD90, vhcadd90) +DO_2OP(VHCADD270, vhcadd270) =20 static bool trans_VQDMULLB(DisasContext *s, arg_2op *a) { --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623088617; cv=none; d=zohomail.com; s=zohoarc; b=DgvPOOmLr+kmxOacEPzYW9AbDGWgibk7yYuw6DD+C9lhoYOXcIuDQQwdHuXqaWoHuiIAezP2pH8nvp57HGoKv61RYnXAQRHuYugfkJHq/VkZf8e3dNIb2Ba6z8u6szeqOSEZIZ1QzpeNRhBDOzUoESF33Q34Vcr3/F4vPRcos34= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623088617; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/0Pzr5dolqTpGYbgOUV73R4nwkTVq7BcD7SErgBnXGg=; b=YbuCMDWetiMIjizO8b9m4+LBvVNEiHeyUivqFZsB1H3zLkE5YYnzUiuh62YE3ZuIFwhAKoA5InVtyDIETzN3w6V6ERYY/WFw2scC2XttdYgMOYIUQPftnEoTfW1l98WBhFDWKnhoJP0yNqChHzxAYSgCB9zQ1AiJIpB6xwvhlag= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623088617598815.5947877240037; Mon, 7 Jun 2021 10:56:57 -0700 (PDT) Received: from localhost ([::1]:58362 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqJUe-0000oI-Ha for importer@patchew.org; Mon, 07 Jun 2021 13:56:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60488) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIbT-0000Vi-1K for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:57 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:53883) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIah-00088Y-DO for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:54 -0400 Received: by mail-wm1-x32d.google.com with SMTP id h3so92276wmq.3 for ; Mon, 07 Jun 2021 09:59:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.59.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:59:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/0Pzr5dolqTpGYbgOUV73R4nwkTVq7BcD7SErgBnXGg=; b=sUELHhYXxxlGEkGj12vzr+h9UhAAxSBmYhjFWjWCoti6RfcJ7CexgMcLtLhiHP2rfQ bAWb5KDnfsDJQZ7KADXj+cfnjJrszLj4YpTcaonNTd5eURxc6w1NBt03Erx3zVUAIFlu UqziNBArl4D80NKU0mk49jgptJwudBPhVK1vGYQKamivLGs5QiMfnRrsreKlQolToP/c UAXSRQfatvfjgKDjEDWikH/j6aWjCpY41pMOjd4mlcfoqfvz+gHLl6BHOFrq+fW4efj1 PSxVeZhucscfoj8ephq7LWP9+WDxzplEGcYqPHuzPku/qRoPSSocVcXEWgOp28oSTrHJ ztPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/0Pzr5dolqTpGYbgOUV73R4nwkTVq7BcD7SErgBnXGg=; b=F19RSp7PLj0X6KUVWUisNAW1taV+DlJNHu7pprNNORIJxOAOYt/6mXKs6W1yS/hQtW 7+UAEeLanbst5s5SyNlpqP3fy2eqpMPTq7XUWvqD9D++ik/3U8BK4EGE2IyNLCzCkrj5 lCixGMVsKY9qauYiboUKrOg2ULNZbtNZd10F386AzrURcCV/XbDWmVOUfN+XtrD/rGVb 6oDE7UAx/E7EQAK1Sa1EqycgLq/n6CHuUulZGt/Yze7ri9MhkubJXT9BvLhvl3gXWkS3 OtcsnxM+qyAVPz8CHzxcnbiL+SYPHti5xvftN7D7nOie8hB5hKGMwll5YC+C2RUo9qMz vxoA== X-Gm-Message-State: AOAM532ZZmQmB+jieMmaQQElZtAFAyGcz23wcS4hapyXlJ8nMQ9SG3Gq QSET0EI2CVT6/1tCv63frCxNFM3dmKkM1vgl X-Google-Smtp-Source: ABdhPJxn7eY91vLNL+Gx2Kb/8lW8e/dHT+6ejtFKJtnQ9QOUom3enTv56EAIYmrd9zSTSywmEnajBw== X-Received: by 2002:a7b:c2e8:: with SMTP id e8mr13195257wmk.41.1623085146173; Mon, 07 Jun 2021 09:59:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 54/55] target/arm: Implement MVE VADDV Date: Mon, 7 Jun 2021 17:58:20 +0100 Message-Id: <20210607165821.9892-55-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement the MVE VADDV insn, which performs an addition across vector lanes. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper-mve.h | 7 ++++++ target/arm/mve.decode | 2 ++ target/arm/mve_helper.c | 24 +++++++++++++++++++ target/arm/translate-mve.c | 48 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 81 insertions(+) diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h index 3f056e67871..c1ef44d5927 100644 --- a/target/arm/helper-mve.h +++ b/target/arm/helper-mve.h @@ -348,3 +348,10 @@ DEF_HELPER_FLAGS_4(mve_vrmlaldavhuw, TCG_CALL_NO_WG, i= 64, env, ptr, ptr, i64) =20 DEF_HELPER_FLAGS_4(mve_vrmlsldavhsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i= 64) DEF_HELPER_FLAGS_4(mve_vrmlsldavhxsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, = i64) + +DEF_HELPER_FLAGS_3(mve_vaddvsb, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vaddvub, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32) +DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) diff --git a/target/arm/mve.decode b/target/arm/mve.decode index 23ae12b7a38..bfbf8cf4252 100644 --- a/target/arm/mve.decode +++ b/target/arm/mve.decode @@ -253,6 +253,8 @@ VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 11= 0 .... @2scalar VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar =20 +# Vector add across vector +VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 r= da=3D%rdalo =20 # Predicate operations %mask_22_13 22:1 13:3 diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c index 3477d2bb191..191eb3f58aa 100644 --- a/target/arm/mve_helper.c +++ b/target/arm/mve_helper.c @@ -1317,3 +1317,27 @@ DO_LDAVH(vrmlaldavhuw, 4, uint32_t, H4, false, int12= 8_add, int128_add, int128_ma =20 DO_LDAVH(vrmlsldavhsw, 4, int32_t, H4, false, int128_add, int128_sub, int1= 28_makes64) DO_LDAVH(vrmlsldavhxsw, 4, int32_t, H4, true, int128_add, int128_sub, int1= 28_makes64) + +/* Vector add across vector */ +#define DO_VADDV(OP, ESIZE, TYPE, H) \ + uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ + uint32_t ra) \ + { \ + uint16_t mask =3D mve_element_mask(env); \ + unsigned e; \ + TYPE *m =3D vm; \ + for (e =3D 0; e < 16 / ESIZE; e++, mask >>=3D ESIZE) { \ + if (mask & 1) { \ + ra +=3D m[H(e)]; \ + } \ + } \ + mve_advance_vpt(env); \ + return ra; \ + } \ + +DO_VADDV(vaddvsb, 1, uint8_t, H1) +DO_VADDV(vaddvsh, 2, uint16_t, H2) +DO_VADDV(vaddvsw, 4, uint32_t, H4) +DO_VADDV(vaddvub, 1, uint8_t, H1) +DO_VADDV(vaddvuh, 2, uint16_t, H2) +DO_VADDV(vaddvuw, 4, uint32_t, H4) diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index b2020bd90b1..1794c50d0e8 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -34,6 +34,7 @@ typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, = TCGv_ptr); typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCG= v_i64); typedef void MVEGenADCFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr,= TCGv_i32); +typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32); =20 /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) = */ static inline long mve_qreg_offset(unsigned reg) @@ -815,3 +816,50 @@ static bool trans_VSBC(DisasContext *s, arg_vadc *a) { return do_vadc(s, a, gen_helper_mve_vsbc, FPCR_C); } + +static bool trans_VADDV(DisasContext *s, arg_VADDV *a) +{ + /* VADDV: vector add across vector */ + MVEGenVADDVFn *fns[4][2] =3D { + { gen_helper_mve_vaddvsb, gen_helper_mve_vaddvub }, + { gen_helper_mve_vaddvsh, gen_helper_mve_vaddvuh }, + { gen_helper_mve_vaddvsw, gen_helper_mve_vaddvuw }, + { NULL, NULL } + }; + TCGv_ptr qm; + TCGv_i32 rda; + + if (!dc_isar_feature(aa32_mve, s)) { + return false; + } + if (a->size =3D=3D 3) { + return false; + } + if (!mve_eci_check(s)) { + return true; + } + if (!vfp_access_check(s)) { + return true; + } + + /* + * This insn is subject to beat-wise execution. Partial execution + * of an A=3D0 (no-accumulate) insn which does not execute the first + * beat must start with the current value of Rda, not zero. + */ + if (a->a || mve_skip_first_beat(s)) { + /* Accumulate input from Rda */ + rda =3D load_reg(s, a->rda); + } else { + /* Accumulate starting at zero */ + rda =3D tcg_const_i32(0); + } + + qm =3D mve_qreg_ptr(a->qm); + fns[a->size][a->u](rda, cpu_env, qm, rda); + store_reg(s, a->rda, rda); + tcg_temp_free_ptr(qm); + + mve_update_eci(s); + return true; +} --=20 2.20.1 From nobody Sat May 11 18:12:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1623087413; cv=none; d=zohomail.com; s=zohoarc; b=ZFUi5sGMndfTcc2uyq5SqT+oJr9WbaY7q7DFdpmouLz4IFfxkM7fmrmtILSi7C1GdK8eM9r+bJB4tb5yNd5PRzVBRz3lf3oIOpDZWb7r/9E0uqDYgSc1jWnLpnZdbFdGrSDNfXWeYISRKrZCFUJvfAHF5FWfTtcuPlaqqeyA7LQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1623087413; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VBu3YA9+F6FYdoX63F7dNFFdaXyzuQNEsH4ibbS/t54=; b=b18uqsWTNQD1QDxmA6jLvi1N9FlTwPDna9UOlwDI/UzjFd5zj9qVXFRa5wZ+6gCFtkt71m23x9gyms0e+59FmoPPJ93kpHRyyBpkAQzBI16oGBwzOfK9OC5EQTWEEOJZfBV6XCL7FM6FN7oU+5I/422KfPaxl1rT7a7mjBcawMk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1623087413009101.01857138120329; Mon, 7 Jun 2021 10:36:53 -0700 (PDT) Received: from localhost ([::1]:56558 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lqJBB-0003D6-PM for importer@patchew.org; Mon, 07 Jun 2021 13:36:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60506) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lqIbU-0000W6-58 for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:58 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:55862) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lqIai-000890-V2 for qemu-devel@nongnu.org; Mon, 07 Jun 2021 12:59:55 -0400 Received: by mail-wm1-x32e.google.com with SMTP id g204so85709wmf.5 for ; Mon, 07 Jun 2021 09:59:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id n10sm18891677wre.95.2021.06.07.09.59.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Jun 2021 09:59:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VBu3YA9+F6FYdoX63F7dNFFdaXyzuQNEsH4ibbS/t54=; b=qnqEO1Zhmlh/8VEJsGb4qHfibbLe9uDJzdgyQFF1QoZlNiTTNmyDyz5EYUNC8jasyc YnxEHmjBQgDcX6eFlgzEqQ6KeLGS4g4ZFNuOtfZMuBh0EliudSpIsGwQbr3Bt2ZXPxJ2 Llt+esVTibsLRm9KMVm/yOFb+tVcKCVzp0T6vCvvXVaGXeqN4G6Wo6mE5Q5PQGMhuRhb UbOfPExoMHY5Px9PKR/Tlt3SAlWjUU4Tofb440W6KpikyAZRKBwd4t0Ljqgwg4YkquzU vPg2PeAz/FuL5GP8312RZ5I/Y+KFz0jc+wmd2SVQG6FNw/oUjC8fOlU3euYtf7TZlZl2 qSLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VBu3YA9+F6FYdoX63F7dNFFdaXyzuQNEsH4ibbS/t54=; b=HCFX6CYJkTy3ETu6iogRTzXLKgn3b47cWy8M/sm5V/Y62jU496MdQn2qJXIcfZW2tD zi45FcOp2K5D9PzCE8ugu190fyDRnKOx/SG/C8D5/gjEvLxD9rkg0YwD6eozgqhMurKn h+LSNPMsAMScFhTiPqP3c3MRHn79TmElMUp2zR0227WTOq6mSXlWsJ/x6sP/oO0QEFF3 zQFatv5J6cWWJBSFHNNpgKXrGF96REE7HltqwfqGrldfVBWORPRSrMxdQREYfHjZva7u 4AWr32hRsGhikEegUADF2gCC+GuQIrZ6F99aDRv5K1SIJPr+iFMJYTi+zf3Rvvk+xZJ4 /+FQ== X-Gm-Message-State: AOAM533KGL5OlurjT4wjHnqzTbUOUPcEkf9L0GGA1TB/giaxUBvw6YYa rz6Qp8zQU+tUZ9jMUcTMqr+Kvu3chNwCb1EL X-Google-Smtp-Source: ABdhPJziYiiDgJ2Roh6PIByCRVgaq8XxetXdetAiLXMI3KBt5CYLtBB7FxqYfL+607E9MBEnDfowrg== X-Received: by 2002:a05:600c:3790:: with SMTP id o16mr65822wmr.41.1623085146946; Mon, 07 Jun 2021 09:59:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 55/55] target/arm: Make VMOV scalar <-> gpreg beatwise for MVE Date: Mon, 7 Jun 2021 17:58:21 +0100 Message-Id: <20210607165821.9892-56-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210607165821.9892-1-peter.maydell@linaro.org> References: <20210607165821.9892-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In a CPU with MVE, the VMOV (vector lane to general-purpose register) and VMOV (general-purpose register to vector lane) insns are not predicated, but they are subject to beatwise execution if they are not in an IT block. Since our implementation always executes all 4 beats in one tick, this means only that we need to handle PSR.ECI: * we must do the usual check for bad ECI state * we must advance ECI state if the insn succeeds * if ECI says we should not be executing the beat corresponding to the lane of the vector register being accessed then we should skip performing the move Note that if PSR.ECI is non-zero then we cannot be in an IT block. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate-a32.h | 2 + target/arm/translate-mve.c | 4 +- target/arm/translate-vfp.c | 85 +++++++++++++++++++++++++++++++++++--- 3 files changed, 83 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index 0a0053949f5..6d384fc7966 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -46,6 +46,8 @@ long neon_full_reg_offset(unsigned reg); long neon_element_offset(int reg, int element, MemOp memop); void gen_rev16(TCGv_i32 dest, TCGv_i32 var); void clear_eci_state(DisasContext *s); +bool mve_eci_check(DisasContext *s); +void mve_update_eci(DisasContext *s); =20 static inline TCGv_i32 load_cpu_offset(int offset) { diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 1794c50d0e8..b62e355a1a3 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -49,7 +49,7 @@ static TCGv_ptr mve_qreg_ptr(unsigned reg) return ret; } =20 -static bool mve_eci_check(DisasContext *s) +bool mve_eci_check(DisasContext *s) { /* * This is a beatwise insn: check that ECI is valid (not a @@ -72,7 +72,7 @@ static bool mve_eci_check(DisasContext *s) } } =20 -static void mve_update_eci(DisasContext *s) +void mve_update_eci(DisasContext *s) { /* * The helper function will always update the CPUState field, diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 6a572591ce9..b5bb8230cd9 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -553,6 +553,48 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) return true; } =20 +static bool mve_skip_vmov(DisasContext *s, int vn, int index, int size) +{ + /* + * In a CPU with MVE, the VMOV (vector lane to general-purpose registe= r) + * and VMOV (general-purpose register to vector lane) insns are not + * predicated, but they are subject to beatwise execution if they are + * not in an IT block. + * + * Since our implementation always executes all 4 beats in one tick, + * this means only that if PSR.ECI says we should not be executing + * the beat corresponding to the lane of the vector register being + * accessed then we should skip performing the move, and that we need + * to do the usual check for bad ECI state and advance of ECI state. + * + * Note that if PSR.ECI is non-zero then we cannot be in an IT block. + * + * Return true if this VMOV scalar <-> gpreg should be skipped because + * the MVE PSR.ECI state says we skip the beat where the store happens. + */ + + /* Calculate the byte offset into Qn which we're going to access */ + int ofs =3D (index << size) + ((vn & 1) * 8); + + if (!dc_isar_feature(aa32_mve, s)) { + return false; + } + + switch (s->eci) { + case ECI_NONE: + return false; + case ECI_A0: + return ofs < 4; + case ECI_A0A1: + return ofs < 8; + case ECI_A0A1A2: + case ECI_A0A1A2B0: + return ofs < 12; + default: + g_assert_not_reached(); + } +} + static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) { /* VMOV scalar to general purpose register */ @@ -575,14 +617,30 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMO= V_to_gp *a) return false; } =20 + if (dc_isar_feature(aa32_mve, s)) { + if (!mve_eci_check(s)) { + return true; + } + } + if (!vfp_access_check(s)) { return true; } =20 - tmp =3D tcg_temp_new_i32(); - read_neon_element32(tmp, a->vn, a->index, a->size | (a->u ? 0 : MO_SIG= N)); - store_reg(s, a->rt, tmp); + if (!mve_skip_vmov(s, a->vn, a->index, a->size)) { + tmp =3D tcg_temp_new_i32(); + read_neon_element32(tmp, a->vn, a->index, + a->size | (a->u ? 0 : MO_SIGN)); + store_reg(s, a->rt, tmp); + } =20 + if (dc_isar_feature(aa32_mve, s)) { + TCGv_i32 eci; + + mve_update_eci(s); + eci =3D tcg_const_i32(s->eci << 4); + store_cpu_field(eci, condexec_bits); + } return true; } =20 @@ -608,14 +666,29 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_V= MOV_from_gp *a) return false; } =20 + if (dc_isar_feature(aa32_mve, s)) { + if (!mve_eci_check(s)) { + return true; + } + } + if (!vfp_access_check(s)) { return true; } =20 - tmp =3D load_reg(s, a->rt); - write_neon_element32(tmp, a->vn, a->index, a->size); - tcg_temp_free_i32(tmp); + if (!mve_skip_vmov(s, a->vn, a->index, a->size)) { + tmp =3D load_reg(s, a->rt); + write_neon_element32(tmp, a->vn, a->index, a->size); + tcg_temp_free_i32(tmp); + } =20 + if (dc_isar_feature(aa32_mve, s)) { + TCGv_i32 eci; + + mve_update_eci(s); + eci =3D tcg_const_i32(s->eci << 4); + store_cpu_field(eci, condexec_bits); + } return true; } =20 --=20 2.20.1