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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana we need to be careful not to use if (tcg_enabled()) here, because of the VMSTATE definitions in machine.c, which are only protected by CONFIG_TCG, and thus it would break the --enable-tcg --enable-kvm build. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/tcg-cpu.h | 1 + target/arm/cpu.c | 30 ++++--------------------- target/arm/tcg/sysemu/tcg-cpu.c | 40 +++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/tcg-cpu.h b/target/arm/tcg/tcg-cpu.h index dd08587949..3e4ce2c355 100644 --- a/target/arm/tcg/tcg-cpu.h +++ b/target/arm/tcg/tcg-cpu.h @@ -33,6 +33,7 @@ void tcg_arm_init_accel_cpu(AccelCPUClass *accel_cpu, CPU= Class *cc); /* Do semihosting call and set the appropriate return value. */ void tcg_handle_semihosting(CPUState *cs); bool tcg_cpu_realizefn(CPUState *cs, Error **errp); +bool tcg_cpu_realize_gt_timers(CPUState *cs, Error **errp); =20 #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 945dfbbe9d..2fef8ca471 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -859,32 +859,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) bool no_aa32 =3D false; =20 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) - { - uint64_t scale; - - if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { - if (!cpu->gt_cntfrq_hz) { - error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", - cpu->gt_cntfrq_hz); - return; - } - scale =3D gt_cntfrq_period_ns(cpu); - } else { - scale =3D GTIMER_SCALE; - } - - cpu->gt_timer[GTIMER_PHYS] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, - arm_gt_ptimer_cb, cpu); - cpu->gt_timer[GTIMER_VIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, - arm_gt_vtimer_cb, cpu); - cpu->gt_timer[GTIMER_HYP] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, - arm_gt_htimer_cb, cpu); - cpu->gt_timer[GTIMER_SEC] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, - arm_gt_stimer_cb, cpu); - cpu->gt_timer[GTIMER_HYPVIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, sc= ale, - arm_gt_hvtimer_cb, cpu); - } -#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ + if (!tcg_cpu_realize_gt_timers(cs, errp)) { + return; + } +#endif =20 cpu_exec_realizefn(cs, &local_err); if (local_err !=3D NULL) { diff --git a/target/arm/tcg/sysemu/tcg-cpu.c b/target/arm/tcg/sysemu/tcg-cp= u.c index 115ac523dc..1c6df15092 100644 --- a/target/arm/tcg/sysemu/tcg-cpu.c +++ b/target/arm/tcg/sysemu/tcg-cpu.c @@ -54,6 +54,46 @@ void tcg_handle_semihosting(CPUState *cs) } } =20 +/* + * we cannot use tcg_enabled() to condition the call to this function, + * due to the fields VMSTATE definitions in machine.c : it would break + * the --enable-tcg --enable-kvm build. We need to run this code whenever + * CONFIG_TCG is true, regardless of the chosen accelerator. + * + * So we cannot call this from tcg_cpu_realizefn, as this needs to + * be called whenever TCG is built-in, regardless of whether it is + * enabled or not. + */ +bool tcg_cpu_realize_gt_timers(CPUState *cs, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + uint64_t scale; + + if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { + if (!cpu->gt_cntfrq_hz) { + error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", + cpu->gt_cntfrq_hz); + return false; + } + scale =3D gt_cntfrq_period_ns(cpu); + } else { + scale =3D GTIMER_SCALE; + } + + cpu->gt_timer[GTIMER_PHYS] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_ptimer_cb, cpu); + cpu->gt_timer[GTIMER_VIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_vtimer_cb, cpu); + cpu->gt_timer[GTIMER_HYP] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_htimer_cb, cpu); + cpu->gt_timer[GTIMER_SEC] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_stimer_cb, cpu); + cpu->gt_timer[GTIMER_HYPVIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_hvtimer_cb, cpu); + return true; +} + bool tcg_cpu_realizefn(CPUState *cs, Error **errp) { ARMCPU *cpu =3D ARM_CPU(cs); --=20 2.20.1