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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana before refactoring the exception code, fix the style of the functions being moved. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/helper.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index 7a9eaec5cb..5b32329895 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -896,10 +896,11 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) new_mode =3D ARM_CPU_MODE_UND; addr =3D 0x04; mask =3D CPSR_I; - if (env->thumb) + if (env->thumb) { offset =3D 2; - else + } else { offset =3D 4; + } break; case EXCP_SWI: new_mode =3D ARM_CPU_MODE_SVC; @@ -985,7 +986,8 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) /* High vectors. When enabled, base address cannot be remapped. */ addr +=3D 0xffff0000; } else { - /* ARM v7 architectures provide a vector base address register to = remap + /* + * ARM v7 architectures provide a vector base address register to = remap * the interrupt vector table. * This register is only followed in non-monitor mode, and is bank= ed. * Note: only bits 31:5 are valid. @@ -1094,7 +1096,8 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); =20 if (cur_el < new_el) { - /* Entry vector offset depends on whether the implemented EL + /* + * Entry vector offset depends on whether the implemented EL * immediately lower than the target level is using AArch32 or AAr= ch64 */ bool is_aa64; @@ -1285,7 +1288,8 @@ static void handle_semihosting(CPUState *cs) } #endif =20 -/* Handle a CPU exception for A and R profile CPUs. +/* + * Handle a CPU exception for A and R profile CPUs. * Do any appropriate logging, handle PSCI calls, and then hand off * to the AArch64-entry or AArch32-entry function depending on the * target exception level's register width. @@ -1330,7 +1334,8 @@ void arm_cpu_do_interrupt(CPUState *cs) } #endif =20 - /* Hooks may change global state so BQL should be held, also the + /* + * Hooks may change global state so BQL should be held, also the * BQL needs to be held for any modification of * cs->interrupt_request. */ --=20 2.20.1