From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622822220; cv=none; d=zohomail.com; s=zohoarc; b=XmGgkvrWI+L+IuEuSGc5sKOJWl+cJxYmKbtg1k/nxzd/hhByX3hCB7Wk1BXVyLhN73c9aeeLBnoJSyUtVD+mn+7EEXZXLFSUf5xKhCA1u0tIWQs9Hg6i1J4sPPHOVLte5xdhjCw5Nq1/iIHupWfcEu0kep1fe10Px0NUWuLKsLM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622822220; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VydS99WQVqx+ym7s6ppugDiseMCd9bc+7KSAd2+foIM=; b=gShB5KE9IjbUw/L4jw4/3OA8ImiMT6sUpO6zYZSEl7rHyvSePFwOf2iKljEt1wvMljaAOFY7D871Ho/0bKg7NNefcU59iEBizxIkZl3//tDKv1LajSCMRmnoCJadxzBNpfd2Dq84JypzyFcj9CgmY+oWt+omvjeHO+RI0BW0dPc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622822220826621.4812068297418; Fri, 4 Jun 2021 08:57:00 -0700 (PDT) Received: from localhost ([::1]:56354 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCBv-0002wO-Mh for importer@patchew.org; Fri, 04 Jun 2021 11:56:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44214) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8P-0002HP-56 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:21 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:36566) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8L-0008MO-Uk for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:20 -0400 Received: by mail-wm1-x32b.google.com with SMTP id n17-20020a7bc5d10000b0290169edfadac9so8215266wmk.1 for ; Fri, 04 Jun 2021 08:53:15 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id f20sm6989289wmh.41.2021.06.04.08.53.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:13 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 6EA4D1FF87; Fri, 4 Jun 2021 16:53:12 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VydS99WQVqx+ym7s6ppugDiseMCd9bc+7KSAd2+foIM=; b=d8VWgbOfZnuu1mRgSriDmrd+UlQFOHJFhDh4AVTwPPW7YAh2cthrWurREZLLC7MKcQ uw2wu9zbbFPivCW+Br6usiYwz1IwMy8ylMmpzynJPiT/DTafq+bdPSaDzODoE2eX8vGH IKPf6q7crBG08MwtnXp9irnfMBA9TJWtprUO9taAiPjjkYTPJ4A9Y0O/cppP0CA5u7qH pYcoEUoyTTdfKhg9vRmmvfOVYbrYmG7aIAULdVJLcPG7ovL3Aycy9u3kKzR1V9LvMXaw LyBin32NpmXjwNdWCzEf5DBLikMxcKxuGWvcac0Y2J1NmTy0X4ELJuxPadIkMuDPp4lh 3Rvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VydS99WQVqx+ym7s6ppugDiseMCd9bc+7KSAd2+foIM=; b=DVAP6wKeayakZ8eDNTRWKe/tzoR17qd5+UO8Mdk5WhZhFK2m2/7Yg0Zi9uVLy7zbDd Y9BAqBUsbszQPIpbK+RIpmJ98IMBwSXXMqRV97Up/BsGvqMLDFeTuxZrzwxNbjaBGB9a 37UiZHpBaE7RkQPxLfyNZNR7fgj987+HNOM0Aq3DKC+WXj7dSkLSLGigGekoIR3W/rNa b4lIThiaLeo3/TMBOYJLdn/ZNwieGMFkfYkcoAI4fTNMty9+qTeMjSwekaurqmpVGBnU hiTlTiHPLRFWAh8MBuk5K4tub8ey8TxMR+aOFWmBst94q8yhFiVvWPkJj6PuEsrM19M+ 9Qhw== X-Gm-Message-State: AOAM532q4jpyi69nSVgpXlWemML555utx1+KBM03v3sd31xq51IAx/2P zvF2F4t9k4+o+BnyMun+1anP9g== X-Google-Smtp-Source: ABdhPJzQW7oUjaCYviGoJOnjOWcdXQSbB+AWU8JaI39cpje9osRaSMwlnLyHlVNbZzQg8DZzTy0lwA== X-Received: by 2002:a7b:c095:: with SMTP id r21mr4374471wmh.86.1622821994736; Fri, 04 Jun 2021 08:53:14 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 01/99] MAINTAINERS: Add qtest/arm-cpu-features.c to ARM TCG CPUs section Date: Fri, 4 Jun 2021 16:51:34 +0100 Message-Id: <20210604155312.15902-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Andrew Jones , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 We want the ARM maintainers and the qemu-arm@ list to be notified when this file is modified. Add an entry to the 'ARM TCG CPUs' section in the MAINTAINERS file. Acked-by: Andrew Jones Reviewed-by: Thomas Huth Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Alex Benn=C3=A9e Message-Id: <20210505125806.1263441-2-philmd@redhat.com> Reviewed-by: Richard Henderson --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 96a4eeb5a5..1ff68116b0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -155,6 +155,7 @@ S: Maintained F: target/arm/ F: tests/tcg/arm/ F: tests/tcg/aarch64/ +F: tests/qtest/arm-cpu-features.c F: hw/arm/ F: hw/cpu/a*mpcore.c F: include/hw/cpu/a*mpcore.h --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622822096; cv=none; d=zohomail.com; s=zohoarc; b=m1H6exbBAxcHjCMxcxzx72MfTxtlxaCS8g3MPROTefJUfi0suhnU3aRD32nQvEuesUWrCVLHm9kKlQ7sHYcc6tjrb58fHrU3+sG0SBLe7A2uGLAFT8swSXAelJpymhqsX4jkLEUkmW1Bs0lPJ5n8LDv+huy2iZaZMOMvapB2uco= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622822096; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TfhBAPUGZRyh95qvT9iSddyRzYFalb2GCwwg+0epNlQ=; b=FUgrPIRlWhFj4aLBVjqT0nyXsXu2yp5D1ZcHizIhsBMcvGc0q0ej+r/4XgP9O0902GMf3UueULcYmo3ZO/fqL7LXW8WQIJTfEqmDjCmld3T569a0OTh6hs7yluHeRnlutRIRW4qIMvQSGc3ODL49VrlMxw39rP+jhcBekdkhGHY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622822096828397.45924397660815; Fri, 4 Jun 2021 08:54:56 -0700 (PDT) Received: from localhost ([::1]:47694 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpC9u-0005ML-E0 for importer@patchew.org; Fri, 04 Jun 2021 11:54:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44196) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8O-0002Gr-Qn for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:20 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:35604) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8L-0008MT-V1 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:20 -0400 Received: by mail-wr1-x433.google.com with SMTP id m18so9807468wrv.2 for ; Fri, 04 Jun 2021 08:53:16 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id j14sm9095407wmi.32.2021.06.04.08.53.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:13 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 8A38D1FF8C; Fri, 4 Jun 2021 16:53:12 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TfhBAPUGZRyh95qvT9iSddyRzYFalb2GCwwg+0epNlQ=; b=lU8Nth9hhzn7DJhdY23Rq5zeLxg6bFeMjTebVFM98emHAVMYG5wBh4B/tPHZfURLUc Mc8sdBji7u80x4idaa6qtx0RtRejaBMxZ+IcgUm3tbcQ8/K9GLy6fV0B2kS5lV1jWBCV Bl/Dn1bYPaN07T1yiMargDzLatmDd5/CDWyfc+q0DkUA4xyHqIaCMbW4etIEF5DwhdSm FaArvVntjXGrt9Z2m7+NWy+JBI9IbrcfOxtpEsYMkmHQpYsxwcDQ5u4i2ioip4+W/yW4 kXQSEqFeBCxqU1vHqQ1vwjvNXILCt7BARH/Ar1cRjeKrkrpPfMHxBPMGr1bsObqkyJpT IgkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TfhBAPUGZRyh95qvT9iSddyRzYFalb2GCwwg+0epNlQ=; b=IT555olwQknDaSAKqgQTySeeC6OV/JCHwfjQDYyZzDUx6mWFi2qzUqMEMMyaaEGNP6 wSpAUuPissZhcbNdjCrrUx60SczPY2yIPLQ5kg7NFmjAYdtbObi1inPRPjHPp8lSPzYh d9Cdp9IwW+oIeht/aNp6L37rf0jGixk64vnDDXr3Q707fJb4aD9liP79SVZ4CFfYGCzy BOaDHVj6mjU5IXqkW6OliVzPRU9AG2hlvAGd0WuJW22BZqTxc8JkyGgrR27PemYk8vig rpo9sFJD1z2J1LACFn20FZmqTnineHI+bp7C/qfu89aY1dQGjezQnO4VBkye7HC1Vi59 Ll8w== X-Gm-Message-State: AOAM532b3ZqSpBJ/EdGfI1LpXgoFNq1EkgARXKeRNszlxXOffSQDq78Q BjxW6ut/iRhTlUuNmgTQy0f3dw== X-Google-Smtp-Source: ABdhPJyHRPnAWWNvKo+0EbBMm0pnvrnQBDYvxOzmgCDuNBAJQE+cyyHKifit58nxyqynvPi9AkBOAw== X-Received: by 2002:a5d:6e92:: with SMTP id k18mr4692302wrz.94.1622821995428; Fri, 04 Jun 2021 08:53:15 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 02/99] accel: Introduce 'query-accels' QMP command Date: Fri, 4 Jun 2021 16:51:35 +0100 Message-Id: <20210604155312.15902-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Richard Henderson , Markus Armbruster , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Introduce the 'query-accels' QMP command which returns a list of built-in accelerator names. - Accelerator is a QAPI enum of all existing accelerators, - AcceleratorInfo is a QAPI structure providing accelerator specific information. Currently the common structure base provides the name of the accelerator, while the specific part is empty, but each accelerator can expand it. - 'query-accels' QMP command returns a list of @AcceleratorInfo For example on a KVM-only build we get: { "execute": "query-accels" } { "return": [ { "name": "qtest" }, { "name": "kvm" } ] } Note that we can't make the enum values or union branches conditional because of target-specific poisoning of accelerator definitions. Reviewed-by: Eric Blake Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Alex Benn=C3=A9e Message-Id: <20210505125806.1263441-3-philmd@redhat.com> Reviewed-by: Thomas Huth --- qapi/machine.json | 47 +++++++++++++++++++++++++++++++++++++++++++++ accel/accel-qmp.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++ accel/meson.build | 2 +- 3 files changed, 97 insertions(+), 1 deletion(-) create mode 100644 accel/accel-qmp.c diff --git a/qapi/machine.json b/qapi/machine.json index 58a9c86b36..79a0891793 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -1274,3 +1274,50 @@ ## { 'event': 'MEM_UNPLUG_ERROR', 'data': { 'device': 'str', 'msg': 'str' } } + +## +# @Accelerator: +# +# An enumeration of accelerator names. +# +# Since: 6.1 +## +{ 'enum': 'Accelerator', + 'data': [ 'hax', 'hvf', 'kvm', 'qtest', 'tcg', 'whpx', 'xen' ] } + +## +# @AcceleratorInfo: +# +# Accelerator information. +# +# @name: The accelerator name. +# +# Since: 6.1 +## +{ 'struct': 'AcceleratorInfo', + 'data': { 'name': 'Accelerator' } } + +## +# @query-accels: +# +# Get a list of AcceleratorInfo for all built-in accelerators. +# +# Returns: a list of @AcceleratorInfo describing each accelerator. +# +# Since: 6.1 +# +# Example: +# +# -> { "execute": "query-accels" } +# <- { "return": [ +# { +# "name": "qtest" +# }, +# { +# "name": "kvm" +# } +# ] } +# +## +{ 'command': 'query-accels', + 'returns': ['AcceleratorInfo'] } diff --git a/accel/accel-qmp.c b/accel/accel-qmp.c new file mode 100644 index 0000000000..426737b3f9 --- /dev/null +++ b/accel/accel-qmp.c @@ -0,0 +1,49 @@ +/* + * QEMU accelerators, QMP commands + * + * Copyright (c) 2021 Red Hat Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/qapi-commands-machine.h" + +static const bool accel_builtin_list[ACCELERATOR__MAX] =3D { + [ACCELERATOR_QTEST] =3D true, +#ifdef CONFIG_TCG + [ACCELERATOR_TCG] =3D true, +#endif +#ifdef CONFIG_KVM + [ACCELERATOR_KVM] =3D true, +#endif +#ifdef CONFIG_HAX + [ACCELERATOR_HAX] =3D true, +#endif +#ifdef CONFIG_HVF + [ACCELERATOR_HVF] =3D true, +#endif +#ifdef CONFIG_WHPX + [ACCELERATOR_WHPX] =3D true, +#endif +#ifdef CONFIG_XEN_BACKEND + [ACCELERATOR_XEN] =3D true, +#endif +}; + +AcceleratorInfoList *qmp_query_accels(Error **errp) +{ + AcceleratorInfoList *list =3D NULL, **tail =3D &list; + + for (Accelerator accel =3D 0; accel < ACCELERATOR__MAX; accel++) { + if (accel_builtin_list[accel]) { + AcceleratorInfo *info =3D g_new0(AcceleratorInfo, 1); + + info->name =3D accel; + + QAPI_LIST_APPEND(tail, info); + } + } + + return list; +} diff --git a/accel/meson.build b/accel/meson.build index b44ba30c86..7a48f6d568 100644 --- a/accel/meson.build +++ b/accel/meson.build @@ -1,4 +1,4 @@ -specific_ss.add(files('accel-common.c')) +specific_ss.add(files('accel-common.c', 'accel-qmp.c')) softmmu_ss.add(files('accel-softmmu.c')) user_ss.add(files('accel-user.c')) =20 --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622822110; cv=none; d=zohomail.com; s=zohoarc; b=L5n0O5vzBT0NFI00GCk9/f0Itw9DOt5NLQ9Yw5SrX/ieB98riP+J3yL7gHoO2Rk4xwQebUwbv+XIohX8vUV8KYQQZCLA4rY/Er7sebVllpJi5BUMyhs5NBBvSA+FeMtbBm9Iu0LcyqF7O0pbTJts1mxTx2PvAFRQWh+NgCelnvI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622822110; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TvyIlJW3PO7q09G/gvxhFxBVndq7M4s8XzLxW3dgEK0=; b=WhmPjaL29usv86nSbcMv+kGaKr8WbKCG90K3dr6fWdguT1oe2IHCI/dYo0O7/vFEbbTYm4jivLNdr2zO70RHumCzLHdHYOnGNmPSZlCYLNhXj32aPrffdUyRl1B57Pi28K0QQH0fFBC+H5ZjnM4Yo+olLkXVjawtpVc1c2dhARc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622822110930717.294481026983; Fri, 4 Jun 2021 08:55:10 -0700 (PDT) Received: from localhost ([::1]:49154 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCA9-0006Ja-Ue for importer@patchew.org; Fri, 04 Jun 2021 11:55:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44266) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8R-0002Kw-14 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:23 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:35599) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8N-0008O5-5g for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:22 -0400 Received: by mail-wr1-x42d.google.com with SMTP id m18so9807582wrv.2 for ; Fri, 04 Jun 2021 08:53:18 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id m37sm482577wms.46.2021.06.04.08.53.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:14 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A239D1FF8F; Fri, 4 Jun 2021 16:53:12 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TvyIlJW3PO7q09G/gvxhFxBVndq7M4s8XzLxW3dgEK0=; b=WYwIOaaIjE19ZhMLtM5SnbB16XfCcI1pHVrnlhT2fH6VApU3pTTbmhEv5Hnt+Vl/wL fifSxS9u1dpXVPAVzXQUsjsZ3DODWwGmkJU0/fT0FoaeHOKuU8bmnCrNW9JHAkGzcRRI qkZgVB9Zlatrkfp1mmUsZC6w9IlWpcaz3+O/LaIXgWysj3Ub75+wpYnDGp2uys3y8B/X gZwoKtc/1J8VyVn0/qKPiUTJmIHGxkyfbDC/iAkYz6oBlYWvJ7X/C2dTf/fAJfumqTdf /AuzUO9YYnSBiCZJFB0SlEepfQLRZ93IOULZngHbt9ignJTL+83PPV3GKYZz00opX1/6 ZxFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TvyIlJW3PO7q09G/gvxhFxBVndq7M4s8XzLxW3dgEK0=; b=CPFxquhAGFr4F/gqkimBxX8KYjx9cAYiitd5aXwOpEd+s43B8EULGTaFe3qR8omF8M Z8GOdatQBQPYmboWku/sh07q5ucGiyMGyXOzz/dyFyhG1qfDxRkRTD+pA+ApAwzsJ3Pi RyEPviVK0HeNeiZlxw51vEb0RUXm8RRpImA0w5eBqY27JmzV9xz09NeLG7Ei2P/tm3qz kCBzMi4D6gMz72n+FNlinTZsEZp5G+9bsUiqwVBgEDnDc9MQ7bzPctgz0OV406NPKt1A +RR3yggwGJ2BNWEOmFiy+KRAt1AFUGRQCXXTlh2GNZ7DtO9kRpDjHmbgRVemtdejOOH6 aC2w== X-Gm-Message-State: AOAM5334f+U7E4zJhxFLRMasQ3qOwVdl+vImEEKNWAlICcEbeWwZNOHf ZLIYfzRV6qFfwT7mESJR/O3QQA== X-Google-Smtp-Source: ABdhPJwLkU+psoJMTHeG9YajGsIX8seZ7zn7gLKg5Ih4dUVq0yaBKpbD/BShRRbSD2gFVJp5bmwh2Q== X-Received: by 2002:a5d:6b0b:: with SMTP id v11mr4489637wrw.339.1622821997592; Fri, 04 Jun 2021 08:53:17 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 03/99] qtest: Add qtest_has_accel() method Date: Fri, 4 Jun 2021 16:51:36 +0100 Message-Id: <20210604155312.15902-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Introduce the qtest_has_accel() method which allows a runtime query on whether a QEMU instance has an accelerator built-in. Reviewed-by: Eric Blake Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Alex Benn=C3=A9e Message-Id: <20210505125806.1263441-4-philmd@redhat.com> --- tests/qtest/libqos/libqtest.h | 8 ++++++++ tests/qtest/libqtest.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/tests/qtest/libqos/libqtest.h b/tests/qtest/libqos/libqtest.h index a68dcd79d4..d80c618c18 100644 --- a/tests/qtest/libqos/libqtest.h +++ b/tests/qtest/libqos/libqtest.h @@ -763,6 +763,14 @@ void qmp_expect_error_and_unref(QDict *rsp, const char= *class); */ bool qtest_probe_child(QTestState *s); =20 +/** + * qtest_has_accel: + * @accel_name: Accelerator name to check for. + * + * Returns: true if the accelerator is built in. + */ +bool qtest_has_accel(const char *accel_name); + /** * qtest_set_expected_status: * @s: QTestState instance to operate on. diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c index 825b13a44c..6bda6e1f33 100644 --- a/tests/qtest/libqtest.c +++ b/tests/qtest/libqtest.c @@ -393,6 +393,35 @@ QTestState *qtest_init_with_serial(const char *extra_a= rgs, int *sock_fd) return qts; } =20 +bool qtest_has_accel(const char *accel_name) +{ + bool has_accel =3D false; + QDict *response; + QList *accels; + QListEntry *accel; + QTestState *qts; + + qts =3D qtest_initf("-accel qtest -machine none"); + response =3D qtest_qmp(qts, "{'execute': 'query-accels'}"); + accels =3D qdict_get_qlist(response, "return"); + + QLIST_FOREACH_ENTRY(accels, accel) { + QDict *accel_dict =3D qobject_to(QDict, qlist_entry_obj(accel)); + const char *name =3D qdict_get_str(accel_dict, "name"); + + if (g_str_equal(name, accel_name)) { + has_accel =3D true; + break; + } + } + qobject_unref(response); + + qtest_quit(qts); + + return has_accel; +} + + void qtest_quit(QTestState *s) { qtest_remove_abrt_handler(s); --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622822238; cv=none; d=zohomail.com; s=zohoarc; b=F1rn16Kss1G7Mt5kaMKhyUFVqBGc75fAR64oVRgatDnC6xPVEQ1AnQNVxMxjn3/PlU6/4IS+r3be5DAE6ixL2wcEdnmL3kv6qBgFQXK0SLstfW0bLxBSiCb8Y/ODrym5Q3GU9PZ3HJjmtqqKM4DgjVGLkVHcgHwLxNq1zl8pzt0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622822238; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JEWHBCHxKVXeNs+cV9ChbBOU9uNopKc+RwL1IoJNYZE=; b=iywGOiRN5faBlf/BrLDIaaBS8klkPD0FBD4QgkI756e+TLu7Ry/Ehe5UMGagfaThJLpV87yCD1WgqraPjES5D6bgpIYauZX/UzdC3isVMr06UE9UflVqMLr7TdSyvojh3/wXAz1DA8FEQ7jqZHBoPROsAl65b5fjznYlfW36x4c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162282223870244.949672164320305; Fri, 4 Jun 2021 08:57:18 -0700 (PDT) Received: from localhost ([::1]:57854 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCCD-0003ui-HK for importer@patchew.org; Fri, 04 Jun 2021 11:57:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44288) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8R-0002M0-HP for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:23 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:35413) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8O-0008Pd-Th for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:23 -0400 Received: by mail-wm1-x334.google.com with SMTP id h5-20020a05600c3505b029019f0654f6f1so7677046wmq.0 for ; Fri, 04 Jun 2021 08:53:20 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id m3sm7492783wrr.32.2021.06.04.08.53.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:17 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id B86BB1FF90; Fri, 4 Jun 2021 16:53:12 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JEWHBCHxKVXeNs+cV9ChbBOU9uNopKc+RwL1IoJNYZE=; b=wtMqn6thCPNnLdYttCGfqmQqMOEg+ctSBuIECrpWX+oK1LZvqOXn8sUv0eNJFaXt/d ZQujLTQrJ9MwHgvc6688BQSlphHC6nL/xfC1CE78GOLOu+6P3jmTYiJOCtE5dsdXpnXu AZW193ADBcVFdKlvwt9SxsPa6DdDebwvuXALb5iCg5fBww2tCfvSyN2VgMENVbIF8b66 GE+83yxVlxSDu2hewbTaHpZAGs00qbMGUIXIS/a44he4BG7vRbEuqq3MqszCbkEBzQBN lU/qF24r0UAgDvZkVUKByxu/QP7Z/eDU1YlNLnzkVdz07nBZE0KcQbSChkwrZQr3/T05 U7dQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JEWHBCHxKVXeNs+cV9ChbBOU9uNopKc+RwL1IoJNYZE=; b=cnlaJcXeRUyMh9drf9V5jyOEKKPyJLx76/CJ2Ay+k5V3HkOfcMybYvd5wrUWnzZfs1 8Sv2MCZ8xo8bhyZYO/uGaUOJNZOucnKR5PjyGxhfvbhOQomE8x4OQEu31NbgxUX5tEc5 DM2lU7oGPbh89zLgDCkLefG1ok19XNtJWCp8/HsHYB+njD1ebXl/wSGVNKDQ6XdScw6b +Ua0r50NiIyDL1do92gaynclMQEovtsH/2i4SgnPGD/QoW5+5FQtGvvW/zSl9ug48rpY S1lF7RcUu5SLOdI32+mL3vKydrpRBGzW2JRTWftmGQJNBQI4aZXWpl7xC/MaKRLMgtFW 3ovA== X-Gm-Message-State: AOAM532BDd61KMFJ7kWOafHObK/Dbsf4w3jAj5egG/7vUd5bMu9uM8vT W3w02icICBTNKXTnKXkiQEak2g== X-Google-Smtp-Source: ABdhPJwkgxI+WQ7cpos6cOO4lrQwqRWxP6qv6I3lso4hCIvy4fBoVLex/yO9XGF0vpkojQ8D6WGXmg== X-Received: by 2002:a1c:5f86:: with SMTP id t128mr4403114wmb.165.1622821999429; Fri, 04 Jun 2021 08:53:19 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 04/99] qtest/arm-cpu-features: Use generic qtest_has_accel() to check for KVM Date: Fri, 4 Jun 2021 16:51:37 +0100 Message-Id: <20210604155312.15902-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Andrew Jones , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , qemu-arm@nongnu.org, Claudio Fontana , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Use the recently added generic qtest_has_accel() method to check if KVM is available. Suggested-by: Claudio Fontana Reviewed-by: Andrew Jones Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Alex Benn=C3=A9e Message-Id: <20210505125806.1263441-5-philmd@redhat.com> Reviewed-by: Richard Henderson --- tests/qtest/arm-cpu-features.c | 25 +------------------------ 1 file changed, 1 insertion(+), 24 deletions(-) diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index 8252b85bb8..7f4b252127 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -26,21 +26,6 @@ " 'arguments': { 'type': 'full', " #define QUERY_TAIL "}}" =20 -static bool kvm_enabled(QTestState *qts) -{ - QDict *resp, *qdict; - bool enabled; - - resp =3D qtest_qmp(qts, "{ 'execute': 'query-kvm' }"); - g_assert(qdict_haskey(resp, "return")); - qdict =3D qdict_get_qdict(resp, "return"); - g_assert(qdict_haskey(qdict, "enabled")); - enabled =3D qdict_get_bool(qdict, "enabled"); - qobject_unref(resp); - - return enabled; -} - static QDict *do_query_no_props(QTestState *qts, const char *cpu_type) { return qtest_qmp(qts, QUERY_HEAD "'model': { 'name': %s }" @@ -493,14 +478,6 @@ static void test_query_cpu_model_expansion_kvm(const v= oid *data) =20 qts =3D qtest_init(MACHINE_KVM "-cpu max"); =20 - /* - * These tests target the 'host' CPU type, so KVM must be enabled. - */ - if (!kvm_enabled(qts)) { - qtest_quit(qts); - return; - } - /* Enabling and disabling kvm-no-adjvtime should always work. */ assert_has_feature_disabled(qts, "host", "kvm-no-adjvtime"); assert_set_feature(qts, "host", "kvm-no-adjvtime", true); @@ -624,7 +601,7 @@ int main(int argc, char **argv) * order avoid attempting to run an AArch32 QEMU with KVM on * AArch64 hosts. That won't work and isn't easy to detect. */ - if (g_str_equal(qtest_get_arch(), "aarch64")) { + if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")= ) { qtest_add_data_func("/arm/kvm/query-cpu-model-expansion", NULL, test_query_cpu_model_expansion_kvm); } --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622822797; cv=none; d=zohomail.com; s=zohoarc; b=MTnQaK7ZZmKAmHFC0mITI85md4Z21p9QuVa+CK76folbzO64h7PV5tBtNe4f87LMOSi2tSm+voE3FJYJ2oEbd0iSxv7hXsd5qd9u0YGMcAxocVgbBTlaT8VxDhJelbGTUQIOkxg5tnnpwNChIxzp0CYnoPwidrjGUmyxGuKzKBM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622822797; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=67nZUzxSZk/gVJPBhG39pqDikF99Pp1OEKbjWVU7ILs=; b=Xm1/HHZt45t9Gi2OzxL8bib5ieTyyK9uxq6FshiY51o69rFhZr9WtBBtRYcOK+x6A5DxHranitK/cXxqdeD0f+V6M3UR166zxbH8+PF9nazLfdLGZj7lr2qMxR+vHP0SgECBhQQ/B1EuhhbTIs5yjImMWRp1CyQWzO6lQ8myvu0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622822797402265.2043894720432; Fri, 4 Jun 2021 09:06:37 -0700 (PDT) Received: from localhost ([::1]:56456 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCLD-0005eo-US for importer@patchew.org; Fri, 04 Jun 2021 12:06:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44382) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8U-0002Xd-Tk for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:26 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:34481) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8P-0008QC-Fe for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:26 -0400 Received: by mail-wm1-x32f.google.com with SMTP id u5-20020a7bc0450000b02901480e40338bso4495442wmc.1 for ; Fri, 04 Jun 2021 08:53:21 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id r2sm7160694wrv.39.2021.06.04.08.53.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:17 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id CDF2F1FF91; Fri, 4 Jun 2021 16:53:12 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=67nZUzxSZk/gVJPBhG39pqDikF99Pp1OEKbjWVU7ILs=; b=m3KM02stufm+OUqybEoRGCzWNyZvvNEe6dwY6eFwewV0WulgmwmgiwjcSiyILfgiI5 GK4vPvD2aMrXn0bbWhgitB2yCpeCFQU2PVP0wC/y21vxeV0k/1BVJG8bjh/84ooWmUJU CSLCMZnWlpDOEUysvdArApkjInVlqzC5DHk4GnElnHYdlmNEeLjp17InzU2VS3HEBywV +vxVQ3RjV67Q4YLLfNxjfWoi0jwPdM3OZY8JqqB8+9ftFJlQrSPjJ9tjqGZBxgNIz1pi GOWZr65ReY3bZLzGB/yzXL6D7OdfnqYX4jUJ61//KvKHU6Ohs3AQ4Ti2EidVUVyE/y6Z C2Pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=67nZUzxSZk/gVJPBhG39pqDikF99Pp1OEKbjWVU7ILs=; b=E72mWJUzLUGFTy3yQP/VxkBixEbPQ2+cdj5W7n2KCyXwWWxxC3xLX2TAK4CSMHvppb m8w7x/ZsR11YP8NycIlhGe+yqZBpOHCAkcx3aEV5dpcsxnrxSYkPOEyXb63MNROoo2qV EJ7ZvY5pSXvpSRlb78/VP6KFJ0g7PG+x5J2BenA8oJ9T+qzwVIQmIen6R9UFHP/qodw0 wQfcMHISfu3fEGUdTzgl/FAE1VKHguS4RpNEIPe+2jrQq4bF/MoYXeEaY0vKFEZvPEWe 6EwuJrIFbGWYRF0ZOpwcyY2sJdf6Gx0OixCtd8KGFwRo7ez6SgvHNu/9s0wYEQ0mMsPM 1U7A== X-Gm-Message-State: AOAM530HjyMym/QmCpgE/0ELu9wQ191wI8KDByZSlWix6/BU6zpSaSbC +qFJ75hkbAxi6t25hfGdy6DBZQ== X-Google-Smtp-Source: ABdhPJzQ+O++4W4taow2egRD3zdcU5N2ZKTUQGyvJeEecw5ufZw/zEjDyV88VFEv4UJ8cUtBKyAVlQ== X-Received: by 2002:a05:600c:3658:: with SMTP id y24mr4406058wmq.122.1622822000148; Fri, 04 Jun 2021 08:53:20 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 05/99] qtest/arm-cpu-features: Restrict sve_tests_sve_off_kvm test to KVM Date: Fri, 4 Jun 2021 16:51:38 +0100 Message-Id: <20210604155312.15902-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Andrew Jones , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 The sve_tests_sve_off_kvm() test is KVM specific. Only run it if KVM is available. Suggested-by: Andrew Jones Reviewed-by: Andrew Jones Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Alex Benn=C3=A9e Message-Id: <20210505125806.1263441-6-philmd@redhat.com> Reviewed-by: Richard Henderson --- tests/qtest/arm-cpu-features.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index 7f4b252127..66300c3bc2 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -604,6 +604,8 @@ int main(int argc, char **argv) if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("kvm")= ) { qtest_add_data_func("/arm/kvm/query-cpu-model-expansion", NULL, test_query_cpu_model_expansion_kvm); + qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off", + NULL, sve_tests_sve_off_kvm); } =20 if (g_str_equal(qtest_get_arch(), "aarch64")) { @@ -611,8 +613,6 @@ int main(int argc, char **argv) NULL, sve_tests_sve_max_vq_8); qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off", NULL, sve_tests_sve_off); - qtest_add_data_func("/arm/kvm/query-cpu-model-expansion/sve-off", - NULL, sve_tests_sve_off_kvm); } =20 return g_test_run(); --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622822160; cv=none; d=zohomail.com; s=zohoarc; b=Z2P7n0Q1zy9R9jCn95hfwRShypHSssl5UKNFqObVyMk6jjwmq91SADI85MXNUFsgoeuhjur24QUr4aNZ02sHCFxD8aP+S6P8cy5/UaG+qd2yVtxDve1zSSWbQlWufzRZ5aA/guyKfvcR9v3BQGGxjjgJ2+oxbiEVv/D2Jx7EgrM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622822160; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HPoMc3YlkQAs9v+mSgnPrpvdiBylh/hj1ZQf5qMDtII=; b=XJ7bGF204F3p+YOM3kCf5JBUqmFWLFCFYQ8/LPBGDuo4VVP1GcykLUN57GmHq0wATHZW4ogWwC3ET67VKP3Y3yxHjL5iAwzaBraF+cIGyp2YecIcMfgqIa8QX37bHTXbWOh/v5NdsVMbIl4VTX1lwRmM8aivh5JHiRhKML4l0xw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162282216073553.55941189564726; Fri, 4 Jun 2021 08:56:00 -0700 (PDT) Received: from localhost ([::1]:52334 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCAx-0008RN-K0 for importer@patchew.org; Fri, 04 Jun 2021 11:55:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44450) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8X-0002jW-Ph for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:29 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:33369) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8U-0008U6-2K for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:29 -0400 Received: by mail-wm1-x331.google.com with SMTP id s70-20020a1ca9490000b02901a589651424so1270454wme.0 for ; Fri, 04 Jun 2021 08:53:25 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id h14sm8563060wmb.1.2021.06.04.08.53.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:17 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id E3F6E1FF92; Fri, 4 Jun 2021 16:53:12 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HPoMc3YlkQAs9v+mSgnPrpvdiBylh/hj1ZQf5qMDtII=; b=NMhDWPfeWN5J/SlWK4FDgmYPV/9S5pRV9gLmvw8KG8Rj/VlzPof07KH9eW1jLslei/ rbHdVH+Ulv7cCfMameePbEkdIsEkW1Uv3f4jp6PmFwJJL2V3jCfrd4QecRd2nrLXFOdz dHiKkvfTAvE4J20DM3S5jUVTaCHI/J/4qnudAYpHScoYPzZbf0jCmh3/ORLa6Sb9m/Fv 2+rJE3ZaqGb0gT/wbUMkGT07i3lIR4MWzSDckRk2Xx1Yv0UIZ5jXQ5fUOlYl7UXYQ9/3 0y1mgO9wnMyw70fph+ri00ZSEGumr+ncGttCw6R/eLnfIWbzz0hnn3aoasMQjPWMSRHk xJwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HPoMc3YlkQAs9v+mSgnPrpvdiBylh/hj1ZQf5qMDtII=; b=gxurZErTpF4EzawYtVUT7QG56nYJOxBkIUPlEXHo64zVaEQPToMbhUoVXuVGHgCrDo fp5uF8PYB8wUu0+FDQHsd7G8SxxjrJgfWbVVs50SNObwsr6KTYt5cBNXssQF//A8UCiq 9m+ENshsM+/J2JgNMMtkoxP8an6+5c8S+FMXD1/zWL81/8CMcC/c7tQH9tBAf4IT5njx dBZiLce5MH3fL9s6SNJfUY/HQXSuIY3okOnoAXa66FSDWjTFakOFfW4gchGncx3B2z3Z C4YuUJZK+MyR6jBvVOQjE3djhUGSfWq5rMk/g1CJb31NvoN88dNIQgDB+f8+Lf9NTb/N 9MJg== X-Gm-Message-State: AOAM532cQfolmfvUqqKKtErFpNAj9zWJE1LNK5US0o6TyaKhoUZB4WOm /JP8aDalnK0yUNlsp95VxEMTLA== X-Google-Smtp-Source: ABdhPJyj00zuxJ9n1GfQWuRX+EFsgbDtB2/YnhlJWS4NYvLi0EQ++mu7xXI8VuLqonLMTME3+vBXBw== X-Received: by 2002:a1c:6209:: with SMTP id w9mr4290273wmb.27.1622822004458; Fri, 04 Jun 2021 08:53:24 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 06/99] qtest/arm-cpu-features: Remove TCG fallback to KVM specific tests Date: Fri, 4 Jun 2021 16:51:39 +0100 Message-Id: <20210604155312.15902-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Andrew Jones , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 sve_tests_sve_off_kvm() and test_query_cpu_model_expansion_kvm() tests are now only being run if KVM is available. Drop the TCG fallback. Suggested-by: Andrew Jones Reviewed-by: Andrew Jones Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Alex Benn=C3=A9e Message-Id: <20210505125806.1263441-7-philmd@redhat.com> Reviewed-by: Richard Henderson --- tests/qtest/arm-cpu-features.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index 66300c3bc2..b1d406542f 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -21,7 +21,7 @@ #define SVE_MAX_VQ 16 =20 #define MACHINE "-machine virt,gic-version=3Dmax -accel tcg " -#define MACHINE_KVM "-machine virt,gic-version=3Dmax -accel kvm -accel tcg= " +#define MACHINE_KVM "-machine virt,gic-version=3Dmax -accel kvm " #define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \ " 'arguments': { 'type': 'full', " #define QUERY_TAIL "}}" --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622822388; cv=none; d=zohomail.com; s=zohoarc; b=UgdrDyDS2PXcpVDsZzn7klxYlTg1X2YcIzx/89oMjDzkBj/0qESkAR4SfprvBbzBT2/ysTNnLVqLMSgy74Mec+5mPrgeUC2Lfm6p/5fmTTBkrtjet2zZFCQ+9CKQ6w6zt64+z4FFPCPS+7/uz9VGCPOf6Y/EVe/I7lMzd0QcmHk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622822388; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WOuysOnef2mMKklKTFeIYkHV2AEtzMpA+XWnC2+7giM=; b=KZTpKDr97j/cnMciw2ULoMcQc81xDkYCCbJLclFY6/iCebO0jMuT0/s0Bf9Sgw6f0kB2us29VPBTwi3JKlARmZoZs9DlxvzF/urMtUWV2bDecjq4kvrn+hfmOCPYglkMGQR/1Rqa+qx6ySAWoobGICMT6ajIczH7y9uHRDWLMwE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622822388415980.5826778898582; Fri, 4 Jun 2021 08:59:48 -0700 (PDT) Received: from localhost ([::1]:38050 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCEd-00017Y-Ae for importer@patchew.org; Fri, 04 Jun 2021 11:59:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44418) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8W-0002dc-EI for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:28 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:38835) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8S-0008SH-He for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:28 -0400 Received: by mail-wr1-x432.google.com with SMTP id c9so1114018wrt.5 for ; Fri, 04 Jun 2021 08:53:23 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id h9sm1793301wmm.33.2021.06.04.08.53.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:17 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 05F101FF93; Fri, 4 Jun 2021 16:53:13 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WOuysOnef2mMKklKTFeIYkHV2AEtzMpA+XWnC2+7giM=; b=lf4rpAtdDhOuo89nFjvu+c5ZRPeDbZIxLSiUlimSH2V32i6d08AWPx6bdZ00+CBKxV p4Nr1NEF1OSrlDSwFWItTQHgmoh9Hpw5fHeiTV5sjLu/hbL3cFCmgZVoelB8JvBv8F9S LoJwhA+6s7djrxFZ+xbL7Qs2wBw7Zqf48rh16OzH9lrcC4uSOaDYPw5K0blRpS3htudg 6+wTPB6i5NisBGF4xd67zWWRkWAHOZmn4uxIR78F4F2GBY5LaIw5hDedTN0uiHeoCAl0 GKyoDemr3Q8R1KJWSNN6N2uutckvOyxxDC2OnJ7MKpoKGHDGd5WpNpteii8V0GE2Vztq AsVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WOuysOnef2mMKklKTFeIYkHV2AEtzMpA+XWnC2+7giM=; b=DMT4ZyIoNPyZoX4EnlDRTx+wdfYHxm292riAM5q+4sgNk6FOp8aiGIICB+aQOSfT2E VkhdklO6n2VjZ+++4GenwdiqrsuI+PcKVxOwu618TjJDxa1o9eZMg9LTmILpNBzVduzH c1IRIJhq2YR8YyQI689o77UuZSKQ1IZVXGLI2jjaqS5yxUS2fpHE3qsIWhdN3E4bjiSz lD+CJCrfj5SAgu7zzml4Xddqdrd2HRtYzTH4T4o3tt9yYOBxW85ySyUhyST6XLho7qh5 QgBuplp60sOwK9nMyfLN+6NYR/4I1MhbvfxKCyjN/EBh5EMyzGL+9C2mOszogRb7oEex gIJA== X-Gm-Message-State: AOAM531byPFsc+oPTNS4mmySORWEIQBiBhi2Oppiohp3/D5AyMbPA4R+ baV1u247TxjwKQuCHnUB/GwQ0g== X-Google-Smtp-Source: ABdhPJy/+4acn7KxICuk9nrmjOuSBxj8wqrTrQlG/EMtj/MWkxBw6rG8kqFQdYuVJkegY6762RR1Sw== X-Received: by 2002:a5d:6109:: with SMTP id v9mr4712052wrt.0.1622822002504; Fri, 04 Jun 2021 08:53:22 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 07/99] qtest/arm-cpu-features: Use generic qtest_has_accel() to check for TCG Date: Fri, 4 Jun 2021 16:51:40 +0100 Message-Id: <20210604155312.15902-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Peter Maydell , Andrew Jones , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Thomas Huth , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Now than we can probe if the TCG accelerator is available at runtime with a QMP command, only run these tests if TCG is built into the QEMU binary. Suggested-by: Andrew Jones Reviewed-by: Andrew Jones Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Alex Benn=C3=A9e Message-Id: <20210505125806.1263441-8-philmd@redhat.com> Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth --- tests/qtest/arm-cpu-features.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c index b1d406542f..0d9145dd16 100644 --- a/tests/qtest/arm-cpu-features.c +++ b/tests/qtest/arm-cpu-features.c @@ -20,7 +20,7 @@ */ #define SVE_MAX_VQ 16 =20 -#define MACHINE "-machine virt,gic-version=3Dmax -accel tcg " +#define MACHINE_TCG "-machine virt,gic-version=3Dmax -accel tcg " #define MACHINE_KVM "-machine virt,gic-version=3Dmax -accel kvm " #define QUERY_HEAD "{ 'execute': 'query-cpu-model-expansion', " \ " 'arguments': { 'type': 'full', " @@ -337,7 +337,7 @@ static void sve_tests_sve_max_vq_8(const void *data) { QTestState *qts; =20 - qts =3D qtest_init(MACHINE "-cpu max,sve-max-vq=3D8"); + qts =3D qtest_init(MACHINE_TCG "-cpu max,sve-max-vq=3D8"); =20 assert_sve_vls(qts, "max", BIT_ULL(8) - 1, NULL); =20 @@ -372,7 +372,7 @@ static void sve_tests_sve_off(const void *data) { QTestState *qts; =20 - qts =3D qtest_init(MACHINE "-cpu max,sve=3Doff"); + qts =3D qtest_init(MACHINE_TCG "-cpu max,sve=3Doff"); =20 /* SVE is off, so the map should be empty. */ assert_sve_vls(qts, "max", 0, NULL); @@ -428,7 +428,7 @@ static void test_query_cpu_model_expansion(const void *= data) { QTestState *qts; =20 - qts =3D qtest_init(MACHINE "-cpu max"); + qts =3D qtest_init(MACHINE_TCG "-cpu max"); =20 /* Test common query-cpu-model-expansion input validation */ assert_type_full(qts); @@ -593,8 +593,10 @@ int main(int argc, char **argv) { g_test_init(&argc, &argv, NULL); =20 - qtest_add_data_func("/arm/query-cpu-model-expansion", - NULL, test_query_cpu_model_expansion); + if (qtest_has_accel("tcg")) { + qtest_add_data_func("/arm/query-cpu-model-expansion", + NULL, test_query_cpu_model_expansion); + } =20 /* * For now we only run KVM specific tests with AArch64 QEMU in @@ -608,7 +610,7 @@ int main(int argc, char **argv) NULL, sve_tests_sve_off_kvm); } =20 - if (g_str_equal(qtest_get_arch(), "aarch64")) { + if (g_str_equal(qtest_get_arch(), "aarch64") && qtest_has_accel("tcg")= ) { qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-max-vq= -8", NULL, sve_tests_sve_max_vq_8); qtest_add_data_func("/arm/max/query-cpu-model-expansion/sve-off", --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622822633; cv=none; d=zohomail.com; s=zohoarc; b=K97hUvipatTmAzw705f8HEStdDinvVv1u/yW50/x9LJVPzlngjCX2p0DXMbbMArtqDDODJxmkVKSz53ad0iVuhxwP4ylXFVeuofCEuRTj4rN0loPVEohpoRL++a4yMOVEDoSvZ1MqN8CWlt+bgU5Vt42J+6QbyJpMBVPc3Ilcrg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622822633; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZW7hi0DfYBrqOjPk2iwpg84qtf2Zw2XIPeU/d/sNq6A=; b=BluGJXtSquCykeineWMtoSbrJRJYa9x+gQvcAEKIoQruYoNvtwi+uHMzX0icX29yznqYHWzOPxY+hsaz11wXyZ4mxJPX5RlsUokGrYJ1YmBCV4g7c/uiaxR4BOpVgYcuc0uvZ5346neza8GoXlMA9017TGf9ps4KVN1jCtQCT64= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622822633201206.21244369202122; Fri, 4 Jun 2021 09:03:53 -0700 (PDT) Received: from localhost ([::1]:47704 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCIZ-0007rZ-TZ for importer@patchew.org; Fri, 04 Jun 2021 12:03:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44356) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8T-0002TJ-Sr for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:25 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:37597) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8R-0008Rv-9p for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:25 -0400 Received: by mail-wr1-x431.google.com with SMTP id i94so4753997wri.4 for ; Fri, 04 Jun 2021 08:53:22 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id n8sm5892201wmi.16.2021.06.04.08.53.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:17 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 1C6171FF96; Fri, 4 Jun 2021 16:53:13 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZW7hi0DfYBrqOjPk2iwpg84qtf2Zw2XIPeU/d/sNq6A=; b=kMSlM8i+xPJ54AVpBAAaZTwcB0JEwBVVmLNzpVQl6rNdMmHeKcvvIH548K9xi/zJ5J Q+aPyx+yYPnKjAulG6recWcT52MwqoPVt3t/DC+M934wqBsNhIYiziyxcezyaVpdu6PY ZGJedqsC6Plzhh0CdFgUQi9QgM2HBkVrltwPEaNpgnVHvQmcN7uO6wzL5ATpEMeYwEQe ZZiSe4MAul5npTnLgwOTsGe67H5/P2rsyKVY36WncbAwXJQhMesMZ6hhPdvWEGKyw7dT jq3oxc27BsoUfg2GgX/pWg1gGNiJ9ysRsC7F9aX/nwzf+82RN9LrcKChyrRHQDh1+Mjh h79g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZW7hi0DfYBrqOjPk2iwpg84qtf2Zw2XIPeU/d/sNq6A=; b=HYFfBpEWPDlrlhZv6npwbSX8qBwrOkPEWEb2hfUG8QQ9d/XxjaZTsOmaKRdXHyj9Mc IToHqQmSrJxCBTztbsFquIIZkV7YY9E4D2vWNHwbvEEW9EWofH18ieZFkWh+2GP/gVTc MfGqsbJUQztS0yZDwybEh4wXrASivoa/FpXgSU7bj2u0EvFuo3dFM+O6RTZgEO2+ltQl MyEsvqTkzbekSmxAgUHubdrp1MhEBVz6QpBsFoGHA0pXbVXKyyCK2QuQACZ3+Z9Mk2tN D3uUJ7CDOktQx5NHbKVlBZo6uhwBW+JFvJkrOH+RoK8HsxQSIiy0z5qYoKEer91SePUI Rtqw== X-Gm-Message-State: AOAM533PVcIMpciTihHbYdlOg456RShD61VXFFEiQhYp0DfRlVAp6hl7 F2CbKvRDfrEKIpi5Dm9sCFCI1g== X-Google-Smtp-Source: ABdhPJzUwmIP0bZ6NAPFLERAQ3MUloYQ5So3v77Cf4Kn+0IDq73I1UUk+hu8PlwadEH42rLGnPGwHg== X-Received: by 2002:adf:dcc3:: with SMTP id x3mr4441419wrm.177.1622822001785; Fri, 04 Jun 2021 08:53:21 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 08/99] qtest/migration-test: Skip tests if KVM not builtin on s390x/ppc64 Date: Fri, 4 Jun 2021 16:51:41 +0100 Message-Id: <20210604155312.15902-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , Juan Quintela , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Cornelia Huck , Greg Kurz , "Dr. David Alan Gilbert" , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 We might have a s390x/ppc64 QEMU binary built without the KVM accelerator (configured with --disable-kvm). Checking for /dev/kvm accessibility isn't enough, also check for the accelerator in the binary. Reviewed-by: David Gibson Reviewed-by: Greg Kurz Reviewed-by: Cornelia Huck Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Alex Benn=C3=A9e Message-Id: <20210505125806.1263441-9-philmd@redhat.com> Reviewed-by: Thomas Huth --- tests/qtest/migration-test.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c index 2b028df687..102bc36b91 100644 --- a/tests/qtest/migration-test.c +++ b/tests/qtest/migration-test.c @@ -1387,7 +1387,7 @@ int main(int argc, char **argv) */ if (g_str_equal(qtest_get_arch(), "ppc64") && (access("/sys/module/kvm_hv", F_OK) || - access("/dev/kvm", R_OK | W_OK))) { + access("/dev/kvm", R_OK | W_OK) || !qtest_has_accel("kvm"))) { g_test_message("Skipping test: kvm_hv not available"); return g_test_run(); } @@ -1398,7 +1398,7 @@ int main(int argc, char **argv) */ if (g_str_equal(qtest_get_arch(), "s390x")) { #if defined(HOST_S390X) - if (access("/dev/kvm", R_OK | W_OK)) { + if (access("/dev/kvm", R_OK | W_OK) || !qtest_has_accel("kvm")) { g_test_message("Skipping test: kvm not available"); return g_test_run(); } --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622822319; cv=none; d=zohomail.com; s=zohoarc; b=Qiydt763htYP5z/6mSRUncHxzjeNbpSO9YXRWFqmOxRD0GszgEsDWakNfNx/GIyXkJH8INPc44KccqVuXwRxXieM5ZqX1mXaXhgAmW3HJfFKGe1TgtbblMmstZXvMfwMql5D1Ip5GR7Bqz48cpcC1bZ2/W+NiGngDaz6dxbQj4g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622822319; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JaXO37oL0Bjgy5CbV3aQwdfffelPx4CsfMkOQJk0Amo=; b=SukzXbxnsbqJ2vCvT8M7FeVQjQv4Ouoxjpl1bDK6rrz5rDn4U2zRLNkF+ywjKnMFTR2bPTTZJ/SdXC+ClxNtOaGYVk0eAJNa2C3yamkdP5okOsvOXdGCK7ktIyae3W7OnNBzWTw5TqP4mAl/8X3lUMSH+VtmgURjcVsMH+ow0lg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622822319670514.7459177770567; Fri, 4 Jun 2021 08:58:39 -0700 (PDT) Received: from localhost ([::1]:35358 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCDV-0007hj-N1 for importer@patchew.org; Fri, 04 Jun 2021 11:58:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44532) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8a-0002ra-7T for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:32 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:46850) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8W-000059-Rx for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:31 -0400 Received: by mail-wr1-x430.google.com with SMTP id a11so7916918wrt.13 for ; Fri, 04 Jun 2021 08:53:28 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id s1sm7478013wre.67.2021.06.04.08.53.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:24 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 337C71FF98; Fri, 4 Jun 2021 16:53:13 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JaXO37oL0Bjgy5CbV3aQwdfffelPx4CsfMkOQJk0Amo=; b=j4ekZwoUGqBxQbvgqsImdYhFqO9F2t+t9MeU/p4DulzCN29f/7iTIdZ6Dtk3+53YDQ UuNXOR/620M6TY/RT9YC9nA0DpE89f4m6gYrhWn9qOZ6laSLAgLrbhubRms0w6EtSksn yN0eFWo2Eu19sJq/9xA7Q7IX9j5NpmvNEVa6AHLHlUnU1Mo4OeOQ+E2OsYc690bHEcSo MOt62W3EWPURM3PvxcXIzUnr61C7hORKFLNe0OlkiL0Q9hMIwfDQFp/tK0oun7W6LnEU SehXadRlI0n8plmH8vsc9eLE8JrFJVYmL27sm2rl3a2gk8v8NRTYPByLPq7TyL8g+am1 88+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JaXO37oL0Bjgy5CbV3aQwdfffelPx4CsfMkOQJk0Amo=; b=QvRn5+YImo/T/JuZNQVPXiWje795aFu0z93Qi4WfSexJbUTxgrPwCKUDAsdn7C7ImU oetbB3uqf9N7FFoRSG2Bhaw4JyonE2JRA9yHjDsS3FYHnDFuS1m0W50pcaXleh0slN4X H14xjWHqpr4m1Y7TnbBS7vLyTnLjuQ0iiUfGjPe7k7OWaZMKSOq4xm/LNgJmjYgbu13x uHpHhc5NSMp24xCCbvdx0o6RuSgPgcSYm2I/68klZqLg13Tvg7RhG6UMpvAq9hh1UstD aqY8cjCs43ijZ0FCoYWtenW5Rd2Gil0F81xdqtDJ/SRuS32OhSojUTz9hT2fEL4I+LSV i9Jw== X-Gm-Message-State: AOAM532E16uDMPi/15R3GLfxvCB99JZmNZPVwUFGstb5vPcruN9o5LsB BiiN4AVWxljqhXvl0OWy2tYkkQ== X-Google-Smtp-Source: ABdhPJz3NIGDMQ09nL9ULOvAhC+N08rdZOk/+ZPlrQkXqPzOSa7LBpLaFOBcoRDVVz7PfS/QurNz/w== X-Received: by 2002:a5d:6e0d:: with SMTP id h13mr4720422wrz.118.1622822007261; Fri, 04 Jun 2021 08:53:27 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 09/99] qtest/bios-tables-test: Rename tests not TCG specific Date: Fri, 4 Jun 2021 16:51:42 +0100 Message-Id: <20210604155312.15902-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Igor Mammedov , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Various tests don't require TCG, but have '_tcg' in their name. As this is misleading, remove 'tcg' from their name. Reported-by: Igor Mammedov Reviewed-by: Igor Mammedov Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Alex Benn=C3=A9e Message-Id: <20210505125806.1263441-10-philmd@redhat.com> --- tests/qtest/bios-tables-test.c | 142 ++++++++++++++++----------------- 1 file changed, 71 insertions(+), 71 deletions(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 156d4174aa..ce498b3ff4 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -753,7 +753,7 @@ static uint8_t base_required_struct_types[] =3D { 0, 1, 3, 4, 16, 17, 19, 32, 127 }; =20 -static void test_acpi_piix4_tcg(void) +static void test_acpi_piix4(void) { test_data data; =20 @@ -768,7 +768,7 @@ static void test_acpi_piix4_tcg(void) free_test_data(&data); } =20 -static void test_acpi_piix4_tcg_bridge(void) +static void test_acpi_piix4_bridge(void) { test_data data; =20 @@ -824,7 +824,7 @@ static void test_acpi_piix4_no_acpi_pci_hotplug(void) free_test_data(&data); } =20 -static void test_acpi_q35_tcg(void) +static void test_acpi_q35(void) { test_data data; =20 @@ -841,7 +841,7 @@ static void test_acpi_q35_tcg(void) free_test_data(&data); } =20 -static void test_acpi_q35_tcg_bridge(void) +static void test_acpi_q35_bridge(void) { test_data data; =20 @@ -855,7 +855,7 @@ static void test_acpi_q35_tcg_bridge(void) free_test_data(&data); } =20 -static void test_acpi_q35_tcg_mmio64(void) +static void test_acpi_q35_mmio64(void) { test_data data =3D { .machine =3D MACHINE_Q35, @@ -872,7 +872,7 @@ static void test_acpi_q35_tcg_mmio64(void) free_test_data(&data); } =20 -static void test_acpi_piix4_tcg_cphp(void) +static void test_acpi_piix4_cphp(void) { test_data data; =20 @@ -888,7 +888,7 @@ static void test_acpi_piix4_tcg_cphp(void) free_test_data(&data); } =20 -static void test_acpi_q35_tcg_cphp(void) +static void test_acpi_q35_cphp(void) { test_data data; =20 @@ -908,7 +908,7 @@ static uint8_t ipmi_required_struct_types[] =3D { 0, 1, 3, 4, 16, 17, 19, 32, 38, 127 }; =20 -static void test_acpi_q35_tcg_ipmi(void) +static void test_acpi_q35_ipmi(void) { test_data data; =20 @@ -923,7 +923,7 @@ static void test_acpi_q35_tcg_ipmi(void) free_test_data(&data); } =20 -static void test_acpi_piix4_tcg_ipmi(void) +static void test_acpi_piix4_ipmi(void) { test_data data; =20 @@ -941,7 +941,7 @@ static void test_acpi_piix4_tcg_ipmi(void) free_test_data(&data); } =20 -static void test_acpi_q35_tcg_memhp(void) +static void test_acpi_q35_memhp(void) { test_data data; =20 @@ -957,7 +957,7 @@ static void test_acpi_q35_tcg_memhp(void) free_test_data(&data); } =20 -static void test_acpi_piix4_tcg_memhp(void) +static void test_acpi_piix4_memhp(void) { test_data data; =20 @@ -973,7 +973,7 @@ static void test_acpi_piix4_tcg_memhp(void) free_test_data(&data); } =20 -static void test_acpi_piix4_tcg_nosmm(void) +static void test_acpi_piix4_nosmm(void) { test_data data; =20 @@ -984,7 +984,7 @@ static void test_acpi_piix4_tcg_nosmm(void) free_test_data(&data); } =20 -static void test_acpi_piix4_tcg_smm_compat(void) +static void test_acpi_piix4_smm_compat(void) { test_data data; =20 @@ -995,7 +995,7 @@ static void test_acpi_piix4_tcg_smm_compat(void) free_test_data(&data); } =20 -static void test_acpi_piix4_tcg_smm_compat_nosmm(void) +static void test_acpi_piix4_smm_compat_nosmm(void) { test_data data; =20 @@ -1006,7 +1006,7 @@ static void test_acpi_piix4_tcg_smm_compat_nosmm(void) free_test_data(&data); } =20 -static void test_acpi_piix4_tcg_nohpet(void) +static void test_acpi_piix4_nohpet(void) { test_data data; =20 @@ -1017,7 +1017,7 @@ static void test_acpi_piix4_tcg_nohpet(void) free_test_data(&data); } =20 -static void test_acpi_q35_tcg_numamem(void) +static void test_acpi_q35_numamem(void) { test_data data; =20 @@ -1029,7 +1029,7 @@ static void test_acpi_q35_tcg_numamem(void) free_test_data(&data); } =20 -static void test_acpi_q35_tcg_nosmm(void) +static void test_acpi_q35_nosmm(void) { test_data data; =20 @@ -1040,7 +1040,7 @@ static void test_acpi_q35_tcg_nosmm(void) free_test_data(&data); } =20 -static void test_acpi_q35_tcg_smm_compat(void) +static void test_acpi_q35_smm_compat(void) { test_data data; =20 @@ -1051,7 +1051,7 @@ static void test_acpi_q35_tcg_smm_compat(void) free_test_data(&data); } =20 -static void test_acpi_q35_tcg_smm_compat_nosmm(void) +static void test_acpi_q35_smm_compat_nosmm(void) { test_data data; =20 @@ -1062,7 +1062,7 @@ static void test_acpi_q35_tcg_smm_compat_nosmm(void) free_test_data(&data); } =20 -static void test_acpi_q35_tcg_nohpet(void) +static void test_acpi_q35_nohpet(void) { test_data data; =20 @@ -1073,7 +1073,7 @@ static void test_acpi_q35_tcg_nohpet(void) free_test_data(&data); } =20 -static void test_acpi_piix4_tcg_numamem(void) +static void test_acpi_piix4_numamem(void) { test_data data; =20 @@ -1087,11 +1087,11 @@ static void test_acpi_piix4_tcg_numamem(void) =20 uint64_t tpm_tis_base_addr; =20 -static void test_acpi_tcg_tpm(const char *machine, const char *tpm_if, +static void test_acpi_tpm(const char *machine, const char *tpm_if, uint64_t base) { #ifdef CONFIG_TPM - gchar *tmp_dir_name =3D g_strdup_printf("qemu-test_acpi_%s_tcg_%s.XXXX= XX", + gchar *tmp_dir_name =3D g_strdup_printf("qemu-test_acpi_%s_%s.XXXXXX", machine, tpm_if); char *tmp_path =3D g_dir_make_tmp(tmp_dir_name, NULL); TestState test; @@ -1139,12 +1139,12 @@ static void test_acpi_tcg_tpm(const char *machine, = const char *tpm_if, #endif } =20 -static void test_acpi_q35_tcg_tpm_tis(void) +static void test_acpi_q35_tpm_tis(void) { - test_acpi_tcg_tpm("q35", "tis", 0xFED40000); + test_acpi_tpm("q35", "tis", 0xFED40000); } =20 -static void test_acpi_tcg_dimm_pxm(const char *machine) +static void test_acpi_dimm_pxm(const char *machine) { test_data data; =20 @@ -1174,14 +1174,14 @@ static void test_acpi_tcg_dimm_pxm(const char *mach= ine) free_test_data(&data); } =20 -static void test_acpi_q35_tcg_dimm_pxm(void) +static void test_acpi_q35_dimm_pxm(void) { - test_acpi_tcg_dimm_pxm(MACHINE_Q35); + test_acpi_dimm_pxm(MACHINE_Q35); } =20 -static void test_acpi_piix4_tcg_dimm_pxm(void) +static void test_acpi_piix4_dimm_pxm(void) { - test_acpi_tcg_dimm_pxm(MACHINE_PC); + test_acpi_dimm_pxm(MACHINE_PC); } =20 static void test_acpi_virt_tcg_memhp(void) @@ -1223,7 +1223,7 @@ static void test_acpi_microvm_prepare(test_data *data) data->blkdev =3D "virtio-blk-device"; } =20 -static void test_acpi_microvm_tcg(void) +static void test_acpi_microvm(void) { test_data data; =20 @@ -1233,7 +1233,7 @@ static void test_acpi_microvm_tcg(void) free_test_data(&data); } =20 -static void test_acpi_microvm_usb_tcg(void) +static void test_acpi_microvm_usb(void) { test_data data; =20 @@ -1244,7 +1244,7 @@ static void test_acpi_microvm_usb_tcg(void) free_test_data(&data); } =20 -static void test_acpi_microvm_rtc_tcg(void) +static void test_acpi_microvm_rtc(void) { test_data data; =20 @@ -1255,7 +1255,7 @@ static void test_acpi_microvm_rtc_tcg(void) free_test_data(&data); } =20 -static void test_acpi_microvm_pcie_tcg(void) +static void test_acpi_microvm_pcie(void) { test_data data; =20 @@ -1267,7 +1267,7 @@ static void test_acpi_microvm_pcie_tcg(void) free_test_data(&data); } =20 -static void test_acpi_microvm_ioapic2_tcg(void) +static void test_acpi_microvm_ioapic2(void) { test_data data; =20 @@ -1332,7 +1332,7 @@ static void test_acpi_virt_tcg_pxb(void) free_test_data(&data); } =20 -static void test_acpi_tcg_acpi_hmat(const char *machine) +static void test_acpi_acpi_hmat(const char *machine) { test_data data; =20 @@ -1364,14 +1364,14 @@ static void test_acpi_tcg_acpi_hmat(const char *mac= hine) free_test_data(&data); } =20 -static void test_acpi_q35_tcg_acpi_hmat(void) +static void test_acpi_q35_acpi_hmat(void) { - test_acpi_tcg_acpi_hmat(MACHINE_Q35); + test_acpi_acpi_hmat(MACHINE_Q35); } =20 -static void test_acpi_piix4_tcg_acpi_hmat(void) +static void test_acpi_piix4_acpi_hmat(void) { - test_acpi_tcg_acpi_hmat(MACHINE_PC); + test_acpi_acpi_hmat(MACHINE_PC); } =20 static void test_acpi_virt_tcg(void) @@ -1512,50 +1512,50 @@ int main(int argc, char *argv[]) return ret; } qtest_add_func("acpi/q35/oem-fields", test_acpi_oem_fields_q35); - qtest_add_func("acpi/q35/tpm-tis", test_acpi_q35_tcg_tpm_tis); - qtest_add_func("acpi/piix4", test_acpi_piix4_tcg); + qtest_add_func("acpi/q35/tpm-tis", test_acpi_q35_tpm_tis); + qtest_add_func("acpi/piix4", test_acpi_piix4); qtest_add_func("acpi/oem-fields", test_acpi_oem_fields_pc); - qtest_add_func("acpi/piix4/bridge", test_acpi_piix4_tcg_bridge); + qtest_add_func("acpi/piix4/bridge", test_acpi_piix4_bridge); qtest_add_func("acpi/piix4/pci-hotplug/no_root_hotplug", test_acpi_piix4_no_root_hotplug); qtest_add_func("acpi/piix4/pci-hotplug/no_bridge_hotplug", test_acpi_piix4_no_bridge_hotplug); qtest_add_func("acpi/piix4/pci-hotplug/off", test_acpi_piix4_no_acpi_pci_hotplug); - qtest_add_func("acpi/q35", test_acpi_q35_tcg); - qtest_add_func("acpi/q35/bridge", test_acpi_q35_tcg_bridge); - qtest_add_func("acpi/q35/mmio64", test_acpi_q35_tcg_mmio64); - qtest_add_func("acpi/piix4/ipmi", test_acpi_piix4_tcg_ipmi); - qtest_add_func("acpi/q35/ipmi", test_acpi_q35_tcg_ipmi); - qtest_add_func("acpi/piix4/cpuhp", test_acpi_piix4_tcg_cphp); - qtest_add_func("acpi/q35/cpuhp", test_acpi_q35_tcg_cphp); - qtest_add_func("acpi/piix4/memhp", test_acpi_piix4_tcg_memhp); - qtest_add_func("acpi/q35/memhp", test_acpi_q35_tcg_memhp); - qtest_add_func("acpi/piix4/numamem", test_acpi_piix4_tcg_numamem); - qtest_add_func("acpi/q35/numamem", test_acpi_q35_tcg_numamem); - qtest_add_func("acpi/piix4/nosmm", test_acpi_piix4_tcg_nosmm); + qtest_add_func("acpi/q35", test_acpi_q35); + qtest_add_func("acpi/q35/bridge", test_acpi_q35_bridge); + qtest_add_func("acpi/q35/mmio64", test_acpi_q35_mmio64); + qtest_add_func("acpi/piix4/ipmi", test_acpi_piix4_ipmi); + qtest_add_func("acpi/q35/ipmi", test_acpi_q35_ipmi); + qtest_add_func("acpi/piix4/cpuhp", test_acpi_piix4_cphp); + qtest_add_func("acpi/q35/cpuhp", test_acpi_q35_cphp); + qtest_add_func("acpi/piix4/memhp", test_acpi_piix4_memhp); + qtest_add_func("acpi/q35/memhp", test_acpi_q35_memhp); + qtest_add_func("acpi/piix4/numamem", test_acpi_piix4_numamem); + qtest_add_func("acpi/q35/numamem", test_acpi_q35_numamem); + qtest_add_func("acpi/piix4/nosmm", test_acpi_piix4_nosmm); qtest_add_func("acpi/piix4/smm-compat", - test_acpi_piix4_tcg_smm_compat); + test_acpi_piix4_smm_compat); qtest_add_func("acpi/piix4/smm-compat-nosmm", - test_acpi_piix4_tcg_smm_compat_nosmm); - qtest_add_func("acpi/piix4/nohpet", test_acpi_piix4_tcg_nohpet); - qtest_add_func("acpi/q35/nosmm", test_acpi_q35_tcg_nosmm); + test_acpi_piix4_smm_compat_nosmm); + qtest_add_func("acpi/piix4/nohpet", test_acpi_piix4_nohpet); + qtest_add_func("acpi/q35/nosmm", test_acpi_q35_nosmm); qtest_add_func("acpi/q35/smm-compat", - test_acpi_q35_tcg_smm_compat); + test_acpi_q35_smm_compat); qtest_add_func("acpi/q35/smm-compat-nosmm", - test_acpi_q35_tcg_smm_compat_nosmm); - qtest_add_func("acpi/q35/nohpet", test_acpi_q35_tcg_nohpet); - qtest_add_func("acpi/piix4/dimmpxm", test_acpi_piix4_tcg_dimm_pxm); - qtest_add_func("acpi/q35/dimmpxm", test_acpi_q35_tcg_dimm_pxm); - qtest_add_func("acpi/piix4/acpihmat", test_acpi_piix4_tcg_acpi_hma= t); - qtest_add_func("acpi/q35/acpihmat", test_acpi_q35_tcg_acpi_hmat); - qtest_add_func("acpi/microvm", test_acpi_microvm_tcg); - qtest_add_func("acpi/microvm/usb", test_acpi_microvm_usb_tcg); - qtest_add_func("acpi/microvm/rtc", test_acpi_microvm_rtc_tcg); - qtest_add_func("acpi/microvm/ioapic2", test_acpi_microvm_ioapic2_t= cg); + test_acpi_q35_smm_compat_nosmm); + qtest_add_func("acpi/q35/nohpet", test_acpi_q35_nohpet); + qtest_add_func("acpi/piix4/dimmpxm", test_acpi_piix4_dimm_pxm); + qtest_add_func("acpi/q35/dimmpxm", test_acpi_q35_dimm_pxm); + qtest_add_func("acpi/piix4/acpihmat", test_acpi_piix4_acpi_hmat); + qtest_add_func("acpi/q35/acpihmat", test_acpi_q35_acpi_hmat); + qtest_add_func("acpi/microvm", test_acpi_microvm); + qtest_add_func("acpi/microvm/usb", test_acpi_microvm_usb); + qtest_add_func("acpi/microvm/rtc", test_acpi_microvm_rtc); + qtest_add_func("acpi/microvm/ioapic2", test_acpi_microvm_ioapic2); qtest_add_func("acpi/microvm/oem-fields", test_acpi_oem_fields_mic= rovm); if (strcmp(arch, "x86_64") =3D=3D 0) { - qtest_add_func("acpi/microvm/pcie", test_acpi_microvm_pcie_tcg= ); + qtest_add_func("acpi/microvm/pcie", test_acpi_microvm_pcie); } } else if (strcmp(arch, "aarch64") =3D=3D 0) { qtest_add_func("acpi/virt", test_acpi_virt_tcg); --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622822149; cv=none; d=zohomail.com; s=zohoarc; b=LXWD+29StHutixcelz7tAXMnl71yZdGur0UAStoXV/X7ixTQOjumdXyEaISoRFkCtYKFjEXbZXiJpMFClHSjnQ7CUckOVsQZnQz6ZJS9VcHwRwMY88o21aM26eZkfwd54ixLOVT8epsMNkFqDiU4NFOjgF5TAf0iwxdb2fSbdMM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622822149; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YzeACc1wsH/oKOcJhjQoY6+4BE5bGAGTHjMBp9qY+rQ=; b=PaMJP9kZq4+YmZ5wgGchFxso9i9H3bx9oX4CDzjophNuzIhclRk4T/bVuBWO+/1OADwCR3Ua5a6myXErS/v6/YIXWyN5vKUUKT5uGQ5tLSkOR4Yym85an0iwFaP96pxUmMojpyY5hGMEQbFnudq578sbzJfIpn2Aer4CcZ0/eIw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622822149921635.1446453137742; Fri, 4 Jun 2021 08:55:49 -0700 (PDT) Received: from localhost ([::1]:51824 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCAm-00086m-T9 for importer@patchew.org; Fri, 04 Jun 2021 11:55:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44680) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8f-0003D9-UI for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:37 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:40958) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8b-00008M-FB for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:37 -0400 Received: by mail-wm1-x333.google.com with SMTP id b145-20020a1c80970000b029019c8c824054so8206279wmd.5 for ; Fri, 04 Jun 2021 08:53:32 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id 32sm7976328wrs.5.2021.06.04.08.53.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:24 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 492161FF99; Fri, 4 Jun 2021 16:53:13 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YzeACc1wsH/oKOcJhjQoY6+4BE5bGAGTHjMBp9qY+rQ=; b=l/E2T43Mtl+Bfg/wVWB0xLuC2QJ8kJrYS9/fn2dhcIsMPJhwwOxgQEYqr86pE3WMYo igXoesKIHiU8siquKI39ttrW6RdREx30d951yWEw4TubQg/5KTLwQDymcv4uGNn5fUk8 Ejx64XeujPRpqIAh8YyYnEuNRKB19BRKq7UbJ1saxAc+jXqoVPZajWC3uYFC996w2k96 oZXcbVHkX8VY65rCCIYkuog73QLZxk1NcEah6o1bGv6rHuEoC/QCJsYsqpKrJdZWUBfk mnWc1RMZ2AfOHeaBMcmyNGpImHiDO7dRrrJMNGMyjp1CYm+FZSSS29WwVojMSV6HndhX fOhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YzeACc1wsH/oKOcJhjQoY6+4BE5bGAGTHjMBp9qY+rQ=; b=sKbpcODBkqiSem4XYGA4zD43xlDWoEFqnDZfYgh6lo1e5EYT9F4CRVQUZ/R2RlcHVN AoVNmTAFr5zYWI/7FlHvOJXlThN4y6OmqgA/1RyA5DUKVeMdM7drGU+CaW9hiph7E+b7 Z3//II9oxoC+Q6e+5KUsuCrK2ft+g5oZMAQovWp1lFaEzz7frXNELe/WitZXzBK3r/fM 2YJg2IE4cgbvmIM0PHPBJdDJoXE/b6gPseUA49vwFPc5bxCZ1LgEEJJWduZbmXF2Xtwg egEEBlHU7MkaksIcXIuzfau2QobGxGzeGeeyNpRent0p6CDoH4MxI70gG1GExLSDGjMg 8z6A== X-Gm-Message-State: AOAM533qQPNmuczOAzsPG1XC5KU9CYEgt4kCJZ+n2aKtWFgS5FcBS52B MB8z38eVzZPWl5snwFNRrJ073w== X-Google-Smtp-Source: ABdhPJwyO8s6HYNMMlFYKenvSdfFwHFRUaFQa/hk9zoTD7ikTSWTyBhZE8351YF5Qt39W+JKCIhfhA== X-Received: by 2002:a05:600c:2188:: with SMTP id e8mr4462876wme.129.1622822011826; Fri, 04 Jun 2021 08:53:31 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 10/99] qtest/bios-tables-test: Rename TCG specific tests Date: Fri, 4 Jun 2021 16:51:43 +0100 Message-Id: <20210604155312.15902-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Igor Mammedov , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Some tests require TCG, but don't have '_tcg' in their name, while others do. Unify the test names by adding 'tcg' to the TCG specific tests. Reported-by: Igor Mammedov Reviewed-by: Igor Mammedov Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Alex Benn=C3=A9e Message-Id: <20210505125806.1263441-11-philmd@redhat.com> --- tests/qtest/bios-tables-test.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index ce498b3ff4..ad877baeb1 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1255,7 +1255,7 @@ static void test_acpi_microvm_rtc(void) free_test_data(&data); } =20 -static void test_acpi_microvm_pcie(void) +static void test_acpi_microvm_pcie_tcg(void) { test_data data; =20 @@ -1475,7 +1475,7 @@ static void test_acpi_oem_fields_microvm(void) g_free(args); } =20 -static void test_acpi_oem_fields_virt(void) +static void test_acpi_oem_fields_virt_tcg(void) { test_data data =3D { .machine =3D "virt", @@ -1555,14 +1555,14 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/microvm/ioapic2", test_acpi_microvm_ioapic2); qtest_add_func("acpi/microvm/oem-fields", test_acpi_oem_fields_mic= rovm); if (strcmp(arch, "x86_64") =3D=3D 0) { - qtest_add_func("acpi/microvm/pcie", test_acpi_microvm_pcie); + qtest_add_func("acpi/microvm/pcie", test_acpi_microvm_pcie_tcg= ); } } else if (strcmp(arch, "aarch64") =3D=3D 0) { qtest_add_func("acpi/virt", test_acpi_virt_tcg); qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem); qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp); qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb); - qtest_add_func("acpi/virt/oem-fields", test_acpi_oem_fields_virt); + qtest_add_func("acpi/virt/oem-fields", test_acpi_oem_fields_virt_t= cg); } ret =3D g_test_run(); boot_sector_cleanup(disk); --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622823197; cv=none; d=zohomail.com; s=zohoarc; b=BZ9o5jPPs1LhmZ9zcB+H6Tpg1Ot05ExNLhkc6GHU93vOZeLDeNaWBUcEhJSlaCsmBjziwh4ZsNGl64JYQGcpfap6nuDEFNi/qwg4W7FV0nEGGFTVcNAKCqucMBbrJKSvl11vej9VvLWHW7/PojLJz/fybOelbZJs7oR/Nnb/voE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622823197; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=S4sdlJss3fc5mJwXHCh2ySSBFoRnKokoMtehS+ckwhM=; b=FRApQY4cjhbqOdyWNJSiuwEomr12p7iFcRB65CorG9c1NKkMh/02/MISyTx6b1arGL5FGgQxZeKvMfHIbbh2I7IeU26Jn6DngveFZ0sC/kdTzpAEZiBSvnBJfiFbqyadt1g3M/BuAtPrs8suBJ92TWFswi6+cPm7Tabb2IGqZcg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622823197292383.9140507450081; Fri, 4 Jun 2021 09:13:17 -0700 (PDT) Received: from localhost ([::1]:46772 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCRg-0002SS-8o for importer@patchew.org; Fri, 04 Jun 2021 12:13:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44542) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8b-0002uS-4G for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:33 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:33531) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8Y-00005q-NJ for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:32 -0400 Received: by mail-wr1-x42d.google.com with SMTP id a20so9852847wrc.0 for ; Fri, 04 Jun 2021 08:53:30 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id s62sm9212366wms.13.2021.06.04.08.53.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:24 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 5E8C71FF9A; Fri, 4 Jun 2021 16:53:13 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S4sdlJss3fc5mJwXHCh2ySSBFoRnKokoMtehS+ckwhM=; b=QTkPKJc14r1NA8Dkr7oI7muo1JR5+lKUzKCMV3FSzcnGm6bOxfrLlgcR+1EVYXfxdb IsM61dWNcNeerTgF6tIgk3I/1vl8AEJHkoTqaVIOVcvaR1D9VqLnb2A9Ex6Ttt/I+ITC Gp6NImQJVwKPRCguWTnsEMpkPWkMmolpHruLc2k+A7MSxLLoK547HTBjszHi4yFEMCwR NdXvV1Czo3jvLjkCE50t6ip6kMsU42tNifRWkxa5OwsftoZ/YEToc0qTu5DPife7iYrE r1aPyWJSmAe1gVn1ZDAaoeG9PBqBPqcT/gbXHMSzCUoy5KVaKi5FN8UzUImlmlRtZVQF pfiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S4sdlJss3fc5mJwXHCh2ySSBFoRnKokoMtehS+ckwhM=; b=tgFJj4VNhUWjRhn0jXs+ucfbWL+p5OvNVQp2Xcn2vk171YZ05/tI6nRBgOQlG5850E MrJF0CMe6roOQZrktI5AWtDYQpUPwDCYPDDdUj/gAiTI1xDkNAaX/Hvc+8f0MhDf7H3p mGQCm8U+2Km/TA2YatIHcZJgrdd35MbSC8HEGGVq0vSqTjMiMWkOjeGbvfp2pFhgq47p Ca3QbZdTfW5yDJK7bLUdwi/sE6o5mGa1qU5eQt5xQEtXRVYhORAzaXYGlghLOwie8jRG cOVr1Z+in0mXSSfsIJf1Y52EGwuay/xHIOt2wAfDDh9xl2uwadruv/OZKoFB5mKV7dKL jZjw== X-Gm-Message-State: AOAM532exfJZ5hJXa0gGUf086J0X2s+6+aJJ5RQBCr+zkUhNZXpZ5qoA A5/hIYIYEts895unzRsaNpXI7w== X-Google-Smtp-Source: ABdhPJzUT78bZHXyFi3wI1MmDI0ZvyoeOzcCvYDdb/ivew4dBjQpWgF2bXZ18j5F5eaNd6dpcWHpyw== X-Received: by 2002:adf:a108:: with SMTP id o8mr4732699wro.290.1622822009072; Fri, 04 Jun 2021 08:53:29 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 11/99] qtest/bios-tables-test: Make test build-independent from accelerator Date: Fri, 4 Jun 2021 16:51:44 +0100 Message-Id: <20210604155312.15902-12-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Michael S. Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Igor Mammedov , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Now that we can probe if the TCG accelerator is available at runtime with a QMP command, do it once at the beginning and only register the tests we can run. We can then replace the #ifdef'ry by an assertion. Reviewed-by: Eric Blake Reviewed-by: Igor Mammedov Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Alex Benn=C3=A9e Message-Id: <20210505125806.1263441-12-philmd@redhat.com> Reviewed-by: Richard Henderson Reviewed-by: Thomas Huth --- tests/qtest/bios-tables-test.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index ad877baeb1..762d154b34 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -97,6 +97,7 @@ typedef struct { QTestState *qts; } test_data; =20 +static bool tcg_accel_available; static char disk[] =3D "tests/acpi-test-disk-XXXXXX"; static const char *data_dir =3D "tests/data/acpi"; #ifdef CONFIG_IASL @@ -718,12 +719,7 @@ static void test_acpi_one(const char *params, test_dat= a *data) char *args; bool use_uefi =3D data->uefi_fl1 && data->uefi_fl2; =20 -#ifndef CONFIG_TCG - if (data->tcg_only) { - g_test_skip("TCG disabled, skipping ACPI tcg_only test"); - return; - } -#endif /* CONFIG_TCG */ + assert(!data->tcg_only || tcg_accel_available); =20 args =3D test_acpi_create_args(data, params, use_uefi); data->qts =3D qtest_init(args); @@ -1506,6 +1502,8 @@ int main(int argc, char *argv[]) =20 g_test_init(&argc, &argv, NULL); =20 + tcg_accel_available =3D qtest_has_accel("tcg"); + if (strcmp(arch, "i386") =3D=3D 0 || strcmp(arch, "x86_64") =3D=3D 0) { ret =3D boot_sector_init(disk); if (ret) { @@ -1554,10 +1552,10 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/microvm/rtc", test_acpi_microvm_rtc); qtest_add_func("acpi/microvm/ioapic2", test_acpi_microvm_ioapic2); qtest_add_func("acpi/microvm/oem-fields", test_acpi_oem_fields_mic= rovm); - if (strcmp(arch, "x86_64") =3D=3D 0) { + if (strcmp(arch, "x86_64") =3D=3D 0 && tcg_accel_available) { qtest_add_func("acpi/microvm/pcie", test_acpi_microvm_pcie_tcg= ); } - } else if (strcmp(arch, "aarch64") =3D=3D 0) { + } else if (strcmp(arch, "aarch64") =3D=3D 0 && tcg_accel_available) { qtest_add_func("acpi/virt", test_acpi_virt_tcg); qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem); qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp); --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622823052; cv=none; d=zohomail.com; s=zohoarc; b=JH3fbDqB9fIXdhQP7J93AVVtH3TBAEpuZoreB7hPLxK4JRyjp5C9xnANjyXjIhQIpUuAjaiMK6OgB/qCA6YEzMl5vvTEL48QfuTw4/RJbO63IkpdWcyh6/MVhkFJWrEt+3o2CQgHFTj9QUmke9310PJw3ry/3jO20a7mHFra+0k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622823052; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TUAH7JH6sleif6Yi/np3XOEDj2fTn8clJjdpTJ+Ga34=; b=MLz30gQzt9vCcpxVVJWovpBuhOnHu8UjtW5E8yTbrUcu3Th7nnOWn6ZL0ljE1YIayp7F+J3BAqetLtcNXzy0pqrw4mZTdoUcQM1uf89JyWO64NYk4kPIjPAPSVZWUIESapZTsDor9VsYEVuAi9ZBFIqeXf/FP8vAmJVVTcXfUO8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622823052636825.9302638019986; Fri, 4 Jun 2021 09:10:52 -0700 (PDT) Received: from localhost ([::1]:37984 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCPL-0004Hj-E2 for importer@patchew.org; Fri, 04 Jun 2021 12:10:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44464) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8Y-0002mU-FY for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:30 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:38652) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8V-0008VI-S0 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:30 -0400 Received: by mail-wm1-x334.google.com with SMTP id t4-20020a1c77040000b029019d22d84ebdso8196130wmi.3 for ; Fri, 04 Jun 2021 08:53:27 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id b22sm2782729wmj.22.2021.06.04.08.53.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:24 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 7374F1FF9B; Fri, 4 Jun 2021 16:53:13 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TUAH7JH6sleif6Yi/np3XOEDj2fTn8clJjdpTJ+Ga34=; b=ujGNIWqbA5UJVSACD3kh2IHSs8XLv2gFrHwVH4KjpF01wDk4mOEyK1yPukApQGZAFA ftZwampw5bHyS6XePvbsZaVIK7L5TiEMsXcBrZdhRNmMsGaRjROThLBzOqICw7P1YknS C9cGsmtqOn49/QZr6i6ICP/llP5VSDRRlz4YOKcDTzVWLlmZSEOg1VHHC1MquiNmDnOd 0lX095Kz+6WOpzrRWJO3GKOr5PCaA4uTxId8jJUQKAbHijHF3qTO0ejXGPuk/7ujKUNu KJ0o7e9VaGqKu1mb0MV0IsIWOxBNTGLETuRWKm+yDwURhyKlEUU54onyVdKXFDmZnKkY VPsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TUAH7JH6sleif6Yi/np3XOEDj2fTn8clJjdpTJ+Ga34=; b=YqAwUfCGB/k/1N4Avr45texPxYzcLspZm4DjVqfvbpqiXmsM3WEkBW+5g6OuJm4Txd If1jIKD2aNRyUt/piU0X6f66RxCsKfjQhPRf9LL9Z3Sl+aY49nwdfOfXeLW3aAi0LfMc zBRmM5g8KzyGKr2RTt2PzmWHaKyf8dJxkZn/Fyo5WDhqJxjAkAZ9jgZNnnhFDdr9Y5AU w9UfP93k92Y0T97rNCJzya/KNEoY/LK8PDfkVlQ0GXeTBbJNIGUvOnPc6fzOuMNadCXQ hzJGr+rLtrGUgQMRM1606wcdrgsZKNDK3l0wInSRoMxSCxDAznYAgjXwrK4i7kZtBBQH YckQ== X-Gm-Message-State: AOAM531aY+fxUPTsaPhrNgOTe6Dgk16hVvK+oNz6FHt+2DmKYBAvQlrg 2s9wODD0eNumAJMU17g2/G/MP99Eod4DTA== X-Google-Smtp-Source: ABdhPJwN7yHNbXjEeSpNqpSxh5+ShIZZhSbXwRml4aeT3QvbtnruJtOwiTz3x3VcWm9qpjDZJzPWVA== X-Received: by 2002:a7b:c157:: with SMTP id z23mr4471975wmi.148.1622822006340; Fri, 04 Jun 2021 08:53:26 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 12/99] qtest: Do not restrict bios-tables-test to Aarch64 hosts anymore Date: Fri, 4 Jun 2021 16:51:45 +0100 Message-Id: <20210604155312.15902-13-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Since commit 82bf7ae84ce ("target/arm: Remove KVM support for 32-bit Arm hosts") we can remove the comment / check added in commit ab6b6a77774 and directly run the bios-tables-test. Reviewed-by: Eric Blake Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Alex Benn=C3=A9e Message-Id: <20210505125806.1263441-13-philmd@redhat.com> Acked-by: Thomas Huth Reviewed-by: Richard Henderson --- tests/qtest/meson.build | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index c3a223a83d..2c7415d616 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -176,14 +176,13 @@ qtests_arm =3D \ 'boot-serial-test', 'hexloader-test'] =20 -# TODO: once aarch64 TCG is fixed on ARM 32 bit host, make bios-tables-tes= t unconditional qtests_aarch64 =3D \ - (cpu !=3D 'arm' ? ['bios-tables-test'] : []) + = \ (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-= test'] : []) + \ (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-= swtpm-test'] : []) + \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', + 'bios-tables-test', 'xlnx-can-test', 'migration-test'] =20 --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622822664; cv=none; d=zohomail.com; s=zohoarc; b=UvYfb/squjCOd9uT3seWm7IvXWSZW8CxRggRicqOo+3Vgu1+LDlJtpD5LDzM8TVs9jmzCAcsQjgtwD0rc7nEcIC0nCcRC6Z7sSRdrDvpfucZRW9bX1UK3Ely0osg2W9g1ri7/tSXQDDUW98rq2Bxmh3+p8OsRKn/BTftAcWlWrQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622822664; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bGZvEWP0B7XQQEsHoRPrpycuhOjRaiqhP5MCalZexp8=; b=JWFrnmUplRsKG2v2vGlHX1D0aZdVRGkZqJciSvcNE19w7zOy4jn5Jn5qA3RAMjLDMGy1FnrzdNbc4Dda9q3Zn5hVyWiOzPOzW6fYPXBFOxLR1I29BgZ4P8Bb+4LqegYHQjpbshi5mz6JHS4wjRVsIq0qnCTMp30AxFi+i8fubmk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622822664826652.4352531410368; Fri, 4 Jun 2021 09:04:24 -0700 (PDT) Received: from localhost ([::1]:51040 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCJ5-0001zi-O6 for importer@patchew.org; Fri, 04 Jun 2021 12:04:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44610) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8d-000331-9c for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:35 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:36842) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8Z-00006V-LB for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:34 -0400 Received: by mail-wr1-x434.google.com with SMTP id n4so9814581wrw.3 for ; Fri, 04 Jun 2021 08:53:31 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id g11sm6873579wri.59.2021.06.04.08.53.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:24 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A88F91FF9C; Fri, 4 Jun 2021 16:53:13 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bGZvEWP0B7XQQEsHoRPrpycuhOjRaiqhP5MCalZexp8=; b=WXrKnXghbHEvw8Vgiq01+e7x8S36P2nbON4QAdKLwgJKvKlXFLZL2t966Npejniae1 kmgtm8uPNGRTwLthfl+0SYlhYwqJ+PI8bI2QsGTUQodygLZHtFTJwsm5wMAXUEx4zKQV k39dJMQ7hLKZ+DAbpot18+mGaLE2QViRkqFgWIUXDqFNMw7861ZL4OtZNqGR6khhc0EA iR5wqCSgX/Hcefcczp7oVSQBjHODyHzSf/Cnfz+oIODZB9yB0GbGKd+H+A5Us597HxLm nlBc6yAyrRjGezhaxh6rRXmL/aCBRz1Slqtq35LlPbThTgqAv/oyZkM080QC9TnX7lnW 3/Uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bGZvEWP0B7XQQEsHoRPrpycuhOjRaiqhP5MCalZexp8=; b=QGbQPD698dcUNSlcXEGoPoyEeKrWIy13ZxJQlui0K67WFIG0tLIr0rJqYvxaWLw7e2 St8WZuvUhhWKwBWEAhVYTp28AV5tkehMniCC30zQ7F6D/wMxgH9SnVxxhEvhXCvhqy7y 5ub7rJToAwagCFtP8Jpe2BLUxEZ4xKm897we2DlSfziK9G0PVMOg92lMyyfJYcCaKdqr CJIOonva2zzleXGy7Z1rlPbSifni17s6WHEnZ0dhKHBEehUtteWashhhnNwTM7erK0Ra FCoU1Diu9YOilf3ko5s/qyOJmCkIuumVPuCuiWDzumpqATHSMwju3BjHnn28A4MrRCgg 3Idw== X-Gm-Message-State: AOAM533fTeLY4H+SQkD8lnbaAyNU0mKBSuNEYEgJptJKs7/CQJAZkKB/ XZyXgqccOMKa79iwbwlTruihiw== X-Google-Smtp-Source: ABdhPJzWNcfOAbmTA2OrWC8c4VzflEkQqWUYnBHLnE3cP+gxprJXVyBjUmPrSNOIvrS6qB5vw7NDBQ== X-Received: by 2002:a5d:54c8:: with SMTP id x8mr4706349wrv.109.1622822010020; Fri, 04 Jun 2021 08:53:30 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 13/99] meson: add target_user_arch Date: Fri, 4 Jun 2021 16:51:46 +0100 Message-Id: <20210604155312.15902-14-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Cornelia Huck , David Hildenbrand , Bin Meng , Mark Cave-Ayland , Max Filippov , Taylor Simpson , Alistair Francis , "Edgar E. Iglesias" , Marek Vasut , Yoshinori Sato , Claudio Fontana , "open list:PowerPC TCG CPUs" , Artyom Tarasenko , Thomas Huth , Richard Henderson , Greg Kurz , "open list:S390 general arch..." , qemu-arm@nongnu.org, Stafford Horne , =?UTF-8?q?Alex=20Benn=C3=A9e?= , David Gibson , "open list:RISC-V TCG CPUs" , Bastian Koppelmann , Chris Wulff , Laurent Vivier , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana the lack of target_user_arch makes it hard to fully leverage the build system in order to separate user code from sysemu code. Provide it, so that we can avoid the proliferation of #ifdef in target code. Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e [claudio: added changes for new target hexagon] Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- v15 - remove duplicate ss.source_set for mips --- target/alpha/meson.build | 3 +++ target/arm/meson.build | 2 ++ target/cris/meson.build | 3 +++ target/hexagon/meson.build | 3 +++ target/hppa/meson.build | 3 +++ target/m68k/meson.build | 3 +++ target/microblaze/meson.build | 3 +++ target/nios2/meson.build | 3 +++ target/openrisc/meson.build | 3 +++ target/ppc/meson.build | 3 +++ target/riscv/meson.build | 3 +++ target/s390x/meson.build | 3 +++ target/sh4/meson.build | 3 +++ target/sparc/meson.build | 3 +++ target/tricore/meson.build | 3 +++ target/xtensa/meson.build | 3 +++ 16 files changed, 47 insertions(+) diff --git a/target/alpha/meson.build b/target/alpha/meson.build index 1aec55abb4..1b0555d3ee 100644 --- a/target/alpha/meson.build +++ b/target/alpha/meson.build @@ -14,5 +14,8 @@ alpha_ss.add(files( alpha_softmmu_ss =3D ss.source_set() alpha_softmmu_ss.add(files('machine.c')) =20 +alpha_user_ss =3D ss.source_set() + target_arch +=3D {'alpha': alpha_ss} target_softmmu_arch +=3D {'alpha': alpha_softmmu_ss} +target_user_arch +=3D {'alpha': alpha_user_ss} diff --git a/target/arm/meson.build b/target/arm/meson.build index 5bfaf43b50..6106d24665 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -56,6 +56,8 @@ arm_softmmu_ss.add(files( 'monitor.c', 'psci.c', )) +arm_user_ss =3D ss.source_set() =20 target_arch +=3D {'arm': arm_ss} target_softmmu_arch +=3D {'arm': arm_softmmu_ss} +target_user_arch +=3D {'arm': arm_user_ss} diff --git a/target/cris/meson.build b/target/cris/meson.build index 67c3793c85..7fd81e0348 100644 --- a/target/cris/meson.build +++ b/target/cris/meson.build @@ -10,5 +10,8 @@ cris_ss.add(files( cris_softmmu_ss =3D ss.source_set() cris_softmmu_ss.add(files('mmu.c', 'machine.c')) =20 +cris_user_ss =3D ss.source_set() + target_arch +=3D {'cris': cris_ss} target_softmmu_arch +=3D {'cris': cris_softmmu_ss} +target_user_arch +=3D {'cris': cris_user_ss} diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index 6fd9360b74..fe232810ab 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -175,4 +175,7 @@ hexagon_ss.add(files( 'fma_emu.c', )) =20 +hexagon_user_ss =3D ss.source_set() + target_arch +=3D {'hexagon': hexagon_ss} +target_user_arch +=3D {'hexagon': hexagon_user_ss} diff --git a/target/hppa/meson.build b/target/hppa/meson.build index 8a7ff82efc..85ad314671 100644 --- a/target/hppa/meson.build +++ b/target/hppa/meson.build @@ -15,5 +15,8 @@ hppa_ss.add(files( hppa_softmmu_ss =3D ss.source_set() hppa_softmmu_ss.add(files('machine.c')) =20 +hppa_user_ss =3D ss.source_set() + target_arch +=3D {'hppa': hppa_ss} target_softmmu_arch +=3D {'hppa': hppa_softmmu_ss} +target_user_arch +=3D {'hppa': hppa_user_ss} diff --git a/target/m68k/meson.build b/target/m68k/meson.build index 05cd9fbd1e..b507682684 100644 --- a/target/m68k/meson.build +++ b/target/m68k/meson.build @@ -13,5 +13,8 @@ m68k_ss.add(files( m68k_softmmu_ss =3D ss.source_set() m68k_softmmu_ss.add(files('monitor.c')) =20 +m68k_user_ss =3D ss.source_set() + target_arch +=3D {'m68k': m68k_ss} target_softmmu_arch +=3D {'m68k': m68k_softmmu_ss} +target_user_arch +=3D {'m68k': m68k_user_ss} diff --git a/target/microblaze/meson.build b/target/microblaze/meson.build index 05ee0ec163..52d8fcb0a3 100644 --- a/target/microblaze/meson.build +++ b/target/microblaze/meson.build @@ -16,5 +16,8 @@ microblaze_softmmu_ss.add(files( 'machine.c', )) =20 +microblaze_user_ss =3D ss.source_set() + target_arch +=3D {'microblaze': microblaze_ss} target_softmmu_arch +=3D {'microblaze': microblaze_softmmu_ss} +target_user_arch +=3D {'microblaze': microblaze_user_ss} diff --git a/target/nios2/meson.build b/target/nios2/meson.build index e643917db1..00367056fa 100644 --- a/target/nios2/meson.build +++ b/target/nios2/meson.build @@ -11,5 +11,8 @@ nios2_ss.add(files( nios2_softmmu_ss =3D ss.source_set() nios2_softmmu_ss.add(files('monitor.c')) =20 +nios2_user_ss =3D ss.source_set() + target_arch +=3D {'nios2': nios2_ss} target_softmmu_arch +=3D {'nios2': nios2_softmmu_ss} +target_user_arch +=3D {'nios2': nios2_user_ss} diff --git a/target/openrisc/meson.build b/target/openrisc/meson.build index 9774a58306..794a9e8161 100644 --- a/target/openrisc/meson.build +++ b/target/openrisc/meson.build @@ -19,5 +19,8 @@ openrisc_ss.add(files( openrisc_softmmu_ss =3D ss.source_set() openrisc_softmmu_ss.add(files('machine.c')) =20 +openrisc_user_ss =3D ss.source_set() + target_arch +=3D {'openrisc': openrisc_ss} target_softmmu_arch +=3D {'openrisc': openrisc_softmmu_ss} +target_user_arch +=3D {'openrisc': openrisc_user_ss} diff --git a/target/ppc/meson.build b/target/ppc/meson.build index a4f18ff414..0afaea25dd 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -51,5 +51,8 @@ ppc_softmmu_ss.add(when: 'TARGET_PPC64', if_true: files( 'mmu-radix64.c', )) =20 +ppc_user_ss =3D ss.source_set() + target_arch +=3D {'ppc': ppc_ss} target_softmmu_arch +=3D {'ppc': ppc_softmmu_ss} +target_user_arch +=3D {'ppc': ppc_user_ss} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index af6c3416b7..673b35b175 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -27,5 +27,8 @@ riscv_softmmu_ss.add(files( 'machine.c' )) =20 +riscv_user_ss =3D ss.source_set() + target_arch +=3D {'riscv': riscv_ss} target_softmmu_arch +=3D {'riscv': riscv_softmmu_ss} +target_user_arch +=3D {'riscv': riscv_user_ss} diff --git a/target/s390x/meson.build b/target/s390x/meson.build index c42eadb7d2..1219f64112 100644 --- a/target/s390x/meson.build +++ b/target/s390x/meson.build @@ -58,5 +58,8 @@ if host_machine.cpu_family() =3D=3D 's390x' and cc.has_li= nk_argument('-Wl,--s390-pgs if_true: declare_dependency(link_args: ['-Wl,--s390= -pgste'])) endif =20 +s390x_user_ss =3D ss.source_set() + target_arch +=3D {'s390x': s390x_ss} target_softmmu_arch +=3D {'s390x': s390x_softmmu_ss} +target_user_arch +=3D {'s390x': s390x_user_ss} diff --git a/target/sh4/meson.build b/target/sh4/meson.build index 56a57576da..5a05729bc1 100644 --- a/target/sh4/meson.build +++ b/target/sh4/meson.build @@ -10,5 +10,8 @@ sh4_ss.add(files( sh4_softmmu_ss =3D ss.source_set() sh4_softmmu_ss.add(files('monitor.c')) =20 +sh4_user_ss =3D ss.source_set() + target_arch +=3D {'sh4': sh4_ss} target_softmmu_arch +=3D {'sh4': sh4_softmmu_ss} +target_user_arch +=3D {'sh4': sh4_user_ss} diff --git a/target/sparc/meson.build b/target/sparc/meson.build index a3638b9503..cc77a77064 100644 --- a/target/sparc/meson.build +++ b/target/sparc/meson.build @@ -19,5 +19,8 @@ sparc_softmmu_ss.add(files( 'monitor.c', )) =20 +sparc_user_ss =3D ss.source_set() + target_arch +=3D {'sparc': sparc_ss} target_softmmu_arch +=3D {'sparc': sparc_softmmu_ss} +target_user_arch +=3D {'sparc': sparc_user_ss} diff --git a/target/tricore/meson.build b/target/tricore/meson.build index 0ccc829517..7086ae1a22 100644 --- a/target/tricore/meson.build +++ b/target/tricore/meson.build @@ -11,5 +11,8 @@ tricore_ss.add(zlib) =20 tricore_softmmu_ss =3D ss.source_set() =20 +tricore_user_ss =3D ss.source_set() + target_arch +=3D {'tricore': tricore_ss} target_softmmu_arch +=3D {'tricore': tricore_softmmu_ss} +target_user_arch +=3D {'tricore': tricore_user_ss} diff --git a/target/xtensa/meson.build b/target/xtensa/meson.build index 7c4efa6c62..ade555ae36 100644 --- a/target/xtensa/meson.build +++ b/target/xtensa/meson.build @@ -23,5 +23,8 @@ xtensa_softmmu_ss.add(files( 'xtensa-semi.c', )) =20 +xtensa_user_ss =3D ss.source_set() + target_arch +=3D {'xtensa': xtensa_ss} target_softmmu_arch +=3D {'xtensa': xtensa_softmmu_ss} +target_user_arch +=3D {'xtensa': xtensa_user_ss} --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622827138; cv=none; d=zohomail.com; s=zohoarc; b=bNfrX9AV0YPE4p2kM5N3jXojWcx3BurP3Pm0xCweyYkE4PGgE6fE+f0h2M0IDYPgBe7Y0DR4EfxZH/XwXmnthmgXoBDCiGpWS0/VWdR10gJJNZyLAjAClhLBIgQbvAUcaOOOONBLU4nQ8Xv2gGETzKNAh8LsyBzXGqpVMKmEQG4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622827138; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0qK3PtK1ZJ0cptr2WVdMdlRn0V00pOzTguQ/XpJv0Nw=; b=aQN46mn8Z7SVostRxfGPZzsuXPPxWPD1+kYH+0XQOgYk3kQE3L/Yh+yjqSulUEPtPCMBXRzjQcjCKM+Ra9cio6dj/NModL1Sikztp0IsFEkXaFb0+8VZYvMJfRWnbjUHWu5ckfNGtVvv3mJgLfUbzhtNqqer2YeU/6YbiI7dmEk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162282713872668.59725375943913; Fri, 4 Jun 2021 10:18:58 -0700 (PDT) Received: from localhost ([::1]:46278 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDTF-0006fV-N7 for importer@patchew.org; Fri, 04 Jun 2021 13:18:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpDNJ-00086u-Lu for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:49 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:39729) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpDNC-00021m-AS for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:49 -0400 Received: by mail-wr1-x42e.google.com with SMTP id l2so10038036wrw.6 for ; Fri, 04 Jun 2021 10:12:41 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id q3sm7211868wrr.43.2021.06.04.10.12.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 10:12:38 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id C96491FF9D; Fri, 4 Jun 2021 16:53:13 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0qK3PtK1ZJ0cptr2WVdMdlRn0V00pOzTguQ/XpJv0Nw=; b=WOjKAbtaYFNBmEFh1M3XN+TY7WR2aqCgcVLpDVHxXUhaCzd27M2HH848aV1XyL/XDW AmHZMagjIFUZuz0nT9LTUVm5OLZDWiUV4m/qDk2ReDfP6yFVsPqypVLIZmjfTKOSbnvC 2+Rl7ubJHcfF1U34Ess78woUEKrPogtxwFHAhd3kX8/BMJdE+qilgxav1+lcYWRs84db vRUYg3+oHhotH3p5gvle/B7MhlVYtupYPliOVC4zrydyHGnBO11QRYR3cXPYXnYarYQN N2bNXmGWbLXnquDq1TsG61jB08krHwffBEH4w4NJLmz15bWihIXTU4+IefOa1q/OlTQe 4cVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0qK3PtK1ZJ0cptr2WVdMdlRn0V00pOzTguQ/XpJv0Nw=; b=QgnIV8uhYv6bEC47AF/FLbL/EjxqcfnwNorH6ryqoTKOPFYzCiE+9w2M+Tu/W9a3+K y03Mh4GXxCfAnPZg5Gdy6yTxmabMUg0QdfoZexxFT6nQdx9HA0FV5J2ozeGF4nXQKuB4 P3HDGM3GeLtXeXBwLpy45qQM0+StEzhQFcmG35BZAjghWsEXXcVuJJ+a46nUMRJb/PW4 GY4DU71OEMIEaJWU+BHPlTMhqlPqytw4hJiBb6k09CTa0fo0xPgMN4f84kkKYU03S2S4 iQKgpsp3iEboTyO6z94IGW14KDWOFCkw2fDA8aW0pAcifmW1scjADl4p/Zepdo9+/gRd qzQg== X-Gm-Message-State: AOAM532hkoPyCmXFCGbq94CCCq1a1UAt2wBgiIYxCRjP4lcV5coH9pCU LODcaqllVgYZ4rtfzySGrV0uXA== X-Google-Smtp-Source: ABdhPJzSOvopO0cd+MEhvR1zsEEWKzvT9HTOJinmq+Ys5Nkqor5ZEJ8qjUqDXMhSsQjnv8zbDmSbRA== X-Received: by 2002:adf:f78d:: with SMTP id q13mr4878148wrp.191.1622826760625; Fri, 04 Jun 2021 10:12:40 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 14/99] accel: add cpu_reset Date: Fri, 4 Jun 2021 16:51:47 +0100 Message-Id: <20210604155312.15902-15-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:X86 KVM CPUs" , Marcelo Tosatti , Richard Henderson , qemu-arm@nongnu.org, Claudio Fontana , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana in cpu_reset(), implemented in the common cpu.c, add a call to a new accel_cpu_reset(), which ensures that the CPU accel interface is also reset when the CPU is reset. Use this first for x86/kvm, simply moving the kvm_arch_reset_vcpu() call. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- include/hw/core/accel-cpu.h | 2 ++ include/qemu/accel.h | 6 ++++++ accel/accel-common.c | 9 +++++++++ hw/core/cpu-common.c | 3 ++- target/i386/cpu.c | 4 ---- target/i386/kvm/kvm-cpu.c | 6 ++++++ 6 files changed, 25 insertions(+), 5 deletions(-) diff --git a/include/hw/core/accel-cpu.h b/include/hw/core/accel-cpu.h index 5dbfd79955..700a5bd266 100644 --- a/include/hw/core/accel-cpu.h +++ b/include/hw/core/accel-cpu.h @@ -33,6 +33,8 @@ typedef struct AccelCPUClass { void (*cpu_class_init)(CPUClass *cc); void (*cpu_instance_init)(CPUState *cpu); bool (*cpu_realizefn)(CPUState *cpu, Error **errp); + void (*cpu_reset)(CPUState *cpu); + } AccelCPUClass; =20 #endif /* ACCEL_CPU_H */ diff --git a/include/qemu/accel.h b/include/qemu/accel.h index 4f4c283f6f..8d3a15b916 100644 --- a/include/qemu/accel.h +++ b/include/qemu/accel.h @@ -91,4 +91,10 @@ void accel_cpu_instance_init(CPUState *cpu); */ bool accel_cpu_realizefn(CPUState *cpu, Error **errp); =20 +/** + * accel_cpu_reset: + * @cpu: The CPU that needs to call accel-specific reset. + */ +void accel_cpu_reset(CPUState *cpu); + #endif /* QEMU_ACCEL_H */ diff --git a/accel/accel-common.c b/accel/accel-common.c index cf07f78421..3331a9dcfd 100644 --- a/accel/accel-common.c +++ b/accel/accel-common.c @@ -121,6 +121,15 @@ bool accel_cpu_realizefn(CPUState *cpu, Error **errp) return true; } =20 +void accel_cpu_reset(CPUState *cpu) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->accel_cpu && cc->accel_cpu->cpu_reset) { + cc->accel_cpu->cpu_reset(cpu); + } +} + static const TypeInfo accel_cpu_type =3D { .name =3D TYPE_ACCEL_CPU, .parent =3D TYPE_OBJECT, diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index e2f5a64604..ab258ad4f2 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -34,6 +34,7 @@ #include "hw/qdev-properties.h" #include "trace/trace-root.h" #include "qemu/plugin.h" +#include "qemu/accel.h" =20 CPUState *cpu_by_arch_id(int64_t id) { @@ -112,7 +113,7 @@ void cpu_dump_state(CPUState *cpu, FILE *f, int flags) void cpu_reset(CPUState *cpu) { device_cold_reset(DEVICE(cpu)); - + accel_cpu_reset(cpu); trace_guest_cpu_reset(cpu); } =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e0ba36cc23..0c22324daf 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5749,10 +5749,6 @@ static void x86_cpu_reset(DeviceState *dev) apic_designate_bsp(cpu->apic_state, s->cpu_index =3D=3D 0); =20 s->halted =3D !cpu_is_bsp(cpu); - - if (kvm_enabled()) { - kvm_arch_reset_vcpu(cpu); - } #endif } =20 diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index 5235bce8dc..63410d3f18 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -135,12 +135,18 @@ static void kvm_cpu_instance_init(CPUState *cs) } } =20 +static void kvm_cpu_reset(CPUState *cpu) +{ + kvm_arch_reset_vcpu(X86_CPU(cpu)); +} + static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) { AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); =20 acc->cpu_realizefn =3D kvm_cpu_realizefn; acc->cpu_instance_init =3D kvm_cpu_instance_init; + acc->cpu_reset =3D kvm_cpu_reset; } static const TypeInfo kvm_cpu_accel_type_info =3D { .name =3D ACCEL_CPU_NAME("kvm"), --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622828274; cv=none; d=zohomail.com; s=zohoarc; b=Q4/ZS3pGVILMwyN6BFGpsGGdQGFMUY1SHd6uYKrfX7DfOjX+8z4TXDqlWFZCPo1TDoiQ0H2YSl0Gdudt+ZPCMRq7xtoys+wGEfe4YgZ2Q1/nevk2GRuHWaa00AfeRT6SvREc7v7RTeZ9lnfRbUY3lowlrT51vK7XwAcqZ8sHrSk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622828274; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2vvNAoxjt1VSZ2ICaP0bgwI19xolrw5FxWN3lqD0Qh4=; b=ZsYdm2AUJjcZOgf5DzznwFww/1FoSZVrUvf5UT8HdHNFOo+rkRrDh+VinWjx3B8aRVAdAxrQ8XdiylpniBsGpKsdnBKaypHZGGnXBQ0j5gDauz0hymVQmyVzETizDD4L483XzdIiFRcTVc+9cx0seVblTsO5SFBFbZkMxWOiWtc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622828274496626.0349330327276; Fri, 4 Jun 2021 10:37:54 -0700 (PDT) Received: from localhost ([::1]:51886 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDlZ-0007DG-Bg for importer@patchew.org; Fri, 04 Jun 2021 13:37:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48848) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpDNO-0008QR-6Q for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:54 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:34516) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpDNL-00025B-BS for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:53 -0400 Received: by mail-wr1-x431.google.com with SMTP id q5so10052209wrm.1 for ; Fri, 04 Jun 2021 10:12:50 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id k16sm6059847wmr.42.2021.06.04.10.12.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 10:12:46 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id E0AC71FF9E; Fri, 4 Jun 2021 16:53:13 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2vvNAoxjt1VSZ2ICaP0bgwI19xolrw5FxWN3lqD0Qh4=; b=d4j6xHj/02LhPK+9akWqA3CXM5sLVzlLbBfXMsglJ/gtWATcvd62Cc+gjYnQvoYTzF z3a1uJait3HaAY9w6JNdWpsL6MZeMdf2vfS6Pv5MWwloW8FV2/I4htK4MNXCis9Pnefu PUNgtMdf5I7XmB2dbqNA6Y3Srgolur1ZsFAvTDhxdUYprKvBQAS7fXO9VM72pXSujxcp w8eZk5sVLGte066UYtgVPuNKDuF/H9qUB9X7qIv1AdY0cZPR3GmRxp1jdqEvS3DxyvrO 95zsolFYDI5NxVa5WP+8YR96a98ww51+B+zTnQgYOnmDtEE9tBsccg0YM9dn7Tp0FH4f 1qWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2vvNAoxjt1VSZ2ICaP0bgwI19xolrw5FxWN3lqD0Qh4=; b=ldN9trUWJKJxF5mlP2hpaQz+UTjpxw4D1G5lH0jgDdS5TVm6I1CexuYL+CdH8azK0G Ox7Y+DweiYOZQd2F6pGMvsM9hAFHTIO6fBy+dvJ0nn5nUPYpQeEE52tuPz2CWNWJ/Jr/ CdyaVvLo5duH5mKlZQlmrAHjASdlb52+pCdJFXUqTcjSP5EIN+f5XQHiVRXJFjLlZ0EC Si4+2WU8coyPbKvlQI/pqPx/ALfd6c0eDwvaDJyMPj3o7O7I6JhJB30H4LuCy4TBk73H T8IL3OkeIECf69s+2m9mqzcdulIR7q3eXF/501MC9AsqiK0IJf088mqftRmD4frYzuNn 6RMA== X-Gm-Message-State: AOAM530ptIOoLrb6R9i4FO6NBvs0v9cu8EPI4Og5oSl02VxL+44xBvAp ADx1n5XRUsr4s+oayIF23IGunw== X-Google-Smtp-Source: ABdhPJxFtpM9WAPGm8FQMYthNTzcvKhjEuBhChhjL69jCzL7JLRMd+Y10QvkMwHW3XD+pajemzrPPg== X-Received: by 2002:adf:f70a:: with SMTP id r10mr4913956wrp.316.1622826769858; Fri, 04 Jun 2021 10:12:49 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 15/99] target/arm: move translate modules to tcg/ Date: Fri, 4 Jun 2021 16:51:48 +0100 Message-Id: <20210604155312.15902-16-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Alex Benn=C3=A9e --- target/arm/{ =3D> tcg}/translate-a64.h | 0 target/arm/{ =3D> tcg}/translate.h | 0 target/arm/{ =3D> tcg}/a32-uncond.decode | 0 target/arm/{ =3D> tcg}/a32.decode | 0 target/arm/{ =3D> tcg}/m-nocp.decode | 0 target/arm/{ =3D> tcg}/neon-dp.decode | 0 target/arm/{ =3D> tcg}/neon-ls.decode | 0 target/arm/{ =3D> tcg}/neon-shared.decode | 0 target/arm/{ =3D> tcg}/sve.decode | 0 target/arm/{ =3D> tcg}/t16.decode | 0 target/arm/{ =3D> tcg}/t32.decode | 0 target/arm/{ =3D> tcg}/vfp-uncond.decode | 0 target/arm/{ =3D> tcg}/vfp.decode | 0 target/arm/{ =3D> tcg}/translate-a64.c | 0 target/arm/{ =3D> tcg}/translate-m-nocp.c | 0 target/arm/{ =3D> tcg}/translate-neon.c | 0 target/arm/{ =3D> tcg}/translate-sve.c | 0 target/arm/{ =3D> tcg}/translate-vfp.c | 0 target/arm/{ =3D> tcg}/translate.c | 0 target/arm/meson.build | 23 ++------------------- target/arm/tcg/meson.build | 27 +++++++++++++++++++++++++ 21 files changed, 29 insertions(+), 21 deletions(-) rename target/arm/{ =3D> tcg}/translate-a64.h (100%) rename target/arm/{ =3D> tcg}/translate.h (100%) rename target/arm/{ =3D> tcg}/a32-uncond.decode (100%) rename target/arm/{ =3D> tcg}/a32.decode (100%) rename target/arm/{ =3D> tcg}/m-nocp.decode (100%) rename target/arm/{ =3D> tcg}/neon-dp.decode (100%) rename target/arm/{ =3D> tcg}/neon-ls.decode (100%) rename target/arm/{ =3D> tcg}/neon-shared.decode (100%) rename target/arm/{ =3D> tcg}/sve.decode (100%) rename target/arm/{ =3D> tcg}/t16.decode (100%) rename target/arm/{ =3D> tcg}/t32.decode (100%) rename target/arm/{ =3D> tcg}/vfp-uncond.decode (100%) rename target/arm/{ =3D> tcg}/vfp.decode (100%) rename target/arm/{ =3D> tcg}/translate-a64.c (100%) rename target/arm/{ =3D> tcg}/translate-m-nocp.c (100%) rename target/arm/{ =3D> tcg}/translate-neon.c (100%) rename target/arm/{ =3D> tcg}/translate-sve.c (100%) rename target/arm/{ =3D> tcg}/translate-vfp.c (100%) rename target/arm/{ =3D> tcg}/translate.c (100%) create mode 100644 target/arm/tcg/meson.build diff --git a/target/arm/translate-a64.h b/target/arm/tcg/translate-a64.h similarity index 100% rename from target/arm/translate-a64.h rename to target/arm/tcg/translate-a64.h diff --git a/target/arm/translate.h b/target/arm/tcg/translate.h similarity index 100% rename from target/arm/translate.h rename to target/arm/tcg/translate.h diff --git a/target/arm/a32-uncond.decode b/target/arm/tcg/a32-uncond.decode similarity index 100% rename from target/arm/a32-uncond.decode rename to target/arm/tcg/a32-uncond.decode diff --git a/target/arm/a32.decode b/target/arm/tcg/a32.decode similarity index 100% rename from target/arm/a32.decode rename to target/arm/tcg/a32.decode diff --git a/target/arm/m-nocp.decode b/target/arm/tcg/m-nocp.decode similarity index 100% rename from target/arm/m-nocp.decode rename to target/arm/tcg/m-nocp.decode diff --git a/target/arm/neon-dp.decode b/target/arm/tcg/neon-dp.decode similarity index 100% rename from target/arm/neon-dp.decode rename to target/arm/tcg/neon-dp.decode diff --git a/target/arm/neon-ls.decode b/target/arm/tcg/neon-ls.decode similarity index 100% rename from target/arm/neon-ls.decode rename to target/arm/tcg/neon-ls.decode diff --git a/target/arm/neon-shared.decode b/target/arm/tcg/neon-shared.dec= ode similarity index 100% rename from target/arm/neon-shared.decode rename to target/arm/tcg/neon-shared.decode diff --git a/target/arm/sve.decode b/target/arm/tcg/sve.decode similarity index 100% rename from target/arm/sve.decode rename to target/arm/tcg/sve.decode diff --git a/target/arm/t16.decode b/target/arm/tcg/t16.decode similarity index 100% rename from target/arm/t16.decode rename to target/arm/tcg/t16.decode diff --git a/target/arm/t32.decode b/target/arm/tcg/t32.decode similarity index 100% rename from target/arm/t32.decode rename to target/arm/tcg/t32.decode diff --git a/target/arm/vfp-uncond.decode b/target/arm/tcg/vfp-uncond.decode similarity index 100% rename from target/arm/vfp-uncond.decode rename to target/arm/tcg/vfp-uncond.decode diff --git a/target/arm/vfp.decode b/target/arm/tcg/vfp.decode similarity index 100% rename from target/arm/vfp.decode rename to target/arm/tcg/vfp.decode diff --git a/target/arm/translate-a64.c b/target/arm/tcg/translate-a64.c similarity index 100% rename from target/arm/translate-a64.c rename to target/arm/tcg/translate-a64.c diff --git a/target/arm/translate-m-nocp.c b/target/arm/tcg/translate-m-noc= p.c similarity index 100% rename from target/arm/translate-m-nocp.c rename to target/arm/tcg/translate-m-nocp.c diff --git a/target/arm/translate-neon.c b/target/arm/tcg/translate-neon.c similarity index 100% rename from target/arm/translate-neon.c rename to target/arm/tcg/translate-neon.c diff --git a/target/arm/translate-sve.c b/target/arm/tcg/translate-sve.c similarity index 100% rename from target/arm/translate-sve.c rename to target/arm/tcg/translate-sve.c diff --git a/target/arm/translate-vfp.c b/target/arm/tcg/translate-vfp.c similarity index 100% rename from target/arm/translate-vfp.c rename to target/arm/tcg/translate-vfp.c diff --git a/target/arm/translate.c b/target/arm/tcg/translate.c similarity index 100% rename from target/arm/translate.c rename to target/arm/tcg/translate.c diff --git a/target/arm/meson.build b/target/arm/meson.build index 6106d24665..229ec7fa11 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,19 +1,4 @@ -gen =3D [ - decodetree.process('sve.decode', extra_args: '--decode=3Ddisas_sve'), - decodetree.process('neon-shared.decode', extra_args: '--decode=3Ddisas_n= eon_shared'), - decodetree.process('neon-dp.decode', extra_args: '--decode=3Ddisas_neon_= dp'), - decodetree.process('neon-ls.decode', extra_args: '--decode=3Ddisas_neon_= ls'), - decodetree.process('vfp.decode', extra_args: '--decode=3Ddisas_vfp'), - decodetree.process('vfp-uncond.decode', extra_args: '--decode=3Ddisas_vf= p_uncond'), - decodetree.process('m-nocp.decode', extra_args: '--decode=3Ddisas_m_nocp= '), - decodetree.process('a32.decode', extra_args: '--static-decode=3Ddisas_a3= 2'), - decodetree.process('a32-uncond.decode', extra_args: '--static-decode=3Dd= isas_a32_uncond'), - decodetree.process('t32.decode', extra_args: '--static-decode=3Ddisas_t3= 2'), - decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-deco= de=3Ddisas_t16']), -] - arm_ss =3D ss.source_set() -arm_ss.add(gen) arm_ss.add(files( 'cpu.c', 'crypto_helper.c', @@ -25,10 +10,6 @@ arm_ss.add(files( 'neon_helper.c', 'op_helper.c', 'tlb_helper.c', - 'translate.c', - 'translate-m-nocp.c', - 'translate-neon.c', - 'translate-vfp.c', 'vec_helper.c', 'vfp_helper.c', 'cpu_tcg.c', @@ -44,8 +25,6 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'mte_helper.c', 'pauth_helper.c', 'sve_helper.c', - 'translate-a64.c', - 'translate-sve.c', )) =20 arm_softmmu_ss =3D ss.source_set() @@ -58,6 +37,8 @@ arm_softmmu_ss.add(files( )) arm_user_ss =3D ss.source_set() =20 +subdir('tcg') + target_arch +=3D {'arm': arm_ss} target_softmmu_arch +=3D {'arm': arm_softmmu_ss} target_user_arch +=3D {'arm': arm_user_ss} diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build new file mode 100644 index 0000000000..53a17ae6e6 --- /dev/null +++ b/target/arm/tcg/meson.build @@ -0,0 +1,27 @@ +gen =3D [ + decodetree.process('sve.decode', extra_args: '--decode=3Ddisas_sve'), + decodetree.process('neon-shared.decode', extra_args: '--decode=3Ddisas_n= eon_shared'), + decodetree.process('neon-dp.decode', extra_args: '--decode=3Ddisas_neon_= dp'), + decodetree.process('neon-ls.decode', extra_args: '--decode=3Ddisas_neon_= ls'), + decodetree.process('vfp.decode', extra_args: '--decode=3Ddisas_vfp'), + decodetree.process('vfp-uncond.decode', extra_args: '--decode=3Ddisas_vf= p_uncond'), + decodetree.process('m-nocp.decode', extra_args: '--decode=3Ddisas_m_nocp= '), + decodetree.process('a32.decode', extra_args: '--static-decode=3Ddisas_a3= 2'), + decodetree.process('a32-uncond.decode', extra_args: '--static-decode=3Dd= isas_a32_uncond'), + decodetree.process('t32.decode', extra_args: '--static-decode=3Ddisas_t3= 2'), + decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-deco= de=3Ddisas_t16']), +] + +arm_ss.add(gen) + +arm_ss.add(files( + 'translate.c', + 'translate-m-nocp.c', + 'translate-neon.c', + 'translate-vfp.c', +)) + +arm_ss.add(when: 'TARGET_AARCH64', if_true: files( + 'translate-a64.c', + 'translate-sve.c', +)) --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622824465; cv=none; d=zohomail.com; s=zohoarc; b=kWKFHv+G///aDbnpAd28n+3fpVACIKawYodAtwmYfzvs2CBI1WHdQiJ3GCE5UV6pYLdJJQOap1O8EAFS7WcPOPi5gbQhbbu6n6DO48Y7bslUpL5FCGwE0yJSCG51kZC7imvEh5aQJ24iDdxdNjTAmNGUfDFhEXyDQQIEbd3HHM8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622824465; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=A8D3uaI26zG4k8R6VTxbVafLxnun9Bh7qIkAIQc8YNo=; b=kZcWFhB8XcK8FkrAwgqTNTyIFtpfLhGdtd80swxkqQ4MGeftrHUab8EjwwDQodishuKMrKhnVbLk6GVPURH7L8Px0JJEXdfdMgSXM+o5d954xOJ4m5LQXqlWbCi7IBcvcEIYFpI4pAsJS4mMAT5vo+I2RBzcJUeQDscmV3vPpLg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16228244657921017.3390022139351; Fri, 4 Jun 2021 09:34:25 -0700 (PDT) Received: from localhost ([::1]:34580 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCm9-0001xa-0t for importer@patchew.org; Fri, 04 Jun 2021 12:34:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52014) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCRR-0003A6-PO for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:13:02 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:33721) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCRH-0003qy-Vh for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:13:01 -0400 Received: by mail-wr1-x431.google.com with SMTP id a20so9911918wrc.0 for ; Fri, 04 Jun 2021 09:12:51 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id q20sm8970286wrf.45.2021.06.04.09.12.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:12:43 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 0B6251FF9F; Fri, 4 Jun 2021 16:53:14 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A8D3uaI26zG4k8R6VTxbVafLxnun9Bh7qIkAIQc8YNo=; b=eEtNeKbN82V6LymS6u8H8344VDVMVL8QN6nYVyCLRFw+pxOjdwXE+BzSChELpacNoH Jlu+2i/mRKmX0VLxPJORs3EwDhmgAf3DTQRSFd7jRHUNiU53vK2Tgo8BpgNCDGNZGCod X5gK0sIwgg3eVtlK49AgnR9NocenTD4VSzw0shmHjQ2HFDw1lQuGgpcW2U/jkHomVLjH n3OnPN8O0G8YFGHRIlROK8jz0ihMnwgpUuS52AywAKrfbsf432YGk7hC2F07/Ib2tgGz dJYXNQ8OGwPA2Vd1DyNrFguJgsRwmN5RgCW4rnnkgh3QbQj4OnLgOr3Ih/fi0BtXjhC8 1xiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A8D3uaI26zG4k8R6VTxbVafLxnun9Bh7qIkAIQc8YNo=; b=U10KQ6lhn7i+QxZTP/D+rS1VGmprNNSQ7rNscKnfXJflnGI2sVWO2RQtYTcD8rokYH WemtnfWMJzJIWRRKC+w9RPmnxPzUvlJIkaZKIbMpxboUkvvVvJsOlG8Y054HXVYZm1/l S1XkscAn37By06ZyWPIbIBB9gxo8LMEBRUuPy5PW4CgYH7M+MiN/rir50ej+PgbmO1/R Q+zOUxF6X0qJqVNzZnldY1k1H0lKtf6dcDpaflQByXnGlOUalnPmySt2+nD+oTGILC1w FK9pHhrz7yWpEUMFgMbF/sq6ZTA5CvvPRJh2VoBg6eQGQvzNJqHIvQAqqSu0gbHPJxI4 xbxQ== X-Gm-Message-State: AOAM532qfmu5NyTqsS4U0tqA8eUPx392ER5e1CcvHYDfwjHaHCmwQ/NY u3d4srTCcUrC7mddXDc1X3YzRA== X-Google-Smtp-Source: ABdhPJymNEPS7GSfrGej3MD84/1SbHAL8trdGc6R4XiXEGIvX3wYpPqciTPIZt0aUX3o5A6YGFpeYA== X-Received: by 2002:adf:f68c:: with SMTP id v12mr4795061wrp.122.1622823170649; Fri, 04 Jun 2021 09:12:50 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 16/99] target/arm: move helpers to tcg/ Date: Fri, 4 Jun 2021 16:51:49 +0100 Message-Id: <20210604155312.15902-17-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Alex Benn=C3=A9e --- meson.build | 1 + target/arm/{ =3D> tcg}/op_addsub.h | 0 target/arm/tcg/trace.h | 1 + target/arm/{ =3D> tcg}/vec_internal.h | 0 target/arm/{ =3D> tcg}/crypto_helper.c | 0 target/arm/{ =3D> tcg}/debug_helper.c | 0 target/arm/{ =3D> tcg}/helper-a64.c | 0 target/arm/{ =3D> tcg}/helper.c | 0 target/arm/{ =3D> tcg}/iwmmxt_helper.c | 0 target/arm/{ =3D> tcg}/m_helper.c | 0 target/arm/{ =3D> tcg}/mte_helper.c | 0 target/arm/{ =3D> tcg}/neon_helper.c | 0 target/arm/{ =3D> tcg}/op_helper.c | 0 target/arm/{ =3D> tcg}/pauth_helper.c | 0 target/arm/{ =3D> tcg}/sve_helper.c | 0 target/arm/{ =3D> tcg}/tlb_helper.c | 0 target/arm/{ =3D> tcg}/vec_helper.c | 0 target/arm/{ =3D> tcg}/vfp_helper.c | 0 target/arm/meson.build | 14 -------------- target/arm/tcg/meson.build | 14 ++++++++++++++ target/arm/tcg/trace-events | 10 ++++++++++ target/arm/trace-events | 9 --------- 22 files changed, 26 insertions(+), 23 deletions(-) rename target/arm/{ =3D> tcg}/op_addsub.h (100%) create mode 100644 target/arm/tcg/trace.h rename target/arm/{ =3D> tcg}/vec_internal.h (100%) rename target/arm/{ =3D> tcg}/crypto_helper.c (100%) rename target/arm/{ =3D> tcg}/debug_helper.c (100%) rename target/arm/{ =3D> tcg}/helper-a64.c (100%) rename target/arm/{ =3D> tcg}/helper.c (100%) rename target/arm/{ =3D> tcg}/iwmmxt_helper.c (100%) rename target/arm/{ =3D> tcg}/m_helper.c (100%) rename target/arm/{ =3D> tcg}/mte_helper.c (100%) rename target/arm/{ =3D> tcg}/neon_helper.c (100%) rename target/arm/{ =3D> tcg}/op_helper.c (100%) rename target/arm/{ =3D> tcg}/pauth_helper.c (100%) rename target/arm/{ =3D> tcg}/sve_helper.c (100%) rename target/arm/{ =3D> tcg}/tlb_helper.c (100%) rename target/arm/{ =3D> tcg}/vec_helper.c (100%) rename target/arm/{ =3D> tcg}/vfp_helper.c (100%) create mode 100644 target/arm/tcg/trace-events diff --git a/meson.build b/meson.build index a876155969..eb22030571 100644 --- a/meson.build +++ b/meson.build @@ -1860,6 +1860,7 @@ if have_system or have_user 'accel/tcg', 'hw/core', 'target/arm', + 'target/arm/tcg', 'target/hppa', 'target/i386', 'target/i386/kvm', diff --git a/target/arm/op_addsub.h b/target/arm/tcg/op_addsub.h similarity index 100% rename from target/arm/op_addsub.h rename to target/arm/tcg/op_addsub.h diff --git a/target/arm/tcg/trace.h b/target/arm/tcg/trace.h new file mode 100644 index 0000000000..c6e89d018b --- /dev/null +++ b/target/arm/tcg/trace.h @@ -0,0 +1 @@ +#include "trace/trace-target_arm_tcg.h" diff --git a/target/arm/vec_internal.h b/target/arm/tcg/vec_internal.h similarity index 100% rename from target/arm/vec_internal.h rename to target/arm/tcg/vec_internal.h diff --git a/target/arm/crypto_helper.c b/target/arm/tcg/crypto_helper.c similarity index 100% rename from target/arm/crypto_helper.c rename to target/arm/tcg/crypto_helper.c diff --git a/target/arm/debug_helper.c b/target/arm/tcg/debug_helper.c similarity index 100% rename from target/arm/debug_helper.c rename to target/arm/tcg/debug_helper.c diff --git a/target/arm/helper-a64.c b/target/arm/tcg/helper-a64.c similarity index 100% rename from target/arm/helper-a64.c rename to target/arm/tcg/helper-a64.c diff --git a/target/arm/helper.c b/target/arm/tcg/helper.c similarity index 100% rename from target/arm/helper.c rename to target/arm/tcg/helper.c diff --git a/target/arm/iwmmxt_helper.c b/target/arm/tcg/iwmmxt_helper.c similarity index 100% rename from target/arm/iwmmxt_helper.c rename to target/arm/tcg/iwmmxt_helper.c diff --git a/target/arm/m_helper.c b/target/arm/tcg/m_helper.c similarity index 100% rename from target/arm/m_helper.c rename to target/arm/tcg/m_helper.c diff --git a/target/arm/mte_helper.c b/target/arm/tcg/mte_helper.c similarity index 100% rename from target/arm/mte_helper.c rename to target/arm/tcg/mte_helper.c diff --git a/target/arm/neon_helper.c b/target/arm/tcg/neon_helper.c similarity index 100% rename from target/arm/neon_helper.c rename to target/arm/tcg/neon_helper.c diff --git a/target/arm/op_helper.c b/target/arm/tcg/op_helper.c similarity index 100% rename from target/arm/op_helper.c rename to target/arm/tcg/op_helper.c diff --git a/target/arm/pauth_helper.c b/target/arm/tcg/pauth_helper.c similarity index 100% rename from target/arm/pauth_helper.c rename to target/arm/tcg/pauth_helper.c diff --git a/target/arm/sve_helper.c b/target/arm/tcg/sve_helper.c similarity index 100% rename from target/arm/sve_helper.c rename to target/arm/tcg/sve_helper.c diff --git a/target/arm/tlb_helper.c b/target/arm/tcg/tlb_helper.c similarity index 100% rename from target/arm/tlb_helper.c rename to target/arm/tcg/tlb_helper.c diff --git a/target/arm/vec_helper.c b/target/arm/tcg/vec_helper.c similarity index 100% rename from target/arm/vec_helper.c rename to target/arm/tcg/vec_helper.c diff --git a/target/arm/vfp_helper.c b/target/arm/tcg/vfp_helper.c similarity index 100% rename from target/arm/vfp_helper.c rename to target/arm/tcg/vfp_helper.c diff --git a/target/arm/meson.build b/target/arm/meson.build index 229ec7fa11..0172937b40 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,17 +1,7 @@ arm_ss =3D ss.source_set() arm_ss.add(files( 'cpu.c', - 'crypto_helper.c', - 'debug_helper.c', 'gdbstub.c', - 'helper.c', - 'iwmmxt_helper.c', - 'm_helper.c', - 'neon_helper.c', - 'op_helper.c', - 'tlb_helper.c', - 'vec_helper.c', - 'vfp_helper.c', 'cpu_tcg.c', )) arm_ss.add(zlib) @@ -21,10 +11,6 @@ arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', '= kvm64.c'), if_false: fil arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'cpu64.c', 'gdbstub64.c', - 'helper-a64.c', - 'mte_helper.c', - 'pauth_helper.c', - 'sve_helper.c', )) =20 arm_softmmu_ss =3D ss.source_set() diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 53a17ae6e6..b3c9d808f5 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -19,9 +19,23 @@ arm_ss.add(files( 'translate-m-nocp.c', 'translate-neon.c', 'translate-vfp.c', + 'helper.c', + 'iwmmxt_helper.c', + 'm_helper.c', + 'neon_helper.c', + 'op_helper.c', + 'tlb_helper.c', + 'vec_helper.c', + 'vfp_helper.c', + 'crypto_helper.c', + 'debug_helper.c', )) =20 arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'translate-a64.c', 'translate-sve.c', + 'helper-a64.c', + 'mte_helper.c', + 'pauth_helper.c', + 'sve_helper.c', )) diff --git a/target/arm/tcg/trace-events b/target/arm/tcg/trace-events new file mode 100644 index 0000000000..755373a5b1 --- /dev/null +++ b/target/arm/tcg/trace-events @@ -0,0 +1,10 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# helper.c +arm_gt_recalc(int timer, int irqstate, uint64_t nexttick) "gt recalc: time= r %d irqstate %d next tick 0x%" PRIx64 +arm_gt_recalc_disabled(int timer) "gt recalc: timer %d irqstate 0 timer di= sabled" +arm_gt_cval_write(int timer, uint64_t value) "gt_cval_write: timer %d valu= e 0x%" PRIx64 +arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write: timer %d valu= e 0x%" PRIx64 +arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value = 0x%" PRIx64 +arm_gt_imask_toggle(int timer, int irqstate) "gt_ctl_write: timer %d IMASK= toggle, new irqstate %d" +arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value 0x%" PRIx64 diff --git a/target/arm/trace-events b/target/arm/trace-events index 2a0ba7bffc..23af2d710e 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -1,13 +1,4 @@ # See docs/devel/tracing.rst for syntax documentation. =20 -# helper.c -arm_gt_recalc(int timer, int irqstate, uint64_t nexttick) "gt recalc: time= r %d irqstate %d next tick 0x%" PRIx64 -arm_gt_recalc_disabled(int timer) "gt recalc: timer %d irqstate 0 timer di= sabled" -arm_gt_cval_write(int timer, uint64_t value) "gt_cval_write: timer %d valu= e 0x%" PRIx64 -arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write: timer %d valu= e 0x%" PRIx64 -arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value = 0x%" PRIx64 -arm_gt_imask_toggle(int timer, int irqstate) "gt_ctl_write: timer %d IMASK= toggle, new irqstate %d" -arm_gt_cntvoff_write(uint64_t value) "gt_cntvoff_write: value 0x%" PRIx64 - # kvm.c kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622831294; cv=none; d=zohomail.com; s=zohoarc; b=FWI01wukNfuOV4iIXytqUAflF+yeRuba4vhY3kX4HxtrJqjoHaERJJJKoExkvPAMldH099qGMuSUSG0FSm1UbJ2/zm71fxvY7HU5GhIJA+ZXXFMOWeTfwzC/YngzBzmKah90UHodxZg7kFu5hD9gyody2N7akCuao6sHJV9CYQY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622831294; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pO+1XQtifTxu7QLeU1fB8+5lGSSsnzVhaAsD9VqsQLM=; b=NNU+bnr5hhm/AqszptxanpSdYNvZWc/KKWGfY/FdsZadXgK2QYZ2cFiTTIPu4WvPd5RJrIopJ7ZTsEGGZhbdhmcwZCBypoE9cafkg3JCf1jrXEVvllI8fD+CLmizoYfBmuUNIIljYiRTr0pFJ4JwazEo/8O0/1sh+m91DtMxSfs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622831294345933.3679331484103; Fri, 4 Jun 2021 11:28:14 -0700 (PDT) Received: from localhost ([::1]:56522 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpEYG-0008FO-Po for importer@patchew.org; Fri, 04 Jun 2021 14:28:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42482) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpETA-0001Lk-MU for qemu-devel@nongnu.org; Fri, 04 Jun 2021 14:22:56 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:43684) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpET4-0000QQ-5O for qemu-devel@nongnu.org; Fri, 04 Jun 2021 14:22:56 -0400 Received: by mail-wr1-x432.google.com with SMTP id u7so4751527wrs.10 for ; Fri, 04 Jun 2021 11:22:49 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id h9sm6140581wmb.35.2021.06.04.11.22.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 11:22:45 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 2040E1FFA5; Fri, 4 Jun 2021 16:53:14 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pO+1XQtifTxu7QLeU1fB8+5lGSSsnzVhaAsD9VqsQLM=; b=hDzhEkN9l5IAgwG6XCIfkza7/Ukj1IimO84reBGPbqru067srecpjGqotATAonFgcd /MCE5OTwRgWScvqQeIhTiD5DimX3fVHlXPBEyTJ5r/Qm+loxUj5zQWqiS7j9+ODpliT6 f1GaA5ByzbM/N/ENR0VJ80DQO4lzI7vNyQgbCqV7Ou1rOZ0nd8s6uXqaISM2KqITV+9f GrG5vE2DDoxfrI/0qXt5uDH1SqZw1idC1KeWWPvy9wB0+Uu6tLqVclltQPO8L01xgscz oJWlp2bVQEFAHMvkHynRCrep1udfBexqPwGZttqq6fu/Pif7YaprXLaTbjWNfaF+Ii+D nhjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pO+1XQtifTxu7QLeU1fB8+5lGSSsnzVhaAsD9VqsQLM=; b=QTA+7paUJaC5byZ/lf/eyoPUC8Rl1LH8/rwy0JxywY4Pcs/QfmCL1DhTepdlvQUave i4q+rhbr3hB2BN8/AJuId08dJmjQI+J+HiA+IK5QPVq/ogd0CCjaRNwshTSH8jidNq/m uCyKII4yhoBQufUB5xAYB/gim0r0fmlbcrdSrRtTDk02vXDr22P1fHBmjOzPtU/BJHi8 gTWkaBx+9moeyQ5wIOKPqSPtIqsFlXLxXPCzB8NUS4ixVBJfXNxEozmPlJmoqtDPWkR6 72/vjxo6xfFdxdwjto2r+izr1qazU0gBKt13/U+7WyAX3MjDMP6U2OEWRDEHFBw8zCJJ VH0A== X-Gm-Message-State: AOAM532gxe/OaenxPcOnGARcoMHRLJVLpBN5gyhCxcsHeYHaM9Dz8rko HS9hJPSnR9IoX/6DdNGDtXs8kA== X-Google-Smtp-Source: ABdhPJwxUzDUCu+JuDbQ/v2yjq7fR48+UEALA6Mdkjo0VkGe5rXf7u2YmQAkeV2hgnWGuu7C/k5BNw== X-Received: by 2002:a5d:44d2:: with SMTP id z18mr5187039wrr.358.1622830968859; Fri, 04 Jun 2021 11:22:48 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 17/99] arm: tcg: only build under CONFIG_TCG Date: Fri, 4 Jun 2021 16:51:50 +0100 Message-Id: <20210604155312.15902-18-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/meson.build | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index b3c9d808f5..04b94a3bfb 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -12,9 +12,9 @@ gen =3D [ decodetree.process('t16.decode', extra_args: ['-w', '16', '--static-deco= de=3Ddisas_t16']), ] =20 -arm_ss.add(gen) +arm_ss.add(when: 'CONFIG_TCG', if_true: gen) =20 -arm_ss.add(files( +arm_ss.add(when: 'CONFIG_TCG', if_true: files( 'translate.c', 'translate-m-nocp.c', 'translate-neon.c', @@ -31,7 +31,7 @@ arm_ss.add(files( 'debug_helper.c', )) =20 -arm_ss.add(when: 'TARGET_AARCH64', if_true: files( +arm_ss.add(when: ['TARGET_AARCH64','CONFIG_TCG'], if_true: files( 'translate-a64.c', 'translate-sve.c', 'helper-a64.c', --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622824456; cv=none; d=zohomail.com; s=zohoarc; b=ksExyhZkYEuoos2s6MdGk7nVpTntfSb+pnEzKALaNWYQPUfeOZc7af5BiA3hTPCRu6UG4Ub63+PFVhymfRVVDlU1VFq2Kk5oQ7jKX2bf/+nydxVRDyKRwV2Jsie2X/JGRKtbKI2m5LNpNgVPUneOOZ0yr60eVnVhZouJwrHEVuY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622824456; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=F0Zjuqp+eDe0I9dgRDfCqEr+Z2SzjMw09N7y7MQfjjk=; b=Kgjj3dNe+lxAIUHK354wNbwn4sWLH3aUWcVBJrGkD+7bUexBThYRr3wpcrd4ErF2YvLkhWdpct67333ARe/wCuoBq4tBH2/tf4WzBiPQqqzW2PWN8irO5ZcNvLqxzqfdpRQ3z8k7V6TPmDYdY/4MDKkofj2HJB8HM0bo4nq2xSc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622824456686271.952756758256; Fri, 4 Jun 2021 09:34:16 -0700 (PDT) Received: from localhost ([::1]:34256 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpClz-0001kH-6R for importer@patchew.org; Fri, 04 Jun 2021 12:34:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48644) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCI7-0008TA-19 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:24 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:55095) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHi-0005t2-5M for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:22 -0400 Received: by mail-wm1-x32f.google.com with SMTP id o127so5677549wmo.4 for ; Fri, 04 Jun 2021 09:02:57 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id z188sm6250138wme.38.2021.06.04.09.02.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:53 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 38A711FFA6; Fri, 4 Jun 2021 16:53:14 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F0Zjuqp+eDe0I9dgRDfCqEr+Z2SzjMw09N7y7MQfjjk=; b=KoszT2d3OrEjU0HDXn5fRCMR3S1GCj6RVvYfry+e6n/8j96tISROd322ddLf2xL9Ks +FATjhE6Q9K3CXnsLg3atwAkjuSKV8l8zj7c5X36YeiudAJ6VhLcANszRsG3koq80d3m d7MC1D56rCRhSJfQo327AHvaPQ4uup6XM8+0lm0Shhuv3hNiUdorBBugq1vjzt6AgdtW vo++L0JTFtGkCVGgs2PqJMLrEgU7wLB6mB1zU1kH6N+ZJh6V9E4eOwsMWcjfLtWFBM66 YI5RIxnM0VCiXz5XsuVXW+CgCsO5eRJAtw7iOi2WssadwuzSwTsTQzOZg2Yw7+mrL3Xw Kezg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F0Zjuqp+eDe0I9dgRDfCqEr+Z2SzjMw09N7y7MQfjjk=; b=GJh1IV8bOT/ei2hezQsyk5HLTJOGGEJRJslZ/OgVWK7ntpnnsE/GcnKxOlJXXrcbVz eNdnP/Sx24kYOBEiZ0DE6GQCWPmALKbngeEaSF17uYYaWP26Xe7pzue5sxrSUCraxIu7 aQZDZ0bADJSs4HV6AV/URiik0rEc3ikfMzTeLOopYLOG/0YkrsFolI7UADh4Dx5hsOBc U+EpzGxDzV7w2hYOG4lTtVrRic5mmLwyZp9HZZYx2B/CqSxnja3Pl2bCUo/hI2nCZ4Yo OyFvgyEW7LV3J6iDCtoy+osoaivbrFhNJRogEphpCvP/tgLLbchsor79uVFHP/uZ/YHQ aUfQ== X-Gm-Message-State: AOAM532o9xk3AKskrivhFtCt4UdH/lU38HfKLCVxA55sTv8vbiqnvezv wtVW8cKcluTbo9rmcXyRE6fkdg== X-Google-Smtp-Source: ABdhPJyTuLcSoC2UHlQLl981MANc0GQrFgEh63niPLzrEORvSJOYuAnzEPl9pBrNAnsdrBXLgmjoBA== X-Received: by 2002:a7b:c7c5:: with SMTP id z5mr4307814wmk.77.1622822576889; Fri, 04 Jun 2021 09:02:56 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 18/99] target/arm: tcg: add sysemu and user subdirs Date: Fri, 4 Jun 2021 16:51:51 +0100 Message-Id: <20210604155312.15902-19-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/meson.build | 3 +++ target/arm/tcg/sysemu/meson.build | 2 ++ target/arm/tcg/user/meson.build | 2 ++ 3 files changed, 7 insertions(+) create mode 100644 target/arm/tcg/sysemu/meson.build create mode 100644 target/arm/tcg/user/meson.build diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 04b94a3bfb..3503ad96c8 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -39,3 +39,6 @@ arm_ss.add(when: ['TARGET_AARCH64','CONFIG_TCG'], if_true= : files( 'pauth_helper.c', 'sve_helper.c', )) + +subdir('user') +subdir('sysemu') diff --git a/target/arm/tcg/sysemu/meson.build b/target/arm/tcg/sysemu/meso= n.build new file mode 100644 index 0000000000..726387b0b3 --- /dev/null +++ b/target/arm/tcg/sysemu/meson.build @@ -0,0 +1,2 @@ +arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( +)) diff --git a/target/arm/tcg/user/meson.build b/target/arm/tcg/user/meson.bu= ild new file mode 100644 index 0000000000..7af3311190 --- /dev/null +++ b/target/arm/tcg/user/meson.build @@ -0,0 +1,2 @@ +arm_user_ss.add(when: 'CONFIG_TCG', if_true: files( +)) --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622824129; cv=none; d=zohomail.com; s=zohoarc; b=LTs29kgd37Zvl/V13idObZuNocTQ1XovNhZP5qVO+cNttt8wy9jJ9JtYQqGvc/3Aa6kCWg6Dbyl1VXSbQlwWByHtRE66yZc3JWDeW3+Zxsa3sOBdEwzIfxs8an14KD+2s9bdjLHfAtXlZAK6vzLHnR9Zs3kv7W+rlN8dkIvz69M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622824129; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DIpMxNA8MOA687Rs0g/qEVI6kRJgN+IDZwl5dPu1YWM=; b=HpBYDyBGKHUlUrx6s2oPe/HVhdGnVQpEOwYkXDHBRuNzdmYk4g4deL1gb/m86ieIDEfCNhE4/8VVUSwfdCsQ3eM92ERfwH9Q26xC7plB0KolwBT4CIQ+jAatWXXAXNVTWgQBEbDlY2xpRWB4lRy0N8/1LtalwKW8gipcfjLRdp0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622824129752303.75724646870447; Fri, 4 Jun 2021 09:28:49 -0700 (PDT) Received: from localhost ([::1]:44774 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCgi-0006US-OU for importer@patchew.org; Fri, 04 Jun 2021 12:28:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48278) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCHd-0007pS-Rg for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:02:53 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:39427) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHR-0005iE-Uu for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:02:53 -0400 Received: by mail-wm1-x336.google.com with SMTP id l18-20020a1ced120000b029014c1adff1edso8219971wmh.4 for ; Fri, 04 Jun 2021 09:02:41 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id j9sm3077307wrs.49.2021.06.04.09.02.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:37 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 592081FFA9; Fri, 4 Jun 2021 16:53:14 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DIpMxNA8MOA687Rs0g/qEVI6kRJgN+IDZwl5dPu1YWM=; b=Aqs95qaNnWQ1Zy0NUQV4PhIa2U+yHeCLteA1hh5kgjzTwMzqaoMhbO46Umssy3R8fP GDbQmGQsjMeaosS8frAwyVKKpt1ThuJs6m1SAdmo3BM5ybPT8ZiGXEYw/y/zbZRTPKGi 2qrv/htA+Pr2qrKXUfHI/Z38rlCmpClo4nGrOyDj3QLjsThodQyAHjSKUac3jyAEy8xi cALIRyvsTtUzv7uKcXnMhZBerhbkabqqlEmexbrRApPZ/PsZc0iWGR/1289TJl2EZ0b0 EwPfyMwzTXWXyiam7oauh2WzUc1DILDOZEYs3bVdt7YtW6dYI7SvCZSv9ck13H8zVzkZ FH1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DIpMxNA8MOA687Rs0g/qEVI6kRJgN+IDZwl5dPu1YWM=; b=DDSRLdHmM+ejQHUtUfjDwDLaFLqZDQzxYpDPQ4JDN5NPt05YIf7diy1SXW/v3JIEDg jlQpj9xkgZpCb1Fd6I5weA7Xe6IeALhpgfLf+aH54tX2f6wA87+amL/vJQeWQF5+3DbE 5Z/e3IzsrksWxDfjZx3EwdH0alGqNO3JNw9hjZN3xiM1SxL5Ayc4UtaYv2JPpRS62x8r MCCO5USoUNGRyTxH71JrIDdVLFWE0hYFnn6TyQAZ1n/KqChtzinEy8MPoHkH1IJvm1CN /6hRbN+Ajn/FXMGs44yTpYAP33/gPmKL/3xXwAiX72v3fxZVO2wk3lVgSGefM14tAp++ /Ynw== X-Gm-Message-State: AOAM5328kvIb4weRKFfdJ+ouafQ0Gj34kDb8QSeZUsWuzKUSDS+iC5mh a43+nKOI9SfSa02E44IQafxsNnlohE1ZIQ== X-Google-Smtp-Source: ABdhPJwgH63iTNyqdkoqB3S2GSH93SZdyLU23+cIMtIPX+5jSnrcoJ2g2YPmYthYAzSvCs5XjH8LHw== X-Received: by 2002:a05:600c:35c8:: with SMTP id r8mr3261544wmq.168.1622822560148; Fri, 04 Jun 2021 09:02:40 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 19/99] target/arm: tcg: split mte_helper user-only and sysemu code Date: Fri, 4 Jun 2021 16:51:52 +0100 Message-Id: <20210604155312.15902-20-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana allocation_tag_mem has a different implementation for user-only and sysemu, so move the two implementations into the dedicated subdirs. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/mte_helper.h | 53 ++++++++ target/arm/tcg/mte_helper.c | 191 +---------------------------- target/arm/tcg/sysemu/mte_helper.c | 159 ++++++++++++++++++++++++ target/arm/tcg/user/mte_helper.c | 57 +++++++++ target/arm/tcg/sysemu/meson.build | 1 + target/arm/tcg/user/meson.build | 1 + 6 files changed, 272 insertions(+), 190 deletions(-) create mode 100644 target/arm/tcg/mte_helper.h create mode 100644 target/arm/tcg/sysemu/mte_helper.c create mode 100644 target/arm/tcg/user/mte_helper.c diff --git a/target/arm/tcg/mte_helper.h b/target/arm/tcg/mte_helper.h new file mode 100644 index 0000000000..29db1ad9fc --- /dev/null +++ b/target/arm/tcg/mte_helper.h @@ -0,0 +1,53 @@ +/* + * ARM v8.5-MemTag Operations + * + * Copyright (c) 2020 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef MTE_HELPER_H +#define MTE_HELPER_H + +/** + * allocation_tag_mem: + * @env: the cpu environment + * @ptr_mmu_idx: the addressing regime to use for the virtual address + * @ptr: the virtual address for which to look up tag memory + * @ptr_access: the access to use for the virtual address + * @ptr_size: the number of bytes in the normal memory access + * @tag_access: the access to use for the tag memory + * @tag_size: the number of bytes in the tag memory access + * @ra: the return address for exception handling + * + * Our tag memory is formatted as a sequence of little-endian nibbles. + * That is, the byte at (addr >> (LOG2_TAG_GRANULE + 1)) contains two + * tags, with the tag at [3:0] for the lower addr and the tag at [7:4] + * for the higher addr. + * + * Here, resolve the physical address from the virtual address, and return + * a pointer to the corresponding tag byte. Exit with exception if the + * virtual address is not accessible for @ptr_access. + * + * The @ptr_size and @tag_size values may not have an obvious relation + * due to the alignment of @ptr, and the number of tag checks required. + * + * If there is no tag storage corresponding to @ptr, return NULL. + */ +uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, + uint64_t ptr, MMUAccessType ptr_access, + int ptr_size, MMUAccessType tag_access, + int tag_size, uintptr_t ra); + +#endif /* MTE_HELPER_H */ diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index a6fccc6e69..7cc9b31fb0 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -26,7 +26,7 @@ #include "exec/helper-proto.h" #include "qapi/error.h" #include "qemu/guest-random.h" - +#include "tcg/mte_helper.h" =20 static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) { @@ -47,195 +47,6 @@ static int choose_nonexcluded_tag(int tag, int offset, = uint16_t exclude) return tag; } =20 -/** - * allocation_tag_mem: - * @env: the cpu environment - * @ptr_mmu_idx: the addressing regime to use for the virtual address - * @ptr: the virtual address for which to look up tag memory - * @ptr_access: the access to use for the virtual address - * @ptr_size: the number of bytes in the normal memory access - * @tag_access: the access to use for the tag memory - * @tag_size: the number of bytes in the tag memory access - * @ra: the return address for exception handling - * - * Our tag memory is formatted as a sequence of little-endian nibbles. - * That is, the byte at (addr >> (LOG2_TAG_GRANULE + 1)) contains two - * tags, with the tag at [3:0] for the lower addr and the tag at [7:4] - * for the higher addr. - * - * Here, resolve the physical address from the virtual address, and return - * a pointer to the corresponding tag byte. Exit with exception if the - * virtual address is not accessible for @ptr_access. - * - * The @ptr_size and @tag_size values may not have an obvious relation - * due to the alignment of @ptr, and the number of tag checks required. - * - * If there is no tag storage corresponding to @ptr, return NULL. - */ -static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, - uint64_t ptr, MMUAccessType ptr_access, - int ptr_size, MMUAccessType tag_access, - int tag_size, uintptr_t ra) -{ -#ifdef CONFIG_USER_ONLY - uint64_t clean_ptr =3D useronly_clean_ptr(ptr); - int flags =3D page_get_flags(clean_ptr); - uint8_t *tags; - uintptr_t index; - - if (!(flags & (ptr_access =3D=3D MMU_DATA_STORE ? PAGE_WRITE_ORG : PAG= E_READ))) { - /* SIGSEGV */ - arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access, - ptr_mmu_idx, false, ra); - g_assert_not_reached(); - } - - /* Require both MAP_ANON and PROT_MTE for the page. */ - if (!(flags & PAGE_ANON) || !(flags & PAGE_MTE)) { - return NULL; - } - - tags =3D page_get_target_data(clean_ptr); - if (tags =3D=3D NULL) { - size_t alloc_size =3D TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); - tags =3D page_alloc_target_data(clean_ptr, alloc_size); - assert(tags !=3D NULL); - } - - index =3D extract32(ptr, LOG2_TAG_GRANULE + 1, - TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); - return tags + index; -#else - uintptr_t index; - CPUIOTLBEntry *iotlbentry; - int in_page, flags; - ram_addr_t ptr_ra; - hwaddr ptr_paddr, tag_paddr, xlat; - MemoryRegion *mr; - ARMASIdx tag_asi; - AddressSpace *tag_as; - void *host; - - /* - * Probe the first byte of the virtual address. This raises an - * exception for inaccessible pages, and resolves the virtual address - * into the softmmu tlb. - * - * When RA =3D=3D 0, this is for mte_probe. The page is expected to be - * valid. Indicate to probe_access_flags no-fault, then assert that - * we received a valid page. - */ - flags =3D probe_access_flags(env, ptr, ptr_access, ptr_mmu_idx, - ra =3D=3D 0, &host, ra); - assert(!(flags & TLB_INVALID_MASK)); - - /* - * Find the iotlbentry for ptr. This *must* be present in the TLB - * because we just found the mapping. - * TODO: Perhaps there should be a cputlb helper that returns a - * matching tlb entry + iotlb entry. - */ - index =3D tlb_index(env, ptr_mmu_idx, ptr); -# ifdef CONFIG_DEBUG_TCG - { - CPUTLBEntry *entry =3D tlb_entry(env, ptr_mmu_idx, ptr); - target_ulong comparator =3D (ptr_access =3D=3D MMU_DATA_LOAD - ? entry->addr_read - : tlb_addr_write(entry)); - g_assert(tlb_hit(comparator, ptr)); - } -# endif - iotlbentry =3D &env_tlb(env)->d[ptr_mmu_idx].iotlb[index]; - - /* If the virtual page MemAttr !=3D Tagged, access unchecked. */ - if (!arm_tlb_mte_tagged(&iotlbentry->attrs)) { - return NULL; - } - - /* - * If not backed by host ram, there is no tag storage: access unchecke= d. - * This is probably a guest os bug though, so log it. - */ - if (unlikely(flags & TLB_MMIO)) { - qemu_log_mask(LOG_GUEST_ERROR, - "Page @ 0x%" PRIx64 " indicates Tagged Normal memory= " - "but is not backed by host ram\n", ptr); - return NULL; - } - - /* - * The Normal memory access can extend to the next page. E.g. a single - * 8-byte access to the last byte of a page will check only the last - * tag on the first page. - * Any page access exception has priority over tag check exception. - */ - in_page =3D -(ptr | TARGET_PAGE_MASK); - if (unlikely(ptr_size > in_page)) { - void *ignore; - flags |=3D probe_access_flags(env, ptr + in_page, ptr_access, - ptr_mmu_idx, ra =3D=3D 0, &ignore, ra); - assert(!(flags & TLB_INVALID_MASK)); - } - - /* Any debug exception has priority over a tag check exception. */ - if (unlikely(flags & TLB_WATCHPOINT)) { - int wp =3D ptr_access =3D=3D MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_= WRITE; - assert(ra !=3D 0); - cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, - iotlbentry->attrs, wp, ra); - } - - /* - * Find the physical address within the normal mem space. - * The memory region lookup must succeed because TLB_MMIO was - * not set in the cputlb lookup above. - */ - mr =3D memory_region_from_host(host, &ptr_ra); - tcg_debug_assert(mr !=3D NULL); - tcg_debug_assert(memory_region_is_ram(mr)); - ptr_paddr =3D ptr_ra; - do { - ptr_paddr +=3D mr->addr; - mr =3D mr->container; - } while (mr); - - /* Convert to the physical address in tag space. */ - tag_paddr =3D ptr_paddr >> (LOG2_TAG_GRANULE + 1); - - /* Look up the address in tag space. */ - tag_asi =3D iotlbentry->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; - tag_as =3D cpu_get_address_space(env_cpu(env), tag_asi); - mr =3D address_space_translate(tag_as, tag_paddr, &xlat, NULL, - tag_access =3D=3D MMU_DATA_STORE, - iotlbentry->attrs); - - /* - * Note that @mr will never be NULL. If there is nothing in the addre= ss - * space at @tag_paddr, the translation will return the unallocated me= mory - * region. For our purposes, the result must be ram. - */ - if (unlikely(!memory_region_is_ram(mr))) { - /* ??? Failure is a board configuration error. */ - qemu_log_mask(LOG_UNIMP, - "Tag Memory @ 0x%" HWADDR_PRIx " not found for " - "Normal Memory @ 0x%" HWADDR_PRIx "\n", - tag_paddr, ptr_paddr); - return NULL; - } - - /* - * Ensure the tag memory is dirty on write, for migration. - * Tag memory can never contain code or display memory (vga). - */ - if (tag_access =3D=3D MMU_DATA_STORE) { - ram_addr_t tag_ra =3D memory_region_get_ram_addr(mr) + xlat; - cpu_physical_memory_set_dirty_flag(tag_ra, DIRTY_MEMORY_MIGRATION); - } - - return memory_region_get_ram_ptr(mr) + xlat; -#endif -} - uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) { uint16_t exclude =3D extract32(rm | env->cp15.gcr_el1, 0, 16); diff --git a/target/arm/tcg/sysemu/mte_helper.c b/target/arm/tcg/sysemu/mte= _helper.c new file mode 100644 index 0000000000..e333324437 --- /dev/null +++ b/target/arm/tcg/sysemu/mte_helper.c @@ -0,0 +1,159 @@ +/* + * ARM v8.5-MemTag Operations - System Emulation + * + * Copyright (c) 2020 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "exec/ram_addr.h" +#include "tcg/mte_helper.h" + +uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, + uint64_t ptr, MMUAccessType ptr_access, + int ptr_size, MMUAccessType tag_access, + int tag_size, uintptr_t ra) +{ + uintptr_t index; + CPUIOTLBEntry *iotlbentry; + int in_page, flags; + ram_addr_t ptr_ra; + hwaddr ptr_paddr, tag_paddr, xlat; + MemoryRegion *mr; + ARMASIdx tag_asi; + AddressSpace *tag_as; + void *host; + + /* + * Probe the first byte of the virtual address. This raises an + * exception for inaccessible pages, and resolves the virtual address + * into the softmmu tlb. + * + * When RA =3D=3D 0, this is for mte_probe. The page is expected to be + * valid. Indicate to probe_access_flags no-fault, then assert that + * we received a valid page. + */ + flags =3D probe_access_flags(env, ptr, ptr_access, ptr_mmu_idx, + ra =3D=3D 0, &host, ra); + assert(!(flags & TLB_INVALID_MASK)); + + /* + * Find the iotlbentry for ptr. This *must* be present in the TLB + * because we just found the mapping. + * TODO: Perhaps there should be a cputlb helper that returns a + * matching tlb entry + iotlb entry. + */ + index =3D tlb_index(env, ptr_mmu_idx, ptr); +# ifdef CONFIG_DEBUG_TCG + { + CPUTLBEntry *entry =3D tlb_entry(env, ptr_mmu_idx, ptr); + target_ulong comparator =3D (ptr_access =3D=3D MMU_DATA_LOAD + ? entry->addr_read + : tlb_addr_write(entry)); + g_assert(tlb_hit(comparator, ptr)); + } +# endif + iotlbentry =3D &env_tlb(env)->d[ptr_mmu_idx].iotlb[index]; + + /* If the virtual page MemAttr !=3D Tagged, access unchecked. */ + if (!arm_tlb_mte_tagged(&iotlbentry->attrs)) { + return NULL; + } + + /* + * If not backed by host ram, there is no tag storage: access unchecke= d. + * This is probably a guest os bug though, so log it. + */ + if (unlikely(flags & TLB_MMIO)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Page @ 0x%" PRIx64 " indicates Tagged Normal memory= " + "but is not backed by host ram\n", ptr); + return NULL; + } + + /* + * The Normal memory access can extend to the next page. E.g. a single + * 8-byte access to the last byte of a page will check only the last + * tag on the first page. + * Any page access exception has priority over tag check exception. + */ + in_page =3D -(ptr | TARGET_PAGE_MASK); + if (unlikely(ptr_size > in_page)) { + void *ignore; + flags |=3D probe_access_flags(env, ptr + in_page, ptr_access, + ptr_mmu_idx, ra =3D=3D 0, &ignore, ra); + assert(!(flags & TLB_INVALID_MASK)); + } + + /* Any debug exception has priority over a tag check exception. */ + if (unlikely(flags & TLB_WATCHPOINT)) { + int wp =3D ptr_access =3D=3D MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_= WRITE; + assert(ra !=3D 0); + cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, + iotlbentry->attrs, wp, ra); + } + + /* + * Find the physical address within the normal mem space. + * The memory region lookup must succeed because TLB_MMIO was + * not set in the cputlb lookup above. + */ + mr =3D memory_region_from_host(host, &ptr_ra); + tcg_debug_assert(mr !=3D NULL); + tcg_debug_assert(memory_region_is_ram(mr)); + ptr_paddr =3D ptr_ra; + do { + ptr_paddr +=3D mr->addr; + mr =3D mr->container; + } while (mr); + + /* Convert to the physical address in tag space. */ + tag_paddr =3D ptr_paddr >> (LOG2_TAG_GRANULE + 1); + + /* Look up the address in tag space. */ + tag_asi =3D iotlbentry->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; + tag_as =3D cpu_get_address_space(env_cpu(env), tag_asi); + mr =3D address_space_translate(tag_as, tag_paddr, &xlat, NULL, + tag_access =3D=3D MMU_DATA_STORE, + iotlbentry->attrs); + + /* + * Note that @mr will never be NULL. If there is nothing in the addre= ss + * space at @tag_paddr, the translation will return the unallocated me= mory + * region. For our purposes, the result must be ram. + */ + if (unlikely(!memory_region_is_ram(mr))) { + /* ??? Failure is a board configuration error. */ + qemu_log_mask(LOG_UNIMP, + "Tag Memory @ 0x%" HWADDR_PRIx " not found for " + "Normal Memory @ 0x%" HWADDR_PRIx "\n", + tag_paddr, ptr_paddr); + return NULL; + } + + /* + * Ensure the tag memory is dirty on write, for migration. + * Tag memory can never contain code or display memory (vga). + */ + if (tag_access =3D=3D MMU_DATA_STORE) { + ram_addr_t tag_ra =3D memory_region_get_ram_addr(mr) + xlat; + cpu_physical_memory_set_dirty_flag(tag_ra, DIRTY_MEMORY_MIGRATION); + } + + return memory_region_get_ram_ptr(mr) + xlat; +} diff --git a/target/arm/tcg/user/mte_helper.c b/target/arm/tcg/user/mte_hel= per.c new file mode 100644 index 0000000000..610a85dc59 --- /dev/null +++ b/target/arm/tcg/user/mte_helper.c @@ -0,0 +1,57 @@ +/* + * ARM v8.5-MemTag Operations - User-mode + * + * Copyright (c) 2020 Linaro, Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "tcg/mte_helper.h" + +uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, + uint64_t ptr, MMUAccessType ptr_access, + int ptr_size, MMUAccessType tag_access, + int tag_size, uintptr_t ra) +{ + uint64_t clean_ptr =3D useronly_clean_ptr(ptr); + int flags =3D page_get_flags(clean_ptr); + uint8_t *tags; + uintptr_t index; + + if (!(flags & (ptr_access =3D=3D MMU_DATA_STORE ? PAGE_WRITE_ORG : PAG= E_READ))) { + /* SIGSEGV */ + arm_cpu_tlb_fill(env_cpu(env), ptr, ptr_size, ptr_access, + ptr_mmu_idx, false, ra); + g_assert_not_reached(); + } + + /* Require both MAP_ANON and PROT_MTE for the page. */ + if (!(flags & PAGE_ANON) || !(flags & PAGE_MTE)) { + return NULL; + } + + tags =3D page_get_target_data(clean_ptr); + if (tags =3D=3D NULL) { + size_t alloc_size =3D TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1); + tags =3D page_alloc_target_data(clean_ptr, alloc_size); + assert(tags !=3D NULL); + } + + index =3D extract32(ptr, LOG2_TAG_GRANULE + 1, + TARGET_PAGE_BITS - LOG2_TAG_GRANULE - 1); + return tags + index; +} diff --git a/target/arm/tcg/sysemu/meson.build b/target/arm/tcg/sysemu/meso= n.build index 726387b0b3..6f014f77ec 100644 --- a/target/arm/tcg/sysemu/meson.build +++ b/target/arm/tcg/sysemu/meson.build @@ -1,2 +1,3 @@ arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( + 'mte_helper.c', )) diff --git a/target/arm/tcg/user/meson.build b/target/arm/tcg/user/meson.bu= ild index 7af3311190..e681e5f5a1 100644 --- a/target/arm/tcg/user/meson.build +++ b/target/arm/tcg/user/meson.build @@ -1,2 +1,3 @@ arm_user_ss.add(when: 'CONFIG_TCG', if_true: files( + 'mte_helper.c', )) --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622831129; cv=none; d=zohomail.com; s=zohoarc; b=UUxFONS+Wux6afbB1KOtURTbmRNL8SKBarLYZXz5bByhYIwed428NAcjzhng6MG8w3OyEhvMXNEZSrqRBNWagN4gDUylgw5WFNnGtLGzS/Smp+K+Px5ZnnwY9D4dsRXQqwn+XObOel8Wn5dJ8HiBqlmnlWWghzGodaot8qtGKd0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622831129; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dUqxN4lb+GfiuAaelODfQHE3gWgKHRBOE5j2GQAObTg=; b=Jidzf8p9Lkc4Trob13zYrDIv9QnoETU6ajNId62YscyqOtdYno7p5EBCvcVBeNfXgmubjYc8E5BaB0pGJC/3aKL7nJ4/hv+2vEEBXYRzsRQFO73oEa+IDVLp8pC30ygyIr0H+rXVepH+bKbdBFQX1IrpUPnpqsObgV3zYORxkgM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622831129208983.4438478802973; Fri, 4 Jun 2021 11:25:29 -0700 (PDT) Received: from localhost ([::1]:46226 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpEVc-0001JG-6d for importer@patchew.org; Fri, 04 Jun 2021 14:25:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42338) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpET3-0000rJ-0g for qemu-devel@nongnu.org; Fri, 04 Jun 2021 14:22:49 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:40675) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpESv-0000Jt-2N for qemu-devel@nongnu.org; Fri, 04 Jun 2021 14:22:48 -0400 Received: by mail-wr1-x42e.google.com with SMTP id y7so5556985wrh.7 for ; Fri, 04 Jun 2021 11:22:40 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id y189sm6540544wmy.25.2021.06.04.11.22.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 11:22:38 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 7351C1FFAA; Fri, 4 Jun 2021 16:53:14 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dUqxN4lb+GfiuAaelODfQHE3gWgKHRBOE5j2GQAObTg=; b=con1IPL0H5Citz/LQVNUjQpcsxmgkwNYBNV+VAnRxx2DTqj9xwtk0zKC6/PmD+h/3c ko+vjrFDOg2zK6vLv7abojdId7lbwhUELOlt9w6lDUo65VdLyOqDizIxlArxYQUQA/l2 up+B1Ml8eYmWMEkl1hAYHYjuHmuByNNAghbZIsCh38RViJE3IOl9yuy3hcyKcc+MTU2t U0gRXemaHaVoYHqnxO/I6Ye6IvV/XQi4mbNAyu8vnmC74hq7YqD7lraBooglFZLoeHkg yIWpaU8LfcWdAjgwOT9g8Abm9h0K0YvyqQ9HsYg//T2CZn8BNHJn9NSpLyGUy4nXloZL 5opg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dUqxN4lb+GfiuAaelODfQHE3gWgKHRBOE5j2GQAObTg=; b=msL3Ad0CUNcJuoGMq9QV6CRbwKH1hUl7x7mAQu2+4yXH5V1Talt6ySIJF5/87yd9dz 0a9f/maigvbB9jClx1p1RL2vxHCfDhDVL9BCJ46WKjXJbZYZanQZ6DVUa0fGAvLbzYMQ vTMbabUw/NfhgercoxXENpRiRdh+hh7nSCtvFAHvn0Kx5WXs/9A6ARWE4NK7wDdgD9ef UcM9TYCNlh4UsZQH8dWI9xYVOBFNFOonGp2eT2aUbG4aSjGkoWJEEyRMBEq6qbsabCv3 ELgvOaKAIqgVEzBwS15qNSlUw6ihJno+LldD8PRwdp06vWLTV3pmJUHJ2+xVkdk3JF4O jPjw== X-Gm-Message-State: AOAM530KC5F6YkXtbSeNu6dMpBtyx9Aclz8DYaI8moDGYs9BmQaB6cb/ kOCQErXgQ5JPVnByH3f26IpBRA== X-Google-Smtp-Source: ABdhPJwVVZPTfbdxtUZSGdoEH7DKywEh2pM/6ZQYYMIlnfl+abPQ4bl+X/NOV0m2NaBH82mpq8SMrw== X-Received: by 2002:adf:f7c3:: with SMTP id a3mr4752291wrq.253.1622830959561; Fri, 04 Jun 2021 11:22:39 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 20/99] target/arm: tcg: move sysemu-only parts of debug_helper Date: Fri, 4 Jun 2021 16:51:53 +0100 Message-Id: <20210604155312.15902-21-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana move sysemu-only parts of debug_helper to sysemu/ Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/debug_helper.c | 27 ----------------------- target/arm/tcg/sysemu/debug_helper.c | 33 ++++++++++++++++++++++++++++ target/arm/tcg/sysemu/meson.build | 1 + 3 files changed, 34 insertions(+), 27 deletions(-) create mode 100644 target/arm/tcg/sysemu/debug_helper.c diff --git a/target/arm/tcg/debug_helper.c b/target/arm/tcg/debug_helper.c index 2ff72d47d1..66a0915393 100644 --- a/target/arm/tcg/debug_helper.c +++ b/target/arm/tcg/debug_helper.c @@ -308,30 +308,3 @@ void arm_debug_excp_handler(CPUState *cs) arm_debug_target_el(env)); } } - -#if !defined(CONFIG_USER_ONLY) - -vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - /* - * In BE32 system mode, target memory is stored byteswapped (on a - * little-endian host system), and by the time we reach here (via an - * opcode helper) the addresses of subword accesses have been adjusted - * to account for that, which means that watchpoints will not match. - * Undo the adjustment here. - */ - if (arm_sctlr_b(env)) { - if (len =3D=3D 1) { - addr ^=3D 3; - } else if (len =3D=3D 2) { - addr ^=3D 2; - } - } - - return addr; -} - -#endif diff --git a/target/arm/tcg/sysemu/debug_helper.c b/target/arm/tcg/sysemu/d= ebug_helper.c new file mode 100644 index 0000000000..0bce00144f --- /dev/null +++ b/target/arm/tcg/sysemu/debug_helper.c @@ -0,0 +1,33 @@ +/* + * ARM debug helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" + +vaddr arm_adjust_watchpoint_address(CPUState *cs, vaddr addr, int len) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + /* + * In BE32 system mode, target memory is stored byteswapped (on a + * little-endian host system), and by the time we reach here (via an + * opcode helper) the addresses of subword accesses have been adjusted + * to account for that, which means that watchpoints will not match. + * Undo the adjustment here. + */ + if (arm_sctlr_b(env)) { + if (len =3D=3D 1) { + addr ^=3D 3; + } else if (len =3D=3D 2) { + addr ^=3D 2; + } + } + + return addr; +} diff --git a/target/arm/tcg/sysemu/meson.build b/target/arm/tcg/sysemu/meso= n.build index 6f014f77ec..1a4d7a0940 100644 --- a/target/arm/tcg/sysemu/meson.build +++ b/target/arm/tcg/sysemu/meson.build @@ -1,3 +1,4 @@ arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( + 'debug_helper.c', 'mte_helper.c', )) --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622823337; cv=none; d=zohomail.com; s=zohoarc; b=hcSEmVMi87EaL7OnGLIvOxMuzKg6+RDqYmIFjqOEdrpWVAbDB4YWbPjwLZ9GD1vcQxvMbeHw1+fThG2WomwTL+juuk41kZxynaKBa7QrrCVyPESNQp/5hfb9DTBWcNZdtYriH0ZoAMYTZoqA4pzAXnDfJYOkZixIfzm3iPB653Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622823337; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eXvK+3AOQ6m3KywdrH0nWhrBTBSo/h3FF5G5cv3gKts=; b=IA7n1LYdTFLGMzbtty8iAKbTHb404nJ9Ia0frw7PxmCULd4g6X0ZBoVQJuuHkvw3yqMj4ssJPB69uYz6cXhIv8Th/2ZzhV1hlyfuxQI51qF+VzkXx+xVdO/C846ZhQdgjCLOa96wC0DQtAT8c3zUmUtKPMdAszUQmcqowh/377U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622823337866617.3904855857016; Fri, 4 Jun 2021 09:15:37 -0700 (PDT) Received: from localhost ([::1]:53850 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCTw-0007Vx-Op for importer@patchew.org; Fri, 04 Jun 2021 12:15:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48158) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCHY-0007eY-RI for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:02:49 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:51043) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHR-0005hM-Ap for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:02:48 -0400 Received: by mail-wm1-x32c.google.com with SMTP id f20so1465561wmg.0 for ; Fri, 04 Jun 2021 09:02:40 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id x10sm7174349wrt.65.2021.06.04.09.02.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:37 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 959141FFAB; Fri, 4 Jun 2021 16:53:14 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eXvK+3AOQ6m3KywdrH0nWhrBTBSo/h3FF5G5cv3gKts=; b=TbUh/sVvJMx2lNXgKLs7LZ0ebdn2mcV+RRTLFTzw3w5qWuePqnwfVzScSvBwDekxth MVQXhGkyRJe7GfusnmnqJtzvdnS8/j93G3XsmjqVJo0m8yZFfPWm4N/3/TjBjbvizsfz mtJDpJ35Ad7WELaz3hOz2w2ipyVEGl6HE13nJ0PfMbu0476nH0Lydqf2aBn0KC54ftjj 6N+H1FwRdSlbVLETp9yvNPUflnNH2Cczal+yz08ocYVs2Z1ee3n5DdrzjyRhLco6vINo 9iuhoaP13DvCM/y5rhqQcTX25f1WXoa3ahLqpPS5oafJrvzt9k/4qKLxDS7fthS5VGLY hw9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eXvK+3AOQ6m3KywdrH0nWhrBTBSo/h3FF5G5cv3gKts=; b=TBYnTdi0GWrDu6zSxAx3YXeLVLu/2GAiRn1fY/cNgFpVcM2QF6gS2tbC5uqCrr+pUT cJDTp0lfYasvsB3uZXR5juLAYsryGyiz0dwX6961Mq2/UdYEnTCf1/ZDV1x7uiYiG35F 3haIIVQxV6AqXx+rR+yT4oWChsgqexhun3THvwrnHtuC/WwaIViqOPiXRmZ+OR1Fh9cm 7loCF9L9vUUVBtHsuvuur+sAzPOgEq1DxVd3cgqmsSeI0vsR408LOCH2ZzK8BslXDd/p kCNkyPhqfFeAjPQfMqVwKvRwR4IxHnVsW39KjnhqPa5nj4QwjcWfPYVh56m6cFawWFRA 9Xcg== X-Gm-Message-State: AOAM533CEKUwcsWiRXxECQrTDixrDYqZzNR8MSe+DdJVydq5JJlTPrC5 1GP1BvaiQEyVUa1b4W5tsknkMg== X-Google-Smtp-Source: ABdhPJxmHzQFLq/Bcz/LHLmuMY4y8Iw0IJ9oewIfbwvB9WKxAvugHjiYeYIdZS4k0SgtXj5ar4QJiQ== X-Received: by 2002:a1c:1bd8:: with SMTP id b207mr4229149wmb.80.1622822559175; Fri, 04 Jun 2021 09:02:39 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 21/99] target/arm: tcg: split tlb_helper user-only and sysemu-only parts Date: Fri, 4 Jun 2021 16:51:54 +0100 Message-Id: <20210604155312.15902-22-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/tlb_helper.h | 17 ++++++ target/arm/tcg/sysemu/tlb_helper.c | 83 +++++++++++++++++++++++++ target/arm/tcg/tlb_helper.c | 97 ++---------------------------- target/arm/tcg/user/tlb_helper.c | 32 ++++++++++ target/arm/tcg/sysemu/meson.build | 1 + target/arm/tcg/user/meson.build | 1 + 6 files changed, 138 insertions(+), 93 deletions(-) create mode 100644 target/arm/tcg/tlb_helper.h create mode 100644 target/arm/tcg/sysemu/tlb_helper.c create mode 100644 target/arm/tcg/user/tlb_helper.c diff --git a/target/arm/tcg/tlb_helper.h b/target/arm/tcg/tlb_helper.h new file mode 100644 index 0000000000..6ce3d315cf --- /dev/null +++ b/target/arm/tcg/tlb_helper.h @@ -0,0 +1,17 @@ +/* + * ARM TLB (Translation lookaside buffer) helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef TLB_HELPER_H +#define TLB_HELPER_H + +#include "cpu.h" + +void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, ARMMMUFaultInfo *fi); + +#endif /* TLB_HELPER_H */ diff --git a/target/arm/tcg/sysemu/tlb_helper.c b/target/arm/tcg/sysemu/tlb= _helper.c new file mode 100644 index 0000000000..586f602989 --- /dev/null +++ b/target/arm/tcg/sysemu/tlb_helper.c @@ -0,0 +1,83 @@ +/* + * ARM TLB (Translation lookaside buffer) helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "tcg/tlb_helper.h" + +/* + * arm_cpu_do_transaction_failed: handle a memory system error response + * (eg "no device/memory present at address") by raising an external abort + * exception + */ +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + ARMMMUFaultInfo fi =3D {}; + + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + + fi.ea =3D arm_extabort_type(response); + fi.type =3D ARMFault_SyncExternal; + arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); +} + +bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + ARMMMUFaultInfo fi =3D {}; + hwaddr phys_addr; + target_ulong page_size; + int prot, ret; + MemTxAttrs attrs =3D {}; + ARMCacheAttrs cacheattrs =3D {}; + + /* + * Walk the page table and (if the mapping exists) add the page + * to the TLB. On success, return true. Otherwise, if probing, + * return false. Otherwise populate fsr with ARM DFSR/IFSR fault + * register format, and signal the fault. + */ + ret =3D get_phys_addr(&cpu->env, address, access_type, + core_to_arm_mmu_idx(&cpu->env, mmu_idx), + &phys_addr, &attrs, &prot, &page_size, + &fi, &cacheattrs); + if (likely(!ret)) { + /* + * Map a single [sub]page. Regions smaller than our declared + * target page size are handled specially, so for those we + * pass in the exact addresses. + */ + if (page_size >=3D TARGET_PAGE_SIZE) { + phys_addr &=3D TARGET_PAGE_MASK; + address &=3D TARGET_PAGE_MASK; + } + /* Notice and record tagged memory. */ + if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs =3D=3D 0xf= 0) { + arm_tlb_mte_tagged(&attrs) =3D true; + } + + tlb_set_page_with_attrs(cs, address, phys_addr, attrs, + prot, mmu_idx, page_size); + return true; + } else if (probe) { + return false; + } else { + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); + } +} diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 3107f9823e..77aefc274d 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -9,6 +9,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "tcg/tlb_helper.h" =20 static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, @@ -49,9 +50,9 @@ static inline uint32_t merge_syn_data_abort(uint32_t temp= late_syn, return syn; } =20 -static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, ARMMMUFaultInfo *= fi) +void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, ARMMMUFaultInfo *fi) { CPUARMState *env =3D &cpu->env; int target_el; @@ -122,93 +123,3 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr v= addr, fi.type =3D ARMFault_Alignment; arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } - -#if !defined(CONFIG_USER_ONLY) - -/* - * arm_cpu_do_transaction_failed: handle a memory system error response - * (eg "no device/memory present at address") by raising an external abort - * exception - */ -void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t retaddr) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - ARMMMUFaultInfo fi =3D {}; - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - - fi.ea =3D arm_extabort_type(response); - fi.type =3D ARMFault_SyncExternal; - arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); -} - -#endif /* !defined(CONFIG_USER_ONLY) */ - -bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - ARMMMUFaultInfo fi =3D {}; - -#ifdef CONFIG_USER_ONLY - int flags =3D page_get_flags(useronly_clean_ptr(address)); - if (flags & PAGE_VALID) { - fi.type =3D ARMFault_Permission; - } else { - fi.type =3D ARMFault_Translation; - } - fi.level =3D 3; - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); -#else - hwaddr phys_addr; - target_ulong page_size; - int prot, ret; - MemTxAttrs attrs =3D {}; - ARMCacheAttrs cacheattrs =3D {}; - - /* - * Walk the page table and (if the mapping exists) add the page - * to the TLB. On success, return true. Otherwise, if probing, - * return false. Otherwise populate fsr with ARM DFSR/IFSR fault - * register format, and signal the fault. - */ - ret =3D get_phys_addr(&cpu->env, address, access_type, - core_to_arm_mmu_idx(&cpu->env, mmu_idx), - &phys_addr, &attrs, &prot, &page_size, - &fi, &cacheattrs); - if (likely(!ret)) { - /* - * Map a single [sub]page. Regions smaller than our declared - * target page size are handled specially, so for those we - * pass in the exact addresses. - */ - if (page_size >=3D TARGET_PAGE_SIZE) { - phys_addr &=3D TARGET_PAGE_MASK; - address &=3D TARGET_PAGE_MASK; - } - /* Notice and record tagged memory. */ - if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs =3D=3D 0xf= 0) { - arm_tlb_mte_tagged(&attrs) =3D true; - } - - tlb_set_page_with_attrs(cs, address, phys_addr, attrs, - prot, mmu_idx, page_size); - return true; - } else if (probe) { - return false; - } else { - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); - } -#endif -} diff --git a/target/arm/tcg/user/tlb_helper.c b/target/arm/tcg/user/tlb_hel= per.c new file mode 100644 index 0000000000..9f24c96ba0 --- /dev/null +++ b/target/arm/tcg/user/tlb_helper.c @@ -0,0 +1,32 @@ +/* + * ARM TLB (Translation lookaside buffer) helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "tcg/tlb_helper.h" + +bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + ARMMMUFaultInfo fi =3D {}; + + int flags =3D page_get_flags(useronly_clean_ptr(address)); + if (flags & PAGE_VALID) { + fi.type =3D ARMFault_Permission; + } else { + fi.type =3D ARMFault_Translation; + } + fi.level =3D 3; + + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + arm_deliver_fault(cpu, address, access_type, mmu_idx, &fi); +} diff --git a/target/arm/tcg/sysemu/meson.build b/target/arm/tcg/sysemu/meso= n.build index 1a4d7a0940..8f5e955cbd 100644 --- a/target/arm/tcg/sysemu/meson.build +++ b/target/arm/tcg/sysemu/meson.build @@ -1,4 +1,5 @@ arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( 'debug_helper.c', 'mte_helper.c', + 'tlb_helper.c', )) diff --git a/target/arm/tcg/user/meson.build b/target/arm/tcg/user/meson.bu= ild index e681e5f5a1..cdca5d970c 100644 --- a/target/arm/tcg/user/meson.build +++ b/target/arm/tcg/user/meson.build @@ -1,3 +1,4 @@ arm_user_ss.add(when: 'CONFIG_TCG', if_true: files( 'mte_helper.c', + 'tlb_helper.c', )) --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622827614; cv=none; d=zohomail.com; s=zohoarc; b=g7KvGdijrhrchL383Ib3RjFXJp1ISwi13GAHVBBGY8gQaUviIDjNugopA8iISHd0W6SJLneeuxWwdFBuPgpeS6s5HEO725hC+XkGjTveQGwtX3J0VDVGSforTbYlnwP8sOHOdl1X0B9/xu1Q1GQKidccTVfvhyuojm1irtSuqFQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622827614; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=82B8itWPwsFy+XyKLmtn3Pgiv8Zj982nxS6sGKaSrzw=; b=bHIR89Yyu4GcJ89BhnzUCzL6BbdCuhHIB86Lo0auqAx/7/UkVnRGuGGi7+soicies8VTCkrSjj3bLazp4YXuYxKlNZyHCLN+hUeR6U3bTtajIHs6fE4EdOzX7ob6ADs/NnWdibDHf+pl36zivyxr+fnRzjVbBihY4ZXiV/cZ0PU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622827614372610.1761345109066; Fri, 4 Jun 2021 10:26:54 -0700 (PDT) Received: from localhost ([::1]:43608 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDau-0007g5-V1 for importer@patchew.org; Fri, 04 Jun 2021 13:26:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33998) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCl7-0000m3-AN for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:21 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:36770) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCkp-0002Fu-4A for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:21 -0400 Received: by mail-wm1-x32b.google.com with SMTP id n17-20020a7bc5d10000b0290169edfadac9so8286768wmk.1 for ; Fri, 04 Jun 2021 09:33:02 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id b10sm6726379wrt.24.2021.06.04.09.32.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:57 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id CD27B1FF87; Fri, 4 Jun 2021 16:53:14 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=82B8itWPwsFy+XyKLmtn3Pgiv8Zj982nxS6sGKaSrzw=; b=Ngw4oRosEXH5oBd38XQuvLgeMRlN7KAI4LXFyI6L1U3eq6MyvfOsky9+EeaGRyVdZ7 t+UtH7lZGUggAZ9JySjCgKUj8Rw50StADDqCymKjDSYO5fu1gjr//XCFG4r5aiL3lnVj goO629xAI081h8gdL8JqUHcAvjf64M98/IkuvYWLbjB5NGZRgLFewVceXPEtDjF3M89Z p/iV04Arp6rKqFgVZ7K3+AZWblY8q9vk9x5UdbE4MhKXYfK7NXaR73iGbCjW3vvVDBT5 a3k5IyPiWOd6mQyhgSatIPXVgYRedsYRkaacNsnl7eL3e3V/idbYnWqYDTcRuMy6dgFX gbhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=82B8itWPwsFy+XyKLmtn3Pgiv8Zj982nxS6sGKaSrzw=; b=XU235YmF3kxcOEy/R28ozwoaC9wuwevvCJKcp+C2IZwBLS3V0wDMgYUd3PZXGy5dZk BAGn6Nor7LNWnNA3HG5BeusAIfwVGY9RvyrJboPSRugoSE6IYArdHtEhBeggtAR9c05J 2t1Ru+pvObExa79wRdZet147YgY5UZR24QNQ6f7mU4puCutppD0XTzba6qi+SMDFq6Z5 27xFEOJXGktA1z7Mcnolrvu6S4kTvkUXxVhLy+Gk/4hSrRx1jTfUK0+j1o3SHT11QzLH XHP8di7b3pXMKPezRIEykgoovgz3fgYfbHKi5LAwybcr5PTmWdvHK17rdx91L1ugVEiV G4Ng== X-Gm-Message-State: AOAM530D7rzkPdoL3iOoUljMWMpH2TCGNRUrh659+IU4R0nDXM2lvh/5 Xxtouh23n/IzWBmg7PnVGeGWOw== X-Google-Smtp-Source: ABdhPJz4xDpji/ZU7V3Xh4NoohRcpP6pP1Ay/P7UkJL6/UZ3MCG50i9ONmQT7YSzLqlcCDektqDBjQ== X-Received: by 2002:a05:600c:251:: with SMTP id 17mr4461531wmj.137.1622824380078; Fri, 04 Jun 2021 09:33:00 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 22/99] target/arm: tcg: split m_helper user-only and sysemu-only parts Date: Fri, 4 Jun 2021 16:51:55 +0100 Message-Id: <20210604155312.15902-23-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana in the process remove a few CONFIG_TCG that are superfluous now. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/m_helper.h | 21 + target/arm/tcg/m_helper.c | 2767 +---------------------------- target/arm/tcg/sysemu/m_helper.c | 2655 +++++++++++++++++++++++++++ target/arm/tcg/user/m_helper.c | 97 + target/arm/tcg/sysemu/meson.build | 1 + target/arm/tcg/user/meson.build | 1 + 6 files changed, 2780 insertions(+), 2762 deletions(-) create mode 100644 target/arm/tcg/m_helper.h create mode 100644 target/arm/tcg/sysemu/m_helper.c create mode 100644 target/arm/tcg/user/m_helper.c diff --git a/target/arm/tcg/m_helper.h b/target/arm/tcg/m_helper.h new file mode 100644 index 0000000000..9da106aa65 --- /dev/null +++ b/target/arm/tcg/m_helper.h @@ -0,0 +1,21 @@ +/* + * ARM v7m generic helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef M_HELPER_H +#define M_HELPER_H + +#include "cpu.h" + +void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, + uint32_t reg, uint32_t val); + +uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el); + +uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure); + +#endif /* M_HELPER_H */ diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index eda74e5545..8f3763155f 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -1,5 +1,5 @@ /* - * ARM generic helpers. + * ARM v7m generic helpers. * * This code is licensed under the GNU GPL v2 or later. * @@ -7,35 +7,11 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/units.h" -#include "target/arm/idau.h" -#include "trace.h" #include "cpu.h" #include "internals.h" -#include "exec/gdbstub.h" -#include "exec/helper-proto.h" -#include "qemu/host-utils.h" -#include "qemu/main-loop.h" -#include "qemu/bitops.h" -#include "qemu/crc32c.h" -#include "qemu/qemu-print.h" -#include "exec/exec-all.h" -#include /* For crc32 */ -#include "semihosting/semihost.h" -#include "sysemu/cpus.h" -#include "sysemu/kvm.h" -#include "qemu/range.h" -#include "qapi/qapi-commands-machine-target.h" -#include "qapi/error.h" -#include "qemu/guest-random.h" -#ifdef CONFIG_TCG -#include "arm_ldst.h" -#include "exec/cpu_ldst.h" -#include "semihosting/common-semi.h" -#endif +#include "tcg/m_helper.h" =20 -static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, - uint32_t reg, uint32_t val) +void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, uint32_t reg, uint32_t = val) { /* Only APSR is actually writable */ if (!(reg & 4)) { @@ -51,7 +27,7 @@ static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, } } =20 -static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el) +uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el) { uint32_t mask =3D 0; =20 @@ -68,7 +44,7 @@ static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t r= eg, unsigned el) return xpsr_read(env) & mask; } =20 -static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure) +uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure) { uint32_t value =3D env->v7m.control[secure]; =20 @@ -79,2739 +55,6 @@ static uint32_t v7m_mrs_control(CPUARMState *env, uint= 32_t secure) return value; } =20 -#ifdef CONFIG_USER_ONLY - -void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) -{ - uint32_t mask =3D extract32(maskreg, 8, 4); - uint32_t reg =3D extract32(maskreg, 0, 8); - - switch (reg) { - case 0 ... 7: /* xPSR sub-fields */ - v7m_msr_xpsr(env, mask, reg, val); - break; - case 20: /* CONTROL */ - /* There are no sub-fields that are actually writable from EL0. */ - break; - default: - /* Unprivileged writes to other registers are ignored */ - break; - } -} - -uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) -{ - switch (reg) { - case 0 ... 7: /* xPSR sub-fields */ - return v7m_mrs_xpsr(env, reg, 0); - case 20: /* CONTROL */ - return v7m_mrs_control(env, 0); - default: - /* Unprivileged reads others as zero. */ - return 0; - } -} - -void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) -{ - /* translate.c should never generate calls here in user-only mode */ - g_assert_not_reached(); -} - -void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) -{ - /* translate.c should never generate calls here in user-only mode */ - g_assert_not_reached(); -} - -void HELPER(v7m_preserve_fp_state)(CPUARMState *env) -{ - /* translate.c should never generate calls here in user-only mode */ - g_assert_not_reached(); -} - -void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) -{ - /* translate.c should never generate calls here in user-only mode */ - g_assert_not_reached(); -} - -void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr) -{ - /* translate.c should never generate calls here in user-only mode */ - g_assert_not_reached(); -} - -uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) -{ - /* - * The TT instructions can be used by unprivileged code, but in - * user-only emulation we don't have the MPU. - * Luckily since we know we are NonSecure unprivileged (and that in - * turn means that the A flag wasn't specified), all the bits in the - * register must be zero: - * IREGION: 0 because IRVALID is 0 - * IRVALID: 0 because NS - * S: 0 because NS - * NSRW: 0 because NS - * NSR: 0 because NS - * RW: 0 because unpriv and A flag not set - * R: 0 because unpriv and A flag not set - * SRVALID: 0 because NS - * MRVALID: 0 because unpriv and A flag not set - * SREGION: 0 becaus SRVALID is 0 - * MREGION: 0 because MRVALID is 0 - */ - return 0; -} - -#else - -/* - * What kind of stack write are we doing? This affects how exceptions - * generated during the stacking are treated. - */ -typedef enum StackingMode { - STACK_NORMAL, - STACK_IGNFAULTS, - STACK_LAZYFP, -} StackingMode; - -static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, - ARMMMUIdx mmu_idx, StackingMode mode) -{ - CPUState *cs =3D CPU(cpu); - CPUARMState *env =3D &cpu->env; - MemTxAttrs attrs =3D {}; - MemTxResult txres; - target_ulong page_size; - hwaddr physaddr; - int prot; - ARMMMUFaultInfo fi =3D {}; - ARMCacheAttrs cacheattrs =3D {}; - bool secure =3D mmu_idx & ARM_MMU_IDX_M_S; - int exc; - bool exc_secure; - - if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &physaddr, - &attrs, &prot, &page_size, &fi, &cacheattrs)) { - /* MPU/SAU lookup failed */ - if (fi.type =3D=3D ARMFault_QEMU_SFault) { - if (mode =3D=3D STACK_LAZYFP) { - qemu_log_mask(CPU_LOG_INT, - "...SecureFault with SFSR.LSPERR " - "during lazy stacking\n"); - env->v7m.sfsr |=3D R_V7M_SFSR_LSPERR_MASK; - } else { - qemu_log_mask(CPU_LOG_INT, - "...SecureFault with SFSR.AUVIOL " - "during stacking\n"); - env->v7m.sfsr |=3D R_V7M_SFSR_AUVIOL_MASK; - } - env->v7m.sfsr |=3D R_V7M_SFSR_SFARVALID_MASK; - env->v7m.sfar =3D addr; - exc =3D ARMV7M_EXCP_SECURE; - exc_secure =3D false; - } else { - if (mode =3D=3D STACK_LAZYFP) { - qemu_log_mask(CPU_LOG_INT, - "...MemManageFault with CFSR.MLSPERR\n"); - env->v7m.cfsr[secure] |=3D R_V7M_CFSR_MLSPERR_MASK; - } else { - qemu_log_mask(CPU_LOG_INT, - "...MemManageFault with CFSR.MSTKERR\n"); - env->v7m.cfsr[secure] |=3D R_V7M_CFSR_MSTKERR_MASK; - } - exc =3D ARMV7M_EXCP_MEM; - exc_secure =3D secure; - } - goto pend_fault; - } - address_space_stl_le(arm_addressspace(cs, attrs), physaddr, value, - attrs, &txres); - if (txres !=3D MEMTX_OK) { - /* BusFault trying to write the data */ - if (mode =3D=3D STACK_LAZYFP) { - qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.LSPERR\n"); - env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_LSPERR_MASK; - } else { - qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.STKERR\n"); - env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_STKERR_MASK; - } - exc =3D ARMV7M_EXCP_BUS; - exc_secure =3D false; - goto pend_fault; - } - return true; - -pend_fault: - /* - * By pending the exception at this point we are making - * the IMPDEF choice "overridden exceptions pended" (see the - * MergeExcInfo() pseudocode). The other choice would be to not - * pend them now and then make a choice about which to throw away - * later if we have two derived exceptions. - * The only case when we must not pend the exception but instead - * throw it away is if we are doing the push of the callee registers - * and we've already generated a derived exception (this is indicated - * by the caller passing STACK_IGNFAULTS). Even in this case we will - * still update the fault status registers. - */ - switch (mode) { - case STACK_NORMAL: - armv7m_nvic_set_pending_derived(env->nvic, exc, exc_secure); - break; - case STACK_LAZYFP: - armv7m_nvic_set_pending_lazyfp(env->nvic, exc, exc_secure); - break; - case STACK_IGNFAULTS: - break; - } - return false; -} - -static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr, - ARMMMUIdx mmu_idx) -{ - CPUState *cs =3D CPU(cpu); - CPUARMState *env =3D &cpu->env; - MemTxAttrs attrs =3D {}; - MemTxResult txres; - target_ulong page_size; - hwaddr physaddr; - int prot; - ARMMMUFaultInfo fi =3D {}; - ARMCacheAttrs cacheattrs =3D {}; - bool secure =3D mmu_idx & ARM_MMU_IDX_M_S; - int exc; - bool exc_secure; - uint32_t value; - - if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr, - &attrs, &prot, &page_size, &fi, &cacheattrs)) { - /* MPU/SAU lookup failed */ - if (fi.type =3D=3D ARMFault_QEMU_SFault) { - qemu_log_mask(CPU_LOG_INT, - "...SecureFault with SFSR.AUVIOL during unstack\= n"); - env->v7m.sfsr |=3D R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVAL= ID_MASK; - env->v7m.sfar =3D addr; - exc =3D ARMV7M_EXCP_SECURE; - exc_secure =3D false; - } else { - qemu_log_mask(CPU_LOG_INT, - "...MemManageFault with CFSR.MUNSTKERR\n"); - env->v7m.cfsr[secure] |=3D R_V7M_CFSR_MUNSTKERR_MASK; - exc =3D ARMV7M_EXCP_MEM; - exc_secure =3D secure; - } - goto pend_fault; - } - - value =3D address_space_ldl(arm_addressspace(cs, attrs), physaddr, - attrs, &txres); - if (txres !=3D MEMTX_OK) { - /* BusFault trying to read the data */ - qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n"); - env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_UNSTKERR_MASK; - exc =3D ARMV7M_EXCP_BUS; - exc_secure =3D false; - goto pend_fault; - } - - *dest =3D value; - return true; - -pend_fault: - /* - * By pending the exception at this point we are making - * the IMPDEF choice "overridden exceptions pended" (see the - * MergeExcInfo() pseudocode). The other choice would be to not - * pend them now and then make a choice about which to throw away - * later if we have two derived exceptions. - */ - armv7m_nvic_set_pending(env->nvic, exc, exc_secure); - return false; -} - -void HELPER(v7m_preserve_fp_state)(CPUARMState *env) -{ - /* - * Preserve FP state (because LSPACT was set and we are about - * to execute an FP instruction). This corresponds to the - * PreserveFPState() pseudocode. - * We may throw an exception if the stacking fails. - */ - ARMCPU *cpu =3D env_archcpu(env); - bool is_secure =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; - bool negpri =3D !(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_HFRDY_MASK); - bool is_priv =3D !(env->v7m.fpccr[is_secure] & R_V7M_FPCCR_USER_MASK); - bool splimviol =3D env->v7m.fpccr[is_secure] & R_V7M_FPCCR_SPLIMVIOL_M= ASK; - uint32_t fpcar =3D env->v7m.fpcar[is_secure]; - bool stacked_ok =3D true; - bool ts =3D is_secure && (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MAS= K); - bool take_exception; - - /* Take the iothread lock as we are going to touch the NVIC */ - qemu_mutex_lock_iothread(); - - /* Check the background context had access to the FPU */ - if (!v7m_cpacr_pass(env, is_secure, is_priv)) { - armv7m_nvic_set_pending_lazyfp(env->nvic, ARMV7M_EXCP_USAGE, is_se= cure); - env->v7m.cfsr[is_secure] |=3D R_V7M_CFSR_NOCP_MASK; - stacked_ok =3D false; - } else if (!is_secure && !extract32(env->v7m.nsacr, 10, 1)) { - armv7m_nvic_set_pending_lazyfp(env->nvic, ARMV7M_EXCP_USAGE, M_REG= _S); - env->v7m.cfsr[M_REG_S] |=3D R_V7M_CFSR_NOCP_MASK; - stacked_ok =3D false; - } - - if (!splimviol && stacked_ok) { - /* We only stack if the stack limit wasn't violated */ - int i; - ARMMMUIdx mmu_idx; - - mmu_idx =3D arm_v7m_mmu_idx_all(env, is_secure, is_priv, negpri); - for (i =3D 0; i < (ts ? 32 : 16); i +=3D 2) { - uint64_t dn =3D *aa32_vfp_dreg(env, i / 2); - uint32_t faddr =3D fpcar + 4 * i; - uint32_t slo =3D extract64(dn, 0, 32); - uint32_t shi =3D extract64(dn, 32, 32); - - if (i >=3D 16) { - faddr +=3D 8; /* skip the slot for the FPSCR */ - } - stacked_ok =3D stacked_ok && - v7m_stack_write(cpu, faddr, slo, mmu_idx, STACK_LAZYFP) && - v7m_stack_write(cpu, faddr + 4, shi, mmu_idx, STACK_LAZYFP= ); - } - - stacked_ok =3D stacked_ok && - v7m_stack_write(cpu, fpcar + 0x40, - vfp_get_fpscr(env), mmu_idx, STACK_LAZYFP); - } - - /* - * We definitely pended an exception, but it's possible that it - * might not be able to be taken now. If its priority permits us - * to take it now, then we must not update the LSPACT or FP regs, - * but instead jump out to take the exception immediately. - * If it's just pending and won't be taken until the current - * handler exits, then we do update LSPACT and the FP regs. - */ - take_exception =3D !stacked_ok && - armv7m_nvic_can_take_pending_exception(env->nvic); - - qemu_mutex_unlock_iothread(); - - if (take_exception) { - raise_exception_ra(env, EXCP_LAZYFP, 0, 1, GETPC()); - } - - env->v7m.fpccr[is_secure] &=3D ~R_V7M_FPCCR_LSPACT_MASK; - - if (ts) { - /* Clear s0 to s31 and the FPSCR */ - int i; - - for (i =3D 0; i < 32; i +=3D 2) { - *aa32_vfp_dreg(env, i / 2) =3D 0; - } - vfp_set_fpscr(env, 0); - } - /* - * Otherwise s0 to s15 and FPSCR are UNKNOWN; we choose to leave them - * unchanged. - */ -} - -/* - * Write to v7M CONTROL.SPSEL bit for the specified security bank. - * This may change the current stack pointer between Main and Process - * stack pointers if it is done for the CONTROL register for the current - * security state. - */ -static void write_v7m_control_spsel_for_secstate(CPUARMState *env, - bool new_spsel, - bool secstate) -{ - bool old_is_psp =3D v7m_using_psp(env); - - env->v7m.control[secstate] =3D - deposit32(env->v7m.control[secstate], - R_V7M_CONTROL_SPSEL_SHIFT, - R_V7M_CONTROL_SPSEL_LENGTH, new_spsel); - - if (secstate =3D=3D env->v7m.secure) { - bool new_is_psp =3D v7m_using_psp(env); - uint32_t tmp; - - if (old_is_psp !=3D new_is_psp) { - tmp =3D env->v7m.other_sp; - env->v7m.other_sp =3D env->regs[13]; - env->regs[13] =3D tmp; - } - } -} - -/* - * Write to v7M CONTROL.SPSEL bit. This may change the current - * stack pointer between Main and Process stack pointers. - */ -static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel) -{ - write_v7m_control_spsel_for_secstate(env, new_spsel, env->v7m.secure); -} - -void write_v7m_exception(CPUARMState *env, uint32_t new_exc) -{ - /* - * Write a new value to v7m.exception, thus transitioning into or out - * of Handler mode; this may result in a change of active stack pointe= r. - */ - bool new_is_psp, old_is_psp =3D v7m_using_psp(env); - uint32_t tmp; - - env->v7m.exception =3D new_exc; - - new_is_psp =3D v7m_using_psp(env); - - if (old_is_psp !=3D new_is_psp) { - tmp =3D env->v7m.other_sp; - env->v7m.other_sp =3D env->regs[13]; - env->regs[13] =3D tmp; - } -} - -/* Switch M profile security state between NS and S */ -static void switch_v7m_security_state(CPUARMState *env, bool new_secstate) -{ - uint32_t new_ss_msp, new_ss_psp; - - if (env->v7m.secure =3D=3D new_secstate) { - return; - } - - /* - * All the banked state is accessed by looking at env->v7m.secure - * except for the stack pointer; rearrange the SP appropriately. - */ - new_ss_msp =3D env->v7m.other_ss_msp; - new_ss_psp =3D env->v7m.other_ss_psp; - - if (v7m_using_psp(env)) { - env->v7m.other_ss_psp =3D env->regs[13]; - env->v7m.other_ss_msp =3D env->v7m.other_sp; - } else { - env->v7m.other_ss_msp =3D env->regs[13]; - env->v7m.other_ss_psp =3D env->v7m.other_sp; - } - - env->v7m.secure =3D new_secstate; - - if (v7m_using_psp(env)) { - env->regs[13] =3D new_ss_psp; - env->v7m.other_sp =3D new_ss_msp; - } else { - env->regs[13] =3D new_ss_msp; - env->v7m.other_sp =3D new_ss_psp; - } -} - -void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) -{ - /* - * Handle v7M BXNS: - * - if the return value is a magic value, do exception return (like = BX) - * - otherwise bit 0 of the return value is the target security state - */ - uint32_t min_magic; - - if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - /* Covers FNC_RETURN and EXC_RETURN magic */ - min_magic =3D FNC_RETURN_MIN_MAGIC; - } else { - /* EXC_RETURN magic only */ - min_magic =3D EXC_RETURN_MIN_MAGIC; - } - - if (dest >=3D min_magic) { - /* - * This is an exception return magic value; put it where - * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT. - * Note that if we ever add gen_ss_advance() singlestep support to - * M profile this should count as an "instruction execution comple= te" - * event (compare gen_bx_excret_final_code()). - */ - env->regs[15] =3D dest & ~1; - env->thumb =3D dest & 1; - HELPER(exception_internal)(env, EXCP_EXCEPTION_EXIT); - /* notreached */ - } - - /* translate.c should have made BXNS UNDEF unless we're secure */ - assert(env->v7m.secure); - - if (!(dest & 1)) { - env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_SFPA_MASK; - } - switch_v7m_security_state(env, dest & 1); - env->thumb =3D 1; - env->regs[15] =3D dest & ~1; - arm_rebuild_hflags(env); -} - -void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) -{ - /* - * Handle v7M BLXNS: - * - bit 0 of the destination address is the target security state - */ - - /* At this point regs[15] is the address just after the BLXNS */ - uint32_t nextinst =3D env->regs[15] | 1; - uint32_t sp =3D env->regs[13] - 8; - uint32_t saved_psr; - - /* translate.c will have made BLXNS UNDEF unless we're secure */ - assert(env->v7m.secure); - - if (dest & 1) { - /* - * Target is Secure, so this is just a normal BLX, - * except that the low bit doesn't indicate Thumb/not. - */ - env->regs[14] =3D nextinst; - env->thumb =3D 1; - env->regs[15] =3D dest & ~1; - return; - } - - /* Target is non-secure: first push a stack frame */ - if (!QEMU_IS_ALIGNED(sp, 8)) { - qemu_log_mask(LOG_GUEST_ERROR, - "BLXNS with misaligned SP is UNPREDICTABLE\n"); - } - - if (sp < v7m_sp_limit(env)) { - raise_exception(env, EXCP_STKOF, 0, 1); - } - - saved_psr =3D env->v7m.exception; - if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK) { - saved_psr |=3D XPSR_SFPA; - } - - /* Note that these stores can throw exceptions on MPU faults */ - cpu_stl_data_ra(env, sp, nextinst, GETPC()); - cpu_stl_data_ra(env, sp + 4, saved_psr, GETPC()); - - env->regs[13] =3D sp; - env->regs[14] =3D 0xfeffffff; - if (arm_v7m_is_handler_mode(env)) { - /* - * Write a dummy value to IPSR, to avoid leaking the current secure - * exception number to non-secure code. This is guaranteed not - * to cause write_v7m_exception() to actually change stacks. - */ - write_v7m_exception(env, 1); - } - env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_SFPA_MASK; - switch_v7m_security_state(env, 0); - env->thumb =3D 1; - env->regs[15] =3D dest; - arm_rebuild_hflags(env); -} - -static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool thread= mode, - bool spsel) -{ - /* - * Return a pointer to the location where we currently store the - * stack pointer for the requested security state and thread mode. - * This pointer will become invalid if the CPU state is updated - * such that the stack pointers are switched around (eg changing - * the SPSEL control bit). - * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode(). - * Unlike that pseudocode, we require the caller to pass us in the - * SPSEL control bit value; this is because we also use this - * function in handling of pushing of the callee-saves registers - * part of the v8M stack frame (pseudocode PushCalleeStack()), - * and in the tailchain codepath the SPSEL bit comes from the exception - * return magic LR value from the previous exception. The pseudocode - * opencodes the stack-selection in PushCalleeStack(), but we prefer - * to make this utility function generic enough to do the job. - */ - bool want_psp =3D threadmode && spsel; - - if (secure =3D=3D env->v7m.secure) { - if (want_psp =3D=3D v7m_using_psp(env)) { - return &env->regs[13]; - } else { - return &env->v7m.other_sp; - } - } else { - if (want_psp) { - return &env->v7m.other_ss_psp; - } else { - return &env->v7m.other_ss_msp; - } - } -} - -static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure, - uint32_t *pvec) -{ - CPUState *cs =3D CPU(cpu); - CPUARMState *env =3D &cpu->env; - MemTxResult result; - uint32_t addr =3D env->v7m.vecbase[targets_secure] + exc * 4; - uint32_t vector_entry; - MemTxAttrs attrs =3D {}; - ARMMMUIdx mmu_idx; - bool exc_secure; - - mmu_idx =3D arm_v7m_mmu_idx_for_secstate_and_priv(env, targets_secure,= true); - - /* - * We don't do a get_phys_addr() here because the rules for vector - * loads are special: they always use the default memory map, and - * the default memory map permits reads from all addresses. - * Since there's no easy way to pass through to pmsav8_mpu_lookup() - * that we want this special case which would always say "yes", - * we just do the SAU lookup here followed by a direct physical load. - */ - attrs.secure =3D targets_secure; - attrs.user =3D false; - - if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - V8M_SAttributes sattrs =3D {}; - - v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs); - if (sattrs.ns) { - attrs.secure =3D false; - } else if (!targets_secure) { - /* - * NS access to S memory: the underlying exception which we es= calate - * to HardFault is SecureFault, which always targets Secure. - */ - exc_secure =3D true; - goto load_fail; - } - } - - vector_entry =3D address_space_ldl(arm_addressspace(cs, attrs), addr, - attrs, &result); - if (result !=3D MEMTX_OK) { - /* - * Underlying exception is BusFault: its target security state - * depends on BFHFNMINS. - */ - exc_secure =3D !(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK); - goto load_fail; - } - *pvec =3D vector_entry; - return true; - -load_fail: - /* - * All vector table fetch fails are reported as HardFault, with - * HFSR.VECTTBL and .FORCED set. (FORCED is set because - * technically the underlying exception is a SecureFault or BusFault - * that is escalated to HardFault.) This is a terminal exception, - * so we will either take the HardFault immediately or else enter - * lockup (the latter case is handled in armv7m_nvic_set_pending_deriv= ed()). - * The HardFault is Secure if BFHFNMINS is 0 (meaning that all HFs are - * secure); otherwise it targets the same security state as the - * underlying exception. - * In v8.1M HardFaults from vector table fetch fails don't set FORCED. - */ - if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { - exc_secure =3D true; - } - env->v7m.hfsr |=3D R_V7M_HFSR_VECTTBL_MASK; - if (!arm_feature(env, ARM_FEATURE_V8_1M)) { - env->v7m.hfsr |=3D R_V7M_HFSR_FORCED_MASK; - } - armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secur= e); - return false; -} - -static uint32_t v7m_integrity_sig(CPUARMState *env, uint32_t lr) -{ - /* - * Return the integrity signature value for the callee-saves - * stack frame section. @lr is the exception return payload/LR value - * whose FType bit forms bit 0 of the signature if FP is present. - */ - uint32_t sig =3D 0xfefa125a; - - if (!cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) - || (lr & R_V7M_EXCRET_FTYPE_MASK)) { - sig |=3D 1; - } - return sig; -} - -static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailcha= in, - bool ignore_faults) -{ - /* - * For v8M, push the callee-saves register part of the stack frame. - * Compare the v8M pseudocode PushCalleeStack(). - * In the tailchaining case this may not be the current stack. - */ - CPUARMState *env =3D &cpu->env; - uint32_t *frame_sp_p; - uint32_t frameptr; - ARMMMUIdx mmu_idx; - bool stacked_ok; - uint32_t limit; - bool want_psp; - uint32_t sig; - StackingMode smode =3D ignore_faults ? STACK_IGNFAULTS : STACK_NORMAL; - - if (dotailchain) { - bool mode =3D lr & R_V7M_EXCRET_MODE_MASK; - bool priv =3D !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_NPRIV_MA= SK) || - !mode; - - mmu_idx =3D arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, pr= iv); - frame_sp_p =3D get_v7m_sp_ptr(env, M_REG_S, mode, - lr & R_V7M_EXCRET_SPSEL_MASK); - want_psp =3D mode && (lr & R_V7M_EXCRET_SPSEL_MASK); - if (want_psp) { - limit =3D env->v7m.psplim[M_REG_S]; - } else { - limit =3D env->v7m.msplim[M_REG_S]; - } - } else { - mmu_idx =3D arm_mmu_idx(env); - frame_sp_p =3D &env->regs[13]; - limit =3D v7m_sp_limit(env); - } - - frameptr =3D *frame_sp_p - 0x28; - if (frameptr < limit) { - /* - * Stack limit failure: set SP to the limit value, and generate - * STKOF UsageFault. Stack pushes below the limit must not be - * performed. It is IMPDEF whether pushes above the limit are - * performed; we choose not to. - */ - qemu_log_mask(CPU_LOG_INT, - "...STKOF during callee-saves register stacking\n"); - env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_STKOF_MASK; - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, - env->v7m.secure); - *frame_sp_p =3D limit; - return true; - } - - /* - * Write as much of the stack frame as we can. A write failure may - * cause us to pend a derived exception. - */ - sig =3D v7m_integrity_sig(env, lr); - stacked_ok =3D - v7m_stack_write(cpu, frameptr, sig, mmu_idx, smode) && - v7m_stack_write(cpu, frameptr + 0x8, env->regs[4], mmu_idx, smode)= && - v7m_stack_write(cpu, frameptr + 0xc, env->regs[5], mmu_idx, smode)= && - v7m_stack_write(cpu, frameptr + 0x10, env->regs[6], mmu_idx, smode= ) && - v7m_stack_write(cpu, frameptr + 0x14, env->regs[7], mmu_idx, smode= ) && - v7m_stack_write(cpu, frameptr + 0x18, env->regs[8], mmu_idx, smode= ) && - v7m_stack_write(cpu, frameptr + 0x1c, env->regs[9], mmu_idx, smode= ) && - v7m_stack_write(cpu, frameptr + 0x20, env->regs[10], mmu_idx, smod= e) && - v7m_stack_write(cpu, frameptr + 0x24, env->regs[11], mmu_idx, smod= e); - - /* Update SP regardless of whether any of the stack accesses failed. */ - *frame_sp_p =3D frameptr; - - return !stacked_ok; -} - -static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain, - bool ignore_stackfaults) -{ - /* - * Do the "take the exception" parts of exception entry, - * but not the pushing of state to the stack. This is - * similar to the pseudocode ExceptionTaken() function. - */ - CPUARMState *env =3D &cpu->env; - uint32_t addr; - bool targets_secure; - int exc; - bool push_failed =3D false; - - armv7m_nvic_get_pending_irq_info(env->nvic, &exc, &targets_secure); - qemu_log_mask(CPU_LOG_INT, "...taking pending %s exception %d\n", - targets_secure ? "secure" : "nonsecure", exc); - - if (dotailchain) { - /* Sanitize LR FType and PREFIX bits */ - if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { - lr |=3D R_V7M_EXCRET_FTYPE_MASK; - } - lr =3D deposit32(lr, 24, 8, 0xff); - } - - if (arm_feature(env, ARM_FEATURE_V8)) { - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && - (lr & R_V7M_EXCRET_S_MASK)) { - /* - * The background code (the owner of the registers in the - * exception frame) is Secure. This means it may either already - * have or now needs to push callee-saves registers. - */ - if (targets_secure) { - if (dotailchain && !(lr & R_V7M_EXCRET_ES_MASK)) { - /* - * We took an exception from Secure to NonSecure - * (which means the callee-saved registers got stacked) - * and are now tailchaining to a Secure exception. - * Clear DCRS so eventual return from this Secure - * exception unstacks the callee-saved registers. - */ - lr &=3D ~R_V7M_EXCRET_DCRS_MASK; - } - } else { - /* - * We're going to a non-secure exception; push the - * callee-saves registers to the stack now, if they're - * not already saved. - */ - if (lr & R_V7M_EXCRET_DCRS_MASK && - !(dotailchain && !(lr & R_V7M_EXCRET_ES_MASK))) { - push_failed =3D v7m_push_callee_stack(cpu, lr, dotailc= hain, - ignore_stackfaults= ); - } - lr |=3D R_V7M_EXCRET_DCRS_MASK; - } - } - - lr &=3D ~R_V7M_EXCRET_ES_MASK; - if (targets_secure || !arm_feature(env, ARM_FEATURE_M_SECURITY)) { - lr |=3D R_V7M_EXCRET_ES_MASK; - } - lr &=3D ~R_V7M_EXCRET_SPSEL_MASK; - if (env->v7m.control[targets_secure] & R_V7M_CONTROL_SPSEL_MASK) { - lr |=3D R_V7M_EXCRET_SPSEL_MASK; - } - - /* - * Clear registers if necessary to prevent non-secure exception - * code being able to see register values from secure code. - * Where register values become architecturally UNKNOWN we leave - * them with their previous values. v8.1M is tighter than v8.0M - * here and always zeroes the caller-saved registers regardless - * of the security state the exception is targeting. - */ - if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - if (!targets_secure || arm_feature(env, ARM_FEATURE_V8_1M)) { - /* - * Always clear the caller-saved registers (they have been - * pushed to the stack earlier in v7m_push_stack()). - * Clear callee-saved registers if the background code is - * Secure (in which case these regs were saved in - * v7m_push_callee_stack()). - */ - int i; - /* - * r4..r11 are callee-saves, zero only if background - * state was Secure (EXCRET.S =3D=3D 1) and exception - * targets Non-secure state - */ - bool zero_callee_saves =3D !targets_secure && - (lr & R_V7M_EXCRET_S_MASK); - - for (i =3D 0; i < 13; i++) { - if (i < 4 || i > 11 || zero_callee_saves) { - env->regs[i] =3D 0; - } - } - /* Clear EAPSR */ - xpsr_write(env, 0, XPSR_NZCV | XPSR_Q | XPSR_GE | XPSR_IT); - } - } - } - - if (push_failed && !ignore_stackfaults) { - /* - * Derived exception on callee-saves register stacking: - * we might now want to take a different exception which - * targets a different security state, so try again from the top. - */ - qemu_log_mask(CPU_LOG_INT, - "...derived exception on callee-saves register stack= ing"); - v7m_exception_taken(cpu, lr, true, true); - return; - } - - if (!arm_v7m_load_vector(cpu, exc, targets_secure, &addr)) { - /* Vector load failed: derived exception */ - qemu_log_mask(CPU_LOG_INT, "...derived exception on vector table l= oad"); - v7m_exception_taken(cpu, lr, true, true); - return; - } - - /* - * Now we've done everything that might cause a derived exception - * we can go ahead and activate whichever exception we're going to - * take (which might now be the derived exception). - */ - armv7m_nvic_acknowledge_irq(env->nvic); - - /* Switch to target security state -- must do this before writing SPSE= L */ - switch_v7m_security_state(env, targets_secure); - write_v7m_control_spsel(env, 0); - arm_clear_exclusive(env); - /* Clear SFPA and FPCA (has no effect if no FPU) */ - env->v7m.control[M_REG_S] &=3D - ~(R_V7M_CONTROL_FPCA_MASK | R_V7M_CONTROL_SFPA_MASK); - /* Clear IT bits */ - env->condexec_bits =3D 0; - env->regs[14] =3D lr; - env->regs[15] =3D addr & 0xfffffffe; - env->thumb =3D addr & 1; - arm_rebuild_hflags(env); -} - -static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, - bool apply_splim) -{ - /* - * Like the pseudocode UpdateFPCCR: save state in FPCAR and FPCCR - * that we will need later in order to do lazy FP reg stacking. - */ - bool is_secure =3D env->v7m.secure; - void *nvic =3D env->nvic; - /* - * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits - * are banked and we want to update the bit in the bank for the - * current security state; and in one case we want to specifically - * update the NS banked version of a bit even if we are secure. - */ - uint32_t *fpccr_s =3D &env->v7m.fpccr[M_REG_S]; - uint32_t *fpccr_ns =3D &env->v7m.fpccr[M_REG_NS]; - uint32_t *fpccr =3D &env->v7m.fpccr[is_secure]; - bool hfrdy, bfrdy, mmrdy, ns_ufrdy, s_ufrdy, sfrdy, monrdy; - - env->v7m.fpcar[is_secure] =3D frameptr & ~0x7; - - if (apply_splim && arm_feature(env, ARM_FEATURE_V8)) { - bool splimviol; - uint32_t splim =3D v7m_sp_limit(env); - bool ign =3D armv7m_nvic_neg_prio_requested(nvic, is_secure) && - (env->v7m.ccr[is_secure] & R_V7M_CCR_STKOFHFNMIGN_MASK); - - splimviol =3D !ign && frameptr < splim; - *fpccr =3D FIELD_DP32(*fpccr, V7M_FPCCR, SPLIMVIOL, splimviol); - } - - *fpccr =3D FIELD_DP32(*fpccr, V7M_FPCCR, LSPACT, 1); - - *fpccr_s =3D FIELD_DP32(*fpccr_s, V7M_FPCCR, S, is_secure); - - *fpccr =3D FIELD_DP32(*fpccr, V7M_FPCCR, USER, arm_current_el(env) =3D= =3D 0); - - *fpccr =3D FIELD_DP32(*fpccr, V7M_FPCCR, THREAD, - !arm_v7m_is_handler_mode(env)); - - hfrdy =3D armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_HARD, false); - *fpccr_s =3D FIELD_DP32(*fpccr_s, V7M_FPCCR, HFRDY, hfrdy); - - bfrdy =3D armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_BUS, false); - *fpccr_s =3D FIELD_DP32(*fpccr_s, V7M_FPCCR, BFRDY, bfrdy); - - mmrdy =3D armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_MEM, is_secur= e); - *fpccr =3D FIELD_DP32(*fpccr, V7M_FPCCR, MMRDY, mmrdy); - - ns_ufrdy =3D armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_USAGE, fal= se); - *fpccr_ns =3D FIELD_DP32(*fpccr_ns, V7M_FPCCR, UFRDY, ns_ufrdy); - - monrdy =3D armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_DEBUG, false= ); - *fpccr_s =3D FIELD_DP32(*fpccr_s, V7M_FPCCR, MONRDY, monrdy); - - if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - s_ufrdy =3D armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_USAGE, = true); - *fpccr_s =3D FIELD_DP32(*fpccr_s, V7M_FPCCR, UFRDY, s_ufrdy); - - sfrdy =3D armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_SECURE, f= alse); - *fpccr_s =3D FIELD_DP32(*fpccr_s, V7M_FPCCR, SFRDY, sfrdy); - } -} - -void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) -{ - /* fptr is the value of Rn, the frame pointer we store the FP regs to = */ - bool s =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; - bool lspact =3D env->v7m.fpccr[s] & R_V7M_FPCCR_LSPACT_MASK; - uintptr_t ra =3D GETPC(); - - assert(env->v7m.secure); - - if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)) { - return; - } - - /* Check access to the coprocessor is permitted */ - if (!v7m_cpacr_pass(env, true, arm_current_el(env) !=3D 0)) { - raise_exception_ra(env, EXCP_NOCP, 0, 1, GETPC()); - } - - if (lspact) { - /* LSPACT should not be active when there is active FP state */ - raise_exception_ra(env, EXCP_LSERR, 0, 1, GETPC()); - } - - if (fptr & 7) { - raise_exception_ra(env, EXCP_UNALIGNED, 0, 1, GETPC()); - } - - /* - * Note that we do not use v7m_stack_write() here, because the - * accesses should not set the FSR bits for stacking errors if they - * fail. (In pseudocode terms, they are AccType_NORMAL, not AccType_ST= ACK - * or AccType_LAZYFP). Faults in cpu_stl_data_ra() will throw exceptio= ns - * and longjmp out. - */ - if (!(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPEN_MASK)) { - bool ts =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK; - int i; - - for (i =3D 0; i < (ts ? 32 : 16); i +=3D 2) { - uint64_t dn =3D *aa32_vfp_dreg(env, i / 2); - uint32_t faddr =3D fptr + 4 * i; - uint32_t slo =3D extract64(dn, 0, 32); - uint32_t shi =3D extract64(dn, 32, 32); - - if (i >=3D 16) { - faddr +=3D 8; /* skip the slot for the FPSCR */ - } - cpu_stl_data_ra(env, faddr, slo, ra); - cpu_stl_data_ra(env, faddr + 4, shi, ra); - } - cpu_stl_data_ra(env, fptr + 0x40, vfp_get_fpscr(env), ra); - - /* - * If TS is 0 then s0 to s15 and FPSCR are UNKNOWN; we choose to - * leave them unchanged, matching our choice in v7m_preserve_fp_st= ate. - */ - if (ts) { - for (i =3D 0; i < 32; i +=3D 2) { - *aa32_vfp_dreg(env, i / 2) =3D 0; - } - vfp_set_fpscr(env, 0); - } - } else { - v7m_update_fpccr(env, fptr, false); - } - - env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_FPCA_MASK; -} - -void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr) -{ - uintptr_t ra =3D GETPC(); - - /* fptr is the value of Rn, the frame pointer we load the FP regs from= */ - assert(env->v7m.secure); - - if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)) { - return; - } - - /* Check access to the coprocessor is permitted */ - if (!v7m_cpacr_pass(env, true, arm_current_el(env) !=3D 0)) { - raise_exception_ra(env, EXCP_NOCP, 0, 1, GETPC()); - } - - if (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPACT_MASK) { - /* State in FP is still valid */ - env->v7m.fpccr[M_REG_S] &=3D ~R_V7M_FPCCR_LSPACT_MASK; - } else { - bool ts =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK; - int i; - uint32_t fpscr; - - if (fptr & 7) { - raise_exception_ra(env, EXCP_UNALIGNED, 0, 1, GETPC()); - } - - for (i =3D 0; i < (ts ? 32 : 16); i +=3D 2) { - uint32_t slo, shi; - uint64_t dn; - uint32_t faddr =3D fptr + 4 * i; - - if (i >=3D 16) { - faddr +=3D 8; /* skip the slot for the FPSCR */ - } - - slo =3D cpu_ldl_data_ra(env, faddr, ra); - shi =3D cpu_ldl_data_ra(env, faddr + 4, ra); - - dn =3D (uint64_t) shi << 32 | slo; - *aa32_vfp_dreg(env, i / 2) =3D dn; - } - fpscr =3D cpu_ldl_data_ra(env, fptr + 0x40, ra); - vfp_set_fpscr(env, fpscr); - } - - env->v7m.control[M_REG_S] |=3D R_V7M_CONTROL_FPCA_MASK; -} - -static bool v7m_push_stack(ARMCPU *cpu) -{ - /* - * Do the "set up stack frame" part of exception entry, - * similar to pseudocode PushStack(). - * Return true if we generate a derived exception (and so - * should ignore further stack faults trying to process - * that derived exception.) - */ - bool stacked_ok =3D true, limitviol =3D false; - CPUARMState *env =3D &cpu->env; - uint32_t xpsr =3D xpsr_read(env); - uint32_t frameptr =3D env->regs[13]; - ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); - uint32_t framesize; - bool nsacr_cp10 =3D extract32(env->v7m.nsacr, 10, 1); - - if ((env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) && - (env->v7m.secure || nsacr_cp10)) { - if (env->v7m.secure && - env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK) { - framesize =3D 0xa8; - } else { - framesize =3D 0x68; - } - } else { - framesize =3D 0x20; - } - - /* Align stack pointer if the guest wants that */ - if ((frameptr & 4) && - (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKALIGN_MASK)) { - frameptr -=3D 4; - xpsr |=3D XPSR_SPREALIGN; - } - - xpsr &=3D ~XPSR_SFPA; - if (env->v7m.secure && - (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)) { - xpsr |=3D XPSR_SFPA; - } - - frameptr -=3D framesize; - - if (arm_feature(env, ARM_FEATURE_V8)) { - uint32_t limit =3D v7m_sp_limit(env); - - if (frameptr < limit) { - /* - * Stack limit failure: set SP to the limit value, and generate - * STKOF UsageFault. Stack pushes below the limit must not be - * performed. It is IMPDEF whether pushes above the limit are - * performed; we choose not to. - */ - qemu_log_mask(CPU_LOG_INT, - "...STKOF during stacking\n"); - env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_STKOF_MASK; - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, - env->v7m.secure); - env->regs[13] =3D limit; - /* - * We won't try to perform any further memory accesses but - * we must continue through the following code to check for - * permission faults during FPU state preservation, and we - * must update FPCCR if lazy stacking is enabled. - */ - limitviol =3D true; - stacked_ok =3D false; - } - } - - /* - * Write as much of the stack frame as we can. If we fail a stack - * write this will result in a derived exception being pended - * (which may be taken in preference to the one we started with - * if it has higher priority). - */ - stacked_ok =3D stacked_ok && - v7m_stack_write(cpu, frameptr, env->regs[0], mmu_idx, STACK_NORMAL= ) && - v7m_stack_write(cpu, frameptr + 4, env->regs[1], - mmu_idx, STACK_NORMAL) && - v7m_stack_write(cpu, frameptr + 8, env->regs[2], - mmu_idx, STACK_NORMAL) && - v7m_stack_write(cpu, frameptr + 12, env->regs[3], - mmu_idx, STACK_NORMAL) && - v7m_stack_write(cpu, frameptr + 16, env->regs[12], - mmu_idx, STACK_NORMAL) && - v7m_stack_write(cpu, frameptr + 20, env->regs[14], - mmu_idx, STACK_NORMAL) && - v7m_stack_write(cpu, frameptr + 24, env->regs[15], - mmu_idx, STACK_NORMAL) && - v7m_stack_write(cpu, frameptr + 28, xpsr, mmu_idx, STACK_NORMAL); - - if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) { - /* FPU is active, try to save its registers */ - bool fpccr_s =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; - bool lspact =3D env->v7m.fpccr[fpccr_s] & R_V7M_FPCCR_LSPACT_MASK; - - if (lspact && arm_feature(env, ARM_FEATURE_M_SECURITY)) { - qemu_log_mask(CPU_LOG_INT, - "...SecureFault because LSPACT and FPCA both set= \n"); - env->v7m.sfsr |=3D R_V7M_SFSR_LSERR_MASK; - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); - } else if (!env->v7m.secure && !nsacr_cp10) { - qemu_log_mask(CPU_LOG_INT, - "...Secure UsageFault with CFSR.NOCP because " - "NSACR.CP10 prevents stacking FP regs\n"); - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, M_REG_S); - env->v7m.cfsr[M_REG_S] |=3D R_V7M_CFSR_NOCP_MASK; - } else { - if (!(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPEN_MASK)) { - /* Lazy stacking disabled, save registers now */ - int i; - bool cpacr_pass =3D v7m_cpacr_pass(env, env->v7m.secure, - arm_current_el(env) !=3D = 0); - - if (stacked_ok && !cpacr_pass) { - /* - * Take UsageFault if CPACR forbids access. The pseudo= code - * here does a full CheckCPEnabled() but we know the N= SACR - * check can never fail as we have already handled tha= t. - */ - qemu_log_mask(CPU_LOG_INT, - "...UsageFault with CFSR.NOCP because " - "CPACR.CP10 prevents stacking FP regs\n"= ); - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, - env->v7m.secure); - env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_NOCP_MA= SK; - stacked_ok =3D false; - } - - for (i =3D 0; i < ((framesize =3D=3D 0xa8) ? 32 : 16); i += =3D 2) { - uint64_t dn =3D *aa32_vfp_dreg(env, i / 2); - uint32_t faddr =3D frameptr + 0x20 + 4 * i; - uint32_t slo =3D extract64(dn, 0, 32); - uint32_t shi =3D extract64(dn, 32, 32); - - if (i >=3D 16) { - faddr +=3D 8; /* skip the slot for the FPSCR */ - } - stacked_ok =3D stacked_ok && - v7m_stack_write(cpu, faddr, slo, - mmu_idx, STACK_NORMAL) && - v7m_stack_write(cpu, faddr + 4, shi, - mmu_idx, STACK_NORMAL); - } - stacked_ok =3D stacked_ok && - v7m_stack_write(cpu, frameptr + 0x60, - vfp_get_fpscr(env), mmu_idx, STACK_NOR= MAL); - if (cpacr_pass) { - for (i =3D 0; i < ((framesize =3D=3D 0xa8) ? 32 : 16);= i +=3D 2) { - *aa32_vfp_dreg(env, i / 2) =3D 0; - } - vfp_set_fpscr(env, 0); - } - } else { - /* Lazy stacking enabled, save necessary info to stack lat= er */ - v7m_update_fpccr(env, frameptr + 0x20, true); - } - } - } - - /* - * If we broke a stack limit then SP was already updated earlier; - * otherwise we update SP regardless of whether any of the stack - * accesses failed or we took some other kind of fault. - */ - if (!limitviol) { - env->regs[13] =3D frameptr; - } - - return !stacked_ok; -} - -static void do_v7m_exception_exit(ARMCPU *cpu) -{ - CPUARMState *env =3D &cpu->env; - uint32_t excret; - uint32_t xpsr, xpsr_mask; - bool ufault =3D false; - bool sfault =3D false; - bool return_to_sp_process; - bool return_to_handler; - bool rettobase =3D false; - bool exc_secure =3D false; - bool return_to_secure; - bool ftype; - bool restore_s16_s31 =3D false; - - /* - * If we're not in Handler mode then jumps to magic exception-exit - * addresses don't have magic behaviour. However for the v8M - * security extensions the magic secure-function-return has to - * work in thread mode too, so to avoid doing an extra check in - * the generated code we allow exception-exit magic to also cause the - * internal exception and bring us here in thread mode. Correct code - * will never try to do this (the following insn fetch will always - * fault) so we the overhead of having taken an unnecessary exception - * doesn't matter. - */ - if (!arm_v7m_is_handler_mode(env)) { - return; - } - - /* - * In the spec pseudocode ExceptionReturn() is called directly - * from BXWritePC() and gets the full target PC value including - * bit zero. In QEMU's implementation we treat it as a normal - * jump-to-register (which is then caught later on), and so split - * the target value up between env->regs[15] and env->thumb in - * gen_bx(). Reconstitute it. - */ - excret =3D env->regs[15]; - if (env->thumb) { - excret |=3D 1; - } - - qemu_log_mask(CPU_LOG_INT, "Exception return: magic PC %" PRIx32 - " previous exception %d\n", - excret, env->v7m.exception); - - if ((excret & R_V7M_EXCRET_RES1_MASK) !=3D R_V7M_EXCRET_RES1_MASK) { - qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in excep= tion " - "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", - excret); - } - - ftype =3D excret & R_V7M_EXCRET_FTYPE_MASK; - - if (!ftype && !cpu_isar_feature(aa32_vfp_simd, cpu)) { - qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception= " - "exit PC value 0x%" PRIx32 " is UNPREDICTABLE " - "if FPU not present\n", - excret); - ftype =3D true; - } - - if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - /* - * EXC_RETURN.ES validation check (R_SMFL). We must do this before - * we pick which FAULTMASK to clear. - */ - if (!env->v7m.secure && - ((excret & R_V7M_EXCRET_ES_MASK) || - !(excret & R_V7M_EXCRET_DCRS_MASK))) { - sfault =3D 1; - /* For all other purposes, treat ES as 0 (R_HXSR) */ - excret &=3D ~R_V7M_EXCRET_ES_MASK; - } - exc_secure =3D excret & R_V7M_EXCRET_ES_MASK; - } - - if (env->v7m.exception !=3D ARMV7M_EXCP_NMI) { - /* - * Auto-clear FAULTMASK on return from other than NMI. - * If the security extension is implemented then this only - * happens if the raw execution priority is >=3D 0; the - * value of the ES bit in the exception return value indicates - * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) - */ - if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - if (armv7m_nvic_raw_execution_priority(env->nvic) >=3D 0) { - env->v7m.faultmask[exc_secure] =3D 0; - } - } else { - env->v7m.faultmask[M_REG_NS] =3D 0; - } - } - - switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception, - exc_secure)) { - case -1: - /* attempt to exit an exception that isn't active */ - ufault =3D true; - break; - case 0: - /* still an irq active now */ - break; - case 1: - /* - * We returned to base exception level, no nesting. - * (In the pseudocode this is written using "NestedActivation !=3D= 1" - * where we have 'rettobase =3D=3D false'.) - */ - rettobase =3D true; - break; - default: - g_assert_not_reached(); - } - - return_to_handler =3D !(excret & R_V7M_EXCRET_MODE_MASK); - return_to_sp_process =3D excret & R_V7M_EXCRET_SPSEL_MASK; - return_to_secure =3D arm_feature(env, ARM_FEATURE_M_SECURITY) && - (excret & R_V7M_EXCRET_S_MASK); - - if (arm_feature(env, ARM_FEATURE_V8)) { - if (!arm_feature(env, ARM_FEATURE_M_SECURITY)) { - /* - * UNPREDICTABLE if S =3D=3D 1 or DCRS =3D=3D 0 or ES =3D=3D 1= (R_XLCP); - * we choose to take the UsageFault. - */ - if ((excret & R_V7M_EXCRET_S_MASK) || - (excret & R_V7M_EXCRET_ES_MASK) || - !(excret & R_V7M_EXCRET_DCRS_MASK)) { - ufault =3D true; - } - } - if (excret & R_V7M_EXCRET_RES0_MASK) { - ufault =3D true; - } - } else { - /* For v7M we only recognize certain combinations of the low bits = */ - switch (excret & 0xf) { - case 1: /* Return to Handler */ - break; - case 13: /* Return to Thread using Process stack */ - case 9: /* Return to Thread using Main stack */ - /* - * We only need to check NONBASETHRDENA for v7M, because in - * v8M this bit does not exist (it is RES1). - */ - if (!rettobase && - !(env->v7m.ccr[env->v7m.secure] & - R_V7M_CCR_NONBASETHRDENA_MASK)) { - ufault =3D true; - } - break; - default: - ufault =3D true; - } - } - - /* - * Set CONTROL.SPSEL from excret.SPSEL. Since we're still in - * Handler mode (and will be until we write the new XPSR.Interrupt - * field) this does not switch around the current stack pointer. - * We must do this before we do any kind of tailchaining, including - * for the derived exceptions on integrity check failures, or we will - * give the guest an incorrect EXCRET.SPSEL value on exception entry. - */ - write_v7m_control_spsel_for_secstate(env, return_to_sp_process, exc_se= cure); - - /* - * Clear scratch FP values left in caller saved registers; this - * must happen before any kind of tail chaining. - */ - if ((env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_CLRONRET_MASK) && - (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) { - if (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPACT_MASK) { - env->v7m.sfsr |=3D R_V7M_SFSR_LSERR_MASK; - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); - qemu_log_mask(CPU_LOG_INT, "...taking SecureFault on existing " - "stackframe: error during lazy state deactivatio= n\n"); - v7m_exception_taken(cpu, excret, true, false); - return; - } else { - if (arm_feature(env, ARM_FEATURE_V8_1M)) { - /* v8.1M adds this NOCP check */ - bool nsacr_pass =3D exc_secure || - extract32(env->v7m.nsacr, 10, 1); - bool cpacr_pass =3D v7m_cpacr_pass(env, exc_secure, true); - if (!nsacr_pass) { - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, = true); - env->v7m.cfsr[M_REG_S] |=3D R_V7M_CFSR_NOCP_MASK; - qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on ex= isting " - "stackframe: NSACR prevents clearing FPU registers= \n"); - v7m_exception_taken(cpu, excret, true, false); - } else if (!cpacr_pass) { - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, - exc_secure); - env->v7m.cfsr[exc_secure] |=3D R_V7M_CFSR_NOCP_MASK; - qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on ex= isting " - "stackframe: CPACR prevents clearing FPU registers= \n"); - v7m_exception_taken(cpu, excret, true, false); - } - } - /* Clear s0..s15 and FPSCR; TODO also VPR when MVE is implemen= ted */ - int i; - - for (i =3D 0; i < 16; i +=3D 2) { - *aa32_vfp_dreg(env, i / 2) =3D 0; - } - vfp_set_fpscr(env, 0); - } - } - - if (sfault) { - env->v7m.sfsr |=3D R_V7M_SFSR_INVER_MASK; - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); - qemu_log_mask(CPU_LOG_INT, "...taking SecureFault on existing " - "stackframe: failed EXC_RETURN.ES validity check\n"); - v7m_exception_taken(cpu, excret, true, false); - return; - } - - if (ufault) { - /* - * Bad exception return: instead of popping the exception - * stack, directly take a usage fault on the current stack. - */ - env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.sec= ure); - qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " - "stackframe: failed exception return integrity check= \n"); - v7m_exception_taken(cpu, excret, true, false); - return; - } - - /* - * Tailchaining: if there is currently a pending exception that - * is high enough priority to preempt execution at the level we're - * about to return to, then just directly take that exception now, - * avoiding an unstack-and-then-stack. Note that now we have - * deactivated the previous exception by calling armv7m_nvic_complete_= irq() - * our current execution priority is already the execution priority we= are - * returning to -- none of the state we would unstack or set based on - * the EXCRET value affects it. - */ - if (armv7m_nvic_can_take_pending_exception(env->nvic)) { - qemu_log_mask(CPU_LOG_INT, "...tailchaining to pending exception\n= "); - v7m_exception_taken(cpu, excret, true, false); - return; - } - - switch_v7m_security_state(env, return_to_secure); - - { - /* - * The stack pointer we should be reading the exception frame from - * depends on bits in the magic exception return type value (and - * for v8M isn't necessarily the stack pointer we will eventually - * end up resuming execution with). Get a pointer to the location - * in the CPU state struct where the SP we need is currently being - * stored; we will use and modify it in place. - * We use this limited C variable scope so we don't accidentally - * use 'frame_sp_p' after we do something that makes it invalid. - */ - bool spsel =3D env->v7m.control[return_to_secure] & R_V7M_CONTROL_= SPSEL_MASK; - uint32_t *frame_sp_p =3D get_v7m_sp_ptr(env, - return_to_secure, - !return_to_handler, - spsel); - uint32_t frameptr =3D *frame_sp_p; - bool pop_ok =3D true; - ARMMMUIdx mmu_idx; - bool return_to_priv =3D return_to_handler || - !(env->v7m.control[return_to_secure] & R_V7M_CONTROL_NPRIV_MAS= K); - - mmu_idx =3D arm_v7m_mmu_idx_for_secstate_and_priv(env, return_to_s= ecure, - return_to_priv); - - if (!QEMU_IS_ALIGNED(frameptr, 8) && - arm_feature(env, ARM_FEATURE_V8)) { - qemu_log_mask(LOG_GUEST_ERROR, - "M profile exception return with non-8-aligned S= P " - "for destination state is UNPREDICTABLE\n"); - } - - /* Do we need to pop callee-saved registers? */ - if (return_to_secure && - ((excret & R_V7M_EXCRET_ES_MASK) =3D=3D 0 || - (excret & R_V7M_EXCRET_DCRS_MASK) =3D=3D 0)) { - uint32_t actual_sig; - - pop_ok =3D v7m_stack_read(cpu, &actual_sig, frameptr, mmu_idx); - - if (pop_ok && v7m_integrity_sig(env, excret) !=3D actual_sig) { - /* Take a SecureFault on the current stack */ - env->v7m.sfsr |=3D R_V7M_SFSR_INVIS_MASK; - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, fal= se); - qemu_log_mask(CPU_LOG_INT, "...taking SecureFault on exist= ing " - "stackframe: failed exception return integri= ty " - "signature check\n"); - v7m_exception_taken(cpu, excret, true, false); - return; - } - - pop_ok =3D pop_ok && - v7m_stack_read(cpu, &env->regs[4], frameptr + 0x8, mmu_idx= ) && - v7m_stack_read(cpu, &env->regs[5], frameptr + 0xc, mmu_idx= ) && - v7m_stack_read(cpu, &env->regs[6], frameptr + 0x10, mmu_id= x) && - v7m_stack_read(cpu, &env->regs[7], frameptr + 0x14, mmu_id= x) && - v7m_stack_read(cpu, &env->regs[8], frameptr + 0x18, mmu_id= x) && - v7m_stack_read(cpu, &env->regs[9], frameptr + 0x1c, mmu_id= x) && - v7m_stack_read(cpu, &env->regs[10], frameptr + 0x20, mmu_i= dx) && - v7m_stack_read(cpu, &env->regs[11], frameptr + 0x24, mmu_i= dx); - - frameptr +=3D 0x28; - } - - /* Pop registers */ - pop_ok =3D pop_ok && - v7m_stack_read(cpu, &env->regs[0], frameptr, mmu_idx) && - v7m_stack_read(cpu, &env->regs[1], frameptr + 0x4, mmu_idx) && - v7m_stack_read(cpu, &env->regs[2], frameptr + 0x8, mmu_idx) && - v7m_stack_read(cpu, &env->regs[3], frameptr + 0xc, mmu_idx) && - v7m_stack_read(cpu, &env->regs[12], frameptr + 0x10, mmu_idx) = && - v7m_stack_read(cpu, &env->regs[14], frameptr + 0x14, mmu_idx) = && - v7m_stack_read(cpu, &env->regs[15], frameptr + 0x18, mmu_idx) = && - v7m_stack_read(cpu, &xpsr, frameptr + 0x1c, mmu_idx); - - if (!pop_ok) { - /* - * v7m_stack_read() pended a fault, so take it (as a tail - * chained exception on the same stack frame) - */ - qemu_log_mask(CPU_LOG_INT, "...derived exception on unstacking= \n"); - v7m_exception_taken(cpu, excret, true, false); - return; - } - - /* - * Returning from an exception with a PC with bit 0 set is defined - * behaviour on v8M (bit 0 is ignored), but for v7M it was specifi= ed - * to be UNPREDICTABLE. In practice actual v7M hardware seems to i= gnore - * the lsbit, and there are several RTOSes out there which incorre= ctly - * assume the r15 in the stack frame should be a Thumb-style "lsbit - * indicates ARM/Thumb" value, so ignore the bit on v7M as well, b= ut - * complain about the badly behaved guest. - */ - if (env->regs[15] & 1) { - env->regs[15] &=3D ~1U; - if (!arm_feature(env, ARM_FEATURE_V8)) { - qemu_log_mask(LOG_GUEST_ERROR, - "M profile return from interrupt with misali= gned " - "PC is UNPREDICTABLE on v7M\n"); - } - } - - if (arm_feature(env, ARM_FEATURE_V8)) { - /* - * For v8M we have to check whether the xPSR exception field - * matches the EXCRET value for return to handler/thread - * before we commit to changing the SP and xPSR. - */ - bool will_be_handler =3D (xpsr & XPSR_EXCP) !=3D 0; - if (return_to_handler !=3D will_be_handler) { - /* - * Take an INVPC UsageFault on the current stack. - * By this point we will have switched to the security sta= te - * for the background state, so this UsageFault will target - * that state. - */ - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, - env->v7m.secure); - env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; - qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existi= ng " - "stackframe: failed exception return integri= ty " - "check\n"); - v7m_exception_taken(cpu, excret, true, false); - return; - } - } - - if (!ftype) { - /* FP present and we need to handle it */ - if (!return_to_secure && - (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPACT_MASK)) { - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, fal= se); - env->v7m.sfsr |=3D R_V7M_SFSR_LSERR_MASK; - qemu_log_mask(CPU_LOG_INT, - "...taking SecureFault on existing stackfram= e: " - "Secure LSPACT set but exception return is " - "not to secure state\n"); - v7m_exception_taken(cpu, excret, true, false); - return; - } - - restore_s16_s31 =3D return_to_secure && - (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK); - - if (env->v7m.fpccr[return_to_secure] & R_V7M_FPCCR_LSPACT_MASK= ) { - /* State in FPU is still valid, just clear LSPACT */ - env->v7m.fpccr[return_to_secure] &=3D ~R_V7M_FPCCR_LSPACT_= MASK; - } else { - int i; - uint32_t fpscr; - bool cpacr_pass, nsacr_pass; - - cpacr_pass =3D v7m_cpacr_pass(env, return_to_secure, - return_to_priv); - nsacr_pass =3D return_to_secure || - extract32(env->v7m.nsacr, 10, 1); - - if (!cpacr_pass) { - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, - return_to_secure); - env->v7m.cfsr[return_to_secure] |=3D R_V7M_CFSR_NOCP_M= ASK; - qemu_log_mask(CPU_LOG_INT, - "...taking UsageFault on existing " - "stackframe: CPACR.CP10 prevents unstack= ing " - "FP regs\n"); - v7m_exception_taken(cpu, excret, true, false); - return; - } else if (!nsacr_pass) { - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, = true); - env->v7m.cfsr[M_REG_S] |=3D R_V7M_CFSR_INVPC_MASK; - qemu_log_mask(CPU_LOG_INT, - "...taking Secure UsageFault on existing= " - "stackframe: NSACR.CP10 prevents unstack= ing " - "FP regs\n"); - v7m_exception_taken(cpu, excret, true, false); - return; - } - - for (i =3D 0; i < (restore_s16_s31 ? 32 : 16); i +=3D 2) { - uint32_t slo, shi; - uint64_t dn; - uint32_t faddr =3D frameptr + 0x20 + 4 * i; - - if (i >=3D 16) { - faddr +=3D 8; /* Skip the slot for the FPSCR */ - } - - pop_ok =3D pop_ok && - v7m_stack_read(cpu, &slo, faddr, mmu_idx) && - v7m_stack_read(cpu, &shi, faddr + 4, mmu_idx); - - if (!pop_ok) { - break; - } - - dn =3D (uint64_t)shi << 32 | slo; - *aa32_vfp_dreg(env, i / 2) =3D dn; - } - pop_ok =3D pop_ok && - v7m_stack_read(cpu, &fpscr, frameptr + 0x60, mmu_idx); - if (pop_ok) { - vfp_set_fpscr(env, fpscr); - } - if (!pop_ok) { - /* - * These regs are 0 if security extension present; - * otherwise merely UNKNOWN. We zero always. - */ - for (i =3D 0; i < (restore_s16_s31 ? 32 : 16); i +=3D = 2) { - *aa32_vfp_dreg(env, i / 2) =3D 0; - } - vfp_set_fpscr(env, 0); - } - } - } - env->v7m.control[M_REG_S] =3D FIELD_DP32(env->v7m.control[M_REG_S], - V7M_CONTROL, FPCA, !ftype); - - /* Commit to consuming the stack frame */ - frameptr +=3D 0x20; - if (!ftype) { - frameptr +=3D 0x48; - if (restore_s16_s31) { - frameptr +=3D 0x40; - } - } - /* - * Undo stack alignment (the SPREALIGN bit indicates that the orig= inal - * pre-exception SP was not 8-aligned and we added a padding word = to - * align it, so we undo this by ORing in the bit that increases it - * from the current 8-aligned value to the 8-unaligned value. (Add= ing 4 - * would work too but a logical OR is how the pseudocode specifies= it.) - */ - if (xpsr & XPSR_SPREALIGN) { - frameptr |=3D 4; - } - *frame_sp_p =3D frameptr; - } - - xpsr_mask =3D ~(XPSR_SPREALIGN | XPSR_SFPA); - if (!arm_feature(env, ARM_FEATURE_THUMB_DSP)) { - xpsr_mask &=3D ~XPSR_GE; - } - /* This xpsr_write() will invalidate frame_sp_p as it may switch stack= */ - xpsr_write(env, xpsr, xpsr_mask); - - if (env->v7m.secure) { - bool sfpa =3D xpsr & XPSR_SFPA; - - env->v7m.control[M_REG_S] =3D FIELD_DP32(env->v7m.control[M_REG_S], - V7M_CONTROL, SFPA, sfpa); - } - - /* - * The restored xPSR exception field will be zero if we're - * resuming in Thread mode. If that doesn't match what the - * exception return excret specified then this is a UsageFault. - * v7M requires we make this check here; v8M did it earlier. - */ - if (return_to_handler !=3D arm_v7m_is_handler_mode(env)) { - /* - * Take an INVPC UsageFault by pushing the stack again; - * we know we're v7M so this is never a Secure UsageFault. - */ - bool ignore_stackfaults; - - assert(!arm_feature(env, ARM_FEATURE_V8)); - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, false); - env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; - ignore_stackfaults =3D v7m_push_stack(cpu); - qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe= : " - "failed exception return integrity check\n"); - v7m_exception_taken(cpu, excret, false, ignore_stackfaults); - return; - } - - /* Otherwise, we have a successful exception exit. */ - arm_clear_exclusive(env); - arm_rebuild_hflags(env); - qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); -} - -static bool do_v7m_function_return(ARMCPU *cpu) -{ - /* - * v8M security extensions magic function return. - * We may either: - * (1) throw an exception (longjump) - * (2) return true if we successfully handled the function return - * (3) return false if we failed a consistency check and have - * pended a UsageFault that needs to be taken now - * - * At this point the magic return value is split between env->regs[15] - * and env->thumb. We don't bother to reconstitute it because we don't - * need it (all values are handled the same way). - */ - CPUARMState *env =3D &cpu->env; - uint32_t newpc, newpsr, newpsr_exc; - - qemu_log_mask(CPU_LOG_INT, "...really v7M secure function return\n"); - - { - bool threadmode, spsel; - TCGMemOpIdx oi; - ARMMMUIdx mmu_idx; - uint32_t *frame_sp_p; - uint32_t frameptr; - - /* Pull the return address and IPSR from the Secure stack */ - threadmode =3D !arm_v7m_is_handler_mode(env); - spsel =3D env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK; - - frame_sp_p =3D get_v7m_sp_ptr(env, true, threadmode, spsel); - frameptr =3D *frame_sp_p; - - /* - * These loads may throw an exception (for MPU faults). We want to - * do them as secure, so work out what MMU index that is. - */ - mmu_idx =3D arm_v7m_mmu_idx_for_secstate(env, true); - oi =3D make_memop_idx(MO_LE, arm_to_core_mmu_idx(mmu_idx)); - newpc =3D helper_le_ldul_mmu(env, frameptr, oi, 0); - newpsr =3D helper_le_ldul_mmu(env, frameptr + 4, oi, 0); - - /* Consistency checks on new IPSR */ - newpsr_exc =3D newpsr & XPSR_EXCP; - if (!((env->v7m.exception =3D=3D 0 && newpsr_exc =3D=3D 0) || - (env->v7m.exception =3D=3D 1 && newpsr_exc !=3D 0))) { - /* Pend the fault and tell our caller to take it */ - env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, - env->v7m.secure); - qemu_log_mask(CPU_LOG_INT, - "...taking INVPC UsageFault: " - "IPSR consistency check failed\n"); - return false; - } - - *frame_sp_p =3D frameptr + 8; - } - - /* This invalidates frame_sp_p */ - switch_v7m_security_state(env, true); - env->v7m.exception =3D newpsr_exc; - env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_SFPA_MASK; - if (newpsr & XPSR_SFPA) { - env->v7m.control[M_REG_S] |=3D R_V7M_CONTROL_SFPA_MASK; - } - xpsr_write(env, 0, XPSR_IT); - env->thumb =3D newpc & 1; - env->regs[15] =3D newpc & ~1; - arm_rebuild_hflags(env); - - qemu_log_mask(CPU_LOG_INT, "...function return successful\n"); - return true; -} - -static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, - uint32_t addr, uint16_t *insn) -{ - /* - * Load a 16-bit portion of a v7M instruction, returning true on succe= ss, - * or false on failure (in which case we will have pended the appropri= ate - * exception). - * We need to do the instruction fetch's MPU and SAU checks - * like this because there is no MMU index that would allow - * doing the load with a single function call. Instead we must - * first check that the security attributes permit the load - * and that they don't mismatch on the two halves of the instruction, - * and then we do the load as a secure load (ie using the security - * attributes of the address, not the CPU, as architecturally required= ). - */ - CPUState *cs =3D CPU(cpu); - CPUARMState *env =3D &cpu->env; - V8M_SAttributes sattrs =3D {}; - MemTxAttrs attrs =3D {}; - ARMMMUFaultInfo fi =3D {}; - ARMCacheAttrs cacheattrs =3D {}; - MemTxResult txres; - target_ulong page_size; - hwaddr physaddr; - int prot; - - v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs); - if (!sattrs.nsc || sattrs.ns) { - /* - * This must be the second half of the insn, and it straddles a - * region boundary with the second half not being S&NSC. - */ - env->v7m.sfsr |=3D R_V7M_SFSR_INVEP_MASK; - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); - qemu_log_mask(CPU_LOG_INT, - "...really SecureFault with SFSR.INVEP\n"); - return false; - } - if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &physaddr, - &attrs, &prot, &page_size, &fi, &cacheattrs)) { - /* the MPU lookup failed */ - env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_IACCVIOL_MASK; - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secur= e); - qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL= \n"); - return false; - } - *insn =3D address_space_lduw_le(arm_addressspace(cs, attrs), physaddr, - attrs, &txres); - if (txres !=3D MEMTX_OK) { - env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_IBUSERR_MASK; - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); - qemu_log_mask(CPU_LOG_INT, "...really BusFault with CFSR.IBUSERR\n= "); - return false; - } - return true; -} - -static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx, - uint32_t addr, uint32_t *spdata) -{ - /* - * Read a word of data from the stack for the SG instruction, - * writing the value into *spdata. If the load succeeds, return - * true; otherwise pend an appropriate exception and return false. - * (We can't use data load helpers here that throw an exception - * because of the context we're called in, which is halfway through - * arm_v7m_cpu_do_interrupt().) - */ - CPUState *cs =3D CPU(cpu); - CPUARMState *env =3D &cpu->env; - MemTxAttrs attrs =3D {}; - MemTxResult txres; - target_ulong page_size; - hwaddr physaddr; - int prot; - ARMMMUFaultInfo fi =3D {}; - ARMCacheAttrs cacheattrs =3D {}; - uint32_t value; - - if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr, - &attrs, &prot, &page_size, &fi, &cacheattrs)) { - /* MPU/SAU lookup failed */ - if (fi.type =3D=3D ARMFault_QEMU_SFault) { - qemu_log_mask(CPU_LOG_INT, - "...SecureFault during stack word read\n"); - env->v7m.sfsr |=3D R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVAL= ID_MASK; - env->v7m.sfar =3D addr; - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); - } else { - qemu_log_mask(CPU_LOG_INT, - "...MemManageFault during stack word read\n"); - env->v7m.cfsr[M_REG_S] |=3D R_V7M_CFSR_DACCVIOL_MASK | - R_V7M_CFSR_MMARVALID_MASK; - env->v7m.mmfar[M_REG_S] =3D addr; - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, false); - } - return false; - } - value =3D address_space_ldl(arm_addressspace(cs, attrs), physaddr, - attrs, &txres); - if (txres !=3D MEMTX_OK) { - /* BusFault trying to read the data */ - qemu_log_mask(CPU_LOG_INT, - "...BusFault during stack word read\n"); - env->v7m.cfsr[M_REG_NS] |=3D - (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK); - env->v7m.bfar =3D addr; - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); - return false; - } - - *spdata =3D value; - return true; -} - -static bool v7m_handle_execute_nsc(ARMCPU *cpu) -{ - /* - * Check whether this attempt to execute code in a Secure & NS-Callable - * memory region is for an SG instruction; if so, then emulate the - * effect of the SG instruction and return true. Otherwise pend - * the correct kind of exception and return false. - */ - CPUARMState *env =3D &cpu->env; - ARMMMUIdx mmu_idx; - uint16_t insn; - - /* - * We should never get here unless get_phys_addr_pmsav8() caused - * an exception for NS executing in S&NSC memory. - */ - assert(!env->v7m.secure); - assert(arm_feature(env, ARM_FEATURE_M_SECURITY)); - - /* We want to do the MPU lookup as secure; work out what mmu_idx that = is */ - mmu_idx =3D arm_v7m_mmu_idx_for_secstate(env, true); - - if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) { - return false; - } - - if (!env->thumb) { - goto gen_invep; - } - - if (insn !=3D 0xe97f) { - /* - * Not an SG instruction first half (we choose the IMPDEF - * early-SG-check option). - */ - goto gen_invep; - } - - if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) { - return false; - } - - if (insn !=3D 0xe97f) { - /* - * Not an SG instruction second half (yes, both halves of the SG - * insn have the same hex value) - */ - goto gen_invep; - } - - /* - * OK, we have confirmed that we really have an SG instruction. - * We know we're NS in S memory so don't need to repeat those checks. - */ - qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx= 32 - ", executing it\n", env->regs[15]); - - if (cpu_isar_feature(aa32_m_sec_state, cpu) && - !arm_v7m_is_handler_mode(env)) { - /* - * v8.1M exception stack frame integrity check. Note that we - * must perform the memory access even if CCR_S.TRD is zero - * and we aren't going to check what the data loaded is. - */ - uint32_t spdata, sp; - - /* - * We know we are currently NS, so the S stack pointers must be - * in other_ss_{psp,msp}, not in regs[13]/other_sp. - */ - sp =3D v7m_using_psp(env) ? env->v7m.other_ss_psp : env->v7m.other= _ss_msp; - if (!v7m_read_sg_stack_word(cpu, mmu_idx, sp, &spdata)) { - /* Stack access failed and an exception has been pended */ - return false; - } - - if (env->v7m.ccr[M_REG_S] & R_V7M_CCR_TRD_MASK) { - if (((spdata & ~1) =3D=3D 0xfefa125a) || - !(env->v7m.control[M_REG_S] & 1)) { - goto gen_invep; - } - } - } - - env->regs[14] &=3D ~1; - env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_SFPA_MASK; - switch_v7m_security_state(env, true); - xpsr_write(env, 0, XPSR_IT); - env->regs[15] +=3D 4; - arm_rebuild_hflags(env); - return true; - -gen_invep: - env->v7m.sfsr |=3D R_V7M_SFSR_INVEP_MASK; - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); - qemu_log_mask(CPU_LOG_INT, - "...really SecureFault with SFSR.INVEP\n"); - return false; -} - -void arm_v7m_cpu_do_interrupt(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - uint32_t lr; - bool ignore_stackfaults; - - arm_log_exception(cs->exception_index); - - /* - * For exceptions we just mark as pending on the NVIC, and let that - * handle it. - */ - switch (cs->exception_index) { - case EXCP_UDEF: - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.sec= ure); - env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_UNDEFINSTR_MASK; - break; - case EXCP_NOCP: - { - /* - * NOCP might be directed to something other than the current - * security state if this fault is because of NSACR; we indicate - * the target security state using exception.target_el. - */ - int target_secstate; - - if (env->exception.target_el =3D=3D 3) { - target_secstate =3D M_REG_S; - } else { - target_secstate =3D env->v7m.secure; - } - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, target_secst= ate); - env->v7m.cfsr[target_secstate] |=3D R_V7M_CFSR_NOCP_MASK; - break; - } - case EXCP_INVSTATE: - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.sec= ure); - env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVSTATE_MASK; - break; - case EXCP_STKOF: - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.sec= ure); - env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_STKOF_MASK; - break; - case EXCP_LSERR: - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); - env->v7m.sfsr |=3D R_V7M_SFSR_LSERR_MASK; - break; - case EXCP_UNALIGNED: - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.sec= ure); - env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_UNALIGNED_MASK; - break; - case EXCP_SWI: - /* The PC already points to the next instruction. */ - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secur= e); - break; - case EXCP_PREFETCH_ABORT: - case EXCP_DATA_ABORT: - /* - * Note that for M profile we don't have a guest facing FSR, but - * the env->exception.fsr will be populated by the code that - * raises the fault, in the A profile short-descriptor format. - */ - switch (env->exception.fsr & 0xf) { - case M_FAKE_FSR_NSC_EXEC: - /* - * Exception generated when we try to execute code at an addre= ss - * which is marked as Secure & Non-Secure Callable and the CPU - * is in the Non-Secure state. The only instruction which can - * be executed like this is SG (and that only if both halves of - * the SG instruction have the same security attributes.) - * Everything else must generate an INVEP SecureFault, so we - * emulate the SG instruction here. - */ - if (v7m_handle_execute_nsc(cpu)) { - return; - } - break; - case M_FAKE_FSR_SFAULT: - /* - * Various flavours of SecureFault for attempts to execute or - * access data in the wrong security state. - */ - switch (cs->exception_index) { - case EXCP_PREFETCH_ABORT: - if (env->v7m.secure) { - env->v7m.sfsr |=3D R_V7M_SFSR_INVTRAN_MASK; - qemu_log_mask(CPU_LOG_INT, - "...really SecureFault with SFSR.INVTRAN= \n"); - } else { - env->v7m.sfsr |=3D R_V7M_SFSR_INVEP_MASK; - qemu_log_mask(CPU_LOG_INT, - "...really SecureFault with SFSR.INVEP\n= "); - } - break; - case EXCP_DATA_ABORT: - /* This must be an NS access to S memory */ - env->v7m.sfsr |=3D R_V7M_SFSR_AUVIOL_MASK; - qemu_log_mask(CPU_LOG_INT, - "...really SecureFault with SFSR.AUVIOL\n"); - break; - } - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); - break; - case 0x8: /* External Abort */ - switch (cs->exception_index) { - case EXCP_PREFETCH_ABORT: - env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_IBUSERR_MASK; - qemu_log_mask(CPU_LOG_INT, "...with CFSR.IBUSERR\n"); - break; - case EXCP_DATA_ABORT: - env->v7m.cfsr[M_REG_NS] |=3D - (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK= ); - env->v7m.bfar =3D env->exception.vaddress; - qemu_log_mask(CPU_LOG_INT, - "...with CFSR.PRECISERR and BFAR 0x%x\n", - env->v7m.bfar); - break; - } - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); - break; - default: - /* - * All other FSR values are either MPU faults or "can't happen - * for M profile" cases. - */ - switch (cs->exception_index) { - case EXCP_PREFETCH_ABORT: - env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_IACCVIOL_MA= SK; - qemu_log_mask(CPU_LOG_INT, "...with CFSR.IACCVIOL\n"); - break; - case EXCP_DATA_ABORT: - env->v7m.cfsr[env->v7m.secure] |=3D - (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK); - env->v7m.mmfar[env->v7m.secure] =3D env->exception.vaddres= s; - qemu_log_mask(CPU_LOG_INT, - "...with CFSR.DACCVIOL and MMFAR 0x%x\n", - env->v7m.mmfar[env->v7m.secure]); - break; - } - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, - env->v7m.secure); - break; - } - break; - case EXCP_SEMIHOST: - qemu_log_mask(CPU_LOG_INT, - "...handling as semihosting call 0x%x\n", - env->regs[0]); -#ifdef CONFIG_TCG - env->regs[0] =3D do_common_semihosting(cs); -#else - g_assert_not_reached(); -#endif - env->regs[15] +=3D env->thumb ? 2 : 4; - return; - case EXCP_BKPT: - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false); - break; - case EXCP_IRQ: - break; - case EXCP_EXCEPTION_EXIT: - if (env->regs[15] < EXC_RETURN_MIN_MAGIC) { - /* Must be v8M security extension function return */ - assert(env->regs[15] >=3D FNC_RETURN_MIN_MAGIC); - assert(arm_feature(env, ARM_FEATURE_M_SECURITY)); - if (do_v7m_function_return(cpu)) { - return; - } - } else { - do_v7m_exception_exit(cpu); - return; - } - break; - case EXCP_LAZYFP: - /* - * We already pended the specific exception in the NVIC in the - * v7m_preserve_fp_state() helper function. - */ - break; - default: - cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); - return; /* Never happens. Keep compiler happy. */ - } - - if (arm_feature(env, ARM_FEATURE_V8)) { - lr =3D R_V7M_EXCRET_RES1_MASK | - R_V7M_EXCRET_DCRS_MASK; - /* - * The S bit indicates whether we should return to Secure - * or NonSecure (ie our current state). - * The ES bit indicates whether we're taking this exception - * to Secure or NonSecure (ie our target state). We set it - * later, in v7m_exception_taken(). - * The SPSEL bit is also set in v7m_exception_taken() for v8M. - * This corresponds to the ARM ARM pseudocode for v8M setting - * some LR bits in PushStack() and some in ExceptionTaken(); - * the distinction matters for the tailchain cases where we - * can take an exception without pushing the stack. - */ - if (env->v7m.secure) { - lr |=3D R_V7M_EXCRET_S_MASK; - } - } else { - lr =3D R_V7M_EXCRET_RES1_MASK | - R_V7M_EXCRET_S_MASK | - R_V7M_EXCRET_DCRS_MASK | - R_V7M_EXCRET_ES_MASK; - if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) { - lr |=3D R_V7M_EXCRET_SPSEL_MASK; - } - } - if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) { - lr |=3D R_V7M_EXCRET_FTYPE_MASK; - } - if (!arm_v7m_is_handler_mode(env)) { - lr |=3D R_V7M_EXCRET_MODE_MASK; - } - - ignore_stackfaults =3D v7m_push_stack(cpu); - v7m_exception_taken(cpu, lr, false, ignore_stackfaults); -} - -uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) -{ - unsigned el =3D arm_current_el(env); - - /* First handle registers which unprivileged can read */ - switch (reg) { - case 0 ... 7: /* xPSR sub-fields */ - return v7m_mrs_xpsr(env, reg, el); - case 20: /* CONTROL */ - return v7m_mrs_control(env, env->v7m.secure); - case 0x94: /* CONTROL_NS */ - /* - * We have to handle this here because unprivileged Secure code - * can read the NS CONTROL register. - */ - if (!env->v7m.secure) { - return 0; - } - return env->v7m.control[M_REG_NS] | - (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK); - } - - if (el =3D=3D 0) { - return 0; /* unprivileged reads others as zero */ - } - - if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - switch (reg) { - case 0x88: /* MSP_NS */ - if (!env->v7m.secure) { - return 0; - } - return env->v7m.other_ss_msp; - case 0x89: /* PSP_NS */ - if (!env->v7m.secure) { - return 0; - } - return env->v7m.other_ss_psp; - case 0x8a: /* MSPLIM_NS */ - if (!env->v7m.secure) { - return 0; - } - return env->v7m.msplim[M_REG_NS]; - case 0x8b: /* PSPLIM_NS */ - if (!env->v7m.secure) { - return 0; - } - return env->v7m.psplim[M_REG_NS]; - case 0x90: /* PRIMASK_NS */ - if (!env->v7m.secure) { - return 0; - } - return env->v7m.primask[M_REG_NS]; - case 0x91: /* BASEPRI_NS */ - if (!env->v7m.secure) { - return 0; - } - return env->v7m.basepri[M_REG_NS]; - case 0x93: /* FAULTMASK_NS */ - if (!env->v7m.secure) { - return 0; - } - return env->v7m.faultmask[M_REG_NS]; - case 0x98: /* SP_NS */ - { - /* - * This gives the non-secure SP selected based on whether we're - * currently in handler mode or not, using the NS CONTROL.SPSE= L. - */ - bool spsel =3D env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSE= L_MASK; - - if (!env->v7m.secure) { - return 0; - } - if (!arm_v7m_is_handler_mode(env) && spsel) { - return env->v7m.other_ss_psp; - } else { - return env->v7m.other_ss_msp; - } - } - default: - break; - } - } - - switch (reg) { - case 8: /* MSP */ - return v7m_using_psp(env) ? env->v7m.other_sp : env->regs[13]; - case 9: /* PSP */ - return v7m_using_psp(env) ? env->regs[13] : env->v7m.other_sp; - case 10: /* MSPLIM */ - if (!arm_feature(env, ARM_FEATURE_V8)) { - goto bad_reg; - } - return env->v7m.msplim[env->v7m.secure]; - case 11: /* PSPLIM */ - if (!arm_feature(env, ARM_FEATURE_V8)) { - goto bad_reg; - } - return env->v7m.psplim[env->v7m.secure]; - case 16: /* PRIMASK */ - return env->v7m.primask[env->v7m.secure]; - case 17: /* BASEPRI */ - case 18: /* BASEPRI_MAX */ - return env->v7m.basepri[env->v7m.secure]; - case 19: /* FAULTMASK */ - return env->v7m.faultmask[env->v7m.secure]; - default: - bad_reg: - qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special" - " register %d\n", reg); - return 0; - } -} - -void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) -{ - /* - * We're passed bits [11..0] of the instruction; extract - * SYSm and the mask bits. - * Invalid combinations of SYSm and mask are UNPREDICTABLE; - * we choose to treat them as if the mask bits were valid. - * NB that the pseudocode 'mask' variable is bits [11..10], - * whereas ours is [11..8]. - */ - uint32_t mask =3D extract32(maskreg, 8, 4); - uint32_t reg =3D extract32(maskreg, 0, 8); - int cur_el =3D arm_current_el(env); - - if (cur_el =3D=3D 0 && reg > 7 && reg !=3D 20) { - /* - * only xPSR sub-fields and CONTROL.SFPA may be written by - * unprivileged code - */ - return; - } - - if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - switch (reg) { - case 0x88: /* MSP_NS */ - if (!env->v7m.secure) { - return; - } - env->v7m.other_ss_msp =3D val; - return; - case 0x89: /* PSP_NS */ - if (!env->v7m.secure) { - return; - } - env->v7m.other_ss_psp =3D val; - return; - case 0x8a: /* MSPLIM_NS */ - if (!env->v7m.secure) { - return; - } - env->v7m.msplim[M_REG_NS] =3D val & ~7; - return; - case 0x8b: /* PSPLIM_NS */ - if (!env->v7m.secure) { - return; - } - env->v7m.psplim[M_REG_NS] =3D val & ~7; - return; - case 0x90: /* PRIMASK_NS */ - if (!env->v7m.secure) { - return; - } - env->v7m.primask[M_REG_NS] =3D val & 1; - return; - case 0x91: /* BASEPRI_NS */ - if (!env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_MAIN))= { - return; - } - env->v7m.basepri[M_REG_NS] =3D val & 0xff; - return; - case 0x93: /* FAULTMASK_NS */ - if (!env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_MAIN))= { - return; - } - env->v7m.faultmask[M_REG_NS] =3D val & 1; - return; - case 0x94: /* CONTROL_NS */ - if (!env->v7m.secure) { - return; - } - write_v7m_control_spsel_for_secstate(env, - val & R_V7M_CONTROL_SPSEL= _MASK, - M_REG_NS); - if (arm_feature(env, ARM_FEATURE_M_MAIN)) { - env->v7m.control[M_REG_NS] &=3D ~R_V7M_CONTROL_NPRIV_MASK; - env->v7m.control[M_REG_NS] |=3D val & R_V7M_CONTROL_NPRIV_= MASK; - } - /* - * SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 =3D=3D 0, - * RES0 if the FPU is not present, and is stored in the S bank - */ - if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) && - extract32(env->v7m.nsacr, 10, 1)) { - env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_FPCA_MASK; - env->v7m.control[M_REG_S] |=3D val & R_V7M_CONTROL_FPCA_MA= SK; - } - return; - case 0x98: /* SP_NS */ - { - /* - * This gives the non-secure SP selected based on whether we're - * currently in handler mode or not, using the NS CONTROL.SPSE= L. - */ - bool spsel =3D env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSE= L_MASK; - bool is_psp =3D !arm_v7m_is_handler_mode(env) && spsel; - uint32_t limit; - - if (!env->v7m.secure) { - return; - } - - limit =3D is_psp ? env->v7m.psplim[false] : env->v7m.msplim[fa= lse]; - - if (val < limit) { - CPUState *cs =3D env_cpu(env); - - cpu_restore_state(cs, GETPC(), true); - raise_exception(env, EXCP_STKOF, 0, 1); - } - - if (is_psp) { - env->v7m.other_ss_psp =3D val; - } else { - env->v7m.other_ss_msp =3D val; - } - return; - } - default: - break; - } - } - - switch (reg) { - case 0 ... 7: /* xPSR sub-fields */ - v7m_msr_xpsr(env, mask, reg, val); - break; - case 8: /* MSP */ - if (v7m_using_psp(env)) { - env->v7m.other_sp =3D val; - } else { - env->regs[13] =3D val; - } - break; - case 9: /* PSP */ - if (v7m_using_psp(env)) { - env->regs[13] =3D val; - } else { - env->v7m.other_sp =3D val; - } - break; - case 10: /* MSPLIM */ - if (!arm_feature(env, ARM_FEATURE_V8)) { - goto bad_reg; - } - env->v7m.msplim[env->v7m.secure] =3D val & ~7; - break; - case 11: /* PSPLIM */ - if (!arm_feature(env, ARM_FEATURE_V8)) { - goto bad_reg; - } - env->v7m.psplim[env->v7m.secure] =3D val & ~7; - break; - case 16: /* PRIMASK */ - env->v7m.primask[env->v7m.secure] =3D val & 1; - break; - case 17: /* BASEPRI */ - if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { - goto bad_reg; - } - env->v7m.basepri[env->v7m.secure] =3D val & 0xff; - break; - case 18: /* BASEPRI_MAX */ - if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { - goto bad_reg; - } - val &=3D 0xff; - if (val !=3D 0 && (val < env->v7m.basepri[env->v7m.secure] - || env->v7m.basepri[env->v7m.secure] =3D=3D 0)) { - env->v7m.basepri[env->v7m.secure] =3D val; - } - break; - case 19: /* FAULTMASK */ - if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { - goto bad_reg; - } - env->v7m.faultmask[env->v7m.secure] =3D val & 1; - break; - case 20: /* CONTROL */ - /* - * Writing to the SPSEL bit only has an effect if we are in - * thread mode; other bits can be updated by any privileged code. - * write_v7m_control_spsel() deals with updating the SPSEL bit in - * env->v7m.control, so we only need update the others. - * For v7M, we must just ignore explicit writes to SPSEL in handler - * mode; for v8M the write is permitted but will have no effect. - * All these bits are writes-ignored from non-privileged code, - * except for SFPA. - */ - if (cur_el > 0 && (arm_feature(env, ARM_FEATURE_V8) || - !arm_v7m_is_handler_mode(env))) { - write_v7m_control_spsel(env, (val & R_V7M_CONTROL_SPSEL_MASK) = !=3D 0); - } - if (cur_el > 0 && arm_feature(env, ARM_FEATURE_M_MAIN)) { - env->v7m.control[env->v7m.secure] &=3D ~R_V7M_CONTROL_NPRIV_MA= SK; - env->v7m.control[env->v7m.secure] |=3D val & R_V7M_CONTROL_NPR= IV_MASK; - } - if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { - /* - * SFPA is RAZ/WI from NS or if no FPU. - * FPCA is RO if NSACR.CP10 =3D=3D 0, RES0 if the FPU is not p= resent. - * Both are stored in the S bank. - */ - if (env->v7m.secure) { - env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_SFPA_MASK; - env->v7m.control[M_REG_S] |=3D val & R_V7M_CONTROL_SFPA_MA= SK; - } - if (cur_el > 0 && - (env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_SECURI= TY) || - extract32(env->v7m.nsacr, 10, 1))) { - env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_FPCA_MASK; - env->v7m.control[M_REG_S] |=3D val & R_V7M_CONTROL_FPCA_MA= SK; - } - } - break; - default: - bad_reg: - qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special" - " register %d\n", reg); - return; - } -} - -uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) -{ - /* Implement the TT instruction. op is bits [7:6] of the insn. */ - bool forceunpriv =3D op & 1; - bool alt =3D op & 2; - V8M_SAttributes sattrs =3D {}; - uint32_t tt_resp; - bool r, rw, nsr, nsrw, mrvalid; - int prot; - ARMMMUFaultInfo fi =3D {}; - MemTxAttrs attrs =3D {}; - hwaddr phys_addr; - ARMMMUIdx mmu_idx; - uint32_t mregion; - bool targetpriv; - bool targetsec =3D env->v7m.secure; - bool is_subpage; - - /* - * Work out what the security state and privilege level we're - * interested in is... - */ - if (alt) { - targetsec =3D !targetsec; - } - - if (forceunpriv) { - targetpriv =3D false; - } else { - targetpriv =3D arm_v7m_is_handler_mode(env) || - !(env->v7m.control[targetsec] & R_V7M_CONTROL_NPRIV_MASK); - } - - /* ...and then figure out which MMU index this is */ - mmu_idx =3D arm_v7m_mmu_idx_for_secstate_and_priv(env, targetsec, targ= etpriv); - - /* - * We know that the MPU and SAU don't care about the access type - * for our purposes beyond that we don't want to claim to be - * an insn fetch, so we arbitrarily call this a read. - */ - - /* - * MPU region info only available for privileged or if - * inspecting the other MPU state. - */ - if (arm_current_el(env) !=3D 0 || alt) { - /* We can ignore the return value as prot is always set */ - pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, - &phys_addr, &attrs, &prot, &is_subpage, - &fi, &mregion); - if (mregion =3D=3D -1) { - mrvalid =3D false; - mregion =3D 0; - } else { - mrvalid =3D true; - } - r =3D prot & PAGE_READ; - rw =3D prot & PAGE_WRITE; - } else { - r =3D false; - rw =3D false; - mrvalid =3D false; - mregion =3D 0; - } - - if (env->v7m.secure) { - v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs); - nsr =3D sattrs.ns && r; - nsrw =3D sattrs.ns && rw; - } else { - sattrs.ns =3D true; - nsr =3D false; - nsrw =3D false; - } - - tt_resp =3D (sattrs.iregion << 24) | - (sattrs.irvalid << 23) | - ((!sattrs.ns) << 22) | - (nsrw << 21) | - (nsr << 20) | - (rw << 19) | - (r << 18) | - (sattrs.srvalid << 17) | - (mrvalid << 16) | - (sattrs.sregion << 8) | - mregion; - - return tt_resp; -} - -#endif /* !CONFIG_USER_ONLY */ - ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, bool secstate, bool priv, bool negpri) { diff --git a/target/arm/tcg/sysemu/m_helper.c b/target/arm/tcg/sysemu/m_hel= per.c new file mode 100644 index 0000000000..77c9fd0b6e --- /dev/null +++ b/target/arm/tcg/sysemu/m_helper.c @@ -0,0 +1,2655 @@ +/* + * ARM v7m generic helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "exec/helper-proto.h" +#include "qemu/main-loop.h" +#include "exec/exec-all.h" +#include "semihosting/common-semi.h" + +#include "tcg/m_helper.h" + +/* + * What kind of stack write are we doing? This affects how exceptions + * generated during the stacking are treated. + */ +typedef enum StackingMode { + STACK_NORMAL, + STACK_IGNFAULTS, + STACK_LAZYFP, +} StackingMode; + +static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, + ARMMMUIdx mmu_idx, StackingMode mode) +{ + CPUState *cs =3D CPU(cpu); + CPUARMState *env =3D &cpu->env; + MemTxAttrs attrs =3D {}; + MemTxResult txres; + target_ulong page_size; + hwaddr physaddr; + int prot; + ARMMMUFaultInfo fi =3D {}; + ARMCacheAttrs cacheattrs =3D {}; + bool secure =3D mmu_idx & ARM_MMU_IDX_M_S; + int exc; + bool exc_secure; + + if (get_phys_addr(env, addr, MMU_DATA_STORE, mmu_idx, &physaddr, + &attrs, &prot, &page_size, &fi, &cacheattrs)) { + /* MPU/SAU lookup failed */ + if (fi.type =3D=3D ARMFault_QEMU_SFault) { + if (mode =3D=3D STACK_LAZYFP) { + qemu_log_mask(CPU_LOG_INT, + "...SecureFault with SFSR.LSPERR " + "during lazy stacking\n"); + env->v7m.sfsr |=3D R_V7M_SFSR_LSPERR_MASK; + } else { + qemu_log_mask(CPU_LOG_INT, + "...SecureFault with SFSR.AUVIOL " + "during stacking\n"); + env->v7m.sfsr |=3D R_V7M_SFSR_AUVIOL_MASK; + } + env->v7m.sfsr |=3D R_V7M_SFSR_SFARVALID_MASK; + env->v7m.sfar =3D addr; + exc =3D ARMV7M_EXCP_SECURE; + exc_secure =3D false; + } else { + if (mode =3D=3D STACK_LAZYFP) { + qemu_log_mask(CPU_LOG_INT, + "...MemManageFault with CFSR.MLSPERR\n"); + env->v7m.cfsr[secure] |=3D R_V7M_CFSR_MLSPERR_MASK; + } else { + qemu_log_mask(CPU_LOG_INT, + "...MemManageFault with CFSR.MSTKERR\n"); + env->v7m.cfsr[secure] |=3D R_V7M_CFSR_MSTKERR_MASK; + } + exc =3D ARMV7M_EXCP_MEM; + exc_secure =3D secure; + } + goto pend_fault; + } + address_space_stl_le(arm_addressspace(cs, attrs), physaddr, value, + attrs, &txres); + if (txres !=3D MEMTX_OK) { + /* BusFault trying to write the data */ + if (mode =3D=3D STACK_LAZYFP) { + qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.LSPERR\n"); + env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_LSPERR_MASK; + } else { + qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.STKERR\n"); + env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_STKERR_MASK; + } + exc =3D ARMV7M_EXCP_BUS; + exc_secure =3D false; + goto pend_fault; + } + return true; + +pend_fault: + /* + * By pending the exception at this point we are making + * the IMPDEF choice "overridden exceptions pended" (see the + * MergeExcInfo() pseudocode). The other choice would be to not + * pend them now and then make a choice about which to throw away + * later if we have two derived exceptions. + * The only case when we must not pend the exception but instead + * throw it away is if we are doing the push of the callee registers + * and we've already generated a derived exception (this is indicated + * by the caller passing STACK_IGNFAULTS). Even in this case we will + * still update the fault status registers. + */ + switch (mode) { + case STACK_NORMAL: + armv7m_nvic_set_pending_derived(env->nvic, exc, exc_secure); + break; + case STACK_LAZYFP: + armv7m_nvic_set_pending_lazyfp(env->nvic, exc, exc_secure); + break; + case STACK_IGNFAULTS: + break; + } + return false; +} + +static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr, + ARMMMUIdx mmu_idx) +{ + CPUState *cs =3D CPU(cpu); + CPUARMState *env =3D &cpu->env; + MemTxAttrs attrs =3D {}; + MemTxResult txres; + target_ulong page_size; + hwaddr physaddr; + int prot; + ARMMMUFaultInfo fi =3D {}; + ARMCacheAttrs cacheattrs =3D {}; + bool secure =3D mmu_idx & ARM_MMU_IDX_M_S; + int exc; + bool exc_secure; + uint32_t value; + + if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr, + &attrs, &prot, &page_size, &fi, &cacheattrs)) { + /* MPU/SAU lookup failed */ + if (fi.type =3D=3D ARMFault_QEMU_SFault) { + qemu_log_mask(CPU_LOG_INT, + "...SecureFault with SFSR.AUVIOL during unstack\= n"); + env->v7m.sfsr |=3D R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVAL= ID_MASK; + env->v7m.sfar =3D addr; + exc =3D ARMV7M_EXCP_SECURE; + exc_secure =3D false; + } else { + qemu_log_mask(CPU_LOG_INT, + "...MemManageFault with CFSR.MUNSTKERR\n"); + env->v7m.cfsr[secure] |=3D R_V7M_CFSR_MUNSTKERR_MASK; + exc =3D ARMV7M_EXCP_MEM; + exc_secure =3D secure; + } + goto pend_fault; + } + + value =3D address_space_ldl(arm_addressspace(cs, attrs), physaddr, + attrs, &txres); + if (txres !=3D MEMTX_OK) { + /* BusFault trying to read the data */ + qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n"); + env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_UNSTKERR_MASK; + exc =3D ARMV7M_EXCP_BUS; + exc_secure =3D false; + goto pend_fault; + } + + *dest =3D value; + return true; + +pend_fault: + /* + * By pending the exception at this point we are making + * the IMPDEF choice "overridden exceptions pended" (see the + * MergeExcInfo() pseudocode). The other choice would be to not + * pend them now and then make a choice about which to throw away + * later if we have two derived exceptions. + */ + armv7m_nvic_set_pending(env->nvic, exc, exc_secure); + return false; +} + +void HELPER(v7m_preserve_fp_state)(CPUARMState *env) +{ + /* + * Preserve FP state (because LSPACT was set and we are about + * to execute an FP instruction). This corresponds to the + * PreserveFPState() pseudocode. + * We may throw an exception if the stacking fails. + */ + ARMCPU *cpu =3D env_archcpu(env); + bool is_secure =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; + bool negpri =3D !(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_HFRDY_MASK); + bool is_priv =3D !(env->v7m.fpccr[is_secure] & R_V7M_FPCCR_USER_MASK); + bool splimviol =3D env->v7m.fpccr[is_secure] & R_V7M_FPCCR_SPLIMVIOL_M= ASK; + uint32_t fpcar =3D env->v7m.fpcar[is_secure]; + bool stacked_ok =3D true; + bool ts =3D is_secure && (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MAS= K); + bool take_exception; + + /* Take the iothread lock as we are going to touch the NVIC */ + qemu_mutex_lock_iothread(); + + /* Check the background context had access to the FPU */ + if (!v7m_cpacr_pass(env, is_secure, is_priv)) { + armv7m_nvic_set_pending_lazyfp(env->nvic, ARMV7M_EXCP_USAGE, is_se= cure); + env->v7m.cfsr[is_secure] |=3D R_V7M_CFSR_NOCP_MASK; + stacked_ok =3D false; + } else if (!is_secure && !extract32(env->v7m.nsacr, 10, 1)) { + armv7m_nvic_set_pending_lazyfp(env->nvic, ARMV7M_EXCP_USAGE, M_REG= _S); + env->v7m.cfsr[M_REG_S] |=3D R_V7M_CFSR_NOCP_MASK; + stacked_ok =3D false; + } + + if (!splimviol && stacked_ok) { + /* We only stack if the stack limit wasn't violated */ + int i; + ARMMMUIdx mmu_idx; + + mmu_idx =3D arm_v7m_mmu_idx_all(env, is_secure, is_priv, negpri); + for (i =3D 0; i < (ts ? 32 : 16); i +=3D 2) { + uint64_t dn =3D *aa32_vfp_dreg(env, i / 2); + uint32_t faddr =3D fpcar + 4 * i; + uint32_t slo =3D extract64(dn, 0, 32); + uint32_t shi =3D extract64(dn, 32, 32); + + if (i >=3D 16) { + faddr +=3D 8; /* skip the slot for the FPSCR */ + } + stacked_ok =3D stacked_ok && + v7m_stack_write(cpu, faddr, slo, mmu_idx, STACK_LAZYFP) && + v7m_stack_write(cpu, faddr + 4, shi, mmu_idx, STACK_LAZYFP= ); + } + + stacked_ok =3D stacked_ok && + v7m_stack_write(cpu, fpcar + 0x40, + vfp_get_fpscr(env), mmu_idx, STACK_LAZYFP); + } + + /* + * We definitely pended an exception, but it's possible that it + * might not be able to be taken now. If its priority permits us + * to take it now, then we must not update the LSPACT or FP regs, + * but instead jump out to take the exception immediately. + * If it's just pending and won't be taken until the current + * handler exits, then we do update LSPACT and the FP regs. + */ + take_exception =3D !stacked_ok && + armv7m_nvic_can_take_pending_exception(env->nvic); + + qemu_mutex_unlock_iothread(); + + if (take_exception) { + raise_exception_ra(env, EXCP_LAZYFP, 0, 1, GETPC()); + } + + env->v7m.fpccr[is_secure] &=3D ~R_V7M_FPCCR_LSPACT_MASK; + + if (ts) { + /* Clear s0 to s31 and the FPSCR */ + int i; + + for (i =3D 0; i < 32; i +=3D 2) { + *aa32_vfp_dreg(env, i / 2) =3D 0; + } + vfp_set_fpscr(env, 0); + } + /* + * Otherwise s0 to s15 and FPSCR are UNKNOWN; we choose to leave them + * unchanged. + */ +} + +/* + * Write to v7M CONTROL.SPSEL bit for the specified security bank. + * This may change the current stack pointer between Main and Process + * stack pointers if it is done for the CONTROL register for the current + * security state. + */ +static void write_v7m_control_spsel_for_secstate(CPUARMState *env, + bool new_spsel, + bool secstate) +{ + bool old_is_psp =3D v7m_using_psp(env); + + env->v7m.control[secstate] =3D + deposit32(env->v7m.control[secstate], + R_V7M_CONTROL_SPSEL_SHIFT, + R_V7M_CONTROL_SPSEL_LENGTH, new_spsel); + + if (secstate =3D=3D env->v7m.secure) { + bool new_is_psp =3D v7m_using_psp(env); + uint32_t tmp; + + if (old_is_psp !=3D new_is_psp) { + tmp =3D env->v7m.other_sp; + env->v7m.other_sp =3D env->regs[13]; + env->regs[13] =3D tmp; + } + } +} + +/* + * Write to v7M CONTROL.SPSEL bit. This may change the current + * stack pointer between Main and Process stack pointers. + */ +static void write_v7m_control_spsel(CPUARMState *env, bool new_spsel) +{ + write_v7m_control_spsel_for_secstate(env, new_spsel, env->v7m.secure); +} + +void write_v7m_exception(CPUARMState *env, uint32_t new_exc) +{ + /* + * Write a new value to v7m.exception, thus transitioning into or out + * of Handler mode; this may result in a change of active stack pointe= r. + */ + bool new_is_psp, old_is_psp =3D v7m_using_psp(env); + uint32_t tmp; + + env->v7m.exception =3D new_exc; + + new_is_psp =3D v7m_using_psp(env); + + if (old_is_psp !=3D new_is_psp) { + tmp =3D env->v7m.other_sp; + env->v7m.other_sp =3D env->regs[13]; + env->regs[13] =3D tmp; + } +} + +/* Switch M profile security state between NS and S */ +static void switch_v7m_security_state(CPUARMState *env, bool new_secstate) +{ + uint32_t new_ss_msp, new_ss_psp; + + if (env->v7m.secure =3D=3D new_secstate) { + return; + } + + /* + * All the banked state is accessed by looking at env->v7m.secure + * except for the stack pointer; rearrange the SP appropriately. + */ + new_ss_msp =3D env->v7m.other_ss_msp; + new_ss_psp =3D env->v7m.other_ss_psp; + + if (v7m_using_psp(env)) { + env->v7m.other_ss_psp =3D env->regs[13]; + env->v7m.other_ss_msp =3D env->v7m.other_sp; + } else { + env->v7m.other_ss_msp =3D env->regs[13]; + env->v7m.other_ss_psp =3D env->v7m.other_sp; + } + + env->v7m.secure =3D new_secstate; + + if (v7m_using_psp(env)) { + env->regs[13] =3D new_ss_psp; + env->v7m.other_sp =3D new_ss_msp; + } else { + env->regs[13] =3D new_ss_msp; + env->v7m.other_sp =3D new_ss_psp; + } +} + +void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) +{ + /* + * Handle v7M BXNS: + * - if the return value is a magic value, do exception return (like = BX) + * - otherwise bit 0 of the return value is the target security state + */ + uint32_t min_magic; + + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + /* Covers FNC_RETURN and EXC_RETURN magic */ + min_magic =3D FNC_RETURN_MIN_MAGIC; + } else { + /* EXC_RETURN magic only */ + min_magic =3D EXC_RETURN_MIN_MAGIC; + } + + if (dest >=3D min_magic) { + /* + * This is an exception return magic value; put it where + * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT. + * Note that if we ever add gen_ss_advance() singlestep support to + * M profile this should count as an "instruction execution comple= te" + * event (compare gen_bx_excret_final_code()). + */ + env->regs[15] =3D dest & ~1; + env->thumb =3D dest & 1; + HELPER(exception_internal)(env, EXCP_EXCEPTION_EXIT); + /* notreached */ + } + + /* translate.c should have made BXNS UNDEF unless we're secure */ + assert(env->v7m.secure); + + if (!(dest & 1)) { + env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_SFPA_MASK; + } + switch_v7m_security_state(env, dest & 1); + env->thumb =3D 1; + env->regs[15] =3D dest & ~1; + arm_rebuild_hflags(env); +} + +void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) +{ + /* + * Handle v7M BLXNS: + * - bit 0 of the destination address is the target security state + */ + + /* At this point regs[15] is the address just after the BLXNS */ + uint32_t nextinst =3D env->regs[15] | 1; + uint32_t sp =3D env->regs[13] - 8; + uint32_t saved_psr; + + /* translate.c will have made BLXNS UNDEF unless we're secure */ + assert(env->v7m.secure); + + if (dest & 1) { + /* + * Target is Secure, so this is just a normal BLX, + * except that the low bit doesn't indicate Thumb/not. + */ + env->regs[14] =3D nextinst; + env->thumb =3D 1; + env->regs[15] =3D dest & ~1; + return; + } + + /* Target is non-secure: first push a stack frame */ + if (!QEMU_IS_ALIGNED(sp, 8)) { + qemu_log_mask(LOG_GUEST_ERROR, + "BLXNS with misaligned SP is UNPREDICTABLE\n"); + } + + if (sp < v7m_sp_limit(env)) { + raise_exception(env, EXCP_STKOF, 0, 1); + } + + saved_psr =3D env->v7m.exception; + if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK) { + saved_psr |=3D XPSR_SFPA; + } + + /* Note that these stores can throw exceptions on MPU faults */ + cpu_stl_data_ra(env, sp, nextinst, GETPC()); + cpu_stl_data_ra(env, sp + 4, saved_psr, GETPC()); + + env->regs[13] =3D sp; + env->regs[14] =3D 0xfeffffff; + if (arm_v7m_is_handler_mode(env)) { + /* + * Write a dummy value to IPSR, to avoid leaking the current secure + * exception number to non-secure code. This is guaranteed not + * to cause write_v7m_exception() to actually change stacks. + */ + write_v7m_exception(env, 1); + } + env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_SFPA_MASK; + switch_v7m_security_state(env, 0); + env->thumb =3D 1; + env->regs[15] =3D dest; + arm_rebuild_hflags(env); +} + +static uint32_t *get_v7m_sp_ptr(CPUARMState *env, bool secure, bool thread= mode, + bool spsel) +{ + /* + * Return a pointer to the location where we currently store the + * stack pointer for the requested security state and thread mode. + * This pointer will become invalid if the CPU state is updated + * such that the stack pointers are switched around (eg changing + * the SPSEL control bit). + * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode(). + * Unlike that pseudocode, we require the caller to pass us in the + * SPSEL control bit value; this is because we also use this + * function in handling of pushing of the callee-saves registers + * part of the v8M stack frame (pseudocode PushCalleeStack()), + * and in the tailchain codepath the SPSEL bit comes from the exception + * return magic LR value from the previous exception. The pseudocode + * opencodes the stack-selection in PushCalleeStack(), but we prefer + * to make this utility function generic enough to do the job. + */ + bool want_psp =3D threadmode && spsel; + + if (secure =3D=3D env->v7m.secure) { + if (want_psp =3D=3D v7m_using_psp(env)) { + return &env->regs[13]; + } else { + return &env->v7m.other_sp; + } + } else { + if (want_psp) { + return &env->v7m.other_ss_psp; + } else { + return &env->v7m.other_ss_msp; + } + } +} + +static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure, + uint32_t *pvec) +{ + CPUState *cs =3D CPU(cpu); + CPUARMState *env =3D &cpu->env; + MemTxResult result; + uint32_t addr =3D env->v7m.vecbase[targets_secure] + exc * 4; + uint32_t vector_entry; + MemTxAttrs attrs =3D {}; + ARMMMUIdx mmu_idx; + bool exc_secure; + + mmu_idx =3D arm_v7m_mmu_idx_for_secstate_and_priv(env, targets_secure,= true); + + /* + * We don't do a get_phys_addr() here because the rules for vector + * loads are special: they always use the default memory map, and + * the default memory map permits reads from all addresses. + * Since there's no easy way to pass through to pmsav8_mpu_lookup() + * that we want this special case which would always say "yes", + * we just do the SAU lookup here followed by a direct physical load. + */ + attrs.secure =3D targets_secure; + attrs.user =3D false; + + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + V8M_SAttributes sattrs =3D {}; + + v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs); + if (sattrs.ns) { + attrs.secure =3D false; + } else if (!targets_secure) { + /* + * NS access to S memory: the underlying exception which we es= calate + * to HardFault is SecureFault, which always targets Secure. + */ + exc_secure =3D true; + goto load_fail; + } + } + + vector_entry =3D address_space_ldl(arm_addressspace(cs, attrs), addr, + attrs, &result); + if (result !=3D MEMTX_OK) { + /* + * Underlying exception is BusFault: its target security state + * depends on BFHFNMINS. + */ + exc_secure =3D !(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK); + goto load_fail; + } + *pvec =3D vector_entry; + return true; + +load_fail: + /* + * All vector table fetch fails are reported as HardFault, with + * HFSR.VECTTBL and .FORCED set. (FORCED is set because + * technically the underlying exception is a SecureFault or BusFault + * that is escalated to HardFault.) This is a terminal exception, + * so we will either take the HardFault immediately or else enter + * lockup (the latter case is handled in armv7m_nvic_set_pending_deriv= ed()). + * The HardFault is Secure if BFHFNMINS is 0 (meaning that all HFs are + * secure); otherwise it targets the same security state as the + * underlying exception. + * In v8.1M HardFaults from vector table fetch fails don't set FORCED. + */ + if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { + exc_secure =3D true; + } + env->v7m.hfsr |=3D R_V7M_HFSR_VECTTBL_MASK; + if (!arm_feature(env, ARM_FEATURE_V8_1M)) { + env->v7m.hfsr |=3D R_V7M_HFSR_FORCED_MASK; + } + armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secur= e); + return false; +} + +static uint32_t v7m_integrity_sig(CPUARMState *env, uint32_t lr) +{ + /* + * Return the integrity signature value for the callee-saves + * stack frame section. @lr is the exception return payload/LR value + * whose FType bit forms bit 0 of the signature if FP is present. + */ + uint32_t sig =3D 0xfefa125a; + + if (!cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) + || (lr & R_V7M_EXCRET_FTYPE_MASK)) { + sig |=3D 1; + } + return sig; +} + +static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailcha= in, + bool ignore_faults) +{ + /* + * For v8M, push the callee-saves register part of the stack frame. + * Compare the v8M pseudocode PushCalleeStack(). + * In the tailchaining case this may not be the current stack. + */ + CPUARMState *env =3D &cpu->env; + uint32_t *frame_sp_p; + uint32_t frameptr; + ARMMMUIdx mmu_idx; + bool stacked_ok; + uint32_t limit; + bool want_psp; + uint32_t sig; + StackingMode smode =3D ignore_faults ? STACK_IGNFAULTS : STACK_NORMAL; + + if (dotailchain) { + bool mode =3D lr & R_V7M_EXCRET_MODE_MASK; + bool priv =3D !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_NPRIV_MA= SK) || + !mode; + + mmu_idx =3D arm_v7m_mmu_idx_for_secstate_and_priv(env, M_REG_S, pr= iv); + frame_sp_p =3D get_v7m_sp_ptr(env, M_REG_S, mode, + lr & R_V7M_EXCRET_SPSEL_MASK); + want_psp =3D mode && (lr & R_V7M_EXCRET_SPSEL_MASK); + if (want_psp) { + limit =3D env->v7m.psplim[M_REG_S]; + } else { + limit =3D env->v7m.msplim[M_REG_S]; + } + } else { + mmu_idx =3D arm_mmu_idx(env); + frame_sp_p =3D &env->regs[13]; + limit =3D v7m_sp_limit(env); + } + + frameptr =3D *frame_sp_p - 0x28; + if (frameptr < limit) { + /* + * Stack limit failure: set SP to the limit value, and generate + * STKOF UsageFault. Stack pushes below the limit must not be + * performed. It is IMPDEF whether pushes above the limit are + * performed; we choose not to. + */ + qemu_log_mask(CPU_LOG_INT, + "...STKOF during callee-saves register stacking\n"); + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_STKOF_MASK; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, + env->v7m.secure); + *frame_sp_p =3D limit; + return true; + } + + /* + * Write as much of the stack frame as we can. A write failure may + * cause us to pend a derived exception. + */ + sig =3D v7m_integrity_sig(env, lr); + stacked_ok =3D + v7m_stack_write(cpu, frameptr, sig, mmu_idx, smode) && + v7m_stack_write(cpu, frameptr + 0x8, env->regs[4], mmu_idx, smode)= && + v7m_stack_write(cpu, frameptr + 0xc, env->regs[5], mmu_idx, smode)= && + v7m_stack_write(cpu, frameptr + 0x10, env->regs[6], mmu_idx, smode= ) && + v7m_stack_write(cpu, frameptr + 0x14, env->regs[7], mmu_idx, smode= ) && + v7m_stack_write(cpu, frameptr + 0x18, env->regs[8], mmu_idx, smode= ) && + v7m_stack_write(cpu, frameptr + 0x1c, env->regs[9], mmu_idx, smode= ) && + v7m_stack_write(cpu, frameptr + 0x20, env->regs[10], mmu_idx, smod= e) && + v7m_stack_write(cpu, frameptr + 0x24, env->regs[11], mmu_idx, smod= e); + + /* Update SP regardless of whether any of the stack accesses failed. */ + *frame_sp_p =3D frameptr; + + return !stacked_ok; +} + +static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain, + bool ignore_stackfaults) +{ + /* + * Do the "take the exception" parts of exception entry, + * but not the pushing of state to the stack. This is + * similar to the pseudocode ExceptionTaken() function. + */ + CPUARMState *env =3D &cpu->env; + uint32_t addr; + bool targets_secure; + int exc; + bool push_failed =3D false; + + armv7m_nvic_get_pending_irq_info(env->nvic, &exc, &targets_secure); + qemu_log_mask(CPU_LOG_INT, "...taking pending %s exception %d\n", + targets_secure ? "secure" : "nonsecure", exc); + + if (dotailchain) { + /* Sanitize LR FType and PREFIX bits */ + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { + lr |=3D R_V7M_EXCRET_FTYPE_MASK; + } + lr =3D deposit32(lr, 24, 8, 0xff); + } + + if (arm_feature(env, ARM_FEATURE_V8)) { + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && + (lr & R_V7M_EXCRET_S_MASK)) { + /* + * The background code (the owner of the registers in the + * exception frame) is Secure. This means it may either already + * have or now needs to push callee-saves registers. + */ + if (targets_secure) { + if (dotailchain && !(lr & R_V7M_EXCRET_ES_MASK)) { + /* + * We took an exception from Secure to NonSecure + * (which means the callee-saved registers got stacked) + * and are now tailchaining to a Secure exception. + * Clear DCRS so eventual return from this Secure + * exception unstacks the callee-saved registers. + */ + lr &=3D ~R_V7M_EXCRET_DCRS_MASK; + } + } else { + /* + * We're going to a non-secure exception; push the + * callee-saves registers to the stack now, if they're + * not already saved. + */ + if (lr & R_V7M_EXCRET_DCRS_MASK && + !(dotailchain && !(lr & R_V7M_EXCRET_ES_MASK))) { + push_failed =3D v7m_push_callee_stack(cpu, lr, dotailc= hain, + ignore_stackfaults= ); + } + lr |=3D R_V7M_EXCRET_DCRS_MASK; + } + } + + lr &=3D ~R_V7M_EXCRET_ES_MASK; + if (targets_secure || !arm_feature(env, ARM_FEATURE_M_SECURITY)) { + lr |=3D R_V7M_EXCRET_ES_MASK; + } + lr &=3D ~R_V7M_EXCRET_SPSEL_MASK; + if (env->v7m.control[targets_secure] & R_V7M_CONTROL_SPSEL_MASK) { + lr |=3D R_V7M_EXCRET_SPSEL_MASK; + } + + /* + * Clear registers if necessary to prevent non-secure exception + * code being able to see register values from secure code. + * Where register values become architecturally UNKNOWN we leave + * them with their previous values. v8.1M is tighter than v8.0M + * here and always zeroes the caller-saved registers regardless + * of the security state the exception is targeting. + */ + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + if (!targets_secure || arm_feature(env, ARM_FEATURE_V8_1M)) { + /* + * Always clear the caller-saved registers (they have been + * pushed to the stack earlier in v7m_push_stack()). + * Clear callee-saved registers if the background code is + * Secure (in which case these regs were saved in + * v7m_push_callee_stack()). + */ + int i; + /* + * r4..r11 are callee-saves, zero only if background + * state was Secure (EXCRET.S =3D=3D 1) and exception + * targets Non-secure state + */ + bool zero_callee_saves =3D !targets_secure && + (lr & R_V7M_EXCRET_S_MASK); + + for (i =3D 0; i < 13; i++) { + if (i < 4 || i > 11 || zero_callee_saves) { + env->regs[i] =3D 0; + } + } + /* Clear EAPSR */ + xpsr_write(env, 0, XPSR_NZCV | XPSR_Q | XPSR_GE | XPSR_IT); + } + } + } + + if (push_failed && !ignore_stackfaults) { + /* + * Derived exception on callee-saves register stacking: + * we might now want to take a different exception which + * targets a different security state, so try again from the top. + */ + qemu_log_mask(CPU_LOG_INT, + "...derived exception on callee-saves register stack= ing"); + v7m_exception_taken(cpu, lr, true, true); + return; + } + + if (!arm_v7m_load_vector(cpu, exc, targets_secure, &addr)) { + /* Vector load failed: derived exception */ + qemu_log_mask(CPU_LOG_INT, "...derived exception on vector table l= oad"); + v7m_exception_taken(cpu, lr, true, true); + return; + } + + /* + * Now we've done everything that might cause a derived exception + * we can go ahead and activate whichever exception we're going to + * take (which might now be the derived exception). + */ + armv7m_nvic_acknowledge_irq(env->nvic); + + /* Switch to target security state -- must do this before writing SPSE= L */ + switch_v7m_security_state(env, targets_secure); + write_v7m_control_spsel(env, 0); + arm_clear_exclusive(env); + /* Clear SFPA and FPCA (has no effect if no FPU) */ + env->v7m.control[M_REG_S] &=3D + ~(R_V7M_CONTROL_FPCA_MASK | R_V7M_CONTROL_SFPA_MASK); + /* Clear IT bits */ + env->condexec_bits =3D 0; + env->regs[14] =3D lr; + env->regs[15] =3D addr & 0xfffffffe; + env->thumb =3D addr & 1; + arm_rebuild_hflags(env); +} + +static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, + bool apply_splim) +{ + /* + * Like the pseudocode UpdateFPCCR: save state in FPCAR and FPCCR + * that we will need later in order to do lazy FP reg stacking. + */ + bool is_secure =3D env->v7m.secure; + void *nvic =3D env->nvic; + /* + * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits + * are banked and we want to update the bit in the bank for the + * current security state; and in one case we want to specifically + * update the NS banked version of a bit even if we are secure. + */ + uint32_t *fpccr_s =3D &env->v7m.fpccr[M_REG_S]; + uint32_t *fpccr_ns =3D &env->v7m.fpccr[M_REG_NS]; + uint32_t *fpccr =3D &env->v7m.fpccr[is_secure]; + bool hfrdy, bfrdy, mmrdy, ns_ufrdy, s_ufrdy, sfrdy, monrdy; + + env->v7m.fpcar[is_secure] =3D frameptr & ~0x7; + + if (apply_splim && arm_feature(env, ARM_FEATURE_V8)) { + bool splimviol; + uint32_t splim =3D v7m_sp_limit(env); + bool ign =3D armv7m_nvic_neg_prio_requested(nvic, is_secure) && + (env->v7m.ccr[is_secure] & R_V7M_CCR_STKOFHFNMIGN_MASK); + + splimviol =3D !ign && frameptr < splim; + *fpccr =3D FIELD_DP32(*fpccr, V7M_FPCCR, SPLIMVIOL, splimviol); + } + + *fpccr =3D FIELD_DP32(*fpccr, V7M_FPCCR, LSPACT, 1); + + *fpccr_s =3D FIELD_DP32(*fpccr_s, V7M_FPCCR, S, is_secure); + + *fpccr =3D FIELD_DP32(*fpccr, V7M_FPCCR, USER, arm_current_el(env) =3D= =3D 0); + + *fpccr =3D FIELD_DP32(*fpccr, V7M_FPCCR, THREAD, + !arm_v7m_is_handler_mode(env)); + + hfrdy =3D armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_HARD, false); + *fpccr_s =3D FIELD_DP32(*fpccr_s, V7M_FPCCR, HFRDY, hfrdy); + + bfrdy =3D armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_BUS, false); + *fpccr_s =3D FIELD_DP32(*fpccr_s, V7M_FPCCR, BFRDY, bfrdy); + + mmrdy =3D armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_MEM, is_secur= e); + *fpccr =3D FIELD_DP32(*fpccr, V7M_FPCCR, MMRDY, mmrdy); + + ns_ufrdy =3D armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_USAGE, fal= se); + *fpccr_ns =3D FIELD_DP32(*fpccr_ns, V7M_FPCCR, UFRDY, ns_ufrdy); + + monrdy =3D armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_DEBUG, false= ); + *fpccr_s =3D FIELD_DP32(*fpccr_s, V7M_FPCCR, MONRDY, monrdy); + + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + s_ufrdy =3D armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_USAGE, = true); + *fpccr_s =3D FIELD_DP32(*fpccr_s, V7M_FPCCR, UFRDY, s_ufrdy); + + sfrdy =3D armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_SECURE, f= alse); + *fpccr_s =3D FIELD_DP32(*fpccr_s, V7M_FPCCR, SFRDY, sfrdy); + } +} + +void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) +{ + /* fptr is the value of Rn, the frame pointer we store the FP regs to = */ + bool s =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; + bool lspact =3D env->v7m.fpccr[s] & R_V7M_FPCCR_LSPACT_MASK; + uintptr_t ra =3D GETPC(); + + assert(env->v7m.secure); + + if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)) { + return; + } + + /* Check access to the coprocessor is permitted */ + if (!v7m_cpacr_pass(env, true, arm_current_el(env) !=3D 0)) { + raise_exception_ra(env, EXCP_NOCP, 0, 1, GETPC()); + } + + if (lspact) { + /* LSPACT should not be active when there is active FP state */ + raise_exception_ra(env, EXCP_LSERR, 0, 1, GETPC()); + } + + if (fptr & 7) { + raise_exception_ra(env, EXCP_UNALIGNED, 0, 1, GETPC()); + } + + /* + * Note that we do not use v7m_stack_write() here, because the + * accesses should not set the FSR bits for stacking errors if they + * fail. (In pseudocode terms, they are AccType_NORMAL, not AccType_ST= ACK + * or AccType_LAZYFP). Faults in cpu_stl_data_ra() will throw exceptio= ns + * and longjmp out. + */ + if (!(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPEN_MASK)) { + bool ts =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK; + int i; + + for (i =3D 0; i < (ts ? 32 : 16); i +=3D 2) { + uint64_t dn =3D *aa32_vfp_dreg(env, i / 2); + uint32_t faddr =3D fptr + 4 * i; + uint32_t slo =3D extract64(dn, 0, 32); + uint32_t shi =3D extract64(dn, 32, 32); + + if (i >=3D 16) { + faddr +=3D 8; /* skip the slot for the FPSCR */ + } + cpu_stl_data_ra(env, faddr, slo, ra); + cpu_stl_data_ra(env, faddr + 4, shi, ra); + } + cpu_stl_data_ra(env, fptr + 0x40, vfp_get_fpscr(env), ra); + + /* + * If TS is 0 then s0 to s15 and FPSCR are UNKNOWN; we choose to + * leave them unchanged, matching our choice in v7m_preserve_fp_st= ate. + */ + if (ts) { + for (i =3D 0; i < 32; i +=3D 2) { + *aa32_vfp_dreg(env, i / 2) =3D 0; + } + vfp_set_fpscr(env, 0); + } + } else { + v7m_update_fpccr(env, fptr, false); + } + + env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_FPCA_MASK; +} + +void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr) +{ + uintptr_t ra =3D GETPC(); + + /* fptr is the value of Rn, the frame pointer we load the FP regs from= */ + assert(env->v7m.secure); + + if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)) { + return; + } + + /* Check access to the coprocessor is permitted */ + if (!v7m_cpacr_pass(env, true, arm_current_el(env) !=3D 0)) { + raise_exception_ra(env, EXCP_NOCP, 0, 1, GETPC()); + } + + if (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPACT_MASK) { + /* State in FP is still valid */ + env->v7m.fpccr[M_REG_S] &=3D ~R_V7M_FPCCR_LSPACT_MASK; + } else { + bool ts =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK; + int i; + uint32_t fpscr; + + if (fptr & 7) { + raise_exception_ra(env, EXCP_UNALIGNED, 0, 1, GETPC()); + } + + for (i =3D 0; i < (ts ? 32 : 16); i +=3D 2) { + uint32_t slo, shi; + uint64_t dn; + uint32_t faddr =3D fptr + 4 * i; + + if (i >=3D 16) { + faddr +=3D 8; /* skip the slot for the FPSCR */ + } + + slo =3D cpu_ldl_data_ra(env, faddr, ra); + shi =3D cpu_ldl_data_ra(env, faddr + 4, ra); + + dn =3D (uint64_t) shi << 32 | slo; + *aa32_vfp_dreg(env, i / 2) =3D dn; + } + fpscr =3D cpu_ldl_data_ra(env, fptr + 0x40, ra); + vfp_set_fpscr(env, fpscr); + } + + env->v7m.control[M_REG_S] |=3D R_V7M_CONTROL_FPCA_MASK; +} + +static bool v7m_push_stack(ARMCPU *cpu) +{ + /* + * Do the "set up stack frame" part of exception entry, + * similar to pseudocode PushStack(). + * Return true if we generate a derived exception (and so + * should ignore further stack faults trying to process + * that derived exception.) + */ + bool stacked_ok =3D true, limitviol =3D false; + CPUARMState *env =3D &cpu->env; + uint32_t xpsr =3D xpsr_read(env); + uint32_t frameptr =3D env->regs[13]; + ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); + uint32_t framesize; + bool nsacr_cp10 =3D extract32(env->v7m.nsacr, 10, 1); + + if ((env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) && + (env->v7m.secure || nsacr_cp10)) { + if (env->v7m.secure && + env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK) { + framesize =3D 0xa8; + } else { + framesize =3D 0x68; + } + } else { + framesize =3D 0x20; + } + + /* Align stack pointer if the guest wants that */ + if ((frameptr & 4) && + (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKALIGN_MASK)) { + frameptr -=3D 4; + xpsr |=3D XPSR_SPREALIGN; + } + + xpsr &=3D ~XPSR_SFPA; + if (env->v7m.secure && + (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)) { + xpsr |=3D XPSR_SFPA; + } + + frameptr -=3D framesize; + + if (arm_feature(env, ARM_FEATURE_V8)) { + uint32_t limit =3D v7m_sp_limit(env); + + if (frameptr < limit) { + /* + * Stack limit failure: set SP to the limit value, and generate + * STKOF UsageFault. Stack pushes below the limit must not be + * performed. It is IMPDEF whether pushes above the limit are + * performed; we choose not to. + */ + qemu_log_mask(CPU_LOG_INT, + "...STKOF during stacking\n"); + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_STKOF_MASK; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, + env->v7m.secure); + env->regs[13] =3D limit; + /* + * We won't try to perform any further memory accesses but + * we must continue through the following code to check for + * permission faults during FPU state preservation, and we + * must update FPCCR if lazy stacking is enabled. + */ + limitviol =3D true; + stacked_ok =3D false; + } + } + + /* + * Write as much of the stack frame as we can. If we fail a stack + * write this will result in a derived exception being pended + * (which may be taken in preference to the one we started with + * if it has higher priority). + */ + stacked_ok =3D stacked_ok && + v7m_stack_write(cpu, frameptr, env->regs[0], mmu_idx, STACK_NORMAL= ) && + v7m_stack_write(cpu, frameptr + 4, env->regs[1], + mmu_idx, STACK_NORMAL) && + v7m_stack_write(cpu, frameptr + 8, env->regs[2], + mmu_idx, STACK_NORMAL) && + v7m_stack_write(cpu, frameptr + 12, env->regs[3], + mmu_idx, STACK_NORMAL) && + v7m_stack_write(cpu, frameptr + 16, env->regs[12], + mmu_idx, STACK_NORMAL) && + v7m_stack_write(cpu, frameptr + 20, env->regs[14], + mmu_idx, STACK_NORMAL) && + v7m_stack_write(cpu, frameptr + 24, env->regs[15], + mmu_idx, STACK_NORMAL) && + v7m_stack_write(cpu, frameptr + 28, xpsr, mmu_idx, STACK_NORMAL); + + if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) { + /* FPU is active, try to save its registers */ + bool fpccr_s =3D env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; + bool lspact =3D env->v7m.fpccr[fpccr_s] & R_V7M_FPCCR_LSPACT_MASK; + + if (lspact && arm_feature(env, ARM_FEATURE_M_SECURITY)) { + qemu_log_mask(CPU_LOG_INT, + "...SecureFault because LSPACT and FPCA both set= \n"); + env->v7m.sfsr |=3D R_V7M_SFSR_LSERR_MASK; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); + } else if (!env->v7m.secure && !nsacr_cp10) { + qemu_log_mask(CPU_LOG_INT, + "...Secure UsageFault with CFSR.NOCP because " + "NSACR.CP10 prevents stacking FP regs\n"); + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, M_REG_S); + env->v7m.cfsr[M_REG_S] |=3D R_V7M_CFSR_NOCP_MASK; + } else { + if (!(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPEN_MASK)) { + /* Lazy stacking disabled, save registers now */ + int i; + bool cpacr_pass =3D v7m_cpacr_pass(env, env->v7m.secure, + arm_current_el(env) !=3D = 0); + + if (stacked_ok && !cpacr_pass) { + /* + * Take UsageFault if CPACR forbids access. The pseudo= code + * here does a full CheckCPEnabled() but we know the N= SACR + * check can never fail as we have already handled tha= t. + */ + qemu_log_mask(CPU_LOG_INT, + "...UsageFault with CFSR.NOCP because " + "CPACR.CP10 prevents stacking FP regs\n"= ); + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, + env->v7m.secure); + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_NOCP_MA= SK; + stacked_ok =3D false; + } + + for (i =3D 0; i < ((framesize =3D=3D 0xa8) ? 32 : 16); i += =3D 2) { + uint64_t dn =3D *aa32_vfp_dreg(env, i / 2); + uint32_t faddr =3D frameptr + 0x20 + 4 * i; + uint32_t slo =3D extract64(dn, 0, 32); + uint32_t shi =3D extract64(dn, 32, 32); + + if (i >=3D 16) { + faddr +=3D 8; /* skip the slot for the FPSCR */ + } + stacked_ok =3D stacked_ok && + v7m_stack_write(cpu, faddr, slo, + mmu_idx, STACK_NORMAL) && + v7m_stack_write(cpu, faddr + 4, shi, + mmu_idx, STACK_NORMAL); + } + stacked_ok =3D stacked_ok && + v7m_stack_write(cpu, frameptr + 0x60, + vfp_get_fpscr(env), mmu_idx, STACK_NOR= MAL); + if (cpacr_pass) { + for (i =3D 0; i < ((framesize =3D=3D 0xa8) ? 32 : 16);= i +=3D 2) { + *aa32_vfp_dreg(env, i / 2) =3D 0; + } + vfp_set_fpscr(env, 0); + } + } else { + /* Lazy stacking enabled, save necessary info to stack lat= er */ + v7m_update_fpccr(env, frameptr + 0x20, true); + } + } + } + + /* + * If we broke a stack limit then SP was already updated earlier; + * otherwise we update SP regardless of whether any of the stack + * accesses failed or we took some other kind of fault. + */ + if (!limitviol) { + env->regs[13] =3D frameptr; + } + + return !stacked_ok; +} + +static void do_v7m_exception_exit(ARMCPU *cpu) +{ + CPUARMState *env =3D &cpu->env; + uint32_t excret; + uint32_t xpsr, xpsr_mask; + bool ufault =3D false; + bool sfault =3D false; + bool return_to_sp_process; + bool return_to_handler; + bool rettobase =3D false; + bool exc_secure =3D false; + bool return_to_secure; + bool ftype; + bool restore_s16_s31 =3D false; + + /* + * If we're not in Handler mode then jumps to magic exception-exit + * addresses don't have magic behaviour. However for the v8M + * security extensions the magic secure-function-return has to + * work in thread mode too, so to avoid doing an extra check in + * the generated code we allow exception-exit magic to also cause the + * internal exception and bring us here in thread mode. Correct code + * will never try to do this (the following insn fetch will always + * fault) so we the overhead of having taken an unnecessary exception + * doesn't matter. + */ + if (!arm_v7m_is_handler_mode(env)) { + return; + } + + /* + * In the spec pseudocode ExceptionReturn() is called directly + * from BXWritePC() and gets the full target PC value including + * bit zero. In QEMU's implementation we treat it as a normal + * jump-to-register (which is then caught later on), and so split + * the target value up between env->regs[15] and env->thumb in + * gen_bx(). Reconstitute it. + */ + excret =3D env->regs[15]; + if (env->thumb) { + excret |=3D 1; + } + + qemu_log_mask(CPU_LOG_INT, "Exception return: magic PC %" PRIx32 + " previous exception %d\n", + excret, env->v7m.exception); + + if ((excret & R_V7M_EXCRET_RES1_MASK) !=3D R_V7M_EXCRET_RES1_MASK) { + qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in excep= tion " + "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", + excret); + } + + ftype =3D excret & R_V7M_EXCRET_FTYPE_MASK; + + if (!ftype && !cpu_isar_feature(aa32_vfp_simd, cpu)) { + qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception= " + "exit PC value 0x%" PRIx32 " is UNPREDICTABLE " + "if FPU not present\n", + excret); + ftype =3D true; + } + + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + /* + * EXC_RETURN.ES validation check (R_SMFL). We must do this before + * we pick which FAULTMASK to clear. + */ + if (!env->v7m.secure && + ((excret & R_V7M_EXCRET_ES_MASK) || + !(excret & R_V7M_EXCRET_DCRS_MASK))) { + sfault =3D 1; + /* For all other purposes, treat ES as 0 (R_HXSR) */ + excret &=3D ~R_V7M_EXCRET_ES_MASK; + } + exc_secure =3D excret & R_V7M_EXCRET_ES_MASK; + } + + if (env->v7m.exception !=3D ARMV7M_EXCP_NMI) { + /* + * Auto-clear FAULTMASK on return from other than NMI. + * If the security extension is implemented then this only + * happens if the raw execution priority is >=3D 0; the + * value of the ES bit in the exception return value indicates + * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) + */ + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + if (armv7m_nvic_raw_execution_priority(env->nvic) >=3D 0) { + env->v7m.faultmask[exc_secure] =3D 0; + } + } else { + env->v7m.faultmask[M_REG_NS] =3D 0; + } + } + + switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception, + exc_secure)) { + case -1: + /* attempt to exit an exception that isn't active */ + ufault =3D true; + break; + case 0: + /* still an irq active now */ + break; + case 1: + /* + * We returned to base exception level, no nesting. + * (In the pseudocode this is written using "NestedActivation !=3D= 1" + * where we have 'rettobase =3D=3D false'.) + */ + rettobase =3D true; + break; + default: + g_assert_not_reached(); + } + + return_to_handler =3D !(excret & R_V7M_EXCRET_MODE_MASK); + return_to_sp_process =3D excret & R_V7M_EXCRET_SPSEL_MASK; + return_to_secure =3D arm_feature(env, ARM_FEATURE_M_SECURITY) && + (excret & R_V7M_EXCRET_S_MASK); + + if (arm_feature(env, ARM_FEATURE_V8)) { + if (!arm_feature(env, ARM_FEATURE_M_SECURITY)) { + /* + * UNPREDICTABLE if S =3D=3D 1 or DCRS =3D=3D 0 or ES =3D=3D 1= (R_XLCP); + * we choose to take the UsageFault. + */ + if ((excret & R_V7M_EXCRET_S_MASK) || + (excret & R_V7M_EXCRET_ES_MASK) || + !(excret & R_V7M_EXCRET_DCRS_MASK)) { + ufault =3D true; + } + } + if (excret & R_V7M_EXCRET_RES0_MASK) { + ufault =3D true; + } + } else { + /* For v7M we only recognize certain combinations of the low bits = */ + switch (excret & 0xf) { + case 1: /* Return to Handler */ + break; + case 13: /* Return to Thread using Process stack */ + case 9: /* Return to Thread using Main stack */ + /* + * We only need to check NONBASETHRDENA for v7M, because in + * v8M this bit does not exist (it is RES1). + */ + if (!rettobase && + !(env->v7m.ccr[env->v7m.secure] & + R_V7M_CCR_NONBASETHRDENA_MASK)) { + ufault =3D true; + } + break; + default: + ufault =3D true; + } + } + + /* + * Set CONTROL.SPSEL from excret.SPSEL. Since we're still in + * Handler mode (and will be until we write the new XPSR.Interrupt + * field) this does not switch around the current stack pointer. + * We must do this before we do any kind of tailchaining, including + * for the derived exceptions on integrity check failures, or we will + * give the guest an incorrect EXCRET.SPSEL value on exception entry. + */ + write_v7m_control_spsel_for_secstate(env, return_to_sp_process, exc_se= cure); + + /* + * Clear scratch FP values left in caller saved registers; this + * must happen before any kind of tail chaining. + */ + if ((env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_CLRONRET_MASK) && + (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) { + if (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPACT_MASK) { + env->v7m.sfsr |=3D R_V7M_SFSR_LSERR_MASK; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); + qemu_log_mask(CPU_LOG_INT, "...taking SecureFault on existing " + "stackframe: error during lazy state deactivatio= n\n"); + v7m_exception_taken(cpu, excret, true, false); + return; + } else { + if (arm_feature(env, ARM_FEATURE_V8_1M)) { + /* v8.1M adds this NOCP check */ + bool nsacr_pass =3D exc_secure || + extract32(env->v7m.nsacr, 10, 1); + bool cpacr_pass =3D v7m_cpacr_pass(env, exc_secure, true); + if (!nsacr_pass) { + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, = true); + env->v7m.cfsr[M_REG_S] |=3D R_V7M_CFSR_NOCP_MASK; + qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on ex= isting " + "stackframe: NSACR prevents clearing FPU registers= \n"); + v7m_exception_taken(cpu, excret, true, false); + } else if (!cpacr_pass) { + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, + exc_secure); + env->v7m.cfsr[exc_secure] |=3D R_V7M_CFSR_NOCP_MASK; + qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on ex= isting " + "stackframe: CPACR prevents clearing FPU registers= \n"); + v7m_exception_taken(cpu, excret, true, false); + } + } + /* Clear s0..s15 and FPSCR; TODO also VPR when MVE is implemen= ted */ + int i; + + for (i =3D 0; i < 16; i +=3D 2) { + *aa32_vfp_dreg(env, i / 2) =3D 0; + } + vfp_set_fpscr(env, 0); + } + } + + if (sfault) { + env->v7m.sfsr |=3D R_V7M_SFSR_INVER_MASK; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); + qemu_log_mask(CPU_LOG_INT, "...taking SecureFault on existing " + "stackframe: failed EXC_RETURN.ES validity check\n"); + v7m_exception_taken(cpu, excret, true, false); + return; + } + + if (ufault) { + /* + * Bad exception return: instead of popping the exception + * stack, directly take a usage fault on the current stack. + */ + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.sec= ure); + qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " + "stackframe: failed exception return integrity check= \n"); + v7m_exception_taken(cpu, excret, true, false); + return; + } + + /* + * Tailchaining: if there is currently a pending exception that + * is high enough priority to preempt execution at the level we're + * about to return to, then just directly take that exception now, + * avoiding an unstack-and-then-stack. Note that now we have + * deactivated the previous exception by calling armv7m_nvic_complete_= irq() + * our current execution priority is already the execution priority we= are + * returning to -- none of the state we would unstack or set based on + * the EXCRET value affects it. + */ + if (armv7m_nvic_can_take_pending_exception(env->nvic)) { + qemu_log_mask(CPU_LOG_INT, "...tailchaining to pending exception\n= "); + v7m_exception_taken(cpu, excret, true, false); + return; + } + + switch_v7m_security_state(env, return_to_secure); + + { + /* + * The stack pointer we should be reading the exception frame from + * depends on bits in the magic exception return type value (and + * for v8M isn't necessarily the stack pointer we will eventually + * end up resuming execution with). Get a pointer to the location + * in the CPU state struct where the SP we need is currently being + * stored; we will use and modify it in place. + * We use this limited C variable scope so we don't accidentally + * use 'frame_sp_p' after we do something that makes it invalid. + */ + uint32_t *frame_sp_p =3D get_v7m_sp_ptr(env, + return_to_secure, + !return_to_handler, + return_to_sp_process); + uint32_t frameptr =3D *frame_sp_p; + bool pop_ok =3D true; + ARMMMUIdx mmu_idx; + bool return_to_priv =3D return_to_handler || + !(env->v7m.control[return_to_secure] & R_V7M_CONTROL_NPRIV_MAS= K); + + mmu_idx =3D arm_v7m_mmu_idx_for_secstate_and_priv(env, return_to_s= ecure, + return_to_priv); + + if (!QEMU_IS_ALIGNED(frameptr, 8) && + arm_feature(env, ARM_FEATURE_V8)) { + qemu_log_mask(LOG_GUEST_ERROR, + "M profile exception return with non-8-aligned S= P " + "for destination state is UNPREDICTABLE\n"); + } + + /* Do we need to pop callee-saved registers? */ + if (return_to_secure && + ((excret & R_V7M_EXCRET_ES_MASK) =3D=3D 0 || + (excret & R_V7M_EXCRET_DCRS_MASK) =3D=3D 0)) { + uint32_t actual_sig; + + pop_ok =3D v7m_stack_read(cpu, &actual_sig, frameptr, mmu_idx); + + if (pop_ok && v7m_integrity_sig(env, excret) !=3D actual_sig) { + /* Take a SecureFault on the current stack */ + env->v7m.sfsr |=3D R_V7M_SFSR_INVIS_MASK; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, fal= se); + qemu_log_mask(CPU_LOG_INT, "...taking SecureFault on exist= ing " + "stackframe: failed exception return integri= ty " + "signature check\n"); + v7m_exception_taken(cpu, excret, true, false); + return; + } + + pop_ok =3D pop_ok && + v7m_stack_read(cpu, &env->regs[4], frameptr + 0x8, mmu_idx= ) && + v7m_stack_read(cpu, &env->regs[5], frameptr + 0xc, mmu_idx= ) && + v7m_stack_read(cpu, &env->regs[6], frameptr + 0x10, mmu_id= x) && + v7m_stack_read(cpu, &env->regs[7], frameptr + 0x14, mmu_id= x) && + v7m_stack_read(cpu, &env->regs[8], frameptr + 0x18, mmu_id= x) && + v7m_stack_read(cpu, &env->regs[9], frameptr + 0x1c, mmu_id= x) && + v7m_stack_read(cpu, &env->regs[10], frameptr + 0x20, mmu_i= dx) && + v7m_stack_read(cpu, &env->regs[11], frameptr + 0x24, mmu_i= dx); + + frameptr +=3D 0x28; + } + + /* Pop registers */ + pop_ok =3D pop_ok && + v7m_stack_read(cpu, &env->regs[0], frameptr, mmu_idx) && + v7m_stack_read(cpu, &env->regs[1], frameptr + 0x4, mmu_idx) && + v7m_stack_read(cpu, &env->regs[2], frameptr + 0x8, mmu_idx) && + v7m_stack_read(cpu, &env->regs[3], frameptr + 0xc, mmu_idx) && + v7m_stack_read(cpu, &env->regs[12], frameptr + 0x10, mmu_idx) = && + v7m_stack_read(cpu, &env->regs[14], frameptr + 0x14, mmu_idx) = && + v7m_stack_read(cpu, &env->regs[15], frameptr + 0x18, mmu_idx) = && + v7m_stack_read(cpu, &xpsr, frameptr + 0x1c, mmu_idx); + + if (!pop_ok) { + /* + * v7m_stack_read() pended a fault, so take it (as a tail + * chained exception on the same stack frame) + */ + qemu_log_mask(CPU_LOG_INT, "...derived exception on unstacking= \n"); + v7m_exception_taken(cpu, excret, true, false); + return; + } + + /* + * Returning from an exception with a PC with bit 0 set is defined + * behaviour on v8M (bit 0 is ignored), but for v7M it was specifi= ed + * to be UNPREDICTABLE. In practice actual v7M hardware seems to i= gnore + * the lsbit, and there are several RTOSes out there which incorre= ctly + * assume the r15 in the stack frame should be a Thumb-style "lsbit + * indicates ARM/Thumb" value, so ignore the bit on v7M as well, b= ut + * complain about the badly behaved guest. + */ + if (env->regs[15] & 1) { + env->regs[15] &=3D ~1U; + if (!arm_feature(env, ARM_FEATURE_V8)) { + qemu_log_mask(LOG_GUEST_ERROR, + "M profile return from interrupt with misali= gned " + "PC is UNPREDICTABLE on v7M\n"); + } + } + + if (arm_feature(env, ARM_FEATURE_V8)) { + /* + * For v8M we have to check whether the xPSR exception field + * matches the EXCRET value for return to handler/thread + * before we commit to changing the SP and xPSR. + */ + bool will_be_handler =3D (xpsr & XPSR_EXCP) !=3D 0; + if (return_to_handler !=3D will_be_handler) { + /* + * Take an INVPC UsageFault on the current stack. + * By this point we will have switched to the security sta= te + * for the background state, so this UsageFault will target + * that state. + */ + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, + env->v7m.secure); + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; + qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existi= ng " + "stackframe: failed exception return integri= ty " + "check\n"); + v7m_exception_taken(cpu, excret, true, false); + return; + } + } + + if (!ftype) { + /* FP present and we need to handle it */ + if (!return_to_secure && + (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPACT_MASK)) { + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, fal= se); + env->v7m.sfsr |=3D R_V7M_SFSR_LSERR_MASK; + qemu_log_mask(CPU_LOG_INT, + "...taking SecureFault on existing stackfram= e: " + "Secure LSPACT set but exception return is " + "not to secure state\n"); + v7m_exception_taken(cpu, excret, true, false); + return; + } + + restore_s16_s31 =3D return_to_secure && + (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK); + + if (env->v7m.fpccr[return_to_secure] & R_V7M_FPCCR_LSPACT_MASK= ) { + /* State in FPU is still valid, just clear LSPACT */ + env->v7m.fpccr[return_to_secure] &=3D ~R_V7M_FPCCR_LSPACT_= MASK; + } else { + int i; + uint32_t fpscr; + bool cpacr_pass, nsacr_pass; + + cpacr_pass =3D v7m_cpacr_pass(env, return_to_secure, + return_to_priv); + nsacr_pass =3D return_to_secure || + extract32(env->v7m.nsacr, 10, 1); + + if (!cpacr_pass) { + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, + return_to_secure); + env->v7m.cfsr[return_to_secure] |=3D R_V7M_CFSR_NOCP_M= ASK; + qemu_log_mask(CPU_LOG_INT, + "...taking UsageFault on existing " + "stackframe: CPACR.CP10 prevents unstack= ing " + "FP regs\n"); + v7m_exception_taken(cpu, excret, true, false); + return; + } else if (!nsacr_pass) { + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, = true); + env->v7m.cfsr[M_REG_S] |=3D R_V7M_CFSR_INVPC_MASK; + qemu_log_mask(CPU_LOG_INT, + "...taking Secure UsageFault on existing= " + "stackframe: NSACR.CP10 prevents unstack= ing " + "FP regs\n"); + v7m_exception_taken(cpu, excret, true, false); + return; + } + + for (i =3D 0; i < (restore_s16_s31 ? 32 : 16); i +=3D 2) { + uint32_t slo, shi; + uint64_t dn; + uint32_t faddr =3D frameptr + 0x20 + 4 * i; + + if (i >=3D 16) { + faddr +=3D 8; /* Skip the slot for the FPSCR */ + } + + pop_ok =3D pop_ok && + v7m_stack_read(cpu, &slo, faddr, mmu_idx) && + v7m_stack_read(cpu, &shi, faddr + 4, mmu_idx); + + if (!pop_ok) { + break; + } + + dn =3D (uint64_t)shi << 32 | slo; + *aa32_vfp_dreg(env, i / 2) =3D dn; + } + pop_ok =3D pop_ok && + v7m_stack_read(cpu, &fpscr, frameptr + 0x60, mmu_idx); + if (pop_ok) { + vfp_set_fpscr(env, fpscr); + } + if (!pop_ok) { + /* + * These regs are 0 if security extension present; + * otherwise merely UNKNOWN. We zero always. + */ + for (i =3D 0; i < (restore_s16_s31 ? 32 : 16); i +=3D = 2) { + *aa32_vfp_dreg(env, i / 2) =3D 0; + } + vfp_set_fpscr(env, 0); + } + } + } + env->v7m.control[M_REG_S] =3D FIELD_DP32(env->v7m.control[M_REG_S], + V7M_CONTROL, FPCA, !ftype); + + /* Commit to consuming the stack frame */ + frameptr +=3D 0x20; + if (!ftype) { + frameptr +=3D 0x48; + if (restore_s16_s31) { + frameptr +=3D 0x40; + } + } + /* + * Undo stack alignment (the SPREALIGN bit indicates that the orig= inal + * pre-exception SP was not 8-aligned and we added a padding word = to + * align it, so we undo this by ORing in the bit that increases it + * from the current 8-aligned value to the 8-unaligned value. (Add= ing 4 + * would work too but a logical OR is how the pseudocode specifies= it.) + */ + if (xpsr & XPSR_SPREALIGN) { + frameptr |=3D 4; + } + *frame_sp_p =3D frameptr; + } + + xpsr_mask =3D ~(XPSR_SPREALIGN | XPSR_SFPA); + if (!arm_feature(env, ARM_FEATURE_THUMB_DSP)) { + xpsr_mask &=3D ~XPSR_GE; + } + /* This xpsr_write() will invalidate frame_sp_p as it may switch stack= */ + xpsr_write(env, xpsr, xpsr_mask); + + if (env->v7m.secure) { + bool sfpa =3D xpsr & XPSR_SFPA; + + env->v7m.control[M_REG_S] =3D FIELD_DP32(env->v7m.control[M_REG_S], + V7M_CONTROL, SFPA, sfpa); + } + + /* + * The restored xPSR exception field will be zero if we're + * resuming in Thread mode. If that doesn't match what the + * exception return excret specified then this is a UsageFault. + * v7M requires we make this check here; v8M did it earlier. + */ + if (return_to_handler !=3D arm_v7m_is_handler_mode(env)) { + /* + * Take an INVPC UsageFault by pushing the stack again; + * we know we're v7M so this is never a Secure UsageFault. + */ + bool ignore_stackfaults; + + assert(!arm_feature(env, ARM_FEATURE_V8)); + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, false); + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; + ignore_stackfaults =3D v7m_push_stack(cpu); + qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe= : " + "failed exception return integrity check\n"); + v7m_exception_taken(cpu, excret, false, ignore_stackfaults); + return; + } + + /* Otherwise, we have a successful exception exit. */ + arm_clear_exclusive(env); + arm_rebuild_hflags(env); + qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); +} + +static bool do_v7m_function_return(ARMCPU *cpu) +{ + /* + * v8M security extensions magic function return. + * We may either: + * (1) throw an exception (longjump) + * (2) return true if we successfully handled the function return + * (3) return false if we failed a consistency check and have + * pended a UsageFault that needs to be taken now + * + * At this point the magic return value is split between env->regs[15] + * and env->thumb. We don't bother to reconstitute it because we don't + * need it (all values are handled the same way). + */ + CPUARMState *env =3D &cpu->env; + uint32_t newpc, newpsr, newpsr_exc; + + qemu_log_mask(CPU_LOG_INT, "...really v7M secure function return\n"); + + { + bool threadmode, spsel; + TCGMemOpIdx oi; + ARMMMUIdx mmu_idx; + uint32_t *frame_sp_p; + uint32_t frameptr; + + /* Pull the return address and IPSR from the Secure stack */ + threadmode =3D !arm_v7m_is_handler_mode(env); + spsel =3D env->v7m.control[M_REG_S] & R_V7M_CONTROL_SPSEL_MASK; + + frame_sp_p =3D get_v7m_sp_ptr(env, true, threadmode, spsel); + frameptr =3D *frame_sp_p; + + /* + * These loads may throw an exception (for MPU faults). We want to + * do them as secure, so work out what MMU index that is. + */ + mmu_idx =3D arm_v7m_mmu_idx_for_secstate(env, true); + oi =3D make_memop_idx(MO_LE, arm_to_core_mmu_idx(mmu_idx)); + newpc =3D helper_le_ldul_mmu(env, frameptr, oi, 0); + newpsr =3D helper_le_ldul_mmu(env, frameptr + 4, oi, 0); + + /* Consistency checks on new IPSR */ + newpsr_exc =3D newpsr & XPSR_EXCP; + if (!((env->v7m.exception =3D=3D 0 && newpsr_exc =3D=3D 0) || + (env->v7m.exception =3D=3D 1 && newpsr_exc !=3D 0))) { + /* Pend the fault and tell our caller to take it */ + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, + env->v7m.secure); + qemu_log_mask(CPU_LOG_INT, + "...taking INVPC UsageFault: " + "IPSR consistency check failed\n"); + return false; + } + + *frame_sp_p =3D frameptr + 8; + } + + /* This invalidates frame_sp_p */ + switch_v7m_security_state(env, true); + env->v7m.exception =3D newpsr_exc; + env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_SFPA_MASK; + if (newpsr & XPSR_SFPA) { + env->v7m.control[M_REG_S] |=3D R_V7M_CONTROL_SFPA_MASK; + } + xpsr_write(env, 0, XPSR_IT); + env->thumb =3D newpc & 1; + env->regs[15] =3D newpc & ~1; + arm_rebuild_hflags(env); + + qemu_log_mask(CPU_LOG_INT, "...function return successful\n"); + return true; +} + +static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, + uint32_t addr, uint16_t *insn) +{ + /* + * Load a 16-bit portion of a v7M instruction, returning true on succe= ss, + * or false on failure (in which case we will have pended the appropri= ate + * exception). + * We need to do the instruction fetch's MPU and SAU checks + * like this because there is no MMU index that would allow + * doing the load with a single function call. Instead we must + * first check that the security attributes permit the load + * and that they don't mismatch on the two halves of the instruction, + * and then we do the load as a secure load (ie using the security + * attributes of the address, not the CPU, as architecturally required= ). + */ + CPUState *cs =3D CPU(cpu); + CPUARMState *env =3D &cpu->env; + V8M_SAttributes sattrs =3D {}; + MemTxAttrs attrs =3D {}; + ARMMMUFaultInfo fi =3D {}; + ARMCacheAttrs cacheattrs =3D {}; + MemTxResult txres; + target_ulong page_size; + hwaddr physaddr; + int prot; + + v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, &sattrs); + if (!sattrs.nsc || sattrs.ns) { + /* + * This must be the second half of the insn, and it straddles a + * region boundary with the second half not being S&NSC. + */ + env->v7m.sfsr |=3D R_V7M_SFSR_INVEP_MASK; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); + qemu_log_mask(CPU_LOG_INT, + "...really SecureFault with SFSR.INVEP\n"); + return false; + } + if (get_phys_addr(env, addr, MMU_INST_FETCH, mmu_idx, &physaddr, + &attrs, &prot, &page_size, &fi, &cacheattrs)) { + /* the MPU lookup failed */ + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_IACCVIOL_MASK; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, env->v7m.secur= e); + qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL= \n"); + return false; + } + *insn =3D address_space_lduw_le(arm_addressspace(cs, attrs), physaddr, + attrs, &txres); + if (txres !=3D MEMTX_OK) { + env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_IBUSERR_MASK; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); + qemu_log_mask(CPU_LOG_INT, "...really BusFault with CFSR.IBUSERR\n= "); + return false; + } + return true; +} + +static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx, + uint32_t addr, uint32_t *spdata) +{ + /* + * Read a word of data from the stack for the SG instruction, + * writing the value into *spdata. If the load succeeds, return + * true; otherwise pend an appropriate exception and return false. + * (We can't use data load helpers here that throw an exception + * because of the context we're called in, which is halfway through + * arm_v7m_cpu_do_interrupt().) + */ + CPUState *cs =3D CPU(cpu); + CPUARMState *env =3D &cpu->env; + MemTxAttrs attrs =3D {}; + MemTxResult txres; + target_ulong page_size; + hwaddr physaddr; + int prot; + ARMMMUFaultInfo fi =3D {}; + ARMCacheAttrs cacheattrs =3D {}; + uint32_t value; + + if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr, + &attrs, &prot, &page_size, &fi, &cacheattrs)) { + /* MPU/SAU lookup failed */ + if (fi.type =3D=3D ARMFault_QEMU_SFault) { + qemu_log_mask(CPU_LOG_INT, + "...SecureFault during stack word read\n"); + env->v7m.sfsr |=3D R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVAL= ID_MASK; + env->v7m.sfar =3D addr; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); + } else { + qemu_log_mask(CPU_LOG_INT, + "...MemManageFault during stack word read\n"); + env->v7m.cfsr[M_REG_S] |=3D R_V7M_CFSR_DACCVIOL_MASK | + R_V7M_CFSR_MMARVALID_MASK; + env->v7m.mmfar[M_REG_S] =3D addr; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, false); + } + return false; + } + value =3D address_space_ldl(arm_addressspace(cs, attrs), physaddr, + attrs, &txres); + if (txres !=3D MEMTX_OK) { + /* BusFault trying to read the data */ + qemu_log_mask(CPU_LOG_INT, + "...BusFault during stack word read\n"); + env->v7m.cfsr[M_REG_NS] |=3D + (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK); + env->v7m.bfar =3D addr; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); + return false; + } + + *spdata =3D value; + return true; +} + +static bool v7m_handle_execute_nsc(ARMCPU *cpu) +{ + /* + * Check whether this attempt to execute code in a Secure & NS-Callable + * memory region is for an SG instruction; if so, then emulate the + * effect of the SG instruction and return true. Otherwise pend + * the correct kind of exception and return false. + */ + CPUARMState *env =3D &cpu->env; + ARMMMUIdx mmu_idx; + uint16_t insn; + + /* + * We should never get here unless get_phys_addr_pmsav8() caused + * an exception for NS executing in S&NSC memory. + */ + assert(!env->v7m.secure); + assert(arm_feature(env, ARM_FEATURE_M_SECURITY)); + + /* We want to do the MPU lookup as secure; work out what mmu_idx that = is */ + mmu_idx =3D arm_v7m_mmu_idx_for_secstate(env, true); + + if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) { + return false; + } + + if (!env->thumb) { + goto gen_invep; + } + + if (insn !=3D 0xe97f) { + /* + * Not an SG instruction first half (we choose the IMPDEF + * early-SG-check option). + */ + goto gen_invep; + } + + if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) { + return false; + } + + if (insn !=3D 0xe97f) { + /* + * Not an SG instruction second half (yes, both halves of the SG + * insn have the same hex value) + */ + goto gen_invep; + } + + /* + * OK, we have confirmed that we really have an SG instruction. + * We know we're NS in S memory so don't need to repeat those checks. + */ + qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx= 32 + ", executing it\n", env->regs[15]); + + if (cpu_isar_feature(aa32_m_sec_state, cpu) && + !arm_v7m_is_handler_mode(env)) { + /* + * v8.1M exception stack frame integrity check. Note that we + * must perform the memory access even if CCR_S.TRD is zero + * and we aren't going to check what the data loaded is. + */ + uint32_t spdata, sp; + + /* + * We know we are currently NS, so the S stack pointers must be + * in other_ss_{psp,msp}, not in regs[13]/other_sp. + */ + sp =3D v7m_using_psp(env) ? env->v7m.other_ss_psp : env->v7m.other= _ss_msp; + if (!v7m_read_sg_stack_word(cpu, mmu_idx, sp, &spdata)) { + /* Stack access failed and an exception has been pended */ + return false; + } + + if (env->v7m.ccr[M_REG_S] & R_V7M_CCR_TRD_MASK) { + if (((spdata & ~1) =3D=3D 0xfefa125a) || + !(env->v7m.control[M_REG_S] & 1)) { + goto gen_invep; + } + } + } + + env->regs[14] &=3D ~1; + env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_SFPA_MASK; + switch_v7m_security_state(env, true); + xpsr_write(env, 0, XPSR_IT); + env->regs[15] +=3D 4; + arm_rebuild_hflags(env); + return true; + +gen_invep: + env->v7m.sfsr |=3D R_V7M_SFSR_INVEP_MASK; + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); + qemu_log_mask(CPU_LOG_INT, + "...really SecureFault with SFSR.INVEP\n"); + return false; +} + +void arm_v7m_cpu_do_interrupt(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + uint32_t lr; + bool ignore_stackfaults; + + arm_log_exception(cs->exception_index); + + /* + * For exceptions we just mark as pending on the NVIC, and let that + * handle it. + */ + switch (cs->exception_index) { + case EXCP_UDEF: + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.sec= ure); + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_UNDEFINSTR_MASK; + break; + case EXCP_NOCP: + { + /* + * NOCP might be directed to something other than the current + * security state if this fault is because of NSACR; we indicate + * the target security state using exception.target_el. + */ + int target_secstate; + + if (env->exception.target_el =3D=3D 3) { + target_secstate =3D M_REG_S; + } else { + target_secstate =3D env->v7m.secure; + } + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, target_secst= ate); + env->v7m.cfsr[target_secstate] |=3D R_V7M_CFSR_NOCP_MASK; + break; + } + case EXCP_INVSTATE: + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.sec= ure); + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVSTATE_MASK; + break; + case EXCP_STKOF: + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.sec= ure); + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_STKOF_MASK; + break; + case EXCP_LSERR: + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); + env->v7m.sfsr |=3D R_V7M_SFSR_LSERR_MASK; + break; + case EXCP_UNALIGNED: + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.sec= ure); + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_UNALIGNED_MASK; + break; + case EXCP_SWI: + /* The PC already points to the next instruction. */ + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secur= e); + break; + case EXCP_PREFETCH_ABORT: + case EXCP_DATA_ABORT: + /* + * Note that for M profile we don't have a guest facing FSR, but + * the env->exception.fsr will be populated by the code that + * raises the fault, in the A profile short-descriptor format. + */ + switch (env->exception.fsr & 0xf) { + case M_FAKE_FSR_NSC_EXEC: + /* + * Exception generated when we try to execute code at an addre= ss + * which is marked as Secure & Non-Secure Callable and the CPU + * is in the Non-Secure state. The only instruction which can + * be executed like this is SG (and that only if both halves of + * the SG instruction have the same security attributes.) + * Everything else must generate an INVEP SecureFault, so we + * emulate the SG instruction here. + */ + if (v7m_handle_execute_nsc(cpu)) { + return; + } + break; + case M_FAKE_FSR_SFAULT: + /* + * Various flavours of SecureFault for attempts to execute or + * access data in the wrong security state. + */ + switch (cs->exception_index) { + case EXCP_PREFETCH_ABORT: + if (env->v7m.secure) { + env->v7m.sfsr |=3D R_V7M_SFSR_INVTRAN_MASK; + qemu_log_mask(CPU_LOG_INT, + "...really SecureFault with SFSR.INVTRAN= \n"); + } else { + env->v7m.sfsr |=3D R_V7M_SFSR_INVEP_MASK; + qemu_log_mask(CPU_LOG_INT, + "...really SecureFault with SFSR.INVEP\n= "); + } + break; + case EXCP_DATA_ABORT: + /* This must be an NS access to S memory */ + env->v7m.sfsr |=3D R_V7M_SFSR_AUVIOL_MASK; + qemu_log_mask(CPU_LOG_INT, + "...really SecureFault with SFSR.AUVIOL\n"); + break; + } + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); + break; + case 0x8: /* External Abort */ + switch (cs->exception_index) { + case EXCP_PREFETCH_ABORT: + env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_IBUSERR_MASK; + qemu_log_mask(CPU_LOG_INT, "...with CFSR.IBUSERR\n"); + break; + case EXCP_DATA_ABORT: + env->v7m.cfsr[M_REG_NS] |=3D + (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK= ); + env->v7m.bfar =3D env->exception.vaddress; + qemu_log_mask(CPU_LOG_INT, + "...with CFSR.PRECISERR and BFAR 0x%x\n", + env->v7m.bfar); + break; + } + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false); + break; + default: + /* + * All other FSR values are either MPU faults or "can't happen + * for M profile" cases. + */ + switch (cs->exception_index) { + case EXCP_PREFETCH_ABORT: + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_IACCVIOL_MA= SK; + qemu_log_mask(CPU_LOG_INT, "...with CFSR.IACCVIOL\n"); + break; + case EXCP_DATA_ABORT: + env->v7m.cfsr[env->v7m.secure] |=3D + (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK); + env->v7m.mmfar[env->v7m.secure] =3D env->exception.vaddres= s; + qemu_log_mask(CPU_LOG_INT, + "...with CFSR.DACCVIOL and MMFAR 0x%x\n", + env->v7m.mmfar[env->v7m.secure]); + break; + } + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, + env->v7m.secure); + break; + } + break; + case EXCP_SEMIHOST: + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%x\n", + env->regs[0]); + env->regs[0] =3D do_common_semihosting(cs); + env->regs[15] +=3D env->thumb ? 2 : 4; + return; + case EXCP_BKPT: + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false); + break; + case EXCP_IRQ: + break; + case EXCP_EXCEPTION_EXIT: + if (env->regs[15] < EXC_RETURN_MIN_MAGIC) { + /* Must be v8M security extension function return */ + assert(env->regs[15] >=3D FNC_RETURN_MIN_MAGIC); + assert(arm_feature(env, ARM_FEATURE_M_SECURITY)); + if (do_v7m_function_return(cpu)) { + return; + } + } else { + do_v7m_exception_exit(cpu); + return; + } + break; + case EXCP_LAZYFP: + /* + * We already pended the specific exception in the NVIC in the + * v7m_preserve_fp_state() helper function. + */ + break; + default: + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); + return; /* Never happens. Keep compiler happy. */ + } + + if (arm_feature(env, ARM_FEATURE_V8)) { + lr =3D R_V7M_EXCRET_RES1_MASK | + R_V7M_EXCRET_DCRS_MASK; + /* + * The S bit indicates whether we should return to Secure + * or NonSecure (ie our current state). + * The ES bit indicates whether we're taking this exception + * to Secure or NonSecure (ie our target state). We set it + * later, in v7m_exception_taken(). + * The SPSEL bit is also set in v7m_exception_taken() for v8M. + * This corresponds to the ARM ARM pseudocode for v8M setting + * some LR bits in PushStack() and some in ExceptionTaken(); + * the distinction matters for the tailchain cases where we + * can take an exception without pushing the stack. + */ + if (env->v7m.secure) { + lr |=3D R_V7M_EXCRET_S_MASK; + } + } else { + lr =3D R_V7M_EXCRET_RES1_MASK | + R_V7M_EXCRET_S_MASK | + R_V7M_EXCRET_DCRS_MASK | + R_V7M_EXCRET_ES_MASK; + if (env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK) { + lr |=3D R_V7M_EXCRET_SPSEL_MASK; + } + } + if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) { + lr |=3D R_V7M_EXCRET_FTYPE_MASK; + } + if (!arm_v7m_is_handler_mode(env)) { + lr |=3D R_V7M_EXCRET_MODE_MASK; + } + + ignore_stackfaults =3D v7m_push_stack(cpu); + v7m_exception_taken(cpu, lr, false, ignore_stackfaults); +} + +uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) +{ + unsigned el =3D arm_current_el(env); + + /* First handle registers which unprivileged can read */ + switch (reg) { + case 0 ... 7: /* xPSR sub-fields */ + return v7m_mrs_xpsr(env, reg, el); + case 20: /* CONTROL */ + return v7m_mrs_control(env, env->v7m.secure); + case 0x94: /* CONTROL_NS */ + /* + * We have to handle this here because unprivileged Secure code + * can read the NS CONTROL register. + */ + if (!env->v7m.secure) { + return 0; + } + return env->v7m.control[M_REG_NS] | + (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK); + } + + if (el =3D=3D 0) { + return 0; /* unprivileged reads others as zero */ + } + + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + switch (reg) { + case 0x88: /* MSP_NS */ + if (!env->v7m.secure) { + return 0; + } + return env->v7m.other_ss_msp; + case 0x89: /* PSP_NS */ + if (!env->v7m.secure) { + return 0; + } + return env->v7m.other_ss_psp; + case 0x8a: /* MSPLIM_NS */ + if (!env->v7m.secure) { + return 0; + } + return env->v7m.msplim[M_REG_NS]; + case 0x8b: /* PSPLIM_NS */ + if (!env->v7m.secure) { + return 0; + } + return env->v7m.psplim[M_REG_NS]; + case 0x90: /* PRIMASK_NS */ + if (!env->v7m.secure) { + return 0; + } + return env->v7m.primask[M_REG_NS]; + case 0x91: /* BASEPRI_NS */ + if (!env->v7m.secure) { + return 0; + } + return env->v7m.basepri[M_REG_NS]; + case 0x93: /* FAULTMASK_NS */ + if (!env->v7m.secure) { + return 0; + } + return env->v7m.faultmask[M_REG_NS]; + case 0x98: /* SP_NS */ + { + /* + * This gives the non-secure SP selected based on whether we're + * currently in handler mode or not, using the NS CONTROL.SPSE= L. + */ + bool spsel =3D env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSE= L_MASK; + + if (!env->v7m.secure) { + return 0; + } + if (!arm_v7m_is_handler_mode(env) && spsel) { + return env->v7m.other_ss_psp; + } else { + return env->v7m.other_ss_msp; + } + } + default: + break; + } + } + + switch (reg) { + case 8: /* MSP */ + return v7m_using_psp(env) ? env->v7m.other_sp : env->regs[13]; + case 9: /* PSP */ + return v7m_using_psp(env) ? env->regs[13] : env->v7m.other_sp; + case 10: /* MSPLIM */ + if (!arm_feature(env, ARM_FEATURE_V8)) { + goto bad_reg; + } + return env->v7m.msplim[env->v7m.secure]; + case 11: /* PSPLIM */ + if (!arm_feature(env, ARM_FEATURE_V8)) { + goto bad_reg; + } + return env->v7m.psplim[env->v7m.secure]; + case 16: /* PRIMASK */ + return env->v7m.primask[env->v7m.secure]; + case 17: /* BASEPRI */ + case 18: /* BASEPRI_MAX */ + return env->v7m.basepri[env->v7m.secure]; + case 19: /* FAULTMASK */ + return env->v7m.faultmask[env->v7m.secure]; + default: + bad_reg: + qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special" + " register %d\n", reg); + return 0; + } +} + +void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) +{ + /* + * We're passed bits [11..0] of the instruction; extract + * SYSm and the mask bits. + * Invalid combinations of SYSm and mask are UNPREDICTABLE; + * we choose to treat them as if the mask bits were valid. + * NB that the pseudocode 'mask' variable is bits [11..10], + * whereas ours is [11..8]. + */ + uint32_t mask =3D extract32(maskreg, 8, 4); + uint32_t reg =3D extract32(maskreg, 0, 8); + int cur_el =3D arm_current_el(env); + + if (cur_el =3D=3D 0 && reg > 7 && reg !=3D 20) { + /* + * only xPSR sub-fields and CONTROL.SFPA may be written by + * unprivileged code + */ + return; + } + + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + switch (reg) { + case 0x88: /* MSP_NS */ + if (!env->v7m.secure) { + return; + } + env->v7m.other_ss_msp =3D val; + return; + case 0x89: /* PSP_NS */ + if (!env->v7m.secure) { + return; + } + env->v7m.other_ss_psp =3D val; + return; + case 0x8a: /* MSPLIM_NS */ + if (!env->v7m.secure) { + return; + } + env->v7m.msplim[M_REG_NS] =3D val & ~7; + return; + case 0x8b: /* PSPLIM_NS */ + if (!env->v7m.secure) { + return; + } + env->v7m.psplim[M_REG_NS] =3D val & ~7; + return; + case 0x90: /* PRIMASK_NS */ + if (!env->v7m.secure) { + return; + } + env->v7m.primask[M_REG_NS] =3D val & 1; + return; + case 0x91: /* BASEPRI_NS */ + if (!env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_MAIN))= { + return; + } + env->v7m.basepri[M_REG_NS] =3D val & 0xff; + return; + case 0x93: /* FAULTMASK_NS */ + if (!env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_MAIN))= { + return; + } + env->v7m.faultmask[M_REG_NS] =3D val & 1; + return; + case 0x94: /* CONTROL_NS */ + if (!env->v7m.secure) { + return; + } + write_v7m_control_spsel_for_secstate(env, + val & R_V7M_CONTROL_SPSEL= _MASK, + M_REG_NS); + if (arm_feature(env, ARM_FEATURE_M_MAIN)) { + env->v7m.control[M_REG_NS] &=3D ~R_V7M_CONTROL_NPRIV_MASK; + env->v7m.control[M_REG_NS] |=3D val & R_V7M_CONTROL_NPRIV_= MASK; + } + /* + * SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 =3D=3D 0, + * RES0 if the FPU is not present, and is stored in the S bank + */ + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) && + extract32(env->v7m.nsacr, 10, 1)) { + env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_FPCA_MASK; + env->v7m.control[M_REG_S] |=3D val & R_V7M_CONTROL_FPCA_MA= SK; + } + return; + case 0x98: /* SP_NS */ + { + /* + * This gives the non-secure SP selected based on whether we're + * currently in handler mode or not, using the NS CONTROL.SPSE= L. + */ + bool spsel =3D env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSE= L_MASK; + bool is_psp =3D !arm_v7m_is_handler_mode(env) && spsel; + uint32_t limit; + + if (!env->v7m.secure) { + return; + } + + limit =3D is_psp ? env->v7m.psplim[false] : env->v7m.msplim[fa= lse]; + + if (val < limit) { + CPUState *cs =3D env_cpu(env); + + cpu_restore_state(cs, GETPC(), true); + raise_exception(env, EXCP_STKOF, 0, 1); + } + + if (is_psp) { + env->v7m.other_ss_psp =3D val; + } else { + env->v7m.other_ss_msp =3D val; + } + return; + } + default: + break; + } + } + + switch (reg) { + case 0 ... 7: /* xPSR sub-fields */ + v7m_msr_xpsr(env, mask, reg, val); + break; + case 8: /* MSP */ + if (v7m_using_psp(env)) { + env->v7m.other_sp =3D val; + } else { + env->regs[13] =3D val; + } + break; + case 9: /* PSP */ + if (v7m_using_psp(env)) { + env->regs[13] =3D val; + } else { + env->v7m.other_sp =3D val; + } + break; + case 10: /* MSPLIM */ + if (!arm_feature(env, ARM_FEATURE_V8)) { + goto bad_reg; + } + env->v7m.msplim[env->v7m.secure] =3D val & ~7; + break; + case 11: /* PSPLIM */ + if (!arm_feature(env, ARM_FEATURE_V8)) { + goto bad_reg; + } + env->v7m.psplim[env->v7m.secure] =3D val & ~7; + break; + case 16: /* PRIMASK */ + env->v7m.primask[env->v7m.secure] =3D val & 1; + break; + case 17: /* BASEPRI */ + if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { + goto bad_reg; + } + env->v7m.basepri[env->v7m.secure] =3D val & 0xff; + break; + case 18: /* BASEPRI_MAX */ + if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { + goto bad_reg; + } + val &=3D 0xff; + if (val !=3D 0 && (val < env->v7m.basepri[env->v7m.secure] + || env->v7m.basepri[env->v7m.secure] =3D=3D 0)) { + env->v7m.basepri[env->v7m.secure] =3D val; + } + break; + case 19: /* FAULTMASK */ + if (!arm_feature(env, ARM_FEATURE_M_MAIN)) { + goto bad_reg; + } + env->v7m.faultmask[env->v7m.secure] =3D val & 1; + break; + case 20: /* CONTROL */ + /* + * Writing to the SPSEL bit only has an effect if we are in + * thread mode; other bits can be updated by any privileged code. + * write_v7m_control_spsel() deals with updating the SPSEL bit in + * env->v7m.control, so we only need update the others. + * For v7M, we must just ignore explicit writes to SPSEL in handler + * mode; for v8M the write is permitted but will have no effect. + * All these bits are writes-ignored from non-privileged code, + * except for SFPA. + */ + if (cur_el > 0 && (arm_feature(env, ARM_FEATURE_V8) || + !arm_v7m_is_handler_mode(env))) { + write_v7m_control_spsel(env, (val & R_V7M_CONTROL_SPSEL_MASK) = !=3D 0); + } + if (cur_el > 0 && arm_feature(env, ARM_FEATURE_M_MAIN)) { + env->v7m.control[env->v7m.secure] &=3D ~R_V7M_CONTROL_NPRIV_MA= SK; + env->v7m.control[env->v7m.secure] |=3D val & R_V7M_CONTROL_NPR= IV_MASK; + } + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { + /* + * SFPA is RAZ/WI from NS or if no FPU. + * FPCA is RO if NSACR.CP10 =3D=3D 0, RES0 if the FPU is not p= resent. + * Both are stored in the S bank. + */ + if (env->v7m.secure) { + env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_SFPA_MASK; + env->v7m.control[M_REG_S] |=3D val & R_V7M_CONTROL_SFPA_MA= SK; + } + if (cur_el > 0 && + (env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_SECURI= TY) || + extract32(env->v7m.nsacr, 10, 1))) { + env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_FPCA_MASK; + env->v7m.control[M_REG_S] |=3D val & R_V7M_CONTROL_FPCA_MA= SK; + } + } + break; + default: + bad_reg: + qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special" + " register %d\n", reg); + return; + } +} + +uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) +{ + /* Implement the TT instruction. op is bits [7:6] of the insn. */ + bool forceunpriv =3D op & 1; + bool alt =3D op & 2; + V8M_SAttributes sattrs =3D {}; + uint32_t tt_resp; + bool r, rw, nsr, nsrw, mrvalid; + int prot; + ARMMMUFaultInfo fi =3D {}; + MemTxAttrs attrs =3D {}; + hwaddr phys_addr; + ARMMMUIdx mmu_idx; + uint32_t mregion; + bool targetpriv; + bool targetsec =3D env->v7m.secure; + bool is_subpage; + + /* + * Work out what the security state and privilege level we're + * interested in is... + */ + if (alt) { + targetsec =3D !targetsec; + } + + if (forceunpriv) { + targetpriv =3D false; + } else { + targetpriv =3D arm_v7m_is_handler_mode(env) || + !(env->v7m.control[targetsec] & R_V7M_CONTROL_NPRIV_MASK); + } + + /* ...and then figure out which MMU index this is */ + mmu_idx =3D arm_v7m_mmu_idx_for_secstate_and_priv(env, targetsec, targ= etpriv); + + /* + * We know that the MPU and SAU don't care about the access type + * for our purposes beyond that we don't want to claim to be + * an insn fetch, so we arbitrarily call this a read. + */ + + /* + * MPU region info only available for privileged or if + * inspecting the other MPU state. + */ + if (arm_current_el(env) !=3D 0 || alt) { + /* We can ignore the return value as prot is always set */ + pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, + &phys_addr, &attrs, &prot, &is_subpage, + &fi, &mregion); + if (mregion =3D=3D -1) { + mrvalid =3D false; + mregion =3D 0; + } else { + mrvalid =3D true; + } + r =3D prot & PAGE_READ; + rw =3D prot & PAGE_WRITE; + } else { + r =3D false; + rw =3D false; + mrvalid =3D false; + mregion =3D 0; + } + + if (env->v7m.secure) { + v8m_security_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, &sattrs); + nsr =3D sattrs.ns && r; + nsrw =3D sattrs.ns && rw; + } else { + sattrs.ns =3D true; + nsr =3D false; + nsrw =3D false; + } + + tt_resp =3D (sattrs.iregion << 24) | + (sattrs.irvalid << 23) | + ((!sattrs.ns) << 22) | + (nsrw << 21) | + (nsr << 20) | + (rw << 19) | + (r << 18) | + (sattrs.srvalid << 17) | + (mrvalid << 16) | + (sattrs.sregion << 8) | + mregion; + + return tt_resp; +} diff --git a/target/arm/tcg/user/m_helper.c b/target/arm/tcg/user/m_helper.c new file mode 100644 index 0000000000..65f0ff9976 --- /dev/null +++ b/target/arm/tcg/user/m_helper.c @@ -0,0 +1,97 @@ +/* + * ARM v7m generic helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" + +#include "tcg/m_helper.h" + +void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) +{ + uint32_t mask =3D extract32(maskreg, 8, 4); + uint32_t reg =3D extract32(maskreg, 0, 8); + + switch (reg) { + case 0 ... 7: /* xPSR sub-fields */ + v7m_msr_xpsr(env, mask, reg, val); + break; + case 20: /* CONTROL */ + /* There are no sub-fields that are actually writable from EL0. */ + break; + default: + /* Unprivileged writes to other registers are ignored */ + break; + } +} + +uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) +{ + switch (reg) { + case 0 ... 7: /* xPSR sub-fields */ + return v7m_mrs_xpsr(env, reg, 0); + case 20: /* CONTROL */ + return v7m_mrs_control(env, 0); + default: + /* Unprivileged reads others as zero. */ + return 0; + } +} + +void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) +{ + /* translate.c should never generate calls here in user-only mode */ + g_assert_not_reached(); +} + +void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) +{ + /* translate.c should never generate calls here in user-only mode */ + g_assert_not_reached(); +} + +void HELPER(v7m_preserve_fp_state)(CPUARMState *env) +{ + /* translate.c should never generate calls here in user-only mode */ + g_assert_not_reached(); +} + +void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) +{ + /* translate.c should never generate calls here in user-only mode */ + g_assert_not_reached(); +} + +void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr) +{ + /* translate.c should never generate calls here in user-only mode */ + g_assert_not_reached(); +} + +uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) +{ + /* + * The TT instructions can be used by unprivileged code, but in + * user-only emulation we don't have the MPU. + * Luckily since we know we are NonSecure unprivileged (and that in + * turn means that the A flag wasn't specified), all the bits in the + * register must be zero: + * IREGION: 0 because IRVALID is 0 + * IRVALID: 0 because NS + * S: 0 because NS + * NSRW: 0 because NS + * NSR: 0 because NS + * RW: 0 because unpriv and A flag not set + * R: 0 because unpriv and A flag not set + * SRVALID: 0 because NS + * MRVALID: 0 because unpriv and A flag not set + * SREGION: 0 becaus SRVALID is 0 + * MREGION: 0 because MRVALID is 0 + */ + return 0; +} diff --git a/target/arm/tcg/sysemu/meson.build b/target/arm/tcg/sysemu/meso= n.build index 8f5e955cbd..26014851bd 100644 --- a/target/arm/tcg/sysemu/meson.build +++ b/target/arm/tcg/sysemu/meson.build @@ -1,5 +1,6 @@ arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( 'debug_helper.c', + 'm_helper.c', 'mte_helper.c', 'tlb_helper.c', )) diff --git a/target/arm/tcg/user/meson.build b/target/arm/tcg/user/meson.bu= ild index cdca5d970c..4a652406e8 100644 --- a/target/arm/tcg/user/meson.build +++ b/target/arm/tcg/user/meson.build @@ -1,4 +1,5 @@ arm_user_ss.add(when: 'CONFIG_TCG', if_true: files( + 'm_helper.c', 'mte_helper.c', 'tlb_helper.c', )) --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622826234; cv=none; d=zohomail.com; s=zohoarc; b=P76lkbsLONnusKcnuI6GyGUkpb+7wTQjz517aDrMkrOmXz5jpkCGK+uAmUlBCzrsQhjGuJBBhC/QgTFCUH7OUYud1fvQPSeZ+1YOQpeCGQPjnn7rZDjiT3PeOCSPdzdn+Y5zwQRX/NPzQBrrmbBjMWTOpSnggu3458Ya+NfuN4g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622826234; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=T5Otzi7s7hlRC+aw9fJv8J9Wjbg5nAbpIivh9IdigL8=; b=FUGn8K19b0CFLFrTMg8h/WpmF4XMPvu3jAobxNPpiYv6CvoS4C7zWvamdV2wkAQBOfkhczRq/b9QUHUJLjjPqM6HRI1/KWkmQY/rit6xHsOEE6Gww0UeC74tC5S5zfO8p+zh7s+md/LjJkImKi6dLwp1dN88XiXMGlu6XLNawBw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622826234586180.99402910824426; Fri, 4 Jun 2021 10:03:54 -0700 (PDT) Received: from localhost ([::1]:50878 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDEf-0003jC-CS for importer@patchew.org; Fri, 04 Jun 2021 13:03:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33220) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCkU-0007sw-8v for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:32:42 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:45678) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCkS-00025K-80 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:32:41 -0400 Received: by mail-wr1-x434.google.com with SMTP id z8so9889785wrp.12 for ; Fri, 04 Jun 2021 09:32:39 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id p12sm8462680wme.43.2021.06.04.09.32.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:37 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id F2F9D1FFAC; Fri, 4 Jun 2021 16:53:14 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T5Otzi7s7hlRC+aw9fJv8J9Wjbg5nAbpIivh9IdigL8=; b=LJ0el1L6WupgMwudXB24M6QmkErVD5gVaWie17x8mH5lPE66JPonxEpSNLuvJWYY6X hEWzavu7OdgKmVsIg99T4RQ+IpIJZx88Bk5TzQpaJO5qZuOJk8OETOrDPa67k5roIEic GtmcJ91W4HZaX+mKWJ7wobb++/IBN5gIS1WLV6X/eVQGP05MvmRyTNRAkEmj2IaP5XwS ZCC37NmkIKGScSihyOZAf62IZTzT3ETou8YYk332b4DVZT6GOxRkO+F3hA8F9J/7xuoS XwQyPYL/4uuhmYKM4U13Moh+YUggKcXF2sO5FMWGln9zPUb2e1130hrl7r0YTeFhl2Ep FAhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T5Otzi7s7hlRC+aw9fJv8J9Wjbg5nAbpIivh9IdigL8=; b=rRsEua0zgpBAo69T/zFOPZBqX33WLM1yMR8iYqMoQyaWeo8JTZiGtr5MQzBsGFOAwm MXw637oioUhf45hJR+6Z+fa9Wet1wgn0LgyeTW6+hdbrPbU9vVyYqQ7mdCpaN7ouPa1i 0aPYIYcHtkeDGwis9WfGnjjnJOUqQaKopyfDqyd/yA1pD7aUM/ZWNCl6y2aF0f0Bt30n kyY6fUx6BbkSB823InsO2mf5wX2WwWX/fhG1Z683k7KKvjLh2CYvPsniMNDLMc57aBu3 H+h0BB5veA/Kac2vvYMFNFxznBmym3JQ2cTegPm/YIYiu5tQRh+2UDtEfqBH1joO3W44 uUPg== X-Gm-Message-State: AOAM531ar8vR/ApR0Y12DKT418a1jkMtdxzAs9KFcDOL86FHOj2pgkC9 /I7xgm9WmLF7k0vGl52X+mtRsg== X-Google-Smtp-Source: ABdhPJztBs9KkH9EVXSMrFMh3FHeCAI0RYm87g8BzQ2iOO3pEo+L5UddmUdt8xB1KAU0cQkJe2u9wg== X-Received: by 2002:adf:ebc4:: with SMTP id v4mr4721123wrn.217.1622824358639; Fri, 04 Jun 2021 09:32:38 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 23/99] target/arm: only build psci for TCG Date: Fri, 4 Jun 2021 16:51:56 +0100 Message-Id: <20210604155312.15902-24-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alexander Graf , Richard Henderson , qemu-arm@nongnu.org, Claudio Fontana , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana We do not move psci.c to tcg/ because we expect other hypervisors to use it (waiting for HVF enablement). Signed-off-by: Claudio Fontana Cc: Alexander Graf Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Alex Benn=C3=A9e --- target/arm/meson.build | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/meson.build b/target/arm/meson.build index 0172937b40..a9fdada0cc 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -19,8 +19,12 @@ arm_softmmu_ss.add(files( 'arm-powerctl.c', 'machine.c', 'monitor.c', +)) + +arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( 'psci.c', )) + arm_user_ss =3D ss.source_set() =20 subdir('tcg') --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622824130; cv=none; d=zohomail.com; s=zohoarc; b=JNwkAckpzaPkqpHkrVtBDoNtNOqGXORrr5aS12+cb/z/BNUYmIYcz25vaCHbQSAUaJIuokKFCXrwSmVGN7LAtHPPguzsT0PZIBPrUOTjzHus8yHcs+WMcBpqF050MM2vOFl6wZahf6bBA/1QMnSiB2SG2vDQEl2z6S4dA+g1iwM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622824130; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GCSulBcboNnhY3ZaOpOOMESbDYWsZSCOIUDwjeQhgs4=; b=VGZA3sFiSQ35+Vo+GEun/TZYta7AKghuc+lckgKm95Akez54L2cRwGie9RoccNyg/sTG0edOCj7LwFZKRjbm41jzoVJNPScxp14PtniHjMzuxtxHwO/vmUvMEWOxiO0GtSY/RMULmgp8mPmlEQVYYq5clPMXAuvUahOvz2hidro= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622824130769902.6392491625078; Fri, 4 Jun 2021 09:28:50 -0700 (PDT) Received: from localhost ([::1]:44966 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCgk-0006c7-1g for importer@patchew.org; Fri, 04 Jun 2021 12:28:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51824) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCRI-0002x6-4v for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:52 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:46009) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCRC-0003pF-QP for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:51 -0400 Received: by mail-wr1-x436.google.com with SMTP id z8so9831954wrp.12 for ; Fri, 04 Jun 2021 09:12:46 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id l8sm9299316wrf.0.2021.06.04.09.12.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:12:42 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 1BDFF1FFAE; Fri, 4 Jun 2021 16:53:15 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GCSulBcboNnhY3ZaOpOOMESbDYWsZSCOIUDwjeQhgs4=; b=K+VlibPVepMujXzNtGQBh8v6ArVzXuqim/LVzd/SGYDgZ3mc7+iMaFoQDQXX3M4gGL aWVwCUi3SkYIRe1Z9lWGra7axoT6/IU6M2sADR8uUOPXeINsSaSvuXx32flCfe5Jsfjx FVF4tX662du1+bT1+ya8eb0NUpvTrqWlVdnIYz5LkLGs5HF9pmkegoV8gq4PwJWZ2QJv UDlvk66hlV5iDUzeCxAk79SNiRU8BUh0WlEsAlAEBdDiKCEQZ2N8kmDYrRaAeOF/SW/H PPJBb0dQH+xIeQ4LbRPz9fhyVdjHIqyDuFrC/VE/VoBtscSUXfJFjBVhUW788lYIhh+W fauw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GCSulBcboNnhY3ZaOpOOMESbDYWsZSCOIUDwjeQhgs4=; b=KxKJaoK6xJM4xWIDSR3Ou4GwQfrPqwM2heNqW057pOp0lfKPrupk8r4Exc+0awIGXX 9xwb01qeJX3rND/W/dlhqxdIX0F9YzjOde3dPs3BNqx65Ea33UzFSPifrtnC9x9f9Zw+ 5ttA4y0lqZiOvR+MrVDI8LQ43f4/HiZxIUN5w248D2oQ6PYKX2qCdr42dFP3pbtekfVt MPxCxVBc8k5kT/o7ylxLSbaKdjkQUpGaouLNGVkKpsAoxuegehSSqbxrPc8i7Q5rp8GS WjcTse+QoCNpAYRh3MYfNC+cHXzntCQ11gXKRWaaWIDopzPyVofSP+NRCrHu4b5RHhpp jHlA== X-Gm-Message-State: AOAM531obpmzttaupgYFs8knokcRfppXnlkzAjET9Jv0Kqd9qMMv7Ias K86xryKP6WF40wTmkWVDzjjDzA== X-Google-Smtp-Source: ABdhPJxYSAESxB7xbZSoXwJlOSK7MnCMaJLqh0xi9M1nKIQeORgpSl0F1J8eshvzFMjr0tbVTWKNjQ== X-Received: by 2002:adf:df02:: with SMTP id y2mr4641178wrl.120.1622823165406; Fri, 04 Jun 2021 09:12:45 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 24/99] target/arm: split off cpu-sysemu.c Date: Fri, 4 Jun 2021 16:51:57 +0100 Message-Id: <20210604155312.15902-25-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana move work is needed later on to split things into tcg-specific portions and kvm-specific portions of this Signed-off-by: Claudio Fontana Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/internals.h | 8 ++- target/arm/cpu-sysemu.c | 105 ++++++++++++++++++++++++++++++++++++++++ target/arm/cpu.c | 83 ------------------------------- target/arm/meson.build | 1 + 4 files changed, 113 insertions(+), 84 deletions(-) create mode 100644 target/arm/cpu-sysemu.c diff --git a/target/arm/internals.h b/target/arm/internals.h index 886db56b58..8809334228 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1202,4 +1202,10 @@ static inline uint64_t useronly_maybe_clean_ptr(uint= 32_t desc, uint64_t ptr) return ptr; } =20 -#endif +#ifndef CONFIG_USER_ONLY +void arm_cpu_set_irq(void *opaque, int irq, int level); +void arm_cpu_kvm_set_irq(void *opaque, int irq, int level); +bool arm_cpu_virtio_is_big_endian(CPUState *cs); +#endif /* !CONFIG_USER_ONLY */ + +#endif /* TARGET_ARM_INTERNALS_H */ diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c new file mode 100644 index 0000000000..db1c8cb245 --- /dev/null +++ b/target/arm/cpu-sysemu.c @@ -0,0 +1,105 @@ +/* + * QEMU ARM CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "sysemu/hw_accel.h" +#include "kvm_arm.h" + +void arm_cpu_set_irq(void *opaque, int irq, int level) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + static const int mask[] =3D { + [ARM_CPU_IRQ] =3D CPU_INTERRUPT_HARD, + [ARM_CPU_FIQ] =3D CPU_INTERRUPT_FIQ, + [ARM_CPU_VIRQ] =3D CPU_INTERRUPT_VIRQ, + [ARM_CPU_VFIQ] =3D CPU_INTERRUPT_VFIQ + }; + + if (level) { + env->irq_line_state |=3D mask[irq]; + } else { + env->irq_line_state &=3D ~mask[irq]; + } + + switch (irq) { + case ARM_CPU_VIRQ: + assert(arm_feature(env, ARM_FEATURE_EL2)); + arm_cpu_update_virq(cpu); + break; + case ARM_CPU_VFIQ: + assert(arm_feature(env, ARM_FEATURE_EL2)); + arm_cpu_update_vfiq(cpu); + break; + case ARM_CPU_IRQ: + case ARM_CPU_FIQ: + if (level) { + cpu_interrupt(cs, mask[irq]); + } else { + cpu_reset_interrupt(cs, mask[irq]); + } + break; + default: + g_assert_not_reached(); + } +} + +void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) +{ +#ifdef CONFIG_KVM + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + uint32_t linestate_bit; + int irq_id; + + switch (irq) { + case ARM_CPU_IRQ: + irq_id =3D KVM_ARM_IRQ_CPU_IRQ; + linestate_bit =3D CPU_INTERRUPT_HARD; + break; + case ARM_CPU_FIQ: + irq_id =3D KVM_ARM_IRQ_CPU_FIQ; + linestate_bit =3D CPU_INTERRUPT_FIQ; + break; + default: + g_assert_not_reached(); + } + + if (level) { + env->irq_line_state |=3D linestate_bit; + } else { + env->irq_line_state &=3D ~linestate_bit; + } + kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); +#endif +} + +bool arm_cpu_virtio_is_big_endian(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + cpu_synchronize_state(cs); + return arm_cpu_data_is_big_endian(env); +} diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ad65b60b04..bd8413c161 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -649,89 +649,6 @@ void arm_cpu_update_vfiq(ARMCPU *cpu) } } =20 -#ifndef CONFIG_USER_ONLY -static void arm_cpu_set_irq(void *opaque, int irq, int level) -{ - ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; - CPUState *cs =3D CPU(cpu); - static const int mask[] =3D { - [ARM_CPU_IRQ] =3D CPU_INTERRUPT_HARD, - [ARM_CPU_FIQ] =3D CPU_INTERRUPT_FIQ, - [ARM_CPU_VIRQ] =3D CPU_INTERRUPT_VIRQ, - [ARM_CPU_VFIQ] =3D CPU_INTERRUPT_VFIQ - }; - - if (level) { - env->irq_line_state |=3D mask[irq]; - } else { - env->irq_line_state &=3D ~mask[irq]; - } - - switch (irq) { - case ARM_CPU_VIRQ: - assert(arm_feature(env, ARM_FEATURE_EL2)); - arm_cpu_update_virq(cpu); - break; - case ARM_CPU_VFIQ: - assert(arm_feature(env, ARM_FEATURE_EL2)); - arm_cpu_update_vfiq(cpu); - break; - case ARM_CPU_IRQ: - case ARM_CPU_FIQ: - if (level) { - cpu_interrupt(cs, mask[irq]); - } else { - cpu_reset_interrupt(cs, mask[irq]); - } - break; - default: - g_assert_not_reached(); - } -} - -static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) -{ -#ifdef CONFIG_KVM - ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; - CPUState *cs =3D CPU(cpu); - uint32_t linestate_bit; - int irq_id; - - switch (irq) { - case ARM_CPU_IRQ: - irq_id =3D KVM_ARM_IRQ_CPU_IRQ; - linestate_bit =3D CPU_INTERRUPT_HARD; - break; - case ARM_CPU_FIQ: - irq_id =3D KVM_ARM_IRQ_CPU_FIQ; - linestate_bit =3D CPU_INTERRUPT_FIQ; - break; - default: - g_assert_not_reached(); - } - - if (level) { - env->irq_line_state |=3D linestate_bit; - } else { - env->irq_line_state &=3D ~linestate_bit; - } - kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); -#endif -} - -static bool arm_cpu_virtio_is_big_endian(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - cpu_synchronize_state(cs); - return arm_cpu_data_is_big_endian(env); -} - -#endif - static int print_insn_thumb1(bfd_vma pc, disassemble_info *info) { diff --git a/target/arm/meson.build b/target/arm/meson.build index a9fdada0cc..b75392e3e9 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -17,6 +17,7 @@ arm_softmmu_ss =3D ss.source_set() arm_softmmu_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', + 'cpu-sysemu.c', 'machine.c', 'monitor.c', )) --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622826314; cv=none; d=zohomail.com; s=zohoarc; b=kKetZRKa2hy65CLCiJCktwMX0sYD3GQau04ZGedA3W1DompNUrR00osyeiopM2eWhUZ12whk31tq0hSVjv8t5gJ6zD7wPT+LuL+yJK/UUL+Z/d8h3XreQKuYTdLOl7vgraa2b3szcJ5E7nzOcSZN9Pj50dDtRxmw6W7ekP/eFBs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622826314; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=S7aS1OcWQ66/PtC9FuFs6o6VaPhc4vwGyLuPu8rbtBw=; b=hyT3ODMtS5pPh/wlhtuhYnLpEgakmg6McmLAioRSToCdfGNC2PPsFaGWdTo1Tj4TEy2GvSbl3im8QlTSVe83Ix27NS48gwnLCcjquWNf0JSK/+POB+FDENa7m/zmVcTW8EbKkWjW7UCdkVyOZRUeAX3r1Xmer3O4YPJ8abE5XoM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622826314676471.49218671247763; Fri, 4 Jun 2021 10:05:14 -0700 (PDT) Received: from localhost ([::1]:54222 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDFx-0005z7-TR for importer@patchew.org; Fri, 04 Jun 2021 13:05:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51760) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCRF-0002sI-MV for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:49 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:44008) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCRA-0003nv-1m for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:49 -0400 Received: by mail-wm1-x32e.google.com with SMTP id 3-20020a05600c0243b029019f2f9b2b8aso5918310wmj.2 for ; Fri, 04 Jun 2021 09:12:43 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id b8sm5422422wmd.35.2021.06.04.09.12.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:12:37 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 348D21FFAF; Fri, 4 Jun 2021 16:53:15 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S7aS1OcWQ66/PtC9FuFs6o6VaPhc4vwGyLuPu8rbtBw=; b=x+m82SoI/BQ/TeyWVXAo1IJysggCCsHSsFt6svYkPcG6HLy1LPWQahTsfJ3Riy6iDE Vp0EtCDclVfiVFJHFrbrwQPpzLBrFpodcOnb4VOHGlrixo0+N07HPJ98J8Rq14oBLvDv Ied62TBHW4vm7+uU60Hom+wLQGjNDfJrJMuiH8cAaw4gWhwVR3SeDilTBz0diriiywIC v4OIx983BR+WFxrt9bXSX1mYc3XY2TZRb7Pts8i18u4xolAj5L3Xmj+fe1rqMak2JAm0 K6xmA5pF2Yg2ij9qjIpA5HII3GmvfxOQ4AgxkIgLt+VRlwlVIpQGL62yTqDKWJQbl4qj c6Nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S7aS1OcWQ66/PtC9FuFs6o6VaPhc4vwGyLuPu8rbtBw=; b=PaRj8JofKowq1LQUaJG633hCW8Iwx66ayNqmIPWmShkmJ5jA5+sPjTSnYH5OEAnXaY DdWXTzv/cZtkRq2PMQRB6ilQkxcXR4Eja5UpbdsiwFas0/GdYWwCAxvlZT8KbchNFlvh Kgp9cAoLPiHAhX8VTpbjRl5e7fWxMc4rWLlVovj6mi8lMv/UlRgtWaVUUJsBfLznta/J 2xaccxmSAccrLWCyxKsU/TzhqH/AgEVCmUGqJLh4LE2eRareKELi/1bXL2Y3ejMA8SLv JuRtiglx7n1hGgocYBcADj4X+SVBn2l0K6Lh/qtTVXgEKRyoAJd+QrAm2MoWa4wEgfFH 7r7g== X-Gm-Message-State: AOAM532cjw18xwRCVHKtE87yKguOU9k9x6mZ8MSg7ogP3jWeX9oSMMPB FQvOL6DFz/Ko34L089EhJ4Ajpw== X-Google-Smtp-Source: ABdhPJyubNWPPJWBfmguk/gXOo6E+/YWiv1EB3vxlBINLruztKiu0RMef34WEEyvrm/ckdZKuTrzFA== X-Received: by 2002:a7b:c095:: with SMTP id r21mr4464018wmh.86.1622823162455; Fri, 04 Jun 2021 09:12:42 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 25/99] target/arm: tcg: fix comment style before move to cpu-mmu Date: Fri, 4 Jun 2021 16:51:58 +0100 Message-Id: <20210604155312.15902-26-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana before exporting some functionality from helper.c into a new module, fix the comment style of those functions. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/helper.c | 152 ++++++++++++++++++++++++++-------------- 1 file changed, 101 insertions(+), 51 deletions(-) diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index a66c1f0b9e..2a5022032c 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -10477,7 +10477,8 @@ static inline bool regime_translation_disabled(CPUA= RMState *env, return false; case 0: default: - /* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but + /* + * HFNMIENA set and ENABLE clear is UNPREDICTABLE, but * we warned about that in armv7m_nvic.c when the guest set it. */ return true; @@ -10531,7 +10532,8 @@ static inline uint64_t regime_ttbr(CPUARMState *env= , ARMMMUIdx mmu_idx, =20 #endif /* !CONFIG_USER_ONLY */ =20 -/* Convert a possible stage1+2 MMU index into the appropriate +/* + * Convert a possible stage1+2 MMU index into the appropriate * stage 1 MMU index */ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) @@ -10602,7 +10604,8 @@ static inline bool regime_is_user(CPUARMState *env,= ARMMMUIdx mmu_idx) } } =20 -/* Translate section/page access permissions to page +/* + * Translate section/page access permissions to page * R/W protection flags * * @env: CPUARMState @@ -10658,7 +10661,8 @@ static inline int ap_to_rw_prot(CPUARMState *env, A= RMMMUIdx mmu_idx, } } =20 -/* Translate section/page access permissions to page +/* + * Translate section/page access permissions to page * R/W protection flags. * * @ap: The 2-bit simple AP (AP[2:1]) @@ -10686,7 +10690,8 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mm= u_idx, int ap) return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); } =20 -/* Translate S2 section/page access permissions to protection flags +/* + * Translate S2 section/page access permissions to protection flags * * @env: CPUARMState * @s2ap: The 2-bit stage2 access permissions (S2AP) @@ -10734,7 +10739,8 @@ static int get_S2prot(CPUARMState *env, int s2ap, i= nt xn, bool s1_is_el0) return prot; } =20 -/* Translate section/page access permissions to protection flags +/* + * Translate section/page access permissions to protection flags * * @env: CPUARMState * @mmu_idx: MMU index indicating required translation regime @@ -10771,7 +10777,8 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx m= mu_idx, bool is_aa64, return prot_rw; } =20 - /* TODO have_wxn should be replaced with + /* + * TODO have_wxn should be replaced with * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE * compatible processors have EL2, which is required for [U]WXN. @@ -11043,7 +11050,8 @@ static bool get_phys_addr_v5(CPUARMState *env, uint= 32_t address, phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); *page_size =3D 0x1000; } else { - /* UNPREDICTABLE in ARMv5; we choose to take a + /* + * UNPREDICTABLE in ARMv5; we choose to take a * page translation fault. */ fi->type =3D ARMFault_Translation; @@ -11109,7 +11117,8 @@ static bool get_phys_addr_v6(CPUARMState *env, uint= 32_t address, } type =3D (desc & 3); if (type =3D=3D 0 || (type =3D=3D 3 && !cpu_isar_feature(aa32_pxn, cpu= ))) { - /* Section translation fault, or attempt to use the encoding + /* + * Section translation fault, or attempt to use the encoding * which is Reserved on implementations without PXN. */ fi->type =3D ARMFault_Translation; @@ -11214,7 +11223,8 @@ static bool get_phys_addr_v6(CPUARMState *env, uint= 32_t address, } } if (ns) { - /* The NS bit will (as required by the architecture) have no effec= t if + /* + * The NS bit will (as required by the architecture) have no effec= t if * the CPU doesn't support TZ or this is a non-secure translation * regime, because the attribute will already be non-secure. */ @@ -11296,7 +11306,8 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is= _aa64, int level, return true; } =20 -/* Translate from the 4-bit stage 2 representation of +/* + * Translate from the 4-bit stage 2 representation of * memory attributes (without cache-allocation hints) to * the 8-bit representation of the stage 1 MAIR registers * (which includes allocation hints). @@ -11585,7 +11596,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, stride =3D 9; } =20 - /* Note that QEMU ignores shareability and cacheability attributes, + /* + * Note that QEMU ignores shareability and cacheability attributes, * so we don't need to do anything with the SH, ORGN, IRGN fields * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently @@ -11594,19 +11606,22 @@ static bool get_phys_addr_lpae(CPUARMState *env, = uint64_t address, */ ttbr =3D regime_ttbr(env, mmu_idx, param.select); =20 - /* Here we should have set up all the parameters for the translation: + /* + * Here we should have set up all the parameters for the translation: * inputsize, ttbr, epd, stride, tbi */ =20 if (param.epd) { - /* Translation table walk disabled =3D> Translation fault on TLB m= iss + /* + * Translation table walk disabled =3D> Translation fault on TLB m= iss * Note: This is always 0 on 64-bit EL2 and EL3. */ goto do_fault; } =20 if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2_S) { - /* The starting level depends on the virtual address size (which c= an + /* + * The starting level depends on the virtual address size (which c= an * be up to 48 bits) and the translation granule size. It indicates * the number of strides (stride bits at a time) needed to * consume the bits of the input address. In the pseudocode this i= s: @@ -11619,7 +11634,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, */ level =3D 4 - (inputsize - 4) / stride; } else { - /* For stage 2 translations the starting level is specified by the + /* + * For stage 2 translations the starting level is specified by the * VTCR_EL2.SL0 field (whose interpretation depends on the page si= ze) */ uint32_t sl0 =3D extract32(tcr->raw_tcr, 6, 2); @@ -11659,7 +11675,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, */ descaddr &=3D ~indexmask; =20 - /* The address field in the descriptor goes up to bit 39 for ARMv7 + /* + * The address field in the descriptor goes up to bit 39 for ARMv7 * but up to bit 47 for ARMv8, but we use the descaddrmask * up to bit 39 for AArch32, because we don't need other bits in that = case * to construct next descriptor address (anyway they should be all zer= oes). @@ -11667,7 +11684,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, descaddrmask =3D ((1ull << (aarch64 ? 48 : 40)) - 1) & ~indexmask_grainsize; =20 - /* Secure accesses start with the page table in secure memory and + /* + * Secure accesses start with the page table in secure memory and * can be downgraded to non-secure at any step. Non-secure accesses * remain non-secure. We implement this by just ORing in the NSTable/NS * bits at each step. @@ -11693,7 +11711,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, descaddr =3D descriptor & descaddrmask; =20 if ((descriptor & 2) && (level < 3)) { - /* Table entry. The top five bits are attributes which may + /* + * Table entry. The top five bits are attributes which may * propagate down through lower levels of the table (and * which are all arranged so that 0 means "no effect", so * we can gather them up by ORing in the bits at each level). @@ -11703,7 +11722,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, indexmask =3D indexmask_grainsize; continue; } - /* Block entry at level 1 or 2, or page entry at level 3. + /* + * Block entry at level 1 or 2, or page entry at level 3. * These are basically the same thing, although the number * of bits we pull in from the vaddr varies. */ @@ -11725,15 +11745,17 @@ static bool get_phys_addr_lpae(CPUARMState *env, = uint64_t address, break; } attrs |=3D extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ - /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] =3D= =3D 1 + /* + * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] =3D= =3D 1 * means "force PL1 access only", which means forcing AP[1] to 0. */ attrs &=3D ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] =3D> = AP[1] */ attrs |=3D extract32(tableattrs, 3, 1) << 5; /* APT[1] =3D> A= P[2] */ break; } - /* Here descaddr is the final physical address, and attributes - * are all in attrs. + /* + * Here descaddr is the final physical address, + * and attributes are all in attrs. */ fault_type =3D ARMFault_AccessFlag; if ((attrs & (1 << 8)) =3D=3D 0) { @@ -11760,7 +11782,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, ui= nt64_t address, } =20 if (ns) { - /* The NS bit will (as required by the architecture) have no effec= t if + /* + * The NS bit will (as required by the architecture) have no effec= t if * the CPU doesn't support TZ or this is a non-secure translation * regime, because the attribute will already be non-secure. */ @@ -11814,7 +11837,8 @@ static inline void get_phys_addr_pmsav7_default(CPU= ARMState *env, break; } } else { - /* Default system address map for M profile cores. + /* + * Default system address map for M profile cores. * The architecture specifies which regions are execute-never; * at the MPU level no other checks are defined. */ @@ -11840,7 +11864,8 @@ static inline void get_phys_addr_pmsav7_default(CPU= ARMState *env, static bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool is_user) { - /* Return true if we should use the default memory map as a + /* + * Return true if we should use the default memory map as a * "background" region if there are no hits against any MPU regions. */ CPUARMState *env =3D &cpu->env; @@ -11866,7 +11891,8 @@ static inline bool m_is_ppb_region(CPUARMState *env= , uint32_t address) =20 static inline bool m_is_system_region(CPUARMState *env, uint32_t address) { - /* True if address is in the M profile system region + /* + * True if address is in the M profile system region * 0xe0000000 - 0xffffffff */ return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) = =3D=3D 0x7; @@ -11888,7 +11914,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, =20 if (regime_translation_disabled(env, mmu_idx) || m_is_ppb_region(env, address)) { - /* MPU disabled or M profile PPB access: use default memory map. + /* + * MPU disabled or M profile PPB access: use default memory map. * The other case which uses the default memory map in the * v7M ARM ARM pseudocode is exception vector reads from the vector * table. In QEMU those accesses are done in arm_v7m_load_vector(), @@ -11954,7 +11981,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, =20 srdis_mask =3D srdis ? 0x3 : 0x0; for (i =3D 2; i <=3D 8 && rsize < TARGET_PAGE_BITS; i *=3D= 2) { - /* This will check in groups of 2, 4 and then 8, wheth= er + /* + * This will check in groups of 2, 4 and then 8, wheth= er * the subregion bits are consistent. rsize is increme= nted * back up to give the region size, considering consis= tent * adjacent subregions as one region. Stop testing if = rsize @@ -12062,7 +12090,8 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, static bool v8m_is_sau_exempt(CPUARMState *env, uint32_t address, MMUAccessType access_type) { - /* The architecture specifies that certain address ranges are + /* + * The architecture specifies that certain address ranges are * exempt from v8M SAU/IDAU checks. */ return @@ -12078,7 +12107,8 @@ void v8m_security_lookup(CPUARMState *env, uint32_t= address, MMUAccessType access_type, ARMMMUIdx mmu_i= dx, V8M_SAttributes *sattrs) { - /* Look up the security attributes for this address. Compare the + /* + * Look up the security attributes for this address. Compare the * pseudocode SecurityCheck() function. * We assume the caller has zero-initialized *sattrs. */ @@ -12129,7 +12159,8 @@ void v8m_security_lookup(CPUARMState *env, uint32_t= address, sattrs->subpage =3D true; } if (sattrs->srvalid) { - /* If we hit in more than one region then we must = report + /* + * If we hit in more than one region then we must = report * as Secure, not NS-Callable, with no valid region * number info. */ @@ -12187,7 +12218,8 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, int *prot, bool *is_subpage, ARMMMUFaultInfo *fi, uint32_t *mregion) { - /* Perform a PMSAv8 MPU lookup (without also doing the SAU check + /* + * Perform a PMSAv8 MPU lookup (without also doing the SAU check * that a full phys-to-virt translation does). * mregion is (if not NULL) set to the region number which matched, * or -1 if no region number is returned (MPU off, address did not @@ -12211,7 +12243,8 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, *mregion =3D -1; } =20 - /* Unlike the ARM ARM pseudocode, we don't need to check whether this + /* + * Unlike the ARM ARM pseudocode, we don't need to check whether this * was an exception vector read from the vector table (which is always * done using the default system address map), because those accesses * are done in arm_v7m_load_vector(), which always does a direct @@ -12228,7 +12261,8 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, =20 for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { /* region search */ - /* Note that the base address is bits [31:5] from the register + /* + * Note that the base address is bits [31:5] from the register * with bits [4:0] all zeroes, but the limit address is bits * [31:5] from the register with bits [4:0] all ones. */ @@ -12264,7 +12298,8 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, } =20 if (matchregion !=3D -1) { - /* Multiple regions match -- always a failure (unlike + /* + * Multiple regions match -- always a failure (unlike * PMSAv7 where highest-numbered-region wins) */ fi->type =3D ARMFault_Permission; @@ -12304,7 +12339,8 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t a= ddress, if (*prot && !xn && !(pxn && !is_user)) { *prot |=3D PAGE_EXEC; } - /* We don't need to look the attribute up in the MAIR0/MAIR1 + /* + * We don't need to look the attribute up in the MAIR0/MAIR1 * registers because that only tells us about cacheability. */ if (mregion) { @@ -12332,7 +12368,8 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, = uint32_t address, if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs); if (access_type =3D=3D MMU_INST_FETCH) { - /* Instruction fetches always use the MMU bank and the + /* + * Instruction fetches always use the MMU bank and the * transaction attribute determined by the fetch address, * regardless of CPU state. This is painful for QEMU * to handle, because it would mean we need to encode @@ -12361,14 +12398,16 @@ static bool get_phys_addr_pmsav8(CPUARMState *env= , uint32_t address, return true; } } else { - /* For data accesses we always use the MMU bank indicated + /* + * For data accesses we always use the MMU bank indicated * by the current CPU state, but the security attributes * might downgrade a secure access to nonsecure. */ if (sattrs.ns) { txattrs->secure =3D false; } else if (!secure) { - /* NS access to S memory must fault. + /* + * NS access to S memory must fault. * Architecturally we should first check whether the * MPU information for this address indicates that we * are doing an unaligned access to Device memory, which @@ -12416,8 +12455,10 @@ static bool get_phys_addr_pmsav5(CPUARMState *env,= uint32_t address, continue; } mask =3D 1 << ((base >> 1) & 0x1f); - /* Keep this shift separate from the above to avoid an - (undefined) << 32. */ + /* + * Keep this shift separate from the above to avoid an + * (undefined) << 32 + */ mask =3D (mask << 1) - 1; if (((base ^ address) & ~mask) =3D=3D 0) { break; @@ -12477,7 +12518,8 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, = uint32_t address, return false; } =20 -/* Combine either inner or outer cacheability attributes for normal +/* + * Combine either inner or outer cacheability attributes for normal * memory, according to table D4-42 and pseudocode procedure * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). * @@ -12493,7 +12535,8 @@ static uint8_t combine_cacheattr_nibble(uint8_t s1,= uint8_t s2) /* stage 1 write-through takes precedence */ return s1; } else if (extract32(s2, 2, 2) =3D=3D 2) { - /* stage 2 write-through takes precedence, but the allocation hint + /* + * stage 2 write-through takes precedence, but the allocation hint * is still taken from stage 1 */ return (2 << 2) | extract32(s1, 0, 2); @@ -12502,7 +12545,8 @@ static uint8_t combine_cacheattr_nibble(uint8_t s1,= uint8_t s2) } } =20 -/* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 +/* + * Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 * and CombineS1S2Desc() * * @s1: Attributes from stage 1 walk @@ -12552,7 +12596,8 @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAtt= rs s1, ARMCacheAttrs s2) ret.attrs =3D 0xc; /* GRE */ } =20 - /* Any location for which the resultant memory type is any + /* + * Any location for which the resultant memory type is any * type of Device memory is always treated as Outer Shareable. */ ret.shareability =3D 2; @@ -12562,7 +12607,8 @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAtt= rs s1, ARMCacheAttrs s2) | combine_cacheattr_nibble(s1lo, s2lo); =20 if (ret.attrs =3D=3D 0x44) { - /* Any location for which the resultant memory type is Normal + /* + * Any location for which the resultant memory type is Normal * Inner Non-cacheable, Outer Non-cacheable is always treated * as Outer Shareable. */ @@ -12579,7 +12625,8 @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAtt= rs s1, ARMCacheAttrs s2) } =20 =20 -/* get_phys_addr - get the physical address for this virtual address +/* + * get_phys_addr - get the physical address for this virtual address * * Find the physical address corresponding to the given virtual address, * by doing a translation table walk on MMU based systems or using the @@ -12614,7 +12661,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, ARMMMUIdx s1_mmu_idx =3D stage_1_mmu_idx(mmu_idx); =20 if (mmu_idx !=3D s1_mmu_idx) { - /* Call ourselves recursively to do the stage 1 and then stage 2 + /* + * Call ourselves recursively to do the stage 1 and then stage 2 * translations if mmu_idx is a two-stage regime. */ if (arm_feature(env, ARM_FEATURE_EL2)) { @@ -12686,14 +12734,16 @@ bool get_phys_addr(CPUARMState *env, target_ulong= address, } } =20 - /* The page table entries may downgrade secure to non-secure, but + /* + * The page table entries may downgrade secure to non-secure, but * cannot upgrade an non-secure translation regime's attributes * to secure. */ attrs->secure =3D regime_is_secure(env, mmu_idx); attrs->user =3D regime_is_user(env, mmu_idx); =20 - /* Fast Context Switch Extension. This doesn't exist at all in v8. + /* + * Fast Context Switch Extension. This doesn't exist at all in v8. * In v7 and earlier it affects all stage 1 translations. */ if (address < 0x02000000 && mmu_idx !=3D ARMMMUIdx_Stage2 --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622823783; cv=none; d=zohomail.com; s=zohoarc; b=CY8zG5R1rmcfDGTyvAjRhb+vjWw40eL+6ZAzuL8hOgpm1xrvlH04Agm86McD4CQpMYLQeEIcm1STiO8sC1OpEnU9aQyW3PHnZUWrv/MfLzDLS2dUhuLT1nTis/MZ1vyRH6zYfPBXeyLVXpOQdp5pQMVK860ekGi45tTsMrqmrNs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622823783; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Hzn7/GNrn6dmW6d6QUtsqKB5J40Zcw3XmUUuIt9agbs=; b=ZYl1fipQmcIlPCW8k0W9ENCiOE222KW/YHNHDYJnrpDkhUi8z0G/x6ZlhXfkuiMPEYEr3UqkpI9a8r201A/xJkGqFY2kMfMt9h1utcIdb9qVNAB5bPo1AKJXXXsRToY3K+h/2OBSkV9g80PYW8mhheCyg8LxEXHpYuOOP5EtPII= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622823783859881.29425054039; Fri, 4 Jun 2021 09:23:03 -0700 (PDT) Received: from localhost ([::1]:48894 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCb8-00073s-V0 for importer@patchew.org; Fri, 04 Jun 2021 12:23:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCIC-00005B-N5 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:29 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:55101) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHk-0005vE-I4 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:28 -0400 Received: by mail-wm1-x335.google.com with SMTP id o127so5677620wmo.4 for ; Fri, 04 Jun 2021 09:03:00 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id p9sm5669885wmq.48.2021.06.04.09.02.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:53 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 759021FF8C; Fri, 4 Jun 2021 16:53:15 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Hzn7/GNrn6dmW6d6QUtsqKB5J40Zcw3XmUUuIt9agbs=; b=KmKS4zAgplYKq+zWodGDHz2mCqTaGJa3C4cuFQO9RC7MR/4HZYzjlhc/C9mH3KZvfi eFPVViNat9Up7jTHg+ESkdd/10ZJeB1QvxfYSxs1uSMGk+cg6acXTw/Qmhrepef0HaDM 3vfbUTp8mdkWZqZmw4MlYwowAm670ut/RvRad4/fl2vzQ2+dZCjiPmZU1jitNMMwC80k sNamP9N5xI40XOSBOm0nlzjf1G8FiFAz0U/I0ZQYPoWkEu++7+uhu3Bw/kD/KUNHBFld XpDASjEE6MeGGpHW9Usj61NGKK4XMPBIGUMF8WlMdEqTDSYh1RfZtXfq38y4GC9mNpZm B92w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Hzn7/GNrn6dmW6d6QUtsqKB5J40Zcw3XmUUuIt9agbs=; b=fi9R8gxzXH6iC9WjEhGnXc3aRbFlNxQXR5v5vCoSck4/HvKSa45e/ttjluB2zLzoau E1vwgljyoRhaJtQHDf116Fvt/TILh134IVVL0L7O1X718u3E1/9SMKCt0Uz8ftbZqDfX hzU3pHyzlMD8i4yo0JsalvxD2yhAPqjIwClatu2X2ocJ4SS6UvNoZFnbVWv33Z3trCu4 4F5vt4JImhMS80hQ+SiyrbfQ8jNVWIxZC4G+wNjgbREnWZHSISgXjMfTeYSA6HHem+SA oZ6VyvQHhrZclpRNLlggp0bZBCB8ag9l2NNNDiLLv8lCBiipeQkzP057DtiDrRKiWgU6 968A== X-Gm-Message-State: AOAM530NNdf4X+LITesGuhdyVngqRfI1AdmqItX5W6M+9dgBoDCDwgnx iqQ20xOe5tz8V1X61SB8LwZR2QeNrqGpbQ== X-Google-Smtp-Source: ABdhPJz4qZkWCdLr/Qs1xXiVfcAgsKUUBvA5ZV9sF2c6oujQcw4k8XnyRRxe8SNFn6AEDXBcKIs+HA== X-Received: by 2002:a05:600c:4e8c:: with SMTP id f12mr4475362wmq.187.1622822578004; Fri, 04 Jun 2021 09:02:58 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 26/99] target/arm: move physical address translation to cpu-mmu Date: Fri, 4 Jun 2021 16:51:59 +0100 Message-Id: <20210604155312.15902-27-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana get_phys_addr is needed for KVM too, and in turn it requires the aa64_va_parameter* family of functions. Create cpu-mmu and cpu-mmu-sysemu to store these and other mmu-related functions. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-mmu.h | 119 ++ target/arm/cpu.h | 3 - target/arm/internals.h | 34 - target/arm/cpu-mmu-sysemu.c | 2307 ++++++++++++++++++++++++++ target/arm/cpu-mmu.c | 124 ++ target/arm/cpu.c | 1 + target/arm/tcg/helper.c | 2442 +--------------------------- target/arm/tcg/pauth_helper.c | 2 +- target/arm/tcg/sysemu/m_helper.c | 2 +- target/arm/tcg/sysemu/tlb_helper.c | 1 + target/arm/meson.build | 2 + 11 files changed, 2557 insertions(+), 2480 deletions(-) create mode 100644 target/arm/cpu-mmu.h create mode 100644 target/arm/cpu-mmu-sysemu.c create mode 100644 target/arm/cpu-mmu.c diff --git a/target/arm/cpu-mmu.h b/target/arm/cpu-mmu.h new file mode 100644 index 0000000000..01b060613a --- /dev/null +++ b/target/arm/cpu-mmu.h @@ -0,0 +1,119 @@ +/* + * QEMU ARM CPU address translation related code + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ +#ifndef ARM_CPU_MMU_H +#define ARM_CPU_MMU_H + +#include "cpu.h" +#include "internals.h" + +/* + * Parameters of a given virtual address, as extracted from the + * translation control register (TCR) for a given regime. + */ +typedef struct ARMVAParameters { + unsigned tsz : 8; + unsigned select : 1; + bool tbi : 1; + bool epd : 1; + bool hpd : 1; + bool using16k : 1; + bool using64k : 1; +} ARMVAParameters; + +/* cpu-mmu.c */ + +int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); +int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx); +int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx); +ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data); + +/* Return the SCTLR value which controls this address translation regime */ +static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; +} + +/* + * Convert a possible stage1+2 MMU index into the appropriate + * stage 1 MMU index + */ +static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_SE10_0: + return ARMMMUIdx_Stage1_SE0; + case ARMMMUIdx_SE10_1: + return ARMMMUIdx_Stage1_SE1; + case ARMMMUIdx_SE10_1_PAN: + return ARMMMUIdx_Stage1_SE1_PAN; + case ARMMMUIdx_E10_0: + return ARMMMUIdx_Stage1_E0; + case ARMMMUIdx_E10_1: + return ARMMMUIdx_Stage1_E1; + case ARMMMUIdx_E10_1_PAN: + return ARMMMUIdx_Stage1_E1_PAN; + default: + return mmu_idx; + } +} + +/* Return true if the translation regime is using LPAE format page tables = */ +static inline bool regime_using_lpae_format(CPUARMState *env, + ARMMMUIdx mmu_idx) +{ + int el =3D regime_el(env, mmu_idx); + if (el =3D=3D 2 || arm_el_is_aa64(env, el)) { + return true; + } + if (arm_feature(env, ARM_FEATURE_LPAE) + && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { + return true; + } + return false; +} + +#ifndef CONFIG_USER_ONLY + +/* cpu-mmu-sysemu.c */ + +void v8m_security_lookup(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + V8M_SAttributes *sattrs); + +bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *txattrs, + int *prot, bool *is_subpage, + ARMMMUFaultInfo *fi, uint32_t *mregion); + +bool get_phys_addr(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) + __attribute__((nonnull)); + +hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, + MemTxAttrs *attrs); + +#endif /* !CONFIG_USER_ONLY */ + +#endif /* ARM_CPU_MMU_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 04f8be35bf..f9ce70e607 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1033,9 +1033,6 @@ void arm_cpu_do_interrupt(CPUState *cpu); void arm_v7m_cpu_do_interrupt(CPUState *cpu); bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); =20 -hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); - int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/target/arm/internals.h b/target/arm/internals.h index 8809334228..c41f91f1c0 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1022,23 +1022,6 @@ static inline uint32_t aarch64_pstate_valid_mask(con= st ARMISARegisters *id) return valid; } =20 -/* - * Parameters of a given virtual address, as extracted from the - * translation control register (TCR) for a given regime. - */ -typedef struct ARMVAParameters { - unsigned tsz : 8; - unsigned select : 1; - bool tbi : 1; - bool epd : 1; - bool hpd : 1; - bool using16k : 1; - bool using64k : 1; -} ARMVAParameters; - -ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx, bool data); - static inline int exception_target_el(CPUARMState *env) { int target_el =3D MAX(1, arm_current_el(env)); @@ -1086,29 +1069,12 @@ typedef struct V8M_SAttributes { bool irvalid; } V8M_SAttributes; =20 -void v8m_security_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - V8M_SAttributes *sattrs); - -bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, bool *is_subpage, - ARMMMUFaultInfo *fi, uint32_t *mregion); - /* Cacheability and shareability attributes for a memory access */ typedef struct ARMCacheAttrs { unsigned int attrs:8; /* as in the MAIR register encoding */ unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PT= Es */ } ARMCacheAttrs; =20 -bool get_phys_addr(CPUARMState *env, target_ulong address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) - __attribute__((nonnull)); - void arm_log_exception(int idx); =20 #endif /* !CONFIG_USER_ONLY */ diff --git a/target/arm/cpu-mmu-sysemu.c b/target/arm/cpu-mmu-sysemu.c new file mode 100644 index 0000000000..9d4735a190 --- /dev/null +++ b/target/arm/cpu-mmu-sysemu.c @@ -0,0 +1,2307 @@ +/* + * QEMU ARM CPU address translation related code (sysemu-only) + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" + +#include "target/arm/idau.h" +#include "qemu/range.h" +#include "cpu-mmu.h" + +static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, + MMUAccessType access_type, ARMMMUIdx mmu_id= x, + bool s1_is_el0, + hwaddr *phys_ptr, MemTxAttrs *txattrs, int = *prot, + target_ulong *page_size_ptr, + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs) + __attribute__((nonnull)); + +/* Return true if the specified stage of address translation is disabled */ +static inline bool regime_translation_disabled(CPUARMState *env, + ARMMMUIdx mmu_idx) +{ + uint64_t hcr_el2; + + if (arm_feature(env, ARM_FEATURE_M)) { + switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & + (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK= )) { + case R_V7M_MPU_CTRL_ENABLE_MASK: + /* Enabled, but not for HardFault and NMI */ + return mmu_idx & ARM_MMU_IDX_M_NEGPRI; + case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: + /* Enabled for all cases */ + return false; + case 0: + default: + /* + * HFNMIENA set and ENABLE clear is UNPREDICTABLE, but + * we warned about that in armv7m_nvic.c when the guest set it. + */ + return true; + } + } + + hcr_el2 =3D arm_hcr_el2_eff(env); + + if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { + /* HCR.DC means HCR.VM behaves as 1 */ + return (hcr_el2 & (HCR_DC | HCR_VM)) =3D=3D 0; + } + + if (hcr_el2 & HCR_TGE) { + /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ + if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) =3D= =3D 1) { + return true; + } + } + + if ((hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { + /* HCR.DC means SCTLR_EL1.M behaves as 0 */ + return true; + } + + return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; +} + +static inline bool regime_translation_big_endian(CPUARMState *env, + ARMMMUIdx mmu_idx) +{ + return (regime_sctlr(env, mmu_idx) & SCTLR_EE) !=3D 0; +} + +/* Return the TTBR associated with this translation regime */ +static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, + int ttbrn) +{ + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + return env->cp15.vttbr_el2; + } + if (mmu_idx =3D=3D ARMMMUIdx_Stage2_S) { + return env->cp15.vsttbr_el2; + } + if (ttbrn =3D=3D 0) { + return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; + } else { + return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; + } +} + +static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_SE10_0: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_SE20_0: + case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_SE0: + case ARMMMUIdx_MUser: + case ARMMMUIdx_MSUser: + case ARMMMUIdx_MUserNegPri: + case ARMMMUIdx_MSUserNegPri: + return true; + default: + return false; + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: + g_assert_not_reached(); + } +} + +/* + * Translate section/page access permissions to page + * R/W protection flags + * + * @env: CPUARMState + * @mmu_idx: MMU index indicating required translation regime + * @ap: The 3-bit access permissions (AP[2:0]) + * @domain_prot: The 2-bit domain access permissions + */ +static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, + int ap, int domain_prot) +{ + bool is_user =3D regime_is_user(env, mmu_idx); + + if (domain_prot =3D=3D 3) { + return PAGE_READ | PAGE_WRITE; + } + + switch (ap) { + case 0: + if (arm_feature(env, ARM_FEATURE_V7)) { + return 0; + } + switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) { + case SCTLR_S: + return is_user ? 0 : PAGE_READ; + case SCTLR_R: + return PAGE_READ; + default: + return 0; + } + case 1: + return is_user ? 0 : PAGE_READ | PAGE_WRITE; + case 2: + if (is_user) { + return PAGE_READ; + } else { + return PAGE_READ | PAGE_WRITE; + } + case 3: + return PAGE_READ | PAGE_WRITE; + case 4: /* Reserved. */ + return 0; + case 5: + return is_user ? 0 : PAGE_READ; + case 6: + return PAGE_READ; + case 7: + if (!arm_feature(env, ARM_FEATURE_V6K)) { + return 0; + } + return PAGE_READ; + default: + g_assert_not_reached(); + } +} + +/* + * Translate section/page access permissions to page + * R/W protection flags. + * + * @ap: The 2-bit simple AP (AP[2:1]) + * @is_user: TRUE if accessing from PL0 + */ +static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user) +{ + switch (ap) { + case 0: + return is_user ? 0 : PAGE_READ | PAGE_WRITE; + case 1: + return PAGE_READ | PAGE_WRITE; + case 2: + return is_user ? 0 : PAGE_READ; + case 3: + return PAGE_READ; + default: + g_assert_not_reached(); + } +} + +static inline int +simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) +{ + return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); +} + +/* + * Translate S2 section/page access permissions to protection flags + * + * @env: CPUARMState + * @s2ap: The 2-bit stage2 access permissions (S2AP) + * @xn: XN (execute-never) bits + * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0 + */ +static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) +{ + int prot =3D 0; + + if (s2ap & 1) { + prot |=3D PAGE_READ; + } + if (s2ap & 2) { + prot |=3D PAGE_WRITE; + } + + if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) { + switch (xn) { + case 0: + prot |=3D PAGE_EXEC; + break; + case 1: + if (s1_is_el0) { + prot |=3D PAGE_EXEC; + } + break; + case 2: + break; + case 3: + if (!s1_is_el0) { + prot |=3D PAGE_EXEC; + } + break; + default: + g_assert_not_reached(); + } + } else { + if (!extract32(xn, 1, 1)) { + if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { + prot |=3D PAGE_EXEC; + } + } + } + return prot; +} + +/* + * Translate section/page access permissions to protection flags + * + * @env: CPUARMState + * @mmu_idx: MMU index indicating required translation regime + * @is_aa64: TRUE if AArch64 + * @ap: The 2-bit simple AP (AP[2:1]) + * @ns: NS (non-secure) bit + * @xn: XN (execute-never) bit + * @pxn: PXN (privileged execute-never) bit + */ +static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, + int ap, int ns, int xn, int pxn) +{ + bool is_user =3D regime_is_user(env, mmu_idx); + int prot_rw, user_rw; + bool have_wxn; + int wxn =3D 0; + + assert(mmu_idx !=3D ARMMMUIdx_Stage2); + assert(mmu_idx !=3D ARMMMUIdx_Stage2_S); + + user_rw =3D simple_ap_to_rw_prot_is_user(ap, true); + if (is_user) { + prot_rw =3D user_rw; + } else { + if (user_rw && regime_is_pan(env, mmu_idx)) { + /* PAN forbids data accesses but doesn't affect insn fetch */ + prot_rw =3D 0; + } else { + prot_rw =3D simple_ap_to_rw_prot_is_user(ap, false); + } + } + + if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { + return prot_rw; + } + + /* + * TODO have_wxn should be replaced with + * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) + * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE + * compatible processors have EL2, which is required for [U]WXN. + */ + have_wxn =3D arm_feature(env, ARM_FEATURE_LPAE); + + if (have_wxn) { + wxn =3D regime_sctlr(env, mmu_idx) & SCTLR_WXN; + } + + if (is_aa64) { + if (regime_has_2_ranges(mmu_idx) && !is_user) { + xn =3D pxn || (user_rw & PAGE_WRITE); + } + } else if (arm_feature(env, ARM_FEATURE_V7)) { + switch (regime_el(env, mmu_idx)) { + case 1: + case 3: + if (is_user) { + xn =3D xn || !(user_rw & PAGE_READ); + } else { + int uwxn =3D 0; + if (have_wxn) { + uwxn =3D regime_sctlr(env, mmu_idx) & SCTLR_UWXN; + } + xn =3D xn || !(prot_rw & PAGE_READ) || pxn || + (uwxn && (user_rw & PAGE_WRITE)); + } + break; + case 2: + break; + } + } else { + xn =3D wxn =3D 0; + } + + if (xn || (wxn && (prot_rw & PAGE_WRITE))) { + return prot_rw; + } + return prot_rw | PAGE_EXEC; +} + +static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, + uint32_t *table, uint32_t address) +{ + /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ + TCR *tcr =3D regime_tcr(env, mmu_idx); + + if (address & tcr->mask) { + if (tcr->raw_tcr & TTBCR_PD1) { + /* Translation table walk disabled for TTBR1 */ + return false; + } + *table =3D regime_ttbr(env, mmu_idx, 1) & 0xffffc000; + } else { + if (tcr->raw_tcr & TTBCR_PD0) { + /* Translation table walk disabled for TTBR0 */ + return false; + } + *table =3D regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; + } + *table |=3D (address >> 18) & 0x3ffc; + return true; +} + +/* Translate a S1 pagetable walk through S2 if needed. */ +static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, + hwaddr addr, bool *is_secure, + ARMMMUFaultInfo *fi) +{ + if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && + !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { + target_ulong s2size; + hwaddr s2pa; + int s2prot; + int ret; + ARMMMUIdx s2_mmu_idx =3D *is_secure ? ARMMMUIdx_Stage2_S + : ARMMMUIdx_Stage2; + ARMCacheAttrs cacheattrs =3D {}; + MemTxAttrs txattrs =3D {}; + + ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, f= alse, + &s2pa, &txattrs, &s2prot, &s2size, fi, + &cacheattrs); + if (ret) { + assert(fi->type !=3D ARMFault_None); + fi->s2addr =3D addr; + fi->stage2 =3D true; + fi->s1ptw =3D true; + fi->s1ns =3D !*is_secure; + return ~0; + } + if ((arm_hcr_el2_eff(env) & HCR_PTW) && + (cacheattrs.attrs & 0xf0) =3D=3D 0) { + /* + * PTW set and S1 walk touched S2 Device memory: + * generate Permission fault. + */ + fi->type =3D ARMFault_Permission; + fi->s2addr =3D addr; + fi->stage2 =3D true; + fi->s1ptw =3D true; + fi->s1ns =3D !*is_secure; + return ~0; + } + + if (arm_is_secure_below_el3(env)) { + /* Check if page table walk is to secure or non-secure PA spac= e. */ + if (*is_secure) { + *is_secure =3D !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); + } else { + *is_secure =3D !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); + } + } else { + assert(!*is_secure); + } + + addr =3D s2pa; + } + return addr; +} + +/* All loads done in the course of a page table walk go through here. */ +static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, + ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + MemTxAttrs attrs =3D {}; + MemTxResult result =3D MEMTX_OK; + AddressSpace *as; + uint32_t data; + + addr =3D S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); + attrs.secure =3D is_secure; + as =3D arm_addressspace(cs, attrs); + if (fi->s1ptw) { + return 0; + } + if (regime_translation_big_endian(env, mmu_idx)) { + data =3D address_space_ldl_be(as, addr, attrs, &result); + } else { + data =3D address_space_ldl_le(as, addr, attrs, &result); + } + if (result =3D=3D MEMTX_OK) { + return data; + } + fi->type =3D ARMFault_SyncExternalOnWalk; + fi->ea =3D arm_extabort_type(result); + return 0; +} + +static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, + ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + MemTxAttrs attrs =3D {}; + MemTxResult result =3D MEMTX_OK; + AddressSpace *as; + uint64_t data; + + addr =3D S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); + attrs.secure =3D is_secure; + as =3D arm_addressspace(cs, attrs); + if (fi->s1ptw) { + return 0; + } + if (regime_translation_big_endian(env, mmu_idx)) { + data =3D address_space_ldq_be(as, addr, attrs, &result); + } else { + data =3D address_space_ldq_le(as, addr, attrs, &result); + } + if (result =3D=3D MEMTX_OK) { + return data; + } + fi->type =3D ARMFault_SyncExternalOnWalk; + fi->ea =3D arm_extabort_type(result); + return 0; +} + +static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi) +{ + CPUState *cs =3D env_cpu(env); + int level =3D 1; + uint32_t table; + uint32_t desc; + int type; + int ap; + int domain =3D 0; + int domain_prot; + hwaddr phys_addr; + uint32_t dacr; + + /* Pagetable walk. */ + /* Lookup l1 descriptor. */ + if (!get_level1_table_address(env, mmu_idx, &table, address)) { + /* Section translation fault if page walk is disabled by PD0 or PD= 1 */ + fi->type =3D ARMFault_Translation; + goto do_fault; + } + desc =3D arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + mmu_idx, fi); + if (fi->type !=3D ARMFault_None) { + goto do_fault; + } + type =3D (desc & 3); + domain =3D (desc >> 5) & 0x0f; + if (regime_el(env, mmu_idx) =3D=3D 1) { + dacr =3D env->cp15.dacr_ns; + } else { + dacr =3D env->cp15.dacr_s; + } + domain_prot =3D (dacr >> (domain * 2)) & 3; + if (type =3D=3D 0) { + /* Section translation fault. */ + fi->type =3D ARMFault_Translation; + goto do_fault; + } + if (type !=3D 2) { + level =3D 2; + } + if (domain_prot =3D=3D 0 || domain_prot =3D=3D 2) { + fi->type =3D ARMFault_Domain; + goto do_fault; + } + if (type =3D=3D 2) { + /* 1Mb section. */ + phys_addr =3D (desc & 0xfff00000) | (address & 0x000fffff); + ap =3D (desc >> 10) & 3; + *page_size =3D 1024 * 1024; + } else { + /* Lookup l2 entry. */ + if (type =3D=3D 1) { + /* Coarse pagetable. */ + table =3D (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); + } else { + /* Fine pagetable. */ + table =3D (desc & 0xfffff000) | ((address >> 8) & 0xffc); + } + desc =3D arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + mmu_idx, fi); + if (fi->type !=3D ARMFault_None) { + goto do_fault; + } + switch (desc & 3) { + case 0: /* Page translation fault. */ + fi->type =3D ARMFault_Translation; + goto do_fault; + case 1: /* 64k page. */ + phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); + ap =3D (desc >> (4 + ((address >> 13) & 6))) & 3; + *page_size =3D 0x10000; + break; + case 2: /* 4k page. */ + phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); + ap =3D (desc >> (4 + ((address >> 9) & 6))) & 3; + *page_size =3D 0x1000; + break; + case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ + if (type =3D=3D 1) { + /* ARMv6/XScale extended small page format */ + if (arm_feature(env, ARM_FEATURE_XSCALE) + || arm_feature(env, ARM_FEATURE_V6)) { + phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); + *page_size =3D 0x1000; + } else { + /* + * UNPREDICTABLE in ARMv5; we choose to take a + * page translation fault. + */ + fi->type =3D ARMFault_Translation; + goto do_fault; + } + } else { + phys_addr =3D (desc & 0xfffffc00) | (address & 0x3ff); + *page_size =3D 0x400; + } + ap =3D (desc >> 4) & 3; + break; + default: + /* Never happens, but compiler isn't smart enough to tell. */ + abort(); + } + } + *prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + *prot |=3D *prot ? PAGE_EXEC : 0; + if (!(*prot & (1 << access_type))) { + /* Access permission fault. */ + fi->type =3D ARMFault_Permission; + goto do_fault; + } + *phys_ptr =3D phys_addr; + return false; +do_fault: + fi->domain =3D domain; + fi->level =3D level; + return true; +} + +static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *pro= t, + target_ulong *page_size, ARMMMUFaultInfo *fi) +{ + CPUState *cs =3D env_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); + int level =3D 1; + uint32_t table; + uint32_t desc; + uint32_t xn; + uint32_t pxn =3D 0; + int type; + int ap; + int domain =3D 0; + int domain_prot; + hwaddr phys_addr; + uint32_t dacr; + bool ns; + + /* Pagetable walk. */ + /* Lookup l1 descriptor. */ + if (!get_level1_table_address(env, mmu_idx, &table, address)) { + /* Section translation fault if page walk is disabled by PD0 or PD= 1 */ + fi->type =3D ARMFault_Translation; + goto do_fault; + } + desc =3D arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + mmu_idx, fi); + if (fi->type !=3D ARMFault_None) { + goto do_fault; + } + type =3D (desc & 3); + if (type =3D=3D 0 || (type =3D=3D 3 && !cpu_isar_feature(aa32_pxn, cpu= ))) { + /* + * Section translation fault, or attempt to use the encoding + * which is Reserved on implementations without PXN. + */ + fi->type =3D ARMFault_Translation; + goto do_fault; + } + if ((type =3D=3D 1) || !(desc & (1 << 18))) { + /* Page or Section. */ + domain =3D (desc >> 5) & 0x0f; + } + if (regime_el(env, mmu_idx) =3D=3D 1) { + dacr =3D env->cp15.dacr_ns; + } else { + dacr =3D env->cp15.dacr_s; + } + if (type =3D=3D 1) { + level =3D 2; + } + domain_prot =3D (dacr >> (domain * 2)) & 3; + if (domain_prot =3D=3D 0 || domain_prot =3D=3D 2) { + /* Section or Page domain fault */ + fi->type =3D ARMFault_Domain; + goto do_fault; + } + if (type !=3D 1) { + if (desc & (1 << 18)) { + /* Supersection. */ + phys_addr =3D (desc & 0xff000000) | (address & 0x00ffffff); + phys_addr |=3D (uint64_t)extract32(desc, 20, 4) << 32; + phys_addr |=3D (uint64_t)extract32(desc, 5, 4) << 36; + *page_size =3D 0x1000000; + } else { + /* Section. */ + phys_addr =3D (desc & 0xfff00000) | (address & 0x000fffff); + *page_size =3D 0x100000; + } + ap =3D ((desc >> 10) & 3) | ((desc >> 13) & 4); + xn =3D desc & (1 << 4); + pxn =3D desc & 1; + ns =3D extract32(desc, 19, 1); + } else { + if (cpu_isar_feature(aa32_pxn, cpu)) { + pxn =3D (desc >> 2) & 1; + } + ns =3D extract32(desc, 3, 1); + /* Lookup l2 entry. */ + table =3D (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); + desc =3D arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + mmu_idx, fi); + if (fi->type !=3D ARMFault_None) { + goto do_fault; + } + ap =3D ((desc >> 4) & 3) | ((desc >> 7) & 4); + switch (desc & 3) { + case 0: /* Page translation fault. */ + fi->type =3D ARMFault_Translation; + goto do_fault; + case 1: /* 64k page. */ + phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); + xn =3D desc & (1 << 15); + *page_size =3D 0x10000; + break; + case 2: case 3: /* 4k page. */ + phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); + xn =3D desc & 1; + *page_size =3D 0x1000; + break; + default: + /* Never happens, but compiler isn't smart enough to tell. */ + abort(); + } + } + if (domain_prot =3D=3D 3) { + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + } else { + if (pxn && !regime_is_user(env, mmu_idx)) { + xn =3D 1; + } + if (xn && access_type =3D=3D MMU_INST_FETCH) { + fi->type =3D ARMFault_Permission; + goto do_fault; + } + + if (arm_feature(env, ARM_FEATURE_V6K) && + (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { + /* The simplified model uses AP[0] as an access control bit. = */ + if ((ap & 1) =3D=3D 0) { + /* Access flag fault. */ + fi->type =3D ARMFault_AccessFlag; + goto do_fault; + } + *prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); + } else { + *prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + } + if (*prot && !xn) { + *prot |=3D PAGE_EXEC; + } + if (!(*prot & (1 << access_type))) { + /* Access permission fault. */ + fi->type =3D ARMFault_Permission; + goto do_fault; + } + } + if (ns) { + /* + * The NS bit will (as required by the architecture) have no effec= t if + * the CPU doesn't support TZ or this is a non-secure translation + * regime, because the attribute will already be non-secure. + */ + attrs->secure =3D false; + } + *phys_ptr =3D phys_addr; + return false; +do_fault: + fi->domain =3D domain; + fi->level =3D level; + return true; +} + +/* + * check_s2_mmu_setup + * @cpu: ARMCPU + * @is_aa64: True if the translation regime is in AArch64 state + * @startlevel: Suggested starting level + * @inputsize: Bitsize of IPAs + * @stride: Page-table stride (See the ARM ARM) + * + * Returns true if the suggested S2 translation parameters are OK and + * false otherwise. + */ +static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, + int inputsize, int stride) +{ + const int grainsize =3D stride + 3; + int startsizecheck; + + /* Negative levels are never allowed. */ + if (level < 0) { + return false; + } + + startsizecheck =3D inputsize - ((3 - level) * stride + grainsize); + if (startsizecheck < 1 || startsizecheck > stride + 4) { + return false; + } + + if (is_aa64) { + CPUARMState *env =3D &cpu->env; + unsigned int pamax =3D arm_pamax(cpu); + + switch (stride) { + case 13: /* 64KB Pages. */ + if (level =3D=3D 0 || (level =3D=3D 1 && pamax <=3D 42)) { + return false; + } + break; + case 11: /* 16KB Pages. */ + if (level =3D=3D 0 || (level =3D=3D 1 && pamax <=3D 40)) { + return false; + } + break; + case 9: /* 4KB Pages. */ + if (level =3D=3D 0 && pamax <=3D 42) { + return false; + } + break; + default: + g_assert_not_reached(); + } + + /* Inputsize checks. */ + if (inputsize > pamax && + (arm_el_is_aa64(env, 1) || inputsize > 40)) { + /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. = */ + return false; + } + } else { + /* AArch32 only supports 4KB pages. Assert on that. */ + assert(stride =3D=3D 9); + + if (level =3D=3D 0) { + return false; + } + } + return true; +} + +/* + * Translate from the 4-bit stage 2 representation of + * memory attributes (without cache-allocation hints) to + * the 8-bit representation of the stage 1 MAIR registers + * (which includes allocation hints). + * + * ref: shared/translation/attrs/S2AttrDecode() + * .../S2ConvertAttrsHints() + */ +static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) +{ + uint8_t hiattr =3D extract32(s2attrs, 2, 2); + uint8_t loattr =3D extract32(s2attrs, 0, 2); + uint8_t hihint =3D 0, lohint =3D 0; + + if (hiattr !=3D 0) { /* normal memory */ + if (arm_hcr_el2_eff(env) & HCR_CD) { /* cache disabled */ + hiattr =3D loattr =3D 1; /* non-cacheable */ + } else { + if (hiattr !=3D 1) { /* Write-through or write-back */ + hihint =3D 3; /* RW allocate */ + } + if (loattr !=3D 1) { /* Write-through or write-back */ + lohint =3D 3; /* RW allocate */ + } + } + } + + return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; +} + +static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, + ARMMMUIdx mmu_idx) +{ + uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; + uint32_t el =3D regime_el(env, mmu_idx); + int select, tsz; + bool epd, hpd; + + assert(mmu_idx !=3D ARMMMUIdx_Stage2_S); + + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + /* VTCR */ + bool sext =3D extract32(tcr, 4, 1); + bool sign =3D extract32(tcr, 3, 1); + + /* + * If the sign-extend bit is not the same as t0sz[3], the result + * is unpredictable. Flag this as a guest error. + */ + if (sign !=3D sext) { + qemu_log_mask(LOG_GUEST_ERROR, + "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); + } + tsz =3D sextract32(tcr, 0, 4) + 8; + select =3D 0; + hpd =3D false; + epd =3D false; + } else if (el =3D=3D 2) { + /* HTCR */ + tsz =3D extract32(tcr, 0, 3); + select =3D 0; + hpd =3D extract64(tcr, 24, 1); + epd =3D false; + } else { + int t0sz =3D extract32(tcr, 0, 3); + int t1sz =3D extract32(tcr, 16, 3); + + if (t1sz =3D=3D 0) { + select =3D va > (0xffffffffu >> t0sz); + } else { + /* Note that we will detect errors later. */ + select =3D va >=3D ~(0xffffffffu >> t1sz); + } + if (!select) { + tsz =3D t0sz; + epd =3D extract32(tcr, 7, 1); + hpd =3D extract64(tcr, 41, 1); + } else { + tsz =3D t1sz; + epd =3D extract32(tcr, 23, 1); + hpd =3D extract64(tcr, 42, 1); + } + /* For aarch32, hpd0 is not enabled without t2e as well. */ + hpd &=3D extract32(tcr, 6, 1); + } + + return (ARMVAParameters) { + .tsz =3D tsz, + .select =3D select, + .epd =3D epd, + .hpd =3D hpd, + }; +} + +/** + * get_phys_addr_lpae: perform one stage of page table walk, LPAE format + * + * Returns false if the translation was successful. Otherwise, phys_ptr, a= ttrs, + * prot and page_size may not be filled in, and the populated fsr value pr= ovides + * information on why the translation aborted, in the format of a long-for= mat + * DFSR/IFSR fault register, with the following caveats: + * * the WnR bit is never set (the caller must do this). + * + * @env: CPUARMState + * @address: virtual address to get physical address for + * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH + * @mmu_idx: MMU index indicating required translation regime + * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page = table + * walk), must be true if this is stage 2 of a stage 1+2 walk = for an + * EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ig= nored. + * @phys_ptr: set to the physical address corresponding to the virtual add= ress + * @attrs: set to the memory transaction attributes to use + * @prot: set to the permissions for the page containing phys_ptr + * @page_size_ptr: set to the size of the page containing phys_ptr + * @fi: set to fault info if the translation fails + * @cacheattrs: (if non-NULL) set to the cacheability/shareability attribu= tes + */ +static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, + MMUAccessType access_type, ARMMMUIdx mmu_id= x, + bool s1_is_el0, + hwaddr *phys_ptr, MemTxAttrs *txattrs, int = *prot, + target_ulong *page_size_ptr, + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs) +{ + ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D CPU(cpu); + /* Read an LPAE long-descriptor translation table. */ + ARMFaultType fault_type =3D ARMFault_Translation; + uint32_t level; + ARMVAParameters param; + uint64_t ttbr; + hwaddr descaddr, indexmask, indexmask_grainsize; + uint32_t tableattrs; + target_ulong page_size; + uint32_t attrs; + int32_t stride; + int addrsize, inputsize; + TCR *tcr =3D regime_tcr(env, mmu_idx); + int ap, ns, xn, pxn; + uint32_t el =3D regime_el(env, mmu_idx); + uint64_t descaddrmask; + bool aarch64 =3D arm_el_is_aa64(env, el); + bool guarded =3D false; + + /* TODO: This code does not support shareability levels. */ + if (aarch64) { + param =3D aa64_va_parameters(env, address, mmu_idx, + access_type !=3D MMU_INST_FETCH); + level =3D 0; + addrsize =3D 64 - 8 * param.tbi; + inputsize =3D 64 - param.tsz; + } else { + param =3D aa32_va_parameters(env, address, mmu_idx); + level =3D 1; + addrsize =3D (mmu_idx =3D=3D ARMMMUIdx_Stage2 ? 40 : 32); + inputsize =3D addrsize - param.tsz; + } + + /* + * We determined the region when collecting the parameters, but we + * have not yet validated that the address is valid for the region. + * Extract the top bits and verify that they all match select. + * + * For aa32, if inputsize =3D=3D addrsize, then we have selected the + * region by exclusion in aa32_va_parameters and there is no more + * validation to do here. + */ + if (inputsize < addrsize) { + target_ulong top_bits =3D sextract64(address, inputsize, + addrsize - inputsize); + if (-top_bits !=3D param.select) { + /* The gap between the two regions is a Translation fault */ + fault_type =3D ARMFault_Translation; + goto do_fault; + } + } + + if (param.using64k) { + stride =3D 13; + } else if (param.using16k) { + stride =3D 11; + } else { + stride =3D 9; + } + + /* + * Note that QEMU ignores shareability and cacheability attributes, + * so we don't need to do anything with the SH, ORGN, IRGN fields + * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the + * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently + * implement any ASID-like capability so we can ignore it (instead + * we will always flush the TLB any time the ASID is changed). + */ + ttbr =3D regime_ttbr(env, mmu_idx, param.select); + + /* + * Here we should have set up all the parameters for the translation: + * inputsize, ttbr, epd, stride, tbi + */ + + if (param.epd) { + /* + * Translation table walk disabled =3D> Translation fault on TLB m= iss + * Note: This is always 0 on 64-bit EL2 and EL3. + */ + goto do_fault; + } + + if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2_S) { + /* + * The starting level depends on the virtual address size (which c= an + * be up to 48 bits) and the translation granule size. It indicates + * the number of strides (stride bits at a time) needed to + * consume the bits of the input address. In the pseudocode this i= s: + * level =3D 4 - RoundUp((inputsize - grainsize) / stride) + * where their 'inputsize' is our 'inputsize', 'grainsize' is + * our 'stride + 3' and 'stride' is our 'stride'. + * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifyin= g: + * =3D 4 - (inputsize - stride - 3 + stride - 1) / stride + * =3D 4 - (inputsize - 4) / stride; + */ + level =3D 4 - (inputsize - 4) / stride; + } else { + /* + * For stage 2 translations the starting level is specified by the + * VTCR_EL2.SL0 field (whose interpretation depends on the page si= ze) + */ + uint32_t sl0 =3D extract32(tcr->raw_tcr, 6, 2); + uint32_t startlevel; + bool ok; + + if (!aarch64 || stride =3D=3D 9) { + /* AArch32 or 4KB pages */ + startlevel =3D 2 - sl0; + + if (cpu_isar_feature(aa64_st, cpu)) { + startlevel &=3D 3; + } + } else { + /* 16KB or 64KB pages */ + startlevel =3D 3 - sl0; + } + + /* Check that the starting level is valid. */ + ok =3D check_s2_mmu_setup(cpu, aarch64, startlevel, + inputsize, stride); + if (!ok) { + fault_type =3D ARMFault_Translation; + goto do_fault; + } + level =3D startlevel; + } + + indexmask_grainsize =3D (1ULL << (stride + 3)) - 1; + indexmask =3D (1ULL << (inputsize - (stride * (4 - level)))) - 1; + + /* Now we can extract the actual base address from the TTBR */ + descaddr =3D extract64(ttbr, 0, 48); + /* + * We rely on this masking to clear the RES0 bits at the bottom of the= TTBR + * and also to mask out CnP (bit 0) which could validly be non-zero. + */ + descaddr &=3D ~indexmask; + + /* + * The address field in the descriptor goes up to bit 39 for ARMv7 + * but up to bit 47 for ARMv8, but we use the descaddrmask + * up to bit 39 for AArch32, because we don't need other bits in that = case + * to construct next descriptor address (anyway they should be all zer= oes). + */ + descaddrmask =3D ((1ull << (aarch64 ? 48 : 40)) - 1) & + ~indexmask_grainsize; + + /* + * Secure accesses start with the page table in secure memory and + * can be downgraded to non-secure at any step. Non-secure accesses + * remain non-secure. We implement this by just ORing in the NSTable/NS + * bits at each step. + */ + tableattrs =3D regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); + for (;;) { + uint64_t descriptor; + bool nstable; + + descaddr |=3D (address >> (stride * (4 - level))) & indexmask; + descaddr &=3D ~7ULL; + nstable =3D extract32(tableattrs, 4, 1); + descriptor =3D arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi); + if (fi->type !=3D ARMFault_None) { + goto do_fault; + } + + if (!(descriptor & 1) || + (!(descriptor & 2) && (level =3D=3D 3))) { + /* Invalid, or the Reserved level 3 encoding */ + goto do_fault; + } + descaddr =3D descriptor & descaddrmask; + + if ((descriptor & 2) && (level < 3)) { + /* + * Table entry. The top five bits are attributes which may + * propagate down through lower levels of the table (and + * which are all arranged so that 0 means "no effect", so + * we can gather them up by ORing in the bits at each level). + */ + tableattrs |=3D extract64(descriptor, 59, 5); + level++; + indexmask =3D indexmask_grainsize; + continue; + } + /* + * Block entry at level 1 or 2, or page entry at level 3. + * These are basically the same thing, although the number + * of bits we pull in from the vaddr varies. + */ + page_size =3D (1ULL << ((stride * (4 - level)) + 3)); + descaddr |=3D (address & (page_size - 1)); + /* Extract attributes from the descriptor */ + attrs =3D extract64(descriptor, 2, 10) + | (extract64(descriptor, 52, 12) << 10); + + if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_St= age2_S) { + /* Stage 2 table descriptors do not include any attribute fiel= ds */ + break; + } + /* Merge in attributes from table descriptors */ + attrs |=3D nstable << 3; /* NS */ + guarded =3D extract64(descriptor, 50, 1); /* GP */ + if (param.hpd) { + /* HPD disables all the table attributes except NSTable. */ + break; + } + attrs |=3D extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ + /* + * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] =3D= =3D 1 + * means "force PL1 access only", which means forcing AP[1] to 0. + */ + attrs &=3D ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] =3D> = AP[1] */ + attrs |=3D extract32(tableattrs, 3, 1) << 5; /* APT[1] =3D> A= P[2] */ + break; + } + /* + * Here descaddr is the final physical address, + * and attributes are all in attrs. + */ + fault_type =3D ARMFault_AccessFlag; + if ((attrs & (1 << 8)) =3D=3D 0) { + /* Access flag */ + goto do_fault; + } + + ap =3D extract32(attrs, 4, 2); + + if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { + ns =3D mmu_idx =3D=3D ARMMMUIdx_Stage2; + xn =3D extract32(attrs, 11, 2); + *prot =3D get_S2prot(env, ap, xn, s1_is_el0); + } else { + ns =3D extract32(attrs, 3, 1); + xn =3D extract32(attrs, 12, 1); + pxn =3D extract32(attrs, 11, 1); + *prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); + } + + fault_type =3D ARMFault_Permission; + if (!(*prot & (1 << access_type))) { + goto do_fault; + } + + if (ns) { + /* + * The NS bit will (as required by the architecture) have no effec= t if + * the CPU doesn't support TZ or this is a non-secure translation + * regime, because the attribute will already be non-secure. + */ + txattrs->secure =3D false; + } + /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB.= */ + if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { + arm_tlb_bti_gp(txattrs) =3D true; + } + + if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { + cacheattrs->attrs =3D convert_stage2_attrs(env, extract32(attrs, 0= , 4)); + } else { + /* Index into MAIR registers for cache attributes */ + uint8_t attrindx =3D extract32(attrs, 0, 3); + uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; + assert(attrindx <=3D 7); + cacheattrs->attrs =3D extract64(mair, attrindx * 8, 8); + } + cacheattrs->shareability =3D extract32(attrs, 6, 2); + + *phys_ptr =3D descaddr; + *page_size_ptr =3D page_size; + return false; + +do_fault: + fi->type =3D fault_type; + fi->level =3D level; + /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ + fi->stage2 =3D fi->s1ptw || (mmu_idx =3D=3D ARMMMUIdx_Stage2 || + mmu_idx =3D=3D ARMMMUIdx_Stage2_S); + fi->s1ns =3D mmu_idx =3D=3D ARMMMUIdx_Stage2; + return true; +} + +static inline void get_phys_addr_pmsav7_default(CPUARMState *env, + ARMMMUIdx mmu_idx, + int32_t address, int *prot) +{ + if (!arm_feature(env, ARM_FEATURE_M)) { + *prot =3D PAGE_READ | PAGE_WRITE; + switch (address) { + case 0xF0000000 ... 0xFFFFFFFF: + if (regime_sctlr(env, mmu_idx) & SCTLR_V) { + /* hivecs execing is ok */ + *prot |=3D PAGE_EXEC; + } + break; + case 0x00000000 ... 0x7FFFFFFF: + *prot |=3D PAGE_EXEC; + break; + } + } else { + /* + * Default system address map for M profile cores. + * The architecture specifies which regions are execute-never; + * at the MPU level no other checks are defined. + */ + switch (address) { + case 0x00000000 ... 0x1fffffff: /* ROM */ + case 0x20000000 ... 0x3fffffff: /* SRAM */ + case 0x60000000 ... 0x7fffffff: /* RAM */ + case 0x80000000 ... 0x9fffffff: /* RAM */ + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + break; + case 0x40000000 ... 0x5fffffff: /* Peripheral */ + case 0xa0000000 ... 0xbfffffff: /* Device */ + case 0xc0000000 ... 0xdfffffff: /* Device */ + case 0xe0000000 ... 0xffffffff: /* System */ + *prot =3D PAGE_READ | PAGE_WRITE; + break; + default: + g_assert_not_reached(); + } + } +} + +static bool pmsav7_use_background_region(ARMCPU *cpu, + ARMMMUIdx mmu_idx, bool is_user) +{ + /* + * Return true if we should use the default memory map as a + * "background" region if there are no hits against any MPU regions. + */ + CPUARMState *env =3D &cpu->env; + + if (is_user) { + return false; + } + + if (arm_feature(env, ARM_FEATURE_M)) { + return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] + & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; + } else { + return regime_sctlr(env, mmu_idx) & SCTLR_BR; + } +} + +static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address) +{ + /* True if address is in the M profile PPB region 0xe0000000 - 0xe00ff= fff */ + return arm_feature(env, ARM_FEATURE_M) && + extract32(address, 20, 12) =3D=3D 0xe00; +} + +static inline bool m_is_system_region(CPUARMState *env, uint32_t address) +{ + /* + * True if address is in the M profile system region + * 0xe0000000 - 0xffffffff + */ + return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) = =3D=3D 0x7; +} + +static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_= idx, + hwaddr *phys_ptr, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi) +{ + ARMCPU *cpu =3D env_archcpu(env); + int n; + bool is_user =3D regime_is_user(env, mmu_idx); + + *phys_ptr =3D address; + *page_size =3D TARGET_PAGE_SIZE; + *prot =3D 0; + + if (regime_translation_disabled(env, mmu_idx) || + m_is_ppb_region(env, address)) { + /* + * MPU disabled or M profile PPB access: use default memory map. + * The other case which uses the default memory map in the + * v7M ARM ARM pseudocode is exception vector reads from the vector + * table. In QEMU those accesses are done in arm_v7m_load_vector(), + * which always does a direct read using address_space_ldl(), rath= er + * than going via this function, so we don't need to check that he= re. + */ + get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + } else { /* MPU enabled */ + for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { + /* region search */ + uint32_t base =3D env->pmsav7.drbar[n]; + uint32_t rsize =3D extract32(env->pmsav7.drsr[n], 1, 5); + uint32_t rmask; + bool srdis =3D false; + + if (!(env->pmsav7.drsr[n] & 0x1)) { + continue; + } + + if (!rsize) { + qemu_log_mask(LOG_GUEST_ERROR, + "DRSR[%d]: Rsize field cannot be 0\n", n); + continue; + } + rsize++; + rmask =3D (1ull << rsize) - 1; + + if (base & rmask) { + qemu_log_mask(LOG_GUEST_ERROR, + "DRBAR[%d]: 0x%" PRIx32 " misaligned " + "to DRSR region size, mask =3D 0x%" PRIx32 "= \n", + n, base, rmask); + continue; + } + + if (address < base || address > base + rmask) { + /* + * Address not in this region. We must check whether the + * region covers addresses in the same page as our address. + * In that case we must not report a size that covers the + * whole page for a subsequent hit against a different MPU + * region or the background region, because it would resul= t in + * incorrect TLB hits for subsequent accesses to addresses= that + * are in this MPU region. + */ + if (ranges_overlap(base, rmask, + address & TARGET_PAGE_MASK, + TARGET_PAGE_SIZE)) { + *page_size =3D 1; + } + continue; + } + + /* Region matched */ + + if (rsize >=3D 8) { /* no subregions for regions < 256 bytes */ + int i, snd; + uint32_t srdis_mask; + + rsize -=3D 3; /* sub region size (power of 2) */ + snd =3D ((address - base) >> rsize) & 0x7; + srdis =3D extract32(env->pmsav7.drsr[n], snd + 8, 1); + + srdis_mask =3D srdis ? 0x3 : 0x0; + for (i =3D 2; i <=3D 8 && rsize < TARGET_PAGE_BITS; i *=3D= 2) { + /* + * This will check in groups of 2, 4 and then 8, wheth= er + * the subregion bits are consistent. rsize is increme= nted + * back up to give the region size, considering consis= tent + * adjacent subregions as one region. Stop testing if = rsize + * is already big enough for an entire QEMU page. + */ + int snd_rounded =3D snd & ~(i - 1); + uint32_t srdis_multi =3D extract32(env->pmsav7.drsr[n], + snd_rounded + 8, i); + if (srdis_mask ^ srdis_multi) { + break; + } + srdis_mask =3D (srdis_mask << i) | srdis_mask; + rsize++; + } + } + if (srdis) { + continue; + } + if (rsize < TARGET_PAGE_BITS) { + *page_size =3D 1 << rsize; + } + break; + } + + if (n =3D=3D -1) { /* no hits */ + if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { + /* background fault */ + fi->type =3D ARMFault_Background; + return true; + } + get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + } else { /* a MPU hit! */ + uint32_t ap =3D extract32(env->pmsav7.dracr[n], 8, 3); + uint32_t xn =3D extract32(env->pmsav7.dracr[n], 12, 1); + + if (m_is_system_region(env, address)) { + /* System space is always execute never */ + xn =3D 1; + } + + if (is_user) { /* User mode AP bit decoding */ + switch (ap) { + case 0: + case 1: + case 5: + break; /* no access */ + case 3: + *prot |=3D PAGE_WRITE; + /* fall through */ + case 2: + case 6: + *prot |=3D PAGE_READ | PAGE_EXEC; + break; + case 7: + /* for v7M, same as 6; for R profile a reserved value = */ + if (arm_feature(env, ARM_FEATURE_M)) { + *prot |=3D PAGE_READ | PAGE_EXEC; + break; + } + /* fall through */ + default: + qemu_log_mask(LOG_GUEST_ERROR, + "DRACR[%d]: Bad value for AP bits: 0x%" + PRIx32 "\n", n, ap); + } + } else { /* Priv. mode AP bits decoding */ + switch (ap) { + case 0: + break; /* no access */ + case 1: + case 2: + case 3: + *prot |=3D PAGE_WRITE; + /* fall through */ + case 5: + case 6: + *prot |=3D PAGE_READ | PAGE_EXEC; + break; + case 7: + /* for v7M, same as 6; for R profile a reserved value = */ + if (arm_feature(env, ARM_FEATURE_M)) { + *prot |=3D PAGE_READ | PAGE_EXEC; + break; + } + /* fall through */ + default: + qemu_log_mask(LOG_GUEST_ERROR, + "DRACR[%d]: Bad value for AP bits: 0x%" + PRIx32 "\n", n, ap); + } + } + + /* execute never */ + if (xn) { + *prot &=3D ~PAGE_EXEC; + } + } + } + + fi->type =3D ARMFault_Permission; + fi->level =3D 1; + return !(*prot & (1 << access_type)); +} + +static bool v8m_is_sau_exempt(CPUARMState *env, + uint32_t address, MMUAccessType access_type) +{ + /* + * The architecture specifies that certain address ranges are + * exempt from v8M SAU/IDAU checks. + */ + return + (access_type =3D=3D MMU_INST_FETCH && m_is_system_region(env, addr= ess)) || + (address >=3D 0xe0000000 && address <=3D 0xe0002fff) || + (address >=3D 0xe000e000 && address <=3D 0xe000efff) || + (address >=3D 0xe002e000 && address <=3D 0xe002efff) || + (address >=3D 0xe0040000 && address <=3D 0xe0041fff) || + (address >=3D 0xe00ff000 && address <=3D 0xe00fffff); +} + +void v8m_security_lookup(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_i= dx, + V8M_SAttributes *sattrs) +{ + /* + * Look up the security attributes for this address. Compare the + * pseudocode SecurityCheck() function. + * We assume the caller has zero-initialized *sattrs. + */ + ARMCPU *cpu =3D env_archcpu(env); + int r; + bool idau_exempt =3D false, idau_ns =3D true, idau_nsc =3D true; + int idau_region =3D IREGION_NOTVALID; + uint32_t addr_page_base =3D address & TARGET_PAGE_MASK; + uint32_t addr_page_limit =3D addr_page_base + (TARGET_PAGE_SIZE - 1); + + if (cpu->idau) { + IDAUInterfaceClass *iic =3D IDAU_INTERFACE_GET_CLASS(cpu->idau); + IDAUInterface *ii =3D IDAU_INTERFACE(cpu->idau); + + iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns, + &idau_nsc); + } + + if (access_type =3D=3D MMU_INST_FETCH && extract32(address, 28, 4) =3D= =3D 0xf) { + /* 0xf0000000..0xffffffff is always S for insn fetches */ + return; + } + + if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) { + sattrs->ns =3D !regime_is_secure(env, mmu_idx); + return; + } + + if (idau_region !=3D IREGION_NOTVALID) { + sattrs->irvalid =3D true; + sattrs->iregion =3D idau_region; + } + + switch (env->sau.ctrl & 3) { + case 0: /* SAU.ENABLE =3D=3D 0, SAU.ALLNS =3D=3D 0 */ + break; + case 2: /* SAU.ENABLE =3D=3D 0, SAU.ALLNS =3D=3D 1 */ + sattrs->ns =3D true; + break; + default: /* SAU.ENABLE =3D=3D 1 */ + for (r =3D 0; r < cpu->sau_sregion; r++) { + if (env->sau.rlar[r] & 1) { + uint32_t base =3D env->sau.rbar[r] & ~0x1f; + uint32_t limit =3D env->sau.rlar[r] | 0x1f; + + if (base <=3D address && limit >=3D address) { + if (base > addr_page_base || limit < addr_page_limit) { + sattrs->subpage =3D true; + } + if (sattrs->srvalid) { + /* + * If we hit in more than one region then we must = report + * as Secure, not NS-Callable, with no valid region + * number info. + */ + sattrs->ns =3D false; + sattrs->nsc =3D false; + sattrs->sregion =3D 0; + sattrs->srvalid =3D false; + break; + } else { + if (env->sau.rlar[r] & 2) { + sattrs->nsc =3D true; + } else { + sattrs->ns =3D true; + } + sattrs->srvalid =3D true; + sattrs->sregion =3D r; + } + } else { + /* + * Address not in this region. We must check whether t= he + * region covers addresses in the same page as our add= ress. + * In that case we must not report a size that covers = the + * whole page for a subsequent hit against a different= MPU + * region or the background region, because it would r= esult + * in incorrect TLB hits for subsequent accesses to + * addresses that are in this MPU region. + */ + if (limit >=3D base && + ranges_overlap(base, limit - base + 1, + addr_page_base, + TARGET_PAGE_SIZE)) { + sattrs->subpage =3D true; + } + } + } + } + break; + } + + /* + * The IDAU will override the SAU lookup results if it specifies + * higher security than the SAU does. + */ + if (!idau_ns) { + if (sattrs->ns || (!idau_nsc && sattrs->nsc)) { + sattrs->ns =3D false; + sattrs->nsc =3D idau_nsc; + } + } +} + +bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *txattrs, + int *prot, bool *is_subpage, + ARMMMUFaultInfo *fi, uint32_t *mregion) +{ + /* + * Perform a PMSAv8 MPU lookup (without also doing the SAU check + * that a full phys-to-virt translation does). + * mregion is (if not NULL) set to the region number which matched, + * or -1 if no region number is returned (MPU off, address did not + * hit a region, address hit in multiple regions). + * We set is_subpage to true if the region hit doesn't cover the + * entire TARGET_PAGE the address is within. + */ + ARMCPU *cpu =3D env_archcpu(env); + bool is_user =3D regime_is_user(env, mmu_idx); + uint32_t secure =3D regime_is_secure(env, mmu_idx); + int n; + int matchregion =3D -1; + bool hit =3D false; + uint32_t addr_page_base =3D address & TARGET_PAGE_MASK; + uint32_t addr_page_limit =3D addr_page_base + (TARGET_PAGE_SIZE - 1); + + *is_subpage =3D false; + *phys_ptr =3D address; + *prot =3D 0; + if (mregion) { + *mregion =3D -1; + } + + /* + * Unlike the ARM ARM pseudocode, we don't need to check whether this + * was an exception vector read from the vector table (which is always + * done using the default system address map), because those accesses + * are done in arm_v7m_load_vector(), which always does a direct + * read using address_space_ldl(), rather than going via this function. + */ + if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ + hit =3D true; + } else if (m_is_ppb_region(env, address)) { + hit =3D true; + } else { + if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) { + hit =3D true; + } + + for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { + /* region search */ + /* + * Note that the base address is bits [31:5] from the register + * with bits [4:0] all zeroes, but the limit address is bits + * [31:5] from the register with bits [4:0] all ones. + */ + uint32_t base =3D env->pmsav8.rbar[secure][n] & ~0x1f; + uint32_t limit =3D env->pmsav8.rlar[secure][n] | 0x1f; + + if (!(env->pmsav8.rlar[secure][n] & 0x1)) { + /* Region disabled */ + continue; + } + + if (address < base || address > limit) { + /* + * Address not in this region. We must check whether the + * region covers addresses in the same page as our address. + * In that case we must not report a size that covers the + * whole page for a subsequent hit against a different MPU + * region or the background region, because it would resul= t in + * incorrect TLB hits for subsequent accesses to addresses= that + * are in this MPU region. + */ + if (limit >=3D base && + ranges_overlap(base, limit - base + 1, + addr_page_base, + TARGET_PAGE_SIZE)) { + *is_subpage =3D true; + } + continue; + } + + if (base > addr_page_base || limit < addr_page_limit) { + *is_subpage =3D true; + } + + if (matchregion !=3D -1) { + /* + * Multiple regions match -- always a failure (unlike + * PMSAv7 where highest-numbered-region wins) + */ + fi->type =3D ARMFault_Permission; + fi->level =3D 1; + return true; + } + + matchregion =3D n; + hit =3D true; + } + } + + if (!hit) { + /* background fault */ + fi->type =3D ARMFault_Background; + return true; + } + + if (matchregion =3D=3D -1) { + /* hit using the background region */ + get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + } else { + uint32_t ap =3D extract32(env->pmsav8.rbar[secure][matchregion], 1= , 2); + uint32_t xn =3D extract32(env->pmsav8.rbar[secure][matchregion], 0= , 1); + bool pxn =3D false; + + if (arm_feature(env, ARM_FEATURE_V8_1M)) { + pxn =3D extract32(env->pmsav8.rlar[secure][matchregion], 4, 1); + } + + if (m_is_system_region(env, address)) { + /* System space is always execute never */ + xn =3D 1; + } + + *prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); + if (*prot && !xn && !(pxn && !is_user)) { + *prot |=3D PAGE_EXEC; + } + /* + * We don't need to look the attribute up in the MAIR0/MAIR1 + * registers because that only tells us about cacheability. + */ + if (mregion) { + *mregion =3D matchregion; + } + } + + fi->type =3D ARMFault_Permission; + fi->level =3D 1; + return !(*prot & (1 << access_type)); +} + + +static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_= idx, + hwaddr *phys_ptr, MemTxAttrs *txattrs, + int *prot, target_ulong *page_size, + ARMMMUFaultInfo *fi) +{ + uint32_t secure =3D regime_is_secure(env, mmu_idx); + V8M_SAttributes sattrs =3D {}; + bool ret; + bool mpu_is_subpage; + + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs); + if (access_type =3D=3D MMU_INST_FETCH) { + /* + * Instruction fetches always use the MMU bank and the + * transaction attribute determined by the fetch address, + * regardless of CPU state. This is painful for QEMU + * to handle, because it would mean we need to encode + * into the mmu_idx not just the (user, negpri) information + * for the current security state but also that for the + * other security state, which would balloon the number + * of mmu_idx values needed alarmingly. + * Fortunately we can avoid this because it's not actually + * possible to arbitrarily execute code from memory with + * the wrong security attribute: it will always generate + * an exception of some kind or another, apart from the + * special case of an NS CPU executing an SG instruction + * in S&NSC memory. So we always just fail the translation + * here and sort things out in the exception handler + * (including possibly emulating an SG instruction). + */ + if (sattrs.ns !=3D !secure) { + if (sattrs.nsc) { + fi->type =3D ARMFault_QEMU_NSCExec; + } else { + fi->type =3D ARMFault_QEMU_SFault; + } + *page_size =3D sattrs.subpage ? 1 : TARGET_PAGE_SIZE; + *phys_ptr =3D address; + *prot =3D 0; + return true; + } + } else { + /* + * For data accesses we always use the MMU bank indicated + * by the current CPU state, but the security attributes + * might downgrade a secure access to nonsecure. + */ + if (sattrs.ns) { + txattrs->secure =3D false; + } else if (!secure) { + /* + * NS access to S memory must fault. + * Architecturally we should first check whether the + * MPU information for this address indicates that we + * are doing an unaligned access to Device memory, which + * should generate a UsageFault instead. QEMU does not + * currently check for that kind of unaligned access thoug= h. + * If we added it we would need to do so as a special case + * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). + */ + fi->type =3D ARMFault_QEMU_SFault; + *page_size =3D sattrs.subpage ? 1 : TARGET_PAGE_SIZE; + *phys_ptr =3D address; + *prot =3D 0; + return true; + } + } + } + + ret =3D pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, + txattrs, prot, &mpu_is_subpage, fi, NULL); + *page_size =3D sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; + return ret; +} + +static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_= idx, + hwaddr *phys_ptr, int *prot, + ARMMMUFaultInfo *fi) +{ + int n; + uint32_t mask; + uint32_t base; + bool is_user =3D regime_is_user(env, mmu_idx); + + if (regime_translation_disabled(env, mmu_idx)) { + /* MPU disabled. */ + *phys_ptr =3D address; + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return false; + } + + *phys_ptr =3D address; + for (n =3D 7; n >=3D 0; n--) { + base =3D env->cp15.c6_region[n]; + if ((base & 1) =3D=3D 0) { + continue; + } + mask =3D 1 << ((base >> 1) & 0x1f); + /* + * Keep this shift separate from the above to avoid an + * (undefined) << 32 + */ + mask =3D (mask << 1) - 1; + if (((base ^ address) & ~mask) =3D=3D 0) { + break; + } + } + if (n < 0) { + fi->type =3D ARMFault_Background; + return true; + } + + if (access_type =3D=3D MMU_INST_FETCH) { + mask =3D env->cp15.pmsav5_insn_ap; + } else { + mask =3D env->cp15.pmsav5_data_ap; + } + mask =3D (mask >> (n * 4)) & 0xf; + switch (mask) { + case 0: + fi->type =3D ARMFault_Permission; + fi->level =3D 1; + return true; + case 1: + if (is_user) { + fi->type =3D ARMFault_Permission; + fi->level =3D 1; + return true; + } + *prot =3D PAGE_READ | PAGE_WRITE; + break; + case 2: + *prot =3D PAGE_READ; + if (!is_user) { + *prot |=3D PAGE_WRITE; + } + break; + case 3: + *prot =3D PAGE_READ | PAGE_WRITE; + break; + case 5: + if (is_user) { + fi->type =3D ARMFault_Permission; + fi->level =3D 1; + return true; + } + *prot =3D PAGE_READ; + break; + case 6: + *prot =3D PAGE_READ; + break; + default: + /* Bad permission. */ + fi->type =3D ARMFault_Permission; + fi->level =3D 1; + return true; + } + *prot |=3D PAGE_EXEC; + return false; +} + +/* + * Combine either inner or outer cacheability attributes for normal + * memory, according to table D4-42 and pseudocode procedure + * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). + * + * NB: only stage 1 includes allocation hints (RW bits), leading to + * some asymmetry. + */ +static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2) +{ + if (s1 =3D=3D 4 || s2 =3D=3D 4) { + /* non-cacheable has precedence */ + return 4; + } else if (extract32(s1, 2, 2) =3D=3D 0 || extract32(s1, 2, 2) =3D=3D = 2) { + /* stage 1 write-through takes precedence */ + return s1; + } else if (extract32(s2, 2, 2) =3D=3D 2) { + /* + * stage 2 write-through takes precedence, but the allocation hint + * is still taken from stage 1 + */ + return (2 << 2) | extract32(s1, 0, 2); + } else { /* write-back */ + return s1; + } +} + +/* + * Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 + * and CombineS1S2Desc() + * + * @s1: Attributes from stage 1 walk + * @s2: Attributes from stage 2 walk + */ +static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) +{ + uint8_t s1lo, s2lo, s1hi, s2hi; + ARMCacheAttrs ret; + bool tagged =3D false; + + if (s1.attrs =3D=3D 0xf0) { + tagged =3D true; + s1.attrs =3D 0xff; + } + + s1lo =3D extract32(s1.attrs, 0, 4); + s2lo =3D extract32(s2.attrs, 0, 4); + s1hi =3D extract32(s1.attrs, 4, 4); + s2hi =3D extract32(s2.attrs, 4, 4); + + /* Combine shareability attributes (table D4-43) */ + if (s1.shareability =3D=3D 2 || s2.shareability =3D=3D 2) { + /* if either are outer-shareable, the result is outer-shareable */ + ret.shareability =3D 2; + } else if (s1.shareability =3D=3D 3 || s2.shareability =3D=3D 3) { + /* if either are inner-shareable, the result is inner-shareable */ + ret.shareability =3D 3; + } else { + /* both non-shareable */ + ret.shareability =3D 0; + } + + /* Combine memory type and cacheability attributes */ + if (s1hi =3D=3D 0 || s2hi =3D=3D 0) { + /* Device has precedence over normal */ + if (s1lo =3D=3D 0 || s2lo =3D=3D 0) { + /* nGnRnE has precedence over anything */ + ret.attrs =3D 0; + } else if (s1lo =3D=3D 4 || s2lo =3D=3D 4) { + /* non-Reordering has precedence over Reordering */ + ret.attrs =3D 4; /* nGnRE */ + } else if (s1lo =3D=3D 8 || s2lo =3D=3D 8) { + /* non-Gathering has precedence over Gathering */ + ret.attrs =3D 8; /* nGRE */ + } else { + ret.attrs =3D 0xc; /* GRE */ + } + + /* + * Any location for which the resultant memory type is any + * type of Device memory is always treated as Outer Shareable. + */ + ret.shareability =3D 2; + } else { /* Normal memory */ + /* Outer/inner cacheability combine independently */ + ret.attrs =3D combine_cacheattr_nibble(s1hi, s2hi) << 4 + | combine_cacheattr_nibble(s1lo, s2lo); + + if (ret.attrs =3D=3D 0x44) { + /* + * Any location for which the resultant memory type is Normal + * Inner Non-cacheable, Outer Non-cacheable is always treated + * as Outer Shareable. + */ + ret.shareability =3D 2; + } + } + + /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */ + if (tagged && ret.attrs =3D=3D 0xff) { + ret.attrs =3D 0xf0; + } + + return ret; +} + + +/* + * get_phys_addr - get the physical address for this virtual address + * + * Find the physical address corresponding to the given virtual address, + * by doing a translation table walk on MMU based systems or using the + * MPU state on MPU based systems. + * + * Returns false if the translation was successful. Otherwise, phys_ptr, a= ttrs, + * prot and page_size may not be filled in, and the populated fsr value pr= ovides + * information on why the translation aborted, in the format of a + * DFSR/IFSR fault register, with the following caveats: + * * we honour the short vs long DFSR format differences. + * * the WnR bit is never set (the caller must do this). + * * for PSMAv5 based systems we don't bother to return a full FSR format + * value. + * + * @env: CPUARMState + * @address: virtual address to get physical address for + * @access_type: 0 for read, 1 for write, 2 for execute + * @mmu_idx: MMU index indicating required translation regime + * @phys_ptr: set to the physical address corresponding to the virtual add= ress + * @attrs: set to the memory transaction attributes to use + * @prot: set to the permissions for the page containing phys_ptr + * @page_size: set to the size of the page containing phys_ptr + * @fi: set to fault info if the translation fails + * @cacheattrs: (if non-NULL) set to the cacheability/shareability attribu= tes + */ +bool get_phys_addr(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) +{ + ARMMMUIdx s1_mmu_idx =3D stage_1_mmu_idx(mmu_idx); + + if (mmu_idx !=3D s1_mmu_idx) { + /* + * Call ourselves recursively to do the stage 1 and then stage 2 + * translations if mmu_idx is a two-stage regime. + */ + if (arm_feature(env, ARM_FEATURE_EL2)) { + hwaddr ipa; + int s2_prot; + int ret; + ARMCacheAttrs cacheattrs2 =3D {}; + ARMMMUIdx s2_mmu_idx; + bool is_el0; + + ret =3D get_phys_addr(env, address, access_type, s1_mmu_idx, &= ipa, + attrs, prot, page_size, fi, cacheattrs); + + /* If S1 fails or S2 is disabled, return early. */ + if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2))= { + *phys_ptr =3D ipa; + return ret; + } + + s2_mmu_idx =3D attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_= Stage2; + is_el0 =3D mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D AR= MMMUIdx_SE10_0; + + /* S1 is done. Now do S2 translation. */ + ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, = is_el0, + phys_ptr, attrs, &s2_prot, + page_size, fi, &cacheattrs2); + fi->s2addr =3D ipa; + /* Combine the S1 and S2 perms. */ + *prot &=3D s2_prot; + + /* If S2 fails, return early. */ + if (ret) { + return ret; + } + + /* Combine the S1 and S2 cache attributes. */ + if (arm_hcr_el2_eff(env) & HCR_DC) { + /* + * HCR.DC forces the first stage attributes to + * Normal Non-Shareable, + * Inner Write-Back Read-Allocate Write-Allocate, + * Outer Write-Back Read-Allocate Write-Allocate. + * Do not overwrite Tagged within attrs. + */ + if (cacheattrs->attrs !=3D 0xf0) { + cacheattrs->attrs =3D 0xff; + } + cacheattrs->shareability =3D 0; + } + *cacheattrs =3D combine_cacheattrs(*cacheattrs, cacheattrs2); + + /* Check if IPA translates to secure or non-secure PA space. */ + if (arm_is_secure_below_el3(env)) { + if (attrs->secure) { + attrs->secure =3D + !(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_= SW)); + } else { + attrs->secure =3D + !((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA | VTCR_N= SW)) + || (env->cp15.vstcr_el2.raw_tcr & VSTCR_SA)); + } + } + return 0; + } else { + /* + * For non-EL2 CPUs a stage1+stage2 translation is just stage = 1. + */ + mmu_idx =3D stage_1_mmu_idx(mmu_idx); + } + } + + /* + * The page table entries may downgrade secure to non-secure, but + * cannot upgrade an non-secure translation regime's attributes + * to secure. + */ + attrs->secure =3D regime_is_secure(env, mmu_idx); + attrs->user =3D regime_is_user(env, mmu_idx); + + /* + * Fast Context Switch Extension. This doesn't exist at all in v8. + * In v7 and earlier it affects all stage 1 translations. + */ + if (address < 0x02000000 && mmu_idx !=3D ARMMMUIdx_Stage2 + && !arm_feature(env, ARM_FEATURE_V8)) { + if (regime_el(env, mmu_idx) =3D=3D 3) { + address +=3D env->cp15.fcseidr_s; + } else { + address +=3D env->cp15.fcseidr_ns; + } + } + + if (arm_feature(env, ARM_FEATURE_PMSA)) { + bool ret; + *page_size =3D TARGET_PAGE_SIZE; + + if (arm_feature(env, ARM_FEATURE_V8)) { + /* PMSAv8 */ + ret =3D get_phys_addr_pmsav8(env, address, access_type, mmu_id= x, + phys_ptr, attrs, prot, page_size, f= i); + } else if (arm_feature(env, ARM_FEATURE_V7)) { + /* PMSAv7 */ + ret =3D get_phys_addr_pmsav7(env, address, access_type, mmu_id= x, + phys_ptr, prot, page_size, fi); + } else { + /* Pre-v7 MPU */ + ret =3D get_phys_addr_pmsav5(env, address, access_type, mmu_id= x, + phys_ptr, prot, fi); + } + qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 + " mmu_idx %u -> %s (prot %c%c%c)\n", + access_type =3D=3D MMU_DATA_LOAD ? "reading" : + (access_type =3D=3D MMU_DATA_STORE ? "writing" : "ex= ecute"), + (uint32_t)address, mmu_idx, + ret ? "Miss" : "Hit", + *prot & PAGE_READ ? 'r' : '-', + *prot & PAGE_WRITE ? 'w' : '-', + *prot & PAGE_EXEC ? 'x' : '-'); + + return ret; + } + + /* Definitely a real MMU, not an MPU */ + + if (regime_translation_disabled(env, mmu_idx)) { + uint64_t hcr; + uint8_t memattr; + + /* + * MMU disabled. S1 addresses within aa64 translation regimes are + * still checked for bounds -- see AArch64.TranslateAddressS1Off. + */ + if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2= _S) { + int r_el =3D regime_el(env, mmu_idx); + if (arm_el_is_aa64(env, r_el)) { + int pamax =3D arm_pamax(env_archcpu(env)); + uint64_t tcr =3D env->cp15.tcr_el[r_el].raw_tcr; + int addrtop, tbi; + + tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); + if (access_type =3D=3D MMU_INST_FETCH) { + tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); + } + tbi =3D (tbi >> extract64(address, 55, 1)) & 1; + addrtop =3D (tbi ? 55 : 63); + + if (extract64(address, pamax, addrtop - pamax + 1) !=3D 0)= { + fi->type =3D ARMFault_AddressSize; + fi->level =3D 0; + fi->stage2 =3D false; + return 1; + } + + /* + * When TBI is disabled, we've just validated that all of = the + * bits above PAMax are zero, so logically we only need to + * clear the top byte for TBI. But it's clearer to follow + * the pseudocode set of addrdesc.paddress. + */ + address =3D extract64(address, 0, 52); + } + } + *phys_ptr =3D address; + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + *page_size =3D TARGET_PAGE_SIZE; + + /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ + hcr =3D arm_hcr_el2_eff(env); + cacheattrs->shareability =3D 0; + if (hcr & HCR_DC) { + if (hcr & HCR_DCT) { + memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ + } else { + memattr =3D 0xff; /* Normal, WB, RWA */ + } + } else if (access_type =3D=3D MMU_INST_FETCH) { + if (regime_sctlr(env, mmu_idx) & SCTLR_I) { + memattr =3D 0xee; /* Normal, WT, RA, NT */ + } else { + memattr =3D 0x44; /* Normal, NC, No */ + } + cacheattrs->shareability =3D 2; /* outer sharable */ + } else { + memattr =3D 0x00; /* Device, nGnRnE */ + } + cacheattrs->attrs =3D memattr; + return 0; + } + + if (regime_using_lpae_format(env, mmu_idx)) { + return get_phys_addr_lpae(env, address, access_type, mmu_idx, fals= e, + phys_ptr, attrs, prot, page_size, + fi, cacheattrs); + } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { + return get_phys_addr_v6(env, address, access_type, mmu_idx, + phys_ptr, attrs, prot, page_size, fi); + } else { + return get_phys_addr_v5(env, address, access_type, mmu_idx, + phys_ptr, prot, page_size, fi); + } +} + +hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, + MemTxAttrs *attrs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + hwaddr phys_addr; + target_ulong page_size; + int prot; + bool ret; + ARMMMUFaultInfo fi =3D {}; + ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); + ARMCacheAttrs cacheattrs =3D {}; + + *attrs =3D (MemTxAttrs) {}; + + ret =3D get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &phys_addr, + attrs, &prot, &page_size, &fi, &cacheattrs); + + if (ret) { + return -1; + } + return phys_addr; +} diff --git a/target/arm/cpu-mmu.c b/target/arm/cpu-mmu.c new file mode 100644 index 0000000000..f463f8458e --- /dev/null +++ b/target/arm/cpu-mmu.c @@ -0,0 +1,124 @@ +/* + * QEMU ARM CPU address translation related code + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "qemu/osdep.h" +#include "cpu-mmu.h" + +int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) +{ + if (regime_has_2_ranges(mmu_idx)) { + return extract64(tcr, 37, 2); + } else if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx= _Stage2_S) { + return 0; /* VTCR_EL2 */ + } else { + /* Replicate the single TBI bit so we always have 2 bits. */ + return extract32(tcr, 20, 1) * 3; + } +} + +int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) +{ + if (regime_has_2_ranges(mmu_idx)) { + return extract64(tcr, 51, 2); + } else if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx= _Stage2_S) { + return 0; /* VTCR_EL2 */ + } else { + /* Replicate the single TBID bit so we always have 2 bits. */ + return extract32(tcr, 29, 1) * 3; + } +} + +int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx) +{ + if (regime_has_2_ranges(mmu_idx)) { + return extract64(tcr, 57, 2); + } else { + /* Replicate the single TCMA bit so we always have 2 bits. */ + return extract32(tcr, 30, 1) * 3; + } +} + +ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data) +{ + uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; + bool epd, hpd, using16k, using64k; + int select, tsz, tbi, max_tsz; + + if (!regime_has_2_ranges(mmu_idx)) { + select =3D 0; + tsz =3D extract32(tcr, 0, 6); + using64k =3D extract32(tcr, 14, 1); + using16k =3D extract32(tcr, 15, 1); + if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_St= age2_S) { + /* VTCR_EL2 */ + hpd =3D false; + } else { + hpd =3D extract32(tcr, 24, 1); + } + epd =3D false; + } else { + /* + * Bit 55 is always between the two regions, and is canonical for + * determining if address tagging is enabled. + */ + select =3D extract64(va, 55, 1); + if (!select) { + tsz =3D extract32(tcr, 0, 6); + epd =3D extract32(tcr, 7, 1); + using64k =3D extract32(tcr, 14, 1); + using16k =3D extract32(tcr, 15, 1); + hpd =3D extract64(tcr, 41, 1); + } else { + int tg =3D extract32(tcr, 30, 2); + using16k =3D tg =3D=3D 1; + using64k =3D tg =3D=3D 3; + tsz =3D extract32(tcr, 16, 6); + epd =3D extract32(tcr, 23, 1); + hpd =3D extract64(tcr, 42, 1); + } + } + + if (cpu_isar_feature(aa64_st, env_archcpu(env))) { + max_tsz =3D 48 - using64k; + } else { + max_tsz =3D 39; + } + + tsz =3D MIN(tsz, max_tsz); + tsz =3D MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ + + /* Present TBI as a composite with TBID. */ + tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); + if (!data) { + tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); + } + tbi =3D (tbi >> select) & 1; + + return (ARMVAParameters) { + .tsz =3D tsz, + .select =3D select, + .tbi =3D tbi, + .epd =3D epd, + .hpd =3D hpd, + .using16k =3D using16k, + .using64k =3D using64k, + }; +} diff --git a/target/arm/cpu.c b/target/arm/cpu.c index bd8413c161..17dc0d4255 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -41,6 +41,7 @@ #include "kvm_arm.h" #include "disas/capstone.h" #include "fpu/softfloat.h" +#include "cpu-mmu.h" =20 static void arm_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index 2a5022032c..7f818e5860 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -36,23 +36,12 @@ #include "exec/cpu_ldst.h" #include "semihosting/common-semi.h" #endif +#include "cpu-mmu.h" =20 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ #define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */ =20 -#ifndef CONFIG_USER_ONLY - -static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, - MMUAccessType access_type, ARMMMUIdx mmu_id= x, - bool s1_is_el0, - hwaddr *phys_ptr, MemTxAttrs *txattrs, int = *prot, - target_ulong *page_size_ptr, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs) - __attribute__((nonnull)); -#endif - static void switch_mode(CPUARMState *env, int mode); -static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx); =20 static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) { @@ -10452,125 +10441,6 @@ uint64_t arm_sctlr(CPUARMState *env, int el) return env->cp15.sctlr_el[el]; } =20 -/* Return the SCTLR value which controls this address translation regime */ -static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; -} - -#ifndef CONFIG_USER_ONLY - -/* Return true if the specified stage of address translation is disabled */ -static inline bool regime_translation_disabled(CPUARMState *env, - ARMMMUIdx mmu_idx) -{ - uint64_t hcr_el2; - - if (arm_feature(env, ARM_FEATURE_M)) { - switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & - (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK= )) { - case R_V7M_MPU_CTRL_ENABLE_MASK: - /* Enabled, but not for HardFault and NMI */ - return mmu_idx & ARM_MMU_IDX_M_NEGPRI; - case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: - /* Enabled for all cases */ - return false; - case 0: - default: - /* - * HFNMIENA set and ENABLE clear is UNPREDICTABLE, but - * we warned about that in armv7m_nvic.c when the guest set it. - */ - return true; - } - } - - hcr_el2 =3D arm_hcr_el2_eff(env); - - if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { - /* HCR.DC means HCR.VM behaves as 1 */ - return (hcr_el2 & (HCR_DC | HCR_VM)) =3D=3D 0; - } - - if (hcr_el2 & HCR_TGE) { - /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ - if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) =3D= =3D 1) { - return true; - } - } - - if ((hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { - /* HCR.DC means SCTLR_EL1.M behaves as 0 */ - return true; - } - - return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; -} - -static inline bool regime_translation_big_endian(CPUARMState *env, - ARMMMUIdx mmu_idx) -{ - return (regime_sctlr(env, mmu_idx) & SCTLR_EE) !=3D 0; -} - -/* Return the TTBR associated with this translation regime */ -static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, - int ttbrn) -{ - if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { - return env->cp15.vttbr_el2; - } - if (mmu_idx =3D=3D ARMMMUIdx_Stage2_S) { - return env->cp15.vsttbr_el2; - } - if (ttbrn =3D=3D 0) { - return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; - } else { - return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; - } -} - -#endif /* !CONFIG_USER_ONLY */ - -/* - * Convert a possible stage1+2 MMU index into the appropriate - * stage 1 MMU index - */ -static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_SE10_0: - return ARMMMUIdx_Stage1_SE0; - case ARMMMUIdx_SE10_1: - return ARMMMUIdx_Stage1_SE1; - case ARMMMUIdx_SE10_1_PAN: - return ARMMMUIdx_Stage1_SE1_PAN; - case ARMMMUIdx_E10_0: - return ARMMMUIdx_Stage1_E0; - case ARMMMUIdx_E10_1: - return ARMMMUIdx_Stage1_E1; - case ARMMMUIdx_E10_1_PAN: - return ARMMMUIdx_Stage1_E1_PAN; - default: - return mmu_idx; - } -} - -/* Return true if the translation regime is using LPAE format page tables = */ -static inline bool regime_using_lpae_format(CPUARMState *env, - ARMMMUIdx mmu_idx) -{ - int el =3D regime_el(env, mmu_idx); - if (el =3D=3D 2 || arm_el_is_aa64(env, el)) { - return true; - } - if (arm_feature(env, ARM_FEATURE_LPAE) - && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) { - return true; - } - return false; -} - /* Returns true if the stage 1 translation regime is using LPAE format page * tables. Used when raising alignment exceptions, whose FSR changes depen= ding * on whether the long or short descriptor format is in use. */ @@ -10581,2316 +10451,6 @@ bool arm_s1_regime_using_lpae_format(CPUARMState= *env, ARMMMUIdx mmu_idx) return regime_using_lpae_format(env, mmu_idx); } =20 -#ifndef CONFIG_USER_ONLY -static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_E20_0: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_Stage1_SE0: - case ARMMMUIdx_MUser: - case ARMMMUIdx_MSUser: - case ARMMMUIdx_MUserNegPri: - case ARMMMUIdx_MSUserNegPri: - return true; - default: - return false; - case ARMMMUIdx_E10_0: - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - g_assert_not_reached(); - } -} - -/* - * Translate section/page access permissions to page - * R/W protection flags - * - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * @ap: The 3-bit access permissions (AP[2:0]) - * @domain_prot: The 2-bit domain access permissions - */ -static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, - int ap, int domain_prot) -{ - bool is_user =3D regime_is_user(env, mmu_idx); - - if (domain_prot =3D=3D 3) { - return PAGE_READ | PAGE_WRITE; - } - - switch (ap) { - case 0: - if (arm_feature(env, ARM_FEATURE_V7)) { - return 0; - } - switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) { - case SCTLR_S: - return is_user ? 0 : PAGE_READ; - case SCTLR_R: - return PAGE_READ; - default: - return 0; - } - case 1: - return is_user ? 0 : PAGE_READ | PAGE_WRITE; - case 2: - if (is_user) { - return PAGE_READ; - } else { - return PAGE_READ | PAGE_WRITE; - } - case 3: - return PAGE_READ | PAGE_WRITE; - case 4: /* Reserved. */ - return 0; - case 5: - return is_user ? 0 : PAGE_READ; - case 6: - return PAGE_READ; - case 7: - if (!arm_feature(env, ARM_FEATURE_V6K)) { - return 0; - } - return PAGE_READ; - default: - g_assert_not_reached(); - } -} - -/* - * Translate section/page access permissions to page - * R/W protection flags. - * - * @ap: The 2-bit simple AP (AP[2:1]) - * @is_user: TRUE if accessing from PL0 - */ -static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user) -{ - switch (ap) { - case 0: - return is_user ? 0 : PAGE_READ | PAGE_WRITE; - case 1: - return PAGE_READ | PAGE_WRITE; - case 2: - return is_user ? 0 : PAGE_READ; - case 3: - return PAGE_READ; - default: - g_assert_not_reached(); - } -} - -static inline int -simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap) -{ - return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); -} - -/* - * Translate S2 section/page access permissions to protection flags - * - * @env: CPUARMState - * @s2ap: The 2-bit stage2 access permissions (S2AP) - * @xn: XN (execute-never) bits - * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0 - */ -static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) -{ - int prot =3D 0; - - if (s2ap & 1) { - prot |=3D PAGE_READ; - } - if (s2ap & 2) { - prot |=3D PAGE_WRITE; - } - - if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) { - switch (xn) { - case 0: - prot |=3D PAGE_EXEC; - break; - case 1: - if (s1_is_el0) { - prot |=3D PAGE_EXEC; - } - break; - case 2: - break; - case 3: - if (!s1_is_el0) { - prot |=3D PAGE_EXEC; - } - break; - default: - g_assert_not_reached(); - } - } else { - if (!extract32(xn, 1, 1)) { - if (arm_el_is_aa64(env, 2) || prot & PAGE_READ) { - prot |=3D PAGE_EXEC; - } - } - } - return prot; -} - -/* - * Translate section/page access permissions to protection flags - * - * @env: CPUARMState - * @mmu_idx: MMU index indicating required translation regime - * @is_aa64: TRUE if AArch64 - * @ap: The 2-bit simple AP (AP[2:1]) - * @ns: NS (non-secure) bit - * @xn: XN (execute-never) bit - * @pxn: PXN (privileged execute-never) bit - */ -static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64, - int ap, int ns, int xn, int pxn) -{ - bool is_user =3D regime_is_user(env, mmu_idx); - int prot_rw, user_rw; - bool have_wxn; - int wxn =3D 0; - - assert(mmu_idx !=3D ARMMMUIdx_Stage2); - assert(mmu_idx !=3D ARMMMUIdx_Stage2_S); - - user_rw =3D simple_ap_to_rw_prot_is_user(ap, true); - if (is_user) { - prot_rw =3D user_rw; - } else { - if (user_rw && regime_is_pan(env, mmu_idx)) { - /* PAN forbids data accesses but doesn't affect insn fetch */ - prot_rw =3D 0; - } else { - prot_rw =3D simple_ap_to_rw_prot_is_user(ap, false); - } - } - - if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) { - return prot_rw; - } - - /* - * TODO have_wxn should be replaced with - * ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2) - * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE - * compatible processors have EL2, which is required for [U]WXN. - */ - have_wxn =3D arm_feature(env, ARM_FEATURE_LPAE); - - if (have_wxn) { - wxn =3D regime_sctlr(env, mmu_idx) & SCTLR_WXN; - } - - if (is_aa64) { - if (regime_has_2_ranges(mmu_idx) && !is_user) { - xn =3D pxn || (user_rw & PAGE_WRITE); - } - } else if (arm_feature(env, ARM_FEATURE_V7)) { - switch (regime_el(env, mmu_idx)) { - case 1: - case 3: - if (is_user) { - xn =3D xn || !(user_rw & PAGE_READ); - } else { - int uwxn =3D 0; - if (have_wxn) { - uwxn =3D regime_sctlr(env, mmu_idx) & SCTLR_UWXN; - } - xn =3D xn || !(prot_rw & PAGE_READ) || pxn || - (uwxn && (user_rw & PAGE_WRITE)); - } - break; - case 2: - break; - } - } else { - xn =3D wxn =3D 0; - } - - if (xn || (wxn && (prot_rw & PAGE_WRITE))) { - return prot_rw; - } - return prot_rw | PAGE_EXEC; -} - -static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, - uint32_t *table, uint32_t address) -{ - /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ - TCR *tcr =3D regime_tcr(env, mmu_idx); - - if (address & tcr->mask) { - if (tcr->raw_tcr & TTBCR_PD1) { - /* Translation table walk disabled for TTBR1 */ - return false; - } - *table =3D regime_ttbr(env, mmu_idx, 1) & 0xffffc000; - } else { - if (tcr->raw_tcr & TTBCR_PD0) { - /* Translation table walk disabled for TTBR0 */ - return false; - } - *table =3D regime_ttbr(env, mmu_idx, 0) & tcr->base_mask; - } - *table |=3D (address >> 18) & 0x3ffc; - return true; -} - -/* Translate a S1 pagetable walk through S2 if needed. */ -static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, - hwaddr addr, bool *is_secure, - ARMMMUFaultInfo *fi) -{ - if (arm_mmu_idx_is_stage1_of_2(mmu_idx) && - !regime_translation_disabled(env, ARMMMUIdx_Stage2)) { - target_ulong s2size; - hwaddr s2pa; - int s2prot; - int ret; - ARMMMUIdx s2_mmu_idx =3D *is_secure ? ARMMMUIdx_Stage2_S - : ARMMMUIdx_Stage2; - ARMCacheAttrs cacheattrs =3D {}; - MemTxAttrs txattrs =3D {}; - - ret =3D get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, f= alse, - &s2pa, &txattrs, &s2prot, &s2size, fi, - &cacheattrs); - if (ret) { - assert(fi->type !=3D ARMFault_None); - fi->s2addr =3D addr; - fi->stage2 =3D true; - fi->s1ptw =3D true; - fi->s1ns =3D !*is_secure; - return ~0; - } - if ((arm_hcr_el2_eff(env) & HCR_PTW) && - (cacheattrs.attrs & 0xf0) =3D=3D 0) { - /* - * PTW set and S1 walk touched S2 Device memory: - * generate Permission fault. - */ - fi->type =3D ARMFault_Permission; - fi->s2addr =3D addr; - fi->stage2 =3D true; - fi->s1ptw =3D true; - fi->s1ns =3D !*is_secure; - return ~0; - } - - if (arm_is_secure_below_el3(env)) { - /* Check if page table walk is to secure or non-secure PA spac= e. */ - if (*is_secure) { - *is_secure =3D !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); - } else { - *is_secure =3D !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); - } - } else { - assert(!*is_secure); - } - - addr =3D s2pa; - } - return addr; -} - -/* All loads done in the course of a page table walk go through here. */ -static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - MemTxAttrs attrs =3D {}; - MemTxResult result =3D MEMTX_OK; - AddressSpace *as; - uint32_t data; - - addr =3D S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); - attrs.secure =3D is_secure; - as =3D arm_addressspace(cs, attrs); - if (fi->s1ptw) { - return 0; - } - if (regime_translation_big_endian(env, mmu_idx)) { - data =3D address_space_ldl_be(as, addr, attrs, &result); - } else { - data =3D address_space_ldl_le(as, addr, attrs, &result); - } - if (result =3D=3D MEMTX_OK) { - return data; - } - fi->type =3D ARMFault_SyncExternalOnWalk; - fi->ea =3D arm_extabort_type(result); - return 0; -} - -static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - MemTxAttrs attrs =3D {}; - MemTxResult result =3D MEMTX_OK; - AddressSpace *as; - uint64_t data; - - addr =3D S1_ptw_translate(env, mmu_idx, addr, &is_secure, fi); - attrs.secure =3D is_secure; - as =3D arm_addressspace(cs, attrs); - if (fi->s1ptw) { - return 0; - } - if (regime_translation_big_endian(env, mmu_idx)) { - data =3D address_space_ldq_be(as, addr, attrs, &result); - } else { - data =3D address_space_ldq_le(as, addr, attrs, &result); - } - if (result =3D=3D MEMTX_OK) { - return data; - } - fi->type =3D ARMFault_SyncExternalOnWalk; - fi->ea =3D arm_extabort_type(result); - return 0; -} - -static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi) -{ - CPUState *cs =3D env_cpu(env); - int level =3D 1; - uint32_t table; - uint32_t desc; - int type; - int ap; - int domain =3D 0; - int domain_prot; - hwaddr phys_addr; - uint32_t dacr; - - /* Pagetable walk. */ - /* Lookup l1 descriptor. */ - if (!get_level1_table_address(env, mmu_idx, &table, address)) { - /* Section translation fault if page walk is disabled by PD0 or PD= 1 */ - fi->type =3D ARMFault_Translation; - goto do_fault; - } - desc =3D arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); - if (fi->type !=3D ARMFault_None) { - goto do_fault; - } - type =3D (desc & 3); - domain =3D (desc >> 5) & 0x0f; - if (regime_el(env, mmu_idx) =3D=3D 1) { - dacr =3D env->cp15.dacr_ns; - } else { - dacr =3D env->cp15.dacr_s; - } - domain_prot =3D (dacr >> (domain * 2)) & 3; - if (type =3D=3D 0) { - /* Section translation fault. */ - fi->type =3D ARMFault_Translation; - goto do_fault; - } - if (type !=3D 2) { - level =3D 2; - } - if (domain_prot =3D=3D 0 || domain_prot =3D=3D 2) { - fi->type =3D ARMFault_Domain; - goto do_fault; - } - if (type =3D=3D 2) { - /* 1Mb section. */ - phys_addr =3D (desc & 0xfff00000) | (address & 0x000fffff); - ap =3D (desc >> 10) & 3; - *page_size =3D 1024 * 1024; - } else { - /* Lookup l2 entry. */ - if (type =3D=3D 1) { - /* Coarse pagetable. */ - table =3D (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); - } else { - /* Fine pagetable. */ - table =3D (desc & 0xfffff000) | ((address >> 8) & 0xffc); - } - desc =3D arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); - if (fi->type !=3D ARMFault_None) { - goto do_fault; - } - switch (desc & 3) { - case 0: /* Page translation fault. */ - fi->type =3D ARMFault_Translation; - goto do_fault; - case 1: /* 64k page. */ - phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); - ap =3D (desc >> (4 + ((address >> 13) & 6))) & 3; - *page_size =3D 0x10000; - break; - case 2: /* 4k page. */ - phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); - ap =3D (desc >> (4 + ((address >> 9) & 6))) & 3; - *page_size =3D 0x1000; - break; - case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ - if (type =3D=3D 1) { - /* ARMv6/XScale extended small page format */ - if (arm_feature(env, ARM_FEATURE_XSCALE) - || arm_feature(env, ARM_FEATURE_V6)) { - phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); - *page_size =3D 0x1000; - } else { - /* - * UNPREDICTABLE in ARMv5; we choose to take a - * page translation fault. - */ - fi->type =3D ARMFault_Translation; - goto do_fault; - } - } else { - phys_addr =3D (desc & 0xfffffc00) | (address & 0x3ff); - *page_size =3D 0x400; - } - ap =3D (desc >> 4) & 3; - break; - default: - /* Never happens, but compiler isn't smart enough to tell. */ - abort(); - } - } - *prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); - *prot |=3D *prot ? PAGE_EXEC : 0; - if (!(*prot & (1 << access_type))) { - /* Access permission fault. */ - fi->type =3D ARMFault_Permission; - goto do_fault; - } - *phys_ptr =3D phys_addr; - return false; -do_fault: - fi->domain =3D domain; - fi->level =3D level; - return true; -} - -static bool get_phys_addr_v6(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *pro= t, - target_ulong *page_size, ARMMMUFaultInfo *fi) -{ - CPUState *cs =3D env_cpu(env); - ARMCPU *cpu =3D env_archcpu(env); - int level =3D 1; - uint32_t table; - uint32_t desc; - uint32_t xn; - uint32_t pxn =3D 0; - int type; - int ap; - int domain =3D 0; - int domain_prot; - hwaddr phys_addr; - uint32_t dacr; - bool ns; - - /* Pagetable walk. */ - /* Lookup l1 descriptor. */ - if (!get_level1_table_address(env, mmu_idx, &table, address)) { - /* Section translation fault if page walk is disabled by PD0 or PD= 1 */ - fi->type =3D ARMFault_Translation; - goto do_fault; - } - desc =3D arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); - if (fi->type !=3D ARMFault_None) { - goto do_fault; - } - type =3D (desc & 3); - if (type =3D=3D 0 || (type =3D=3D 3 && !cpu_isar_feature(aa32_pxn, cpu= ))) { - /* - * Section translation fault, or attempt to use the encoding - * which is Reserved on implementations without PXN. - */ - fi->type =3D ARMFault_Translation; - goto do_fault; - } - if ((type =3D=3D 1) || !(desc & (1 << 18))) { - /* Page or Section. */ - domain =3D (desc >> 5) & 0x0f; - } - if (regime_el(env, mmu_idx) =3D=3D 1) { - dacr =3D env->cp15.dacr_ns; - } else { - dacr =3D env->cp15.dacr_s; - } - if (type =3D=3D 1) { - level =3D 2; - } - domain_prot =3D (dacr >> (domain * 2)) & 3; - if (domain_prot =3D=3D 0 || domain_prot =3D=3D 2) { - /* Section or Page domain fault */ - fi->type =3D ARMFault_Domain; - goto do_fault; - } - if (type !=3D 1) { - if (desc & (1 << 18)) { - /* Supersection. */ - phys_addr =3D (desc & 0xff000000) | (address & 0x00ffffff); - phys_addr |=3D (uint64_t)extract32(desc, 20, 4) << 32; - phys_addr |=3D (uint64_t)extract32(desc, 5, 4) << 36; - *page_size =3D 0x1000000; - } else { - /* Section. */ - phys_addr =3D (desc & 0xfff00000) | (address & 0x000fffff); - *page_size =3D 0x100000; - } - ap =3D ((desc >> 10) & 3) | ((desc >> 13) & 4); - xn =3D desc & (1 << 4); - pxn =3D desc & 1; - ns =3D extract32(desc, 19, 1); - } else { - if (cpu_isar_feature(aa32_pxn, cpu)) { - pxn =3D (desc >> 2) & 1; - } - ns =3D extract32(desc, 3, 1); - /* Lookup l2 entry. */ - table =3D (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); - desc =3D arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); - if (fi->type !=3D ARMFault_None) { - goto do_fault; - } - ap =3D ((desc >> 4) & 3) | ((desc >> 7) & 4); - switch (desc & 3) { - case 0: /* Page translation fault. */ - fi->type =3D ARMFault_Translation; - goto do_fault; - case 1: /* 64k page. */ - phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); - xn =3D desc & (1 << 15); - *page_size =3D 0x10000; - break; - case 2: case 3: /* 4k page. */ - phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); - xn =3D desc & 1; - *page_size =3D 0x1000; - break; - default: - /* Never happens, but compiler isn't smart enough to tell. */ - abort(); - } - } - if (domain_prot =3D=3D 3) { - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - } else { - if (pxn && !regime_is_user(env, mmu_idx)) { - xn =3D 1; - } - if (xn && access_type =3D=3D MMU_INST_FETCH) { - fi->type =3D ARMFault_Permission; - goto do_fault; - } - - if (arm_feature(env, ARM_FEATURE_V6K) && - (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) { - /* The simplified model uses AP[0] as an access control bit. = */ - if ((ap & 1) =3D=3D 0) { - /* Access flag fault. */ - fi->type =3D ARMFault_AccessFlag; - goto do_fault; - } - *prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap >> 1); - } else { - *prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); - } - if (*prot && !xn) { - *prot |=3D PAGE_EXEC; - } - if (!(*prot & (1 << access_type))) { - /* Access permission fault. */ - fi->type =3D ARMFault_Permission; - goto do_fault; - } - } - if (ns) { - /* - * The NS bit will (as required by the architecture) have no effec= t if - * the CPU doesn't support TZ or this is a non-secure translation - * regime, because the attribute will already be non-secure. - */ - attrs->secure =3D false; - } - *phys_ptr =3D phys_addr; - return false; -do_fault: - fi->domain =3D domain; - fi->level =3D level; - return true; -} - -/* - * check_s2_mmu_setup - * @cpu: ARMCPU - * @is_aa64: True if the translation regime is in AArch64 state - * @startlevel: Suggested starting level - * @inputsize: Bitsize of IPAs - * @stride: Page-table stride (See the ARM ARM) - * - * Returns true if the suggested S2 translation parameters are OK and - * false otherwise. - */ -static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, - int inputsize, int stride) -{ - const int grainsize =3D stride + 3; - int startsizecheck; - - /* Negative levels are never allowed. */ - if (level < 0) { - return false; - } - - startsizecheck =3D inputsize - ((3 - level) * stride + grainsize); - if (startsizecheck < 1 || startsizecheck > stride + 4) { - return false; - } - - if (is_aa64) { - CPUARMState *env =3D &cpu->env; - unsigned int pamax =3D arm_pamax(cpu); - - switch (stride) { - case 13: /* 64KB Pages. */ - if (level =3D=3D 0 || (level =3D=3D 1 && pamax <=3D 42)) { - return false; - } - break; - case 11: /* 16KB Pages. */ - if (level =3D=3D 0 || (level =3D=3D 1 && pamax <=3D 40)) { - return false; - } - break; - case 9: /* 4KB Pages. */ - if (level =3D=3D 0 && pamax <=3D 42) { - return false; - } - break; - default: - g_assert_not_reached(); - } - - /* Inputsize checks. */ - if (inputsize > pamax && - (arm_el_is_aa64(env, 1) || inputsize > 40)) { - /* This is CONSTRAINED UNPREDICTABLE and we choose to fault. = */ - return false; - } - } else { - /* AArch32 only supports 4KB pages. Assert on that. */ - assert(stride =3D=3D 9); - - if (level =3D=3D 0) { - return false; - } - } - return true; -} - -/* - * Translate from the 4-bit stage 2 representation of - * memory attributes (without cache-allocation hints) to - * the 8-bit representation of the stage 1 MAIR registers - * (which includes allocation hints). - * - * ref: shared/translation/attrs/S2AttrDecode() - * .../S2ConvertAttrsHints() - */ -static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs) -{ - uint8_t hiattr =3D extract32(s2attrs, 2, 2); - uint8_t loattr =3D extract32(s2attrs, 0, 2); - uint8_t hihint =3D 0, lohint =3D 0; - - if (hiattr !=3D 0) { /* normal memory */ - if (arm_hcr_el2_eff(env) & HCR_CD) { /* cache disabled */ - hiattr =3D loattr =3D 1; /* non-cacheable */ - } else { - if (hiattr !=3D 1) { /* Write-through or write-back */ - hihint =3D 3; /* RW allocate */ - } - if (loattr !=3D 1) { /* Write-through or write-back */ - lohint =3D 3; /* RW allocate */ - } - } - } - - return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint; -} -#endif /* !CONFIG_USER_ONLY */ - -static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) -{ - if (regime_has_2_ranges(mmu_idx)) { - return extract64(tcr, 37, 2); - } else if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx= _Stage2_S) { - return 0; /* VTCR_EL2 */ - } else { - /* Replicate the single TBI bit so we always have 2 bits. */ - return extract32(tcr, 20, 1) * 3; - } -} - -static int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) -{ - if (regime_has_2_ranges(mmu_idx)) { - return extract64(tcr, 51, 2); - } else if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx= _Stage2_S) { - return 0; /* VTCR_EL2 */ - } else { - /* Replicate the single TBID bit so we always have 2 bits. */ - return extract32(tcr, 29, 1) * 3; - } -} - -static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx) -{ - if (regime_has_2_ranges(mmu_idx)) { - return extract64(tcr, 57, 2); - } else { - /* Replicate the single TCMA bit so we always have 2 bits. */ - return extract32(tcr, 30, 1) * 3; - } -} - -ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx, bool data) -{ - uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; - bool epd, hpd, using16k, using64k; - int select, tsz, tbi, max_tsz; - - if (!regime_has_2_ranges(mmu_idx)) { - select =3D 0; - tsz =3D extract32(tcr, 0, 6); - using64k =3D extract32(tcr, 14, 1); - using16k =3D extract32(tcr, 15, 1); - if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_St= age2_S) { - /* VTCR_EL2 */ - hpd =3D false; - } else { - hpd =3D extract32(tcr, 24, 1); - } - epd =3D false; - } else { - /* - * Bit 55 is always between the two regions, and is canonical for - * determining if address tagging is enabled. - */ - select =3D extract64(va, 55, 1); - if (!select) { - tsz =3D extract32(tcr, 0, 6); - epd =3D extract32(tcr, 7, 1); - using64k =3D extract32(tcr, 14, 1); - using16k =3D extract32(tcr, 15, 1); - hpd =3D extract64(tcr, 41, 1); - } else { - int tg =3D extract32(tcr, 30, 2); - using16k =3D tg =3D=3D 1; - using64k =3D tg =3D=3D 3; - tsz =3D extract32(tcr, 16, 6); - epd =3D extract32(tcr, 23, 1); - hpd =3D extract64(tcr, 42, 1); - } - } - - if (cpu_isar_feature(aa64_st, env_archcpu(env))) { - max_tsz =3D 48 - using64k; - } else { - max_tsz =3D 39; - } - - tsz =3D MIN(tsz, max_tsz); - tsz =3D MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ - - /* Present TBI as a composite with TBID. */ - tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); - if (!data) { - tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); - } - tbi =3D (tbi >> select) & 1; - - return (ARMVAParameters) { - .tsz =3D tsz, - .select =3D select, - .tbi =3D tbi, - .epd =3D epd, - .hpd =3D hpd, - .using16k =3D using16k, - .using64k =3D using64k, - }; -} - -#ifndef CONFIG_USER_ONLY -static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, - ARMMMUIdx mmu_idx) -{ - uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; - uint32_t el =3D regime_el(env, mmu_idx); - int select, tsz; - bool epd, hpd; - - assert(mmu_idx !=3D ARMMMUIdx_Stage2_S); - - if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { - /* VTCR */ - bool sext =3D extract32(tcr, 4, 1); - bool sign =3D extract32(tcr, 3, 1); - - /* - * If the sign-extend bit is not the same as t0sz[3], the result - * is unpredictable. Flag this as a guest error. - */ - if (sign !=3D sext) { - qemu_log_mask(LOG_GUEST_ERROR, - "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n"); - } - tsz =3D sextract32(tcr, 0, 4) + 8; - select =3D 0; - hpd =3D false; - epd =3D false; - } else if (el =3D=3D 2) { - /* HTCR */ - tsz =3D extract32(tcr, 0, 3); - select =3D 0; - hpd =3D extract64(tcr, 24, 1); - epd =3D false; - } else { - int t0sz =3D extract32(tcr, 0, 3); - int t1sz =3D extract32(tcr, 16, 3); - - if (t1sz =3D=3D 0) { - select =3D va > (0xffffffffu >> t0sz); - } else { - /* Note that we will detect errors later. */ - select =3D va >=3D ~(0xffffffffu >> t1sz); - } - if (!select) { - tsz =3D t0sz; - epd =3D extract32(tcr, 7, 1); - hpd =3D extract64(tcr, 41, 1); - } else { - tsz =3D t1sz; - epd =3D extract32(tcr, 23, 1); - hpd =3D extract64(tcr, 42, 1); - } - /* For aarch32, hpd0 is not enabled without t2e as well. */ - hpd &=3D extract32(tcr, 6, 1); - } - - return (ARMVAParameters) { - .tsz =3D tsz, - .select =3D select, - .epd =3D epd, - .hpd =3D hpd, - }; -} - -/** - * get_phys_addr_lpae: perform one stage of page table walk, LPAE format - * - * Returns false if the translation was successful. Otherwise, phys_ptr, a= ttrs, - * prot and page_size may not be filled in, and the populated fsr value pr= ovides - * information on why the translation aborted, in the format of a long-for= mat - * DFSR/IFSR fault register, with the following caveats: - * * the WnR bit is never set (the caller must do this). - * - * @env: CPUARMState - * @address: virtual address to get physical address for - * @access_type: MMU_DATA_LOAD, MMU_DATA_STORE or MMU_INST_FETCH - * @mmu_idx: MMU index indicating required translation regime - * @s1_is_el0: if @mmu_idx is ARMMMUIdx_Stage2 (so this is a stage 2 page = table - * walk), must be true if this is stage 2 of a stage 1+2 walk = for an - * EL0 access). If @mmu_idx is anything else, @s1_is_el0 is ig= nored. - * @phys_ptr: set to the physical address corresponding to the virtual add= ress - * @attrs: set to the memory transaction attributes to use - * @prot: set to the permissions for the page containing phys_ptr - * @page_size_ptr: set to the size of the page containing phys_ptr - * @fi: set to fault info if the translation fails - * @cacheattrs: (if non-NULL) set to the cacheability/shareability attribu= tes - */ -static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address, - MMUAccessType access_type, ARMMMUIdx mmu_id= x, - bool s1_is_el0, - hwaddr *phys_ptr, MemTxAttrs *txattrs, int = *prot, - target_ulong *page_size_ptr, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheat= trs) -{ - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); - /* Read an LPAE long-descriptor translation table. */ - ARMFaultType fault_type =3D ARMFault_Translation; - uint32_t level; - ARMVAParameters param; - uint64_t ttbr; - hwaddr descaddr, indexmask, indexmask_grainsize; - uint32_t tableattrs; - target_ulong page_size; - uint32_t attrs; - int32_t stride; - int addrsize, inputsize; - TCR *tcr =3D regime_tcr(env, mmu_idx); - int ap, ns, xn, pxn; - uint32_t el =3D regime_el(env, mmu_idx); - uint64_t descaddrmask; - bool aarch64 =3D arm_el_is_aa64(env, el); - bool guarded =3D false; - - /* TODO: This code does not support shareability levels. */ - if (aarch64) { - param =3D aa64_va_parameters(env, address, mmu_idx, - access_type !=3D MMU_INST_FETCH); - level =3D 0; - addrsize =3D 64 - 8 * param.tbi; - inputsize =3D 64 - param.tsz; - } else { - param =3D aa32_va_parameters(env, address, mmu_idx); - level =3D 1; - addrsize =3D (mmu_idx =3D=3D ARMMMUIdx_Stage2 ? 40 : 32); - inputsize =3D addrsize - param.tsz; - } - - /* - * We determined the region when collecting the parameters, but we - * have not yet validated that the address is valid for the region. - * Extract the top bits and verify that they all match select. - * - * For aa32, if inputsize =3D=3D addrsize, then we have selected the - * region by exclusion in aa32_va_parameters and there is no more - * validation to do here. - */ - if (inputsize < addrsize) { - target_ulong top_bits =3D sextract64(address, inputsize, - addrsize - inputsize); - if (-top_bits !=3D param.select) { - /* The gap between the two regions is a Translation fault */ - fault_type =3D ARMFault_Translation; - goto do_fault; - } - } - - if (param.using64k) { - stride =3D 13; - } else if (param.using16k) { - stride =3D 11; - } else { - stride =3D 9; - } - - /* - * Note that QEMU ignores shareability and cacheability attributes, - * so we don't need to do anything with the SH, ORGN, IRGN fields - * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the - * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently - * implement any ASID-like capability so we can ignore it (instead - * we will always flush the TLB any time the ASID is changed). - */ - ttbr =3D regime_ttbr(env, mmu_idx, param.select); - - /* - * Here we should have set up all the parameters for the translation: - * inputsize, ttbr, epd, stride, tbi - */ - - if (param.epd) { - /* - * Translation table walk disabled =3D> Translation fault on TLB m= iss - * Note: This is always 0 on 64-bit EL2 and EL3. - */ - goto do_fault; - } - - if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2_S) { - /* - * The starting level depends on the virtual address size (which c= an - * be up to 48 bits) and the translation granule size. It indicates - * the number of strides (stride bits at a time) needed to - * consume the bits of the input address. In the pseudocode this i= s: - * level =3D 4 - RoundUp((inputsize - grainsize) / stride) - * where their 'inputsize' is our 'inputsize', 'grainsize' is - * our 'stride + 3' and 'stride' is our 'stride'. - * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifyin= g: - * =3D 4 - (inputsize - stride - 3 + stride - 1) / stride - * =3D 4 - (inputsize - 4) / stride; - */ - level =3D 4 - (inputsize - 4) / stride; - } else { - /* - * For stage 2 translations the starting level is specified by the - * VTCR_EL2.SL0 field (whose interpretation depends on the page si= ze) - */ - uint32_t sl0 =3D extract32(tcr->raw_tcr, 6, 2); - uint32_t startlevel; - bool ok; - - if (!aarch64 || stride =3D=3D 9) { - /* AArch32 or 4KB pages */ - startlevel =3D 2 - sl0; - - if (cpu_isar_feature(aa64_st, cpu)) { - startlevel &=3D 3; - } - } else { - /* 16KB or 64KB pages */ - startlevel =3D 3 - sl0; - } - - /* Check that the starting level is valid. */ - ok =3D check_s2_mmu_setup(cpu, aarch64, startlevel, - inputsize, stride); - if (!ok) { - fault_type =3D ARMFault_Translation; - goto do_fault; - } - level =3D startlevel; - } - - indexmask_grainsize =3D (1ULL << (stride + 3)) - 1; - indexmask =3D (1ULL << (inputsize - (stride * (4 - level)))) - 1; - - /* Now we can extract the actual base address from the TTBR */ - descaddr =3D extract64(ttbr, 0, 48); - /* - * We rely on this masking to clear the RES0 bits at the bottom of the= TTBR - * and also to mask out CnP (bit 0) which could validly be non-zero. - */ - descaddr &=3D ~indexmask; - - /* - * The address field in the descriptor goes up to bit 39 for ARMv7 - * but up to bit 47 for ARMv8, but we use the descaddrmask - * up to bit 39 for AArch32, because we don't need other bits in that = case - * to construct next descriptor address (anyway they should be all zer= oes). - */ - descaddrmask =3D ((1ull << (aarch64 ? 48 : 40)) - 1) & - ~indexmask_grainsize; - - /* - * Secure accesses start with the page table in secure memory and - * can be downgraded to non-secure at any step. Non-secure accesses - * remain non-secure. We implement this by just ORing in the NSTable/NS - * bits at each step. - */ - tableattrs =3D regime_is_secure(env, mmu_idx) ? 0 : (1 << 4); - for (;;) { - uint64_t descriptor; - bool nstable; - - descaddr |=3D (address >> (stride * (4 - level))) & indexmask; - descaddr &=3D ~7ULL; - nstable =3D extract32(tableattrs, 4, 1); - descriptor =3D arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fi); - if (fi->type !=3D ARMFault_None) { - goto do_fault; - } - - if (!(descriptor & 1) || - (!(descriptor & 2) && (level =3D=3D 3))) { - /* Invalid, or the Reserved level 3 encoding */ - goto do_fault; - } - descaddr =3D descriptor & descaddrmask; - - if ((descriptor & 2) && (level < 3)) { - /* - * Table entry. The top five bits are attributes which may - * propagate down through lower levels of the table (and - * which are all arranged so that 0 means "no effect", so - * we can gather them up by ORing in the bits at each level). - */ - tableattrs |=3D extract64(descriptor, 59, 5); - level++; - indexmask =3D indexmask_grainsize; - continue; - } - /* - * Block entry at level 1 or 2, or page entry at level 3. - * These are basically the same thing, although the number - * of bits we pull in from the vaddr varies. - */ - page_size =3D (1ULL << ((stride * (4 - level)) + 3)); - descaddr |=3D (address & (page_size - 1)); - /* Extract attributes from the descriptor */ - attrs =3D extract64(descriptor, 2, 10) - | (extract64(descriptor, 52, 12) << 10); - - if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_St= age2_S) { - /* Stage 2 table descriptors do not include any attribute fiel= ds */ - break; - } - /* Merge in attributes from table descriptors */ - attrs |=3D nstable << 3; /* NS */ - guarded =3D extract64(descriptor, 50, 1); /* GP */ - if (param.hpd) { - /* HPD disables all the table attributes except NSTable. */ - break; - } - attrs |=3D extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ - /* - * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] =3D= =3D 1 - * means "force PL1 access only", which means forcing AP[1] to 0. - */ - attrs &=3D ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] =3D> = AP[1] */ - attrs |=3D extract32(tableattrs, 3, 1) << 5; /* APT[1] =3D> A= P[2] */ - break; - } - /* - * Here descaddr is the final physical address, - * and attributes are all in attrs. - */ - fault_type =3D ARMFault_AccessFlag; - if ((attrs & (1 << 8)) =3D=3D 0) { - /* Access flag */ - goto do_fault; - } - - ap =3D extract32(attrs, 4, 2); - - if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { - ns =3D mmu_idx =3D=3D ARMMMUIdx_Stage2; - xn =3D extract32(attrs, 11, 2); - *prot =3D get_S2prot(env, ap, xn, s1_is_el0); - } else { - ns =3D extract32(attrs, 3, 1); - xn =3D extract32(attrs, 12, 1); - pxn =3D extract32(attrs, 11, 1); - *prot =3D get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn); - } - - fault_type =3D ARMFault_Permission; - if (!(*prot & (1 << access_type))) { - goto do_fault; - } - - if (ns) { - /* - * The NS bit will (as required by the architecture) have no effec= t if - * the CPU doesn't support TZ or this is a non-secure translation - * regime, because the attribute will already be non-secure. - */ - txattrs->secure =3D false; - } - /* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB.= */ - if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) { - arm_tlb_bti_gp(txattrs) =3D true; - } - - if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { - cacheattrs->attrs =3D convert_stage2_attrs(env, extract32(attrs, 0= , 4)); - } else { - /* Index into MAIR registers for cache attributes */ - uint8_t attrindx =3D extract32(attrs, 0, 3); - uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; - assert(attrindx <=3D 7); - cacheattrs->attrs =3D extract64(mair, attrindx * 8, 8); - } - cacheattrs->shareability =3D extract32(attrs, 6, 2); - - *phys_ptr =3D descaddr; - *page_size_ptr =3D page_size; - return false; - -do_fault: - fi->type =3D fault_type; - fi->level =3D level; - /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */ - fi->stage2 =3D fi->s1ptw || (mmu_idx =3D=3D ARMMMUIdx_Stage2 || - mmu_idx =3D=3D ARMMMUIdx_Stage2_S); - fi->s1ns =3D mmu_idx =3D=3D ARMMMUIdx_Stage2; - return true; -} - -static inline void get_phys_addr_pmsav7_default(CPUARMState *env, - ARMMMUIdx mmu_idx, - int32_t address, int *prot) -{ - if (!arm_feature(env, ARM_FEATURE_M)) { - *prot =3D PAGE_READ | PAGE_WRITE; - switch (address) { - case 0xF0000000 ... 0xFFFFFFFF: - if (regime_sctlr(env, mmu_idx) & SCTLR_V) { - /* hivecs execing is ok */ - *prot |=3D PAGE_EXEC; - } - break; - case 0x00000000 ... 0x7FFFFFFF: - *prot |=3D PAGE_EXEC; - break; - } - } else { - /* - * Default system address map for M profile cores. - * The architecture specifies which regions are execute-never; - * at the MPU level no other checks are defined. - */ - switch (address) { - case 0x00000000 ... 0x1fffffff: /* ROM */ - case 0x20000000 ... 0x3fffffff: /* SRAM */ - case 0x60000000 ... 0x7fffffff: /* RAM */ - case 0x80000000 ... 0x9fffffff: /* RAM */ - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - break; - case 0x40000000 ... 0x5fffffff: /* Peripheral */ - case 0xa0000000 ... 0xbfffffff: /* Device */ - case 0xc0000000 ... 0xdfffffff: /* Device */ - case 0xe0000000 ... 0xffffffff: /* System */ - *prot =3D PAGE_READ | PAGE_WRITE; - break; - default: - g_assert_not_reached(); - } - } -} - -static bool pmsav7_use_background_region(ARMCPU *cpu, - ARMMMUIdx mmu_idx, bool is_user) -{ - /* - * Return true if we should use the default memory map as a - * "background" region if there are no hits against any MPU regions. - */ - CPUARMState *env =3D &cpu->env; - - if (is_user) { - return false; - } - - if (arm_feature(env, ARM_FEATURE_M)) { - return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] - & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; - } else { - return regime_sctlr(env, mmu_idx) & SCTLR_BR; - } -} - -static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address) -{ - /* True if address is in the M profile PPB region 0xe0000000 - 0xe00ff= fff */ - return arm_feature(env, ARM_FEATURE_M) && - extract32(address, 20, 12) =3D=3D 0xe00; -} - -static inline bool m_is_system_region(CPUARMState *env, uint32_t address) -{ - /* - * True if address is in the M profile system region - * 0xe0000000 - 0xffffffff - */ - return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) = =3D=3D 0x7; -} - -static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_= idx, - hwaddr *phys_ptr, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi) -{ - ARMCPU *cpu =3D env_archcpu(env); - int n; - bool is_user =3D regime_is_user(env, mmu_idx); - - *phys_ptr =3D address; - *page_size =3D TARGET_PAGE_SIZE; - *prot =3D 0; - - if (regime_translation_disabled(env, mmu_idx) || - m_is_ppb_region(env, address)) { - /* - * MPU disabled or M profile PPB access: use default memory map. - * The other case which uses the default memory map in the - * v7M ARM ARM pseudocode is exception vector reads from the vector - * table. In QEMU those accesses are done in arm_v7m_load_vector(), - * which always does a direct read using address_space_ldl(), rath= er - * than going via this function, so we don't need to check that he= re. - */ - get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); - } else { /* MPU enabled */ - for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { - /* region search */ - uint32_t base =3D env->pmsav7.drbar[n]; - uint32_t rsize =3D extract32(env->pmsav7.drsr[n], 1, 5); - uint32_t rmask; - bool srdis =3D false; - - if (!(env->pmsav7.drsr[n] & 0x1)) { - continue; - } - - if (!rsize) { - qemu_log_mask(LOG_GUEST_ERROR, - "DRSR[%d]: Rsize field cannot be 0\n", n); - continue; - } - rsize++; - rmask =3D (1ull << rsize) - 1; - - if (base & rmask) { - qemu_log_mask(LOG_GUEST_ERROR, - "DRBAR[%d]: 0x%" PRIx32 " misaligned " - "to DRSR region size, mask =3D 0x%" PRIx32 "= \n", - n, base, rmask); - continue; - } - - if (address < base || address > base + rmask) { - /* - * Address not in this region. We must check whether the - * region covers addresses in the same page as our address. - * In that case we must not report a size that covers the - * whole page for a subsequent hit against a different MPU - * region or the background region, because it would resul= t in - * incorrect TLB hits for subsequent accesses to addresses= that - * are in this MPU region. - */ - if (ranges_overlap(base, rmask, - address & TARGET_PAGE_MASK, - TARGET_PAGE_SIZE)) { - *page_size =3D 1; - } - continue; - } - - /* Region matched */ - - if (rsize >=3D 8) { /* no subregions for regions < 256 bytes */ - int i, snd; - uint32_t srdis_mask; - - rsize -=3D 3; /* sub region size (power of 2) */ - snd =3D ((address - base) >> rsize) & 0x7; - srdis =3D extract32(env->pmsav7.drsr[n], snd + 8, 1); - - srdis_mask =3D srdis ? 0x3 : 0x0; - for (i =3D 2; i <=3D 8 && rsize < TARGET_PAGE_BITS; i *=3D= 2) { - /* - * This will check in groups of 2, 4 and then 8, wheth= er - * the subregion bits are consistent. rsize is increme= nted - * back up to give the region size, considering consis= tent - * adjacent subregions as one region. Stop testing if = rsize - * is already big enough for an entire QEMU page. - */ - int snd_rounded =3D snd & ~(i - 1); - uint32_t srdis_multi =3D extract32(env->pmsav7.drsr[n], - snd_rounded + 8, i); - if (srdis_mask ^ srdis_multi) { - break; - } - srdis_mask =3D (srdis_mask << i) | srdis_mask; - rsize++; - } - } - if (srdis) { - continue; - } - if (rsize < TARGET_PAGE_BITS) { - *page_size =3D 1 << rsize; - } - break; - } - - if (n =3D=3D -1) { /* no hits */ - if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { - /* background fault */ - fi->type =3D ARMFault_Background; - return true; - } - get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); - } else { /* a MPU hit! */ - uint32_t ap =3D extract32(env->pmsav7.dracr[n], 8, 3); - uint32_t xn =3D extract32(env->pmsav7.dracr[n], 12, 1); - - if (m_is_system_region(env, address)) { - /* System space is always execute never */ - xn =3D 1; - } - - if (is_user) { /* User mode AP bit decoding */ - switch (ap) { - case 0: - case 1: - case 5: - break; /* no access */ - case 3: - *prot |=3D PAGE_WRITE; - /* fall through */ - case 2: - case 6: - *prot |=3D PAGE_READ | PAGE_EXEC; - break; - case 7: - /* for v7M, same as 6; for R profile a reserved value = */ - if (arm_feature(env, ARM_FEATURE_M)) { - *prot |=3D PAGE_READ | PAGE_EXEC; - break; - } - /* fall through */ - default: - qemu_log_mask(LOG_GUEST_ERROR, - "DRACR[%d]: Bad value for AP bits: 0x%" - PRIx32 "\n", n, ap); - } - } else { /* Priv. mode AP bits decoding */ - switch (ap) { - case 0: - break; /* no access */ - case 1: - case 2: - case 3: - *prot |=3D PAGE_WRITE; - /* fall through */ - case 5: - case 6: - *prot |=3D PAGE_READ | PAGE_EXEC; - break; - case 7: - /* for v7M, same as 6; for R profile a reserved value = */ - if (arm_feature(env, ARM_FEATURE_M)) { - *prot |=3D PAGE_READ | PAGE_EXEC; - break; - } - /* fall through */ - default: - qemu_log_mask(LOG_GUEST_ERROR, - "DRACR[%d]: Bad value for AP bits: 0x%" - PRIx32 "\n", n, ap); - } - } - - /* execute never */ - if (xn) { - *prot &=3D ~PAGE_EXEC; - } - } - } - - fi->type =3D ARMFault_Permission; - fi->level =3D 1; - return !(*prot & (1 << access_type)); -} - -static bool v8m_is_sau_exempt(CPUARMState *env, - uint32_t address, MMUAccessType access_type) -{ - /* - * The architecture specifies that certain address ranges are - * exempt from v8M SAU/IDAU checks. - */ - return - (access_type =3D=3D MMU_INST_FETCH && m_is_system_region(env, addr= ess)) || - (address >=3D 0xe0000000 && address <=3D 0xe0002fff) || - (address >=3D 0xe000e000 && address <=3D 0xe000efff) || - (address >=3D 0xe002e000 && address <=3D 0xe002efff) || - (address >=3D 0xe0040000 && address <=3D 0xe0041fff) || - (address >=3D 0xe00ff000 && address <=3D 0xe00fffff); -} - -void v8m_security_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_i= dx, - V8M_SAttributes *sattrs) -{ - /* - * Look up the security attributes for this address. Compare the - * pseudocode SecurityCheck() function. - * We assume the caller has zero-initialized *sattrs. - */ - ARMCPU *cpu =3D env_archcpu(env); - int r; - bool idau_exempt =3D false, idau_ns =3D true, idau_nsc =3D true; - int idau_region =3D IREGION_NOTVALID; - uint32_t addr_page_base =3D address & TARGET_PAGE_MASK; - uint32_t addr_page_limit =3D addr_page_base + (TARGET_PAGE_SIZE - 1); - - if (cpu->idau) { - IDAUInterfaceClass *iic =3D IDAU_INTERFACE_GET_CLASS(cpu->idau); - IDAUInterface *ii =3D IDAU_INTERFACE(cpu->idau); - - iic->check(ii, address, &idau_region, &idau_exempt, &idau_ns, - &idau_nsc); - } - - if (access_type =3D=3D MMU_INST_FETCH && extract32(address, 28, 4) =3D= =3D 0xf) { - /* 0xf0000000..0xffffffff is always S for insn fetches */ - return; - } - - if (idau_exempt || v8m_is_sau_exempt(env, address, access_type)) { - sattrs->ns =3D !regime_is_secure(env, mmu_idx); - return; - } - - if (idau_region !=3D IREGION_NOTVALID) { - sattrs->irvalid =3D true; - sattrs->iregion =3D idau_region; - } - - switch (env->sau.ctrl & 3) { - case 0: /* SAU.ENABLE =3D=3D 0, SAU.ALLNS =3D=3D 0 */ - break; - case 2: /* SAU.ENABLE =3D=3D 0, SAU.ALLNS =3D=3D 1 */ - sattrs->ns =3D true; - break; - default: /* SAU.ENABLE =3D=3D 1 */ - for (r =3D 0; r < cpu->sau_sregion; r++) { - if (env->sau.rlar[r] & 1) { - uint32_t base =3D env->sau.rbar[r] & ~0x1f; - uint32_t limit =3D env->sau.rlar[r] | 0x1f; - - if (base <=3D address && limit >=3D address) { - if (base > addr_page_base || limit < addr_page_limit) { - sattrs->subpage =3D true; - } - if (sattrs->srvalid) { - /* - * If we hit in more than one region then we must = report - * as Secure, not NS-Callable, with no valid region - * number info. - */ - sattrs->ns =3D false; - sattrs->nsc =3D false; - sattrs->sregion =3D 0; - sattrs->srvalid =3D false; - break; - } else { - if (env->sau.rlar[r] & 2) { - sattrs->nsc =3D true; - } else { - sattrs->ns =3D true; - } - sattrs->srvalid =3D true; - sattrs->sregion =3D r; - } - } else { - /* - * Address not in this region. We must check whether t= he - * region covers addresses in the same page as our add= ress. - * In that case we must not report a size that covers = the - * whole page for a subsequent hit against a different= MPU - * region or the background region, because it would r= esult - * in incorrect TLB hits for subsequent accesses to - * addresses that are in this MPU region. - */ - if (limit >=3D base && - ranges_overlap(base, limit - base + 1, - addr_page_base, - TARGET_PAGE_SIZE)) { - sattrs->subpage =3D true; - } - } - } - } - break; - } - - /* - * The IDAU will override the SAU lookup results if it specifies - * higher security than the SAU does. - */ - if (!idau_ns) { - if (sattrs->ns || (!idau_nsc && sattrs->nsc)) { - sattrs->ns =3D false; - sattrs->nsc =3D idau_nsc; - } - } -} - -bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, bool *is_subpage, - ARMMMUFaultInfo *fi, uint32_t *mregion) -{ - /* - * Perform a PMSAv8 MPU lookup (without also doing the SAU check - * that a full phys-to-virt translation does). - * mregion is (if not NULL) set to the region number which matched, - * or -1 if no region number is returned (MPU off, address did not - * hit a region, address hit in multiple regions). - * We set is_subpage to true if the region hit doesn't cover the - * entire TARGET_PAGE the address is within. - */ - ARMCPU *cpu =3D env_archcpu(env); - bool is_user =3D regime_is_user(env, mmu_idx); - uint32_t secure =3D regime_is_secure(env, mmu_idx); - int n; - int matchregion =3D -1; - bool hit =3D false; - uint32_t addr_page_base =3D address & TARGET_PAGE_MASK; - uint32_t addr_page_limit =3D addr_page_base + (TARGET_PAGE_SIZE - 1); - - *is_subpage =3D false; - *phys_ptr =3D address; - *prot =3D 0; - if (mregion) { - *mregion =3D -1; - } - - /* - * Unlike the ARM ARM pseudocode, we don't need to check whether this - * was an exception vector read from the vector table (which is always - * done using the default system address map), because those accesses - * are done in arm_v7m_load_vector(), which always does a direct - * read using address_space_ldl(), rather than going via this function. - */ - if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ - hit =3D true; - } else if (m_is_ppb_region(env, address)) { - hit =3D true; - } else { - if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) { - hit =3D true; - } - - for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { - /* region search */ - /* - * Note that the base address is bits [31:5] from the register - * with bits [4:0] all zeroes, but the limit address is bits - * [31:5] from the register with bits [4:0] all ones. - */ - uint32_t base =3D env->pmsav8.rbar[secure][n] & ~0x1f; - uint32_t limit =3D env->pmsav8.rlar[secure][n] | 0x1f; - - if (!(env->pmsav8.rlar[secure][n] & 0x1)) { - /* Region disabled */ - continue; - } - - if (address < base || address > limit) { - /* - * Address not in this region. We must check whether the - * region covers addresses in the same page as our address. - * In that case we must not report a size that covers the - * whole page for a subsequent hit against a different MPU - * region or the background region, because it would resul= t in - * incorrect TLB hits for subsequent accesses to addresses= that - * are in this MPU region. - */ - if (limit >=3D base && - ranges_overlap(base, limit - base + 1, - addr_page_base, - TARGET_PAGE_SIZE)) { - *is_subpage =3D true; - } - continue; - } - - if (base > addr_page_base || limit < addr_page_limit) { - *is_subpage =3D true; - } - - if (matchregion !=3D -1) { - /* - * Multiple regions match -- always a failure (unlike - * PMSAv7 where highest-numbered-region wins) - */ - fi->type =3D ARMFault_Permission; - fi->level =3D 1; - return true; - } - - matchregion =3D n; - hit =3D true; - } - } - - if (!hit) { - /* background fault */ - fi->type =3D ARMFault_Background; - return true; - } - - if (matchregion =3D=3D -1) { - /* hit using the background region */ - get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); - } else { - uint32_t ap =3D extract32(env->pmsav8.rbar[secure][matchregion], 1= , 2); - uint32_t xn =3D extract32(env->pmsav8.rbar[secure][matchregion], 0= , 1); - bool pxn =3D false; - - if (arm_feature(env, ARM_FEATURE_V8_1M)) { - pxn =3D extract32(env->pmsav8.rlar[secure][matchregion], 4, 1); - } - - if (m_is_system_region(env, address)) { - /* System space is always execute never */ - xn =3D 1; - } - - *prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); - if (*prot && !xn && !(pxn && !is_user)) { - *prot |=3D PAGE_EXEC; - } - /* - * We don't need to look the attribute up in the MAIR0/MAIR1 - * registers because that only tells us about cacheability. - */ - if (mregion) { - *mregion =3D matchregion; - } - } - - fi->type =3D ARMFault_Permission; - fi->level =3D 1; - return !(*prot & (1 << access_type)); -} - - -static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_= idx, - hwaddr *phys_ptr, MemTxAttrs *txattrs, - int *prot, target_ulong *page_size, - ARMMMUFaultInfo *fi) -{ - uint32_t secure =3D regime_is_secure(env, mmu_idx); - V8M_SAttributes sattrs =3D {}; - bool ret; - bool mpu_is_subpage; - - if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - v8m_security_lookup(env, address, access_type, mmu_idx, &sattrs); - if (access_type =3D=3D MMU_INST_FETCH) { - /* - * Instruction fetches always use the MMU bank and the - * transaction attribute determined by the fetch address, - * regardless of CPU state. This is painful for QEMU - * to handle, because it would mean we need to encode - * into the mmu_idx not just the (user, negpri) information - * for the current security state but also that for the - * other security state, which would balloon the number - * of mmu_idx values needed alarmingly. - * Fortunately we can avoid this because it's not actually - * possible to arbitrarily execute code from memory with - * the wrong security attribute: it will always generate - * an exception of some kind or another, apart from the - * special case of an NS CPU executing an SG instruction - * in S&NSC memory. So we always just fail the translation - * here and sort things out in the exception handler - * (including possibly emulating an SG instruction). - */ - if (sattrs.ns !=3D !secure) { - if (sattrs.nsc) { - fi->type =3D ARMFault_QEMU_NSCExec; - } else { - fi->type =3D ARMFault_QEMU_SFault; - } - *page_size =3D sattrs.subpage ? 1 : TARGET_PAGE_SIZE; - *phys_ptr =3D address; - *prot =3D 0; - return true; - } - } else { - /* - * For data accesses we always use the MMU bank indicated - * by the current CPU state, but the security attributes - * might downgrade a secure access to nonsecure. - */ - if (sattrs.ns) { - txattrs->secure =3D false; - } else if (!secure) { - /* - * NS access to S memory must fault. - * Architecturally we should first check whether the - * MPU information for this address indicates that we - * are doing an unaligned access to Device memory, which - * should generate a UsageFault instead. QEMU does not - * currently check for that kind of unaligned access thoug= h. - * If we added it we would need to do so as a special case - * for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt(). - */ - fi->type =3D ARMFault_QEMU_SFault; - *page_size =3D sattrs.subpage ? 1 : TARGET_PAGE_SIZE; - *phys_ptr =3D address; - *prot =3D 0; - return true; - } - } - } - - ret =3D pmsav8_mpu_lookup(env, address, access_type, mmu_idx, phys_ptr, - txattrs, prot, &mpu_is_subpage, fi, NULL); - *page_size =3D sattrs.subpage || mpu_is_subpage ? 1 : TARGET_PAGE_SIZE; - return ret; -} - -static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_= idx, - hwaddr *phys_ptr, int *prot, - ARMMMUFaultInfo *fi) -{ - int n; - uint32_t mask; - uint32_t base; - bool is_user =3D regime_is_user(env, mmu_idx); - - if (regime_translation_disabled(env, mmu_idx)) { - /* MPU disabled. */ - *phys_ptr =3D address; - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return false; - } - - *phys_ptr =3D address; - for (n =3D 7; n >=3D 0; n--) { - base =3D env->cp15.c6_region[n]; - if ((base & 1) =3D=3D 0) { - continue; - } - mask =3D 1 << ((base >> 1) & 0x1f); - /* - * Keep this shift separate from the above to avoid an - * (undefined) << 32 - */ - mask =3D (mask << 1) - 1; - if (((base ^ address) & ~mask) =3D=3D 0) { - break; - } - } - if (n < 0) { - fi->type =3D ARMFault_Background; - return true; - } - - if (access_type =3D=3D MMU_INST_FETCH) { - mask =3D env->cp15.pmsav5_insn_ap; - } else { - mask =3D env->cp15.pmsav5_data_ap; - } - mask =3D (mask >> (n * 4)) & 0xf; - switch (mask) { - case 0: - fi->type =3D ARMFault_Permission; - fi->level =3D 1; - return true; - case 1: - if (is_user) { - fi->type =3D ARMFault_Permission; - fi->level =3D 1; - return true; - } - *prot =3D PAGE_READ | PAGE_WRITE; - break; - case 2: - *prot =3D PAGE_READ; - if (!is_user) { - *prot |=3D PAGE_WRITE; - } - break; - case 3: - *prot =3D PAGE_READ | PAGE_WRITE; - break; - case 5: - if (is_user) { - fi->type =3D ARMFault_Permission; - fi->level =3D 1; - return true; - } - *prot =3D PAGE_READ; - break; - case 6: - *prot =3D PAGE_READ; - break; - default: - /* Bad permission. */ - fi->type =3D ARMFault_Permission; - fi->level =3D 1; - return true; - } - *prot |=3D PAGE_EXEC; - return false; -} - -/* - * Combine either inner or outer cacheability attributes for normal - * memory, according to table D4-42 and pseudocode procedure - * CombineS1S2AttrHints() of ARM DDI 0487B.b (the ARMv8 ARM). - * - * NB: only stage 1 includes allocation hints (RW bits), leading to - * some asymmetry. - */ -static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2) -{ - if (s1 =3D=3D 4 || s2 =3D=3D 4) { - /* non-cacheable has precedence */ - return 4; - } else if (extract32(s1, 2, 2) =3D=3D 0 || extract32(s1, 2, 2) =3D=3D = 2) { - /* stage 1 write-through takes precedence */ - return s1; - } else if (extract32(s2, 2, 2) =3D=3D 2) { - /* - * stage 2 write-through takes precedence, but the allocation hint - * is still taken from stage 1 - */ - return (2 << 2) | extract32(s1, 0, 2); - } else { /* write-back */ - return s1; - } -} - -/* - * Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 - * and CombineS1S2Desc() - * - * @s1: Attributes from stage 1 walk - * @s2: Attributes from stage 2 walk - */ -static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) -{ - uint8_t s1lo, s2lo, s1hi, s2hi; - ARMCacheAttrs ret; - bool tagged =3D false; - - if (s1.attrs =3D=3D 0xf0) { - tagged =3D true; - s1.attrs =3D 0xff; - } - - s1lo =3D extract32(s1.attrs, 0, 4); - s2lo =3D extract32(s2.attrs, 0, 4); - s1hi =3D extract32(s1.attrs, 4, 4); - s2hi =3D extract32(s2.attrs, 4, 4); - - /* Combine shareability attributes (table D4-43) */ - if (s1.shareability =3D=3D 2 || s2.shareability =3D=3D 2) { - /* if either are outer-shareable, the result is outer-shareable */ - ret.shareability =3D 2; - } else if (s1.shareability =3D=3D 3 || s2.shareability =3D=3D 3) { - /* if either are inner-shareable, the result is inner-shareable */ - ret.shareability =3D 3; - } else { - /* both non-shareable */ - ret.shareability =3D 0; - } - - /* Combine memory type and cacheability attributes */ - if (s1hi =3D=3D 0 || s2hi =3D=3D 0) { - /* Device has precedence over normal */ - if (s1lo =3D=3D 0 || s2lo =3D=3D 0) { - /* nGnRnE has precedence over anything */ - ret.attrs =3D 0; - } else if (s1lo =3D=3D 4 || s2lo =3D=3D 4) { - /* non-Reordering has precedence over Reordering */ - ret.attrs =3D 4; /* nGnRE */ - } else if (s1lo =3D=3D 8 || s2lo =3D=3D 8) { - /* non-Gathering has precedence over Gathering */ - ret.attrs =3D 8; /* nGRE */ - } else { - ret.attrs =3D 0xc; /* GRE */ - } - - /* - * Any location for which the resultant memory type is any - * type of Device memory is always treated as Outer Shareable. - */ - ret.shareability =3D 2; - } else { /* Normal memory */ - /* Outer/inner cacheability combine independently */ - ret.attrs =3D combine_cacheattr_nibble(s1hi, s2hi) << 4 - | combine_cacheattr_nibble(s1lo, s2lo); - - if (ret.attrs =3D=3D 0x44) { - /* - * Any location for which the resultant memory type is Normal - * Inner Non-cacheable, Outer Non-cacheable is always treated - * as Outer Shareable. - */ - ret.shareability =3D 2; - } - } - - /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */ - if (tagged && ret.attrs =3D=3D 0xff) { - ret.attrs =3D 0xf0; - } - - return ret; -} - - -/* - * get_phys_addr - get the physical address for this virtual address - * - * Find the physical address corresponding to the given virtual address, - * by doing a translation table walk on MMU based systems or using the - * MPU state on MPU based systems. - * - * Returns false if the translation was successful. Otherwise, phys_ptr, a= ttrs, - * prot and page_size may not be filled in, and the populated fsr value pr= ovides - * information on why the translation aborted, in the format of a - * DFSR/IFSR fault register, with the following caveats: - * * we honour the short vs long DFSR format differences. - * * the WnR bit is never set (the caller must do this). - * * for PSMAv5 based systems we don't bother to return a full FSR format - * value. - * - * @env: CPUARMState - * @address: virtual address to get physical address for - * @access_type: 0 for read, 1 for write, 2 for execute - * @mmu_idx: MMU index indicating required translation regime - * @phys_ptr: set to the physical address corresponding to the virtual add= ress - * @attrs: set to the memory transaction attributes to use - * @prot: set to the permissions for the page containing phys_ptr - * @page_size: set to the size of the page containing phys_ptr - * @fi: set to fault info if the translation fails - * @cacheattrs: (if non-NULL) set to the cacheability/shareability attribu= tes - */ -bool get_phys_addr(CPUARMState *env, target_ulong address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs) -{ - ARMMMUIdx s1_mmu_idx =3D stage_1_mmu_idx(mmu_idx); - - if (mmu_idx !=3D s1_mmu_idx) { - /* - * Call ourselves recursively to do the stage 1 and then stage 2 - * translations if mmu_idx is a two-stage regime. - */ - if (arm_feature(env, ARM_FEATURE_EL2)) { - hwaddr ipa; - int s2_prot; - int ret; - ARMCacheAttrs cacheattrs2 =3D {}; - ARMMMUIdx s2_mmu_idx; - bool is_el0; - - ret =3D get_phys_addr(env, address, access_type, s1_mmu_idx, &= ipa, - attrs, prot, page_size, fi, cacheattrs); - - /* If S1 fails or S2 is disabled, return early. */ - if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2))= { - *phys_ptr =3D ipa; - return ret; - } - - s2_mmu_idx =3D attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_= Stage2; - is_el0 =3D mmu_idx =3D=3D ARMMMUIdx_E10_0 || mmu_idx =3D=3D AR= MMMUIdx_SE10_0; - - /* S1 is done. Now do S2 translation. */ - ret =3D get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx, = is_el0, - phys_ptr, attrs, &s2_prot, - page_size, fi, &cacheattrs2); - fi->s2addr =3D ipa; - /* Combine the S1 and S2 perms. */ - *prot &=3D s2_prot; - - /* If S2 fails, return early. */ - if (ret) { - return ret; - } - - /* Combine the S1 and S2 cache attributes. */ - if (arm_hcr_el2_eff(env) & HCR_DC) { - /* - * HCR.DC forces the first stage attributes to - * Normal Non-Shareable, - * Inner Write-Back Read-Allocate Write-Allocate, - * Outer Write-Back Read-Allocate Write-Allocate. - * Do not overwrite Tagged within attrs. - */ - if (cacheattrs->attrs !=3D 0xf0) { - cacheattrs->attrs =3D 0xff; - } - cacheattrs->shareability =3D 0; - } - *cacheattrs =3D combine_cacheattrs(*cacheattrs, cacheattrs2); - - /* Check if IPA translates to secure or non-secure PA space. */ - if (arm_is_secure_below_el3(env)) { - if (attrs->secure) { - attrs->secure =3D - !(env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_= SW)); - } else { - attrs->secure =3D - !((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA | VTCR_N= SW)) - || (env->cp15.vstcr_el2.raw_tcr & VSTCR_SA)); - } - } - return 0; - } else { - /* - * For non-EL2 CPUs a stage1+stage2 translation is just stage = 1. - */ - mmu_idx =3D stage_1_mmu_idx(mmu_idx); - } - } - - /* - * The page table entries may downgrade secure to non-secure, but - * cannot upgrade an non-secure translation regime's attributes - * to secure. - */ - attrs->secure =3D regime_is_secure(env, mmu_idx); - attrs->user =3D regime_is_user(env, mmu_idx); - - /* - * Fast Context Switch Extension. This doesn't exist at all in v8. - * In v7 and earlier it affects all stage 1 translations. - */ - if (address < 0x02000000 && mmu_idx !=3D ARMMMUIdx_Stage2 - && !arm_feature(env, ARM_FEATURE_V8)) { - if (regime_el(env, mmu_idx) =3D=3D 3) { - address +=3D env->cp15.fcseidr_s; - } else { - address +=3D env->cp15.fcseidr_ns; - } - } - - if (arm_feature(env, ARM_FEATURE_PMSA)) { - bool ret; - *page_size =3D TARGET_PAGE_SIZE; - - if (arm_feature(env, ARM_FEATURE_V8)) { - /* PMSAv8 */ - ret =3D get_phys_addr_pmsav8(env, address, access_type, mmu_id= x, - phys_ptr, attrs, prot, page_size, f= i); - } else if (arm_feature(env, ARM_FEATURE_V7)) { - /* PMSAv7 */ - ret =3D get_phys_addr_pmsav7(env, address, access_type, mmu_id= x, - phys_ptr, prot, page_size, fi); - } else { - /* Pre-v7 MPU */ - ret =3D get_phys_addr_pmsav5(env, address, access_type, mmu_id= x, - phys_ptr, prot, fi); - } - qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 - " mmu_idx %u -> %s (prot %c%c%c)\n", - access_type =3D=3D MMU_DATA_LOAD ? "reading" : - (access_type =3D=3D MMU_DATA_STORE ? "writing" : "ex= ecute"), - (uint32_t)address, mmu_idx, - ret ? "Miss" : "Hit", - *prot & PAGE_READ ? 'r' : '-', - *prot & PAGE_WRITE ? 'w' : '-', - *prot & PAGE_EXEC ? 'x' : '-'); - - return ret; - } - - /* Definitely a real MMU, not an MPU */ - - if (regime_translation_disabled(env, mmu_idx)) { - uint64_t hcr; - uint8_t memattr; - - /* - * MMU disabled. S1 addresses within aa64 translation regimes are - * still checked for bounds -- see AArch64.TranslateAddressS1Off. - */ - if (mmu_idx !=3D ARMMMUIdx_Stage2 && mmu_idx !=3D ARMMMUIdx_Stage2= _S) { - int r_el =3D regime_el(env, mmu_idx); - if (arm_el_is_aa64(env, r_el)) { - int pamax =3D arm_pamax(env_archcpu(env)); - uint64_t tcr =3D env->cp15.tcr_el[r_el].raw_tcr; - int addrtop, tbi; - - tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); - if (access_type =3D=3D MMU_INST_FETCH) { - tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); - } - tbi =3D (tbi >> extract64(address, 55, 1)) & 1; - addrtop =3D (tbi ? 55 : 63); - - if (extract64(address, pamax, addrtop - pamax + 1) !=3D 0)= { - fi->type =3D ARMFault_AddressSize; - fi->level =3D 0; - fi->stage2 =3D false; - return 1; - } - - /* - * When TBI is disabled, we've just validated that all of = the - * bits above PAMax are zero, so logically we only need to - * clear the top byte for TBI. But it's clearer to follow - * the pseudocode set of addrdesc.paddress. - */ - address =3D extract64(address, 0, 52); - } - } - *phys_ptr =3D address; - *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; - *page_size =3D TARGET_PAGE_SIZE; - - /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ - hcr =3D arm_hcr_el2_eff(env); - cacheattrs->shareability =3D 0; - if (hcr & HCR_DC) { - if (hcr & HCR_DCT) { - memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ - } else { - memattr =3D 0xff; /* Normal, WB, RWA */ - } - } else if (access_type =3D=3D MMU_INST_FETCH) { - if (regime_sctlr(env, mmu_idx) & SCTLR_I) { - memattr =3D 0xee; /* Normal, WT, RA, NT */ - } else { - memattr =3D 0x44; /* Normal, NC, No */ - } - cacheattrs->shareability =3D 2; /* outer sharable */ - } else { - memattr =3D 0x00; /* Device, nGnRnE */ - } - cacheattrs->attrs =3D memattr; - return 0; - } - - if (regime_using_lpae_format(env, mmu_idx)) { - return get_phys_addr_lpae(env, address, access_type, mmu_idx, fals= e, - phys_ptr, attrs, prot, page_size, - fi, cacheattrs); - } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) { - return get_phys_addr_v6(env, address, access_type, mmu_idx, - phys_ptr, attrs, prot, page_size, fi); - } else { - return get_phys_addr_v5(env, address, access_type, mmu_idx, - phys_ptr, prot, page_size, fi); - } -} - -hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, - MemTxAttrs *attrs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - hwaddr phys_addr; - target_ulong page_size; - int prot; - bool ret; - ARMMMUFaultInfo fi =3D {}; - ARMMMUIdx mmu_idx =3D arm_mmu_idx(env); - ARMCacheAttrs cacheattrs =3D {}; - - *attrs =3D (MemTxAttrs) {}; - - ret =3D get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &phys_addr, - attrs, &prot, &page_size, &fi, &cacheattrs); - - if (ret) { - return -1; - } - return phys_addr; -} - -#endif - /* Note that signed overflow is undefined in C. The following routines are careful to use unsigned types where modulo arithmetic is required. Failure to do so _will_ break on newer gcc. */ diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index cd6df18150..11021d1a2f 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -25,7 +25,7 @@ #include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "qemu/xxhash.h" - +#include "cpu-mmu.h" =20 static uint64_t pac_cell_shuffle(uint64_t i) { diff --git a/target/arm/tcg/sysemu/m_helper.c b/target/arm/tcg/sysemu/m_hel= per.c index 77c9fd0b6e..59787c5650 100644 --- a/target/arm/tcg/sysemu/m_helper.c +++ b/target/arm/tcg/sysemu/m_helper.c @@ -13,7 +13,7 @@ #include "qemu/main-loop.h" #include "exec/exec-all.h" #include "semihosting/common-semi.h" - +#include "cpu-mmu.h" #include "tcg/m_helper.h" =20 /* diff --git a/target/arm/tcg/sysemu/tlb_helper.c b/target/arm/tcg/sysemu/tlb= _helper.c index 586f602989..1290612ed9 100644 --- a/target/arm/tcg/sysemu/tlb_helper.c +++ b/target/arm/tcg/sysemu/tlb_helper.c @@ -9,6 +9,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "cpu-mmu.h" #include "tcg/tlb_helper.h" =20 /* diff --git a/target/arm/meson.build b/target/arm/meson.build index b75392e3e9..3e7cea7604 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,6 +1,7 @@ arm_ss =3D ss.source_set() arm_ss.add(files( 'cpu.c', + 'cpu-mmu.c', 'gdbstub.c', 'cpu_tcg.c', )) @@ -17,6 +18,7 @@ arm_softmmu_ss =3D ss.source_set() arm_softmmu_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', + 'cpu-mmu-sysemu.c', 'cpu-sysemu.c', 'machine.c', 'monitor.c', --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622827007; cv=none; d=zohomail.com; s=zohoarc; b=hG7E3KeRhwnPiChMx7gqnZQz9T6dhbE037WWUwSgfpOdcelCsjG+PvH/K5qP4/6KdO+IqTdgt+OGTwXvlq+cz00VVXi3VX+SVgd/xrL+fL0Io37OD4X/EfQVIw1037CWbwAhqpTOAM65gNpKhPd+MRIA9PBE4csH1v3zzeS4FOU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622827007; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sc/6uajFSwSpb53JElt22XiaxKOlvTHLpMwHaEEN5+g=; b=O1SYyUdtSuKEYCdS/kHhD5S8FAwMwRQii+euoZKYgZq/+WeMi9bkI6PS1cyhWcup5QBga0UZy8wADeYz69hwWD6QDhMcJcef1h+tyE2Q6jLMQMlTEsHpX+OvGX4vtx96ovqmc+G6TBgDqNnXzSY1TYhOcvtXz4S3I1UJvPfJJgA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622827007202363.20299510389714; Fri, 4 Jun 2021 10:16:47 -0700 (PDT) Received: from localhost ([::1]:36226 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDR8-0007gP-8L for importer@patchew.org; Fri, 04 Jun 2021 13:16:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33788) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCku-0000Bq-Fx for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:08 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:50688) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCke-0002Cm-FB for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:08 -0400 Received: by mail-wm1-x32f.google.com with SMTP id f20so1516808wmg.0 for ; Fri, 04 Jun 2021 09:32:52 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id j18sm7153953wrw.30.2021.06.04.09.32.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:43 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A03961FFB1; Fri, 4 Jun 2021 16:53:15 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sc/6uajFSwSpb53JElt22XiaxKOlvTHLpMwHaEEN5+g=; b=t0vz8HfzwvE8bOXplCvnxf2Mgd1L9NoAhuG7EixVrTsr7QyMgUdVkXMNm5cDs+jzQq jLW654pamsz8Ir3ofA8FE1llovuOHNjcrXOhdQWe08TeNvWesi7VU9btFfBqRuUIOc6W OMQq/j3bs9yyx6QdK6o+QhNQXJVE3LySa6WbOGMyYq2pClypi2wFaE3Rc9ESkEfOvt9d WwWG4P+x4V12w9WJRbE70uZHqS5zn+HWPfVy9T+eFvO5BWhgHKJTPe1GsSXJd2TnIOJ7 iraXuLyQbDcBCJ1RlxoUafh68SdBIDBJEuc+2zKFmeQvMpUvp/jECA1JKYPhoSNPCvLQ 3udQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sc/6uajFSwSpb53JElt22XiaxKOlvTHLpMwHaEEN5+g=; b=HfUWPgUZsuePH7fqGLHdRAp5v9PG5UcTq9JlANviaeAj/N6g79zLmTAy/0XWqofx+y 6bKq7DoaExPjxETm/k6zii6fvufbliEza/sUhlBbBfMp7ZJcN71eBBF+fFui/I4fPunJ urEttUKu2p+5ThRnsjNufbpf/jcRhJaWRBaZ+VzdrVoBZtbknzvrdxLy0aJOsDZ0Tu3H VR5RaDT322BBb+No3vsABIMsiLVPTwED3zs1j81ciLKmHlBuwSt9tuw9sZnN1pMu9vam HxRFwmFTliwxW34grur+db+IQm7HyJc6VqfqsRVw01oAbuJp4VAJPtLAavpKikVa5ZAD EQbg== X-Gm-Message-State: AOAM530PYXqKI5uUF+PHcXZKOrK0emkB7WkG4l0YGmIpdS+4opCrux4d ORdyLYpDo/ALkYCD6c7tDjX7wM6Rur9Mag== X-Google-Smtp-Source: ABdhPJwapkbpcjgjgv9A+xiJYk1Jr67WiIYtZqEPJ1YWX6XImfMHkwYleVZepI0LYmrgDKslu8AHPg== X-Received: by 2002:a1c:1d04:: with SMTP id d4mr4462577wmd.126.1622824370280; Fri, 04 Jun 2021 09:32:50 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 27/99] target/arm: fix style in preparation of new cpregs module Date: Fri, 4 Jun 2021 16:52:00 +0100 Message-Id: <20210604155312.15902-28-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana in preparation of the creation of a new cpregs module, fix the style for the to-be-exported code. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 54 ++++--- target/arm/tcg/helper.c | 310 ++++++++++++++++++++++++++-------------- 2 files changed, 239 insertions(+), 125 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f9ce70e607..af788c7801 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2709,14 +2709,16 @@ typedef struct ARMCPRegInfo ARMCPRegInfo; typedef enum CPAccessResult { /* Access is permitted */ CP_ACCESS_OK =3D 0, - /* Access fails due to a configurable trap or enable which would + /* + * Access fails due to a configurable trap or enable which would * result in a categorized exception syndrome giving information about * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or * PL1 if in EL0, otherwise to the current EL). */ CP_ACCESS_TRAP =3D 1, - /* Access fails and results in an exception syndrome 0x0 ("uncategoriz= ed"). + /* + * Access fails and results in an exception syndrome 0x0 ("uncategoriz= ed"). * Note that this is not a catch-all case -- the set of cases which may * result in this failure is specifically defined by the architecture. */ @@ -2727,14 +2729,16 @@ typedef enum CPAccessResult { /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ CP_ACCESS_TRAP_UNCATEGORIZED_EL2 =3D 5, CP_ACCESS_TRAP_UNCATEGORIZED_EL3 =3D 6, - /* Access fails and results in an exception syndrome for an FP access, + /* + * Access fails and results in an exception syndrome for an FP access, * trapped directly to EL2 or EL3 */ CP_ACCESS_TRAP_FP_EL2 =3D 7, CP_ACCESS_TRAP_FP_EL3 =3D 8, } CPAccessResult; =20 -/* Access functions for coprocessor registers. These cannot fail and +/* + * Access functions for coprocessor registers. These cannot fail and * may not raise exceptions. */ typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); @@ -2753,7 +2757,8 @@ typedef void CPResetFn(CPUARMState *env, const ARMCPR= egInfo *opaque); struct ARMCPRegInfo { /* Name of register (useful mainly for debugging, need not be unique) = */ const char *name; - /* Location of register: coprocessor number and (crn,crm,opc1,opc2) + /* + * Location of register: coprocessor number and (crn,crm,opc1,opc2) * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a * 'wildcard' field -- any value of that field in the MRC/MCR insn * will be decoded to this register. The register read and write @@ -2784,16 +2789,19 @@ struct ARMCPRegInfo { int access; /* Security state: ARM_CP_SECSTATE_* bits/values */ int secure; - /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when + /* + * The opaque pointer passed to define_arm_cp_regs_with_opaque() when * this register was defined: can be used to hand data through to the * register read/write functions, since they are passed the ARMCPRegIn= fo*. */ void *opaque; - /* Value of this register, if it is ARM_CP_CONST. Otherwise, if + /* + * Value of this register, if it is ARM_CP_CONST. Otherwise, if * fieldoffset is non-zero, the reset value of the register. */ uint64_t resetvalue; - /* Offset of the field in CPUARMState for this register. + /* + * Offset of the field in CPUARMState for this register. * * This is not needed if either: * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs @@ -2801,7 +2809,8 @@ struct ARMCPRegInfo { */ ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ =20 - /* Offsets of the secure and non-secure fields in CPUARMState for the + /* + * Offsets of the secure and non-secure fields in CPUARMState for the * register if it is banked. These fields are only used during the st= atic * registration of a register. During hashing the bank associated * with a given security state is copied to fieldoffset which is used = from @@ -2814,36 +2823,42 @@ struct ARMCPRegInfo { */ ptrdiff_t bank_fieldoffsets[2]; =20 - /* Function for making any access checks for this register in addition= to + /* + * Function for making any access checks for this register in addition= to * those specified by the 'access' permissions bits. If NULL, no extra * checks required. The access check is performed at runtime, not at * translate time. */ CPAccessFn *accessfn; - /* Function for handling reads of this register. If NULL, then reads + /* + * Function for handling reads of this register. If NULL, then reads * will be done by loading from the offset into CPUARMState specified * by fieldoffset. */ CPReadFn *readfn; - /* Function for handling writes of this register. If NULL, then writes + /* + * Function for handling writes of this register. If NULL, then writes * will be done by writing to the offset into CPUARMState specified * by fieldoffset. */ CPWriteFn *writefn; - /* Function for doing a "raw" read; used when we need to copy + /* + * Function for doing a "raw" read; used when we need to copy * coprocessor state to the kernel for KVM or out for * migration. This only needs to be provided if there is also a * readfn and it has side effects (for instance clear-on-read bits). */ CPReadFn *raw_readfn; - /* Function for doing a "raw" write; used when we need to copy KVM + /* + * Function for doing a "raw" write; used when we need to copy KVM * kernel coprocessor state into userspace, or for inbound * migration. This only needs to be provided if there is also a * writefn and it masks out "unwritable" bits or has write-one-to-clear * or similar behaviour. */ CPWriteFn *raw_writefn; - /* Function for resetting the register. If NULL, then reset will be do= ne + /* + * Function for resetting the register. If NULL, then reset will be do= ne * by writing resetvalue to the field specified in fieldoffset. If * fieldoffset is 0 then no reset will be done. */ @@ -2863,7 +2878,8 @@ struct ARMCPRegInfo { CPWriteFn *orig_writefn; }; =20 -/* Macros which are lvalues for the field in CPUARMState for the +/* + * Macros which are lvalues for the field in CPUARMState for the * ARMCPRegInfo *ri. */ #define CPREG_FIELD32(env, ri) \ @@ -2917,12 +2933,14 @@ void arm_cp_write_ignore(CPUARMState *env, const AR= MCPRegInfo *ri, /* CPReadFn that can be used for read-as-zero behaviour */ uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); =20 -/* CPResetFn that does nothing, for use if no reset is required even +/* + * CPResetFn that does nothing, for use if no reset is required even * if fieldoffset is non zero. */ void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); =20 -/* Return true if this reginfo struct's field in the cpu state struct +/* + * Return true if this reginfo struct's field in the cpu state struct * is 64 bits wide. */ static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index 7f818e5860..0f4ebcc46f 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -327,7 +327,8 @@ static int arm_gdb_set_svereg(CPUARMState *env, uint8_t= *buf, int reg) =20 static bool raw_accessors_invalid(const ARMCPRegInfo *ri) { - /* Return true if the regdef would cause an assertion if you called + /* + * Return true if the regdef would cause an assertion if you called * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a * program bug for it not to have the NO_RAW flag). * NB that returning false here doesn't necessarily mean that calling @@ -431,7 +432,7 @@ static void add_cpreg_to_list(gpointer key, gpointer op= aque) regidx =3D *(uint32_t *)key; ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); =20 - if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { + if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { cpu->cpreg_indexes[cpu->cpreg_array_len] =3D cpreg_to_kvm_id(regid= x); /* The value array need not be initialized at this point */ cpu->cpreg_array_len++; @@ -447,7 +448,7 @@ static void count_cpreg(gpointer key, gpointer opaque) regidx =3D *(uint32_t *)key; ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); =20 - if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { + if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { cpu->cpreg_array_len++; } } @@ -468,7 +469,8 @@ static gint cpreg_key_compare(gconstpointer a, gconstpo= inter b) =20 void init_cpreg_list(ARMCPU *cpu) { - /* Initialise the cpreg_tuples[] array based on the cp_regs hash. + /* + * Initialise the cpreg_tuples[] array based on the cp_regs hash. * Note that we require cpreg_tuples[] to be sorted by key ID. */ GList *keys; @@ -510,7 +512,8 @@ static CPAccessResult access_el3_aa32ns(CPUARMState *en= v, return CP_ACCESS_OK; } =20 -/* Some secure-only AArch32 registers trap to EL3 if used from +/* + * Some secure-only AArch32 registers trap to EL3 if used from * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). * Note that an access from Secure EL1 can only happen if EL3 is AArch64. * We assume that the .access field is set to PL1_RW. @@ -537,7 +540,8 @@ static uint64_t arm_mdcr_el2_eff(CPUARMState *env) return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0; } =20 -/* Check for traps to "powerdown debug" registers, which are controlled +/* + * Check for traps to "powerdown debug" registers, which are controlled * by MDCR.TDOSA */ static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -557,7 +561,8 @@ static CPAccessResult access_tdosa(CPUARMState *env, co= nst ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 -/* Check for traps to "debug ROM" registers, which are controlled +/* + * Check for traps to "debug ROM" registers, which are controlled * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. */ static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, @@ -577,7 +582,8 @@ static CPAccessResult access_tdra(CPUARMState *env, con= st ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 -/* Check for traps to general debug registers, which are controlled +/* + * Check for traps to general debug registers, which are controlled * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. */ static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, @@ -597,7 +603,8 @@ static CPAccessResult access_tda(CPUARMState *env, cons= t ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 -/* Check for traps to performance monitor registers, which are controlled +/* + * Check for traps to performance monitor registers, which are controlled * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. */ static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, @@ -671,7 +678,8 @@ static void fcse_write(CPUARMState *env, const ARMCPReg= Info *ri, uint64_t value) ARMCPU *cpu =3D env_archcpu(env); =20 if (raw_read(env, ri) !=3D value) { - /* Unlike real hardware the qemu TLB uses virtual addresses, + /* + * Unlike real hardware the qemu TLB uses virtual addresses, * not modified virtual addresses, so this causes a TLB flush. */ tlb_flush(CPU(cpu)); @@ -686,7 +694,8 @@ static void contextidr_write(CPUARMState *env, const AR= MCPRegInfo *ri, =20 if (raw_read(env, ri) !=3D value && !arm_feature(env, ARM_FEATURE_PMSA) && !extended_addresses_enabled(env)) { - /* For VMSA (when not using the LPAE long descriptor page table + /* + * For VMSA (when not using the LPAE long descriptor page table * format) this register includes the ASID, so do a TLB flush. * For PMSA it is purely a process ID and no action is needed. */ @@ -851,7 +860,8 @@ static void tlbimva_hyp_is_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, } =20 static const ARMCPRegInfo cp_reginfo[] =3D { - /* Define the secure and non-secure FCSE identifier CP registers + /* + * Define the secure and non-secure FCSE identifier CP registers * separately because there is no secure bank in V8 (no _EL3). This a= llows * the secure register to be properly reset and migrated. There is als= o no * v8 EL1 version of the register so the non-secure instance stands al= one. @@ -866,7 +876,8 @@ static const ARMCPRegInfo cp_reginfo[] =3D { .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_S, .fieldoffset =3D offsetof(CPUARMState, cp15.fcseidr_s), .resetvalue =3D 0, .writefn =3D fcse_write, .raw_writefn =3D raw_wri= te, }, - /* Define the secure and non-secure context identifier CP registers + /* + * Define the secure and non-secure context identifier CP registers * separately because there is no secure bank in V8 (no _EL3). This a= llows * the secure register to be properly reset and migrated. In the * non-secure case, the 32-bit register will have reset and migration @@ -888,7 +899,8 @@ static const ARMCPRegInfo cp_reginfo[] =3D { }; =20 static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { - /* NB: Some of these registers exist in v8 but with more precise + /* + * NB: Some of these registers exist in v8 but with more precise * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginf= o[]). */ /* MMU Domain access control / MPU write buffer control */ @@ -898,7 +910,8 @@ static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { .writefn =3D dacr_write, .raw_writefn =3D raw_write, .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dacr_s), offsetoflow32(CPUARMState, cp15.dacr_ns) } }, - /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. + /* + * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. * For v6 and v5, these mappings are overly broad. */ { .name =3D "TLB_LOCKDOWN", .cp =3D 15, .crn =3D 10, .crm =3D 0, @@ -917,7 +930,8 @@ static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { }; =20 static const ARMCPRegInfo not_v6_cp_reginfo[] =3D { - /* Not all pre-v6 cores implemented this WFI, so this is slightly + /* + * Not all pre-v6 cores implemented this WFI, so this is slightly * over-broad. */ { .name =3D "WFI_v5", .cp =3D 15, .crn =3D 7, .crm =3D 8, .opc1 =3D 0,= .opc2 =3D 2, @@ -926,12 +940,14 @@ static const ARMCPRegInfo not_v6_cp_reginfo[] =3D { }; =20 static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { - /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which + /* + * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which * is UNPREDICTABLE; we choose to NOP as most implementations do). */ { .name =3D "WFI_v6", .cp =3D 15, .crn =3D 7, .crm =3D 0, .opc1 =3D 0,= .opc2 =3D 4, .access =3D PL1_W, .type =3D ARM_CP_WFI }, - /* L1 cache lockdown. Not architectural in v6 and earlier but in pract= ice + /* + * L1 cache lockdown. Not architectural in v6 and earlier but in pract= ice * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM a= nd * OMAPCP will override this space. */ @@ -945,14 +961,16 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { { .name =3D "DUMMY", .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, = .opc2 =3D CP_ANY, .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, .resetvalue =3D 0 }, - /* We don't implement pre-v7 debug but most CPUs had at least a DBGDID= R; + /* + * We don't implement pre-v7 debug but most CPUs had at least a DBGDID= R; * implementing it as RAZ means the "debug architecture version" bits * will read as a reserved value, which should cause Linux to not try * to use the debug hardware. */ { .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, .access =3D PL0_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* MMU TLB control. Note that the wildcarding means we cover not just + /* + * MMU TLB control. Note that the wildcarding means we cover not just * the unified TLB ops but also the dside/iside/inner-shareable varian= ts. */ { .name =3D "TLBIALL", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, @@ -981,7 +999,8 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, =20 /* In ARMv8 most bits of CPACR_EL1 are RES0. */ if (!arm_feature(env, ARM_FEATURE_V8)) { - /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. + /* + * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. * TRCDIS [28] is RAZ/WI since we do not implement a trace macroce= ll. */ @@ -994,7 +1013,8 @@ static void cpacr_write(CPUARMState *env, const ARMCPR= egInfo *ri, value |=3D (1 << 31); } =20 - /* VFPv3 and upwards with NEON implement 32 double precision + /* + * VFPv3 and upwards with NEON implement 32 double precision * registers (D0-D31). */ if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { @@ -1036,7 +1056,8 @@ static uint64_t cpacr_read(CPUARMState *env, const AR= MCPRegInfo *ri) =20 static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) { - /* Call cpacr_write() so that we reset with the correct RAO bits set + /* + * Call cpacr_write() so that we reset with the correct RAO bits set * for our CPU features. */ cpacr_write(env, ri, 0); @@ -1076,7 +1097,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { { .name =3D "MVA_prefetch", .cp =3D 15, .crn =3D 7, .crm =3D 13, .opc1 =3D 0, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NOP }, - /* We need to break the TB after ISB to execute self-modifying code + /* + * We need to break the TB after ISB to execute self-modifying code * correctly and also to take any pending interrupts immediately. * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. */ @@ -1091,7 +1113,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ifar_s), offsetof(CPUARMState, cp15.ifar_ns) }, .resetvalue =3D 0, }, - /* Watchpoint Fault Address Register : should actually only be present + /* + * Watchpoint Fault Address Register : should actually only be present * for 1136, 1176, 11MPCore. */ { .name =3D "WFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 1, @@ -2492,7 +2515,8 @@ static const ARMCPRegInfo v6k_cp_reginfo[] =3D { static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInf= o *ri, bool isread) { - /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. + /* + * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. * Writable only at the highest implemented exception level. */ int el =3D arm_current_el(env); @@ -2651,7 +2675,8 @@ static CPAccessResult gt_stimer_access(CPUARMState *e= nv, const ARMCPRegInfo *ri, bool isread) { - /* The AArch64 register view of the secure physical timer is + /* + * The AArch64 register view of the secure physical timer is * always accessible from EL3, and configurably accessible from * Secure EL1. */ @@ -2686,7 +2711,8 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) ARMGenericTimer *gt =3D &cpu->env.cp15.c14_timer[timeridx]; =20 if (gt->ctl & 1) { - /* Timer enabled: calculate and set current ISTATUS, irq, and + /* + * Timer enabled: calculate and set current ISTATUS, irq, and * reset timer to when ISTATUS next has to change */ uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? @@ -2709,7 +2735,8 @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx) /* Next transition is when we hit cval */ nexttick =3D gt->cval + offset; } - /* Note that the desired next expiry time might be beyond the + /* + * Note that the desired next expiry time might be beyond the * signed-64-bit range of a QEMUTimer -- in this case we just * set the timer for as far in the future as possible. When the * timer expires we will reset the timer for any remaining period. @@ -2826,7 +2853,8 @@ static void gt_ctl_write(CPUARMState *env, const ARMC= PRegInfo *ri, /* Enable toggled */ gt_recalc_timer(cpu, timeridx); } else if ((oldval ^ value) & 2) { - /* IMASK toggled: don't need to recalculate, + /* + * IMASK toggled: don't need to recalculate, * just set the interrupt line based on ISTATUS */ int irqstate =3D (oldval & 4) && !(value & 2); @@ -3143,7 +3171,8 @@ static void arm_gt_cntfrq_reset(CPUARMState *env, con= st ARMCPRegInfo *opaque) } =20 static const ARMCPRegInfo generic_timer_cp_reginfo[] =3D { - /* Note that CNTFRQ is purely reads-as-written for the benefit + /* + * Note that CNTFRQ is purely reads-as-written for the benefit * of software; writing it doesn't actually change the timer frequency. * Our reset value matches the fixed frequency we implement the timer = at. */ @@ -3306,7 +3335,8 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .readfn =3D gt_virt_redir_cval_read, .raw_readfn =3D raw_read, .writefn =3D gt_virt_redir_cval_write, .raw_writefn =3D raw_write, }, - /* Secure timer -- this is actually restricted to only EL3 + /* + * Secure timer -- this is actually restricted to only EL3 * and configurably Secure-EL1 via the accessfn. */ { .name =3D "CNTPS_TVAL_EL1", .state =3D ARM_CP_STATE_AA64, @@ -3346,7 +3376,8 @@ static CPAccessResult e2h_access(CPUARMState *env, co= nst ARMCPRegInfo *ri, =20 #else =20 -/* In user-mode most of the generic timer registers are inaccessible +/* + * In user-mode most of the generic timer registers are inaccessible * however modern kernels (4.12+) allow access to cntvct_el0 */ =20 @@ -3354,7 +3385,8 @@ static uint64_t gt_virt_cnt_read(CPUARMState *env, co= nst ARMCPRegInfo *ri) { ARMCPU *cpu =3D env_archcpu(env); =20 - /* Currently we have no support for QEMUTimer in linux-user so we + /* + * Currently we have no support for QEMUTimer in linux-user so we * can't call gt_get_countervalue(env), instead we directly * call the lower level functions. */ @@ -3396,7 +3428,8 @@ static CPAccessResult ats_access(CPUARMState *env, co= nst ARMCPRegInfo *ri, bool isread) { if (ri->opc2 & 4) { - /* The ATS12NSO* operations must trap to EL3 or EL2 if executed in + /* + * The ATS12NSO* operations must trap to EL3 or EL2 if executed in * Secure EL1 (which can only happen if EL3 is AArch64). * They are simply UNDEF if executed from NS EL1. * They function normally from EL2 or EL3. @@ -3554,7 +3587,8 @@ static uint64_t do_ats_write(CPUARMState *env, uint64= _t value, } } } else { - /* fsr is a DFSR/IFSR value for the short descriptor + /* + * fsr is a DFSR/IFSR value for the short descriptor * translation table format (with WnR always clear). * Convert it to a 32-bit PAR. */ @@ -3836,7 +3870,8 @@ static void pmsav7_rgnr_write(CPUARMState *env, const= ARMCPRegInfo *ri, } =20 static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { - /* Reset for all these registers is handled in arm_cpu_reset(), + /* + * Reset for all these registers is handled in arm_cpu_reset(), * because the PMSAv7 is also used by M-profile CPUs, which do * not register cpregs but still need the state to be reset. */ @@ -3922,11 +3957,14 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, = const ARMCPRegInfo *ri, =20 if (!arm_feature(env, ARM_FEATURE_V8)) { if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { - /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when - * using Long-desciptor translation table format */ + /* + * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when + * using Long-desciptor translation table format + */ value &=3D ~((7 << 19) | (3 << 14) | (0xf << 3)); } else if (arm_feature(env, ARM_FEATURE_EL3)) { - /* In an implementation that includes the Security Extensions + /* + * In an implementation that includes the Security Extensions * TTBCR has additional fields PD0 [4] and PD1 [5] for * Short-descriptor translation table format. */ @@ -3936,7 +3974,8 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, } } =20 - /* Update the masks corresponding to the TCR bank being written + /* + * Update the masks corresponding to the TCR bank being written * Note that we always calculate mask and base_mask, but * they are only used for short-descriptor tables (ie if EAE is 0); * for long-descriptor tables the TCR fields are used differently @@ -3954,7 +3993,8 @@ static void vmsa_ttbcr_write(CPUARMState *env, const = ARMCPRegInfo *ri, TCR *tcr =3D raw_ptr(env, ri); =20 if (arm_feature(env, ARM_FEATURE_LPAE)) { - /* With LPAE the TTBCR could result in a change of ASID + /* + * With LPAE the TTBCR could result in a change of ASID * via the TTBCR.A1 bit, so do a TLB flush. */ tlb_flush(CPU(cpu)); @@ -3968,7 +4008,8 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const = ARMCPRegInfo *ri) { TCR *tcr =3D raw_ptr(env, ri); =20 - /* Reset both the TCR as well as the masks corresponding to the bank of + /* + * Reset both the TCR as well as the masks corresponding to the bank of * the TCR being reset. */ tcr->raw_tcr =3D 0; @@ -4100,7 +4141,8 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { REGINFO_SENTINEL }; =20 -/* Note that unlike TTBCR, writing to TTBCR2 does not require flushing +/* + * Note that unlike TTBCR, writing to TTBCR2 does not require flushing * qemu tlbs nor adjusting cached masks. */ static const ARMCPRegInfo ttbcr2_reginfo =3D { @@ -4136,7 +4178,8 @@ static void omap_wfi_write(CPUARMState *env, const AR= MCPRegInfo *ri, static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* On OMAP there are registers indicating the max/min index of dcache = lines + /* + * On OMAP there are registers indicating the max/min index of dcache = lines * containing a dirty line; cache flush operations have to reset these. */ env->cp15.c15_i_max =3D 0x000; @@ -4168,7 +4211,8 @@ static const ARMCPRegInfo omap_cp_reginfo[] =3D { .crm =3D 8, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, .readfn =3D arm_cp_read_zero, .writefn =3D omap_wfi_write, }, - /* TODO: Peripheral port remap register: + /* + * TODO: Peripheral port remap register: * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), * when MMU is off. @@ -4198,7 +4242,8 @@ static const ARMCPRegInfo xscale_cp_reginfo[] =3D { .cp =3D 15, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 1, .acces= s =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c1_xscaleauxcr), .resetvalue =3D 0, }, - /* XScale specific cache-lockdown: since we have no cache we NOP these + /* + * XScale specific cache-lockdown: since we have no cache we NOP these * and hope the guest does not really rely on cache behaviour. */ { .name =3D "XSCALE_LOCK_ICACHE_LINE", @@ -4217,7 +4262,8 @@ static const ARMCPRegInfo xscale_cp_reginfo[] =3D { }; =20 static const ARMCPRegInfo dummy_c15_cp_reginfo[] =3D { - /* RAZ/WI the whole crn=3D15 space, when we don't have a more specific + /* + * RAZ/WI the whole crn=3D15 space, when we don't have a more specific * implementation of this implementation-defined space. * Ideally this should eventually disappear in favour of actually * implementing the correct behaviour for all cores. @@ -4260,7 +4306,8 @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[= ] =3D { }; =20 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] =3D { - /* The cache test-and-clean instructions always return (1 << 30) + /* + * The cache test-and-clean instructions always return (1 << 30) * to indicate that there are no dirty cache lines. */ { .name =3D "TC_DCACHE", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 = =3D 0, .opc2 =3D 3, @@ -4298,7 +4345,8 @@ static uint64_t mpidr_read_val(CPUARMState *env) =20 if (arm_feature(env, ARM_FEATURE_V7MP)) { mpidr |=3D (1U << 31); - /* Cores which are uniprocessor (non-coherent) + /* + * Cores which are uniprocessor (non-coherent) * but still implement the MP extensions set * bit 30. (For instance, Cortex-R5). */ @@ -4501,7 +4549,8 @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMS= tate *env, return CP_ACCESS_OK; } =20 -/* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions +/* + * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions * Page D4-1736 (DDI0487A.b) */ =20 @@ -4668,7 +4717,8 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env,= const ARMCPRegInfo *ri, static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* Invalidate by VA, EL2 + /* + * Invalidate by VA, EL2 * Currently handles both VAE2 and VALE2, since we don't support * flush-last-level-only. */ @@ -4682,7 +4732,8 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* Invalidate by VA, EL3 + /* + * Invalidate by VA, EL3 * Currently handles both VAE3 and VALE3, since we don't support * flush-last-level-only. */ @@ -4707,7 +4758,8 @@ static void tlbi_aa64_vae1is_write(CPUARMState *env, = const ARMCPRegInfo *ri, static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* Invalidate by VA, EL1&0 (AArch64 version). + /* + * Invalidate by VA, EL1&0 (AArch64 version). * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, * since we don't support flush-for-specific-ASID-only or * flush-last-level-only. @@ -4958,7 +5010,8 @@ static CPAccessResult sp_el0_access(CPUARMState *env,= const ARMCPRegInfo *ri, bool isread) { if (!(env->pstate & PSTATE_SP)) { - /* Access to SP_EL0 is undefined if it's being used as + /* + * Access to SP_EL0 is undefined if it's being used as * the stack pointer. */ return CP_ACCESS_TRAP_UNCATEGORIZED; @@ -4998,7 +5051,8 @@ static void sctlr_write(CPUARMState *env, const ARMCP= RegInfo *ri, } =20 if (raw_read(env, ri) =3D=3D value) { - /* Skip the TLB flush if nothing actually changed; Linux likes + /* + * Skip the TLB flush if nothing actually changed; Linux likes * to do a lot of pointless SCTLR writes. */ return; @@ -5039,7 +5093,8 @@ static void sdcr_write(CPUARMState *env, const ARMCPR= egInfo *ri, } =20 static const ARMCPRegInfo v8_cp_reginfo[] =3D { - /* Minimal set of EL0-visible registers. This will need to be expanded + /* + * Minimal set of EL0-visible registers. This will need to be expanded * significantly for system emulation of AArch64 CPUs. */ { .name =3D "NZCV", .state =3D ARM_CP_STATE_AA64, @@ -5314,7 +5369,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, - /* We rely on the access checks not allowing the guest to write to the + /* + * We rely on the access checks not allowing the guest to write to the * state field when SPSel indicates that it's being used as the stack * pointer. */ @@ -5510,7 +5566,8 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (arm_feature(env, ARM_FEATURE_EL3)) { valid_mask &=3D ~HCR_HCD; } else if (cpu->psci_conduit !=3D QEMU_PSCI_CONDUIT_SMC) { - /* Architecturally HCR.TSC is RES0 if EL3 is not implemented. + /* + * Architecturally HCR.TSC is RES0 if EL3 is not implemented. * However, if we're using the SMC PSCI conduit then QEMU is * effectively acting like EL3 firmware and so the guest at * EL2 should retain the ability to prevent EL1 from being @@ -5772,7 +5829,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, .access =3D PL2_RW, - /* no .writefn needed as this can't cause an ASID change; + /* + * no .writefn needed as this can't cause an ASID change; * no .raw_writefn or .resetfn needed as we never use mask/base_mask */ .fieldoffset =3D offsetof(CPUARMState, cp15.vtcr_el2) }, @@ -5846,7 +5904,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, .writefn =3D tlbi_aa64_vae2is_write }, #ifndef CONFIG_USER_ONLY - /* Unlike the other EL2-related AT operations, these must + /* + * Unlike the other EL2-related AT operations, these must * UNDEF from EL3 if EL2 is not implemented, which is why we * define them here rather than with the rest of the AT ops. */ @@ -5858,7 +5917,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, .access =3D PL2_W, .accessfn =3D at_s1e2_access, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write6= 4 }, - /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE + /* + * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 * with SCR.NS =3D=3D 0 outside Monitor mode is UNPREDICTABLE; we choo= se * to behave as if SCR.NS was 1. @@ -5871,7 +5931,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .writefn =3D ats1h_write, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EX= C }, { .name =3D "CNTHCTL_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, - /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the + /* + * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the * reset values as IMPDEF. We choose to reset to 3 to comply with * both ARMv7 and ARMv8. */ @@ -5964,7 +6025,8 @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] =3D { static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *r= i, bool isread) { - /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. + /* + * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. * At Secure EL1 it traps to EL3 or EL2. */ if (arm_current_el(env) =3D=3D 3) { @@ -6012,7 +6074,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { { .name =3D "TCR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, .access =3D PL3_RW, - /* no .writefn needed as this can't cause an ASID change; + /* + * no .writefn needed as this can't cause an ASID change; * we must provide a .raw_writefn and .resetfn because we handle * reset and migration for the AArch32 TTBCR(S), which might be * using mask and base_mask. @@ -6278,7 +6341,8 @@ static CPAccessResult ctr_el0_access(CPUARMState *env= , const ARMCPRegInfo *ri, static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - /* Writes to OSLAR_EL1 may update the OS lock status, which can be + /* + * Writes to OSLAR_EL1 may update the OS lock status, which can be * read via a bit in OSLSR_EL1. */ int oslock; @@ -6293,7 +6357,8 @@ static void oslar_write(CPUARMState *env, const ARMCP= RegInfo *ri, } =20 static const ARMCPRegInfo debug_cp_reginfo[] =3D { - /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped + /* + * DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; * unlike DBGDRAR it is never accessible from EL0. * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AAr= ch64 @@ -6315,7 +6380,8 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tda, .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), .resetvalue =3D 0 }, - /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. + /* + * MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. * We don't implement the configurable EL0 access. */ { .name =3D "MDCCSR_EL0", .state =3D ARM_CP_STATE_BOTH, @@ -6338,21 +6404,24 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 = =3D 4, .access =3D PL1_RW, .accessfn =3D access_tdosa, .type =3D ARM_CP_NOP }, - /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't + /* + * Dummy DBGVCR: Linux wants to clear this on startup, but we don't * implement vector catch debug events yet. */ { .name =3D "DBGVCR", .cp =3D 14, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tda, .type =3D ARM_CP_NOP }, - /* Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor + /* + * Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor * to save and restore a 32-bit guest's DBGVCR) */ { .name =3D "DBGVCR32_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 2, .opc1 =3D 4, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, .access =3D PL2_RW, .accessfn =3D access_tda, .type =3D ARM_CP_NOP }, - /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications + /* + * Dummy MDCCINT_EL1, since we don't implement the Debug Communications * Channel but Linux may try to access this register. The 32-bit * alias is DBGDCCINT. */ @@ -6624,7 +6693,8 @@ static void dbgwvr_write(CPUARMState *env, const ARMC= PRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); int i =3D ri->crm; =20 - /* Bits [63:49] are hardwired to the value of bit [48]; that is, the + /* + * Bits [63:49] are hardwired to the value of bit [48]; that is, the * register reads and behaves as if values written are sign extended. * Bits [1:0] are RES0. */ @@ -6752,7 +6822,8 @@ static void dbgbcr_write(CPUARMState *env, const ARMC= PRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); int i =3D ri->crm; =20 - /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only + /* + * BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only * copy of BAS[0]. */ value =3D deposit64(value, 6, 1, extract64(value, 5, 1)); @@ -6764,7 +6835,8 @@ static void dbgbcr_write(CPUARMState *env, const ARMC= PRegInfo *ri, =20 static void define_debug_regs(ARMCPU *cpu) { - /* Define v7 and v8 architectural debug registers. + /* + * Define v7 and v8 architectural debug registers. * These are just dummy implementations for now. */ int i; @@ -6927,7 +6999,8 @@ static void define_pmu_regs(ARMCPU *cpu) } } =20 -/* We don't know until after realize whether there's a GICv3 +/* + * We don't know until after realize whether there's a GICv3 * attached, and that is what registers the gicv3 sysregs. * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_= EL1 * at runtime. @@ -6956,7 +7029,8 @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, co= nst ARMCPRegInfo *ri) } #endif =20 -/* Shared logic between LORID and the rest of the LOR* registers. +/* + * Shared logic between LORID and the rest of the LOR* registers. * Secure state exclusion has already been dealt with. */ static CPAccessResult access_lor_ns(CPUARMState *env, @@ -7699,7 +7773,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) =20 define_arm_cp_regs(cpu, cp_reginfo); if (!arm_feature(env, ARM_FEATURE_V8)) { - /* Must go early as it is full of wildcards that may be + /* + * Must go early as it is full of wildcards that may be * overridden by later definitions. */ define_arm_cp_regs(cpu, not_v8_cp_reginfo); @@ -7713,7 +7788,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->isar.id_pfr0 }, - /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know + /* + * ID_PFR1 is not a plain ARM_CP_CONST because we don't know * the value of the GIC field until after we define these regs. */ { .name =3D "ID_PFR1", .state =3D ARM_CP_STATE_BOTH, @@ -7825,7 +7901,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, not_v7_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_V8)) { - /* AArch64 ID registers, which all have impdef reset values. + /* + * AArch64 ID registers, which all have impdef reset values. * Note that within the ID register ranges the unused slots * must all RAZ, not UNDEF; future architecture versions may * define new registers here. @@ -8149,11 +8226,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &rvbar); } } else { - /* If EL2 is missing but higher ELs are enabled, we need to + /* + * If EL2 is missing but higher ELs are enabled, we need to * register the no_el2 reginfos. */ if (arm_feature(env, ARM_FEATURE_EL3)) { - /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value + /* + * When EL3 exists but not EL2, VPIDR and VMPIDR take the value * of MIDR_EL1 and MPIDR_EL1. */ ARMCPRegInfo vpidr_regs[] =3D { @@ -8193,7 +8272,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) =20 define_arm_cp_regs(cpu, el3_regs); } - /* The behaviour of NSACR is sufficiently various that we don't + /* + * The behaviour of NSACR is sufficiently various that we don't * try to describe it in a single reginfo: * if EL3 is 64 bit, then trap to EL3 from S EL1, * reads as constant 0xc00 from NS EL1 and NS EL2 @@ -8285,13 +8365,15 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa32_jazelle, cpu)) { define_arm_cp_regs(cpu, jazelle_regs); } - /* Slightly awkwardly, the OMAP and StrongARM cores need all of + /* + * Slightly awkwardly, the OMAP and StrongARM cores need all of * cp15 crn=3D0 to be writes-ignored, whereas for other cores they sho= uld * be read-only (ie write causes UNDEF exception). */ { ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] =3D { - /* Pre-v8 MIDR space. + /* + * Pre-v8 MIDR space. * Note that the MIDR isn't a simple constant register because * of the TI925 behaviour where writes to another register can * cause the MIDR value to change. @@ -8395,7 +8477,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_OMAPCP) || arm_feature(env, ARM_FEATURE_STRONGARM)) { ARMCPRegInfo *r; - /* Register the blanket "writes ignored" value first to cover = the + /* + * Register the blanket "writes ignored" value first to cover = the * whole space. Then update the specific ID registers to allow= write * access, so that they ignore writes rather than causing them= to * UNDEF. @@ -8757,7 +8840,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, int crm, int opc1, int opc2, const char *name) { - /* Private utility function for define_one_arm_cp_reg_with_opaque(): + /* + * Private utility function for define_one_arm_cp_reg_with_opaque(): * add a single reginfo struct to the hash table. */ uint32_t *key =3D g_new(uint32_t, 1); @@ -8766,13 +8850,15 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; =20 r2->name =3D g_strdup(name); - /* Reset the secure state to the specific incoming state. This is + /* + * Reset the secure state to the specific incoming state. This is * necessary as the register may have been defined with both states. */ r2->secure =3D secstate; =20 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { - /* Register is banked (using both entries in array). + /* + * Register is banked (using both entries in array). * Overwriting fieldoffset as the array is only used to define * banked registers but later only fieldoffset is used. */ @@ -8781,7 +8867,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, =20 if (state =3D=3D ARM_CP_STATE_AA32) { if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { - /* If the register is banked then we don't need to migrate or + /* + * If the register is banked then we don't need to migrate or * reset the 32-bit instance in certain cases: * * 1) If the register has both 32-bit and 64-bit instances the= n we @@ -8796,15 +8883,15 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, r2->type |=3D ARM_CP_ALIAS; } } else if ((secstate !=3D r->secure) && !ns) { - /* The register is not banked so we only want to allow migrati= on of + /* + * The register is not banked so we only want to allow migrati= on of * the non-secure instance. */ r2->type |=3D ARM_CP_ALIAS; } =20 if (r->state =3D=3D ARM_CP_STATE_BOTH) { - /* We assume it is a cp15 register if the .cp field is left un= set. - */ + /* We assume it is a cp15 register if the .cp field is left un= set */ if (r2->cp =3D=3D 0) { r2->cp =3D 15; } @@ -8817,7 +8904,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, } } if (state =3D=3D ARM_CP_STATE_AA64) { - /* To allow abbreviation of ARMCPRegInfo + /* + * To allow abbreviation of ARMCPRegInfo * definitions, we treat cp =3D=3D 0 as equivalent to * the value for "standard guest-visible sysreg". * STATE_BOTH definitions are also always "standard @@ -8835,17 +8923,20 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, if (opaque) { r2->opaque =3D opaque; } - /* reginfo passed to helpers is correct for the actual access, + /* + * reginfo passed to helpers is correct for the actual access, * and is never ARM_CP_STATE_BOTH: */ r2->state =3D state; - /* Make sure reginfo passed to helpers for wildcarded regs + /* + * Make sure reginfo passed to helpers for wildcarded regs * has the correct crm/opc1/opc2 for this reg, not CP_ANY: */ r2->crm =3D crm; r2->opc1 =3D opc1; r2->opc2 =3D opc2; - /* By convention, for wildcarded registers only the first + /* + * By convention, for wildcarded registers only the first * entry is used for migration; the others are marked as * ALIAS so we don't try to transfer the register * multiple times. Special registers (ie NOP/WFI) are @@ -8860,7 +8951,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; } =20 - /* Check that raw accesses are either forbidden or handled. Note that + /* + * Check that raw accesses are either forbidden or handled. Note that * we can't assert this earlier because the setup of fieldoffset for * banked registers has to be done first. */ @@ -8868,9 +8960,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, assert(!raw_accessors_invalid(r2)); } =20 - /* Overriding of an existing definition must be explicitly - * requested. - */ + /* Overriding of an existing definition must be explicitly requested. = */ if (!(r->type & ARM_CP_OVERRIDE)) { ARMCPRegInfo *oldreg; oldreg =3D g_hash_table_lookup(cpu->cp_regs, key); @@ -8890,7 +8980,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *r, void *opaque) { - /* Define implementations of coprocessor registers. + /* + * Define implementations of coprocessor registers. * We store these in a hashtable because typically * there are less than 150 registers in a space which * is 16*16*16*8*8 =3D 262144 in size. @@ -8955,7 +9046,8 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, default: g_assert_not_reached(); } - /* The AArch64 pseudocode CheckSystemAccess() specifies that op1 + /* + * The AArch64 pseudocode CheckSystemAccess() specifies that op1 * encodes a minimum access level for the register. We roll this * runtime check into our general permission check code, so check * here that the reginfo's specified permissions are strict enough @@ -8998,10 +9090,11 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, assert((r->access & ~mask) =3D=3D 0); } =20 - /* Check that the register definition has enough info to handle + /* + * Check that the register definition has enough info to handle * reads and writes if they are permitted. */ - if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { + if (!(r->type & (ARM_CP_SPECIAL | ARM_CP_CONST))) { if (r->access & PL3_R) { assert((r->fieldoffset || (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || @@ -9024,7 +9117,8 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, continue; } if (state =3D=3D ARM_CP_STATE_AA32) { - /* Under AArch32 CP registers can be common + /* + * Under AArch32 CP registers can be common * (same for secure and non-secure world) or banke= d. */ char *name; @@ -9048,8 +9142,10 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, break; } } else { - /* AArch64 registers get mapped to non-secure inst= ance - * of AArch32 */ + /* + * AArch64 registers get mapped to non-secure + * instance of AArch32 + */ add_cpreg_to_hashtable(cpu, r, opaque, state, ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->name); --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622824803; cv=none; d=zohomail.com; s=zohoarc; b=NTLSqHCKrIoKhOieoNZNLu+hYcNgup6g58NysiOZgnTeB3PPmfx/tFq2qnHvsDQsfZUUuS1xvjQH1ch5BggxfgL9SuIFSqfWu+vvA57n6DGvkbuh0uvWJxdeDuhu5LxKgzd6ch5gWwnBpry8z6sIoc6I1PMThIUSg2dcJG9GgXA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622824803; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9IAZoH1FQVFYKQUbTP+HG3rskhG4h312NYkS47dna/I=; b=F/2Lp7a6NOeChX4MkR1FXN9KkF5KYYk5EHpnNm7ExZEAlxDr6JhX60Ot2Lhwy2b5QuDJrbU086NFviP3l676oOl71qKXqtNFJOtfnJpFrIOp+809l+bBDRScCI5dYZV860j7W1lEMSlhb2jIy8zRmy4AkDneIVOy7bq3+LqIY/Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622824803770414.3514634936836; Fri, 4 Jun 2021 09:40:03 -0700 (PDT) Received: from localhost ([::1]:49374 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCrZ-0003f1-SS for importer@patchew.org; Fri, 04 Jun 2021 12:40:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48804) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCIL-0000Qg-GY for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:37 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:54128) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHo-0005vt-PD for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:37 -0400 Received: by mail-wm1-x32d.google.com with SMTP id h3so5688409wmq.3 for ; Fri, 04 Jun 2021 09:03:02 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id x11sm7147165wru.87.2021.06.04.09.02.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:54 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 3D4361FFB3; Fri, 4 Jun 2021 16:53:16 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9IAZoH1FQVFYKQUbTP+HG3rskhG4h312NYkS47dna/I=; b=KyX7j3WwfsSw17NIdi5Qk4YGnD0DAB/Yz6xbKS2pdYFjJgf1JSSQevF3XvG5Hq/JXg uZA61OnBowgdtUyz1TE+NytVVKCUE17xMd3xFgGqW4yjJv4ONjjVxfLg1Ei8B9FCy1NC BnGtkaXaj/vBqvNoI8BdqJVLiIvf1UgoEkFqreCC7bkKAJOvx7G5xTImI7gNq2Z2HHAo 4btqRb8klVaEVyNNGhnXBtZGs9y4NTiW77oby4vSuNk8G9piGLF9vxvI/0rhPUW25ZrQ 0jldm/HsvP6i2xP4QzjJwQEGCuAv1ANH09vv1Ucc/SIyCjPRQ24nA+9tdF9eswToC+HK VQsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9IAZoH1FQVFYKQUbTP+HG3rskhG4h312NYkS47dna/I=; b=fvyChdXcPh/qTMFEUZq1NKJEss1fqqVIrixeZ3ZDLDuxbvlS0E8mNlH6+BS44Ip9zD oL6VjKO/B0o5IAc6cV6V+GyVTHotylN/ya/Fw/pFPrz1TUDfW1zvd1nl3wQl2W6Ek/Db 7KbV1kzZubgF6cgsNTA1ZnyBnYqWxwlWPMHvmigIIka85TkA7Ts06Pd6w/wzhWcbFKAc YATVqLoS3rhPKSvMPup7CE6EJ8ZZLbEglEFNTnozgcomxDpO/b9Q9OrWAald6fK3nWd8 9v68obRZ7/+lKEcfLTRo9rDGaUw3rD6kFd1P1/f/v54E5Lkkr0PQDplw7/nSCNNUIreS S0vg== X-Gm-Message-State: AOAM5311gCk/pzloLtsWtGGF4Ga0UG9umpNumoRZqqqy04djenrVONWn eGiFYOpgRVirZNzXQQ41xG5Acw== X-Google-Smtp-Source: ABdhPJwwsGklNvKDuA9B+fmi1PRcdx8lFr+auEyY1H/1MHL0vLkkCsvHKER3+5Lu6jep77Jn+6rupA== X-Received: by 2002:a1c:282:: with SMTP id 124mr4485073wmc.82.1622822579539; Fri, 04 Jun 2021 09:02:59 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 28/99] target/arm: split cpregs from tcg/helper.c Date: Fri, 4 Jun 2021 16:52:01 +0100 Message-Id: <20210604155312.15902-29-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , qemu-arm@nongnu.org, Claudio Fontana , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana give them their own common module cpregs.c, and an interface cpregs.h. Extract the raw cpustate list to its own module. This is more or less needed for KVM too. For the tcg-specific registers, stuff them into tcg/cpregs.c As a result, the monster that is tcg/helper.c is a bit less scary, and a lot of stuff is removed from cpu.h too, relegated to cpregs.h. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpregs.h | 515 ++ target/arm/cpu.h | 480 -- hw/arm/pxa2xx.c | 1 + hw/arm/pxa2xx_pic.c | 1 + hw/intc/arm_gicv3_cpuif.c | 1 + hw/intc/arm_gicv3_kvm.c | 1 + target/arm/cpregs.c | 380 ++ target/arm/cpu.c | 1 + target/arm/cpu64.c | 2 +- target/arm/cpu_tcg.c | 1 + target/arm/cpustate-list.c | 146 + target/arm/gdbstub.c | 1 + target/arm/machine.c | 1 + target/arm/tcg/cpregs.c | 7674 +++++++++++++++++++++++++++ target/arm/tcg/helper.c | 9051 +------------------------------- target/arm/tcg/op_helper.c | 1 + target/arm/tcg/translate-a64.c | 1 + target/arm/tcg/translate.c | 1 + target/arm/meson.build | 2 + target/arm/tcg/meson.build | 1 + 20 files changed, 9005 insertions(+), 9257 deletions(-) create mode 100644 target/arm/cpregs.h create mode 100644 target/arm/cpregs.c create mode 100644 target/arm/cpustate-list.c create mode 100644 target/arm/tcg/cpregs.c diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h new file mode 100644 index 0000000000..a4e62d8f3d --- /dev/null +++ b/target/arm/cpregs.h @@ -0,0 +1,515 @@ +/* + * ARM CP registers + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef CPREGS_H +#define CPREGS_H + +/* + * Interface for defining coprocessor registers. + * Registers are defined in tables of arm_cp_reginfo structs + * which are passed to define_arm_cp_regs(). + */ + +/* + * When looking up a coprocessor register we look for it + * via an integer which encodes all of: + * coprocessor number + * Crn, Crm, opc1, opc2 fields + * 32 or 64 bit register (ie is it accessed via MRC/MCR + * or via MRRC/MCRR?) + * non-secure/secure bank (AArch32 only) + * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. + * (In this case crn and opc2 should be zero.) + * For AArch64, there is no 32/64 bit size distinction; + * instead all registers have a 2 bit op0, 3 bit op1 and op2, + * and 4 bit CRn and CRm. The encoding patterns are chosen + * to be easy to convert to and from the KVM encodings, and also + * so that the hashtable can contain both AArch32 and AArch64 + * registers (to allow for interprocessing where we might run + * 32 bit code on a 64 bit core). + */ +/* + * This bit is private to our hashtable cpreg; in KVM register + * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 + * in the upper bits of the 64 bit ID. + */ +#define CP_REG_AA64_SHIFT 28 +#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) + +/* + * To enable banking of coprocessor registers depending on ns-bit we + * add a bit to distinguish between secure and non-secure cpregs in the + * hashtable. + */ +#define CP_REG_NS_SHIFT 29 +#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) + +#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ + ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ + ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) + +#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ + (CP_REG_AA64_MASK | \ + ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ + ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ + ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ + ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ + ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ + ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) + +/* + * Convert a full 64 bit KVM register ID to the truncated 32 bit + * version used as a key for the coprocessor register hashtable + */ +static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) +{ + uint32_t cpregid =3D kvmid; + if ((kvmid & CP_REG_ARCH_MASK) =3D=3D CP_REG_ARM64) { + cpregid |=3D CP_REG_AA64_MASK; + } else { + if ((kvmid & CP_REG_SIZE_MASK) =3D=3D CP_REG_SIZE_U64) { + cpregid |=3D (1 << 15); + } + + /* + * KVM is always non-secure so add the NS flag on AArch32 register + * entries. + */ + cpregid |=3D 1 << CP_REG_NS_SHIFT; + } + return cpregid; +} + +/* + * Convert a truncated 32 bit hashtable key into the full + * 64 bit KVM register ID. + */ +static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) +{ + uint64_t kvmid; + + if (cpregid & CP_REG_AA64_MASK) { + kvmid =3D cpregid & ~CP_REG_AA64_MASK; + kvmid |=3D CP_REG_SIZE_U64 | CP_REG_ARM64; + } else { + kvmid =3D cpregid & ~(1 << 15); + if (cpregid & (1 << 15)) { + kvmid |=3D CP_REG_SIZE_U64 | CP_REG_ARM; + } else { + kvmid |=3D CP_REG_SIZE_U32 | CP_REG_ARM; + } + } + return kvmid; +} + +/* + * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a + * special-behaviour cp reg and bits [11..8] indicate what behaviour + * it has. Otherwise it is a simple cp reg, where CONST indicates that + * TCG can assume the value to be constant (ie load at translate time) + * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END + * indicates that the TB should not be ended after a write to this register + * (the default is that the TB ends after cp writes). OVERRIDE permits + * a register definition to override a previous definition for the + * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the + * old must have the OVERRIDE bit set. + * ALIAS indicates that this register is an alias view of some underlying + * state which is also visible via another register, and that the other + * register is handling migration and reset; registers marked ALIAS will n= ot be + * migrated but may have their state set by syncing of register state from= KVM. + * NO_RAW indicates that this register has no underlying state and does not + * support raw access for state saving/loading; it will not be used for ei= ther + * migration or KVM state synchronization. (Typically this is for "registe= rs" + * which are actually used as instructions for cache maintenance and so on= .) + * IO indicates that this register does I/O and therefore its accesses + * need to be marked with gen_io_start() and also end the TB. In particula= r, + * registers which implement clocks or timers require this. + * RAISES_EXC is for when the read or write hook might raise an exception; + * the generated code will synchronize the CPU state before calling the ho= ok + * so that it is safe for the hook to call raise_exception(). + * NEWEL is for writes to registers that might change the exception + * level - typically on older ARM chips. For those cases we need to + * re-read the new el when recomputing the translation flags. + */ +#define ARM_CP_SPECIAL 0x0001 +#define ARM_CP_CONST 0x0002 +#define ARM_CP_64BIT 0x0004 +#define ARM_CP_SUPPRESS_TB_END 0x0008 +#define ARM_CP_OVERRIDE 0x0010 +#define ARM_CP_ALIAS 0x0020 +#define ARM_CP_IO 0x0040 +#define ARM_CP_NO_RAW 0x0080 +#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) +#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) +#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) +#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) +#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) +#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) +#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) +#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA +#define ARM_CP_FPU 0x1000 +#define ARM_CP_SVE 0x2000 +#define ARM_CP_NO_GDB 0x4000 +#define ARM_CP_RAISES_EXC 0x8000 +#define ARM_CP_NEWEL 0x10000 +/* Used only as a terminator for ARMCPRegInfo lists */ +#define ARM_CP_SENTINEL 0xfffff +/* Mask of only the flag bits in a type field */ +#define ARM_CP_FLAG_MASK 0x1f0ff + +/* + * Valid values for ARMCPRegInfo state field, indicating which of + * the AArch32 and AArch64 execution states this register is visible in. + * If the reginfo doesn't explicitly specify then it is AArch32 only. + * If the reginfo is declared to be visible in both states then a second + * reginfo is synthesised for the AArch32 view of the AArch64 register, + * such that the AArch32 view is the lower 32 bits of the AArch64 one. + * Note that we rely on the values of these enums as we iterate through + * the various states in some places. + */ +enum { + ARM_CP_STATE_AA32 =3D 0, + ARM_CP_STATE_AA64 =3D 1, + ARM_CP_STATE_BOTH =3D 2, +}; + +/* + * ARM CP register secure state flags. These flags identify security state + * attributes for a given CP register entry. + * The existence of both or neither secure and non-secure flags indicates = that + * the register has both a secure and non-secure hash entry. A single one= of + * these flags causes the register to only be hashed for the specified + * security state. + * Although definitions may have any combination of the S/NS bits, each + * registered entry will only have one to identify whether the entry is se= cure + * or non-secure. + */ +enum { + ARM_CP_SECSTATE_S =3D (1 << 0), /* bit[0]: Secure state register */ + ARM_CP_SECSTATE_NS =3D (1 << 1), /* bit[1]: Non-secure state register= */ +}; + +/* + * Return true if cptype is a valid type field. This is used to try to + * catch errors where the sentinel has been accidentally left off the end + * of a list of registers. + */ +static inline bool cptype_valid(int cptype) +{ + return ((cptype & ~ARM_CP_FLAG_MASK) =3D=3D 0) + || ((cptype & ARM_CP_SPECIAL) && + ((cptype & ~ARM_CP_FLAG_MASK) <=3D ARM_LAST_SPECIAL)); +} + +/* + * Access rights: + * We define bits for Read and Write access for what rev C of the v7-AR AR= M ARM + * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and + * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 + * (ie any of the privileged modes in Secure state, or Monitor mode). + * If a register is accessible in one privilege level it's always accessib= le + * in higher privilege levels too. Since "Secure PL1" also follows this ru= le + * (ie anything visible in PL2 is visible in S-PL1, some things are only + * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the + * terminology a little and call this PL3. + * In AArch64 things are somewhat simpler as the PLx bits line up exactly + * with the ELx exception levels. + * + * If access permissions for a register are more complex than can be + * described with these bits, then use a laxer set of restrictions, and + * do the more restrictive/complex check inside a helper function. + */ +#define PL3_R 0x80 +#define PL3_W 0x40 +#define PL2_R (0x20 | PL3_R) +#define PL2_W (0x10 | PL3_W) +#define PL1_R (0x08 | PL2_R) +#define PL1_W (0x04 | PL2_W) +#define PL0_R (0x02 | PL1_R) +#define PL0_W (0x01 | PL1_W) + +/* + * For user-mode some registers are accessible to EL0 via a kernel + * trap-and-emulate ABI. In this case we define the read permissions + * as actually being PL0_R. However some bits of any given register + * may still be masked. + */ +#ifdef CONFIG_USER_ONLY +#define PL0U_R PL0_R +#else +#define PL0U_R PL1_R +#endif + +#define PL3_RW (PL3_R | PL3_W) +#define PL2_RW (PL2_R | PL2_W) +#define PL1_RW (PL1_R | PL1_W) +#define PL0_RW (PL0_R | PL0_W) + +typedef enum CPAccessResult { + /* Access is permitted */ + CP_ACCESS_OK =3D 0, + /* + * Access fails due to a configurable trap or enable which would + * result in a categorized exception syndrome giving information about + * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, + * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or + * PL1 if in EL0, otherwise to the current EL). + */ + CP_ACCESS_TRAP =3D 1, + /* + * Access fails and results in an exception syndrome 0x0 ("uncategoriz= ed"). + * Note that this is not a catch-all case -- the set of cases which may + * result in this failure is specifically defined by the architecture. + */ + CP_ACCESS_TRAP_UNCATEGORIZED =3D 2, + /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ + CP_ACCESS_TRAP_EL2 =3D 3, + CP_ACCESS_TRAP_EL3 =3D 4, + /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ + CP_ACCESS_TRAP_UNCATEGORIZED_EL2 =3D 5, + CP_ACCESS_TRAP_UNCATEGORIZED_EL3 =3D 6, + /* + * Access fails and results in an exception syndrome for an FP access, + * trapped directly to EL2 or EL3 + */ + CP_ACCESS_TRAP_FP_EL2 =3D 7, + CP_ACCESS_TRAP_FP_EL3 =3D 8, +} CPAccessResult; + +/* + * Access functions for coprocessor registers. These cannot fail and + * may not raise exceptions. + */ +typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); +typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, + uint64_t value); +/* Access permission check functions for coprocessor registers. */ +typedef CPAccessResult CPAccessFn(CPUARMState *env, + const ARMCPRegInfo *opaque, + bool isread); +/* Hook function for register reset */ +typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); + +#define CP_ANY 0xff + +/* Definition of an ARM coprocessor register */ +struct ARMCPRegInfo { + /* Name of register (useful mainly for debugging, need not be unique) = */ + const char *name; + /* + * Location of register: coprocessor number and (crn,crm,opc1,opc2) + * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a + * 'wildcard' field -- any value of that field in the MRC/MCR insn + * will be decoded to this register. The register read and write + * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 + * used by the program, so it is possible to register a wildcard and + * then behave differently on read/write if necessary. + * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 + * must both be zero. + * For AArch64-visible registers, opc0 is also used. + * Since there are no "coprocessors" in AArch64, cp is purely used as a + * way to distinguish (for KVM's benefit) guest-visible system registe= rs + * from demuxed ones provided to preserve the "no side effects on + * KVM register read/write from QEMU" semantics. cp=3D=3D0x13 is guest + * visible (to match KVM's encoding); cp=3D=3D0 will be converted to + * cp=3D=3D0x13 when the ARMCPRegInfo is registered, for convenience. + */ + uint8_t cp; + uint8_t crn; + uint8_t crm; + uint8_t opc0; + uint8_t opc1; + uint8_t opc2; + /* Execution state in which this register is visible: ARM_CP_STATE_* */ + int state; + /* Register type: ARM_CP_* bits/values */ + int type; + /* Access rights: PL*_[RW] */ + int access; + /* Security state: ARM_CP_SECSTATE_* bits/values */ + int secure; + /* + * The opaque pointer passed to define_arm_cp_regs_with_opaque() when + * this register was defined: can be used to hand data through to the + * register read/write functions, since they are passed the ARMCPRegIn= fo*. + */ + void *opaque; + /* + * Value of this register, if it is ARM_CP_CONST. Otherwise, if + * fieldoffset is non-zero, the reset value of the register. + */ + uint64_t resetvalue; + /* + * Offset of the field in CPUARMState for this register. + * + * This is not needed if either: + * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs + * 2. both readfn and writefn are specified + */ + ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ + + /* + * Offsets of the secure and non-secure fields in CPUARMState for the + * register if it is banked. These fields are only used during the st= atic + * registration of a register. During hashing the bank associated + * with a given security state is copied to fieldoffset which is used = from + * there on out. + * + * It is expected that register definitions use either fieldoffset or + * bank_fieldoffsets in the definition but not both. It is also expec= ted + * that both bank offsets are set when defining a banked register. Th= is + * use indicates that a register is banked. + */ + ptrdiff_t bank_fieldoffsets[2]; + + /* + * Function for making any access checks for this register in addition= to + * those specified by the 'access' permissions bits. If NULL, no extra + * checks required. The access check is performed at runtime, not at + * translate time. + */ + CPAccessFn *accessfn; + /* + * Function for handling reads of this register. If NULL, then reads + * will be done by loading from the offset into CPUARMState specified + * by fieldoffset. + */ + CPReadFn *readfn; + /* + * Function for handling writes of this register. If NULL, then writes + * will be done by writing to the offset into CPUARMState specified + * by fieldoffset. + */ + CPWriteFn *writefn; + /* + * Function for doing a "raw" read; used when we need to copy + * coprocessor state to the kernel for KVM or out for + * migration. This only needs to be provided if there is also a + * readfn and it has side effects (for instance clear-on-read bits). + */ + CPReadFn *raw_readfn; + /* + * Function for doing a "raw" write; used when we need to copy KVM + * kernel coprocessor state into userspace, or for inbound + * migration. This only needs to be provided if there is also a + * writefn and it masks out "unwritable" bits or has write-one-to-clear + * or similar behaviour. + */ + CPWriteFn *raw_writefn; + /* + * Function for resetting the register. If NULL, then reset will be do= ne + * by writing resetvalue to the field specified in fieldoffset. If + * fieldoffset is 0 then no reset will be done. + */ + CPResetFn *resetfn; + + /* + * "Original" writefn and readfn. + * For ARMv8.1-VHE register aliases, we overwrite the read/write + * accessor functions of various EL1/EL0 to perform the runtime + * check for which sysreg should actually be modified, and then + * forwards the operation. Before overwriting the accessors, + * the original function is copied here, so that accesses that + * really do go to the EL1/EL0 version proceed normally. + * (The corresponding EL2 register is linked via opaque.) + */ + CPReadFn *orig_readfn; + CPWriteFn *orig_writefn; +}; + +/* + * Macros which are lvalues for the field in CPUARMState for the + * ARMCPRegInfo *ri. + */ +#define CPREG_FIELD32(env, ri) \ + (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) +#define CPREG_FIELD64(env, ri) \ + (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) + +#define REGINFO_SENTINEL { .type =3D ARM_CP_SENTINEL } + +void define_arm_cp_regs_with_opaque(ARMCPU *cpu, + const ARMCPRegInfo *regs, void *opaque= ); +void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, + const ARMCPRegInfo *regs, void *opa= que); +static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *reg= s) +{ + define_arm_cp_regs_with_opaque(cpu, regs, 0); +} +static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *= regs) +{ + define_one_arm_cp_reg_with_opaque(cpu, regs, 0); +} +const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp); + +/* + * Definition of an ARM co-processor register as viewed from + * userspace. This is used for presenting sanitised versions of + * registers to userspace when emulating the Linux AArch64 CPU + * ID/feature ABI (advertised as HWCAP_CPUID). + */ +typedef struct ARMCPRegUserSpaceInfo { + /* Name of register */ + const char *name; + + /* Is the name actually a glob pattern */ + bool is_glob; + + /* Only some bits are exported to user space */ + uint64_t exported_bits; + + /* Fixed bits are applied after the mask */ + uint64_t fixed_bits; +} ARMCPRegUserSpaceInfo; + +#define REGUSERINFO_SENTINEL { .name =3D NULL } + +/* CPWriteFn that can be used to implement writes-ignored behaviour */ +void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value); +/* CPReadFn that can be used for read-as-zero behaviour */ +uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); + +/* + * CPResetFn that does nothing, for use if no reset is required even + * if fieldoffset is non zero. + */ +void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); + +/* + * Return true if this reginfo struct's field in the cpu state struct + * is 64 bits wide. + */ +static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) +{ + return (ri->state =3D=3D ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BI= T); +} + +static inline bool cp_access_ok(int current_el, + const ARMCPRegInfo *ri, int isread) +{ + return (ri->access >> ((current_el * 2) + isread)) & 1; +} + +/* Raw read of a coprocessor register (as needed for migration, etc) */ +uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); + +#ifdef CONFIG_TCG +/* Modify ARMCPRegInfo for access from userspace. */ +void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods); +#endif + +/* + * default raw read/write of coprocessor register field, + * behavior if no other function defined, and not const. + */ +uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri); +void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value); + +#endif /* CPREGS_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index af788c7801..adb9d2828d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2424,235 +2424,6 @@ static inline bool armv7m_nvic_neg_prio_requested(v= oid *opaque, bool secure) } #endif =20 -/* Interface for defining coprocessor registers. - * Registers are defined in tables of arm_cp_reginfo structs - * which are passed to define_arm_cp_regs(). - */ - -/* When looking up a coprocessor register we look for it - * via an integer which encodes all of: - * coprocessor number - * Crn, Crm, opc1, opc2 fields - * 32 or 64 bit register (ie is it accessed via MRC/MCR - * or via MRRC/MCRR?) - * non-secure/secure bank (AArch32 only) - * We allow 4 bits for opc1 because MRRC/MCRR have a 4 bit field. - * (In this case crn and opc2 should be zero.) - * For AArch64, there is no 32/64 bit size distinction; - * instead all registers have a 2 bit op0, 3 bit op1 and op2, - * and 4 bit CRn and CRm. The encoding patterns are chosen - * to be easy to convert to and from the KVM encodings, and also - * so that the hashtable can contain both AArch32 and AArch64 - * registers (to allow for interprocessing where we might run - * 32 bit code on a 64 bit core). - */ -/* This bit is private to our hashtable cpreg; in KVM register - * IDs the AArch64/32 distinction is the KVM_REG_ARM/ARM64 - * in the upper bits of the 64 bit ID. - */ -#define CP_REG_AA64_SHIFT 28 -#define CP_REG_AA64_MASK (1 << CP_REG_AA64_SHIFT) - -/* To enable banking of coprocessor registers depending on ns-bit we - * add a bit to distinguish between secure and non-secure cpregs in the - * hashtable. - */ -#define CP_REG_NS_SHIFT 29 -#define CP_REG_NS_MASK (1 << CP_REG_NS_SHIFT) - -#define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ - ((ns) << CP_REG_NS_SHIFT | ((cp) << 16) | ((is64) << 15) | \ - ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) - -#define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ - (CP_REG_AA64_MASK | \ - ((cp) << CP_REG_ARM_COPROC_SHIFT) | \ - ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ - ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ - ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \ - ((crm) << CP_REG_ARM64_SYSREG_CRM_SHIFT) | \ - ((op2) << CP_REG_ARM64_SYSREG_OP2_SHIFT)) - -/* Convert a full 64 bit KVM register ID to the truncated 32 bit - * version used as a key for the coprocessor register hashtable - */ -static inline uint32_t kvm_to_cpreg_id(uint64_t kvmid) -{ - uint32_t cpregid =3D kvmid; - if ((kvmid & CP_REG_ARCH_MASK) =3D=3D CP_REG_ARM64) { - cpregid |=3D CP_REG_AA64_MASK; - } else { - if ((kvmid & CP_REG_SIZE_MASK) =3D=3D CP_REG_SIZE_U64) { - cpregid |=3D (1 << 15); - } - - /* KVM is always non-secure so add the NS flag on AArch32 register - * entries. - */ - cpregid |=3D 1 << CP_REG_NS_SHIFT; - } - return cpregid; -} - -/* Convert a truncated 32 bit hashtable key into the full - * 64 bit KVM register ID. - */ -static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) -{ - uint64_t kvmid; - - if (cpregid & CP_REG_AA64_MASK) { - kvmid =3D cpregid & ~CP_REG_AA64_MASK; - kvmid |=3D CP_REG_SIZE_U64 | CP_REG_ARM64; - } else { - kvmid =3D cpregid & ~(1 << 15); - if (cpregid & (1 << 15)) { - kvmid |=3D CP_REG_SIZE_U64 | CP_REG_ARM; - } else { - kvmid |=3D CP_REG_SIZE_U32 | CP_REG_ARM; - } - } - return kvmid; -} - -/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a - * special-behaviour cp reg and bits [11..8] indicate what behaviour - * it has. Otherwise it is a simple cp reg, where CONST indicates that - * TCG can assume the value to be constant (ie load at translate time) - * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END - * indicates that the TB should not be ended after a write to this register - * (the default is that the TB ends after cp writes). OVERRIDE permits - * a register definition to override a previous definition for the - * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the - * old must have the OVERRIDE bit set. - * ALIAS indicates that this register is an alias view of some underlying - * state which is also visible via another register, and that the other - * register is handling migration and reset; registers marked ALIAS will n= ot be - * migrated but may have their state set by syncing of register state from= KVM. - * NO_RAW indicates that this register has no underlying state and does not - * support raw access for state saving/loading; it will not be used for ei= ther - * migration or KVM state synchronization. (Typically this is for "registe= rs" - * which are actually used as instructions for cache maintenance and so on= .) - * IO indicates that this register does I/O and therefore its accesses - * need to be marked with gen_io_start() and also end the TB. In particula= r, - * registers which implement clocks or timers require this. - * RAISES_EXC is for when the read or write hook might raise an exception; - * the generated code will synchronize the CPU state before calling the ho= ok - * so that it is safe for the hook to call raise_exception(). - * NEWEL is for writes to registers that might change the exception - * level - typically on older ARM chips. For those cases we need to - * re-read the new el when recomputing the translation flags. - */ -#define ARM_CP_SPECIAL 0x0001 -#define ARM_CP_CONST 0x0002 -#define ARM_CP_64BIT 0x0004 -#define ARM_CP_SUPPRESS_TB_END 0x0008 -#define ARM_CP_OVERRIDE 0x0010 -#define ARM_CP_ALIAS 0x0020 -#define ARM_CP_IO 0x0040 -#define ARM_CP_NO_RAW 0x0080 -#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) -#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) -#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) -#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) -#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) -#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) -#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) -#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA -#define ARM_CP_FPU 0x1000 -#define ARM_CP_SVE 0x2000 -#define ARM_CP_NO_GDB 0x4000 -#define ARM_CP_RAISES_EXC 0x8000 -#define ARM_CP_NEWEL 0x10000 -/* Used only as a terminator for ARMCPRegInfo lists */ -#define ARM_CP_SENTINEL 0xfffff -/* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0x1f0ff - -/* Valid values for ARMCPRegInfo state field, indicating which of - * the AArch32 and AArch64 execution states this register is visible in. - * If the reginfo doesn't explicitly specify then it is AArch32 only. - * If the reginfo is declared to be visible in both states then a second - * reginfo is synthesised for the AArch32 view of the AArch64 register, - * such that the AArch32 view is the lower 32 bits of the AArch64 one. - * Note that we rely on the values of these enums as we iterate through - * the various states in some places. - */ -enum { - ARM_CP_STATE_AA32 =3D 0, - ARM_CP_STATE_AA64 =3D 1, - ARM_CP_STATE_BOTH =3D 2, -}; - -/* ARM CP register secure state flags. These flags identify security state - * attributes for a given CP register entry. - * The existence of both or neither secure and non-secure flags indicates = that - * the register has both a secure and non-secure hash entry. A single one= of - * these flags causes the register to only be hashed for the specified - * security state. - * Although definitions may have any combination of the S/NS bits, each - * registered entry will only have one to identify whether the entry is se= cure - * or non-secure. - */ -enum { - ARM_CP_SECSTATE_S =3D (1 << 0), /* bit[0]: Secure state register */ - ARM_CP_SECSTATE_NS =3D (1 << 1), /* bit[1]: Non-secure state register= */ -}; - -/* Return true if cptype is a valid type field. This is used to try to - * catch errors where the sentinel has been accidentally left off the end - * of a list of registers. - */ -static inline bool cptype_valid(int cptype) -{ - return ((cptype & ~ARM_CP_FLAG_MASK) =3D=3D 0) - || ((cptype & ARM_CP_SPECIAL) && - ((cptype & ~ARM_CP_FLAG_MASK) <=3D ARM_LAST_SPECIAL)); -} - -/* Access rights: - * We define bits for Read and Write access for what rev C of the v7-AR AR= M ARM - * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and - * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 - * (ie any of the privileged modes in Secure state, or Monitor mode). - * If a register is accessible in one privilege level it's always accessib= le - * in higher privilege levels too. Since "Secure PL1" also follows this ru= le - * (ie anything visible in PL2 is visible in S-PL1, some things are only - * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the - * terminology a little and call this PL3. - * In AArch64 things are somewhat simpler as the PLx bits line up exactly - * with the ELx exception levels. - * - * If access permissions for a register are more complex than can be - * described with these bits, then use a laxer set of restrictions, and - * do the more restrictive/complex check inside a helper function. - */ -#define PL3_R 0x80 -#define PL3_W 0x40 -#define PL2_R (0x20 | PL3_R) -#define PL2_W (0x10 | PL3_W) -#define PL1_R (0x08 | PL2_R) -#define PL1_W (0x04 | PL2_W) -#define PL0_R (0x02 | PL1_R) -#define PL0_W (0x01 | PL1_W) - -/* - * For user-mode some registers are accessible to EL0 via a kernel - * trap-and-emulate ABI. In this case we define the read permissions - * as actually being PL0_R. However some bits of any given register - * may still be masked. - */ -#ifdef CONFIG_USER_ONLY -#define PL0U_R PL0_R -#else -#define PL0U_R PL1_R -#endif - -#define PL3_RW (PL3_R | PL3_W) -#define PL2_RW (PL2_R | PL2_W) -#define PL1_RW (PL1_R | PL1_W) -#define PL0_RW (PL0_R | PL0_W) - /* Return the highest implemented Exception Level */ static inline int arm_highest_el(CPUARMState *env) { @@ -2706,257 +2477,6 @@ static inline int arm_current_el(CPUARMState *env) =20 typedef struct ARMCPRegInfo ARMCPRegInfo; =20 -typedef enum CPAccessResult { - /* Access is permitted */ - CP_ACCESS_OK =3D 0, - /* - * Access fails due to a configurable trap or enable which would - * result in a categorized exception syndrome giving information about - * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, - * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or - * PL1 if in EL0, otherwise to the current EL). - */ - CP_ACCESS_TRAP =3D 1, - /* - * Access fails and results in an exception syndrome 0x0 ("uncategoriz= ed"). - * Note that this is not a catch-all case -- the set of cases which may - * result in this failure is specifically defined by the architecture. - */ - CP_ACCESS_TRAP_UNCATEGORIZED =3D 2, - /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ - CP_ACCESS_TRAP_EL2 =3D 3, - CP_ACCESS_TRAP_EL3 =3D 4, - /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ - CP_ACCESS_TRAP_UNCATEGORIZED_EL2 =3D 5, - CP_ACCESS_TRAP_UNCATEGORIZED_EL3 =3D 6, - /* - * Access fails and results in an exception syndrome for an FP access, - * trapped directly to EL2 or EL3 - */ - CP_ACCESS_TRAP_FP_EL2 =3D 7, - CP_ACCESS_TRAP_FP_EL3 =3D 8, -} CPAccessResult; - -/* - * Access functions for coprocessor registers. These cannot fail and - * may not raise exceptions. - */ -typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); -typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, - uint64_t value); -/* Access permission check functions for coprocessor registers. */ -typedef CPAccessResult CPAccessFn(CPUARMState *env, - const ARMCPRegInfo *opaque, - bool isread); -/* Hook function for register reset */ -typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); - -#define CP_ANY 0xff - -/* Definition of an ARM coprocessor register */ -struct ARMCPRegInfo { - /* Name of register (useful mainly for debugging, need not be unique) = */ - const char *name; - /* - * Location of register: coprocessor number and (crn,crm,opc1,opc2) - * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a - * 'wildcard' field -- any value of that field in the MRC/MCR insn - * will be decoded to this register. The register read and write - * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 - * used by the program, so it is possible to register a wildcard and - * then behave differently on read/write if necessary. - * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 - * must both be zero. - * For AArch64-visible registers, opc0 is also used. - * Since there are no "coprocessors" in AArch64, cp is purely used as a - * way to distinguish (for KVM's benefit) guest-visible system registe= rs - * from demuxed ones provided to preserve the "no side effects on - * KVM register read/write from QEMU" semantics. cp=3D=3D0x13 is guest - * visible (to match KVM's encoding); cp=3D=3D0 will be converted to - * cp=3D=3D0x13 when the ARMCPRegInfo is registered, for convenience. - */ - uint8_t cp; - uint8_t crn; - uint8_t crm; - uint8_t opc0; - uint8_t opc1; - uint8_t opc2; - /* Execution state in which this register is visible: ARM_CP_STATE_* */ - int state; - /* Register type: ARM_CP_* bits/values */ - int type; - /* Access rights: PL*_[RW] */ - int access; - /* Security state: ARM_CP_SECSTATE_* bits/values */ - int secure; - /* - * The opaque pointer passed to define_arm_cp_regs_with_opaque() when - * this register was defined: can be used to hand data through to the - * register read/write functions, since they are passed the ARMCPRegIn= fo*. - */ - void *opaque; - /* - * Value of this register, if it is ARM_CP_CONST. Otherwise, if - * fieldoffset is non-zero, the reset value of the register. - */ - uint64_t resetvalue; - /* - * Offset of the field in CPUARMState for this register. - * - * This is not needed if either: - * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs - * 2. both readfn and writefn are specified - */ - ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ - - /* - * Offsets of the secure and non-secure fields in CPUARMState for the - * register if it is banked. These fields are only used during the st= atic - * registration of a register. During hashing the bank associated - * with a given security state is copied to fieldoffset which is used = from - * there on out. - * - * It is expected that register definitions use either fieldoffset or - * bank_fieldoffsets in the definition but not both. It is also expec= ted - * that both bank offsets are set when defining a banked register. Th= is - * use indicates that a register is banked. - */ - ptrdiff_t bank_fieldoffsets[2]; - - /* - * Function for making any access checks for this register in addition= to - * those specified by the 'access' permissions bits. If NULL, no extra - * checks required. The access check is performed at runtime, not at - * translate time. - */ - CPAccessFn *accessfn; - /* - * Function for handling reads of this register. If NULL, then reads - * will be done by loading from the offset into CPUARMState specified - * by fieldoffset. - */ - CPReadFn *readfn; - /* - * Function for handling writes of this register. If NULL, then writes - * will be done by writing to the offset into CPUARMState specified - * by fieldoffset. - */ - CPWriteFn *writefn; - /* - * Function for doing a "raw" read; used when we need to copy - * coprocessor state to the kernel for KVM or out for - * migration. This only needs to be provided if there is also a - * readfn and it has side effects (for instance clear-on-read bits). - */ - CPReadFn *raw_readfn; - /* - * Function for doing a "raw" write; used when we need to copy KVM - * kernel coprocessor state into userspace, or for inbound - * migration. This only needs to be provided if there is also a - * writefn and it masks out "unwritable" bits or has write-one-to-clear - * or similar behaviour. - */ - CPWriteFn *raw_writefn; - /* - * Function for resetting the register. If NULL, then reset will be do= ne - * by writing resetvalue to the field specified in fieldoffset. If - * fieldoffset is 0 then no reset will be done. - */ - CPResetFn *resetfn; - - /* - * "Original" writefn and readfn. - * For ARMv8.1-VHE register aliases, we overwrite the read/write - * accessor functions of various EL1/EL0 to perform the runtime - * check for which sysreg should actually be modified, and then - * forwards the operation. Before overwriting the accessors, - * the original function is copied here, so that accesses that - * really do go to the EL1/EL0 version proceed normally. - * (The corresponding EL2 register is linked via opaque.) - */ - CPReadFn *orig_readfn; - CPWriteFn *orig_writefn; -}; - -/* - * Macros which are lvalues for the field in CPUARMState for the - * ARMCPRegInfo *ri. - */ -#define CPREG_FIELD32(env, ri) \ - (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) -#define CPREG_FIELD64(env, ri) \ - (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) - -#define REGINFO_SENTINEL { .type =3D ARM_CP_SENTINEL } - -void define_arm_cp_regs_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *regs, void *opaque= ); -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *regs, void *opa= que); -static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *reg= s) -{ - define_arm_cp_regs_with_opaque(cpu, regs, 0); -} -static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *= regs) -{ - define_one_arm_cp_reg_with_opaque(cpu, regs, 0); -} -const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp); - -/* - * Definition of an ARM co-processor register as viewed from - * userspace. This is used for presenting sanitised versions of - * registers to userspace when emulating the Linux AArch64 CPU - * ID/feature ABI (advertised as HWCAP_CPUID). - */ -typedef struct ARMCPRegUserSpaceInfo { - /* Name of register */ - const char *name; - - /* Is the name actually a glob pattern */ - bool is_glob; - - /* Only some bits are exported to user space */ - uint64_t exported_bits; - - /* Fixed bits are applied after the mask */ - uint64_t fixed_bits; -} ARMCPRegUserSpaceInfo; - -#define REGUSERINFO_SENTINEL { .name =3D NULL } - -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods); - -/* CPWriteFn that can be used to implement writes-ignored behaviour */ -void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value); -/* CPReadFn that can be used for read-as-zero behaviour */ -uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); - -/* - * CPResetFn that does nothing, for use if no reset is required even - * if fieldoffset is non zero. - */ -void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); - -/* - * Return true if this reginfo struct's field in the cpu state struct - * is 64 bits wide. - */ -static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) -{ - return (ri->state =3D=3D ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BI= T); -} - -static inline bool cp_access_ok(int current_el, - const ARMCPRegInfo *ri, int isread) -{ - return (ri->access >> ((current_el * 2) + isread)) & 1; -} - -/* Raw read of a coprocessor register (as needed for migration, etc) */ -uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); - /** * write_list_to_cpustate * @cpu: ARMCPU diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index fdc4955e95..2f7a4e90ad 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -30,6 +30,7 @@ #include "qemu/cutils.h" #include "qemu/log.h" #include "qom/object.h" +#include "cpregs.h" =20 static struct { hwaddr io_base; diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index ed032fed54..934ff6716a 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -17,6 +17,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "qom/object.h" +#include "cpregs.h" =20 #define ICIP 0x00 /* Interrupt Controller IRQ Pending register */ #define ICMR 0x04 /* Interrupt Controller Mask register */ diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 81f94c7f4a..fa374d5ecc 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -19,6 +19,7 @@ #include "gicv3_internal.h" #include "hw/irq.h" #include "cpu.h" +#include "cpregs.h" =20 void gicv3_set_gicv3state(CPUState *cpu, GICv3CPUState *s) { diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 5c09f00dec..96c7e8b80c 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -31,6 +31,7 @@ #include "vgic_common.h" #include "migration/blocker.h" #include "qom/object.h" +#include "cpregs.h" =20 #ifdef DEBUG_GICV3_KVM #define DPRINTF(fmt, ...) \ diff --git a/target/arm/cpregs.c b/target/arm/cpregs.c new file mode 100644 index 0000000000..3fbfbfb35a --- /dev/null +++ b/target/arm/cpregs.c @@ -0,0 +1,380 @@ +/* + * ARM CP registers - common functionality + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "cpregs.h" + +static bool raw_accessors_invalid(const ARMCPRegInfo *ri) +{ + /* + * Return true if the regdef would cause an assertion if you called + * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a + * program bug for it not to have the NO_RAW flag). + * NB that returning false here doesn't necessarily mean that calling + * read/write_raw_cp_reg() is safe, because we can't distinguish "has + * read/write access functions which are safe for raw use" from "has + * read/write access functions which have side effects but has forgotten + * to provide raw access functions". + * The tests here line up with the conditions in read/write_raw_cp_reg() + * and assertions in raw_read()/raw_write(). + */ + if ((ri->type & ARM_CP_CONST) || + ri->fieldoffset || + ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn= ))) { + return false; + } + return true; +} + +static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, + void *opaque, int state, int secstate, + int crm, int opc1, int opc2, + const char *name) +{ + /* + * Private utility function for define_one_arm_cp_reg_with_opaque(): + * add a single reginfo struct to the hash table. + */ + uint32_t *key =3D g_new(uint32_t, 1); + ARMCPRegInfo *r2 =3D g_memdup(r, sizeof(ARMCPRegInfo)); + int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0; + int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; + + r2->name =3D g_strdup(name); + /* + * Reset the secure state to the specific incoming state. This is + * necessary as the register may have been defined with both states. + */ + r2->secure =3D secstate; + + if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { + /* + * Register is banked (using both entries in array). + * Overwriting fieldoffset as the array is only used to define + * banked registers but later only fieldoffset is used. + */ + r2->fieldoffset =3D r->bank_fieldoffsets[ns]; + } + + if (state =3D=3D ARM_CP_STATE_AA32) { + if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { + /* + * If the register is banked then we don't need to migrate or + * reset the 32-bit instance in certain cases: + * + * 1) If the register has both 32-bit and 64-bit instances the= n we + * can count on the 64-bit instance taking care of the + * non-secure bank. + * 2) If ARMv8 is enabled then we can count on a 64-bit version + * taking care of the secure bank. This requires that sepa= rate + * 32 and 64-bit definitions are provided. + */ + if ((r->state =3D=3D ARM_CP_STATE_BOTH && ns) || + (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { + r2->type |=3D ARM_CP_ALIAS; + } + } else if ((secstate !=3D r->secure) && !ns) { + /* + * The register is not banked so we only want to allow migrati= on of + * the non-secure instance. + */ + r2->type |=3D ARM_CP_ALIAS; + } + + if (r->state =3D=3D ARM_CP_STATE_BOTH) { + /* We assume it is a cp15 register if the .cp field is left un= set */ + if (r2->cp =3D=3D 0) { + r2->cp =3D 15; + } + +#ifdef HOST_WORDS_BIGENDIAN + if (r2->fieldoffset) { + r2->fieldoffset +=3D sizeof(uint32_t); + } +#endif + } + } + if (state =3D=3D ARM_CP_STATE_AA64) { + /* + * To allow abbreviation of ARMCPRegInfo + * definitions, we treat cp =3D=3D 0 as equivalent to + * the value for "standard guest-visible sysreg". + * STATE_BOTH definitions are also always "standard + * sysreg" in their AArch64 view (the .cp value may + * be non-zero for the benefit of the AArch32 view). + */ + if (r->cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH) { + r2->cp =3D CP_REG_ARM64_SYSREG_CP; + } + *key =3D ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, + r2->opc0, opc1, opc2); + } else { + *key =3D ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); + } + if (opaque) { + r2->opaque =3D opaque; + } + /* + * reginfo passed to helpers is correct for the actual access, + * and is never ARM_CP_STATE_BOTH: + */ + r2->state =3D state; + /* + * Make sure reginfo passed to helpers for wildcarded regs + * has the correct crm/opc1/opc2 for this reg, not CP_ANY: + */ + r2->crm =3D crm; + r2->opc1 =3D opc1; + r2->opc2 =3D opc2; + /* + * By convention, for wildcarded registers only the first + * entry is used for migration; the others are marked as + * ALIAS so we don't try to transfer the register + * multiple times. Special registers (ie NOP/WFI) are + * never migratable and not even raw-accessible. + */ + if ((r->type & ARM_CP_SPECIAL)) { + r2->type |=3D ARM_CP_NO_RAW; + } + if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || + ((r->opc1 =3D=3D CP_ANY) && opc1 !=3D 0) || + ((r->opc2 =3D=3D CP_ANY) && opc2 !=3D 0)) { + r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; + } + + /* + * Check that raw accesses are either forbidden or handled. Note that + * we can't assert this earlier because the setup of fieldoffset for + * banked registers has to be done first. + */ + if (!(r2->type & ARM_CP_NO_RAW)) { + assert(!raw_accessors_invalid(r2)); + } + + /* Overriding of an existing definition must be explicitly requested. = */ + if (!(r->type & ARM_CP_OVERRIDE)) { + ARMCPRegInfo *oldreg; + oldreg =3D g_hash_table_lookup(cpu->cp_regs, key); + if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { + fprintf(stderr, "Register redefined: cp=3D%d %d bit " + "crn=3D%d crm=3D%d opc1=3D%d opc2=3D%d, " + "was %s, now %s\n", r2->cp, 32 + 32 * is64, + r2->crn, r2->crm, r2->opc1, r2->opc2, + oldreg->name, r2->name); + g_assert_not_reached(); + } + } + g_hash_table_insert(cpu->cp_regs, key, r2); +} + +void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, + const ARMCPRegInfo *r, void *opaque) +{ + /* + * Define implementations of coprocessor registers. + * We store these in a hashtable because typically + * there are less than 150 registers in a space which + * is 16*16*16*8*8 =3D 262144 in size. + * Wildcarding is supported for the crm, opc1 and opc2 fields. + * If a register is defined twice then the second definition is + * used, so this can be used to define some generic registers and + * then override them with implementation specific variations. + * At least one of the original and the second definition should + * include ARM_CP_OVERRIDE in its type bits -- this is just a guard + * against accidental use. + * + * The state field defines whether the register is to be + * visible in the AArch32 or AArch64 execution state. If the + * state is set to ARM_CP_STATE_BOTH then we synthesise a + * reginfo structure for the AArch32 view, which sees the lower + * 32 bits of the 64 bit register. + * + * Only registers visible in AArch64 may set r->opc0; opc0 cannot + * be wildcarded. AArch64 registers are always considered to be 64 + * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of + * the register, if any. + */ + int crm, opc1, opc2, state; + int crmmin =3D (r->crm =3D=3D CP_ANY) ? 0 : r->crm; + int crmmax =3D (r->crm =3D=3D CP_ANY) ? 15 : r->crm; + int opc1min =3D (r->opc1 =3D=3D CP_ANY) ? 0 : r->opc1; + int opc1max =3D (r->opc1 =3D=3D CP_ANY) ? 7 : r->opc1; + int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2; + int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2; + /* 64 bit registers have only CRm and Opc1 fields */ + assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); + /* op0 only exists in the AArch64 encodings */ + assert((r->state !=3D ARM_CP_STATE_AA32) || (r->opc0 =3D=3D 0)); + /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ + assert((r->state !=3D ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); + /* + * This API is only for Arm's system coprocessors (14 and 15) or + * (M-profile or v7A-and-earlier only) for implementation defined + * coprocessors in the range 0..7. Our decode assumes this, since + * 8..13 can be used for other insns including VFP and Neon. See + * valid_cp() in translate.c. Assert here that we haven't tried + * to use an invalid coprocessor number. + */ + switch (r->state) { + case ARM_CP_STATE_BOTH: + /* 0 has a special meaning, but otherwise the same rules as AA32. = */ + if (r->cp =3D=3D 0) { + break; + } + /* fall through */ + case ARM_CP_STATE_AA32: + if (arm_feature(&cpu->env, ARM_FEATURE_V8) && + !arm_feature(&cpu->env, ARM_FEATURE_M)) { + assert(r->cp >=3D 14 && r->cp <=3D 15); + } else { + assert(r->cp < 8 || (r->cp >=3D 14 && r->cp <=3D 15)); + } + break; + case ARM_CP_STATE_AA64: + assert(r->cp =3D=3D 0 || r->cp =3D=3D CP_REG_ARM64_SYSREG_CP); + break; + default: + g_assert_not_reached(); + } + /* + * The AArch64 pseudocode CheckSystemAccess() specifies that op1 + * encodes a minimum access level for the register. We roll this + * runtime check into our general permission check code, so check + * here that the reginfo's specified permissions are strict enough + * to encompass the generic architectural permission check. + */ + if (r->state !=3D ARM_CP_STATE_AA32) { + int mask =3D 0; + switch (r->opc1) { + case 0: + /* min_EL EL1, but some accessible to EL0 via kernel ABI */ + mask =3D PL0U_R | PL1_RW; + break; + case 1: case 2: + /* min_EL EL1 */ + mask =3D PL1_RW; + break; + case 3: + /* min_EL EL0 */ + mask =3D PL0_RW; + break; + case 4: + case 5: + /* min_EL EL2 */ + mask =3D PL2_RW; + break; + case 6: + /* min_EL EL3 */ + mask =3D PL3_RW; + break; + case 7: + /* min_EL EL1, secure mode only (we don't check the latter) */ + mask =3D PL1_RW; + break; + default: + /* broken reginfo with out-of-range opc1 */ + assert(false); + break; + } + /* assert our permissions are not too lax (stricter is fine) */ + assert((r->access & ~mask) =3D=3D 0); + } + + /* + * Check that the register definition has enough info to handle + * reads and writes if they are permitted. + */ + if (!(r->type & (ARM_CP_SPECIAL | ARM_CP_CONST))) { + if (r->access & PL3_R) { + assert((r->fieldoffset || + (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || + r->readfn); + } + if (r->access & PL3_W) { + assert((r->fieldoffset || + (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || + r->writefn); + } + } + /* Bad type field probably means missing sentinel at end of reg list */ + assert(cptype_valid(r->type)); + for (crm =3D crmmin; crm <=3D crmmax; crm++) { + for (opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { + for (opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { + for (state =3D ARM_CP_STATE_AA32; + state <=3D ARM_CP_STATE_AA64; state++) { + if (r->state !=3D state && r->state !=3D ARM_CP_STATE_= BOTH) { + continue; + } + if (state =3D=3D ARM_CP_STATE_AA32) { + /* + * Under AArch32 CP registers can be common + * (same for secure and non-secure world) or banke= d. + */ + char *name; + + switch (r->secure) { + case ARM_CP_SECSTATE_S: + case ARM_CP_SECSTATE_NS: + add_cpreg_to_hashtable(cpu, r, opaque, state, + r->secure, crm, opc1, o= pc2, + r->name); + break; + default: + name =3D g_strdup_printf("%s_S", r->name); + add_cpreg_to_hashtable(cpu, r, opaque, state, + ARM_CP_SECSTATE_S, + crm, opc1, opc2, name); + g_free(name); + add_cpreg_to_hashtable(cpu, r, opaque, state, + ARM_CP_SECSTATE_NS, + crm, opc1, opc2, r->nam= e); + break; + } + } else { + /* + * AArch64 registers get mapped to non-secure + * instance of AArch32 + */ + add_cpreg_to_hashtable(cpu, r, opaque, state, + ARM_CP_SECSTATE_NS, + crm, opc1, opc2, r->name); + } + } + } + } + } +} + +void define_arm_cp_regs_with_opaque(ARMCPU *cpu, + const ARMCPRegInfo *regs, void *opaque) +{ + /* Define a whole list of registers */ + const ARMCPRegInfo *r; + for (r =3D regs; r->type !=3D ARM_CP_SENTINEL; r++) { + define_one_arm_cp_reg_with_opaque(cpu, r, opaque); + } +} + +void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Helper coprocessor write function for write-ignore registers */ +} + +uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* Helper coprocessor write function for read-as-zero registers */ + return 0; +} + +void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) +{ + /* Helper coprocessor reset function for do-nothing-on-reset registers= */ +} diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 17dc0d4255..9e616a15e1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -26,6 +26,7 @@ #include "qapi/error.h" #include "qapi/visitor.h" #include "cpu.h" +#include "cpregs.h" #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" #endif /* CONFIG_TCG */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d561dc7acc..5354069c63 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -32,7 +32,7 @@ #include "kvm_arm.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" - +#include "cpregs.h" =20 #ifndef CONFIG_USER_ONLY static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *= ri) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 2e0e508f0e..d973239d78 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -18,6 +18,7 @@ #if !defined(CONFIG_USER_ONLY) #include "hw/boards.h" #endif +#include "cpregs.h" =20 /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) diff --git a/target/arm/cpustate-list.c b/target/arm/cpustate-list.c new file mode 100644 index 0000000000..7885806f78 --- /dev/null +++ b/target/arm/cpustate-list.c @@ -0,0 +1,146 @@ +/* + * ARM CPUState list read/write + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "cpregs.h" + +uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + assert(ri->fieldoffset); + if (cpreg_field_is_64bit(ri)) { + return CPREG_FIELD64(env, ri); + } else { + return CPREG_FIELD32(env, ri); + } +} + +void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + assert(ri->fieldoffset); + if (cpreg_field_is_64bit(ri)) { + CPREG_FIELD64(env, ri) =3D value; + } else { + CPREG_FIELD32(env, ri) =3D value; + } +} + +const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp) +{ + return g_hash_table_lookup(cpregs, &encoded_cp); +} + +uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* Raw read of a coprocessor register (as needed for migration, etc). = */ + if (ri->type & ARM_CP_CONST) { + return ri->resetvalue; + } else if (ri->raw_readfn) { + return ri->raw_readfn(env, ri); + } else if (ri->readfn) { + return ri->readfn(env, ri); + } else { + return raw_read(env, ri); + } +} + +static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t v) +{ + /* Raw write of a coprocessor register (as needed for migration, etc). + * Note that constant registers are treated as write-ignored; the + * caller should check for success by whether a readback gives the + * value written. + */ + if (ri->type & ARM_CP_CONST) { + return; + } else if (ri->raw_writefn) { + ri->raw_writefn(env, ri, v); + } else if (ri->writefn) { + ri->writefn(env, ri, v); + } else { + raw_write(env, ri, v); + } +} + +bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync) +{ + /* Write the coprocessor state from cpu->env to the (index,value) list= . */ + int i; + bool ok =3D true; + + for (i =3D 0; i < cpu->cpreg_array_len; i++) { + uint32_t regidx =3D kvm_to_cpreg_id(cpu->cpreg_indexes[i]); + const ARMCPRegInfo *ri; + uint64_t newval; + + ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + if (!ri) { + ok =3D false; + continue; + } + if (ri->type & ARM_CP_NO_RAW) { + continue; + } + + newval =3D read_raw_cp_reg(&cpu->env, ri); + if (kvm_sync) { + /* + * Only sync if the previous list->cpustate sync succeeded. + * Rather than tracking the success/failure state for every + * item in the list, we just recheck "does the raw write we mu= st + * have made in write_list_to_cpustate() read back OK" here. + */ + uint64_t oldval =3D cpu->cpreg_values[i]; + + if (oldval =3D=3D newval) { + continue; + } + + write_raw_cp_reg(&cpu->env, ri, oldval); + if (read_raw_cp_reg(&cpu->env, ri) !=3D oldval) { + continue; + } + + write_raw_cp_reg(&cpu->env, ri, newval); + } + cpu->cpreg_values[i] =3D newval; + } + return ok; +} + +bool write_list_to_cpustate(ARMCPU *cpu) +{ + int i; + bool ok =3D true; + + for (i =3D 0; i < cpu->cpreg_array_len; i++) { + uint32_t regidx =3D kvm_to_cpreg_id(cpu->cpreg_indexes[i]); + uint64_t v =3D cpu->cpreg_values[i]; + const ARMCPRegInfo *ri; + + ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + if (!ri) { + ok =3D false; + continue; + } + if (ri->type & ARM_CP_NO_RAW) { + continue; + } + /* Write value and confirm it reads back as written + * (to catch read-only registers and partially read-only + * registers where the incoming migration value doesn't match) + */ + write_raw_cp_reg(&cpu->env, ri, v); + if (read_raw_cp_reg(&cpu->env, ri) !=3D v) { + ok =3D false; + } + } + return ok; +} diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index a8fff2a3d0..0645415f44 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/gdbstub.h" +#include "cpregs.h" =20 typedef struct RegisterSysregXmlParam { CPUState *cs; diff --git a/target/arm/machine.c b/target/arm/machine.c index 6ad1d306b1..e568662cca 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -5,6 +5,7 @@ #include "kvm_arm.h" #include "internals.h" #include "migration/cpu.h" +#include "cpregs.h" =20 static bool vfp_needed(void *opaque) { diff --git a/target/arm/tcg/cpregs.c b/target/arm/tcg/cpregs.c new file mode 100644 index 0000000000..8422da4335 --- /dev/null +++ b/target/arm/tcg/cpregs.c @@ -0,0 +1,7674 @@ +/* + * ARM CP registers + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "trace.h" +#include "qemu/main-loop.h" +#include "exec/exec-all.h" +#include "hw/irq.h" +#include "qapi/error.h" +#include "qemu/guest-random.h" +#include "cpu-mmu.h" +#include "cpregs.h" + +#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ +#define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */ + +static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return (char *)env + ri->fieldoffset; +} + +static void add_cpreg_to_list(gpointer key, gpointer opaque) +{ + ARMCPU *cpu =3D opaque; + uint64_t regidx; + const ARMCPRegInfo *ri; + + regidx =3D *(uint32_t *)key; + ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + + if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { + cpu->cpreg_indexes[cpu->cpreg_array_len] =3D cpreg_to_kvm_id(regid= x); + /* The value array need not be initialized at this point */ + cpu->cpreg_array_len++; + } +} + +static void count_cpreg(gpointer key, gpointer opaque) +{ + ARMCPU *cpu =3D opaque; + uint64_t regidx; + const ARMCPRegInfo *ri; + + regidx =3D *(uint32_t *)key; + ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + + if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { + cpu->cpreg_array_len++; + } +} + +static gint cpreg_key_compare(gconstpointer a, gconstpointer b) +{ + uint64_t aidx =3D cpreg_to_kvm_id(*(uint32_t *)a); + uint64_t bidx =3D cpreg_to_kvm_id(*(uint32_t *)b); + + if (aidx > bidx) { + return 1; + } + if (aidx < bidx) { + return -1; + } + return 0; +} + +void init_cpreg_list(ARMCPU *cpu) +{ + /* + * Initialise the cpreg_tuples[] array based on the cp_regs hash. + * Note that we require cpreg_tuples[] to be sorted by key ID. + */ + GList *keys; + int arraylen; + + keys =3D g_hash_table_get_keys(cpu->cp_regs); + keys =3D g_list_sort(keys, cpreg_key_compare); + + cpu->cpreg_array_len =3D 0; + + g_list_foreach(keys, count_cpreg, cpu); + + arraylen =3D cpu->cpreg_array_len; + cpu->cpreg_indexes =3D g_new(uint64_t, arraylen); + cpu->cpreg_values =3D g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_indexes =3D g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_values =3D g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_array_len =3D cpu->cpreg_array_len; + cpu->cpreg_array_len =3D 0; + + g_list_foreach(keys, add_cpreg_to_list, cpu); + + assert(cpu->cpreg_array_len =3D=3D arraylen); + + g_list_free(keys); +} + +/* + * Some registers are not accessible from AArch32 EL3 if SCR.NS =3D=3D 0. + */ +static CPAccessResult access_el3_aa32ns(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + if (!is_a64(env) && arm_current_el(env) =3D=3D 3 && + arm_is_secure_below_el3(env)) { + return CP_ACCESS_TRAP_UNCATEGORIZED; + } + return CP_ACCESS_OK; +} + +/* + * Some secure-only AArch32 registers trap to EL3 if used from + * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). + * Note that an access from Secure EL1 can only happen if EL3 is AArch64. + * We assume that the .access field is set to PL1_RW. + */ +static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 3) { + return CP_ACCESS_OK; + } + if (arm_is_secure_below_el3(env)) { + if (env->cp15.scr_el3 & SCR_EEL2) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_TRAP_EL3; + } + /* This will be EL1 NS and EL2 NS, which just UNDEF */ + return CP_ACCESS_TRAP_UNCATEGORIZED; +} + +static uint64_t arm_mdcr_el2_eff(CPUARMState *env) +{ + return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0; +} + +/* + * Check for traps to "powerdown debug" registers, which are controlled + * by MDCR.TDOSA + */ +static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + int el =3D arm_current_el(env); + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); + bool mdcr_el2_tdosa =3D (mdcr_el2 & MDCR_TDOSA) || (mdcr_el2 & MDCR_TD= E) || + (arm_hcr_el2_eff(env) & HCR_TGE); + + if (el < 2 && mdcr_el2_tdosa) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +/* + * Check for traps to "debug ROM" registers, which are controlled + * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. + */ +static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); + bool mdcr_el2_tdra =3D (mdcr_el2 & MDCR_TDRA) || (mdcr_el2 & MDCR_TDE)= || + (arm_hcr_el2_eff(env) & HCR_TGE); + + if (el < 2 && mdcr_el2_tdra) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +/* + * Check for traps to general debug registers, which are controlled + * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. + */ +static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); + bool mdcr_el2_tda =3D (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) || + (arm_hcr_el2_eff(env) & HCR_TGE); + + if (el < 2 && mdcr_el2_tda) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +/* + * Check for traps to performance monitor registers, which are controlled + * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. + */ +static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); + + if (el < 2 && (mdcr_el2 & MDCR_TPM)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +/* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ +static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1) { + uint64_t trap =3D isread ? HCR_TRVM : HCR_TVM; + if (arm_hcr_el2_eff(env) & trap) { + return CP_ACCESS_TRAP_EL2; + } + } + return CP_ACCESS_OK; +} + +/* Check for traps from EL1 due to HCR_EL2.TSW. */ +static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + +/* Check for traps from EL1 due to HCR_EL2.TACR. */ +static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TACR))= { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + +/* Check for traps from EL1 due to HCR_EL2.TTLB. */ +static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TTLB))= { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + +static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + raw_write(env, ri, value); + tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ +} + +static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + if (raw_read(env, ri) !=3D value) { + /* + * Unlike real hardware the qemu TLB uses virtual addresses, + * not modified virtual addresses, so this causes a TLB flush. + */ + tlb_flush(CPU(cpu)); + raw_write(env, ri, value); + } +} + +static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + if (raw_read(env, ri) !=3D value && !arm_feature(env, ARM_FEATURE_PMSA) + && !extended_addresses_enabled(env)) { + /* + * For VMSA (when not using the LPAE long descriptor page table + * format) this register includes the ASID, so do a TLB flush. + * For PMSA it is purely a process ID and no action is needed. + */ + tlb_flush(CPU(cpu)); + } + raw_write(env, ri, value); +} + +/* IS variants of TLB operations must affect all cores */ +static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + + tlb_flush_all_cpus_synced(cs); +} + +static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + + tlb_flush_all_cpus_synced(cs); +} + +static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + + tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); +} + +static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + + tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); +} + +/* + * Non-IS variants of TLB operations are upgraded to + * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to + * force broadcast of these operations. + */ +static bool tlb_force_broadcast(CPUARMState *env) +{ + return arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_FB); +} + +static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate all (TLBIALL) */ + CPUState *cs =3D env_cpu(env); + + if (tlb_force_broadcast(env)) { + tlb_flush_all_cpus_synced(cs); + } else { + tlb_flush(cs); + } +} + +static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ + CPUState *cs =3D env_cpu(env); + + value &=3D TARGET_PAGE_MASK; + if (tlb_force_broadcast(env)) { + tlb_flush_page_all_cpus_synced(cs, value); + } else { + tlb_flush_page(cs, value); + } +} + +static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate by ASID (TLBIASID) */ + CPUState *cs =3D env_cpu(env); + + if (tlb_force_broadcast(env)) { + tlb_flush_all_cpus_synced(cs); + } else { + tlb_flush(cs); + } +} + +static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ + CPUState *cs =3D env_cpu(env); + + value &=3D TARGET_PAGE_MASK; + if (tlb_force_broadcast(env)) { + tlb_flush_page_all_cpus_synced(cs, value); + } else { + tlb_flush_page(cs, value); + } +} + +static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + + tlb_flush_by_mmuidx(cs, + ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0); +} + +static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + + tlb_flush_by_mmuidx_all_cpus_synced(cs, + ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0); +} + + +static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); +} + +static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); +} + +static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); + + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); +} + +static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); + + tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, + ARMMMUIdxBit_E2); +} + +static const ARMCPRegInfo cp_reginfo[] =3D { + /* + * Define the secure and non-secure FCSE identifier CP registers + * separately because there is no secure bank in V8 (no _EL3). This a= llows + * the secure register to be properly reset and migrated. There is als= o no + * v8 EL1 version of the register so the non-secure instance stands al= one. + */ + { .name =3D "FCSEIDR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_NS, + .fieldoffset =3D offsetof(CPUARMState, cp15.fcseidr_ns), + .resetvalue =3D 0, .writefn =3D fcse_write, .raw_writefn =3D raw_wri= te, }, + { .name =3D "FCSEIDR_S", + .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_S, + .fieldoffset =3D offsetof(CPUARMState, cp15.fcseidr_s), + .resetvalue =3D 0, .writefn =3D fcse_write, .raw_writefn =3D raw_wri= te, }, + /* + * Define the secure and non-secure context identifier CP registers + * separately because there is no secure bank in V8 (no _EL3). This a= llows + * the secure register to be properly reset and migrated. In the + * non-secure case, the 32-bit register will have reset and migration + * disabled during registration as it is handled by the 64-bit instanc= e. + */ + { .name =3D "CONTEXTIDR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .secure =3D ARM_CP_SECSTATE_NS, + .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[1]), + .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, + { .name =3D "CONTEXTIDR_S", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .secure =3D ARM_CP_SECSTATE_S, + .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_s), + .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { + /* + * NB: Some of these registers exist in v8 but with more precise + * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginf= o[]). + */ + /* MMU Domain access control / MPU write buffer control */ + { .name =3D "DACR", + .cp =3D 15, .opc1 =3D CP_ANY, .crn =3D 3, .crm =3D CP_ANY, .opc2 =3D= CP_ANY, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, + .writefn =3D dacr_write, .raw_writefn =3D raw_write, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dacr_s), + offsetoflow32(CPUARMState, cp15.dacr_ns) } }, + /* + * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. + * For v6 and v5, these mappings are overly broad. + */ + { .name =3D "TLB_LOCKDOWN", .cp =3D 15, .crn =3D 10, .crm =3D 0, + .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_NOP }, + { .name =3D "TLB_LOCKDOWN", .cp =3D 15, .crn =3D 10, .crm =3D 1, + .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_NOP }, + { .name =3D "TLB_LOCKDOWN", .cp =3D 15, .crn =3D 10, .crm =3D 4, + .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_NOP }, + { .name =3D "TLB_LOCKDOWN", .cp =3D 15, .crn =3D 10, .crm =3D 8, + .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_NOP }, + /* Cache maintenance ops; some of this space may be overridden later. = */ + { .name =3D "CACHEMAINT", .cp =3D 15, .crn =3D 7, .crm =3D CP_ANY, + .opc1 =3D 0, .opc2 =3D CP_ANY, .access =3D PL1_W, + .type =3D ARM_CP_NOP | ARM_CP_OVERRIDE }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo not_v6_cp_reginfo[] =3D { + /* + * Not all pre-v6 cores implemented this WFI, so this is slightly + * over-broad. + */ + { .name =3D "WFI_v5", .cp =3D 15, .crn =3D 7, .crm =3D 8, .opc1 =3D 0,= .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_WFI }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { + /* + * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which + * is UNPREDICTABLE; we choose to NOP as most implementations do). + */ + { .name =3D "WFI_v6", .cp =3D 15, .crn =3D 7, .crm =3D 0, .opc1 =3D 0,= .opc2 =3D 4, + .access =3D PL1_W, .type =3D ARM_CP_WFI }, + /* + * L1 cache lockdown. Not architectural in v6 and earlier but in pract= ice + * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM a= nd + * OMAPCP will override this space. + */ + { .name =3D "DLOCKDOWN", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 0, + .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_d= ata), + .resetvalue =3D 0 }, + { .name =3D "ILOCKDOWN", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 1, + .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_i= nsn), + .resetvalue =3D 0 }, + /* v6 doesn't have the cache ID registers but Linux reads them anyway = */ + { .name =3D "DUMMY", .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, = .opc2 =3D CP_ANY, + .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, + .resetvalue =3D 0 }, + /* + * We don't implement pre-v7 debug but most CPUs had at least a DBGDID= R; + * implementing it as RAZ means the "debug architecture version" bits + * will read as a reserved value, which should cause Linux to not try + * to use the debug hardware. + */ + { .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, + .access =3D PL0_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + /* + * MMU TLB control. Note that the wildcarding means we cover not just + * the unified TLB ops but also the dside/iside/inner-shareable varian= ts. + */ + { .name =3D "TLBIALL", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, + .opc1 =3D CP_ANY, .opc2 =3D 0, .access =3D PL1_W, .writefn =3D tlbia= ll_write, + .type =3D ARM_CP_NO_RAW }, + { .name =3D "TLBIMVA", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, + .opc1 =3D CP_ANY, .opc2 =3D 1, .access =3D PL1_W, .writefn =3D tlbim= va_write, + .type =3D ARM_CP_NO_RAW }, + { .name =3D "TLBIASID", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, + .opc1 =3D CP_ANY, .opc2 =3D 2, .access =3D PL1_W, .writefn =3D tlbia= sid_write, + .type =3D ARM_CP_NO_RAW }, + { .name =3D "TLBIMVAA", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, + .opc1 =3D CP_ANY, .opc2 =3D 3, .access =3D PL1_W, .writefn =3D tlbim= vaa_write, + .type =3D ARM_CP_NO_RAW }, + { .name =3D "PRRR", .cp =3D 15, .crn =3D 10, .crm =3D 2, + .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, + { .name =3D "NMRR", .cp =3D 15, .crn =3D 10, .crm =3D 2, + .opc1 =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, + REGINFO_SENTINEL +}; + +static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint32_t mask =3D 0; + + /* In ARMv8 most bits of CPACR_EL1 are RES0. */ + if (!arm_feature(env, ARM_FEATURE_V8)) { + /* + * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. + * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. + * TRCDIS [28] is RAZ/WI since we do not implement a trace macroce= ll. + */ + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { + /* VFP coprocessor: cp10 & cp11 [23:20] */ + mask |=3D (1 << 31) | (1 << 30) | (0xf << 20); + + if (!arm_feature(env, ARM_FEATURE_NEON)) { + /* ASEDIS [31] bit is RAO/WI */ + value |=3D (1 << 31); + } + + /* + * VFPv3 and upwards with NEON implement 32 double precision + * registers (D0-D31). + */ + if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { + /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ + value |=3D (1 << 30); + } + } + value &=3D mask; + } + + /* + * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR= .CP10 + * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. + */ + if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && + !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { + value &=3D ~(0xf << 20); + value |=3D env->cp15.cpacr_el1 & (0xf << 20); + } + + env->cp15.cpacr_el1 =3D value; +} + +static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* + * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR= .CP10 + * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. + */ + uint64_t value =3D env->cp15.cpacr_el1; + + if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && + !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { + value &=3D ~(0xf << 20); + } + return value; +} + + +static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* + * Call cpacr_write() so that we reset with the correct RAO bits set + * for our CPU features. + */ + cpacr_write(env, ri, 0); +} + +static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + if (arm_feature(env, ARM_FEATURE_V8)) { + /* Check if CPACR accesses are to be trapped to EL2 */ + if (arm_current_el(env) =3D=3D 1 && arm_is_el2_enabled(env) && + (env->cp15.cptr_el[2] & CPTR_TCPAC)) { + return CP_ACCESS_TRAP_EL2; + /* Check if CPACR accesses are to be trapped to EL3 */ + } else if (arm_current_el(env) < 3 && + (env->cp15.cptr_el[3] & CPTR_TCPAC)) { + return CP_ACCESS_TRAP_EL3; + } + } + + return CP_ACCESS_OK; +} + +static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + /* Check if CPTR accesses are set to trap to EL3 */ + if (arm_current_el(env) =3D=3D 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC= )) { + return CP_ACCESS_TRAP_EL3; + } + + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo v6_cp_reginfo[] =3D { + /* prefetch by MVA in v6, NOP in v7 */ + { .name =3D "MVA_prefetch", + .cp =3D 15, .crn =3D 7, .crm =3D 13, .opc1 =3D 0, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NOP }, + /* + * We need to break the TB after ISB to execute self-modifying code + * correctly and also to take any pending interrupts immediately. + * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. + */ + { .name =3D "ISB", .cp =3D 15, .crn =3D 7, .crm =3D 5, .opc1 =3D 0, .o= pc2 =3D 4, + .access =3D PL0_W, .type =3D ARM_CP_NO_RAW, .writefn =3D arm_cp_writ= e_ignore }, + { .name =3D "DSB", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 =3D 0, .= opc2 =3D 4, + .access =3D PL0_W, .type =3D ARM_CP_NOP }, + { .name =3D "DMB", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 =3D 0, .= opc2 =3D 5, + .access =3D PL0_W, .type =3D ARM_CP_NOP }, + { .name =3D "IFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ifar_s), + offsetof(CPUARMState, cp15.ifar_ns) }, + .resetvalue =3D 0, }, + /* + * Watchpoint Fault Address Register : should actually only be present + * for 1136, 1176, 11MPCore. + */ + { .name =3D "WFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, }, + { .name =3D "CPACR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, + .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .accessfn =3D cpac= r_access, + .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.cpac= r_el1), + .resetfn =3D cpacr_reset, .writefn =3D cpacr_write, .readfn =3D cpac= r_read }, + REGINFO_SENTINEL +}; + +/* Definitions for the PMU registers */ +#define PMCRN_MASK 0xf800 +#define PMCRN_SHIFT 11 +#define PMCRLC 0x40 +#define PMCRDP 0x20 +#define PMCRX 0x10 +#define PMCRD 0x8 +#define PMCRC 0x4 +#define PMCRP 0x2 +#define PMCRE 0x1 +/* + * Mask of PMCR bits writeable by guest (not including WO bits like C, P, + * which can be written as 1 to trigger behaviour but which stay RAZ). + */ +#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) + +#define PMXEVTYPER_P 0x80000000 +#define PMXEVTYPER_U 0x40000000 +#define PMXEVTYPER_NSK 0x20000000 +#define PMXEVTYPER_NSU 0x10000000 +#define PMXEVTYPER_NSH 0x08000000 +#define PMXEVTYPER_M 0x04000000 +#define PMXEVTYPER_MT 0x02000000 +#define PMXEVTYPER_EVTCOUNT 0x0000ffff +#define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NS= K | \ + PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ + PMXEVTYPER_M | PMXEVTYPER_MT | \ + PMXEVTYPER_EVTCOUNT) + +#define PMCCFILTR 0xf8000000 +#define PMCCFILTR_M PMXEVTYPER_M +#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) + +static inline uint32_t pmu_num_counters(CPUARMState *env) +{ + return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; +} + +/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ +static inline uint64_t pmu_counter_mask(CPUARMState *env) +{ + return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); +} + +typedef struct pm_event { + uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ + /* If the event is supported on this CPU (used to generate PMCEID[01])= */ + bool (*supported)(CPUARMState *); + /* + * Retrieve the current count of the underlying event. The programmed + * counters hold a difference from the return value from this function + */ + uint64_t (*get_count)(CPUARMState *); + /* + * Return how many nanoseconds it will take (at a minimum) for count e= vents + * to occur. A negative value indicates the counter will never overflo= w, or + * that the counter has otherwise arranged for the overflow bit to be = set + * and the PMU interrupt to be raised on overflow. + */ + int64_t (*ns_per_count)(uint64_t); +} pm_event; + +static bool event_always_supported(CPUARMState *env) +{ + return true; +} + +static uint64_t swinc_get_count(CPUARMState *env) +{ + /* + * SW_INCR events are written directly to the pmevcntr's by writes to + * PMSWINC, so there is no underlying count maintained by the PMU itse= lf + */ + return 0; +} + +static int64_t swinc_ns_per(uint64_t ignored) +{ + return -1; +} + +/* + * Return the underlying cycle count for the PMU cycle counters. If we're = in + * usermode, simply return 0. + */ +static uint64_t cycles_get_count(CPUARMState *env) +{ +#ifndef CONFIG_USER_ONLY + return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); +#else + return cpu_get_host_ticks(); +#endif +} + +#ifndef CONFIG_USER_ONLY +static int64_t cycles_ns_per(uint64_t cycles) +{ + return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles; +} + +static bool instructions_supported(CPUARMState *env) +{ + return icount_enabled() =3D=3D 1; /* Precise instruction counting */ +} + +static uint64_t instructions_get_count(CPUARMState *env) +{ + return (uint64_t)icount_get_raw(); +} + +static int64_t instructions_ns_per(uint64_t icount) +{ + return icount_to_ns((int64_t)icount); +} +#endif + +static bool pmu_8_1_events_supported(CPUARMState *env) +{ + /* For events which are supported in any v8.1 PMU */ + return cpu_isar_feature(any_pmu_8_1, env_archcpu(env)); +} + +static bool pmu_8_4_events_supported(CPUARMState *env) +{ + /* For events which are supported in any v8.1 PMU */ + return cpu_isar_feature(any_pmu_8_4, env_archcpu(env)); +} + +static uint64_t zero_event_get_count(CPUARMState *env) +{ + /* For events which on QEMU never fire, so their count is always zero = */ + return 0; +} + +static int64_t zero_event_ns_per(uint64_t cycles) +{ + /* An event which never fires can never overflow */ + return -1; +} + +static const pm_event pm_events[] =3D { + { .number =3D 0x000, /* SW_INCR */ + .supported =3D event_always_supported, + .get_count =3D swinc_get_count, + .ns_per_count =3D swinc_ns_per, + }, +#ifndef CONFIG_USER_ONLY + { .number =3D 0x008, /* INST_RETIRED, Instruction architecturally exec= uted */ + .supported =3D instructions_supported, + .get_count =3D instructions_get_count, + .ns_per_count =3D instructions_ns_per, + }, + { .number =3D 0x011, /* CPU_CYCLES, Cycle */ + .supported =3D event_always_supported, + .get_count =3D cycles_get_count, + .ns_per_count =3D cycles_ns_per, + }, +#endif + { .number =3D 0x023, /* STALL_FRONTEND */ + .supported =3D pmu_8_1_events_supported, + .get_count =3D zero_event_get_count, + .ns_per_count =3D zero_event_ns_per, + }, + { .number =3D 0x024, /* STALL_BACKEND */ + .supported =3D pmu_8_1_events_supported, + .get_count =3D zero_event_get_count, + .ns_per_count =3D zero_event_ns_per, + }, + { .number =3D 0x03c, /* STALL */ + .supported =3D pmu_8_4_events_supported, + .get_count =3D zero_event_get_count, + .ns_per_count =3D zero_event_ns_per, + }, +}; + +/* + * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range = of + * events (i.e. the statistical profiling extension), this implementation + * should first be updated to something sparse instead of the current + * supported_event_map[] array. + */ +#define MAX_EVENT_ID 0x3c +#define UNSUPPORTED_EVENT UINT16_MAX +static uint16_t supported_event_map[MAX_EVENT_ID + 1]; + +/* + * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a= map + * of ARM event numbers to indices in our pm_events array. + * + * Note: Events in the 0x40XX range are not currently supported. + */ +void pmu_init(ARMCPU *cpu) +{ + unsigned int i; + + /* + * Empty supported_event_map and cpu->pmceid[01] before adding support= ed + * events to them + */ + for (i =3D 0; i < ARRAY_SIZE(supported_event_map); i++) { + supported_event_map[i] =3D UNSUPPORTED_EVENT; + } + cpu->pmceid0 =3D 0; + cpu->pmceid1 =3D 0; + + for (i =3D 0; i < ARRAY_SIZE(pm_events); i++) { + const pm_event *cnt =3D &pm_events[i]; + assert(cnt->number <=3D MAX_EVENT_ID); + /* We do not currently support events in the 0x40xx range */ + assert(cnt->number <=3D 0x3f); + + if (cnt->supported(&cpu->env)) { + supported_event_map[cnt->number] =3D i; + uint64_t event_mask =3D 1ULL << (cnt->number & 0x1f); + if (cnt->number & 0x20) { + cpu->pmceid1 |=3D event_mask; + } else { + cpu->pmceid0 |=3D event_mask; + } + } + } +} + +/* + * Check at runtime whether a PMU event is supported for the current machi= ne + */ +static bool event_supported(uint16_t number) +{ + if (number > MAX_EVENT_ID) { + return false; + } + return supported_event_map[number] !=3D UNSUPPORTED_EVENT; +} + +static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + /* Performance monitor registers user accessibility is controlled + * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable + * trapping to EL2 or EL3 for other accesses. + */ + int el =3D arm_current_el(env); + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); + + if (el =3D=3D 0 && !(env->cp15.c9_pmuserenr & 1)) { + return CP_ACCESS_TRAP; + } + if (el < 2 && (mdcr_el2 & MDCR_TPM)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { + return CP_ACCESS_TRAP_EL3; + } + + return CP_ACCESS_OK; +} + +static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* ER: event counter read trap control */ + if (arm_feature(env, ARM_FEATURE_V8) + && arm_current_el(env) =3D=3D 0 + && (env->cp15.c9_pmuserenr & (1 << 3)) !=3D 0 + && isread) { + return CP_ACCESS_OK; + } + + return pmreg_access(env, ri, isread); +} + +static CPAccessResult pmreg_access_swinc(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* SW: software increment write trap control */ + if (arm_feature(env, ARM_FEATURE_V8) + && arm_current_el(env) =3D=3D 0 + && (env->cp15.c9_pmuserenr & (1 << 1)) !=3D 0 + && !isread) { + return CP_ACCESS_OK; + } + + return pmreg_access(env, ri, isread); +} + +static CPAccessResult pmreg_access_selr(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* ER: event counter read trap control */ + if (arm_feature(env, ARM_FEATURE_V8) + && arm_current_el(env) =3D=3D 0 + && (env->cp15.c9_pmuserenr & (1 << 3)) !=3D 0) { + return CP_ACCESS_OK; + } + + return pmreg_access(env, ri, isread); +} + +static CPAccessResult pmreg_access_ccntr(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* CR: cycle counter read trap control */ + if (arm_feature(env, ARM_FEATURE_V8) + && arm_current_el(env) =3D=3D 0 + && (env->cp15.c9_pmuserenr & (1 << 2)) !=3D 0 + && isread) { + return CP_ACCESS_OK; + } + + return pmreg_access(env, ri, isread); +} + +/* Returns true if the counter (pass 31 for PMCCNTR) should count events u= sing + * the current EL, security state, and register configuration. + */ +static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) +{ + uint64_t filter; + bool e, p, u, nsk, nsu, nsh, m; + bool enabled, prohibited, filtered; + bool secure =3D arm_is_secure(env); + int el =3D arm_current_el(env); + uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); + uint8_t hpmn =3D mdcr_el2 & MDCR_HPMN; + + if (!arm_feature(env, ARM_FEATURE_PMU)) { + return false; + } + + if (!arm_feature(env, ARM_FEATURE_EL2) || + (counter < hpmn || counter =3D=3D 31)) { + e =3D env->cp15.c9_pmcr & PMCRE; + } else { + e =3D mdcr_el2 & MDCR_HPME; + } + enabled =3D e && (env->cp15.c9_pmcnten & (1 << counter)); + + if (!secure) { + if (el =3D=3D 2 && (counter < hpmn || counter =3D=3D 31)) { + prohibited =3D mdcr_el2 & MDCR_HPMD; + } else { + prohibited =3D false; + } + } else { + prohibited =3D arm_feature(env, ARM_FEATURE_EL3) && + !(env->cp15.mdcr_el3 & MDCR_SPME); + } + + if (prohibited && counter =3D=3D 31) { + prohibited =3D env->cp15.c9_pmcr & PMCRDP; + } + + if (counter =3D=3D 31) { + filter =3D env->cp15.pmccfiltr_el0; + } else { + filter =3D env->cp15.c14_pmevtyper[counter]; + } + + p =3D filter & PMXEVTYPER_P; + u =3D filter & PMXEVTYPER_U; + nsk =3D arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); + nsu =3D arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); + nsh =3D arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); + m =3D arm_el_is_aa64(env, 1) && + arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); + + if (el =3D=3D 0) { + filtered =3D secure ? u : u !=3D nsu; + } else if (el =3D=3D 1) { + filtered =3D secure ? p : p !=3D nsk; + } else if (el =3D=3D 2) { + filtered =3D !nsh; + } else { /* EL3 */ + filtered =3D m !=3D p; + } + + if (counter !=3D 31) { + /* + * If not checking PMCCNTR, ensure the counter is setup to an even= t we + * support + */ + uint16_t event =3D filter & PMXEVTYPER_EVTCOUNT; + if (!event_supported(event)) { + return false; + } + } + + return enabled && !prohibited && !filtered; +} + +static void pmu_update_irq(CPUARMState *env) +{ + ARMCPU *cpu =3D env_archcpu(env); + qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && + (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); +} + +/* + * Ensure c15_ccnt is the guest-visible count so that operations such as + * enabling/disabling the counter or filtering, modifying the count itself, + * etc. can be done logically. This is essentially a no-op if the counter = is + * not enabled at the time of the call. + */ +static void pmccntr_op_start(CPUARMState *env) +{ + uint64_t cycles =3D cycles_get_count(env); + + if (pmu_counter_enabled(env, 31)) { + uint64_t eff_cycles =3D cycles; + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + eff_cycles /=3D 64; + } + + uint64_t new_pmccntr =3D eff_cycles - env->cp15.c15_ccnt_delta; + + uint64_t overflow_mask =3D env->cp15.c9_pmcr & PMCRLC ? \ + 1ull << 63 : 1ull << 31; + if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { + env->cp15.c9_pmovsr |=3D (1 << 31); + pmu_update_irq(env); + } + + env->cp15.c15_ccnt =3D new_pmccntr; + } + env->cp15.c15_ccnt_delta =3D cycles; +} + +/* + * If PMCCNTR is enabled, recalculate the delta between the clock and the + * guest-visible count. A call to pmccntr_op_finish should follow every ca= ll to + * pmccntr_op_start. + */ +static void pmccntr_op_finish(CPUARMState *env) +{ + if (pmu_counter_enabled(env, 31)) { +#ifndef CONFIG_USER_ONLY + /* Calculate when the counter will next overflow */ + uint64_t remaining_cycles =3D -env->cp15.c15_ccnt; + if (!(env->cp15.c9_pmcr & PMCRLC)) { + remaining_cycles =3D (uint32_t)remaining_cycles; + } + int64_t overflow_in =3D cycles_ns_per(remaining_cycles); + + if (overflow_in > 0) { + int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + overflow_in; + ARMCPU *cpu =3D env_archcpu(env); + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + } +#endif + + uint64_t prev_cycles =3D env->cp15.c15_ccnt_delta; + if (env->cp15.c9_pmcr & PMCRD) { + /* Increment once every 64 processor clock cycles */ + prev_cycles /=3D 64; + } + env->cp15.c15_ccnt_delta =3D prev_cycles - env->cp15.c15_ccnt; + } +} + +static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) +{ + + uint16_t event =3D env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCO= UNT; + uint64_t count =3D 0; + if (event_supported(event)) { + uint16_t event_idx =3D supported_event_map[event]; + count =3D pm_events[event_idx].get_count(env); + } + + if (pmu_counter_enabled(env, counter)) { + uint32_t new_pmevcntr =3D count - env->cp15.c14_pmevcntr_delta[cou= nter]; + + if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & INT32_MIN) { + env->cp15.c9_pmovsr |=3D (1 << counter); + pmu_update_irq(env); + } + env->cp15.c14_pmevcntr[counter] =3D new_pmevcntr; + } + env->cp15.c14_pmevcntr_delta[counter] =3D count; +} + +static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) +{ + if (pmu_counter_enabled(env, counter)) { +#ifndef CONFIG_USER_ONLY + uint16_t event =3D env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_E= VTCOUNT; + uint16_t event_idx =3D supported_event_map[event]; + uint64_t delta =3D UINT32_MAX - + (uint32_t)env->cp15.c14_pmevcntr[counter] + 1; + int64_t overflow_in =3D pm_events[event_idx].ns_per_count(delta); + + if (overflow_in > 0) { + int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + overflow_in; + ARMCPU *cpu =3D env_archcpu(env); + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + } +#endif + + env->cp15.c14_pmevcntr_delta[counter] -=3D + env->cp15.c14_pmevcntr[counter]; + } +} + +void pmu_op_start(CPUARMState *env) +{ + unsigned int i; + pmccntr_op_start(env); + for (i =3D 0; i < pmu_num_counters(env); i++) { + pmevcntr_op_start(env, i); + } +} + +void pmu_op_finish(CPUARMState *env) +{ + unsigned int i; + pmccntr_op_finish(env); + for (i =3D 0; i < pmu_num_counters(env); i++) { + pmevcntr_op_finish(env, i); + } +} + +void pmu_pre_el_change(ARMCPU *cpu, void *ignored) +{ + pmu_op_start(&cpu->env); +} + +void pmu_post_el_change(ARMCPU *cpu, void *ignored) +{ + pmu_op_finish(&cpu->env); +} + +void arm_pmu_timer_cb(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + /* + * Update all the counter values based on the current underlying count= s, + * triggering interrupts to be raised, if necessary. pmu_op_finish() a= lso + * has the effect of setting the cpu->pmu_timer to the next earliest t= ime a + * counter may expire. + */ + pmu_op_start(&cpu->env); + pmu_op_finish(&cpu->env); +} + +static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmu_op_start(env); + + if (value & PMCRC) { + /* The counter has been reset */ + env->cp15.c15_ccnt =3D 0; + } + + if (value & PMCRP) { + unsigned int i; + for (i =3D 0; i < pmu_num_counters(env); i++) { + env->cp15.c14_pmevcntr[i] =3D 0; + } + } + + env->cp15.c9_pmcr &=3D ~PMCR_WRITEABLE_MASK; + env->cp15.c9_pmcr |=3D (value & PMCR_WRITEABLE_MASK); + + pmu_op_finish(env); +} + +static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + unsigned int i; + for (i =3D 0; i < pmu_num_counters(env); i++) { + /* Increment a counter's count iff: */ + if ((value & (1 << i)) && /* counter's bit is set */ + /* counter is enabled and not filtered */ + pmu_counter_enabled(env, i) && + /* counter is SW_INCR */ + (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) =3D=3D = 0x0) { + pmevcntr_op_start(env, i); + + /* + * Detect if this write causes an overflow since we can't pred= ict + * PMSWINC overflows like we can for other events + */ + uint32_t new_pmswinc =3D env->cp15.c14_pmevcntr[i] + 1; + + if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { + env->cp15.c9_pmovsr |=3D (1 << i); + pmu_update_irq(env); + } + + env->cp15.c14_pmevcntr[i] =3D new_pmswinc; + + pmevcntr_op_finish(env, i); + } + } +} + +static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint64_t ret; + pmccntr_op_start(env); + ret =3D env->cp15.c15_ccnt; + pmccntr_op_finish(env); + return ret; +} + +static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and + * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the + * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are + * accessed. + */ + env->cp15.c9_pmselr =3D value & 0x1f; +} + +static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmccntr_op_start(env); + env->cp15.c15_ccnt =3D value; + pmccntr_op_finish(env); +} + +static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t cur_val =3D pmccntr_read(env, NULL); + + pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); +} + +static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmccntr_op_start(env); + env->cp15.pmccfiltr_el0 =3D value & PMCCFILTR_EL0; + pmccntr_op_finish(env); +} + +static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmccntr_op_start(env); + /* M is not accessible from AArch32 */ + env->cp15.pmccfiltr_el0 =3D (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | + (value & PMCCFILTR); + pmccntr_op_finish(env); +} + +static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *r= i) +{ + /* M is not visible in AArch32 */ + return env->cp15.pmccfiltr_el0 & PMCCFILTR; +} + +static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &=3D pmu_counter_mask(env); + env->cp15.c9_pmcnten |=3D value; +} + +static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &=3D pmu_counter_mask(env); + env->cp15.c9_pmcnten &=3D ~value; +} + +static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &=3D pmu_counter_mask(env); + env->cp15.c9_pmovsr &=3D ~value; + pmu_update_irq(env); +} + +static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &=3D pmu_counter_mask(env); + env->cp15.c9_pmovsr |=3D value; + pmu_update_irq(env); +} + +static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value, const uint8_t counter) +{ + if (counter =3D=3D 31) { + pmccfiltr_write(env, ri, value); + } else if (counter < pmu_num_counters(env)) { + pmevcntr_op_start(env, counter); + + /* + * If this counter's event type is changing, store the current + * underlying count for the new type in c14_pmevcntr_delta[counter= ] so + * pmevcntr_op_finish has the correct baseline when it converts ba= ck to + * a delta. + */ + uint16_t old_event =3D env->cp15.c14_pmevtyper[counter] & + PMXEVTYPER_EVTCOUNT; + uint16_t new_event =3D value & PMXEVTYPER_EVTCOUNT; + if (old_event !=3D new_event) { + uint64_t count =3D 0; + if (event_supported(new_event)) { + uint16_t event_idx =3D supported_event_map[new_event]; + count =3D pm_events[event_idx].get_count(env); + } + env->cp15.c14_pmevcntr_delta[counter] =3D count; + } + + env->cp15.c14_pmevtyper[counter] =3D value & PMXEVTYPER_MASK; + pmevcntr_op_finish(env, counter); + } + /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when + * PMSELR value is equal to or greater than the number of implemented + * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. + */ +} + +static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, + const uint8_t counter) +{ + if (counter =3D=3D 31) { + return env->cp15.pmccfiltr_el0; + } else if (counter < pmu_num_counters(env)) { + return env->cp15.c14_pmevtyper[counter]; + } else { + /* + * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER + * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). + */ + return 0; + } +} + +static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + pmevtyper_write(env, ri, value, counter); +} + +static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + env->cp15.c14_pmevtyper[counter] =3D value; + + /* + * pmevtyper_rawwrite is called between a pair of pmu_op_start and + * pmu_op_finish calls when loading saved state for a migration. Becau= se + * we're potentially updating the type of event here, the value writte= n to + * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a + * different counter type. Therefore, we need to set this value to the + * current count for the counter type we're writing so that pmu_op_fin= ish + * has the correct count for its calculation. + */ + uint16_t event =3D value & PMXEVTYPER_EVTCOUNT; + if (event_supported(event)) { + uint16_t event_idx =3D supported_event_map[event]; + env->cp15.c14_pmevcntr_delta[counter] =3D + pm_events[event_idx].get_count(env); + } +} + +static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + return pmevtyper_read(env, ri, counter); +} + +static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); +} + +static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); +} + +static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value, uint8_t counter) +{ + if (counter < pmu_num_counters(env)) { + pmevcntr_op_start(env, counter); + env->cp15.c14_pmevcntr[counter] =3D value; + pmevcntr_op_finish(env, counter); + } + /* + * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR + * are CONSTRAINED UNPREDICTABLE. + */ +} + +static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, + uint8_t counter) +{ + if (counter < pmu_num_counters(env)) { + uint64_t ret; + pmevcntr_op_start(env, counter); + ret =3D env->cp15.c14_pmevcntr[counter]; + pmevcntr_op_finish(env, counter); + return ret; + } else { + /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR + * are CONSTRAINED UNPREDICTABLE. */ + return 0; + } +} + +static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + pmevcntr_write(env, ri, value, counter); +} + +static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + return pmevcntr_read(env, ri, counter); +} + +static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + assert(counter < pmu_num_counters(env)); + env->cp15.c14_pmevcntr[counter] =3D value; + pmevcntr_write(env, ri, value, counter); +} + +static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); + assert(counter < pmu_num_counters(env)); + return env->cp15.c14_pmevcntr[counter]; +} + +static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); +} + +static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); +} + +static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + if (arm_feature(env, ARM_FEATURE_V8)) { + env->cp15.c9_pmuserenr =3D value & 0xf; + } else { + env->cp15.c9_pmuserenr =3D value & 1; + } +} + +static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* We have no event counters so only the C bit can be changed */ + value &=3D pmu_counter_mask(env); + env->cp15.c9_pminten |=3D value; + pmu_update_irq(env); +} + +static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &=3D pmu_counter_mask(env); + env->cp15.c9_pminten &=3D ~value; + pmu_update_irq(env); +} + +static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Note that even though the AArch64 view of this register has bits + * [10:0] all RES0 we can only mask the bottom 5, to comply with the + * architectural requirements for bits which are RES0 only in some + * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 + * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP= .) + */ + raw_write(env, ri, value & ~0x1FULL); +} + +static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +{ + /* Begin with base v8.0 state. */ + uint32_t valid_mask =3D 0x3fff; + ARMCPU *cpu =3D env_archcpu(env); + + if (ri->state =3D=3D ARM_CP_STATE_AA64) { + if (arm_feature(env, ARM_FEATURE_AARCH64) && + !cpu_isar_feature(aa64_aa32_el1, cpu)) { + value |=3D SCR_FW | SCR_AW; /* these two bits are RES1. = */ + } + valid_mask &=3D ~SCR_NET; + + if (cpu_isar_feature(aa64_lor, cpu)) { + valid_mask |=3D SCR_TLOR; + } + if (cpu_isar_feature(aa64_pauth, cpu)) { + valid_mask |=3D SCR_API | SCR_APK; + } + if (cpu_isar_feature(aa64_sel2, cpu)) { + valid_mask |=3D SCR_EEL2; + } + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |=3D SCR_ATA; + } + } else { + valid_mask &=3D ~(SCR_RW | SCR_ST); + } + + if (!arm_feature(env, ARM_FEATURE_EL2)) { + valid_mask &=3D ~SCR_HCE; + + /* On ARMv7, SMD (or SCD as it is called in v7) is only + * supported if EL2 exists. The bit is UNK/SBZP when + * EL2 is unavailable. In QEMU ARMv7, we force it to always zero + * when EL2 is unavailable. + * On ARMv8, this bit is always available. + */ + if (arm_feature(env, ARM_FEATURE_V7) && + !arm_feature(env, ARM_FEATURE_V8)) { + valid_mask &=3D ~SCR_SMD; + } + } + + /* Clear all-context RES0 bits. */ + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* + * scr_write will set the RES1 bits on an AArch64-only CPU. + * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise. + */ + scr_write(env, ri, 0); +} + +static CPAccessResult access_aa64_tid2(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TID2))= { + return CP_ACCESS_TRAP_EL2; + } + + return CP_ACCESS_OK; +} + +static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D env_archcpu(env); + + /* Acquire the CSSELR index from the bank corresponding to the CCSIDR + * bank + */ + uint32_t index =3D A32_BANKED_REG_GET(env, csselr, + ri->secure & ARM_CP_SECSTATE_S); + + return cpu->ccsidr[index]; +} + +static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + raw_write(env, ri, value & 0xf); +} + +static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + CPUState *cs =3D env_cpu(env); + bool el1 =3D arm_current_el(env) =3D=3D 1; + uint64_t hcr_el2 =3D el1 ? arm_hcr_el2_eff(env) : 0; + uint64_t ret =3D 0; + + if (hcr_el2 & HCR_IMO) { + if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { + ret |=3D CPSR_I; + } + } else { + if (cs->interrupt_request & CPU_INTERRUPT_HARD) { + ret |=3D CPSR_I; + } + } + + if (hcr_el2 & HCR_FMO) { + if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { + ret |=3D CPSR_F; + } + } else { + if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { + ret |=3D CPSR_F; + } + } + + /* External aborts are not possible in QEMU so A bit is always clear */ + return ret; +} + +static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TID1))= { + return CP_ACCESS_TRAP_EL2; + } + + return CP_ACCESS_OK; +} + +static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + if (arm_feature(env, ARM_FEATURE_V8)) { + return access_aa64_tid1(env, ri, isread); + } + + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo v7_cp_reginfo[] =3D { + /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ + { .name =3D "NOP", .cp =3D 15, .crn =3D 7, .crm =3D 0, .opc1 =3D 0, .o= pc2 =3D 4, + .access =3D PL1_W, .type =3D ARM_CP_NOP }, + /* Performance monitors are implementation defined in v7, + * but with an ARM recommended set of registers, which we + * follow. + * + * Performance registers fall into three categories: + * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) + * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) + * (c) UNDEF in PL0 if PMUSERENR.EN=3D=3D0, otherwise accessible (all= others) + * For the cases controlled by PMUSERENR we must set .access to PL0_RW + * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. + */ + { .name =3D "PMCNTENSET", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 1, + .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), + .writefn =3D pmcntenset_write, + .accessfn =3D pmreg_access, + .raw_writefn =3D raw_write }, + { .name =3D "PMCNTENSET_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 1, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue= =3D 0, + .writefn =3D pmcntenset_write, .raw_writefn =3D raw_write }, + { .name =3D "PMCNTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 2, + .access =3D PL0_RW, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), + .accessfn =3D pmreg_access, + .writefn =3D pmcntenclr_write, + .type =3D ARM_CP_ALIAS }, + { .name =3D "PMCNTENCLR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 2, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), + .writefn =3D pmcntenclr_write }, + { .name =3D "PMOVSR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 3, + .access =3D PL0_RW, .type =3D ARM_CP_IO, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), + .accessfn =3D pmreg_access, + .writefn =3D pmovsr_write, + .raw_writefn =3D raw_write }, + { .name =3D "PMOVSCLR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 3, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), + .writefn =3D pmovsr_write, + .raw_writefn =3D raw_write }, + { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, + .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .writefn =3D pmswinc_write }, + { .name =3D "PMSWINC_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 4, + .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .writefn =3D pmswinc_write }, + { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, + .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmselr), + .accessfn =3D pmreg_access_selr, .writefn =3D pmselr_write, + .raw_writefn =3D raw_write}, + { .name =3D "PMSELR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 5, + .access =3D PL0_RW, .accessfn =3D pmreg_access_selr, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmselr), + .writefn =3D pmselr_write, .raw_writefn =3D raw_write, }, + { .name =3D "PMCCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 =3D = 0, .opc2 =3D 0, + .access =3D PL0_RW, .resetvalue =3D 0, .type =3D ARM_CP_ALIAS | ARM_= CP_IO, + .readfn =3D pmccntr_read, .writefn =3D pmccntr_write32, + .accessfn =3D pmreg_access_ccntr }, + { .name =3D "PMCCNTR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 0, + .access =3D PL0_RW, .accessfn =3D pmreg_access_ccntr, + .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_ccnt), + .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, + .raw_readfn =3D raw_read, .raw_writefn =3D raw_write, }, + { .name =3D "PMCCFILTR", .cp =3D 15, .opc1 =3D 0, .crn =3D 14, .crm = =3D 15, .opc2 =3D 7, + .writefn =3D pmccfiltr_write_a32, .readfn =3D pmccfiltr_read_a32, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .resetvalue =3D 0, }, + { .name =3D "PMCCFILTR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 15, .opc2 =3D 7, + .writefn =3D pmccfiltr_write, .raw_writefn =3D raw_write, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.pmccfiltr_el0), + .resetvalue =3D 0, }, + { .name =3D "PMXEVTYPER", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 1, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access, + .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, + { .name =3D "PMXEVTYPER_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 1, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access, + .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, + { .name =3D "PMXEVCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 2, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access_xevcntr, + .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, + { .name =3D "PMXEVCNTR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 2, + .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D pmreg_access_xevcntr, + .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, + { .name =3D "PMUSERENR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 0, + .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmuserenr), + .resetvalue =3D 0, + .writefn =3D pmuserenr_write, .raw_writefn =3D raw_write }, + { .name =3D "PMUSERENR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 14, .opc2 =3D 0, + .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, .type =3D ARM_= CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmuserenr), + .resetvalue =3D 0, + .writefn =3D pmuserenr_write, .raw_writefn =3D raw_write }, + { .name =3D "PMINTENSET", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tpm, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pminten), + .resetvalue =3D 0, + .writefn =3D pmintenset_write, .raw_writefn =3D raw_write }, + { .name =3D "PMINTENSET_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tpm, + .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), + .writefn =3D pmintenset_write, .raw_writefn =3D raw_write, + .resetvalue =3D 0x0 }, + { .name =3D "PMINTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_tpm, + .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), + .writefn =3D pmintenclr_write, }, + { .name =3D "PMINTENCLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_tpm, + .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), + .writefn =3D pmintenclr_write }, + { .name =3D "CCSIDR", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 0, + .access =3D PL1_R, + .accessfn =3D access_aa64_tid2, + .readfn =3D ccsidr_read, .type =3D ARM_CP_NO_RAW }, + { .name =3D "CSSELR", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, + .accessfn =3D access_aa64_tid2, + .writefn =3D csselr_write, .resetvalue =3D 0, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.csselr_s), + offsetof(CPUARMState, cp15.csselr_ns) } }, + /* Auxiliary ID register: this actually has an IMPDEF value but for now + * just RAZ for all cores: + */ + { .name =3D "AIDR", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 7, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid1, + .resetvalue =3D 0 }, + /* Auxiliary fault status registers: these also are IMPDEF, and we + * choose to RAZ/WI for all cores. + */ + { .name =3D "AFSR0_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "AFSR1_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + /* MAIR can just read-as-written because we don't implement caches + * and so don't need to care about memory attributes. + */ + { .name =3D "MAIR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, cp15.mair_el[1]), + .resetvalue =3D 0 }, + { .name =3D "MAIR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, + .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[3]), + .resetvalue =3D 0 }, + /* For non-long-descriptor page tables these are PRRR and NMRR; + * regardless they still act as reads-as-written for QEMU. + */ + /* MAIR0/1 are defined separately from their 64-bit counterpart which + * allows them to assign the correct fieldoffset based on the endiann= ess + * handled in the field definitions. + */ + { .name =3D "MAIR0", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.mair0_s), + offsetof(CPUARMState, cp15.mair0_ns) }, + .resetfn =3D arm_cp_reset_ignore }, + { .name =3D "MAIR1", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.mair1_s), + offsetof(CPUARMState, cp15.mair1_ns) }, + .resetfn =3D arm_cp_reset_ignore }, + { .name =3D "ISR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_R, .readfn =3D isr_read }, + /* 32 bit ITLB invalidates */ + { .name =3D "ITLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 5, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiall_write }, + { .name =3D "ITLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 5, .opc2 =3D 1, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_write }, + { .name =3D "ITLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 5, .opc2 =3D 2, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiasid_write }, + /* 32 bit DTLB invalidates */ + { .name =3D "DTLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 6, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiall_write }, + { .name =3D "DTLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 6, .opc2 =3D 1, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_write }, + { .name =3D "DTLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 6, .opc2 =3D 2, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiasid_write }, + /* 32 bit TLB invalidates */ + { .name =3D "TLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7= , .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiall_write }, + { .name =3D "TLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7= , .opc2 =3D 1, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_write }, + { .name =3D "TLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 2, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiasid_write }, + { .name =3D "TLBIMVAA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 3, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimvaa_write }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo v7mp_cp_reginfo[] =3D { + /* 32 bit TLB invalidates, Inner Shareable */ + { .name =3D "TLBIALLIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 3, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiall_is_write }, + { .name =3D "TLBIMVAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 3, .opc2 =3D 1, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_is_write }, + { .name =3D "TLBIASIDIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 2, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiasid_is_write }, + { .name =3D "TLBIMVAAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 3, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimvaa_is_write }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { + /* PMOVSSET is not implemented in v7 before v7ve */ + { .name =3D "PMOVSSET", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D = 14, .opc2 =3D 3, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), + .writefn =3D pmovsset_write, + .raw_writefn =3D raw_write }, + { .name =3D "PMOVSSET_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 14, .opc2 =3D 3, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), + .writefn =3D pmovsset_write, + .raw_writefn =3D raw_write }, + REGINFO_SENTINEL +}; + +static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + value &=3D 1; + env->teecr =3D value; +} + +static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *= ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 0 && (env->teecr & 1)) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo t2ee_cp_reginfo[] =3D { + { .name =3D "TEECR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D 6, = .opc2 =3D 0, + .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, teecr), + .resetvalue =3D 0, + .writefn =3D teecr_write }, + { .name =3D "TEEHBR", .cp =3D 14, .crn =3D 1, .crm =3D 0, .opc1 =3D 6,= .opc2 =3D 0, + .access =3D PL0_RW, .fieldoffset =3D offsetof(CPUARMState, teehbr), + .accessfn =3D teehbr_access, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo v6k_cp_reginfo[] =3D { + { .name =3D "TPIDR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 2, .crn =3D 13, .crm =3D 0, + .access =3D PL0_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalu= e =3D 0 }, + { .name =3D "TPIDRURW", .cp =3D 15, .crn =3D 13, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 2, + .access =3D PL0_RW, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidrurw_s), + offsetoflow32(CPUARMState, cp15.tpidrurw_ns) = }, + .resetfn =3D arm_cp_reset_ignore }, + { .name =3D "TPIDRRO_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 3, .crn =3D 13, .crm =3D 0, + .access =3D PL0_R|PL1_W, + .fieldoffset =3D offsetof(CPUARMState, cp15.tpidrro_el[0]), + .resetvalue =3D 0}, + { .name =3D "TPIDRURO", .cp =3D 15, .crn =3D 13, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 3, + .access =3D PL0_R|PL1_W, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidruro_s), + offsetoflow32(CPUARMState, cp15.tpidruro_ns) = }, + .resetfn =3D arm_cp_reset_ignore }, + { .name =3D "TPIDR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 4, .crn =3D 13, .crm =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalu= e =3D 0 }, + { .name =3D "TPIDRPRW", .opc1 =3D 0, .cp =3D 15, .crn =3D 13, .crm =3D= 0, .opc2 =3D 4, + .access =3D PL1_RW, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidrprw_s), + offsetoflow32(CPUARMState, cp15.tpidrprw_ns) = }, + .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +#ifndef CONFIG_USER_ONLY + +static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + /* + * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. + * Writable only at the highest implemented exception level. + */ + int el =3D arm_current_el(env); + uint64_t hcr; + uint32_t cntkctl; + + switch (el) { + case 0: + hcr =3D arm_hcr_el2_eff(env); + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + cntkctl =3D env->cp15.cnthctl_el2; + } else { + cntkctl =3D env->cp15.c14_cntkctl; + } + if (!extract32(cntkctl, 0, 2)) { + return CP_ACCESS_TRAP; + } + break; + case 1: + if (!isread && ri->state =3D=3D ARM_CP_STATE_AA32 && + arm_is_secure_below_el3(env)) { + /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) = */ + return CP_ACCESS_TRAP_UNCATEGORIZED; + } + break; + case 2: + case 3: + break; + } + + if (!isread && el < arm_highest_el(env)) { + return CP_ACCESS_TRAP_UNCATEGORIZED; + } + + return CP_ACCESS_OK; +} + +static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, + bool isread) +{ + unsigned int cur_el =3D arm_current_el(env); + bool has_el2 =3D arm_is_el2_enabled(env); + uint64_t hcr =3D arm_hcr_el2_eff(env); + + switch (cur_el) { + case 0: + /* If HCR_EL2. =3D=3D '11': check CNTHCTL_EL2.EL0[PV]CTEN= . */ + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + return (extract32(env->cp15.cnthctl_el2, timeridx, 1) + ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); + } + + /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */ + if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) { + return CP_ACCESS_TRAP; + } + + /* If HCR_EL2. =3D=3D '10': check CNTHCTL_EL2.EL1PCTEN. */ + if (hcr & HCR_E2H) { + if (timeridx =3D=3D GTIMER_PHYS && + !extract32(env->cp15.cnthctl_el2, 10, 1)) { + return CP_ACCESS_TRAP_EL2; + } + } else { + /* If HCR_EL2. =3D=3D 0: check CNTHCTL_EL2.EL1PCEN. */ + if (has_el2 && timeridx =3D=3D GTIMER_PHYS && + !extract32(env->cp15.cnthctl_el2, 1, 1)) { + return CP_ACCESS_TRAP_EL2; + } + } + break; + + case 1: + /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H= . */ + if (has_el2 && timeridx =3D=3D GTIMER_PHYS && + (hcr & HCR_E2H + ? !extract32(env->cp15.cnthctl_el2, 10, 1) + : !extract32(env->cp15.cnthctl_el2, 0, 1))) { + return CP_ACCESS_TRAP_EL2; + } + break; + } + return CP_ACCESS_OK; +} + +static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, + bool isread) +{ + unsigned int cur_el =3D arm_current_el(env); + bool has_el2 =3D arm_is_el2_enabled(env); + uint64_t hcr =3D arm_hcr_el2_eff(env); + + switch (cur_el) { + case 0: + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + /* If HCR_EL2. =3D=3D '11': check CNTHCTL_EL2.EL0[PV]= TEN. */ + return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1) + ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); + } + + /* + * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from + * EL0 if EL0[PV]TEN is zero. + */ + if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { + return CP_ACCESS_TRAP; + } + /* fall through */ + + case 1: + if (has_el2 && timeridx =3D=3D GTIMER_PHYS) { + if (hcr & HCR_E2H) { + /* If HCR_EL2. =3D=3D '10': check CNTHCTL_EL2.EL1= PTEN. */ + if (!extract32(env->cp15.cnthctl_el2, 11, 1)) { + return CP_ACCESS_TRAP_EL2; + } + } else { + /* If HCR_EL2. =3D=3D 0: check CNTHCTL_EL2.EL1PCEN. */ + if (!extract32(env->cp15.cnthctl_el2, 1, 1)) { + return CP_ACCESS_TRAP_EL2; + } + } + } + break; + } + return CP_ACCESS_OK; +} + +static CPAccessResult gt_pct_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + return gt_counter_access(env, GTIMER_PHYS, isread); +} + +static CPAccessResult gt_vct_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + return gt_counter_access(env, GTIMER_VIRT, isread); +} + +static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + return gt_timer_access(env, GTIMER_PHYS, isread); +} + +static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + return gt_timer_access(env, GTIMER_VIRT, isread); +} + +static CPAccessResult gt_stimer_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* + * The AArch64 register view of the secure physical timer is + * always accessible from EL3, and configurably accessible from + * Secure EL1. + */ + switch (arm_current_el(env)) { + case 1: + if (!arm_is_secure(env)) { + return CP_ACCESS_TRAP; + } + if (!(env->cp15.scr_el3 & SCR_ST)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; + case 0: + case 2: + return CP_ACCESS_TRAP; + case 3: + return CP_ACCESS_OK; + default: + g_assert_not_reached(); + } +} + +static uint64_t gt_get_countervalue(CPUARMState *env) +{ + ARMCPU *cpu =3D env_archcpu(env); + + return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu= ); +} + +static void gt_recalc_timer(ARMCPU *cpu, int timeridx) +{ + ARMGenericTimer *gt =3D &cpu->env.cp15.c14_timer[timeridx]; + + if (gt->ctl & 1) { + /* + * Timer enabled: calculate and set current ISTATUS, irq, and + * reset timer to when ISTATUS next has to change + */ + uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? + cpu->env.cp15.cntvoff_el2 : 0; + uint64_t count =3D gt_get_countervalue(&cpu->env); + /* Note that this must be unsigned 64 bit arithmetic: */ + int istatus =3D count - offset >=3D gt->cval; + uint64_t nexttick; + int irqstate; + + gt->ctl =3D deposit32(gt->ctl, 2, 1, istatus); + + irqstate =3D (istatus && !(gt->ctl & 2)); + qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); + + if (istatus) { + /* Next transition is when count rolls back over to zero */ + nexttick =3D UINT64_MAX; + } else { + /* Next transition is when we hit cval */ + nexttick =3D gt->cval + offset; + } + /* + * Note that the desired next expiry time might be beyond the + * signed-64-bit range of a QEMUTimer -- in this case we just + * set the timer for as far in the future as possible. When the + * timer expires we will reset the timer for any remaining period. + */ + if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { + timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX); + } else { + timer_mod(cpu->gt_timer[timeridx], nexttick); + } + trace_arm_gt_recalc(timeridx, irqstate, nexttick); + } else { + /* Timer disabled: ISTATUS and timer output always clear */ + gt->ctl &=3D ~4; + qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); + timer_del(cpu->gt_timer[timeridx]); + trace_arm_gt_recalc_disabled(timeridx); + } +} + +static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, + int timeridx) +{ + ARMCPU *cpu =3D env_archcpu(env); + + timer_del(cpu->gt_timer[timeridx]); +} + +static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_get_countervalue(env); +} + +static uint64_t gt_virt_cnt_offset(CPUARMState *env) +{ + uint64_t hcr; + + switch (arm_current_el(env)) { + case 2: + hcr =3D arm_hcr_el2_eff(env); + if (hcr & HCR_E2H) { + return 0; + } + break; + case 0: + hcr =3D arm_hcr_el2_eff(env); + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + return 0; + } + break; + } + + return env->cp15.cntvoff_el2; +} + +static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_get_countervalue(env) - gt_virt_cnt_offset(env); +} + +static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + int timeridx, + uint64_t value) +{ + trace_arm_gt_cval_write(timeridx, value); + env->cp15.c14_timer[timeridx].cval =3D value; + gt_recalc_timer(env_archcpu(env), timeridx); +} + +static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, + int timeridx) +{ + uint64_t offset =3D 0; + + switch (timeridx) { + case GTIMER_VIRT: + case GTIMER_HYPVIRT: + offset =3D gt_virt_cnt_offset(env); + break; + } + + return (uint32_t)(env->cp15.c14_timer[timeridx].cval - + (gt_get_countervalue(env) - offset)); +} + +static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + int timeridx, + uint64_t value) +{ + uint64_t offset =3D 0; + + switch (timeridx) { + case GTIMER_VIRT: + case GTIMER_HYPVIRT: + offset =3D gt_virt_cnt_offset(env); + break; + } + + trace_arm_gt_tval_write(timeridx, value); + env->cp15.c14_timer[timeridx].cval =3D gt_get_countervalue(env) - offs= et + + sextract64(value, 0, 32); + gt_recalc_timer(env_archcpu(env), timeridx); +} + +static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + int timeridx, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + uint32_t oldval =3D env->cp15.c14_timer[timeridx].ctl; + + trace_arm_gt_ctl_write(timeridx, value); + env->cp15.c14_timer[timeridx].ctl =3D deposit64(oldval, 0, 2, value); + if ((oldval ^ value) & 1) { + /* Enable toggled */ + gt_recalc_timer(cpu, timeridx); + } else if ((oldval ^ value) & 2) { + /* + * IMASK toggled: don't need to recalculate, + * just set the interrupt line based on ISTATUS + */ + int irqstate =3D (oldval & 4) && !(value & 2); + + trace_arm_gt_imask_toggle(timeridx, irqstate); + qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); + } +} + +static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + gt_timer_reset(env, ri, GTIMER_PHYS); +} + +static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_cval_write(env, ri, GTIMER_PHYS, value); +} + +static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_tval_read(env, ri, GTIMER_PHYS); +} + +static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_tval_write(env, ri, GTIMER_PHYS, value); +} + +static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_ctl_write(env, ri, GTIMER_PHYS, value); +} + +static int gt_phys_redir_timeridx(CPUARMState *env) +{ + switch (arm_mmu_idx(env)) { + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_SE20_0: + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: + return GTIMER_HYP; + default: + return GTIMER_PHYS; + } +} + +static int gt_virt_redir_timeridx(CPUARMState *env) +{ + switch (arm_mmu_idx(env)) { + case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_SE20_0: + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: + return GTIMER_HYPVIRT; + default: + return GTIMER_VIRT; + } +} + +static uint64_t gt_phys_redir_cval_read(CPUARMState *env, + const ARMCPRegInfo *ri) +{ + int timeridx =3D gt_phys_redir_timeridx(env); + return env->cp15.c14_timer[timeridx].cval; +} + +static void gt_phys_redir_cval_write(CPUARMState *env, const ARMCPRegInfo = *ri, + uint64_t value) +{ + int timeridx =3D gt_phys_redir_timeridx(env); + gt_cval_write(env, ri, timeridx, value); +} + +static uint64_t gt_phys_redir_tval_read(CPUARMState *env, + const ARMCPRegInfo *ri) +{ + int timeridx =3D gt_phys_redir_timeridx(env); + return gt_tval_read(env, ri, timeridx); +} + +static void gt_phys_redir_tval_write(CPUARMState *env, const ARMCPRegInfo = *ri, + uint64_t value) +{ + int timeridx =3D gt_phys_redir_timeridx(env); + gt_tval_write(env, ri, timeridx, value); +} + +static uint64_t gt_phys_redir_ctl_read(CPUARMState *env, + const ARMCPRegInfo *ri) +{ + int timeridx =3D gt_phys_redir_timeridx(env); + return env->cp15.c14_timer[timeridx].ctl; +} + +static void gt_phys_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + int timeridx =3D gt_phys_redir_timeridx(env); + gt_ctl_write(env, ri, timeridx, value); +} + +static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + gt_timer_reset(env, ri, GTIMER_VIRT); +} + +static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_cval_write(env, ri, GTIMER_VIRT, value); +} + +static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_tval_read(env, ri, GTIMER_VIRT); +} + +static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_tval_write(env, ri, GTIMER_VIRT, value); +} + +static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_ctl_write(env, ri, GTIMER_VIRT, value); +} + +static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + trace_arm_gt_cntvoff_write(value); + raw_write(env, ri, value); + gt_recalc_timer(cpu, GTIMER_VIRT); +} + +static uint64_t gt_virt_redir_cval_read(CPUARMState *env, + const ARMCPRegInfo *ri) +{ + int timeridx =3D gt_virt_redir_timeridx(env); + return env->cp15.c14_timer[timeridx].cval; +} + +static void gt_virt_redir_cval_write(CPUARMState *env, const ARMCPRegInfo = *ri, + uint64_t value) +{ + int timeridx =3D gt_virt_redir_timeridx(env); + gt_cval_write(env, ri, timeridx, value); +} + +static uint64_t gt_virt_redir_tval_read(CPUARMState *env, + const ARMCPRegInfo *ri) +{ + int timeridx =3D gt_virt_redir_timeridx(env); + return gt_tval_read(env, ri, timeridx); +} + +static void gt_virt_redir_tval_write(CPUARMState *env, const ARMCPRegInfo = *ri, + uint64_t value) +{ + int timeridx =3D gt_virt_redir_timeridx(env); + gt_tval_write(env, ri, timeridx, value); +} + +static uint64_t gt_virt_redir_ctl_read(CPUARMState *env, + const ARMCPRegInfo *ri) +{ + int timeridx =3D gt_virt_redir_timeridx(env); + return env->cp15.c14_timer[timeridx].ctl; +} + +static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + int timeridx =3D gt_virt_redir_timeridx(env); + gt_ctl_write(env, ri, timeridx, value); +} + +static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + gt_timer_reset(env, ri, GTIMER_HYP); +} + +static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_cval_write(env, ri, GTIMER_HYP, value); +} + +static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_tval_read(env, ri, GTIMER_HYP); +} + +static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_tval_write(env, ri, GTIMER_HYP, value); +} + +static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_ctl_write(env, ri, GTIMER_HYP, value); +} + +static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + gt_timer_reset(env, ri, GTIMER_SEC); +} + +static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_cval_write(env, ri, GTIMER_SEC, value); +} + +static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_tval_read(env, ri, GTIMER_SEC); +} + +static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_tval_write(env, ri, GTIMER_SEC, value); +} + +static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_ctl_write(env, ri, GTIMER_SEC, value); +} + +static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + gt_timer_reset(env, ri, GTIMER_HYPVIRT); +} + +static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_cval_write(env, ri, GTIMER_HYPVIRT, value); +} + +static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return gt_tval_read(env, ri, GTIMER_HYPVIRT); +} + +static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_tval_write(env, ri, GTIMER_HYPVIRT, value); +} + +static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + gt_ctl_write(env, ri, GTIMER_HYPVIRT, value); +} + +void arm_gt_ptimer_cb(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + gt_recalc_timer(cpu, GTIMER_PHYS); +} + +void arm_gt_vtimer_cb(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + gt_recalc_timer(cpu, GTIMER_VIRT); +} + +void arm_gt_htimer_cb(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + gt_recalc_timer(cpu, GTIMER_HYP); +} + +void arm_gt_stimer_cb(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + gt_recalc_timer(cpu, GTIMER_SEC); +} + +void arm_gt_hvtimer_cb(void *opaque) +{ + ARMCPU *cpu =3D opaque; + + gt_recalc_timer(cpu, GTIMER_HYPVIRT); +} + +static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaq= ue) +{ + ARMCPU *cpu =3D env_archcpu(env); + + cpu->env.cp15.c14_cntfrq =3D cpu->gt_cntfrq_hz; +} + +static const ARMCPRegInfo generic_timer_cp_reginfo[] =3D { + /* + * Note that CNTFRQ is purely reads-as-written for the benefit + * of software; writing it doesn't actually change the timer frequency. + * Our reset value matches the fixed frequency we implement the timer = at. + */ + { .name =3D "CNTFRQ", .cp =3D 15, .crn =3D 14, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, + .type =3D ARM_CP_ALIAS, + .access =3D PL1_RW | PL0_R, .accessfn =3D gt_cntfrq_access, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c14_cntfrq), + }, + { .name =3D "CNTFRQ_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW | PL0_R, .accessfn =3D gt_cntfrq_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_cntfrq), + .resetfn =3D arm_gt_cntfrq_reset, + }, + /* overall control: mostly access permissions */ + { .name =3D "CNTKCTL", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_cntkctl), + .resetvalue =3D 0, + }, + /* per-timer control */ + { .name =3D "CNTP_CTL", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D= 0, .opc2 =3D 1, + .secure =3D ARM_CP_SECSTATE_NS, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL0_RW, + .accessfn =3D gt_ptimer_access, + .fieldoffset =3D offsetoflow32(CPUARMState, + cp15.c14_timer[GTIMER_PHYS].ctl), + .readfn =3D gt_phys_redir_ctl_read, .raw_readfn =3D raw_read, + .writefn =3D gt_phys_redir_ctl_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTP_CTL_S", + .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 1, + .secure =3D ARM_CP_SECSTATE_S, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL0_RW, + .accessfn =3D gt_ptimer_access, + .fieldoffset =3D offsetoflow32(CPUARMState, + cp15.c14_timer[GTIMER_SEC].ctl), + .writefn =3D gt_sec_ctl_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTP_CTL_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, + .type =3D ARM_CP_IO, .access =3D PL0_RW, + .accessfn =3D gt_ptimer_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= tl), + .resetvalue =3D 0, + .readfn =3D gt_phys_redir_ctl_read, .raw_readfn =3D raw_read, + .writefn =3D gt_phys_redir_ctl_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTV_CTL", .cp =3D 15, .crn =3D 14, .crm =3D 3, .opc1 =3D= 0, .opc2 =3D 1, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL0_RW, + .accessfn =3D gt_vtimer_access, + .fieldoffset =3D offsetoflow32(CPUARMState, + cp15.c14_timer[GTIMER_VIRT].ctl), + .readfn =3D gt_virt_redir_ctl_read, .raw_readfn =3D raw_read, + .writefn =3D gt_virt_redir_ctl_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTV_CTL_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, + .type =3D ARM_CP_IO, .access =3D PL0_RW, + .accessfn =3D gt_vtimer_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= tl), + .resetvalue =3D 0, + .readfn =3D gt_virt_redir_ctl_read, .raw_readfn =3D raw_read, + .writefn =3D gt_virt_redir_ctl_write, .raw_writefn =3D raw_write, + }, + /* TimerValue views: a 32 bit downcounting view of the underlying stat= e */ + { .name =3D "CNTP_TVAL", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 = =3D 0, .opc2 =3D 0, + .secure =3D ARM_CP_SECSTATE_NS, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, + .accessfn =3D gt_ptimer_access, + .readfn =3D gt_phys_redir_tval_read, .writefn =3D gt_phys_redir_tval= _write, + }, + { .name =3D "CNTP_TVAL_S", + .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, + .secure =3D ARM_CP_SECSTATE_S, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, + .accessfn =3D gt_ptimer_access, + .readfn =3D gt_sec_tval_read, .writefn =3D gt_sec_tval_write, + }, + { .name =3D "CNTP_TVAL_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, + .accessfn =3D gt_ptimer_access, .resetfn =3D gt_phys_timer_reset, + .readfn =3D gt_phys_redir_tval_read, .writefn =3D gt_phys_redir_tval= _write, + }, + { .name =3D "CNTV_TVAL", .cp =3D 15, .crn =3D 14, .crm =3D 3, .opc1 = =3D 0, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, + .accessfn =3D gt_vtimer_access, + .readfn =3D gt_virt_redir_tval_read, .writefn =3D gt_virt_redir_tval= _write, + }, + { .name =3D "CNTV_TVAL_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, + .accessfn =3D gt_vtimer_access, .resetfn =3D gt_virt_timer_reset, + .readfn =3D gt_virt_redir_tval_read, .writefn =3D gt_virt_redir_tval= _write, + }, + /* The counter itself */ + { .name =3D "CNTPCT", .cp =3D 15, .crm =3D 14, .opc1 =3D 0, + .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_I= O, + .accessfn =3D gt_pct_access, + .readfn =3D gt_cnt_read, .resetfn =3D arm_cp_reset_ignore, + }, + { .name =3D "CNTPCT_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 1, + .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D gt_pct_access, .readfn =3D gt_cnt_read, + }, + { .name =3D "CNTVCT", .cp =3D 15, .crm =3D 14, .opc1 =3D 1, + .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_I= O, + .accessfn =3D gt_vct_access, + .readfn =3D gt_virt_cnt_read, .resetfn =3D arm_cp_reset_ignore, + }, + { .name =3D "CNTVCT_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 2, + .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .accessfn =3D gt_vct_access, .readfn =3D gt_virt_cnt_read, + }, + /* Comparison value, indicating when the timer goes off */ + { .name =3D "CNTP_CVAL", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, + .secure =3D ARM_CP_SECSTATE_NS, + .access =3D PL0_RW, + .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), + .accessfn =3D gt_ptimer_access, + .readfn =3D gt_phys_redir_cval_read, .raw_readfn =3D raw_read, + .writefn =3D gt_phys_redir_cval_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTP_CVAL_S", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, + .secure =3D ARM_CP_SECSTATE_S, + .access =3D PL0_RW, + .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cv= al), + .accessfn =3D gt_ptimer_access, + .writefn =3D gt_sec_cval_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTP_CVAL_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, + .access =3D PL0_RW, + .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), + .resetvalue =3D 0, .accessfn =3D gt_ptimer_access, + .readfn =3D gt_phys_redir_cval_read, .raw_readfn =3D raw_read, + .writefn =3D gt_phys_redir_cval_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTV_CVAL", .cp =3D 15, .crm =3D 14, .opc1 =3D 3, + .access =3D PL0_RW, + .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), + .accessfn =3D gt_vtimer_access, + .readfn =3D gt_virt_redir_cval_read, .raw_readfn =3D raw_read, + .writefn =3D gt_virt_redir_cval_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTV_CVAL_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, + .access =3D PL0_RW, + .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), + .resetvalue =3D 0, .accessfn =3D gt_vtimer_access, + .readfn =3D gt_virt_redir_cval_read, .raw_readfn =3D raw_read, + .writefn =3D gt_virt_redir_cval_write, .raw_writefn =3D raw_write, + }, + /* + * Secure timer -- this is actually restricted to only EL3 + * and configurably Secure-EL1 via the accessfn. + */ + { .name =3D "CNTPS_TVAL_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 7, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW, + .accessfn =3D gt_stimer_access, + .readfn =3D gt_sec_tval_read, + .writefn =3D gt_sec_tval_write, + .resetfn =3D gt_sec_timer_reset, + }, + { .name =3D "CNTPS_CTL_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 7, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, + .type =3D ARM_CP_IO, .access =3D PL1_RW, + .accessfn =3D gt_stimer_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ct= l), + .resetvalue =3D 0, + .writefn =3D gt_sec_ctl_write, .raw_writefn =3D raw_write, + }, + { .name =3D "CNTPS_CVAL_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 7, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, + .type =3D ARM_CP_IO, .access =3D PL1_RW, + .accessfn =3D gt_stimer_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cv= al), + .writefn =3D gt_sec_cval_write, .raw_writefn =3D raw_write, + }, + REGINFO_SENTINEL +}; + +static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + +#else + +/* + * In user-mode most of the generic timer registers are inaccessible + * however modern kernels (4.12+) allow access to cntvct_el0 + */ + +static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D env_archcpu(env); + + /* + * Currently we have no support for QEMUTimer in linux-user so we + * can't call gt_get_countervalue(env), instead we directly + * call the lower level functions. + */ + return cpu_get_clock() / gt_cntfrq_period_ns(cpu); +} + +static const ARMCPRegInfo generic_timer_cp_reginfo[] =3D { + { .name =3D "CNTFRQ_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 0, + .type =3D ARM_CP_CONST, .access =3D PL0_R /* no PL1_RW in linux-user= */, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_cntfrq), + .resetvalue =3D NANOSECONDS_PER_SECOND / GTIMER_SCALE, + }, + { .name =3D "CNTVCT_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 2, + .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, + .readfn =3D gt_virt_cnt_read, + }, + REGINFO_SENTINEL +}; + +#endif + +static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +{ + if (arm_feature(env, ARM_FEATURE_LPAE)) { + raw_write(env, ri, value); + } else if (arm_feature(env, ARM_FEATURE_V7)) { + raw_write(env, ri, value & 0xfffff6ff); + } else { + raw_write(env, ri, value & 0xfffff1ff); + } +} + +#ifndef CONFIG_USER_ONLY +/* get_phys_addr() isn't present for user-mode-only targets */ + +static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (ri->opc2 & 4) { + /* + * The ATS12NSO* operations must trap to EL3 or EL2 if executed in + * Secure EL1 (which can only happen if EL3 is AArch64). + * They are simply UNDEF if executed from NS EL1. + * They function normally from EL2 or EL3. + */ + if (arm_current_el(env) =3D=3D 1) { + if (arm_is_secure_below_el3(env)) { + if (env->cp15.scr_el3 & SCR_EEL2) { + return CP_ACCESS_TRAP_UNCATEGORIZED_EL2; + } + return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; + } + return CP_ACCESS_TRAP_UNCATEGORIZED; + } + } + return CP_ACCESS_OK; +} + +static uint64_t do_ats_write(CPUARMState *env, uint64_t value, + MMUAccessType access_type, ARMMMUIdx mmu_idx) +{ + hwaddr phys_addr; + target_ulong page_size; + int prot; + bool ret; + uint64_t par64; + bool format64 =3D false; + MemTxAttrs attrs =3D {}; + ARMMMUFaultInfo fi =3D {}; + ARMCacheAttrs cacheattrs =3D {}; + + ret =3D get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &a= ttrs, + &prot, &page_size, &fi, &cacheattrs); + + if (ret) { + /* + * Some kinds of translation fault must cause exceptions rather + * than being reported in the PAR. + */ + int current_el =3D arm_current_el(env); + int target_el; + uint32_t syn, fsr, fsc; + bool take_exc =3D false; + + if (fi.s1ptw && current_el =3D=3D 1 + && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { + /* + * Synchronous stage 2 fault on an access made as part of the + * translation table walk for AT S1E0* or AT S1E1* insn + * executed from NS EL1. If this is a synchronous external abo= rt + * and SCR_EL3.EA =3D=3D 1, then we take a synchronous externa= l abort + * to EL3. Otherwise the fault is taken as an exception to EL2, + * and HPFAR_EL2 holds the faulting IPA. + */ + if (fi.type =3D=3D ARMFault_SyncExternalOnWalk && + (env->cp15.scr_el3 & SCR_EA)) { + target_el =3D 3; + } else { + env->cp15.hpfar_el2 =3D extract64(fi.s2addr, 12, 47) << 4; + if (arm_is_secure_below_el3(env) && fi.s1ns) { + env->cp15.hpfar_el2 |=3D HPFAR_NS; + } + target_el =3D 2; + } + take_exc =3D true; + } else if (fi.type =3D=3D ARMFault_SyncExternalOnWalk) { + /* + * Synchronous external aborts during a translation table walk + * are taken as Data Abort exceptions. + */ + if (fi.stage2) { + if (current_el =3D=3D 3) { + target_el =3D 3; + } else { + target_el =3D 2; + } + } else { + target_el =3D exception_target_el(env); + } + take_exc =3D true; + } + + if (take_exc) { + /* Construct FSR and FSC using same logic as arm_deliver_fault= () */ + if (target_el =3D=3D 2 || arm_el_is_aa64(env, target_el) || + arm_s1_regime_using_lpae_format(env, mmu_idx)) { + fsr =3D arm_fi_to_lfsc(&fi); + fsc =3D extract32(fsr, 0, 6); + } else { + fsr =3D arm_fi_to_sfsc(&fi); + fsc =3D 0x3f; + } + /* + * Report exception with ESR indicating a fault due to a + * translation table walk for a cache maintenance instruction. + */ + syn =3D syn_data_abort_no_iss(current_el =3D=3D target_el, 0, + fi.ea, 1, fi.s1ptw, 1, fsc); + env->exception.vaddress =3D value; + env->exception.fsr =3D fsr; + raise_exception(env, EXCP_DATA_ABORT, syn, target_el); + } + } + + if (is_a64(env)) { + format64 =3D true; + } else if (arm_feature(env, ARM_FEATURE_LPAE)) { + /* + * ATS1Cxx: + * * TTBCR.EAE determines whether the result is returned using the + * 32-bit or the 64-bit PAR format + * * Instructions executed in Hyp mode always use the 64bit format + * + * ATS1S2NSOxx uses the 64bit format if any of the following is tr= ue: + * * The Non-secure TTBCR.EAE bit is set to 1 + * * The implementation includes EL2, and the value of HCR.VM is 1 + * + * (Note that HCR.DC makes HCR.VM behave as if it is 1.) + * + * ATS1Hx always uses the 64bit format. + */ + format64 =3D arm_s1_regime_using_lpae_format(env, mmu_idx); + + if (arm_feature(env, ARM_FEATURE_EL2)) { + if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || + mmu_idx =3D=3D ARMMMUIdx_E10_1 || + mmu_idx =3D=3D ARMMMUIdx_E10_1_PAN) { + format64 |=3D env->cp15.hcr_el2 & (HCR_VM | HCR_DC); + } else { + format64 |=3D arm_current_el(env) =3D=3D 2; + } + } + } + + if (format64) { + /* Create a 64-bit PAR */ + par64 =3D (1 << 11); /* LPAE bit always set */ + if (!ret) { + par64 |=3D phys_addr & ~0xfffULL; + if (!attrs.secure) { + par64 |=3D (1 << 9); /* NS */ + } + par64 |=3D (uint64_t)cacheattrs.attrs << 56; /* ATTR */ + par64 |=3D cacheattrs.shareability << 7; /* SH */ + } else { + uint32_t fsr =3D arm_fi_to_lfsc(&fi); + + par64 |=3D 1; /* F */ + par64 |=3D (fsr & 0x3f) << 1; /* FS */ + if (fi.stage2) { + par64 |=3D (1 << 9); /* S */ + } + if (fi.s1ptw) { + par64 |=3D (1 << 8); /* PTW */ + } + } + } else { + /* + * fsr is a DFSR/IFSR value for the short descriptor + * translation table format (with WnR always clear). + * Convert it to a 32-bit PAR. + */ + if (!ret) { + /* We do not set any attribute bits in the PAR */ + if (page_size =3D=3D (1 << 24) + && arm_feature(env, ARM_FEATURE_V7)) { + par64 =3D (phys_addr & 0xff000000) | (1 << 1); + } else { + par64 =3D phys_addr & 0xfffff000; + } + if (!attrs.secure) { + par64 |=3D (1 << 9); /* NS */ + } + } else { + uint32_t fsr =3D arm_fi_to_sfsc(&fi); + + par64 =3D ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | + ((fsr & 0xf) << 1) | 1; + } + } + return par64; +} + +static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +{ + MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; + uint64_t par64; + ARMMMUIdx mmu_idx; + int el =3D arm_current_el(env); + bool secure =3D arm_is_secure_below_el3(env); + + switch (ri->opc2 & 6) { + case 0: + /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP= */ + switch (el) { + case 3: + mmu_idx =3D ARMMMUIdx_SE3; + break; + case 2: + g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ + /* fall through */ + case 1: + if (ri->crm =3D=3D 9 && (env->uncached_cpsr & CPSR_PAN)) { + mmu_idx =3D (secure ? ARMMMUIdx_Stage1_SE1_PAN + : ARMMMUIdx_Stage1_E1_PAN); + } else { + mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stag= e1_E1; + } + break; + default: + g_assert_not_reached(); + } + break; + case 2: + /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ + switch (el) { + case 3: + mmu_idx =3D ARMMMUIdx_SE10_0; + break; + case 2: + g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ + mmu_idx =3D ARMMMUIdx_Stage1_E0; + break; + case 1: + mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E= 0; + break; + default: + g_assert_not_reached(); + } + break; + case 4: + /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ + mmu_idx =3D ARMMMUIdx_E10_1; + break; + case 6: + /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ + mmu_idx =3D ARMMMUIdx_E10_0; + break; + default: + g_assert_not_reached(); + } + + par64 =3D do_ats_write(env, value, access_type, mmu_idx); + + A32_BANKED_CURRENT_REG_SET(env, par, par64); +} + +static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; + uint64_t par64; + + par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2); + + A32_BANKED_CURRENT_REG_SET(env, par, par64); +} + +static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 3 && + !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + +static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; + ARMMMUIdx mmu_idx; + int secure =3D arm_is_secure_below_el3(env); + + switch (ri->opc2 & 6) { + case 0: + switch (ri->opc1) { + case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ + if (ri->crm =3D=3D 9 && (env->pstate & PSTATE_PAN)) { + mmu_idx =3D (secure ? ARMMMUIdx_Stage1_SE1_PAN + : ARMMMUIdx_Stage1_E1_PAN); + } else { + mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stag= e1_E1; + } + break; + case 4: /* AT S1E2R, AT S1E2W */ + mmu_idx =3D secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2; + break; + case 6: /* AT S1E3R, AT S1E3W */ + mmu_idx =3D ARMMMUIdx_SE3; + break; + default: + g_assert_not_reached(); + } + break; + case 2: /* AT S1E0R, AT S1E0W */ + mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0; + break; + case 4: /* AT S12E1R, AT S12E1W */ + mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1; + break; + case 6: /* AT S12E0R, AT S12E0W */ + mmu_idx =3D secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0; + break; + default: + g_assert_not_reached(); + } + + env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, mmu_idx); +} +#endif + +static const ARMCPRegInfo vapa_cp_reginfo[] =3D { + { .name =3D "PAR", .cp =3D 15, .crn =3D 7, .crm =3D 4, .opc1 =3D 0, .o= pc2 =3D 0, + .access =3D PL1_RW, .resetvalue =3D 0, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.par_s), + offsetoflow32(CPUARMState, cp15.par_ns) }, + .writefn =3D par_write }, +#ifndef CONFIG_USER_ONLY + /* This underdecoding is safe because the reginfo is NO_RAW. */ + { .name =3D "ATS", .cp =3D 15, .crn =3D 7, .crm =3D 8, .opc1 =3D 0, .o= pc2 =3D CP_ANY, + .access =3D PL1_W, .accessfn =3D ats_access, + .writefn =3D ats_write, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC = }, +#endif + REGINFO_SENTINEL +}; + +/* Return basic MPU access permission bits. */ +static uint32_t simple_mpu_ap_bits(uint32_t val) +{ + uint32_t ret; + uint32_t mask; + int i; + ret =3D 0; + mask =3D 3; + for (i =3D 0; i < 16; i +=3D 2) { + ret |=3D (val >> i) & mask; + mask <<=3D 2; + } + return ret; +} + +/* Pad basic MPU access permission bits to extended format. */ +static uint32_t extended_mpu_ap_bits(uint32_t val) +{ + uint32_t ret; + uint32_t mask; + int i; + ret =3D 0; + mask =3D 3; + for (i =3D 0; i < 16; i +=3D 2) { + ret |=3D (val & mask) << i; + mask <<=3D 2; + } + return ret; +} + +static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.pmsav5_data_ap =3D extended_mpu_ap_bits(value); +} + +static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *= ri) +{ + return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); +} + +static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.pmsav5_insn_ap =3D extended_mpu_ap_bits(value); +} + +static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *= ri) +{ + return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); +} + +static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + uint32_t *u32p =3D *(uint32_t **)raw_ptr(env, ri); + + if (!u32p) { + return 0; + } + + u32p +=3D env->pmsav7.rnr[M_REG_NS]; + return *u32p; +} + +static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + uint32_t *u32p =3D *(uint32_t **)raw_ptr(env, ri); + + if (!u32p) { + return; + } + + u32p +=3D env->pmsav7.rnr[M_REG_NS]; + tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ + *u32p =3D value; +} + +static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + uint32_t nrgs =3D cpu->pmsav7_dregion; + + if (value >=3D nrgs) { + qemu_log_mask(LOG_GUEST_ERROR, + "PMSAv7 RGNR write >=3D # supported regions, %" PRIu= 32 + " > %" PRIu32 "\n", (uint32_t)value, nrgs); + return; + } + + raw_write(env, ri, value); +} + +static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { + /* + * Reset for all these registers is handled in arm_cpu_reset(), + * because the PMSAv7 is also used by M-profile CPUs, which do + * not register cpregs but still need the state to be reset. + */ + { .name =3D "DRBAR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, = .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, pmsav7.drbar), + .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, + .resetfn =3D arm_cp_reset_ignore }, + { .name =3D "DRSR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, .= opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, pmsav7.drsr), + .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, + .resetfn =3D arm_cp_reset_ignore }, + { .name =3D "DRACR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, = .opc2 =3D 4, + .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, + .fieldoffset =3D offsetof(CPUARMState, pmsav7.dracr), + .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, + .resetfn =3D arm_cp_reset_ignore }, + { .name =3D "RGNR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 2, .= opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), + .writefn =3D pmsav7_rgnr_write, + .resetfn =3D arm_cp_reset_ignore }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo pmsav5_cp_reginfo[] =3D { + { .name =3D "DATA_AP", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.pmsav5_data_ap), + .readfn =3D pmsav5_data_ap_read, .writefn =3D pmsav5_data_ap_write, = }, + { .name =3D "INSN_AP", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.pmsav5_insn_ap), + .readfn =3D pmsav5_insn_ap_read, .writefn =3D pmsav5_insn_ap_write, = }, + { .name =3D "DATA_EXT_AP", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.pmsav5_data_ap), + .resetvalue =3D 0, }, + { .name =3D "INSN_EXT_AP", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 3, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.pmsav5_insn_ap), + .resetvalue =3D 0, }, + { .name =3D "DCACHE_CFG", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c2_data), .resetvalue = =3D 0, }, + { .name =3D "ICACHE_CFG", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 1, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c2_insn), .resetvalue = =3D 0, }, + /* Protection region base and size registers */ + { .name =3D "946_PRBS0", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D= 0, + .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[0]) }, + { .name =3D "946_PRBS1", .cp =3D 15, .crn =3D 6, .crm =3D 1, .opc1 =3D= 0, + .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[1]) }, + { .name =3D "946_PRBS2", .cp =3D 15, .crn =3D 6, .crm =3D 2, .opc1 =3D= 0, + .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[2]) }, + { .name =3D "946_PRBS3", .cp =3D 15, .crn =3D 6, .crm =3D 3, .opc1 =3D= 0, + .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[3]) }, + { .name =3D "946_PRBS4", .cp =3D 15, .crn =3D 6, .crm =3D 4, .opc1 =3D= 0, + .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[4]) }, + { .name =3D "946_PRBS5", .cp =3D 15, .crn =3D 6, .crm =3D 5, .opc1 =3D= 0, + .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[5]) }, + { .name =3D "946_PRBS6", .cp =3D 15, .crn =3D 6, .crm =3D 6, .opc1 =3D= 0, + .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[6]) }, + { .name =3D "946_PRBS7", .cp =3D 15, .crn =3D 6, .crm =3D 7, .opc1 =3D= 0, + .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[7]) }, + REGINFO_SENTINEL +}; + +static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + TCR *tcr =3D raw_ptr(env, ri); + int maskshift =3D extract32(value, 0, 3); + + if (!arm_feature(env, ARM_FEATURE_V8)) { + if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { + /* + * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when + * using Long-desciptor translation table format + */ + value &=3D ~((7 << 19) | (3 << 14) | (0xf << 3)); + } else if (arm_feature(env, ARM_FEATURE_EL3)) { + /* + * In an implementation that includes the Security Extensions + * TTBCR has additional fields PD0 [4] and PD1 [5] for + * Short-descriptor translation table format. + */ + value &=3D TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; + } else { + value &=3D TTBCR_N; + } + } + + /* + * Update the masks corresponding to the TCR bank being written + * Note that we always calculate mask and base_mask, but + * they are only used for short-descriptor tables (ie if EAE is 0); + * for long-descriptor tables the TCR fields are used differently + * and the mask and base_mask values are meaningless. + */ + tcr->raw_tcr =3D value; + tcr->mask =3D ~(((uint32_t)0xffffffffu) >> maskshift); + tcr->base_mask =3D ~((uint32_t)0x3fffu >> maskshift); +} + +static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + TCR *tcr =3D raw_ptr(env, ri); + + if (arm_feature(env, ARM_FEATURE_LPAE)) { + /* + * With LPAE the TTBCR could result in a change of ASID + * via the TTBCR.A1 bit, so do a TLB flush. + */ + tlb_flush(CPU(cpu)); + } + /* Preserve the high half of TCR_EL1, set via TTBCR2. */ + value =3D deposit64(tcr->raw_tcr, 0, 32, value); + vmsa_ttbcr_raw_write(env, ri, value); +} + +static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) +{ + TCR *tcr =3D raw_ptr(env, ri); + + /* + * Reset both the TCR as well as the masks corresponding to the bank of + * the TCR being reset. + */ + tcr->raw_tcr =3D 0; + tcr->mask =3D 0; + tcr->base_mask =3D 0xffffc000u; +} + +static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + TCR *tcr =3D raw_ptr(env, ri); + + /* For AArch64 the A1 bit could result in a change of ASID, so TLB flu= sh. */ + tlb_flush(CPU(cpu)); + tcr->raw_tcr =3D value; +} + +static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* If the ASID changes (with a 64-bit write), we must flush the TLB. = */ + if (cpreg_field_is_64bit(ri) && + extract64(raw_read(env, ri) ^ value, 48, 16) !=3D 0) { + ARMCPU *cpu =3D env_archcpu(env); + tlb_flush(CPU(cpu)); + } + raw_write(env, ri, value); +} + +static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + /* + * If we are running with E2&0 regime, then an ASID is active. + * Flush if that might be changing. Note we're not checking + * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that + * holds the active ASID, only checking the field that might. + */ + if (extract64(raw_read(env, ri) ^ value, 48, 16) && + (arm_hcr_el2_eff(env) & HCR_E2H)) { + uint16_t mask =3D ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0; + + if (arm_is_secure_below_el3(env)) { + mask >>=3D ARM_MMU_IDX_A_NS; + } + + tlb_flush_by_mmuidx(env_cpu(env), mask); + } + raw_write(env, ri, value); +} + +static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D CPU(cpu); + + /* + * A change in VMID to the stage2 page table (Stage2) invalidates + * the combined stage 1&2 tlbs (EL10_1 and EL10_0). + */ + if (raw_read(env, ri) !=3D value) { + uint16_t mask =3D ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0; + + if (arm_is_secure_below_el3(env)) { + mask >>=3D ARM_MMU_IDX_A_NS; + } + + tlb_flush_by_mmuidx(cs, mask); + raw_write(env, ri, value); + } +} + +static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { + { .name =3D "DFSR", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .type =3D ARM_CP_= ALIAS, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dfsr_s), + offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, + { .name =3D "IFSR", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.ifsr_s), + offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, + { .name =3D "DFAR", .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 0, .= opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.dfar_s), + offsetof(CPUARMState, cp15.dfar_ns) } }, + { .name =3D "FAR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, cp15.far_el[1]), + .resetvalue =3D 0, }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { + { .name =3D "ESR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .crn =3D 5, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, + { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), + offsetof(CPUARMState, cp15.ttbr0_ns) } }, + { .name =3D "TTBR1_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), + offsetof(CPUARMState, cp15.ttbr1_ns) } }, + { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .writefn =3D vmsa_tcr_el12_write, + .resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D raw_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[1]) }, + { .name =3D "TTBCR", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, = .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_ALIAS, .writefn =3D vmsa_ttbcr_write, + .raw_writefn =3D vmsa_ttbcr_raw_write, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tcr_el[3]), + offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, + REGINFO_SENTINEL +}; + +/* + * Note that unlike TTBCR, writing to TTBCR2 does not require flushing + * qemu tlbs nor adjusting cached masks. + */ +static const ARMCPRegInfo ttbcr2_reginfo =3D { + .name =3D "TTBCR2", .cp =3D 15, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .= opc2 =3D 3, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_ALIAS, + .bank_fieldoffsets =3D { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), + offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, +}; + +static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.c15_ticonfig =3D value & 0xe7; + /* The OS_TYPE bit in this register changes the reported CPUID! */ + env->cp15.c0_cpuid =3D (value & (1 << 5)) ? + ARM_CPUID_TI915T : ARM_CPUID_TI925T; +} + +static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.c15_threadid =3D value & 0xffff; +} + +static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Wait-for-interrupt (deprecated) */ + cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); +} + +static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * On OMAP there are registers indicating the max/min index of dcache = lines + * containing a dirty line; cache flush operations have to reset these. + */ + env->cp15.c15_i_max =3D 0x000; + env->cp15.c15_i_min =3D 0xff0; +} + +static const ARMCPRegInfo omap_cp_reginfo[] =3D { + { .name =3D "DFSR", .cp =3D 15, .crn =3D 5, .crm =3D CP_ANY, + .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_OVERRIDE, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.esr_el[1]), + .resetvalue =3D 0, }, + { .name =3D "", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D 0, .opc= 2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_NOP }, + { .name =3D "TICONFIG", .cp =3D 15, .crn =3D 15, .crm =3D 1, .opc1 =3D= 0, .opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_ticonfig), .resetval= ue =3D 0, + .writefn =3D omap_ticonfig_write }, + { .name =3D "IMAX", .cp =3D 15, .crn =3D 15, .crm =3D 2, .opc1 =3D 0, = .opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = =3D 0, }, + { .name =3D "IMIN", .cp =3D 15, .crn =3D 15, .crm =3D 3, .opc1 =3D 0, = .opc2 =3D 0, + .access =3D PL1_RW, .resetvalue =3D 0xff0, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_i_min) }, + { .name =3D "THREADID", .cp =3D 15, .crn =3D 15, .crm =3D 4, .opc1 =3D= 0, .opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_threadid), .resetval= ue =3D 0, + .writefn =3D omap_threadid_write }, + { .name =3D "TI925T_STATUS", .cp =3D 15, .crn =3D 15, + .crm =3D 8, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, + .type =3D ARM_CP_NO_RAW, + .readfn =3D arm_cp_read_zero, .writefn =3D omap_wfi_write, }, + /* + * TODO: Peripheral port remap register: + * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller + * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), + * when MMU is off. + */ + { .name =3D "OMAP_CACHEMAINT", .cp =3D 15, .crn =3D 7, .crm =3D CP_ANY, + .opc1 =3D 0, .opc2 =3D CP_ANY, .access =3D PL1_W, + .type =3D ARM_CP_OVERRIDE | ARM_CP_NO_RAW, + .writefn =3D omap_cachemaint_write }, + { .name =3D "C9", .cp =3D 15, .crn =3D 9, + .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1= _RW, + .type =3D ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.c15_cpar =3D value & 0x3fff; +} + +static const ARMCPRegInfo xscale_cp_reginfo[] =3D { + { .name =3D "XSCALE_CPAR", + .cp =3D 15, .crn =3D 15, .crm =3D 1, .opc1 =3D 0, .opc2 =3D 0, .acce= ss =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = =3D 0, + .writefn =3D xscale_cpar_write, }, + { .name =3D "XSCALE_AUXCR", + .cp =3D 15, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 1, .acces= s =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c1_xscaleauxcr), + .resetvalue =3D 0, }, + /* + * XScale specific cache-lockdown: since we have no cache we NOP these + * and hope the guest does not really rely on cache behaviour. + */ + { .name =3D "XSCALE_LOCK_ICACHE_LINE", + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NOP }, + { .name =3D "XSCALE_UNLOCK_ICACHE", + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NOP }, + { .name =3D "XSCALE_DCACHE_LOCK", + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_NOP }, + { .name =3D "XSCALE_UNLOCK_DCACHE", + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NOP }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo dummy_c15_cp_reginfo[] =3D { + /* + * RAZ/WI the whole crn=3D15 space, when we don't have a more specific + * implementation of this implementation-defined space. + * Ideally this should eventually disappear in favour of actually + * implementing the correct behaviour for all cores. + */ + { .name =3D "C15_IMPDEF", .cp =3D 15, .crn =3D 15, + .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, + .access =3D PL1_RW, + .type =3D ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, + .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] =3D { + /* Cache status: RAZ because we have no cache so it's always clean */ + { .name =3D "CDSR", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 =3D 0, = .opc2 =3D 6, + .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, + .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo cache_block_ops_cp_reginfo[] =3D { + /* We never have a a block transfer operation in progress */ + { .name =3D "BXSR", .cp =3D 15, .crn =3D 7, .crm =3D 12, .opc1 =3D 0, = .opc2 =3D 4, + .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, + .resetvalue =3D 0 }, + /* The cache ops themselves: these all NOP for QEMU */ + { .name =3D "IICR", .cp =3D 15, .crm =3D 5, .opc1 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + { .name =3D "IDCR", .cp =3D 15, .crm =3D 6, .opc1 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + { .name =3D "CDCR", .cp =3D 15, .crm =3D 12, .opc1 =3D 0, + .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + { .name =3D "PIR", .cp =3D 15, .crm =3D 12, .opc1 =3D 1, + .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + { .name =3D "PDR", .cp =3D 15, .crm =3D 12, .opc1 =3D 2, + .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + { .name =3D "CIDCR", .cp =3D 15, .crm =3D 14, .opc1 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo cache_test_clean_cp_reginfo[] =3D { + /* + * The cache test-and-clean instructions always return (1 << 30) + * to indicate that there are no dirty cache lines. + */ + { .name =3D "TC_DCACHE", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 = =3D 0, .opc2 =3D 3, + .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, + .resetvalue =3D (1 << 30) }, + { .name =3D "TCI_DCACHE", .cp =3D 15, .crn =3D 7, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 3, + .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, + .resetvalue =3D (1 << 30) }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo strongarm_cp_reginfo[] =3D { + /* Ignore ReadBuffer accesses */ + { .name =3D "C9_READBUFFER", .cp =3D 15, .crn =3D 9, + .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, + .access =3D PL1_RW, .resetvalue =3D 0, + .type =3D ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, + REGINFO_SENTINEL +}; + +static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + unsigned int cur_el =3D arm_current_el(env); + + if (arm_is_el2_enabled(env) && cur_el =3D=3D 1) { + return env->cp15.vpidr_el2; + } + return raw_read(env, ri); +} + +static uint64_t mpidr_read_val(CPUARMState *env) +{ + ARMCPU *cpu =3D env_archcpu(env); + uint64_t mpidr =3D cpu->mp_affinity; + + if (arm_feature(env, ARM_FEATURE_V7MP)) { + mpidr |=3D (1U << 31); + /* + * Cores which are uniprocessor (non-coherent) + * but still implement the MP extensions set + * bit 30. (For instance, Cortex-R5). + */ + if (cpu->mp_is_up) { + mpidr |=3D (1u << 30); + } + } + return mpidr; +} + +static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + unsigned int cur_el =3D arm_current_el(env); + + if (arm_is_el2_enabled(env) && cur_el =3D=3D 1) { + return env->cp15.vmpidr_el2; + } + return mpidr_read_val(env); +} + +static const ARMCPRegInfo lpae_cp_reginfo[] =3D { + /* NOP AMAIR0/1 */ + { .name =3D "AMAIR0", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .crn =3D 10, .crm =3D 3, .opc1 =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ + { .name =3D "AMAIR1", .cp =3D 15, .crn =3D 10, .crm =3D 3, .opc1 =3D 0= , .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "PAR", .cp =3D 15, .crm =3D 7, .opc1 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_64BIT, .resetvalue =3D 0, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.par_s), + offsetof(CPUARMState, cp15.par_ns)} }, + { .name =3D "TTBR0", .cp =3D 15, .crm =3D 2, .opc1 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), + offsetof(CPUARMState, cp15.ttbr0_ns) }, + .writefn =3D vmsa_ttbr_write, }, + { .name =3D "TTBR1", .cp =3D 15, .crm =3D 2, .opc1 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), + offsetof(CPUARMState, cp15.ttbr1_ns) }, + .writefn =3D vmsa_ttbr_write, }, + REGINFO_SENTINEL +}; + +static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return vfp_get_fpcr(env); +} + +static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + vfp_set_fpcr(env, value); +} + +static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return vfp_get_fpsr(env); +} + +static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + vfp_set_fpsr(env, value); +} + +static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + +static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->daif =3D value & PSTATE_DAIF; +} + +static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_PAN; +} + +static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate =3D (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN); +} + +static const ARMCPRegInfo pan_reginfo =3D { + .name =3D "PAN", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 2, .opc2 =3D 3, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_RW, + .readfn =3D aa64_pan_read, .writefn =3D aa64_pan_write +}; + +static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_UAO; +} + +static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate =3D (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO); +} + +static const ARMCPRegInfo uao_reginfo =3D { + .name =3D "UAO", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 2, .opc2 =3D 4, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_RW, + .readfn =3D aa64_uao_read, .writefn =3D aa64_uao_write +}; + +static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_DIT; +} + +static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate =3D (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT); +} + +static const ARMCPRegInfo dit_reginfo =3D { + .name =3D "DIT", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 5, + .type =3D ARM_CP_NO_RAW, .access =3D PL0_RW, + .readfn =3D aa64_dit_read, .writefn =3D aa64_dit_write +}; + +static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_SSBS; +} + +static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->pstate =3D (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS); +} + +static const ARMCPRegInfo ssbs_reginfo =3D { + .name =3D "SSBS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 6, + .type =3D ARM_CP_NO_RAW, .access =3D PL0_RW, + .readfn =3D aa64_ssbs_read, .writefn =3D aa64_ssbs_write +}; + +static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* Cache invalidate/clean to Point of Coherency or Persistence... */ + switch (arm_current_el(env)) { + case 0: + /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ + if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { + return CP_ACCESS_TRAP; + } + /* fall through */ + case 1: + /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */ + if (arm_hcr_el2_eff(env) & HCR_TPCP) { + return CP_ACCESS_TRAP_EL2; + } + break; + } + return CP_ACCESS_OK; +} + +static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* Cache invalidate/clean to Point of Unification... */ + switch (arm_current_el(env)) { + case 0: + /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ + if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { + return CP_ACCESS_TRAP; + } + /* fall through */ + case 1: + /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */ + if (arm_hcr_el2_eff(env) & HCR_TPU) { + return CP_ACCESS_TRAP_EL2; + } + break; + } + return CP_ACCESS_OK; +} + +/* + * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions + * Page D4-1736 (DDI0487A.b) + */ + +static int vae1_tlbmask(CPUARMState *env) +{ + uint64_t hcr =3D arm_hcr_el2_eff(env); + uint16_t mask; + + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + mask =3D ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0; + } else { + mask =3D ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0; + } + + if (arm_is_secure_below_el3(env)) { + mask >>=3D ARM_MMU_IDX_A_NS; + } + + return mask; +} + +/* Return 56 if TBI is enabled, 64 otherwise. */ +static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, + uint64_t addr) +{ + uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; + int tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); + int select =3D extract64(addr, 55, 1); + + return (tbi >> select) & 1 ? 56 : 64; +} + +static int vae1_tlbbits(CPUARMState *env, uint64_t addr) +{ + uint64_t hcr =3D arm_hcr_el2_eff(env); + ARMMMUIdx mmu_idx; + + /* Only the regime of the mmu_idx below is significant. */ + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + mmu_idx =3D ARMMMUIdx_E20_0; + } else { + mmu_idx =3D ARMMMUIdx_E10_0; + } + + if (arm_is_secure_below_el3(env)) { + mmu_idx &=3D ~ARM_MMU_IDX_A_NS; + } + + return tlbbits_for_regime(env, mmu_idx, addr); +} + +static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo= *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); + + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); +} + +static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); + + if (tlb_force_broadcast(env)) { + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); + } else { + tlb_flush_by_mmuidx(cs, mask); + } +} + +static int alle1_tlbmask(CPUARMState *env) +{ + /* + * Note that the 'ALL' scope must invalidate both stage 1 and + * stage 2 translations, whereas most other scopes only invalidate + * stage 1 translations. + */ + if (arm_is_secure_below_el3(env)) { + return ARMMMUIdxBit_SE10_1 | + ARMMMUIdxBit_SE10_1_PAN | + ARMMMUIdxBit_SE10_0; + } else { + return ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0; + } +} + +static int e2_tlbmask(CPUARMState *env) +{ + if (arm_is_secure_below_el3(env)) { + return ARMMMUIdxBit_SE20_0 | + ARMMMUIdxBit_SE20_2 | + ARMMMUIdxBit_SE20_2_PAN | + ARMMMUIdxBit_SE2; + } else { + return ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E2; + } +} + +static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + int mask =3D alle1_tlbmask(env); + + tlb_flush_by_mmuidx(cs, mask); +} + +static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + int mask =3D e2_tlbmask(env); + + tlb_flush_by_mmuidx(cs, mask); +} + +static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D CPU(cpu); + + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3); +} + +static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + int mask =3D alle1_tlbmask(env); + + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); +} + +static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + int mask =3D e2_tlbmask(env); + + tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); +} + +static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3); +} + +static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA, EL2 + * Currently handles both VAE2 and VALE2, since we don't support + * flush-last-level-only. + */ + CPUState *cs =3D env_cpu(env); + int mask =3D e2_tlbmask(env); + uint64_t pageaddr =3D sextract64(value << 12, 0, 56); + + tlb_flush_page_by_mmuidx(cs, pageaddr, mask); +} + +static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA, EL3 + * Currently handles both VAE3 and VALE3, since we don't support + * flush-last-level-only. + */ + ARMCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D CPU(cpu); + uint64_t pageaddr =3D sextract64(value << 12, 0, 56); + + tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3); +} + +static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r= i, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); + uint64_t pageaddr =3D sextract64(value << 12, 0, 56); + int bits =3D vae1_tlbbits(env, pageaddr); + + tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits= ); +} + +static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Invalidate by VA, EL1&0 (AArch64 version). + * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, + * since we don't support flush-for-specific-ASID-only or + * flush-last-level-only. + */ + CPUState *cs =3D env_cpu(env); + int mask =3D vae1_tlbmask(env); + uint64_t pageaddr =3D sextract64(value << 12, 0, 56); + int bits =3D vae1_tlbbits(env, pageaddr); + + if (tlb_force_broadcast(env)) { + tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, = bits); + } else { + tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits); + } +} + +static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r= i, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + uint64_t pageaddr =3D sextract64(value << 12, 0, 56); + bool secure =3D arm_is_secure_below_el3(env); + int mask =3D secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; + int bits =3D tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUId= x_E2, + pageaddr); + + tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits= ); +} + +static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r= i, + uint64_t value) +{ + CPUState *cs =3D env_cpu(env); + uint64_t pageaddr =3D sextract64(value << 12, 0, 56); + int bits =3D tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr); + + tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, + ARMMMUIdxBit_SE3, bits); +} + +static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + int cur_el =3D arm_current_el(env); + + if (cur_el < 2) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + + if (cur_el =3D=3D 0) { + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) { + return CP_ACCESS_TRAP_EL2; + } + } else { + if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) { + return CP_ACCESS_TRAP; + } + if (hcr & HCR_TDZ) { + return CP_ACCESS_TRAP_EL2; + } + } + } else if (hcr & HCR_TDZ) { + return CP_ACCESS_TRAP_EL2; + } + } + return CP_ACCESS_OK; +} + +static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D env_archcpu(env); + int dzp_bit =3D 1 << 4; + + /* DZP indicates whether DC ZVA access is allowed */ + if (aa64_zva_access(env, NULL, false) =3D=3D CP_ACCESS_OK) { + dzp_bit =3D 0; + } + return cpu->dcz_blocksize | dzp_bit; +} + +static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *= ri, + bool isread) +{ + if (!(env->pstate & PSTATE_SP)) { + /* + * Access to SP_EL0 is undefined if it's being used as + * the stack pointer. + */ + return CP_ACCESS_TRAP_UNCATEGORIZED; + } + return CP_ACCESS_OK; +} + +static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_SP; +} + +static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t= val) +{ + update_spsel(env, val); +} + +static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { + /* M bit is RAZ/WI for PMSA with no MPU implemented */ + value &=3D ~SCTLR_M; + } + + /* ??? Lots of these bits are not implemented. */ + + if (ri->state =3D=3D ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, = cpu)) { + if (ri->opc1 =3D=3D 6) { /* SCTLR_EL3 */ + value &=3D ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); + } else { + value &=3D ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | + SCTLR_ATA0 | SCTLR_ATA); + } + } + + if (raw_read(env, ri) =3D=3D value) { + /* + * Skip the TLB flush if nothing actually changed; Linux likes + * to do a lot of pointless SCTLR writes. + */ + return; + } + + raw_write(env, ri, value); + + /* This may enable/disable the MMU, so do a TLB flush. */ + tlb_flush(CPU(cpu)); + + if (ri->type & ARM_CP_SUPPRESS_TB_END) { + /* + * Normally we would always end the TB on an SCTLR write; see the + * comment in ARMCPRegInfo sctlr initialization below for why Xsca= le + * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebu= ild + * of hflags from the translator, so do it here. + */ + arm_rebuild_hflags(env); + } +} + +static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) =3D=3D 2)= { + return CP_ACCESS_TRAP_FP_EL2; + } + if (env->cp15.cptr_el[3] & CPTR_TFP) { + return CP_ACCESS_TRAP_FP_EL3; + } + return CP_ACCESS_OK; +} + +static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.mdcr_el3 =3D value & SDCR_VALID_MASK; +} + +static const ARMCPRegInfo v8_cp_reginfo[] =3D { + /* + * Minimal set of EL0-visible registers. This will need to be expanded + * significantly for system emulation of AArch64 CPUs. + */ + { .name =3D "NZCV", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 0, .crn =3D 4, .crm =3D 2, + .access =3D PL0_RW, .type =3D ARM_CP_NZCV }, + { .name =3D "DAIF", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 4, .crm =3D 2, + .type =3D ARM_CP_NO_RAW, + .access =3D PL0_RW, .accessfn =3D aa64_daif_access, + .fieldoffset =3D offsetof(CPUARMState, daif), + .writefn =3D aa64_daif_write, .resetfn =3D arm_cp_reset_ignore }, + { .name =3D "FPCR", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 0, .crn =3D 4, .crm =3D 4, + .access =3D PL0_RW, .type =3D ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, + .readfn =3D aa64_fpcr_read, .writefn =3D aa64_fpcr_write }, + { .name =3D "FPSR", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 4, .crm =3D 4, + .access =3D PL0_RW, .type =3D ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, + .readfn =3D aa64_fpsr_read, .writefn =3D aa64_fpsr_write }, + { .name =3D "DCZID_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 7, .crn =3D 0, .crm =3D 0, + .access =3D PL0_R, .type =3D ARM_CP_NO_RAW, + .readfn =3D aa64_dczid_read }, + { .name =3D "DC_ZVA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 1, + .access =3D PL0_W, .type =3D ARM_CP_DC_ZVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode= */ + .accessfn =3D aa64_zva_access, +#endif + }, + { .name =3D "CURRENTEL", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 2, .crn =3D 4, .crm =3D 2, + .access =3D PL1_R, .type =3D ARM_CP_CURRENTEL }, + /* Cache ops: all NOPs since we don't emulate caches */ + { .name =3D "IC_IALLUIS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NOP, + .accessfn =3D aa64_cacheop_pou_access }, + { .name =3D "IC_IALLU", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 5, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NOP, + .accessfn =3D aa64_cacheop_pou_access }, + { .name =3D "IC_IVAU", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 5, .opc2 =3D 1, + .access =3D PL0_W, .type =3D ARM_CP_NOP, + .accessfn =3D aa64_cacheop_pou_access }, + { .name =3D "DC_IVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 1, + .access =3D PL1_W, .accessfn =3D aa64_cacheop_poc_access, + .type =3D ARM_CP_NOP }, + { .name =3D "DC_ISW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 2, + .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, + { .name =3D "DC_CVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 1, + .access =3D PL0_W, .type =3D ARM_CP_NOP, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 2, + .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, + { .name =3D "DC_CVAU", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 11, .opc2 =3D 1, + .access =3D PL0_W, .type =3D ARM_CP_NOP, + .accessfn =3D aa64_cacheop_pou_access }, + { .name =3D "DC_CIVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, + .access =3D PL0_W, .type =3D ARM_CP_NOP, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CISW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 2, + .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, + /* TLBI operations */ + { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_vmalle1is_write }, + { .name =3D "TLBI_VAE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_vae1is_write }, + { .name =3D "TLBI_ASIDE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 2, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_vmalle1is_write }, + { .name =3D "TLBI_VAAE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 3, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_vae1is_write }, + { .name =3D "TLBI_VALE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_vae1is_write }, + { .name =3D "TLBI_VAALE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 7, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_vae1is_write }, + { .name =3D "TLBI_VMALLE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_vmalle1_write }, + { .name =3D "TLBI_VAE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_vae1_write }, + { .name =3D "TLBI_ASIDE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 2, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_vmalle1_write }, + { .name =3D "TLBI_VAAE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 3, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_vae1_write }, + { .name =3D "TLBI_VALE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_vae1_write }, + { .name =3D "TLBI_VAALE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 7, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, + .writefn =3D tlbi_aa64_vae1_write }, + { .name =3D "TLBI_IPAS2E1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_IPAS2LE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_ALLE1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, + { .name =3D "TLBI_VMALLS12E1IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, + { .name =3D "TLBI_IPAS2E1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 1, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_IPAS2LE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NOP }, + { .name =3D "TLBI_ALLE1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1_write }, + { .name =3D "TLBI_VMALLS12E1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle1is_write }, +#ifndef CONFIG_USER_ONLY + /* 64 bit address translation operations */ + { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write64 }, + { .name =3D "AT_S1E1W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write64 }, + { .name =3D "AT_S1E0R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write64 }, + { .name =3D "AT_S1E0W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 3, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write64 }, + { .name =3D "AT_S12E1R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 4, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write64 }, + { .name =3D "AT_S12E1W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write64 }, + { .name =3D "AT_S12E0R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 6, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write64 }, + { .name =3D "AT_S12E0W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 7, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write64 }, + /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present= */ + { .name =3D "AT_S1E3R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write64 }, + { .name =3D "AT_S1E3W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write64 }, + { .name =3D "PAR_EL1", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 7, .crm =3D 4, .opc2 =3D 0, + .access =3D PL1_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.par_el[1]), + .writefn =3D par_write }, +#endif + /* TLB invalidate last level of translation table walk */ + { .name =3D "TLBIMVALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 5, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_is_write }, + { .name =3D "TLBIMVAALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 7, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimvaa_is_write }, + { .name =3D "TLBIMVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 5, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_write }, + { .name =3D "TLBIMVAAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 7, .opc2 =3D 7, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimvaa_write }, + { .name =3D "TLBIMVALH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D= 7, .opc2 =3D 5, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbimva_hyp_write }, + { .name =3D "TLBIMVALHIS", + .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbimva_hyp_is_write }, + { .name =3D "TLBIIPAS2", + .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 1, + .type =3D ARM_CP_NOP, .access =3D PL2_W }, + { .name =3D "TLBIIPAS2IS", + .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1, + .type =3D ARM_CP_NOP, .access =3D PL2_W }, + { .name =3D "TLBIIPAS2L", + .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL2_W }, + { .name =3D "TLBIIPAS2LIS", + .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL2_W }, + /* 32 bit cache operations */ + { .name =3D "ICIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 0, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, + { .name =3D "BPIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 6, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "ICIALLU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5= , .opc2 =3D 0, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, + { .name =3D "ICIMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5= , .opc2 =3D 1, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, + { .name =3D "BPIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 6, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "BPIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 7, + .type =3D ARM_CP_NOP, .access =3D PL1_W }, + { .name =3D "DCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6= , .opc2 =3D 1, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, + { .name =3D "DCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, = .opc2 =3D 2, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DCCMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 0, .opc2 =3D 1, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, + { .name =3D "DCCSW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 10,= .opc2 =3D 2, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DCCMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 1, .opc2 =3D 1, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, + { .name =3D "DCCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D = 14, .opc2 =3D 1, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, + { .name =3D "DCCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 14= , .opc2 =3D 2, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + /* MMU Domain access control / MPU write buffer control */ + { .name =3D "DACR", .cp =3D 15, .opc1 =3D 0, .crn =3D 3, .crm =3D 0, .= opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, + .writefn =3D dacr_write, .raw_writefn =3D raw_write, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dacr_s), + offsetoflow32(CPUARMState, cp15.dacr_ns) } }, + { .name =3D "ELR_EL1", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, elr_el[1]) }, + { .name =3D "SPSR_EL1", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, + /* + * We rely on the access checks not allowing the guest to write to the + * state field when SPSel indicates that it's being used as the stack + * pointer. + */ + { .name =3D "SP_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D sp_el0_access, + .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, sp_el[0]) }, + { .name =3D "SP_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, sp_el[1]) }, + { .name =3D "SPSel", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 2, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW, + .access =3D PL1_RW, .readfn =3D spsel_read, .writefn =3D spsel_write= }, + { .name =3D "FPEXC32_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, + .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), + .access =3D PL2_RW, .accessfn =3D fpexc32_access }, + { .name =3D "DACR32_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .resetvalue =3D 0, + .writefn =3D dacr_write, .raw_writefn =3D raw_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.dacr32_el2) }, + { .name =3D "IFSR32_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.ifsr32_el2) }, + { .name =3D "SPSR_IRQ", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 0, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, + { .name =3D "SPSR_ABT", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 1, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, + { .name =3D "SPSR_UND", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 2, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_UND]) }, + { .name =3D "SPSR_FIQ", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 3, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, + { .name =3D "MDCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 3, .opc2 =3D 1, + .resetvalue =3D 0, + .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr= _el3) }, + { .name =3D "SDCR", .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, + .writefn =3D sdcr_write, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.mdcr_el3) }, + REGINFO_SENTINEL +}; + +/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ +static const ARMCPRegInfo el3_no_el2_cp_reginfo[] =3D { + { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, + .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }, + { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_RW, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "HACR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 7, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "ESR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPTR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "MAIR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "AMAIR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "HAMAIR1", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "AFSR0_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "AFSR1_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "VTTBR", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 6, .crm =3D 2, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetvalue =3D 0 }, + { .name =3D "VTTBR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "SCTLR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "TPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, + .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "CNTHCTL_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CNTVOFF_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 0, .opc2 =3D 3, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CNTVOFF", .cp =3D 15, .opc1 =3D 4, .crm =3D 14, + .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "CNTHP_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CNTHP_CVAL", .cp =3D 15, .opc1 =3D 6, .crm =3D 14, + .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "CNTHP_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CNTHP_CTL_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .accessfn =3D access_tda, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "HPFAR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "HSTR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 3, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "FAR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "HIFAR", .state =3D ARM_CP_STATE_AA32, + .type =3D ARM_CP_CONST, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_RW, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +/* Ditto, but for registers which exist in ARMv8 but not v7 */ +static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] =3D { + { .name =3D "HCR2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, + .access =3D PL2_RW, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_= mask) +{ + ARMCPU *cpu =3D env_archcpu(env); + + if (arm_feature(env, ARM_FEATURE_V8)) { + valid_mask |=3D MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */ + } else { + valid_mask |=3D MAKE_64BIT_MASK(0, 28); /* ARMv7VE */ + } + + if (arm_feature(env, ARM_FEATURE_EL3)) { + valid_mask &=3D ~HCR_HCD; + } else if (cpu->psci_conduit !=3D QEMU_PSCI_CONDUIT_SMC) { + /* + * Architecturally HCR.TSC is RES0 if EL3 is not implemented. + * However, if we're using the SMC PSCI conduit then QEMU is + * effectively acting like EL3 firmware and so the guest at + * EL2 should retain the ability to prevent EL1 from being + * able to make SMC calls into the ersatz firmware, so in + * that case HCR.TSC should be read/write. + */ + valid_mask &=3D ~HCR_TSC; + } + + if (arm_feature(env, ARM_FEATURE_AARCH64)) { + if (cpu_isar_feature(aa64_vh, cpu)) { + valid_mask |=3D HCR_E2H; + } + if (cpu_isar_feature(aa64_lor, cpu)) { + valid_mask |=3D HCR_TLOR; + } + if (cpu_isar_feature(aa64_pauth, cpu)) { + valid_mask |=3D HCR_API | HCR_APK; + } + if (cpu_isar_feature(aa64_mte, cpu)) { + valid_mask |=3D HCR_ATA | HCR_DCT | HCR_TID5; + } + } + + /* Clear RES0 bits. */ + value &=3D valid_mask; + + /* + * These bits change the MMU setup: + * HCR_VM enables stage 2 translation + * HCR_PTW forbids certain page-table setups + * HCR_DC disables stage1 and enables stage2 translation + * HCR_DCT enables tagging on (disabled) stage1 translation + */ + if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT= )) { + tlb_flush(CPU(cpu)); + } + env->cp15.hcr_el2 =3D value; + + /* + * Updates to VI and VF require us to update the status of + * virtual interrupts, which are the logical OR of these bits + * and the state of the input lines from the GIC. (This requires + * that we have the iothread lock, which is done by marking the + * reginfo structs as ARM_CP_IO.) + * Note that if a write to HCR pends a VIRQ or VFIQ it is never + * possible for it to be taken immediately, because VIRQ and + * VFIQ are masked unless running at EL0 or EL1, and HCR + * can only be written at EL2. + */ + g_assert(qemu_mutex_iothread_locked()); + arm_cpu_update_virq(cpu); + arm_cpu_update_vfiq(cpu); +} + +static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +{ + do_hcr_write(env, value, 0); +} + +static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */ + value =3D deposit64(env->cp15.hcr_el2, 32, 32, value); + do_hcr_write(env, value, MAKE_64BIT_MASK(0, 32)); +} + +static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Handle HCR write, i.e. write to low half of HCR_EL2 */ + value =3D deposit64(env->cp15.hcr_el2, 0, 32, value); + do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32)); +} + +static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * For A-profile AArch32 EL3, if NSACR.CP10 + * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. + */ + if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && + !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { + value &=3D ~(0x3 << 10); + value |=3D env->cp15.cptr_el[2] & (0x3 << 10); + } + env->cp15.cptr_el[2] =3D value; +} + +static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* + * For A-profile AArch32 EL3, if NSACR.CP10 + * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. + */ + uint64_t value =3D env->cp15.cptr_el[2]; + + if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && + !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { + value |=3D 0x3 << 10; + } + return value; +} + +static const ARMCPRegInfo el2_cp_reginfo[] =3D { + { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_IO, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), + .writefn =3D hcr_write }, + { .name =3D "HCR", .state =3D ARM_CP_STATE_AA32, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), + .writefn =3D hcr_writelow }, + { .name =3D "HACR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 7, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "ELR_EL2", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, elr_el[2]) }, + { .name =3D "ESR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.esr_= el[2]) }, + { .name =3D "FAR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.far_= el[2]) }, + { .name =3D "HIFAR", .state =3D ARM_CP_STATE_AA32, + .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_RW, + .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.far_el[2]) }, + { .name =3D "SPSR_EL2", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, + { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .writefn =3D vbar_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vbar_el[2]), + .resetvalue =3D 0 }, + { .name =3D "SP_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 1, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, sp_el[2]) }, + { .name =3D "CPTR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, + .access =3D PL2_RW, .accessfn =3D cptr_access, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.cptr_el[2]), + .readfn =3D cptr_el2_read, .writefn =3D cptr_el2_write }, + { .name =3D "MAIR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[2]), + .resetvalue =3D 0 }, + { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, + { .name =3D "AMAIR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ + { .name =3D "HAMAIR1", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "AFSR0_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "AFSR1_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_RW, .writefn =3D vmsa_tcr_el12_write, + /* no .raw_writefn or .resetfn needed as we never use mask/base_mask= */ + .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[2]) }, + { .name =3D "VTCR", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, + .type =3D ARM_CP_ALIAS, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .fieldoffset =3D offsetof(CPUARMState, cp15.vtcr_el2) }, + { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, + .access =3D PL2_RW, + /* + * no .writefn needed as this can't cause an ASID change; + * no .raw_writefn or .resetfn needed as we never use mask/base_mask + */ + .fieldoffset =3D offsetof(CPUARMState, cp15.vtcr_el2) }, + { .name =3D "VTTBR", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 6, .crm =3D 2, + .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .fieldoffset =3D offsetof(CPUARMState, cp15.vttbr_el2), + .writefn =3D vttbr_write }, + { .name =3D "VTTBR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_RW, .writefn =3D vttbr_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vttbr_el2) }, + { .name =3D "SCTLR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .raw_writefn =3D raw_write, .writefn =3D sctlr_w= rite, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr_el[2]) }, + { .name =3D "TPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[2]) }, + { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .resetvalue =3D 0, .writefn =3D vmsa_tcr_ttbr_el= 2_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) }, + { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, + .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) }, + { .name =3D "TLBIALLNSNH", + .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 4, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbiall_nsnh_write }, + { .name =3D "TLBIALLNSNHIS", + .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 4, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbiall_nsnh_is_write }, + { .name =3D "TLBIALLH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D = 7, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbiall_hyp_write }, + { .name =3D "TLBIALLHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm = =3D 3, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbiall_hyp_is_write }, + { .name =3D "TLBIMVAH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D = 7, .opc2 =3D 1, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbimva_hyp_write }, + { .name =3D "TLBIMVAHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm = =3D 3, .opc2 =3D 1, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbimva_hyp_is_write }, + { .name =3D "TLBI_ALLE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbi_aa64_alle2_write }, + { .name =3D "TLBI_VAE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbi_aa64_vae2_write }, + { .name =3D "TLBI_VALE2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae2_write }, + { .name =3D "TLBI_ALLE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle2is_write }, + { .name =3D "TLBI_VAE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, + .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .writefn =3D tlbi_aa64_vae2is_write }, + { .name =3D "TLBI_VALE2IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae2is_write }, +#ifndef CONFIG_USER_ONLY + /* + * Unlike the other EL2-related AT operations, these must + * UNDEF from EL3 if EL2 is not implemented, which is why we + * define them here rather than with the rest of the AT ops. + */ + { .name =3D "AT_S1E2R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, + .access =3D PL2_W, .accessfn =3D at_s1e2_access, + .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write6= 4 }, + { .name =3D "AT_S1E2W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, + .access =3D PL2_W, .accessfn =3D at_s1e2_access, + .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write6= 4 }, + /* + * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE + * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 + * with SCR.NS =3D=3D 0 outside Monitor mode is UNPREDICTABLE; we choo= se + * to behave as if SCR.NS was 1. + */ + { .name =3D "ATS1HR", .cp =3D 15, .opc1 =3D 4, .crn =3D 7, .crm =3D 8,= .opc2 =3D 0, + .access =3D PL2_W, + .writefn =3D ats1h_write, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EX= C }, + { .name =3D "ATS1HW", .cp =3D 15, .opc1 =3D 4, .crn =3D 7, .crm =3D 8,= .opc2 =3D 1, + .access =3D PL2_W, + .writefn =3D ats1h_write, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EX= C }, + { .name =3D "CNTHCTL_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, + /* + * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the + * reset values as IMPDEF. We choose to reset to 3 to comply with + * both ARMv7 and ARMv8. + */ + .access =3D PL2_RW, .resetvalue =3D 3, + .fieldoffset =3D offsetof(CPUARMState, cp15.cnthctl_el2) }, + { .name =3D "CNTVOFF_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 0, .opc2 =3D 3, + .access =3D PL2_RW, .type =3D ARM_CP_IO, .resetvalue =3D 0, + .writefn =3D gt_cntvoff_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.cntvoff_el2) }, + { .name =3D "CNTVOFF", .cp =3D 15, .opc1 =3D 4, .crm =3D 14, + .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_I= O, + .writefn =3D gt_cntvoff_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.cntvoff_el2) }, + { .name =3D "CNTHP_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cv= al), + .type =3D ARM_CP_IO, .access =3D PL2_RW, + .writefn =3D gt_hyp_cval_write, .raw_writefn =3D raw_write }, + { .name =3D "CNTHP_CVAL", .cp =3D 15, .opc1 =3D 6, .crm =3D 14, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cv= al), + .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_IO, + .writefn =3D gt_hyp_cval_write, .raw_writefn =3D raw_write }, + { .name =3D "CNTHP_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL2_RW, + .resetfn =3D gt_hyp_timer_reset, + .readfn =3D gt_hyp_tval_read, .writefn =3D gt_hyp_tval_write }, + { .name =3D "CNTHP_CTL_EL2", .state =3D ARM_CP_STATE_BOTH, + .type =3D ARM_CP_IO, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ct= l), + .resetvalue =3D 0, + .writefn =3D gt_hyp_ctl_write, .raw_writefn =3D raw_write }, +#endif + /* The only field of MDCR_EL2 that has a defined architectural reset v= alue + * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N. + */ + { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .resetvalue =3D PMCR_NUM_COUNTERS, + .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr_el2), }, + { .name =3D "HPFAR", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .fieldoffset =3D offsetof(CPUARMState, cp15.hpfar_el2) }, + { .name =3D "HPFAR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.hpfar_el2) }, + { .name =3D "HSTR_EL2", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 15, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 = =3D 3, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.hstr_el2) }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo el2_v8_cp_reginfo[] =3D { + { .name =3D "HCR2", .state =3D ARM_CP_STATE_AA32, + .type =3D ARM_CP_ALIAS | ARM_CP_IO, + .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, + .access =3D PL2_RW, + .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.hcr_el2), + .writefn =3D hcr_writehigh }, + REGINFO_SENTINEL +}; + +static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 3 || arm_is_secure_below_el3(env)) { + return CP_ACCESS_OK; + } + return CP_ACCESS_TRAP_UNCATEGORIZED; +} + +static const ARMCPRegInfo el2_sec_cp_reginfo[] =3D { + { .name =3D "VSTTBR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 6, .opc2 =3D 0, + .access =3D PL2_RW, .accessfn =3D sel2_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.vsttbr_el2) }, + { .name =3D "VSTCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 6, .opc2 =3D 2, + .access =3D PL2_RW, .accessfn =3D sel2_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.vstcr_el2) }, + REGINFO_SENTINEL +}; + +static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + /* + * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. + * At Secure EL1 it traps to EL3 or EL2. + */ + if (arm_current_el(env) =3D=3D 3) { + return CP_ACCESS_OK; + } + if (arm_is_secure_below_el3(env)) { + if (env->cp15.scr_el3 & SCR_EEL2) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_TRAP_EL3; + } + /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads= . */ + if (isread) { + return CP_ACCESS_OK; + } + return CP_ACCESS_TRAP_UNCATEGORIZED; +} + +static const ARMCPRegInfo el3_cp_reginfo[] =3D { + { .name =3D "SCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, + .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.scr_= el3), + .resetfn =3D scr_reset, .writefn =3D scr_write }, + { .name =3D "SCR", .type =3D ARM_CP_ALIAS | ARM_CP_NEWEL, + .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.scr_el3), + .writefn =3D scr_write }, + { .name =3D "SDER32_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, + .access =3D PL3_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.sder) }, + { .name =3D "SDER", + .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, + .access =3D PL3_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.sder) }, + { .name =3D "MVBAR", .cp =3D 15, .opc1 =3D 0, .crn =3D 12, .crm =3D 0,= .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, + .writefn =3D vbar_write, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.mvbar) }, + { .name =3D "TTBR0_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, + .access =3D PL3_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[3]) }, + { .name =3D "TCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, + .access =3D PL3_RW, + /* + * no .writefn needed as this can't cause an ASID change; + * we must provide a .raw_writefn and .resetfn because we handle + * reset and migration for the AArch32 TTBCR(S), which might be + * using mask and base_mask. + */ + .resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D vmsa_ttbcr_raw_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[3]) }, + { .name =3D "ELR_EL3", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, elr_el[3]) }, + { .name =3D "ESR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, + .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.esr_= el[3]) }, + { .name =3D "FAR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 6, .crm =3D 0, .opc2 =3D 0, + .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.far_= el[3]) }, + { .name =3D "SPSR_EL3", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_ALIAS, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_MON]) }, + { .name =3D "VBAR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, + .access =3D PL3_RW, .writefn =3D vbar_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.vbar_el[3]), + .resetvalue =3D 0 }, + { .name =3D "CPTR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, + .access =3D PL3_RW, .accessfn =3D cptr_access, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.cptr_el[3]) }, + { .name =3D "TPIDR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 13, .crm =3D 0, .opc2 =3D 2, + .access =3D PL3_RW, .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[3]) }, + { .name =3D "AMAIR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "AFSR0_EL3", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "AFSR1_EL3", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "TLBI_ALLE3IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle3is_write }, + { .name =3D "TLBI_VAE3IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae3is_write }, + { .name =3D "TLBI_VALE3IS", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae3is_write }, + { .name =3D "TLBI_ALLE3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_alle3_write }, + { .name =3D "TLBI_VAE3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae3_write }, + { .name =3D "TLBI_VALE3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, + .writefn =3D tlbi_aa64_vae3_write }, + REGINFO_SENTINEL +}; + +#ifndef CONFIG_USER_ONLY +/* Test if system register redirection is to occur in the current state. = */ +static bool redirect_for_e2h(CPUARMState *env) +{ + return arm_current_el(env) =3D=3D 2 && (arm_hcr_el2_eff(env) & HCR_E2H= ); +} + +static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + CPReadFn *readfn; + + if (redirect_for_e2h(env)) { + /* Switch to the saved EL2 version of the register. */ + ri =3D ri->opaque; + readfn =3D ri->readfn; + } else { + readfn =3D ri->orig_readfn; + } + if (readfn =3D=3D NULL) { + readfn =3D raw_read; + } + return readfn(env, ri); +} + +static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + CPWriteFn *writefn; + + if (redirect_for_e2h(env)) { + /* Switch to the saved EL2 version of the register. */ + ri =3D ri->opaque; + writefn =3D ri->writefn; + } else { + writefn =3D ri->orig_writefn; + } + if (writefn =3D=3D NULL) { + writefn =3D raw_write; + } + writefn(env, ri, value); +} + +static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) +{ + struct E2HAlias { + uint32_t src_key, dst_key, new_key; + const char *src_name, *dst_name, *new_name; + bool (*feature)(const ARMISARegisters *id); + }; + +#define K(op0, op1, crn, crm, op2) \ + ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) + + static const struct E2HAlias aliases[] =3D { + { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), + "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, + { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), + "CPACR", "CPTR_EL2", "CPACR_EL12" }, + { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), + "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, + { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), + "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, + { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), + "TCR_EL1", "TCR_EL2", "TCR_EL12" }, + { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), + "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, + { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), + "ELR_EL1", "ELR_EL2", "ELR_EL12" }, + { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0), + "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" }, + { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1), + "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" }, + { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0), + "ESR_EL1", "ESR_EL2", "ESR_EL12" }, + { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0), + "FAR_EL1", "FAR_EL2", "FAR_EL12" }, + { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), + "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, + { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), + "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" }, + { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), + "VBAR", "VBAR_EL2", "VBAR_EL12" }, + { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), + "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, + { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), + "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" }, + + /* + * Note that redirection of ZCR is mentioned in the description + * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but + * not in the summary table. + */ + { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), + "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, + + { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), + "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, + + /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ + /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ + }; +#undef K + + size_t i; + + for (i =3D 0; i < ARRAY_SIZE(aliases); i++) { + const struct E2HAlias *a =3D &aliases[i]; + ARMCPRegInfo *src_reg, *dst_reg; + + if (a->feature && !a->feature(&cpu->isar)) { + continue; + } + + src_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->src_key); + dst_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->dst_key); + g_assert(src_reg !=3D NULL); + g_assert(dst_reg !=3D NULL); + + /* Cross-compare names to detect typos in the keys. */ + g_assert(strcmp(src_reg->name, a->src_name) =3D=3D 0); + g_assert(strcmp(dst_reg->name, a->dst_name) =3D=3D 0); + + /* None of the core system registers use opaque; we will. */ + g_assert(src_reg->opaque =3D=3D NULL); + + /* Create alias before redirection so we dup the right data. */ + if (a->new_key) { + ARMCPRegInfo *new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInf= o)); + uint32_t *new_key =3D g_memdup(&a->new_key, sizeof(uint32_t)); + bool ok; + + new_reg->name =3D a->new_name; + new_reg->type |=3D ARM_CP_ALIAS; + /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ + new_reg->access &=3D PL2_RW | PL3_RW; + + ok =3D g_hash_table_insert(cpu->cp_regs, new_key, new_reg); + g_assert(ok); + } + + src_reg->opaque =3D dst_reg; + src_reg->orig_readfn =3D src_reg->readfn ?: raw_read; + src_reg->orig_writefn =3D src_reg->writefn ?: raw_write; + if (!src_reg->raw_readfn) { + src_reg->raw_readfn =3D raw_read; + } + if (!src_reg->raw_writefn) { + src_reg->raw_writefn =3D raw_write; + } + src_reg->readfn =3D el2_e2h_read; + src_reg->writefn =3D el2_e2h_write; + } +} +#endif + +static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + int cur_el =3D arm_current_el(env); + + if (cur_el < 2) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + + if (cur_el =3D=3D 0) { + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) { + return CP_ACCESS_TRAP_EL2; + } + } else { + if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) { + return CP_ACCESS_TRAP; + } + if (hcr & HCR_TID2) { + return CP_ACCESS_TRAP_EL2; + } + } + } else if (hcr & HCR_TID2) { + return CP_ACCESS_TRAP_EL2; + } + } + + if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) { + return CP_ACCESS_TRAP_EL2; + } + + return CP_ACCESS_OK; +} + +static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Writes to OSLAR_EL1 may update the OS lock status, which can be + * read via a bit in OSLSR_EL1. + */ + int oslock; + + if (ri->state =3D=3D ARM_CP_STATE_AA32) { + oslock =3D (value =3D=3D 0xC5ACCE55); + } else { + oslock =3D value & 1; + } + + env->cp15.oslsr_el1 =3D deposit32(env->cp15.oslsr_el1, 1, 1, oslock); +} + +static const ARMCPRegInfo debug_cp_reginfo[] =3D { + /* + * DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped + * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; + * unlike DBGDRAR it is never accessible from EL0. + * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AAr= ch64 + * accessor. + */ + { .name =3D "DBGDRAR", .cp =3D 14, .crn =3D 1, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, + .access =3D PL0_R, .accessfn =3D access_tdra, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "MDRAR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_R, .accessfn =3D access_tdra, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "DBGDSAR", .cp =3D 14, .crn =3D 2, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, + .access =3D PL0_R, .accessfn =3D access_tdra, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + /* Monitor debug system control register; the 32-bit alias is DBGDSCRe= xt. */ + { .name =3D "MDSCR_EL1", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 2, + .access =3D PL1_RW, .accessfn =3D access_tda, + .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), + .resetvalue =3D 0 }, + /* + * MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. + * We don't implement the configurable EL0 access. + */ + { .name =3D "MDCCSR_EL0", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 = =3D 0, + .type =3D ARM_CP_ALIAS, + .access =3D PL1_R, .accessfn =3D access_tda, + .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), }, + { .name =3D "OSLAR_EL1", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 = =3D 4, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .accessfn =3D access_tdosa, + .writefn =3D oslar_write }, + { .name =3D "OSLSR_EL1", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 = =3D 4, + .access =3D PL1_R, .resetvalue =3D 10, + .accessfn =3D access_tdosa, + .fieldoffset =3D offsetof(CPUARMState, cp15.oslsr_el1) }, + /* Dummy OSDLR_EL1: 32-bit Linux will read this */ + { .name =3D "OSDLR_EL1", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 = =3D 4, + .access =3D PL1_RW, .accessfn =3D access_tdosa, + .type =3D ARM_CP_NOP }, + /* + * Dummy DBGVCR: Linux wants to clear this on startup, but we don't + * implement vector catch debug events yet. + */ + { .name =3D "DBGVCR", + .cp =3D 14, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tda, + .type =3D ARM_CP_NOP }, + /* + * Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor + * to save and restore a 32-bit guest's DBGVCR) + */ + { .name =3D "DBGVCR32_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 2, .opc1 =3D 4, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, + .access =3D PL2_RW, .accessfn =3D access_tda, + .type =3D ARM_CP_NOP }, + /* + * Dummy MDCCINT_EL1, since we don't implement the Debug Communications + * Channel but Linux may try to access this register. The 32-bit + * alias is DBGDCCINT. + */ + { .name =3D "MDCCINT_EL1", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tda, + .type =3D ARM_CP_NOP }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D { + /* 64 bit access versions of the (dummy) debug registers */ + { .name =3D "DBGDRAR", .cp =3D 14, .crm =3D 1, .opc1 =3D 0, + .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, + { .name =3D "DBGDSAR", .cp =3D 14, .crm =3D 2, .opc1 =3D 0, + .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, + REGINFO_SENTINEL +}; + +static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + int cur_el =3D arm_current_el(env); + int old_len =3D sve_zcr_len_for_el(env, cur_el); + int new_len; + + /* Bits other than [3:0] are RAZ/WI. */ + QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16); + raw_write(env, ri, value & 0xf); + + /* + * Because we arrived here, we know both FP and SVE are enabled; + * otherwise we would have trapped access to the ZCR_ELn register. + */ + new_len =3D sve_zcr_len_for_el(env, cur_el); + if (new_len < old_len) { + aarch64_sve_narrow_vq(env, new_len + 1); + } +} + +static const ARMCPRegInfo zcr_el1_reginfo =3D { + .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_SVE, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write +}; + +static const ARMCPRegInfo zcr_el2_reginfo =3D { + .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_SVE, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write +}; + +static const ARMCPRegInfo zcr_no_el2_reginfo =3D { + .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_SVE, + .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore +}; + +static const ARMCPRegInfo zcr_el3_reginfo =3D { + .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_SVE, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write +}; + +static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + int i =3D ri->crm; + + /* + * Bits [63:49] are hardwired to the value of bit [48]; that is, the + * register reads and behaves as if values written are sign extended. + * Bits [1:0] are RES0. + */ + value =3D sextract64(value, 0, 49) & ~3ULL; + + raw_write(env, ri, value); + hw_watchpoint_update(cpu, i); +} + +static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + int i =3D ri->crm; + + raw_write(env, ri, value); + hw_watchpoint_update(cpu, i); +} + +static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + int i =3D ri->crm; + + raw_write(env, ri, value); + hw_breakpoint_update(cpu, i); +} + +static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + int i =3D ri->crm; + + /* + * BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only + * copy of BAS[0]. + */ + value =3D deposit64(value, 6, 1, extract64(value, 5, 1)); + value =3D deposit64(value, 8, 1, extract64(value, 7, 1)); + + raw_write(env, ri, value); + hw_breakpoint_update(cpu, i); +} + +static void define_debug_regs(ARMCPU *cpu) +{ + /* + * Define v7 and v8 architectural debug registers. + * These are just dummy implementations for now. + */ + int i; + int wrps, brps, ctx_cmps; + + /* + * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot + * use AArch32. Given that bit 15 is RES1, if the value is 0 then + * the register must not exist for this cpu. + */ + if (cpu->isar.dbgdidr !=3D 0) { + ARMCPRegInfo dbgdidr =3D { + .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, + .opc1 =3D 0, .opc2 =3D 0, + .access =3D PL0_R, .accessfn =3D access_tda, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->isar.dbgdidr, + }; + define_one_arm_cp_reg(cpu, &dbgdidr); + } + + /* Note that all these register fields hold "number of Xs minus 1". */ + brps =3D arm_num_brps(cpu); + wrps =3D arm_num_wrps(cpu); + ctx_cmps =3D arm_num_ctx_cmps(cpu); + + assert(ctx_cmps <=3D brps); + + define_arm_cp_regs(cpu, debug_cp_reginfo); + + if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { + define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); + } + + for (i =3D 0; i < brps; i++) { + ARMCPRegInfo dbgregs[] =3D { + { .name =3D "DBGBVR", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 4, + .access =3D PL1_RW, .accessfn =3D access_tda, + .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbvr[i]), + .writefn =3D dbgbvr_write, .raw_writefn =3D raw_write + }, + { .name =3D "DBGBCR", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 5, + .access =3D PL1_RW, .accessfn =3D access_tda, + .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbcr[i]), + .writefn =3D dbgbcr_write, .raw_writefn =3D raw_write + }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, dbgregs); + } + + for (i =3D 0; i < wrps; i++) { + ARMCPRegInfo dbgregs[] =3D { + { .name =3D "DBGWVR", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 6, + .access =3D PL1_RW, .accessfn =3D access_tda, + .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwvr[i]), + .writefn =3D dbgwvr_write, .raw_writefn =3D raw_write + }, + { .name =3D "DBGWCR", .state =3D ARM_CP_STATE_BOTH, + .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 7, + .access =3D PL1_RW, .accessfn =3D access_tda, + .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwcr[i]), + .writefn =3D dbgwcr_write, .raw_writefn =3D raw_write + }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, dbgregs); + } +} + +static void define_pmu_regs(ARMCPU *cpu) +{ + /* + * v7 performance monitor control register: same implementor + * field as main ID register, and we implement four counters in + * addition to the cycle count register. + */ + unsigned int i, pmcrn =3D PMCR_NUM_COUNTERS; + ARMCPRegInfo pmcr =3D { + .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 0, + .access =3D PL0_RW, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcr), + .accessfn =3D pmreg_access, .writefn =3D pmcr_write, + .raw_writefn =3D raw_write, + }; + ARMCPRegInfo pmcr64 =3D { + .name =3D "PMCR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 0, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), + .resetvalue =3D (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) | + PMCRLC, + .writefn =3D pmcr_write, .raw_writefn =3D raw_write, + }; + define_one_arm_cp_reg(cpu, &pmcr); + define_one_arm_cp_reg(cpu, &pmcr64); + for (i =3D 0; i < pmcrn; i++) { + char *pmevcntr_name =3D g_strdup_printf("PMEVCNTR%d", i); + char *pmevcntr_el0_name =3D g_strdup_printf("PMEVCNTR%d_EL0", i); + char *pmevtyper_name =3D g_strdup_printf("PMEVTYPER%d", i); + char *pmevtyper_el0_name =3D g_strdup_printf("PMEVTYPER%d_EL0", i); + ARMCPRegInfo pmev_regs[] =3D { + { .name =3D pmevcntr_name, .cp =3D 15, .crn =3D 14, + .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, + .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, + .accessfn =3D pmreg_access }, + { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 8 | (3 & (i = >> 3)), + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess, + .type =3D ARM_CP_IO, + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, + .raw_readfn =3D pmevcntr_rawread, + .raw_writefn =3D pmevcntr_rawwrite }, + { .name =3D pmevtyper_name, .cp =3D 15, .crn =3D 14, + .crm =3D 12 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, + .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, + .accessfn =3D pmreg_access }, + { .name =3D pmevtyper_el0_name, .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 12 | (3 & (i= >> 3)), + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess, + .type =3D ARM_CP_IO, + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, + .raw_writefn =3D pmevtyper_rawwrite }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, pmev_regs); + g_free(pmevcntr_name); + g_free(pmevcntr_el0_name); + g_free(pmevtyper_name); + g_free(pmevtyper_el0_name); + } + if (cpu_isar_feature(aa32_pmu_8_1, cpu)) { + ARMCPRegInfo v81_pmu_regs[] =3D { + { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 4, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D extract64(cpu->pmceid0, 32, 32) }, + { .name =3D "PMCEID3", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 5, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, v81_pmu_regs); + } + if (cpu_isar_feature(any_pmu_8_4, cpu)) { + static const ARMCPRegInfo v84_pmmir =3D { + .name =3D "PMMIR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 6, + .access =3D PL1_R, .accessfn =3D pmreg_access, .type =3D ARM_C= P_CONST, + .resetvalue =3D 0 + }; + define_one_arm_cp_reg(cpu, &v84_pmmir); + } +} + +/* + * We don't know until after realize whether there's a GICv3 + * attached, and that is what registers the gicv3 sysregs. + * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_= EL1 + * at runtime. + */ +static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D env_archcpu(env); + uint64_t pfr1 =3D cpu->isar.id_pfr1; + + if (env->gicv3state) { + pfr1 |=3D 1 << 28; + } + return pfr1; +} + +#ifndef CONFIG_USER_ONLY +static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D env_archcpu(env); + uint64_t pfr0 =3D cpu->isar.id_aa64pfr0; + + if (env->gicv3state) { + pfr0 |=3D 1 << 24; + } + return pfr0; +} +#endif + +/* + * Shared logic between LORID and the rest of the LOR* registers. + * Secure state exclusion has already been dealt with. + */ +static CPAccessResult access_lor_ns(CPUARMState *env, + const ARMCPRegInfo *ri, bool isread) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult access_lor_other(CPUARMState *env, + const ARMCPRegInfo *ri, bool isread) +{ + if (arm_is_secure_below_el3(env)) { + /* Access denied in secure mode. */ + return CP_ACCESS_TRAP; + } + return access_lor_ns(env, ri, isread); +} + +/* + * A trivial implementation of ARMv8.1-LOR leaves all of these + * registers fixed at 0, which indicates that there are zero + * supported Limited Ordering regions. + */ +static const ARMCPRegInfo lor_reginfo[] =3D { + { .name =3D "LORSA_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LOREA_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORN_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORC_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 3, + .access =3D PL1_RW, .accessfn =3D access_lor_other, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "LORID_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 7, + .access =3D PL1_R, .accessfn =3D access_lor_ns, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +#ifdef TARGET_AARCH64 +static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *r= i, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el < 2 && + arm_feature(env, ARM_FEATURE_EL2) && + !(arm_hcr_el2_eff(env) & HCR_APK)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && + arm_feature(env, ARM_FEATURE_EL3) && + !(env->cp15.scr_el3 & SCR_APK)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo pauth_reginfo[] =3D { + { .name =3D "APDAKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, keys.apda.lo) }, + { .name =3D "APDAKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, keys.apda.hi) }, + { .name =3D "APDBKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, keys.apdb.lo) }, + { .name =3D "APDBKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 3, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, keys.apdb.hi) }, + { .name =3D "APGAKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, keys.apga.lo) }, + { .name =3D "APGAKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 3, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, keys.apga.hi) }, + { .name =3D "APIAKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, keys.apia.lo) }, + { .name =3D "APIAKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, keys.apia.hi) }, + { .name =3D "APIBKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, keys.apib.lo) }, + { .name =3D "APIBKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 3, + .access =3D PL1_RW, .accessfn =3D access_pauth, + .fieldoffset =3D offsetof(CPUARMState, keys.apib.hi) }, + REGINFO_SENTINEL +}; + +static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) +{ + Error *err =3D NULL; + uint64_t ret; + + /* Success sets NZCV =3D 0000. */ + env->NF =3D env->CF =3D env->VF =3D 0, env->ZF =3D 1; + + if (qemu_guest_getrandom(&ret, sizeof(ret), &err) < 0) { + /* + * ??? Failed, for unknown reasons in the crypto subsystem. + * The best we can do is log the reason and return the + * timed-out indication to the guest. There is no reason + * we know to expect this failure to be transitory, so the + * guest may well hang retrying the operation. + */ + qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", + ri->name, error_get_pretty(err)); + error_free(err); + + env->ZF =3D 0; /* NZCF =3D 0100 */ + return 0; + } + return ret; +} + +/* We do not support re-seeding, so the two registers operate the same. */ +static const ARMCPRegInfo rndr_reginfo[] =3D { + { .name =3D "RNDR", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 2, .crm =3D 4, .opc2 =3D 0, + .access =3D PL0_R, .readfn =3D rndr_readfn }, + { .name =3D "RNDRRS", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 2, .crm =3D 4, .opc2 =3D 1, + .access =3D PL0_R, .readfn =3D rndr_readfn }, + REGINFO_SENTINEL +}; + +#ifndef CONFIG_USER_ONLY +static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + /* CTR_EL0 System register -> DminLine, bits [19:16] */ + uint64_t dline_size =3D 4 << ((cpu->ctr >> 16) & 0xF); + uint64_t vaddr_in =3D (uint64_t) value; + uint64_t vaddr =3D vaddr_in & ~(dline_size - 1); + void *haddr; + int mem_idx =3D cpu_mmu_index(env, false); + + /* This won't be crossing page boundaries */ + haddr =3D probe_read(env, vaddr, dline_size, mem_idx, GETPC()); + if (haddr) { + + ram_addr_t offset; + MemoryRegion *mr; + + /* RCU lock is already being held */ + mr =3D memory_region_from_host(haddr, &offset); + + if (mr) { + memory_region_writeback(mr, offset, dline_size); + } + } +} + +static const ARMCPRegInfo dcpop_reg[] =3D { + { .name =3D "DC_CVAP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 1, + .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, + .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo dcpodp_reg[] =3D { + { .name =3D "DC_CVADP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 1, + .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, + .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, + REGINFO_SENTINEL +}; +#endif /*CONFIG_USER_ONLY*/ + +static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID5)) { + return CP_ACCESS_TRAP_EL2; + } + + return CP_ACCESS_OK; +} + +static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { + return CP_ACCESS_TRAP_EL2; + } + } + if (el < 3 && + arm_feature(env, ARM_FEATURE_EL3) && + !(env->cp15.scr_el3 & SCR_ATA)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + return env->pstate & PSTATE_TCO; +} + +static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= al) +{ + env->pstate =3D (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); +} + +static const ARMCPRegInfo mte_reginfo[] =3D { + { .name =3D "TFSRE0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 6, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_mte, + .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[0]) }, + { .name =3D "TFSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 6, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_mte, + .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[1]) }, + { .name =3D "TFSR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 6, .opc2 =3D 0, + .access =3D PL2_RW, .accessfn =3D access_mte, + .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[2]) }, + { .name =3D "TFSR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 6, .opc2 =3D 0, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[3]) }, + { .name =3D "RGSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 5, + .access =3D PL1_RW, .accessfn =3D access_mte, + .fieldoffset =3D offsetof(CPUARMState, cp15.rgsr_el1) }, + { .name =3D "GCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 6, + .access =3D PL1_RW, .accessfn =3D access_mte, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcr_el1) }, + { .name =3D "GMID_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 4, + .access =3D PL1_R, .accessfn =3D access_aa64_tid5, + .type =3D ARM_CP_CONST, .resetvalue =3D GMID_EL1_BS }, + { .name =3D "TCO", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 7, + .type =3D ARM_CP_NO_RAW, + .access =3D PL0_RW, .readfn =3D tco_read, .writefn =3D tco_write }, + { .name =3D "DC_IGVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL1_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_IGSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_IGDVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL1_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_IGDSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 6, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_CGSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_CGDSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 6, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_CIGSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_CIGDSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 6, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo mte_tco_ro_reginfo[] =3D { + { .name =3D "TCO", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 7, + .type =3D ARM_CP_CONST, .access =3D PL0_RW, }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo mte_el0_cacheop_reginfo[] =3D { + { .name =3D "DC_CGVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGDVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGVAP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGDVAP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGVADP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGDVADP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CIGVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CIGDVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_GVA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 3, + .access =3D PL0_W, .type =3D ARM_CP_DC_GVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode= */ + .accessfn =3D aa64_zva_access, +#endif + }, + { .name =3D "DC_GZVA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 4, + .access =3D PL0_W, .type =3D ARM_CP_DC_GZVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode= */ + .accessfn =3D aa64_zva_access, +#endif + }, + REGINFO_SENTINEL +}; + +#endif + +static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el =3D=3D 0) { + uint64_t sctlr =3D arm_sctlr(env, el); + if (!(sctlr & SCTLR_EnRCTX)) { + return CP_ACCESS_TRAP; + } + } else if (el =3D=3D 1) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + if (hcr & HCR_NV) { + return CP_ACCESS_TRAP_EL2; + } + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo predinv_reginfo[] =3D { + { .name =3D "CFP_RCTX", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + { .name =3D "DVP_RCTX", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + { .name =3D "CPP_RCTX", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + /* + * Note the AArch32 opcodes have a different OPC1. + */ + { .name =3D "CFPRCTX", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + { .name =3D "DVPRCTX", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + { .name =3D "CPPRCTX", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, + .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, + REGINFO_SENTINEL +}; + +static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* Read the high 32 bits of the current CCSIDR */ + return extract64(ccsidr_read(env, ri), 32, 32); +} + +static const ARMCPRegInfo ccsidr2_reginfo[] =3D { + { .name =3D "CCSIDR2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 2, + .access =3D PL1_R, + .accessfn =3D access_aa64_tid2, + .readfn =3D ccsidr2_read, .type =3D ARM_CP_NO_RAW }, + REGINFO_SENTINEL +}; + +static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) { + return CP_ACCESS_TRAP_EL2; + } + + return CP_ACCESS_OK; +} + +static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInf= o *ri, + bool isread) +{ + if (arm_feature(env, ARM_FEATURE_V8)) { + return access_aa64_tid3(env, ri, isread); + } + + return CP_ACCESS_OK; +} + +static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TID0))= { + return CP_ACCESS_TRAP_EL2; + } + + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo jazelle_regs[] =3D { + { .name =3D "JIDR", + .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D 7, .opc2 =3D 0, + .access =3D PL1_R, .accessfn =3D access_jazelle, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "JOSCR", + .cp =3D 14, .crn =3D 1, .crm =3D 0, .opc1 =3D 7, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "JMCR", + .cp =3D 14, .crn =3D 2, .crm =3D 0, .opc1 =3D 7, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo vhe_reginfo[] =3D { + { .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]) }, + { .name =3D "TTBR1_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr1_el[2]) }, +#ifndef CONFIG_USER_ONLY + { .name =3D "CNTHV_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, + .fieldoffset =3D + offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval), + .type =3D ARM_CP_IO, .access =3D PL2_RW, + .writefn =3D gt_hv_cval_write, .raw_writefn =3D raw_write }, + { .name =3D "CNTHV_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL2_RW, + .resetfn =3D gt_hv_timer_reset, + .readfn =3D gt_hv_tval_read, .writefn =3D gt_hv_tval_write }, + { .name =3D "CNTHV_CTL_EL2", .state =3D ARM_CP_STATE_BOTH, + .type =3D ARM_CP_IO, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT= ].ctl), + .writefn =3D gt_hv_ctl_write, .raw_writefn =3D raw_write }, + { .name =3D "CNTP_CTL_EL02", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .access =3D PL2_RW, .accessfn =3D e2h_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= tl), + .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write }, + { .name =3D "CNTV_CTL_EL02", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .access =3D PL2_RW, .accessfn =3D e2h_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= tl), + .writefn =3D gt_virt_ctl_write, .raw_writefn =3D raw_write }, + { .name =3D "CNTP_TVAL_EL02", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, + .access =3D PL2_RW, .accessfn =3D e2h_access, + .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write }, + { .name =3D "CNTV_TVAL_EL02", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 0, + .type =3D ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, + .access =3D PL2_RW, .accessfn =3D e2h_access, + .readfn =3D gt_virt_tval_read, .writefn =3D gt_virt_tval_write }, + { .name =3D "CNTP_CVAL_EL02", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), + .access =3D PL2_RW, .accessfn =3D e2h_access, + .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write }, + { .name =3D "CNTV_CVAL_EL02", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), + .access =3D PL2_RW, .accessfn =3D e2h_access, + .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write }, +#endif + REGINFO_SENTINEL +}; + +#ifndef CONFIG_USER_ONLY +static const ARMCPRegInfo ats1e1_reginfo[] =3D { + { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write64 }, + { .name =3D "AT_S1E1W", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write64 }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo ats1cp_reginfo[] =3D { + { .name =3D "ATS1CPRP", + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write }, + { .name =3D "ATS1CPWP", + .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_write }, + REGINFO_SENTINEL +}; +#endif + +/* + * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and + * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field + * is non-zero, which is never for ARMv7, optionally in ARMv8 + * and mandatorily for ARMv8.2 and up. + * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's + * implementation is RAZ/WI we can ignore this detail, as we + * do for ACTLR. + */ +static const ARMCPRegInfo actlr2_hactlr2_reginfo[] =3D { + { .name =3D "ACTLR2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, + .access =3D PL1_RW, .accessfn =3D access_tacr, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "HACTLR2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +void register_cp_regs_for_features(ARMCPU *cpu) +{ + /* Register all the coprocessor registers based on feature bits */ + CPUARMState *env =3D &cpu->env; + if (arm_feature(env, ARM_FEATURE_M)) { + /* M profile has no coprocessor registers */ + return; + } + + define_arm_cp_regs(cpu, cp_reginfo); + if (!arm_feature(env, ARM_FEATURE_V8)) { + /* + * Must go early as it is full of wildcards that may be + * overridden by later definitions. + */ + define_arm_cp_regs(cpu, not_v8_cp_reginfo); + } + + if (arm_feature(env, ARM_FEATURE_V6)) { + /* The ID registers all have impdef reset values */ + ARMCPRegInfo v6_idregs[] =3D { + { .name =3D "ID_PFR0", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 0, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, + .resetvalue =3D cpu->isar.id_pfr0 }, + /* + * ID_PFR1 is not a plain ARM_CP_CONST because we don't know + * the value of the GIC field until after we define these regs. + */ + { .name =3D "ID_PFR1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 1, + .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, + .accessfn =3D access_aa32_tid3, + .readfn =3D id_pfr1_read, + .writefn =3D arm_cp_write_ignore }, + { .name =3D "ID_DFR0", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 2, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, + .resetvalue =3D cpu->isar.id_dfr0 }, + { .name =3D "ID_AFR0", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 3, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, + .resetvalue =3D cpu->id_afr0 }, + { .name =3D "ID_MMFR0", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 4, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, + .resetvalue =3D cpu->isar.id_mmfr0 }, + { .name =3D "ID_MMFR1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 5, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, + .resetvalue =3D cpu->isar.id_mmfr1 }, + { .name =3D "ID_MMFR2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 6, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, + .resetvalue =3D cpu->isar.id_mmfr2 }, + { .name =3D "ID_MMFR3", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 7, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, + .resetvalue =3D cpu->isar.id_mmfr3 }, + { .name =3D "ID_ISAR0", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 0, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, + .resetvalue =3D cpu->isar.id_isar0 }, + { .name =3D "ID_ISAR1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 1, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, + .resetvalue =3D cpu->isar.id_isar1 }, + { .name =3D "ID_ISAR2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 2, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, + .resetvalue =3D cpu->isar.id_isar2 }, + { .name =3D "ID_ISAR3", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 3, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, + .resetvalue =3D cpu->isar.id_isar3 }, + { .name =3D "ID_ISAR4", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 4, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, + .resetvalue =3D cpu->isar.id_isar4 }, + { .name =3D "ID_ISAR5", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 5, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, + .resetvalue =3D cpu->isar.id_isar5 }, + { .name =3D "ID_MMFR4", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 6, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, + .resetvalue =3D cpu->isar.id_mmfr4 }, + { .name =3D "ID_ISAR6", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 7, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa32_tid3, + .resetvalue =3D cpu->isar.id_isar6 }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, v6_idregs); + define_arm_cp_regs(cpu, v6_cp_reginfo); + } else { + define_arm_cp_regs(cpu, not_v6_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_V6K)) { + define_arm_cp_regs(cpu, v6k_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_V7MP) && + !arm_feature(env, ARM_FEATURE_PMSA)) { + define_arm_cp_regs(cpu, v7mp_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_V7VE)) { + define_arm_cp_regs(cpu, pmovsset_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_V7)) { + ARMCPRegInfo clidr =3D { + .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 1, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid2, + .resetvalue =3D cpu->clidr + }; + define_one_arm_cp_reg(cpu, &clidr); + define_arm_cp_regs(cpu, v7_cp_reginfo); + define_debug_regs(cpu); + define_pmu_regs(cpu); + } else { + define_arm_cp_regs(cpu, not_v7_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_V8)) { + /* + * AArch64 ID registers, which all have impdef reset values. + * Note that within the ID register ranges the unused slots + * must all RAZ, not UNDEF; future architecture versions may + * define new registers here. + */ + ARMCPRegInfo v8_idregs[] =3D { + /* + * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system + * emulation because we don't know the right value for the + * GIC field until after we define these regs. + */ + { .name =3D "ID_AA64PFR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 0, + .access =3D PL1_R, +#ifdef CONFIG_USER_ONLY + .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->isar.id_aa64pfr0 +#else + .type =3D ARM_CP_NO_RAW, + .accessfn =3D access_aa64_tid3, + .readfn =3D id_aa64pfr0_read, + .writefn =3D arm_cp_write_ignore +#endif + }, + { .name =3D "ID_AA64PFR1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 1, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D cpu->isar.id_aa64pfr1}, + { .name =3D "ID_AA64PFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 2, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64PFR3_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 3, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64ZFR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 4, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + /* At present, only SVEver =3D=3D 0 is defined anyway. */ + .resetvalue =3D 0 }, + { .name =3D "ID_AA64PFR5_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 5, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64PFR6_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 6, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64PFR7_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 7, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64DFR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 0, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D cpu->isar.id_aa64dfr0 }, + { .name =3D "ID_AA64DFR1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 1, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D cpu->isar.id_aa64dfr1 }, + { .name =3D "ID_AA64DFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 2, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64DFR3_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 3, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64AFR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 4, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D cpu->id_aa64afr0 }, + { .name =3D "ID_AA64AFR1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 5, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D cpu->id_aa64afr1 }, + { .name =3D "ID_AA64AFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 6, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64AFR3_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 7, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64ISAR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 0, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D cpu->isar.id_aa64isar0 }, + { .name =3D "ID_AA64ISAR1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 1, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D cpu->isar.id_aa64isar1 }, + { .name =3D "ID_AA64ISAR2_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 2, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64ISAR3_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 3, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64ISAR4_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 4, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64ISAR5_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 5, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64ISAR6_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 6, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64ISAR7_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 7, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64MMFR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 0, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D cpu->isar.id_aa64mmfr0 }, + { .name =3D "ID_AA64MMFR1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 1, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D cpu->isar.id_aa64mmfr1 }, + { .name =3D "ID_AA64MMFR2_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 2, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D cpu->isar.id_aa64mmfr2 }, + { .name =3D "ID_AA64MMFR3_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 3, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64MMFR4_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 4, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64MMFR5_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 5, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64MMFR6_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 6, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_AA64MMFR7_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 7, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "MVFR0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 0, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D cpu->isar.mvfr0 }, + { .name =3D "MVFR1_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 1, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D cpu->isar.mvfr1 }, + { .name =3D "MVFR2_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 2, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D cpu->isar.mvfr2 }, + { .name =3D "MVFR3_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 3, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "ID_PFR2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 4, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D cpu->isar.id_pfr2 }, + { .name =3D "MVFR5_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 5, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "MVFR6_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 6, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "MVFR7_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 7, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .accessfn =3D access_aa64_tid3, + .resetvalue =3D 0 }, + { .name =3D "PMCEID0", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 6, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D extract64(cpu->pmceid0, 0, 32) }, + { .name =3D "PMCEID0_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 6, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D cpu->pmceid0 }, + { .name =3D "PMCEID1", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 7, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D extract64(cpu->pmceid1, 0, 32) }, + { .name =3D "PMCEID1_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 7, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D cpu->pmceid1 }, + REGINFO_SENTINEL + }; +#ifdef CONFIG_USER_ONLY + ARMCPRegUserSpaceInfo v8_user_idregs[] =3D { + { .name =3D "ID_AA64PFR0_EL1", + .exported_bits =3D 0x000f000f00ff0000, + .fixed_bits =3D 0x0000000000000011 }, + { .name =3D "ID_AA64PFR1_EL1", + .exported_bits =3D 0x00000000000000f0 }, + { .name =3D "ID_AA64PFR*_EL1_RESERVED", + .is_glob =3D true }, + { .name =3D "ID_AA64ZFR0_EL1" }, + { .name =3D "ID_AA64MMFR0_EL1", + .fixed_bits =3D 0x00000000ff000000 }, + { .name =3D "ID_AA64MMFR1_EL1" }, + { .name =3D "ID_AA64MMFR*_EL1_RESERVED", + .is_glob =3D true }, + { .name =3D "ID_AA64DFR0_EL1", + .fixed_bits =3D 0x0000000000000006 }, + { .name =3D "ID_AA64DFR1_EL1" }, + { .name =3D "ID_AA64DFR*_EL1_RESERVED", + .is_glob =3D true }, + { .name =3D "ID_AA64AFR*", + .is_glob =3D true }, + { .name =3D "ID_AA64ISAR0_EL1", + .exported_bits =3D 0x00fffffff0fffff0 }, + { .name =3D "ID_AA64ISAR1_EL1", + .exported_bits =3D 0x000000f0ffffffff }, + { .name =3D "ID_AA64ISAR*_EL1_RESERVED", + .is_glob =3D true }, + REGUSERINFO_SENTINEL + }; + modify_arm_cp_regs(v8_idregs, v8_user_idregs); +#endif + /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ + if (!arm_feature(env, ARM_FEATURE_EL3) && + !arm_feature(env, ARM_FEATURE_EL2)) { + ARMCPRegInfo rvbar =3D { + .name =3D "RVBAR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc2 = =3D 1, + .type =3D ARM_CP_CONST, .access =3D PL1_R, .resetvalue =3D= cpu->rvbar + }; + define_one_arm_cp_reg(cpu, &rvbar); + } + define_arm_cp_regs(cpu, v8_idregs); + define_arm_cp_regs(cpu, v8_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_EL2)) { + uint64_t vmpidr_def =3D mpidr_read_val(env); + ARMCPRegInfo vpidr_regs[] =3D { + { .name =3D "VPIDR", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .resetvalue =3D cpu->midr, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.vpidr_el2) = }, + { .name =3D "VPIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D = 0, + .access =3D PL2_RW, .resetvalue =3D cpu->midr, + .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, + { .name =3D "VMPIDR", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 5, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .resetvalue =3D vmpidr_def, .type =3D ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.vmpidr_el2)= }, + { .name =3D "VMPIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D = 5, + .access =3D PL2_RW, + .resetvalue =3D vmpidr_def, + .fieldoffset =3D offsetof(CPUARMState, cp15.vmpidr_el2) }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, vpidr_regs); + define_arm_cp_regs(cpu, el2_cp_reginfo); + if (arm_feature(env, ARM_FEATURE_V8)) { + define_arm_cp_regs(cpu, el2_v8_cp_reginfo); + } + if (cpu_isar_feature(aa64_sel2, cpu)) { + define_arm_cp_regs(cpu, el2_sec_cp_reginfo); + } + /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ + if (!arm_feature(env, ARM_FEATURE_EL3)) { + ARMCPRegInfo rvbar =3D { + .name =3D "RVBAR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 = =3D 1, + .type =3D ARM_CP_CONST, .access =3D PL2_R, .resetvalue =3D= cpu->rvbar + }; + define_one_arm_cp_reg(cpu, &rvbar); + } + } else { + /* + * If EL2 is missing but higher ELs are enabled, we need to + * register the no_el2 reginfos. + */ + if (arm_feature(env, ARM_FEATURE_EL3)) { + /* + * When EL3 exists but not EL2, VPIDR and VMPIDR take the value + * of MIDR_EL1 and MPIDR_EL1. + */ + ARMCPRegInfo vpidr_regs[] =3D { + { .name =3D "VPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 = =3D 0, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->midr, + .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, + { .name =3D "VMPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 = =3D 5, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .type =3D ARM_CP_NO_RAW, + .writefn =3D arm_cp_write_ignore, .readfn =3D mpidr_read= }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, vpidr_regs); + define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); + if (arm_feature(env, ARM_FEATURE_V8)) { + define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo); + } + } + } + if (arm_feature(env, ARM_FEATURE_EL3)) { + define_arm_cp_regs(cpu, el3_cp_reginfo); + ARMCPRegInfo el3_regs[] =3D { + { .name =3D "RVBAR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 12, .crm =3D 0, .opc2 =3D= 1, + .type =3D ARM_CP_CONST, .access =3D PL3_R, .resetvalue =3D c= pu->rvbar }, + { .name =3D "SCTLR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 0, .opc2 =3D = 0, + .access =3D PL3_RW, + .raw_writefn =3D raw_write, .writefn =3D sctlr_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr_el[3]), + .resetvalue =3D cpu->reset_sctlr }, + REGINFO_SENTINEL + }; + + define_arm_cp_regs(cpu, el3_regs); + } + /* + * The behaviour of NSACR is sufficiently various that we don't + * try to describe it in a single reginfo: + * if EL3 is 64 bit, then trap to EL3 from S EL1, + * reads as constant 0xc00 from NS EL1 and NS EL2 + * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 + * if v7 without EL3, register doesn't exist + * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 + */ + if (arm_feature(env, ARM_FEATURE_EL3)) { + if (arm_feature(env, ARM_FEATURE_AARCH64)) { + ARMCPRegInfo nsacr =3D { + .name =3D "NSACR", .type =3D ARM_CP_CONST, + .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, + .access =3D PL1_RW, .accessfn =3D nsacr_access, + .resetvalue =3D 0xc00 + }; + define_one_arm_cp_reg(cpu, &nsacr); + } else { + ARMCPRegInfo nsacr =3D { + .name =3D "NSACR", + .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, + .access =3D PL3_RW | PL1_R, + .resetvalue =3D 0, + .fieldoffset =3D offsetof(CPUARMState, cp15.nsacr) + }; + define_one_arm_cp_reg(cpu, &nsacr); + } + } else { + if (arm_feature(env, ARM_FEATURE_V8)) { + ARMCPRegInfo nsacr =3D { + .name =3D "NSACR", .type =3D ARM_CP_CONST, + .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, + .access =3D PL1_R, + .resetvalue =3D 0xc00 + }; + define_one_arm_cp_reg(cpu, &nsacr); + } + } + + if (arm_feature(env, ARM_FEATURE_PMSA)) { + if (arm_feature(env, ARM_FEATURE_V6)) { + /* PMSAv6 not implemented */ + assert(arm_feature(env, ARM_FEATURE_V7)); + define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); + define_arm_cp_regs(cpu, pmsav7_cp_reginfo); + } else { + define_arm_cp_regs(cpu, pmsav5_cp_reginfo); + } + } else { + define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); + define_arm_cp_regs(cpu, vmsa_cp_reginfo); + /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */ + if (cpu_isar_feature(aa32_hpd, cpu)) { + define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); + } + } + if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { + define_arm_cp_regs(cpu, t2ee_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { + define_arm_cp_regs(cpu, generic_timer_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_VAPA)) { + define_arm_cp_regs(cpu, vapa_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { + define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { + define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { + define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_OMAPCP)) { + define_arm_cp_regs(cpu, omap_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_STRONGARM)) { + define_arm_cp_regs(cpu, strongarm_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_XSCALE)) { + define_arm_cp_regs(cpu, xscale_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { + define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); + } + if (arm_feature(env, ARM_FEATURE_LPAE)) { + define_arm_cp_regs(cpu, lpae_cp_reginfo); + } + if (cpu_isar_feature(aa32_jazelle, cpu)) { + define_arm_cp_regs(cpu, jazelle_regs); + } + /* + * Slightly awkwardly, the OMAP and StrongARM cores need all of + * cp15 crn=3D0 to be writes-ignored, whereas for other cores they sho= uld + * be read-only (ie write causes UNDEF exception). + */ + { + ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] =3D { + /* + * Pre-v8 MIDR space. + * Note that the MIDR isn't a simple constant register because + * of the TI925 behaviour where writes to another register can + * cause the MIDR value to change. + * + * Unimplemented registers in the c15 0 0 0 space default to + * MIDR. Define MIDR first as this entire space, then CTR, TCM= TR + * and friends override accordingly. + */ + { .name =3D "MIDR", + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D C= P_ANY, + .access =3D PL1_R, .resetvalue =3D cpu->midr, + .writefn =3D arm_cp_write_ignore, .raw_writefn =3D raw_write, + .readfn =3D midr_read, + .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), + .type =3D ARM_CP_OVERRIDE }, + /* crn =3D 0 op1 =3D 0 crm =3D 3..7 : currently unassigned; we= RAZ. */ + { .name =3D "DUMMY", + .cp =3D 15, .crn =3D 0, .crm =3D 3, .opc1 =3D 0, .opc2 =3D C= P_ANY, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, + { .name =3D "DUMMY", + .cp =3D 15, .crn =3D 0, .crm =3D 4, .opc1 =3D 0, .opc2 =3D C= P_ANY, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, + { .name =3D "DUMMY", + .cp =3D 15, .crn =3D 0, .crm =3D 5, .opc1 =3D 0, .opc2 =3D C= P_ANY, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, + { .name =3D "DUMMY", + .cp =3D 15, .crn =3D 0, .crm =3D 6, .opc1 =3D 0, .opc2 =3D C= P_ANY, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, + { .name =3D "DUMMY", + .cp =3D 15, .crn =3D 0, .crm =3D 7, .opc1 =3D 0, .opc2 =3D C= P_ANY, + .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, + REGINFO_SENTINEL + }; + ARMCPRegInfo id_v8_midr_cp_reginfo[] =3D { + { .name =3D "MIDR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 0, + .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, .resetvalue =3D = cpu->midr, + .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), + .readfn =3D midr_read }, + /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 4,7 : AArch32 aliases= of MIDR */ + { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4, + .access =3D PL1_R, .resetvalue =3D cpu->midr }, + { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 7, + .access =3D PL1_R, .resetvalue =3D cpu->midr }, + { .name =3D "REVIDR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 6, + .access =3D PL1_R, + .accessfn =3D access_aa64_tid1, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->revidr }, + REGINFO_SENTINEL + }; + ARMCPRegInfo id_cp_reginfo[] =3D { + /* These are common to v8 and pre-v8 */ + { .name =3D "CTR", + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 1, + .access =3D PL1_R, .accessfn =3D ctr_el0_access, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->ctr }, + { .name =3D "CTR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 0, .crm =3D = 0, + .access =3D PL0_R, .accessfn =3D ctr_el0_access, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->ctr }, + /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ + { .name =3D "TCMTR", + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, + .access =3D PL1_R, + .accessfn =3D access_aa32_tid1, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL + }; + /* TLBTR is specific to VMSA */ + ARMCPRegInfo id_tlbtr_reginfo =3D { + .name =3D "TLBTR", + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 3, + .access =3D PL1_R, + .accessfn =3D access_aa32_tid1, + .type =3D ARM_CP_CONST, .resetvalue =3D 0, + }; + /* MPUIR is specific to PMSA V6+ */ + ARMCPRegInfo id_mpuir_reginfo =3D { + .name =3D "MPUIR", + .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4, + .access =3D PL1_R, .type =3D ARM_CP_CONST, + .resetvalue =3D cpu->pmsav7_dregion << 8 + }; + ARMCPRegInfo crn0_wi_reginfo =3D { + .name =3D "CRN0_WI", .cp =3D 15, .crn =3D 0, .crm =3D CP_ANY, + .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_W, + .type =3D ARM_CP_NOP | ARM_CP_OVERRIDE + }; +#ifdef CONFIG_USER_ONLY + ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] =3D { + { .name =3D "MIDR_EL1", + .exported_bits =3D 0x00000000ffffffff }, + { .name =3D "REVIDR_EL1" }, + REGUSERINFO_SENTINEL + }; + modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_regin= fo); +#endif + if (arm_feature(env, ARM_FEATURE_OMAPCP) || + arm_feature(env, ARM_FEATURE_STRONGARM)) { + ARMCPRegInfo *r; + /* + * Register the blanket "writes ignored" value first to cover = the + * whole space. Then update the specific ID registers to allow= write + * access, so that they ignore writes rather than causing them= to + * UNDEF. + */ + define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); + for (r =3D id_pre_v8_midr_cp_reginfo; + r->type !=3D ARM_CP_SENTINEL; r++) { + r->access =3D PL1_RW; + } + for (r =3D id_cp_reginfo; r->type !=3D ARM_CP_SENTINEL; r++) { + r->access =3D PL1_RW; + } + id_mpuir_reginfo.access =3D PL1_RW; + id_tlbtr_reginfo.access =3D PL1_RW; + } + if (arm_feature(env, ARM_FEATURE_V8)) { + define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); + } else { + define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); + } + define_arm_cp_regs(cpu, id_cp_reginfo); + if (!arm_feature(env, ARM_FEATURE_PMSA)) { + define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); + } else if (arm_feature(env, ARM_FEATURE_V7)) { + define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); + } + } + + if (arm_feature(env, ARM_FEATURE_MPIDR)) { + ARMCPRegInfo mpidr_cp_reginfo[] =3D { + { .name =3D "MPIDR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D = 5, + .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D ARM_CP_= NO_RAW }, + REGINFO_SENTINEL + }; +#ifdef CONFIG_USER_ONLY + ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] =3D { + { .name =3D "MPIDR_EL1", + .fixed_bits =3D 0x0000000080000000 }, + REGUSERINFO_SENTINEL + }; + modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); +#endif + define_arm_cp_regs(cpu, mpidr_cp_reginfo); + } + + if (arm_feature(env, ARM_FEATURE_AUXCR)) { + ARMCPRegInfo auxcr_reginfo[] =3D { + { .name =3D "ACTLR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, + .access =3D PL1_RW, .accessfn =3D access_tacr, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->reset_auxcr }, + { .name =3D "ACTLR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "ACTLR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, + .access =3D PL3_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, auxcr_reginfo); + if (cpu_isar_feature(aa32_ac2, cpu)) { + define_arm_cp_regs(cpu, actlr2_hactlr2_reginfo); + } + } + + if (arm_feature(env, ARM_FEATURE_CBAR)) { + /* + * CBAR is IMPDEF, but common on Arm Cortex-A implementations. + * There are two flavours: + * (1) older 32-bit only cores have a simple 32-bit CBAR + * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a + * 32-bit register visible to AArch32 at a different encoding + * to the "flavour 1" register and with the bits rearranged to + * be able to squash a 64-bit address into the 32-bit view. + * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but + * in future if we support AArch32-only configs of some of the + * AArch64 cores we might need to add a specific feature flag + * to indicate cores with "flavour 2" CBAR. + */ + if (arm_feature(env, ARM_FEATURE_AARCH64)) { + /* 32 bit view is [31:18] 0...0 [43:32]. */ + uint32_t cbar32 =3D (extract64(cpu->reset_cbar, 18, 14) << 18) + | extract64(cpu->reset_cbar, 32, 12); + ARMCPRegInfo cbar_reginfo[] =3D { + { .name =3D "CBAR", + .type =3D ARM_CP_CONST, + .cp =3D 15, .crn =3D 15, .crm =3D 3, .opc1 =3D 1, .opc2 = =3D 0, + .access =3D PL1_R, .resetvalue =3D cbar32 }, + { .name =3D "CBAR_EL1", .state =3D ARM_CP_STATE_AA64, + .type =3D ARM_CP_CONST, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 3, .opc2= =3D 0, + .access =3D PL1_R, .resetvalue =3D cpu->reset_cbar }, + REGINFO_SENTINEL + }; + /* We don't implement a r/w 64 bit CBAR currently */ + assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); + define_arm_cp_regs(cpu, cbar_reginfo); + } else { + ARMCPRegInfo cbar =3D { + .name =3D "CBAR", + .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D 4, .opc2 = =3D 0, + .access =3D PL1_R|PL3_W, .resetvalue =3D cpu->reset_cbar, + .fieldoffset =3D offsetof(CPUARMState, + cp15.c15_config_base_address) + }; + if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { + cbar.access =3D PL1_R; + cbar.fieldoffset =3D 0; + cbar.type =3D ARM_CP_CONST; + } + define_one_arm_cp_reg(cpu, &cbar); + } + } + + if (arm_feature(env, ARM_FEATURE_VBAR)) { + ARMCPRegInfo vbar_cp_reginfo[] =3D { + { .name =3D "VBAR", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .crn =3D 12, .crm =3D 0, .opc1 =3D 0, .opc2 =3D= 0, + .access =3D PL1_RW, .writefn =3D vbar_write, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.vbar_s), + offsetof(CPUARMState, cp15.vbar_ns) }, + .resetvalue =3D 0 }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, vbar_cp_reginfo); + } + + /* Generic registers whose values depend on the implementation */ + { + ARMCPRegInfo sctlr =3D { + .name =3D "SCTLR", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.sctlr_s), + offsetof(CPUARMState, cp15.sctlr_ns) }, + .writefn =3D sctlr_write, .resetvalue =3D cpu->reset_sctlr, + .raw_writefn =3D raw_write, + }; + if (arm_feature(env, ARM_FEATURE_XSCALE)) { + /* Normally we would always end the TB on an SCTLR write, but = Linux + * arch/arm/mach-pxa/sleep.S expects two instructions following + * an MMU enable to execute from cache. Imitate this behaviou= r. + */ + sctlr.type |=3D ARM_CP_SUPPRESS_TB_END; + } + define_one_arm_cp_reg(cpu, &sctlr); + } + + if (cpu_isar_feature(aa64_lor, cpu)) { + define_arm_cp_regs(cpu, lor_reginfo); + } + if (cpu_isar_feature(aa64_pan, cpu)) { + define_one_arm_cp_reg(cpu, &pan_reginfo); + } +#ifndef CONFIG_USER_ONLY + if (cpu_isar_feature(aa64_ats1e1, cpu)) { + define_arm_cp_regs(cpu, ats1e1_reginfo); + } + if (cpu_isar_feature(aa32_ats1e1, cpu)) { + define_arm_cp_regs(cpu, ats1cp_reginfo); + } +#endif + if (cpu_isar_feature(aa64_uao, cpu)) { + define_one_arm_cp_reg(cpu, &uao_reginfo); + } + + if (cpu_isar_feature(aa64_dit, cpu)) { + define_one_arm_cp_reg(cpu, &dit_reginfo); + } + if (cpu_isar_feature(aa64_ssbs, cpu)) { + define_one_arm_cp_reg(cpu, &ssbs_reginfo); + } + + if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { + define_arm_cp_regs(cpu, vhe_reginfo); + } + + if (cpu_isar_feature(aa64_sve, cpu)) { + define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); + if (arm_feature(env, ARM_FEATURE_EL2)) { + define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); + } else { + define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo); + } + if (arm_feature(env, ARM_FEATURE_EL3)) { + define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); + } + } + +#ifdef TARGET_AARCH64 + if (cpu_isar_feature(aa64_pauth, cpu)) { + define_arm_cp_regs(cpu, pauth_reginfo); + } + if (cpu_isar_feature(aa64_rndr, cpu)) { + define_arm_cp_regs(cpu, rndr_reginfo); + } +#ifndef CONFIG_USER_ONLY + /* Data Cache clean instructions up to PoP */ + if (cpu_isar_feature(aa64_dcpop, cpu)) { + define_one_arm_cp_reg(cpu, dcpop_reg); + + if (cpu_isar_feature(aa64_dcpodp, cpu)) { + define_one_arm_cp_reg(cpu, dcpodp_reg); + } + } +#endif /*CONFIG_USER_ONLY*/ + + /* + * If full MTE is enabled, add all of the system registers. + * If only "instructions available at EL0" are enabled, + * then define only a RAZ/WI version of PSTATE.TCO. + */ + if (cpu_isar_feature(aa64_mte, cpu)) { + define_arm_cp_regs(cpu, mte_reginfo); + define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); + } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { + define_arm_cp_regs(cpu, mte_tco_ro_reginfo); + define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); + } +#endif + + if (cpu_isar_feature(any_predinv, cpu)) { + define_arm_cp_regs(cpu, predinv_reginfo); + } + + if (cpu_isar_feature(any_ccidx, cpu)) { + define_arm_cp_regs(cpu, ccsidr2_reginfo); + } + +#ifndef CONFIG_USER_ONLY + /* + * Register redirections and aliases must be done last, + * after the registers from the other extensions have been defined. + */ + if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { + define_arm_vh_e2h_redirects_aliases(cpu); + } +#endif +} + +/* + * Modify ARMCPRegInfo for access from userspace. + * + * This is a data driven modification directed by + * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as + * user-space cannot alter any values and dynamic values pertaining to + * execution state are hidden from user space view anyway. + */ +void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods) +{ + const ARMCPRegUserSpaceInfo *m; + ARMCPRegInfo *r; + + for (m =3D mods; m->name; m++) { + GPatternSpec *pat =3D NULL; + if (m->is_glob) { + pat =3D g_pattern_spec_new(m->name); + } + for (r =3D regs; r->type !=3D ARM_CP_SENTINEL; r++) { + if (pat && g_pattern_match_string(pat, r->name)) { + r->type =3D ARM_CP_CONST; + r->access =3D PL0U_R; + r->resetvalue =3D 0; + /* continue */ + } else if (strcmp(r->name, m->name) =3D=3D 0) { + r->type =3D ARM_CP_CONST; + r->access =3D PL0U_R; + r->resetvalue &=3D m->exported_bits; + r->resetvalue |=3D m->fixed_bits; + break; + } + } + if (pat) { + g_pattern_spec_free(pat); + } + } +} diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index 0f4ebcc46f..09503db37b 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -37,9 +37,7 @@ #include "semihosting/common-semi.h" #endif #include "cpu-mmu.h" - -#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ -#define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */ +#include "cpregs.h" =20 static void switch_mode(CPUARMState *env, int mode); =20 @@ -138,65 +136,6 @@ static int aarch64_fpu_gdb_set_reg(CPUARMState *env, u= int8_t *buf, int reg) } } =20 -static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - assert(ri->fieldoffset); - if (cpreg_field_is_64bit(ri)) { - return CPREG_FIELD64(env, ri); - } else { - return CPREG_FIELD32(env, ri); - } -} - -static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - assert(ri->fieldoffset); - if (cpreg_field_is_64bit(ri)) { - CPREG_FIELD64(env, ri) =3D value; - } else { - CPREG_FIELD32(env, ri) =3D value; - } -} - -static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return (char *)env + ri->fieldoffset; -} - -uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri) -{ - /* Raw read of a coprocessor register (as needed for migration, etc). = */ - if (ri->type & ARM_CP_CONST) { - return ri->resetvalue; - } else if (ri->raw_readfn) { - return ri->raw_readfn(env, ri); - } else if (ri->readfn) { - return ri->readfn(env, ri); - } else { - return raw_read(env, ri); - } -} - -static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t v) -{ - /* Raw write of a coprocessor register (as needed for migration, etc). - * Note that constant registers are treated as write-ignored; the - * caller should check for success by whether a readback gives the - * value written. - */ - if (ri->type & ARM_CP_CONST) { - return; - } else if (ri->raw_writefn) { - ri->raw_writefn(env, ri, v); - } else if (ri->writefn) { - ri->writefn(env, ri, v); - } else { - raw_write(env, ri, v); - } -} - /** * arm_get/set_gdb_*: get/set a gdb register * @env: the CPU state @@ -325,8407 +264,358 @@ static int arm_gdb_set_svereg(CPUARMState *env, ui= nt8_t *buf, int reg) } #endif /* TARGET_AARCH64 */ =20 -static bool raw_accessors_invalid(const ARMCPRegInfo *ri) -{ - /* - * Return true if the regdef would cause an assertion if you called - * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a - * program bug for it not to have the NO_RAW flag). - * NB that returning false here doesn't necessarily mean that calling - * read/write_raw_cp_reg() is safe, because we can't distinguish "has - * read/write access functions which are safe for raw use" from "has - * read/write access functions which have side effects but has forgotten - * to provide raw access functions". - * The tests here line up with the conditions in read/write_raw_cp_reg() - * and assertions in raw_read()/raw_write(). - */ - if ((ri->type & ARM_CP_CONST) || - ri->fieldoffset || - ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn= ))) { - return false; - } - return true; -} - -bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync) -{ - /* Write the coprocessor state from cpu->env to the (index,value) list= . */ - int i; - bool ok =3D true; - - for (i =3D 0; i < cpu->cpreg_array_len; i++) { - uint32_t regidx =3D kvm_to_cpreg_id(cpu->cpreg_indexes[i]); - const ARMCPRegInfo *ri; - uint64_t newval; - - ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); - if (!ri) { - ok =3D false; - continue; - } - if (ri->type & ARM_CP_NO_RAW) { - continue; - } - - newval =3D read_raw_cp_reg(&cpu->env, ri); - if (kvm_sync) { - /* - * Only sync if the previous list->cpustate sync succeeded. - * Rather than tracking the success/failure state for every - * item in the list, we just recheck "does the raw write we mu= st - * have made in write_list_to_cpustate() read back OK" here. - */ - uint64_t oldval =3D cpu->cpreg_values[i]; - - if (oldval =3D=3D newval) { - continue; - } - - write_raw_cp_reg(&cpu->env, ri, oldval); - if (read_raw_cp_reg(&cpu->env, ri) !=3D oldval) { - continue; - } - - write_raw_cp_reg(&cpu->env, ri, newval); - } - cpu->cpreg_values[i] =3D newval; - } - return ok; -} - -bool write_list_to_cpustate(ARMCPU *cpu) +/* + * Return the effective value of HCR_EL2. + * Bits that are not included here: + * RW (read from SCR_EL3.RW as needed) + */ +uint64_t arm_hcr_el2_eff(CPUARMState *env) { - int i; - bool ok =3D true; - - for (i =3D 0; i < cpu->cpreg_array_len; i++) { - uint32_t regidx =3D kvm_to_cpreg_id(cpu->cpreg_indexes[i]); - uint64_t v =3D cpu->cpreg_values[i]; - const ARMCPRegInfo *ri; + uint64_t ret =3D env->cp15.hcr_el2; =20 - ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); - if (!ri) { - ok =3D false; - continue; - } - if (ri->type & ARM_CP_NO_RAW) { - continue; - } - /* Write value and confirm it reads back as written - * (to catch read-only registers and partially read-only - * registers where the incoming migration value doesn't match) + if (!arm_is_el2_enabled(env)) { + /* + * "This register has no effect if EL2 is not enabled in the + * current Security state". This is ARMv8.4-SecEL2 speak for + * !(SCR_EL3.NS=3D=3D1 || SCR_EL3.EEL2=3D=3D1). + * + * Prior to that, the language was "In an implementation that + * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves + * as if this field is 0 for all purposes other than a direct + * read or write access of HCR_EL2". With lots of enumeration + * on a per-field basis. In current QEMU, this is condition + * is arm_is_secure_below_el3. + * + * Since the v8.4 language applies to the entire register, and + * appears to be backward compatible, use that. */ - write_raw_cp_reg(&cpu->env, ri, v); - if (read_raw_cp_reg(&cpu->env, ri) !=3D v) { - ok =3D false; - } + return 0; } - return ok; -} =20 -static void add_cpreg_to_list(gpointer key, gpointer opaque) -{ - ARMCPU *cpu =3D opaque; - uint64_t regidx; - const ARMCPRegInfo *ri; - - regidx =3D *(uint32_t *)key; - ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + /* + * For a cpu that supports both aarch64 and aarch32, we can set bits + * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32. + * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32. + */ + if (!arm_el_is_aa64(env, 2)) { + uint64_t aa32_valid; =20 - if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { - cpu->cpreg_indexes[cpu->cpreg_array_len] =3D cpreg_to_kvm_id(regid= x); - /* The value array need not be initialized at this point */ - cpu->cpreg_array_len++; + /* + * These bits are up-to-date as of ARMv8.6. + * For HCR, it's easiest to list just the 2 bits that are invalid. + * For HCR2, list those that are valid. + */ + aa32_valid =3D MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ); + aa32_valid |=3D (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNC= E | + HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS); + ret &=3D aa32_valid; } -} =20 -static void count_cpreg(gpointer key, gpointer opaque) -{ - ARMCPU *cpu =3D opaque; - uint64_t regidx; - const ARMCPRegInfo *ri; - - regidx =3D *(uint32_t *)key; - ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); - - if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { - cpu->cpreg_array_len++; + if (ret & HCR_TGE) { + /* These bits are up-to-date as of ARMv8.6. */ + if (ret & HCR_E2H) { + ret &=3D ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | + HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | + HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | + HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE | + HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT | + HCR_TTLBIS | HCR_TTLBOS | HCR_TID5); + } else { + ret |=3D HCR_FMO | HCR_IMO | HCR_AMO; + } + ret &=3D ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | + HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | + HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | + HCR_TLOR); } -} - -static gint cpreg_key_compare(gconstpointer a, gconstpointer b) -{ - uint64_t aidx =3D cpreg_to_kvm_id(*(uint32_t *)a); - uint64_t bidx =3D cpreg_to_kvm_id(*(uint32_t *)b); =20 - if (aidx > bidx) { - return 1; - } - if (aidx < bidx) { - return -1; - } - return 0; + return ret; } =20 -void init_cpreg_list(ARMCPU *cpu) +/* Return the exception level to which exceptions should be taken + * via SVEAccessTrap. If an exception should be routed through + * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should + * take care of raising that exception. + * C.f. the ARM pseudocode function CheckSVEEnabled. + */ +int sve_exception_el(CPUARMState *env, int el) { - /* - * Initialise the cpreg_tuples[] array based on the cp_regs hash. - * Note that we require cpreg_tuples[] to be sorted by key ID. - */ - GList *keys; - int arraylen; - - keys =3D g_hash_table_get_keys(cpu->cp_regs); - keys =3D g_list_sort(keys, cpreg_key_compare); - - cpu->cpreg_array_len =3D 0; - - g_list_foreach(keys, count_cpreg, cpu); - - arraylen =3D cpu->cpreg_array_len; - cpu->cpreg_indexes =3D g_new(uint64_t, arraylen); - cpu->cpreg_values =3D g_new(uint64_t, arraylen); - cpu->cpreg_vmstate_indexes =3D g_new(uint64_t, arraylen); - cpu->cpreg_vmstate_values =3D g_new(uint64_t, arraylen); - cpu->cpreg_vmstate_array_len =3D cpu->cpreg_array_len; - cpu->cpreg_array_len =3D 0; - - g_list_foreach(keys, add_cpreg_to_list, cpu); +#ifndef CONFIG_USER_ONLY + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); =20 - assert(cpu->cpreg_array_len =3D=3D arraylen); + if (el <=3D 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { + bool disabled =3D false; =20 - g_list_free(keys); -} + /* The CPACR.ZEN controls traps to EL1: + * 0, 2 : trap EL0 and EL1 accesses + * 1 : trap only EL0 accesses + * 3 : trap no accesses + */ + if (!extract32(env->cp15.cpacr_el1, 16, 1)) { + disabled =3D true; + } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) { + disabled =3D el =3D=3D 0; + } + if (disabled) { + /* route_to_el2 */ + return hcr_el2 & HCR_TGE ? 2 : 1; + } =20 -/* - * Some registers are not accessible from AArch32 EL3 if SCR.NS =3D=3D 0. - */ -static CPAccessResult access_el3_aa32ns(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - if (!is_a64(env) && arm_current_el(env) =3D=3D 3 && - arm_is_secure_below_el3(env)) { - return CP_ACCESS_TRAP_UNCATEGORIZED; + /* Check CPACR.FPEN. */ + if (!extract32(env->cp15.cpacr_el1, 20, 1)) { + disabled =3D true; + } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) { + disabled =3D el =3D=3D 0; + } + if (disabled) { + return 0; + } } - return CP_ACCESS_OK; -} =20 -/* - * Some secure-only AArch32 registers trap to EL3 if used from - * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). - * Note that an access from Secure EL1 can only happen if EL3 is AArch64. - * We assume that the .access field is set to PL1_RW. - */ -static CPAccessResult access_trap_aa32s_el1(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - if (arm_current_el(env) =3D=3D 3) { - return CP_ACCESS_OK; - } - if (arm_is_secure_below_el3(env)) { - if (env->cp15.scr_el3 & SCR_EEL2) { - return CP_ACCESS_TRAP_EL2; + /* CPTR_EL2. Since TZ and TFP are positive, + * they will be zero when EL2 is not present. + */ + if (el <=3D 2 && arm_is_el2_enabled(env)) { + if (env->cp15.cptr_el[2] & CPTR_TZ) { + return 2; + } + if (env->cp15.cptr_el[2] & CPTR_TFP) { + return 0; } - return CP_ACCESS_TRAP_EL3; } - /* This will be EL1 NS and EL2 NS, which just UNDEF */ - return CP_ACCESS_TRAP_UNCATEGORIZED; -} - -static uint64_t arm_mdcr_el2_eff(CPUARMState *env) -{ - return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0; -} - -/* - * Check for traps to "powerdown debug" registers, which are controlled - * by MDCR.TDOSA - */ -static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *r= i, - bool isread) -{ - int el =3D arm_current_el(env); - uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); - bool mdcr_el2_tdosa =3D (mdcr_el2 & MDCR_TDOSA) || (mdcr_el2 & MDCR_TD= E) || - (arm_hcr_el2_eff(env) & HCR_TGE); =20 - if (el < 2 && mdcr_el2_tdosa) { - return CP_ACCESS_TRAP_EL2; - } - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { - return CP_ACCESS_TRAP_EL3; + /* CPTR_EL3. Since EZ is negative we must check for EL3. */ + if (arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.cptr_el[3] & CPTR_EZ)) { + return 3; } - return CP_ACCESS_OK; +#endif + return 0; } =20 -/* - * Check for traps to "debug ROM" registers, which are controlled - * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3. - */ -static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) +static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) { - int el =3D arm_current_el(env); - uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); - bool mdcr_el2_tdra =3D (mdcr_el2 & MDCR_TDRA) || (mdcr_el2 & MDCR_TDE)= || - (arm_hcr_el2_eff(env) & HCR_TGE); + uint32_t end_len; =20 - if (el < 2 && mdcr_el2_tdra) { - return CP_ACCESS_TRAP_EL2; - } - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { - return CP_ACCESS_TRAP_EL3; + end_len =3D start_len &=3D 0xf; + if (!test_bit(start_len, cpu->sve_vq_map)) { + end_len =3D find_last_bit(cpu->sve_vq_map, start_len); + assert(end_len < start_len); } - return CP_ACCESS_OK; + return end_len; } =20 /* - * Check for traps to general debug registers, which are controlled - * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3. + * Given that SVE is enabled, return the vector length for EL. */ -static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) +uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) { - int el =3D arm_current_el(env); - uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); - bool mdcr_el2_tda =3D (mdcr_el2 & MDCR_TDA) || (mdcr_el2 & MDCR_TDE) || - (arm_hcr_el2_eff(env) & HCR_TGE); + ARMCPU *cpu =3D env_archcpu(env); + uint32_t zcr_len =3D cpu->sve_max_vq - 1; =20 - if (el < 2 && mdcr_el2_tda) { - return CP_ACCESS_TRAP_EL2; - } - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { - return CP_ACCESS_TRAP_EL3; + if (el <=3D 1) { + zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); } - return CP_ACCESS_OK; -} - -/* - * Check for traps to performance monitor registers, which are controlled - * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3. - */ -static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - int el =3D arm_current_el(env); - uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); - - if (el < 2 && (mdcr_el2 & MDCR_TPM)) { - return CP_ACCESS_TRAP_EL2; + if (el <=3D 2 && arm_feature(env, ARM_FEATURE_EL2)) { + zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); } - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { - return CP_ACCESS_TRAP_EL3; + if (arm_feature(env, ARM_FEATURE_EL3)) { + zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); } - return CP_ACCESS_OK; -} =20 -/* Check for traps from EL1 due to HCR_EL2.TVM and HCR_EL2.TRVM. */ -static CPAccessResult access_tvm_trvm(CPUARMState *env, const ARMCPRegInfo= *ri, - bool isread) -{ - if (arm_current_el(env) =3D=3D 1) { - uint64_t trap =3D isread ? HCR_TRVM : HCR_TVM; - if (arm_hcr_el2_eff(env) & trap) { - return CP_ACCESS_TRAP_EL2; - } - } - return CP_ACCESS_OK; + return sve_zcr_get_valid_len(cpu, zcr_len); } =20 -/* Check for traps from EL1 due to HCR_EL2.TSW. */ -static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) +void hw_watchpoint_update(ARMCPU *cpu, int n) { - if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) { - return CP_ACCESS_TRAP_EL2; - } - return CP_ACCESS_OK; -} + CPUARMState *env =3D &cpu->env; + vaddr len =3D 0; + vaddr wvr =3D env->cp15.dbgwvr[n]; + uint64_t wcr =3D env->cp15.dbgwcr[n]; + int mask; + int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; =20 -/* Check for traps from EL1 due to HCR_EL2.TACR. */ -static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TACR))= { - return CP_ACCESS_TRAP_EL2; + if (env->cpu_watchpoint[n]) { + cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); + env->cpu_watchpoint[n] =3D NULL; } - return CP_ACCESS_OK; -} =20 -/* Check for traps from EL1 due to HCR_EL2.TTLB. */ -static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TTLB))= { - return CP_ACCESS_TRAP_EL2; + if (!extract64(wcr, 0, 1)) { + /* E bit clear : watchpoint disabled */ + return; } - return CP_ACCESS_OK; -} =20 -static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) -{ - ARMCPU *cpu =3D env_archcpu(env); - - raw_write(env, ri, value); - tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */ -} - -static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) -{ - ARMCPU *cpu =3D env_archcpu(env); - - if (raw_read(env, ri) !=3D value) { - /* - * Unlike real hardware the qemu TLB uses virtual addresses, - * not modified virtual addresses, so this causes a TLB flush. - */ - tlb_flush(CPU(cpu)); - raw_write(env, ri, value); - } -} - -static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - - if (raw_read(env, ri) !=3D value && !arm_feature(env, ARM_FEATURE_PMSA) - && !extended_addresses_enabled(env)) { - /* - * For VMSA (when not using the LPAE long descriptor page table - * format) this register includes the ASID, so do a TLB flush. - * For PMSA it is purely a process ID and no action is needed. - */ - tlb_flush(CPU(cpu)); - } - raw_write(env, ri, value); -} - -/* IS variants of TLB operations must affect all cores */ -static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - - tlb_flush_all_cpus_synced(cs); -} - -static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - - tlb_flush_all_cpus_synced(cs); -} - -static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - - tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); -} - -static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - - tlb_flush_page_all_cpus_synced(cs, value & TARGET_PAGE_MASK); -} - -/* - * Non-IS variants of TLB operations are upgraded to - * IS versions if we are at EL1 and HCR_EL2.FB is effectively set to - * force broadcast of these operations. - */ -static bool tlb_force_broadcast(CPUARMState *env) -{ - return arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_FB); -} - -static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Invalidate all (TLBIALL) */ - CPUState *cs =3D env_cpu(env); - - if (tlb_force_broadcast(env)) { - tlb_flush_all_cpus_synced(cs); - } else { - tlb_flush(cs); - } -} - -static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */ - CPUState *cs =3D env_cpu(env); - - value &=3D TARGET_PAGE_MASK; - if (tlb_force_broadcast(env)) { - tlb_flush_page_all_cpus_synced(cs, value); - } else { - tlb_flush_page(cs, value); - } -} - -static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Invalidate by ASID (TLBIASID) */ - CPUState *cs =3D env_cpu(env); - - if (tlb_force_broadcast(env)) { - tlb_flush_all_cpus_synced(cs); - } else { - tlb_flush(cs); - } -} - -static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */ - CPUState *cs =3D env_cpu(env); - - value &=3D TARGET_PAGE_MASK; - if (tlb_force_broadcast(env)) { - tlb_flush_page_all_cpus_synced(cs, value); - } else { - tlb_flush_page(cs, value); - } -} - -static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_E10_1 | - ARMMMUIdxBit_E10_1_PAN | - ARMMMUIdxBit_E10_0); -} - -static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - - tlb_flush_by_mmuidx_all_cpus_synced(cs, - ARMMMUIdxBit_E10_1 | - ARMMMUIdxBit_E10_1_PAN | - ARMMMUIdxBit_E10_0); -} - - -static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); -} - -static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); -} - -static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); - - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); -} - -static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); - - tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_E2); -} - -static const ARMCPRegInfo cp_reginfo[] =3D { - /* - * Define the secure and non-secure FCSE identifier CP registers - * separately because there is no secure bank in V8 (no _EL3). This a= llows - * the secure register to be properly reset and migrated. There is als= o no - * v8 EL1 version of the register so the non-secure instance stands al= one. - */ - { .name =3D "FCSEIDR", - .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_NS, - .fieldoffset =3D offsetof(CPUARMState, cp15.fcseidr_ns), - .resetvalue =3D 0, .writefn =3D fcse_write, .raw_writefn =3D raw_wri= te, }, - { .name =3D "FCSEIDR_S", - .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .secure =3D ARM_CP_SECSTATE_S, - .fieldoffset =3D offsetof(CPUARMState, cp15.fcseidr_s), - .resetvalue =3D 0, .writefn =3D fcse_write, .raw_writefn =3D raw_wri= te, }, - /* - * Define the secure and non-secure context identifier CP registers - * separately because there is no secure bank in V8 (no _EL3). This a= llows - * the secure register to be properly reset and migrated. In the - * non-secure case, the 32-bit register will have reset and migration - * disabled during registration as it is handled by the 64-bit instanc= e. - */ - { .name =3D "CONTEXTIDR_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .secure =3D ARM_CP_SECSTATE_NS, - .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[1]), - .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, - { .name =3D "CONTEXTIDR_S", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .secure =3D ARM_CP_SECSTATE_S, - .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_s), - .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { - /* - * NB: Some of these registers exist in v8 but with more precise - * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginf= o[]). - */ - /* MMU Domain access control / MPU write buffer control */ - { .name =3D "DACR", - .cp =3D 15, .opc1 =3D CP_ANY, .crn =3D 3, .crm =3D CP_ANY, .opc2 =3D= CP_ANY, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, - .writefn =3D dacr_write, .raw_writefn =3D raw_write, - .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dacr_s), - offsetoflow32(CPUARMState, cp15.dacr_ns) } }, - /* - * ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs. - * For v6 and v5, these mappings are overly broad. - */ - { .name =3D "TLB_LOCKDOWN", .cp =3D 15, .crn =3D 10, .crm =3D 0, - .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_NOP }, - { .name =3D "TLB_LOCKDOWN", .cp =3D 15, .crn =3D 10, .crm =3D 1, - .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_NOP }, - { .name =3D "TLB_LOCKDOWN", .cp =3D 15, .crn =3D 10, .crm =3D 4, - .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_NOP }, - { .name =3D "TLB_LOCKDOWN", .cp =3D 15, .crn =3D 10, .crm =3D 8, - .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_NOP }, - /* Cache maintenance ops; some of this space may be overridden later. = */ - { .name =3D "CACHEMAINT", .cp =3D 15, .crn =3D 7, .crm =3D CP_ANY, - .opc1 =3D 0, .opc2 =3D CP_ANY, .access =3D PL1_W, - .type =3D ARM_CP_NOP | ARM_CP_OVERRIDE }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo not_v6_cp_reginfo[] =3D { - /* - * Not all pre-v6 cores implemented this WFI, so this is slightly - * over-broad. - */ - { .name =3D "WFI_v5", .cp =3D 15, .crn =3D 7, .crm =3D 8, .opc1 =3D 0,= .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_WFI }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { - /* - * Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which - * is UNPREDICTABLE; we choose to NOP as most implementations do). - */ - { .name =3D "WFI_v6", .cp =3D 15, .crn =3D 7, .crm =3D 0, .opc1 =3D 0,= .opc2 =3D 4, - .access =3D PL1_W, .type =3D ARM_CP_WFI }, - /* - * L1 cache lockdown. Not architectural in v6 and earlier but in pract= ice - * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM a= nd - * OMAPCP will override this space. - */ - { .name =3D "DLOCKDOWN", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 0, - .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_d= ata), - .resetvalue =3D 0 }, - { .name =3D "ILOCKDOWN", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 1, - .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_i= nsn), - .resetvalue =3D 0 }, - /* v6 doesn't have the cache ID registers but Linux reads them anyway = */ - { .name =3D "DUMMY", .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, = .opc2 =3D CP_ANY, - .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, - .resetvalue =3D 0 }, - /* - * We don't implement pre-v7 debug but most CPUs had at least a DBGDID= R; - * implementing it as RAZ means the "debug architecture version" bits - * will read as a reserved value, which should cause Linux to not try - * to use the debug hardware. - */ - { .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, - .access =3D PL0_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* - * MMU TLB control. Note that the wildcarding means we cover not just - * the unified TLB ops but also the dside/iside/inner-shareable varian= ts. - */ - { .name =3D "TLBIALL", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D 0, .access =3D PL1_W, .writefn =3D tlbia= ll_write, - .type =3D ARM_CP_NO_RAW }, - { .name =3D "TLBIMVA", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D 1, .access =3D PL1_W, .writefn =3D tlbim= va_write, - .type =3D ARM_CP_NO_RAW }, - { .name =3D "TLBIASID", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D 2, .access =3D PL1_W, .writefn =3D tlbia= sid_write, - .type =3D ARM_CP_NO_RAW }, - { .name =3D "TLBIMVAA", .cp =3D 15, .crn =3D 8, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D 3, .access =3D PL1_W, .writefn =3D tlbim= vaa_write, - .type =3D ARM_CP_NO_RAW }, - { .name =3D "PRRR", .cp =3D 15, .crn =3D 10, .crm =3D 2, - .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, - { .name =3D "NMRR", .cp =3D 15, .crn =3D 10, .crm =3D 2, - .opc1 =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL -}; - -static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - uint32_t mask =3D 0; - - /* In ARMv8 most bits of CPACR_EL1 are RES0. */ - if (!arm_feature(env, ARM_FEATURE_V8)) { - /* - * ARMv7 defines bits for unimplemented coprocessors as RAZ/WI. - * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. - * TRCDIS [28] is RAZ/WI since we do not implement a trace macroce= ll. - */ - if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { - /* VFP coprocessor: cp10 & cp11 [23:20] */ - mask |=3D (1 << 31) | (1 << 30) | (0xf << 20); - - if (!arm_feature(env, ARM_FEATURE_NEON)) { - /* ASEDIS [31] bit is RAO/WI */ - value |=3D (1 << 31); - } - - /* - * VFPv3 and upwards with NEON implement 32 double precision - * registers (D0-D31). - */ - if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { - /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ - value |=3D (1 << 30); - } - } - value &=3D mask; - } - - /* - * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR= .CP10 - * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. - */ - if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && - !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { - value &=3D ~(0xf << 20); - value |=3D env->cp15.cpacr_el1 & (0xf << 20); - } - - env->cp15.cpacr_el1 =3D value; -} - -static uint64_t cpacr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - /* - * For A-profile AArch32 EL3 (but not M-profile secure mode), if NSACR= .CP10 - * is 0 then CPACR.{CP11,CP10} ignore writes and read as 0b00. - */ - uint64_t value =3D env->cp15.cpacr_el1; - - if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && - !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { - value &=3D ~(0xf << 20); - } - return value; -} - - -static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - /* - * Call cpacr_write() so that we reset with the correct RAO bits set - * for our CPU features. - */ - cpacr_write(env, ri, 0); -} - -static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *r= i, - bool isread) -{ - if (arm_feature(env, ARM_FEATURE_V8)) { - /* Check if CPACR accesses are to be trapped to EL2 */ - if (arm_current_el(env) =3D=3D 1 && arm_is_el2_enabled(env) && - (env->cp15.cptr_el[2] & CPTR_TCPAC)) { - return CP_ACCESS_TRAP_EL2; - /* Check if CPACR accesses are to be trapped to EL3 */ - } else if (arm_current_el(env) < 3 && - (env->cp15.cptr_el[3] & CPTR_TCPAC)) { - return CP_ACCESS_TRAP_EL3; - } - } - - return CP_ACCESS_OK; -} - -static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - /* Check if CPTR accesses are set to trap to EL3 */ - if (arm_current_el(env) =3D=3D 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC= )) { - return CP_ACCESS_TRAP_EL3; - } - - return CP_ACCESS_OK; -} - -static const ARMCPRegInfo v6_cp_reginfo[] =3D { - /* prefetch by MVA in v6, NOP in v7 */ - { .name =3D "MVA_prefetch", - .cp =3D 15, .crn =3D 7, .crm =3D 13, .opc1 =3D 0, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, - /* - * We need to break the TB after ISB to execute self-modifying code - * correctly and also to take any pending interrupts immediately. - * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag. - */ - { .name =3D "ISB", .cp =3D 15, .crn =3D 7, .crm =3D 5, .opc1 =3D 0, .o= pc2 =3D 4, - .access =3D PL0_W, .type =3D ARM_CP_NO_RAW, .writefn =3D arm_cp_writ= e_ignore }, - { .name =3D "DSB", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 =3D 0, .= opc2 =3D 4, - .access =3D PL0_W, .type =3D ARM_CP_NOP }, - { .name =3D "DMB", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 =3D 0, .= opc2 =3D 5, - .access =3D PL0_W, .type =3D ARM_CP_NOP }, - { .name =3D "IFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ifar_s), - offsetof(CPUARMState, cp15.ifar_ns) }, - .resetvalue =3D 0, }, - /* - * Watchpoint Fault Address Register : should actually only be present - * for 1136, 1176, 11MPCore. - */ - { .name =3D "WFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0, }, - { .name =3D "CPACR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, - .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .accessfn =3D cpac= r_access, - .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.cpac= r_el1), - .resetfn =3D cpacr_reset, .writefn =3D cpacr_write, .readfn =3D cpac= r_read }, - REGINFO_SENTINEL -}; - -/* Definitions for the PMU registers */ -#define PMCRN_MASK 0xf800 -#define PMCRN_SHIFT 11 -#define PMCRLC 0x40 -#define PMCRDP 0x20 -#define PMCRX 0x10 -#define PMCRD 0x8 -#define PMCRC 0x4 -#define PMCRP 0x2 -#define PMCRE 0x1 -/* - * Mask of PMCR bits writeable by guest (not including WO bits like C, P, - * which can be written as 1 to trigger behaviour but which stay RAZ). - */ -#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) - -#define PMXEVTYPER_P 0x80000000 -#define PMXEVTYPER_U 0x40000000 -#define PMXEVTYPER_NSK 0x20000000 -#define PMXEVTYPER_NSU 0x10000000 -#define PMXEVTYPER_NSH 0x08000000 -#define PMXEVTYPER_M 0x04000000 -#define PMXEVTYPER_MT 0x02000000 -#define PMXEVTYPER_EVTCOUNT 0x0000ffff -#define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NS= K | \ - PMXEVTYPER_NSU | PMXEVTYPER_NSH | \ - PMXEVTYPER_M | PMXEVTYPER_MT | \ - PMXEVTYPER_EVTCOUNT) - -#define PMCCFILTR 0xf8000000 -#define PMCCFILTR_M PMXEVTYPER_M -#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M) - -static inline uint32_t pmu_num_counters(CPUARMState *env) -{ - return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT; -} - -/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ -static inline uint64_t pmu_counter_mask(CPUARMState *env) -{ - return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); -} - -typedef struct pm_event { - uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */ - /* If the event is supported on this CPU (used to generate PMCEID[01])= */ - bool (*supported)(CPUARMState *); - /* - * Retrieve the current count of the underlying event. The programmed - * counters hold a difference from the return value from this function - */ - uint64_t (*get_count)(CPUARMState *); - /* - * Return how many nanoseconds it will take (at a minimum) for count e= vents - * to occur. A negative value indicates the counter will never overflo= w, or - * that the counter has otherwise arranged for the overflow bit to be = set - * and the PMU interrupt to be raised on overflow. - */ - int64_t (*ns_per_count)(uint64_t); -} pm_event; - -static bool event_always_supported(CPUARMState *env) -{ - return true; -} - -static uint64_t swinc_get_count(CPUARMState *env) -{ - /* - * SW_INCR events are written directly to the pmevcntr's by writes to - * PMSWINC, so there is no underlying count maintained by the PMU itse= lf - */ - return 0; -} - -static int64_t swinc_ns_per(uint64_t ignored) -{ - return -1; -} - -/* - * Return the underlying cycle count for the PMU cycle counters. If we're = in - * usermode, simply return 0. - */ -static uint64_t cycles_get_count(CPUARMState *env) -{ -#ifndef CONFIG_USER_ONLY - return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - ARM_CPU_FREQ, NANOSECONDS_PER_SECOND); -#else - return cpu_get_host_ticks(); -#endif -} - -#ifndef CONFIG_USER_ONLY -static int64_t cycles_ns_per(uint64_t cycles) -{ - return (ARM_CPU_FREQ / NANOSECONDS_PER_SECOND) * cycles; -} - -static bool instructions_supported(CPUARMState *env) -{ - return icount_enabled() =3D=3D 1; /* Precise instruction counting */ -} - -static uint64_t instructions_get_count(CPUARMState *env) -{ - return (uint64_t)icount_get_raw(); -} - -static int64_t instructions_ns_per(uint64_t icount) -{ - return icount_to_ns((int64_t)icount); -} -#endif - -static bool pmu_8_1_events_supported(CPUARMState *env) -{ - /* For events which are supported in any v8.1 PMU */ - return cpu_isar_feature(any_pmu_8_1, env_archcpu(env)); -} - -static bool pmu_8_4_events_supported(CPUARMState *env) -{ - /* For events which are supported in any v8.1 PMU */ - return cpu_isar_feature(any_pmu_8_4, env_archcpu(env)); -} - -static uint64_t zero_event_get_count(CPUARMState *env) -{ - /* For events which on QEMU never fire, so their count is always zero = */ - return 0; -} - -static int64_t zero_event_ns_per(uint64_t cycles) -{ - /* An event which never fires can never overflow */ - return -1; -} - -static const pm_event pm_events[] =3D { - { .number =3D 0x000, /* SW_INCR */ - .supported =3D event_always_supported, - .get_count =3D swinc_get_count, - .ns_per_count =3D swinc_ns_per, - }, -#ifndef CONFIG_USER_ONLY - { .number =3D 0x008, /* INST_RETIRED, Instruction architecturally exec= uted */ - .supported =3D instructions_supported, - .get_count =3D instructions_get_count, - .ns_per_count =3D instructions_ns_per, - }, - { .number =3D 0x011, /* CPU_CYCLES, Cycle */ - .supported =3D event_always_supported, - .get_count =3D cycles_get_count, - .ns_per_count =3D cycles_ns_per, - }, -#endif - { .number =3D 0x023, /* STALL_FRONTEND */ - .supported =3D pmu_8_1_events_supported, - .get_count =3D zero_event_get_count, - .ns_per_count =3D zero_event_ns_per, - }, - { .number =3D 0x024, /* STALL_BACKEND */ - .supported =3D pmu_8_1_events_supported, - .get_count =3D zero_event_get_count, - .ns_per_count =3D zero_event_ns_per, - }, - { .number =3D 0x03c, /* STALL */ - .supported =3D pmu_8_4_events_supported, - .get_count =3D zero_event_get_count, - .ns_per_count =3D zero_event_ns_per, - }, -}; - -/* - * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range = of - * events (i.e. the statistical profiling extension), this implementation - * should first be updated to something sparse instead of the current - * supported_event_map[] array. - */ -#define MAX_EVENT_ID 0x3c -#define UNSUPPORTED_EVENT UINT16_MAX -static uint16_t supported_event_map[MAX_EVENT_ID + 1]; - -/* - * Called upon CPU initialization to initialize PMCEID[01]_EL0 and build a= map - * of ARM event numbers to indices in our pm_events array. - * - * Note: Events in the 0x40XX range are not currently supported. - */ -void pmu_init(ARMCPU *cpu) -{ - unsigned int i; - - /* - * Empty supported_event_map and cpu->pmceid[01] before adding support= ed - * events to them - */ - for (i =3D 0; i < ARRAY_SIZE(supported_event_map); i++) { - supported_event_map[i] =3D UNSUPPORTED_EVENT; - } - cpu->pmceid0 =3D 0; - cpu->pmceid1 =3D 0; - - for (i =3D 0; i < ARRAY_SIZE(pm_events); i++) { - const pm_event *cnt =3D &pm_events[i]; - assert(cnt->number <=3D MAX_EVENT_ID); - /* We do not currently support events in the 0x40xx range */ - assert(cnt->number <=3D 0x3f); - - if (cnt->supported(&cpu->env)) { - supported_event_map[cnt->number] =3D i; - uint64_t event_mask =3D 1ULL << (cnt->number & 0x1f); - if (cnt->number & 0x20) { - cpu->pmceid1 |=3D event_mask; - } else { - cpu->pmceid0 |=3D event_mask; - } - } - } -} - -/* - * Check at runtime whether a PMU event is supported for the current machi= ne - */ -static bool event_supported(uint16_t number) -{ - if (number > MAX_EVENT_ID) { - return false; - } - return supported_event_map[number] !=3D UNSUPPORTED_EVENT; -} - -static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *r= i, - bool isread) -{ - /* Performance monitor registers user accessibility is controlled - * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable - * trapping to EL2 or EL3 for other accesses. - */ - int el =3D arm_current_el(env); - uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); - - if (el =3D=3D 0 && !(env->cp15.c9_pmuserenr & 1)) { - return CP_ACCESS_TRAP; - } - if (el < 2 && (mdcr_el2 & MDCR_TPM)) { - return CP_ACCESS_TRAP_EL2; - } - if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) { - return CP_ACCESS_TRAP_EL3; - } - - return CP_ACCESS_OK; -} - -static CPAccessResult pmreg_access_xevcntr(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - /* ER: event counter read trap control */ - if (arm_feature(env, ARM_FEATURE_V8) - && arm_current_el(env) =3D=3D 0 - && (env->cp15.c9_pmuserenr & (1 << 3)) !=3D 0 - && isread) { - return CP_ACCESS_OK; - } - - return pmreg_access(env, ri, isread); -} - -static CPAccessResult pmreg_access_swinc(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - /* SW: software increment write trap control */ - if (arm_feature(env, ARM_FEATURE_V8) - && arm_current_el(env) =3D=3D 0 - && (env->cp15.c9_pmuserenr & (1 << 1)) !=3D 0 - && !isread) { - return CP_ACCESS_OK; - } - - return pmreg_access(env, ri, isread); -} - -static CPAccessResult pmreg_access_selr(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - /* ER: event counter read trap control */ - if (arm_feature(env, ARM_FEATURE_V8) - && arm_current_el(env) =3D=3D 0 - && (env->cp15.c9_pmuserenr & (1 << 3)) !=3D 0) { - return CP_ACCESS_OK; - } - - return pmreg_access(env, ri, isread); -} - -static CPAccessResult pmreg_access_ccntr(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - /* CR: cycle counter read trap control */ - if (arm_feature(env, ARM_FEATURE_V8) - && arm_current_el(env) =3D=3D 0 - && (env->cp15.c9_pmuserenr & (1 << 2)) !=3D 0 - && isread) { - return CP_ACCESS_OK; - } - - return pmreg_access(env, ri, isread); -} - -/* Returns true if the counter (pass 31 for PMCCNTR) should count events u= sing - * the current EL, security state, and register configuration. - */ -static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) -{ - uint64_t filter; - bool e, p, u, nsk, nsu, nsh, m; - bool enabled, prohibited, filtered; - bool secure =3D arm_is_secure(env); - int el =3D arm_current_el(env); - uint64_t mdcr_el2 =3D arm_mdcr_el2_eff(env); - uint8_t hpmn =3D mdcr_el2 & MDCR_HPMN; - - if (!arm_feature(env, ARM_FEATURE_PMU)) { - return false; - } - - if (!arm_feature(env, ARM_FEATURE_EL2) || - (counter < hpmn || counter =3D=3D 31)) { - e =3D env->cp15.c9_pmcr & PMCRE; - } else { - e =3D mdcr_el2 & MDCR_HPME; - } - enabled =3D e && (env->cp15.c9_pmcnten & (1 << counter)); - - if (!secure) { - if (el =3D=3D 2 && (counter < hpmn || counter =3D=3D 31)) { - prohibited =3D mdcr_el2 & MDCR_HPMD; - } else { - prohibited =3D false; - } - } else { - prohibited =3D arm_feature(env, ARM_FEATURE_EL3) && - !(env->cp15.mdcr_el3 & MDCR_SPME); - } - - if (prohibited && counter =3D=3D 31) { - prohibited =3D env->cp15.c9_pmcr & PMCRDP; - } - - if (counter =3D=3D 31) { - filter =3D env->cp15.pmccfiltr_el0; - } else { - filter =3D env->cp15.c14_pmevtyper[counter]; - } - - p =3D filter & PMXEVTYPER_P; - u =3D filter & PMXEVTYPER_U; - nsk =3D arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK); - nsu =3D arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU); - nsh =3D arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH); - m =3D arm_el_is_aa64(env, 1) && - arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M); - - if (el =3D=3D 0) { - filtered =3D secure ? u : u !=3D nsu; - } else if (el =3D=3D 1) { - filtered =3D secure ? p : p !=3D nsk; - } else if (el =3D=3D 2) { - filtered =3D !nsh; - } else { /* EL3 */ - filtered =3D m !=3D p; - } - - if (counter !=3D 31) { - /* - * If not checking PMCCNTR, ensure the counter is setup to an even= t we - * support - */ - uint16_t event =3D filter & PMXEVTYPER_EVTCOUNT; - if (!event_supported(event)) { - return false; - } - } - - return enabled && !prohibited && !filtered; -} - -static void pmu_update_irq(CPUARMState *env) -{ - ARMCPU *cpu =3D env_archcpu(env); - qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) && - (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); -} - -/* - * Ensure c15_ccnt is the guest-visible count so that operations such as - * enabling/disabling the counter or filtering, modifying the count itself, - * etc. can be done logically. This is essentially a no-op if the counter = is - * not enabled at the time of the call. - */ -static void pmccntr_op_start(CPUARMState *env) -{ - uint64_t cycles =3D cycles_get_count(env); - - if (pmu_counter_enabled(env, 31)) { - uint64_t eff_cycles =3D cycles; - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ - eff_cycles /=3D 64; - } - - uint64_t new_pmccntr =3D eff_cycles - env->cp15.c15_ccnt_delta; - - uint64_t overflow_mask =3D env->cp15.c9_pmcr & PMCRLC ? \ - 1ull << 63 : 1ull << 31; - if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { - env->cp15.c9_pmovsr |=3D (1 << 31); - pmu_update_irq(env); - } - - env->cp15.c15_ccnt =3D new_pmccntr; - } - env->cp15.c15_ccnt_delta =3D cycles; -} - -/* - * If PMCCNTR is enabled, recalculate the delta between the clock and the - * guest-visible count. A call to pmccntr_op_finish should follow every ca= ll to - * pmccntr_op_start. - */ -static void pmccntr_op_finish(CPUARMState *env) -{ - if (pmu_counter_enabled(env, 31)) { -#ifndef CONFIG_USER_ONLY - /* Calculate when the counter will next overflow */ - uint64_t remaining_cycles =3D -env->cp15.c15_ccnt; - if (!(env->cp15.c9_pmcr & PMCRLC)) { - remaining_cycles =3D (uint32_t)remaining_cycles; - } - int64_t overflow_in =3D cycles_ns_per(remaining_cycles); - - if (overflow_in > 0) { - int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + - overflow_in; - ARMCPU *cpu =3D env_archcpu(env); - timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); - } -#endif - - uint64_t prev_cycles =3D env->cp15.c15_ccnt_delta; - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ - prev_cycles /=3D 64; - } - env->cp15.c15_ccnt_delta =3D prev_cycles - env->cp15.c15_ccnt; - } -} - -static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) -{ - - uint16_t event =3D env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCO= UNT; - uint64_t count =3D 0; - if (event_supported(event)) { - uint16_t event_idx =3D supported_event_map[event]; - count =3D pm_events[event_idx].get_count(env); - } - - if (pmu_counter_enabled(env, counter)) { - uint32_t new_pmevcntr =3D count - env->cp15.c14_pmevcntr_delta[cou= nter]; - - if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & INT32_MIN) { - env->cp15.c9_pmovsr |=3D (1 << counter); - pmu_update_irq(env); - } - env->cp15.c14_pmevcntr[counter] =3D new_pmevcntr; - } - env->cp15.c14_pmevcntr_delta[counter] =3D count; -} - -static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) -{ - if (pmu_counter_enabled(env, counter)) { -#ifndef CONFIG_USER_ONLY - uint16_t event =3D env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_E= VTCOUNT; - uint16_t event_idx =3D supported_event_map[event]; - uint64_t delta =3D UINT32_MAX - - (uint32_t)env->cp15.c14_pmevcntr[counter] + 1; - int64_t overflow_in =3D pm_events[event_idx].ns_per_count(delta); - - if (overflow_in > 0) { - int64_t overflow_at =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + - overflow_in; - ARMCPU *cpu =3D env_archcpu(env); - timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); - } -#endif - - env->cp15.c14_pmevcntr_delta[counter] -=3D - env->cp15.c14_pmevcntr[counter]; - } -} - -void pmu_op_start(CPUARMState *env) -{ - unsigned int i; - pmccntr_op_start(env); - for (i =3D 0; i < pmu_num_counters(env); i++) { - pmevcntr_op_start(env, i); - } -} - -void pmu_op_finish(CPUARMState *env) -{ - unsigned int i; - pmccntr_op_finish(env); - for (i =3D 0; i < pmu_num_counters(env); i++) { - pmevcntr_op_finish(env, i); - } -} - -void pmu_pre_el_change(ARMCPU *cpu, void *ignored) -{ - pmu_op_start(&cpu->env); -} - -void pmu_post_el_change(ARMCPU *cpu, void *ignored) -{ - pmu_op_finish(&cpu->env); -} - -void arm_pmu_timer_cb(void *opaque) -{ - ARMCPU *cpu =3D opaque; - - /* - * Update all the counter values based on the current underlying count= s, - * triggering interrupts to be raised, if necessary. pmu_op_finish() a= lso - * has the effect of setting the cpu->pmu_timer to the next earliest t= ime a - * counter may expire. - */ - pmu_op_start(&cpu->env); - pmu_op_finish(&cpu->env); -} - -static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - pmu_op_start(env); - - if (value & PMCRC) { - /* The counter has been reset */ - env->cp15.c15_ccnt =3D 0; - } - - if (value & PMCRP) { - unsigned int i; - for (i =3D 0; i < pmu_num_counters(env); i++) { - env->cp15.c14_pmevcntr[i] =3D 0; - } - } - - env->cp15.c9_pmcr &=3D ~PMCR_WRITEABLE_MASK; - env->cp15.c9_pmcr |=3D (value & PMCR_WRITEABLE_MASK); - - pmu_op_finish(env); -} - -static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - unsigned int i; - for (i =3D 0; i < pmu_num_counters(env); i++) { - /* Increment a counter's count iff: */ - if ((value & (1 << i)) && /* counter's bit is set */ - /* counter is enabled and not filtered */ - pmu_counter_enabled(env, i) && - /* counter is SW_INCR */ - (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) =3D=3D = 0x0) { - pmevcntr_op_start(env, i); - - /* - * Detect if this write causes an overflow since we can't pred= ict - * PMSWINC overflows like we can for other events - */ - uint32_t new_pmswinc =3D env->cp15.c14_pmevcntr[i] + 1; - - if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { - env->cp15.c9_pmovsr |=3D (1 << i); - pmu_update_irq(env); - } - - env->cp15.c14_pmevcntr[i] =3D new_pmswinc; - - pmevcntr_op_finish(env, i); - } - } -} - -static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - uint64_t ret; - pmccntr_op_start(env); - ret =3D env->cp15.c15_ccnt; - pmccntr_op_finish(env); - return ret; -} - -static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* The value of PMSELR.SEL affects the behavior of PMXEVTYPER and - * PMXEVCNTR. We allow [0..31] to be written to PMSELR here; in the - * meanwhile, we check PMSELR.SEL when PMXEVTYPER and PMXEVCNTR are - * accessed. - */ - env->cp15.c9_pmselr =3D value & 0x1f; -} - -static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - pmccntr_op_start(env); - env->cp15.c15_ccnt =3D value; - pmccntr_op_finish(env); -} - -static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - uint64_t cur_val =3D pmccntr_read(env, NULL); - - pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); -} - -static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - pmccntr_op_start(env); - env->cp15.pmccfiltr_el0 =3D value & PMCCFILTR_EL0; - pmccntr_op_finish(env); -} - -static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - pmccntr_op_start(env); - /* M is not accessible from AArch32 */ - env->cp15.pmccfiltr_el0 =3D (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) | - (value & PMCCFILTR); - pmccntr_op_finish(env); -} - -static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *r= i) -{ - /* M is not visible in AArch32 */ - return env->cp15.pmccfiltr_el0 & PMCCFILTR; -} - -static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - value &=3D pmu_counter_mask(env); - env->cp15.c9_pmcnten |=3D value; -} - -static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - value &=3D pmu_counter_mask(env); - env->cp15.c9_pmcnten &=3D ~value; -} - -static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - value &=3D pmu_counter_mask(env); - env->cp15.c9_pmovsr &=3D ~value; - pmu_update_irq(env); -} - -static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - value &=3D pmu_counter_mask(env); - env->cp15.c9_pmovsr |=3D value; - pmu_update_irq(env); -} - -static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value, const uint8_t counter) -{ - if (counter =3D=3D 31) { - pmccfiltr_write(env, ri, value); - } else if (counter < pmu_num_counters(env)) { - pmevcntr_op_start(env, counter); - - /* - * If this counter's event type is changing, store the current - * underlying count for the new type in c14_pmevcntr_delta[counter= ] so - * pmevcntr_op_finish has the correct baseline when it converts ba= ck to - * a delta. - */ - uint16_t old_event =3D env->cp15.c14_pmevtyper[counter] & - PMXEVTYPER_EVTCOUNT; - uint16_t new_event =3D value & PMXEVTYPER_EVTCOUNT; - if (old_event !=3D new_event) { - uint64_t count =3D 0; - if (event_supported(new_event)) { - uint16_t event_idx =3D supported_event_map[new_event]; - count =3D pm_events[event_idx].get_count(env); - } - env->cp15.c14_pmevcntr_delta[counter] =3D count; - } - - env->cp15.c14_pmevtyper[counter] =3D value & PMXEVTYPER_MASK; - pmevcntr_op_finish(env, counter); - } - /* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when - * PMSELR value is equal to or greater than the number of implemented - * counters, but not equal to 0x1f. We opt to behave as a RAZ/WI. - */ -} - -static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri, - const uint8_t counter) -{ - if (counter =3D=3D 31) { - return env->cp15.pmccfiltr_el0; - } else if (counter < pmu_num_counters(env)) { - return env->cp15.c14_pmevtyper[counter]; - } else { - /* - * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER - * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write(). - */ - return 0; - } -} - -static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); - pmevtyper_write(env, ri, value, counter); -} - -static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); - env->cp15.c14_pmevtyper[counter] =3D value; - - /* - * pmevtyper_rawwrite is called between a pair of pmu_op_start and - * pmu_op_finish calls when loading saved state for a migration. Becau= se - * we're potentially updating the type of event here, the value writte= n to - * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a - * different counter type. Therefore, we need to set this value to the - * current count for the counter type we're writing so that pmu_op_fin= ish - * has the correct count for its calculation. - */ - uint16_t event =3D value & PMXEVTYPER_EVTCOUNT; - if (event_supported(event)) { - uint16_t event_idx =3D supported_event_map[event]; - env->cp15.c14_pmevcntr_delta[counter] =3D - pm_events[event_idx].get_count(env); - } -} - -static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri) -{ - uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); - return pmevtyper_read(env, ri, counter); -} - -static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31); -} - -static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31); -} - -static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value, uint8_t counter) -{ - if (counter < pmu_num_counters(env)) { - pmevcntr_op_start(env, counter); - env->cp15.c14_pmevcntr[counter] =3D value; - pmevcntr_op_finish(env, counter); - } - /* - * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR - * are CONSTRAINED UNPREDICTABLE. - */ -} - -static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, - uint8_t counter) -{ - if (counter < pmu_num_counters(env)) { - uint64_t ret; - pmevcntr_op_start(env, counter); - ret =3D env->cp15.c14_pmevcntr[counter]; - pmevcntr_op_finish(env, counter); - return ret; - } else { - /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR - * are CONSTRAINED UNPREDICTABLE. */ - return 0; - } -} - -static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); - pmevcntr_write(env, ri, value, counter); -} - -static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) -{ - uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); - return pmevcntr_read(env, ri, counter); -} - -static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); - assert(counter < pmu_num_counters(env)); - env->cp15.c14_pmevcntr[counter] =3D value; - pmevcntr_write(env, ri, value, counter); -} - -static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri) -{ - uint8_t counter =3D ((ri->crm & 3) << 3) | (ri->opc2 & 7); - assert(counter < pmu_num_counters(env)); - return env->cp15.c14_pmevcntr[counter]; -} - -static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31); -} - -static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31); -} - -static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - if (arm_feature(env, ARM_FEATURE_V8)) { - env->cp15.c9_pmuserenr =3D value & 0xf; - } else { - env->cp15.c9_pmuserenr =3D value & 1; - } -} - -static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* We have no event counters so only the C bit can be changed */ - value &=3D pmu_counter_mask(env); - env->cp15.c9_pminten |=3D value; - pmu_update_irq(env); -} - -static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - value &=3D pmu_counter_mask(env); - env->cp15.c9_pminten &=3D ~value; - pmu_update_irq(env); -} - -static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Note that even though the AArch64 view of this register has bits - * [10:0] all RES0 we can only mask the bottom 5, to comply with the - * architectural requirements for bits which are RES0 only in some - * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 - * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP= .) - */ - raw_write(env, ri, value & ~0x1FULL); -} - -static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) -{ - /* Begin with base v8.0 state. */ - uint32_t valid_mask =3D 0x3fff; - ARMCPU *cpu =3D env_archcpu(env); - - if (ri->state =3D=3D ARM_CP_STATE_AA64) { - if (arm_feature(env, ARM_FEATURE_AARCH64) && - !cpu_isar_feature(aa64_aa32_el1, cpu)) { - value |=3D SCR_FW | SCR_AW; /* these two bits are RES1. = */ - } - valid_mask &=3D ~SCR_NET; - - if (cpu_isar_feature(aa64_lor, cpu)) { - valid_mask |=3D SCR_TLOR; - } - if (cpu_isar_feature(aa64_pauth, cpu)) { - valid_mask |=3D SCR_API | SCR_APK; - } - if (cpu_isar_feature(aa64_sel2, cpu)) { - valid_mask |=3D SCR_EEL2; - } - if (cpu_isar_feature(aa64_mte, cpu)) { - valid_mask |=3D SCR_ATA; - } - } else { - valid_mask &=3D ~(SCR_RW | SCR_ST); - } - - if (!arm_feature(env, ARM_FEATURE_EL2)) { - valid_mask &=3D ~SCR_HCE; - - /* On ARMv7, SMD (or SCD as it is called in v7) is only - * supported if EL2 exists. The bit is UNK/SBZP when - * EL2 is unavailable. In QEMU ARMv7, we force it to always zero - * when EL2 is unavailable. - * On ARMv8, this bit is always available. - */ - if (arm_feature(env, ARM_FEATURE_V7) && - !arm_feature(env, ARM_FEATURE_V8)) { - valid_mask &=3D ~SCR_SMD; - } - } - - /* Clear all-context RES0 bits. */ - value &=3D valid_mask; - raw_write(env, ri, value); -} - -static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - /* - * scr_write will set the RES1 bits on an AArch64-only CPU. - * The reset value will be 0x30 on an AArch64-only CPU and 0 otherwise. - */ - scr_write(env, ri, 0); -} - -static CPAccessResult access_aa64_tid2(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TID2))= { - return CP_ACCESS_TRAP_EL2; - } - - return CP_ACCESS_OK; -} - -static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - ARMCPU *cpu =3D env_archcpu(env); - - /* Acquire the CSSELR index from the bank corresponding to the CCSIDR - * bank - */ - uint32_t index =3D A32_BANKED_REG_GET(env, csselr, - ri->secure & ARM_CP_SECSTATE_S); - - return cpu->ccsidr[index]; -} - -static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - raw_write(env, ri, value & 0xf); -} - -static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - CPUState *cs =3D env_cpu(env); - bool el1 =3D arm_current_el(env) =3D=3D 1; - uint64_t hcr_el2 =3D el1 ? arm_hcr_el2_eff(env) : 0; - uint64_t ret =3D 0; - - if (hcr_el2 & HCR_IMO) { - if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { - ret |=3D CPSR_I; - } - } else { - if (cs->interrupt_request & CPU_INTERRUPT_HARD) { - ret |=3D CPSR_I; - } - } - - if (hcr_el2 & HCR_FMO) { - if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { - ret |=3D CPSR_F; - } - } else { - if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { - ret |=3D CPSR_F; - } - } - - /* External aborts are not possible in QEMU so A bit is always clear */ - return ret; -} - -static CPAccessResult access_aa64_tid1(CPUARMState *env, const ARMCPRegInf= o *ri, - bool isread) -{ - if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TID1))= { - return CP_ACCESS_TRAP_EL2; - } - - return CP_ACCESS_OK; -} - -static CPAccessResult access_aa32_tid1(CPUARMState *env, const ARMCPRegInf= o *ri, - bool isread) -{ - if (arm_feature(env, ARM_FEATURE_V8)) { - return access_aa64_tid1(env, ri, isread); - } - - return CP_ACCESS_OK; -} - -static const ARMCPRegInfo v7_cp_reginfo[] =3D { - /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */ - { .name =3D "NOP", .cp =3D 15, .crn =3D 7, .crm =3D 0, .opc1 =3D 0, .o= pc2 =3D 4, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, - /* Performance monitors are implementation defined in v7, - * but with an ARM recommended set of registers, which we - * follow. - * - * Performance registers fall into three categories: - * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR) - * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR) - * (c) UNDEF in PL0 if PMUSERENR.EN=3D=3D0, otherwise accessible (all= others) - * For the cases controlled by PMUSERENR we must set .access to PL0_RW - * or PL0_RO as appropriate and then check PMUSERENR in the helper fn. - */ - { .name =3D "PMCNTENSET", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 1, - .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), - .writefn =3D pmcntenset_write, - .accessfn =3D pmreg_access, - .raw_writefn =3D raw_write }, - { .name =3D "PMCNTENSET_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 1, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue= =3D 0, - .writefn =3D pmcntenset_write, .raw_writefn =3D raw_write }, - { .name =3D "PMCNTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 2, - .access =3D PL0_RW, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcnten), - .accessfn =3D pmreg_access, - .writefn =3D pmcntenclr_write, - .type =3D ARM_CP_ALIAS }, - { .name =3D "PMCNTENCLR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 2, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcnten), - .writefn =3D pmcntenclr_write }, - { .name =3D "PMOVSR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 3, - .access =3D PL0_RW, .type =3D ARM_CP_IO, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), - .accessfn =3D pmreg_access, - .writefn =3D pmovsr_write, - .raw_writefn =3D raw_write }, - { .name =3D "PMOVSCLR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 3, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .type =3D ARM_CP_ALIAS | ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), - .writefn =3D pmovsr_write, - .raw_writefn =3D raw_write }, - { .name =3D "PMSWINC", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D = 0, .opc2 =3D 4, - .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, - .writefn =3D pmswinc_write }, - { .name =3D "PMSWINC_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 4, - .access =3D PL0_W, .accessfn =3D pmreg_access_swinc, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, - .writefn =3D pmswinc_write }, - { .name =3D "PMSELR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 5, - .access =3D PL0_RW, .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmselr), - .accessfn =3D pmreg_access_selr, .writefn =3D pmselr_write, - .raw_writefn =3D raw_write}, - { .name =3D "PMSELR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 5, - .access =3D PL0_RW, .accessfn =3D pmreg_access_selr, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmselr), - .writefn =3D pmselr_write, .raw_writefn =3D raw_write, }, - { .name =3D "PMCCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 =3D = 0, .opc2 =3D 0, - .access =3D PL0_RW, .resetvalue =3D 0, .type =3D ARM_CP_ALIAS | ARM_= CP_IO, - .readfn =3D pmccntr_read, .writefn =3D pmccntr_write32, - .accessfn =3D pmreg_access_ccntr }, - { .name =3D "PMCCNTR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 0, - .access =3D PL0_RW, .accessfn =3D pmreg_access_ccntr, - .type =3D ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_ccnt), - .readfn =3D pmccntr_read, .writefn =3D pmccntr_write, - .raw_readfn =3D raw_read, .raw_writefn =3D raw_write, }, - { .name =3D "PMCCFILTR", .cp =3D 15, .opc1 =3D 0, .crn =3D 14, .crm = =3D 15, .opc2 =3D 7, - .writefn =3D pmccfiltr_write_a32, .readfn =3D pmccfiltr_read_a32, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .type =3D ARM_CP_ALIAS | ARM_CP_IO, - .resetvalue =3D 0, }, - { .name =3D "PMCCFILTR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 15, .opc2 =3D 7, - .writefn =3D pmccfiltr_write, .raw_writefn =3D raw_write, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .type =3D ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.pmccfiltr_el0), - .resetvalue =3D 0, }, - { .name =3D "PMXEVTYPER", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 1, - .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, - .accessfn =3D pmreg_access, - .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, - { .name =3D "PMXEVTYPER_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 1, - .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, - .accessfn =3D pmreg_access, - .writefn =3D pmxevtyper_write, .readfn =3D pmxevtyper_read }, - { .name =3D "PMXEVCNTR", .cp =3D 15, .crn =3D 9, .crm =3D 13, .opc1 = =3D 0, .opc2 =3D 2, - .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, - .accessfn =3D pmreg_access_xevcntr, - .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, - { .name =3D "PMXEVCNTR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 13, .opc2 =3D 2, - .access =3D PL0_RW, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, - .accessfn =3D pmreg_access_xevcntr, - .writefn =3D pmxevcntr_write, .readfn =3D pmxevcntr_read }, - { .name =3D "PMUSERENR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 0, - .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmuserenr), - .resetvalue =3D 0, - .writefn =3D pmuserenr_write, .raw_writefn =3D raw_write }, - { .name =3D "PMUSERENR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 14, .opc2 =3D 0, - .access =3D PL0_R | PL1_RW, .accessfn =3D access_tpm, .type =3D ARM_= CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmuserenr), - .resetvalue =3D 0, - .writefn =3D pmuserenr_write, .raw_writefn =3D raw_write }, - { .name =3D "PMINTENSET", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_tpm, - .type =3D ARM_CP_ALIAS | ARM_CP_IO, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pminten), - .resetvalue =3D 0, - .writefn =3D pmintenset_write, .raw_writefn =3D raw_write }, - { .name =3D "PMINTENSET_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_tpm, - .type =3D ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), - .writefn =3D pmintenset_write, .raw_writefn =3D raw_write, - .resetvalue =3D 0x0 }, - { .name =3D "PMINTENCLR", .cp =3D 15, .crn =3D 9, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tpm, - .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), - .writefn =3D pmintenclr_write, }, - { .name =3D "PMINTENCLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tpm, - .type =3D ARM_CP_ALIAS | ARM_CP_IO | ARM_CP_NO_RAW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pminten), - .writefn =3D pmintenclr_write }, - { .name =3D "CCSIDR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 0, - .access =3D PL1_R, - .accessfn =3D access_aa64_tid2, - .readfn =3D ccsidr_read, .type =3D ARM_CP_NO_RAW }, - { .name =3D "CSSELR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, - .accessfn =3D access_aa64_tid2, - .writefn =3D csselr_write, .resetvalue =3D 0, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.csselr_s), - offsetof(CPUARMState, cp15.csselr_ns) } }, - /* Auxiliary ID register: this actually has an IMPDEF value but for now - * just RAZ for all cores: - */ - { .name =3D "AIDR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 7, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid1, - .resetvalue =3D 0 }, - /* Auxiliary fault status registers: these also are IMPDEF, and we - * choose to RAZ/WI for all cores. - */ - { .name =3D "AFSR0_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "AFSR1_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* MAIR can just read-as-written because we don't implement caches - * and so don't need to care about memory attributes. - */ - { .name =3D "MAIR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .fieldoffset =3D offsetof(CPUARMState, cp15.mair_el[1]), - .resetvalue =3D 0 }, - { .name =3D "MAIR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, - .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[3]), - .resetvalue =3D 0 }, - /* For non-long-descriptor page tables these are PRRR and NMRR; - * regardless they still act as reads-as-written for QEMU. - */ - /* MAIR0/1 are defined separately from their 64-bit counterpart which - * allows them to assign the correct fieldoffset based on the endiann= ess - * handled in the field definitions. - */ - { .name =3D "MAIR0", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.mair0_s), - offsetof(CPUARMState, cp15.mair0_ns) }, - .resetfn =3D arm_cp_reset_ignore }, - { .name =3D "MAIR1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.mair1_s), - offsetof(CPUARMState, cp15.mair1_ns) }, - .resetfn =3D arm_cp_reset_ignore }, - { .name =3D "ISR_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_R, .readfn =3D isr_read }, - /* 32 bit ITLB invalidates */ - { .name =3D "ITLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 5, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbiall_write }, - { .name =3D "ITLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 5, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimva_write }, - { .name =3D "ITLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 5, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbiasid_write }, - /* 32 bit DTLB invalidates */ - { .name =3D "DTLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 6, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbiall_write }, - { .name =3D "DTLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 6, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimva_write }, - { .name =3D "DTLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 6, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbiasid_write }, - /* 32 bit TLB invalidates */ - { .name =3D "TLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7= , .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbiall_write }, - { .name =3D "TLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7= , .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimva_write }, - { .name =3D "TLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbiasid_write }, - { .name =3D "TLBIMVAA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 3, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimvaa_write }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo v7mp_cp_reginfo[] =3D { - /* 32 bit TLB invalidates, Inner Shareable */ - { .name =3D "TLBIALLIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 3, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbiall_is_write }, - { .name =3D "TLBIMVAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 3, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimva_is_write }, - { .name =3D "TLBIASIDIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbiasid_is_write }, - { .name =3D "TLBIMVAAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 3, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimvaa_is_write }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { - /* PMOVSSET is not implemented in v7 before v7ve */ - { .name =3D "PMOVSSET", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D = 14, .opc2 =3D 3, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .type =3D ARM_CP_ALIAS | ARM_CP_IO, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmovsr), - .writefn =3D pmovsset_write, - .raw_writefn =3D raw_write }, - { .name =3D "PMOVSSET_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 14, .opc2 =3D 3, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .type =3D ARM_CP_ALIAS | ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), - .writefn =3D pmovsset_write, - .raw_writefn =3D raw_write }, - REGINFO_SENTINEL -}; - -static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - value &=3D 1; - env->teecr =3D value; -} - -static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *= ri, - bool isread) -{ - if (arm_current_el(env) =3D=3D 0 && (env->teecr & 1)) { - return CP_ACCESS_TRAP; - } - return CP_ACCESS_OK; -} - -static const ARMCPRegInfo t2ee_cp_reginfo[] =3D { - { .name =3D "TEECR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D 6, = .opc2 =3D 0, - .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, teecr), - .resetvalue =3D 0, - .writefn =3D teecr_write }, - { .name =3D "TEEHBR", .cp =3D 14, .crn =3D 1, .crm =3D 0, .opc1 =3D 6,= .opc2 =3D 0, - .access =3D PL0_RW, .fieldoffset =3D offsetof(CPUARMState, teehbr), - .accessfn =3D teehbr_access, .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo v6k_cp_reginfo[] =3D { - { .name =3D "TPIDR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 2, .crn =3D 13, .crm =3D 0, - .access =3D PL0_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalu= e =3D 0 }, - { .name =3D "TPIDRURW", .cp =3D 15, .crn =3D 13, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 2, - .access =3D PL0_RW, - .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidrurw_s), - offsetoflow32(CPUARMState, cp15.tpidrurw_ns) = }, - .resetfn =3D arm_cp_reset_ignore }, - { .name =3D "TPIDRRO_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 3, .crn =3D 13, .crm =3D 0, - .access =3D PL0_R|PL1_W, - .fieldoffset =3D offsetof(CPUARMState, cp15.tpidrro_el[0]), - .resetvalue =3D 0}, - { .name =3D "TPIDRURO", .cp =3D 15, .crn =3D 13, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 3, - .access =3D PL0_R|PL1_W, - .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidruro_s), - offsetoflow32(CPUARMState, cp15.tpidruro_ns) = }, - .resetfn =3D arm_cp_reset_ignore }, - { .name =3D "TPIDR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 4, .crn =3D 13, .crm =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalu= e =3D 0 }, - { .name =3D "TPIDRPRW", .opc1 =3D 0, .cp =3D 15, .crn =3D 13, .crm =3D= 0, .opc2 =3D 4, - .access =3D PL1_RW, - .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidrprw_s), - offsetoflow32(CPUARMState, cp15.tpidrprw_ns) = }, - .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -#ifndef CONFIG_USER_ONLY - -static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInf= o *ri, - bool isread) -{ - /* - * CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero. - * Writable only at the highest implemented exception level. - */ - int el =3D arm_current_el(env); - uint64_t hcr; - uint32_t cntkctl; - - switch (el) { - case 0: - hcr =3D arm_hcr_el2_eff(env); - if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { - cntkctl =3D env->cp15.cnthctl_el2; - } else { - cntkctl =3D env->cp15.c14_cntkctl; - } - if (!extract32(cntkctl, 0, 2)) { - return CP_ACCESS_TRAP; - } - break; - case 1: - if (!isread && ri->state =3D=3D ARM_CP_STATE_AA32 && - arm_is_secure_below_el3(env)) { - /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) = */ - return CP_ACCESS_TRAP_UNCATEGORIZED; - } - break; - case 2: - case 3: - break; - } - - if (!isread && el < arm_highest_el(env)) { - return CP_ACCESS_TRAP_UNCATEGORIZED; - } - - return CP_ACCESS_OK; -} - -static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx, - bool isread) -{ - unsigned int cur_el =3D arm_current_el(env); - bool has_el2 =3D arm_is_el2_enabled(env); - uint64_t hcr =3D arm_hcr_el2_eff(env); - - switch (cur_el) { - case 0: - /* If HCR_EL2. =3D=3D '11': check CNTHCTL_EL2.EL0[PV]CTEN= . */ - if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { - return (extract32(env->cp15.cnthctl_el2, timeridx, 1) - ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); - } - - /* CNT[PV]CT: not visible from PL0 if EL0[PV]CTEN is zero */ - if (!extract32(env->cp15.c14_cntkctl, timeridx, 1)) { - return CP_ACCESS_TRAP; - } - - /* If HCR_EL2. =3D=3D '10': check CNTHCTL_EL2.EL1PCTEN. */ - if (hcr & HCR_E2H) { - if (timeridx =3D=3D GTIMER_PHYS && - !extract32(env->cp15.cnthctl_el2, 10, 1)) { - return CP_ACCESS_TRAP_EL2; - } - } else { - /* If HCR_EL2. =3D=3D 0: check CNTHCTL_EL2.EL1PCEN. */ - if (has_el2 && timeridx =3D=3D GTIMER_PHYS && - !extract32(env->cp15.cnthctl_el2, 1, 1)) { - return CP_ACCESS_TRAP_EL2; - } - } - break; - - case 1: - /* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H= . */ - if (has_el2 && timeridx =3D=3D GTIMER_PHYS && - (hcr & HCR_E2H - ? !extract32(env->cp15.cnthctl_el2, 10, 1) - : !extract32(env->cp15.cnthctl_el2, 0, 1))) { - return CP_ACCESS_TRAP_EL2; - } - break; - } - return CP_ACCESS_OK; -} - -static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx, - bool isread) -{ - unsigned int cur_el =3D arm_current_el(env); - bool has_el2 =3D arm_is_el2_enabled(env); - uint64_t hcr =3D arm_hcr_el2_eff(env); - - switch (cur_el) { - case 0: - if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { - /* If HCR_EL2. =3D=3D '11': check CNTHCTL_EL2.EL0[PV]= TEN. */ - return (extract32(env->cp15.cnthctl_el2, 9 - timeridx, 1) - ? CP_ACCESS_OK : CP_ACCESS_TRAP_EL2); - } - - /* - * CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from - * EL0 if EL0[PV]TEN is zero. - */ - if (!extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) { - return CP_ACCESS_TRAP; - } - /* fall through */ - - case 1: - if (has_el2 && timeridx =3D=3D GTIMER_PHYS) { - if (hcr & HCR_E2H) { - /* If HCR_EL2. =3D=3D '10': check CNTHCTL_EL2.EL1= PTEN. */ - if (!extract32(env->cp15.cnthctl_el2, 11, 1)) { - return CP_ACCESS_TRAP_EL2; - } - } else { - /* If HCR_EL2. =3D=3D 0: check CNTHCTL_EL2.EL1PCEN. */ - if (!extract32(env->cp15.cnthctl_el2, 1, 1)) { - return CP_ACCESS_TRAP_EL2; - } - } - } - break; - } - return CP_ACCESS_OK; -} - -static CPAccessResult gt_pct_access(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - return gt_counter_access(env, GTIMER_PHYS, isread); -} - -static CPAccessResult gt_vct_access(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - return gt_counter_access(env, GTIMER_VIRT, isread); -} - -static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInf= o *ri, - bool isread) -{ - return gt_timer_access(env, GTIMER_PHYS, isread); -} - -static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInf= o *ri, - bool isread) -{ - return gt_timer_access(env, GTIMER_VIRT, isread); -} - -static CPAccessResult gt_stimer_access(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - /* - * The AArch64 register view of the secure physical timer is - * always accessible from EL3, and configurably accessible from - * Secure EL1. - */ - switch (arm_current_el(env)) { - case 1: - if (!arm_is_secure(env)) { - return CP_ACCESS_TRAP; - } - if (!(env->cp15.scr_el3 & SCR_ST)) { - return CP_ACCESS_TRAP_EL3; - } - return CP_ACCESS_OK; - case 0: - case 2: - return CP_ACCESS_TRAP; - case 3: - return CP_ACCESS_OK; - default: - g_assert_not_reached(); - } -} - -static uint64_t gt_get_countervalue(CPUARMState *env) -{ - ARMCPU *cpu =3D env_archcpu(env); - - return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu= ); -} - -static void gt_recalc_timer(ARMCPU *cpu, int timeridx) -{ - ARMGenericTimer *gt =3D &cpu->env.cp15.c14_timer[timeridx]; - - if (gt->ctl & 1) { - /* - * Timer enabled: calculate and set current ISTATUS, irq, and - * reset timer to when ISTATUS next has to change - */ - uint64_t offset =3D timeridx =3D=3D GTIMER_VIRT ? - cpu->env.cp15.cntvoff_el2 : 0; - uint64_t count =3D gt_get_countervalue(&cpu->env); - /* Note that this must be unsigned 64 bit arithmetic: */ - int istatus =3D count - offset >=3D gt->cval; - uint64_t nexttick; - int irqstate; - - gt->ctl =3D deposit32(gt->ctl, 2, 1, istatus); - - irqstate =3D (istatus && !(gt->ctl & 2)); - qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); - - if (istatus) { - /* Next transition is when count rolls back over to zero */ - nexttick =3D UINT64_MAX; - } else { - /* Next transition is when we hit cval */ - nexttick =3D gt->cval + offset; - } - /* - * Note that the desired next expiry time might be beyond the - * signed-64-bit range of a QEMUTimer -- in this case we just - * set the timer for as far in the future as possible. When the - * timer expires we will reset the timer for any remaining period. - */ - if (nexttick > INT64_MAX / gt_cntfrq_period_ns(cpu)) { - timer_mod_ns(cpu->gt_timer[timeridx], INT64_MAX); - } else { - timer_mod(cpu->gt_timer[timeridx], nexttick); - } - trace_arm_gt_recalc(timeridx, irqstate, nexttick); - } else { - /* Timer disabled: ISTATUS and timer output always clear */ - gt->ctl &=3D ~4; - qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0); - timer_del(cpu->gt_timer[timeridx]); - trace_arm_gt_recalc_disabled(timeridx); - } -} - -static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri, - int timeridx) -{ - ARMCPU *cpu =3D env_archcpu(env); - - timer_del(cpu->gt_timer[timeridx]); -} - -static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return gt_get_countervalue(env); -} - -static uint64_t gt_virt_cnt_offset(CPUARMState *env) -{ - uint64_t hcr; - - switch (arm_current_el(env)) { - case 2: - hcr =3D arm_hcr_el2_eff(env); - if (hcr & HCR_E2H) { - return 0; - } - break; - case 0: - hcr =3D arm_hcr_el2_eff(env); - if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { - return 0; - } - break; - } - - return env->cp15.cntvoff_el2; -} - -static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return gt_get_countervalue(env) - gt_virt_cnt_offset(env); -} - -static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, - int timeridx, - uint64_t value) -{ - trace_arm_gt_cval_write(timeridx, value); - env->cp15.c14_timer[timeridx].cval =3D value; - gt_recalc_timer(env_archcpu(env), timeridx); -} - -static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri, - int timeridx) -{ - uint64_t offset =3D 0; - - switch (timeridx) { - case GTIMER_VIRT: - case GTIMER_HYPVIRT: - offset =3D gt_virt_cnt_offset(env); - break; - } - - return (uint32_t)(env->cp15.c14_timer[timeridx].cval - - (gt_get_countervalue(env) - offset)); -} - -static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, - int timeridx, - uint64_t value) -{ - uint64_t offset =3D 0; - - switch (timeridx) { - case GTIMER_VIRT: - case GTIMER_HYPVIRT: - offset =3D gt_virt_cnt_offset(env); - break; - } - - trace_arm_gt_tval_write(timeridx, value); - env->cp15.c14_timer[timeridx].cval =3D gt_get_countervalue(env) - offs= et + - sextract64(value, 0, 32); - gt_recalc_timer(env_archcpu(env), timeridx); -} - -static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, - int timeridx, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - uint32_t oldval =3D env->cp15.c14_timer[timeridx].ctl; - - trace_arm_gt_ctl_write(timeridx, value); - env->cp15.c14_timer[timeridx].ctl =3D deposit64(oldval, 0, 2, value); - if ((oldval ^ value) & 1) { - /* Enable toggled */ - gt_recalc_timer(cpu, timeridx); - } else if ((oldval ^ value) & 2) { - /* - * IMASK toggled: don't need to recalculate, - * just set the interrupt line based on ISTATUS - */ - int irqstate =3D (oldval & 4) && !(value & 2); - - trace_arm_gt_imask_toggle(timeridx, irqstate); - qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate); - } -} - -static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - gt_timer_reset(env, ri, GTIMER_PHYS); -} - -static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_cval_write(env, ri, GTIMER_PHYS, value); -} - -static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return gt_tval_read(env, ri, GTIMER_PHYS); -} - -static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_tval_write(env, ri, GTIMER_PHYS, value); -} - -static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_ctl_write(env, ri, GTIMER_PHYS, value); -} - -static int gt_phys_redir_timeridx(CPUARMState *env) -{ - switch (arm_mmu_idx(env)) { - case ARMMMUIdx_E20_0: - case ARMMMUIdx_E20_2: - case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: - return GTIMER_HYP; - default: - return GTIMER_PHYS; - } -} - -static int gt_virt_redir_timeridx(CPUARMState *env) -{ - switch (arm_mmu_idx(env)) { - case ARMMMUIdx_E20_0: - case ARMMMUIdx_E20_2: - case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE20_0: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: - return GTIMER_HYPVIRT; - default: - return GTIMER_VIRT; - } -} - -static uint64_t gt_phys_redir_cval_read(CPUARMState *env, - const ARMCPRegInfo *ri) -{ - int timeridx =3D gt_phys_redir_timeridx(env); - return env->cp15.c14_timer[timeridx].cval; -} - -static void gt_phys_redir_cval_write(CPUARMState *env, const ARMCPRegInfo = *ri, - uint64_t value) -{ - int timeridx =3D gt_phys_redir_timeridx(env); - gt_cval_write(env, ri, timeridx, value); -} - -static uint64_t gt_phys_redir_tval_read(CPUARMState *env, - const ARMCPRegInfo *ri) -{ - int timeridx =3D gt_phys_redir_timeridx(env); - return gt_tval_read(env, ri, timeridx); -} - -static void gt_phys_redir_tval_write(CPUARMState *env, const ARMCPRegInfo = *ri, - uint64_t value) -{ - int timeridx =3D gt_phys_redir_timeridx(env); - gt_tval_write(env, ri, timeridx, value); -} - -static uint64_t gt_phys_redir_ctl_read(CPUARMState *env, - const ARMCPRegInfo *ri) -{ - int timeridx =3D gt_phys_redir_timeridx(env); - return env->cp15.c14_timer[timeridx].ctl; -} - -static void gt_phys_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *= ri, - uint64_t value) -{ - int timeridx =3D gt_phys_redir_timeridx(env); - gt_ctl_write(env, ri, timeridx, value); -} - -static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - gt_timer_reset(env, ri, GTIMER_VIRT); -} - -static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_cval_write(env, ri, GTIMER_VIRT, value); -} - -static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return gt_tval_read(env, ri, GTIMER_VIRT); -} - -static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_tval_write(env, ri, GTIMER_VIRT, value); -} - -static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_ctl_write(env, ri, GTIMER_VIRT, value); -} - -static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - - trace_arm_gt_cntvoff_write(value); - raw_write(env, ri, value); - gt_recalc_timer(cpu, GTIMER_VIRT); -} - -static uint64_t gt_virt_redir_cval_read(CPUARMState *env, - const ARMCPRegInfo *ri) -{ - int timeridx =3D gt_virt_redir_timeridx(env); - return env->cp15.c14_timer[timeridx].cval; -} - -static void gt_virt_redir_cval_write(CPUARMState *env, const ARMCPRegInfo = *ri, - uint64_t value) -{ - int timeridx =3D gt_virt_redir_timeridx(env); - gt_cval_write(env, ri, timeridx, value); -} - -static uint64_t gt_virt_redir_tval_read(CPUARMState *env, - const ARMCPRegInfo *ri) -{ - int timeridx =3D gt_virt_redir_timeridx(env); - return gt_tval_read(env, ri, timeridx); -} - -static void gt_virt_redir_tval_write(CPUARMState *env, const ARMCPRegInfo = *ri, - uint64_t value) -{ - int timeridx =3D gt_virt_redir_timeridx(env); - gt_tval_write(env, ri, timeridx, value); -} - -static uint64_t gt_virt_redir_ctl_read(CPUARMState *env, - const ARMCPRegInfo *ri) -{ - int timeridx =3D gt_virt_redir_timeridx(env); - return env->cp15.c14_timer[timeridx].ctl; -} - -static void gt_virt_redir_ctl_write(CPUARMState *env, const ARMCPRegInfo *= ri, - uint64_t value) -{ - int timeridx =3D gt_virt_redir_timeridx(env); - gt_ctl_write(env, ri, timeridx, value); -} - -static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - gt_timer_reset(env, ri, GTIMER_HYP); -} - -static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_cval_write(env, ri, GTIMER_HYP, value); -} - -static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return gt_tval_read(env, ri, GTIMER_HYP); -} - -static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_tval_write(env, ri, GTIMER_HYP, value); -} - -static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_ctl_write(env, ri, GTIMER_HYP, value); -} - -static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - gt_timer_reset(env, ri, GTIMER_SEC); -} - -static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_cval_write(env, ri, GTIMER_SEC, value); -} - -static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return gt_tval_read(env, ri, GTIMER_SEC); -} - -static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_tval_write(env, ri, GTIMER_SEC, value); -} - -static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_ctl_write(env, ri, GTIMER_SEC, value); -} - -static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - gt_timer_reset(env, ri, GTIMER_HYPVIRT); -} - -static void gt_hv_cval_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_cval_write(env, ri, GTIMER_HYPVIRT, value); -} - -static uint64_t gt_hv_tval_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return gt_tval_read(env, ri, GTIMER_HYPVIRT); -} - -static void gt_hv_tval_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_tval_write(env, ri, GTIMER_HYPVIRT, value); -} - -static void gt_hv_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - gt_ctl_write(env, ri, GTIMER_HYPVIRT, value); -} - -void arm_gt_ptimer_cb(void *opaque) -{ - ARMCPU *cpu =3D opaque; - - gt_recalc_timer(cpu, GTIMER_PHYS); -} - -void arm_gt_vtimer_cb(void *opaque) -{ - ARMCPU *cpu =3D opaque; - - gt_recalc_timer(cpu, GTIMER_VIRT); -} - -void arm_gt_htimer_cb(void *opaque) -{ - ARMCPU *cpu =3D opaque; - - gt_recalc_timer(cpu, GTIMER_HYP); -} - -void arm_gt_stimer_cb(void *opaque) -{ - ARMCPU *cpu =3D opaque; - - gt_recalc_timer(cpu, GTIMER_SEC); -} - -void arm_gt_hvtimer_cb(void *opaque) -{ - ARMCPU *cpu =3D opaque; - - gt_recalc_timer(cpu, GTIMER_HYPVIRT); -} - -static void arm_gt_cntfrq_reset(CPUARMState *env, const ARMCPRegInfo *opaq= ue) -{ - ARMCPU *cpu =3D env_archcpu(env); - - cpu->env.cp15.c14_cntfrq =3D cpu->gt_cntfrq_hz; -} - -static const ARMCPRegInfo generic_timer_cp_reginfo[] =3D { - /* - * Note that CNTFRQ is purely reads-as-written for the benefit - * of software; writing it doesn't actually change the timer frequency. - * Our reset value matches the fixed frequency we implement the timer = at. - */ - { .name =3D "CNTFRQ", .cp =3D 15, .crn =3D 14, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, - .type =3D ARM_CP_ALIAS, - .access =3D PL1_RW | PL0_R, .accessfn =3D gt_cntfrq_access, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c14_cntfrq), - }, - { .name =3D "CNTFRQ_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW | PL0_R, .accessfn =3D gt_cntfrq_access, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_cntfrq), - .resetfn =3D arm_gt_cntfrq_reset, - }, - /* overall control: mostly access permissions */ - { .name =3D "CNTKCTL", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_cntkctl), - .resetvalue =3D 0, - }, - /* per-timer control */ - { .name =3D "CNTP_CTL", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D= 0, .opc2 =3D 1, - .secure =3D ARM_CP_SECSTATE_NS, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL0_RW, - .accessfn =3D gt_ptimer_access, - .fieldoffset =3D offsetoflow32(CPUARMState, - cp15.c14_timer[GTIMER_PHYS].ctl), - .readfn =3D gt_phys_redir_ctl_read, .raw_readfn =3D raw_read, - .writefn =3D gt_phys_redir_ctl_write, .raw_writefn =3D raw_write, - }, - { .name =3D "CNTP_CTL_S", - .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 1, - .secure =3D ARM_CP_SECSTATE_S, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL0_RW, - .accessfn =3D gt_ptimer_access, - .fieldoffset =3D offsetoflow32(CPUARMState, - cp15.c14_timer[GTIMER_SEC].ctl), - .writefn =3D gt_sec_ctl_write, .raw_writefn =3D raw_write, - }, - { .name =3D "CNTP_CTL_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, - .type =3D ARM_CP_IO, .access =3D PL0_RW, - .accessfn =3D gt_ptimer_access, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= tl), - .resetvalue =3D 0, - .readfn =3D gt_phys_redir_ctl_read, .raw_readfn =3D raw_read, - .writefn =3D gt_phys_redir_ctl_write, .raw_writefn =3D raw_write, - }, - { .name =3D "CNTV_CTL", .cp =3D 15, .crn =3D 14, .crm =3D 3, .opc1 =3D= 0, .opc2 =3D 1, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, .access =3D PL0_RW, - .accessfn =3D gt_vtimer_access, - .fieldoffset =3D offsetoflow32(CPUARMState, - cp15.c14_timer[GTIMER_VIRT].ctl), - .readfn =3D gt_virt_redir_ctl_read, .raw_readfn =3D raw_read, - .writefn =3D gt_virt_redir_ctl_write, .raw_writefn =3D raw_write, - }, - { .name =3D "CNTV_CTL_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, - .type =3D ARM_CP_IO, .access =3D PL0_RW, - .accessfn =3D gt_vtimer_access, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= tl), - .resetvalue =3D 0, - .readfn =3D gt_virt_redir_ctl_read, .raw_readfn =3D raw_read, - .writefn =3D gt_virt_redir_ctl_write, .raw_writefn =3D raw_write, - }, - /* TimerValue views: a 32 bit downcounting view of the underlying stat= e */ - { .name =3D "CNTP_TVAL", .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 = =3D 0, .opc2 =3D 0, - .secure =3D ARM_CP_SECSTATE_NS, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, - .accessfn =3D gt_ptimer_access, - .readfn =3D gt_phys_redir_tval_read, .writefn =3D gt_phys_redir_tval= _write, - }, - { .name =3D "CNTP_TVAL_S", - .cp =3D 15, .crn =3D 14, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, - .secure =3D ARM_CP_SECSTATE_S, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, - .accessfn =3D gt_ptimer_access, - .readfn =3D gt_sec_tval_read, .writefn =3D gt_sec_tval_write, - }, - { .name =3D "CNTP_TVAL_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, - .accessfn =3D gt_ptimer_access, .resetfn =3D gt_phys_timer_reset, - .readfn =3D gt_phys_redir_tval_read, .writefn =3D gt_phys_redir_tval= _write, - }, - { .name =3D "CNTV_TVAL", .cp =3D 15, .crn =3D 14, .crm =3D 3, .opc1 = =3D 0, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, - .accessfn =3D gt_vtimer_access, - .readfn =3D gt_virt_redir_tval_read, .writefn =3D gt_virt_redir_tval= _write, - }, - { .name =3D "CNTV_TVAL_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL0_RW, - .accessfn =3D gt_vtimer_access, .resetfn =3D gt_virt_timer_reset, - .readfn =3D gt_virt_redir_tval_read, .writefn =3D gt_virt_redir_tval= _write, - }, - /* The counter itself */ - { .name =3D "CNTPCT", .cp =3D 15, .crm =3D 14, .opc1 =3D 0, - .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_I= O, - .accessfn =3D gt_pct_access, - .readfn =3D gt_cnt_read, .resetfn =3D arm_cp_reset_ignore, - }, - { .name =3D "CNTPCT_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 1, - .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, - .accessfn =3D gt_pct_access, .readfn =3D gt_cnt_read, - }, - { .name =3D "CNTVCT", .cp =3D 15, .crm =3D 14, .opc1 =3D 1, - .access =3D PL0_R, .type =3D ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_I= O, - .accessfn =3D gt_vct_access, - .readfn =3D gt_virt_cnt_read, .resetfn =3D arm_cp_reset_ignore, - }, - { .name =3D "CNTVCT_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 2, - .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, - .accessfn =3D gt_vct_access, .readfn =3D gt_virt_cnt_read, - }, - /* Comparison value, indicating when the timer goes off */ - { .name =3D "CNTP_CVAL", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, - .secure =3D ARM_CP_SECSTATE_NS, - .access =3D PL0_RW, - .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), - .accessfn =3D gt_ptimer_access, - .readfn =3D gt_phys_redir_cval_read, .raw_readfn =3D raw_read, - .writefn =3D gt_phys_redir_cval_write, .raw_writefn =3D raw_write, - }, - { .name =3D "CNTP_CVAL_S", .cp =3D 15, .crm =3D 14, .opc1 =3D 2, - .secure =3D ARM_CP_SECSTATE_S, - .access =3D PL0_RW, - .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cv= al), - .accessfn =3D gt_ptimer_access, - .writefn =3D gt_sec_cval_write, .raw_writefn =3D raw_write, - }, - { .name =3D "CNTP_CVAL_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, - .access =3D PL0_RW, - .type =3D ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), - .resetvalue =3D 0, .accessfn =3D gt_ptimer_access, - .readfn =3D gt_phys_redir_cval_read, .raw_readfn =3D raw_read, - .writefn =3D gt_phys_redir_cval_write, .raw_writefn =3D raw_write, - }, - { .name =3D "CNTV_CVAL", .cp =3D 15, .crm =3D 14, .opc1 =3D 3, - .access =3D PL0_RW, - .type =3D ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), - .accessfn =3D gt_vtimer_access, - .readfn =3D gt_virt_redir_cval_read, .raw_readfn =3D raw_read, - .writefn =3D gt_virt_redir_cval_write, .raw_writefn =3D raw_write, - }, - { .name =3D "CNTV_CVAL_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, - .access =3D PL0_RW, - .type =3D ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), - .resetvalue =3D 0, .accessfn =3D gt_vtimer_access, - .readfn =3D gt_virt_redir_cval_read, .raw_readfn =3D raw_read, - .writefn =3D gt_virt_redir_cval_write, .raw_writefn =3D raw_write, - }, - /* - * Secure timer -- this is actually restricted to only EL3 - * and configurably Secure-EL1 via the accessfn. - */ - { .name =3D "CNTPS_TVAL_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 7, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL1_RW, - .accessfn =3D gt_stimer_access, - .readfn =3D gt_sec_tval_read, - .writefn =3D gt_sec_tval_write, - .resetfn =3D gt_sec_timer_reset, - }, - { .name =3D "CNTPS_CTL_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 7, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, - .type =3D ARM_CP_IO, .access =3D PL1_RW, - .accessfn =3D gt_stimer_access, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ct= l), - .resetvalue =3D 0, - .writefn =3D gt_sec_ctl_write, .raw_writefn =3D raw_write, - }, - { .name =3D "CNTPS_CVAL_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 7, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, - .type =3D ARM_CP_IO, .access =3D PL1_RW, - .accessfn =3D gt_stimer_access, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cv= al), - .writefn =3D gt_sec_cval_write, .raw_writefn =3D raw_write, - }, - REGINFO_SENTINEL -}; - -static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { - return CP_ACCESS_TRAP; - } - return CP_ACCESS_OK; -} - -#else - -/* - * In user-mode most of the generic timer registers are inaccessible - * however modern kernels (4.12+) allow access to cntvct_el0 - */ - -static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - ARMCPU *cpu =3D env_archcpu(env); - - /* - * Currently we have no support for QEMUTimer in linux-user so we - * can't call gt_get_countervalue(env), instead we directly - * call the lower level functions. - */ - return cpu_get_clock() / gt_cntfrq_period_ns(cpu); -} - -static const ARMCPRegInfo generic_timer_cp_reginfo[] =3D { - { .name =3D "CNTFRQ_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 0, - .type =3D ARM_CP_CONST, .access =3D PL0_R /* no PL1_RW in linux-user= */, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_cntfrq), - .resetvalue =3D NANOSECONDS_PER_SECOND / GTIMER_SCALE, - }, - { .name =3D "CNTVCT_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 0, .opc2 =3D 2, - .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, - .readfn =3D gt_virt_cnt_read, - }, - REGINFO_SENTINEL -}; - -#endif - -static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) -{ - if (arm_feature(env, ARM_FEATURE_LPAE)) { - raw_write(env, ri, value); - } else if (arm_feature(env, ARM_FEATURE_V7)) { - raw_write(env, ri, value & 0xfffff6ff); - } else { - raw_write(env, ri, value & 0xfffff1ff); - } -} - -#ifndef CONFIG_USER_ONLY -/* get_phys_addr() isn't present for user-mode-only targets */ - -static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - if (ri->opc2 & 4) { - /* - * The ATS12NSO* operations must trap to EL3 or EL2 if executed in - * Secure EL1 (which can only happen if EL3 is AArch64). - * They are simply UNDEF if executed from NS EL1. - * They function normally from EL2 or EL3. - */ - if (arm_current_el(env) =3D=3D 1) { - if (arm_is_secure_below_el3(env)) { - if (env->cp15.scr_el3 & SCR_EEL2) { - return CP_ACCESS_TRAP_UNCATEGORIZED_EL2; - } - return CP_ACCESS_TRAP_UNCATEGORIZED_EL3; - } - return CP_ACCESS_TRAP_UNCATEGORIZED; - } - } - return CP_ACCESS_OK; -} - -#ifdef CONFIG_TCG -static uint64_t do_ats_write(CPUARMState *env, uint64_t value, - MMUAccessType access_type, ARMMMUIdx mmu_idx) -{ - hwaddr phys_addr; - target_ulong page_size; - int prot; - bool ret; - uint64_t par64; - bool format64 =3D false; - MemTxAttrs attrs =3D {}; - ARMMMUFaultInfo fi =3D {}; - ARMCacheAttrs cacheattrs =3D {}; - - ret =3D get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &a= ttrs, - &prot, &page_size, &fi, &cacheattrs); - - if (ret) { - /* - * Some kinds of translation fault must cause exceptions rather - * than being reported in the PAR. - */ - int current_el =3D arm_current_el(env); - int target_el; - uint32_t syn, fsr, fsc; - bool take_exc =3D false; - - if (fi.s1ptw && current_el =3D=3D 1 - && arm_mmu_idx_is_stage1_of_2(mmu_idx)) { - /* - * Synchronous stage 2 fault on an access made as part of the - * translation table walk for AT S1E0* or AT S1E1* insn - * executed from NS EL1. If this is a synchronous external abo= rt - * and SCR_EL3.EA =3D=3D 1, then we take a synchronous externa= l abort - * to EL3. Otherwise the fault is taken as an exception to EL2, - * and HPFAR_EL2 holds the faulting IPA. - */ - if (fi.type =3D=3D ARMFault_SyncExternalOnWalk && - (env->cp15.scr_el3 & SCR_EA)) { - target_el =3D 3; - } else { - env->cp15.hpfar_el2 =3D extract64(fi.s2addr, 12, 47) << 4; - if (arm_is_secure_below_el3(env) && fi.s1ns) { - env->cp15.hpfar_el2 |=3D HPFAR_NS; - } - target_el =3D 2; - } - take_exc =3D true; - } else if (fi.type =3D=3D ARMFault_SyncExternalOnWalk) { - /* - * Synchronous external aborts during a translation table walk - * are taken as Data Abort exceptions. - */ - if (fi.stage2) { - if (current_el =3D=3D 3) { - target_el =3D 3; - } else { - target_el =3D 2; - } - } else { - target_el =3D exception_target_el(env); - } - take_exc =3D true; - } - - if (take_exc) { - /* Construct FSR and FSC using same logic as arm_deliver_fault= () */ - if (target_el =3D=3D 2 || arm_el_is_aa64(env, target_el) || - arm_s1_regime_using_lpae_format(env, mmu_idx)) { - fsr =3D arm_fi_to_lfsc(&fi); - fsc =3D extract32(fsr, 0, 6); - } else { - fsr =3D arm_fi_to_sfsc(&fi); - fsc =3D 0x3f; - } - /* - * Report exception with ESR indicating a fault due to a - * translation table walk for a cache maintenance instruction. - */ - syn =3D syn_data_abort_no_iss(current_el =3D=3D target_el, 0, - fi.ea, 1, fi.s1ptw, 1, fsc); - env->exception.vaddress =3D value; - env->exception.fsr =3D fsr; - raise_exception(env, EXCP_DATA_ABORT, syn, target_el); - } - } - - if (is_a64(env)) { - format64 =3D true; - } else if (arm_feature(env, ARM_FEATURE_LPAE)) { - /* - * ATS1Cxx: - * * TTBCR.EAE determines whether the result is returned using the - * 32-bit or the 64-bit PAR format - * * Instructions executed in Hyp mode always use the 64bit format - * - * ATS1S2NSOxx uses the 64bit format if any of the following is tr= ue: - * * The Non-secure TTBCR.EAE bit is set to 1 - * * The implementation includes EL2, and the value of HCR.VM is 1 - * - * (Note that HCR.DC makes HCR.VM behave as if it is 1.) - * - * ATS1Hx always uses the 64bit format. - */ - format64 =3D arm_s1_regime_using_lpae_format(env, mmu_idx); - - if (arm_feature(env, ARM_FEATURE_EL2)) { - if (mmu_idx =3D=3D ARMMMUIdx_E10_0 || - mmu_idx =3D=3D ARMMMUIdx_E10_1 || - mmu_idx =3D=3D ARMMMUIdx_E10_1_PAN) { - format64 |=3D env->cp15.hcr_el2 & (HCR_VM | HCR_DC); - } else { - format64 |=3D arm_current_el(env) =3D=3D 2; - } - } - } - - if (format64) { - /* Create a 64-bit PAR */ - par64 =3D (1 << 11); /* LPAE bit always set */ - if (!ret) { - par64 |=3D phys_addr & ~0xfffULL; - if (!attrs.secure) { - par64 |=3D (1 << 9); /* NS */ - } - par64 |=3D (uint64_t)cacheattrs.attrs << 56; /* ATTR */ - par64 |=3D cacheattrs.shareability << 7; /* SH */ - } else { - uint32_t fsr =3D arm_fi_to_lfsc(&fi); - - par64 |=3D 1; /* F */ - par64 |=3D (fsr & 0x3f) << 1; /* FS */ - if (fi.stage2) { - par64 |=3D (1 << 9); /* S */ - } - if (fi.s1ptw) { - par64 |=3D (1 << 8); /* PTW */ - } - } - } else { - /* - * fsr is a DFSR/IFSR value for the short descriptor - * translation table format (with WnR always clear). - * Convert it to a 32-bit PAR. - */ - if (!ret) { - /* We do not set any attribute bits in the PAR */ - if (page_size =3D=3D (1 << 24) - && arm_feature(env, ARM_FEATURE_V7)) { - par64 =3D (phys_addr & 0xff000000) | (1 << 1); - } else { - par64 =3D phys_addr & 0xfffff000; - } - if (!attrs.secure) { - par64 |=3D (1 << 9); /* NS */ - } - } else { - uint32_t fsr =3D arm_fi_to_sfsc(&fi); - - par64 =3D ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) | - ((fsr & 0xf) << 1) | 1; - } - } - return par64; -} -#endif /* CONFIG_TCG */ - -static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) -{ -#ifdef CONFIG_TCG - MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; - uint64_t par64; - ARMMMUIdx mmu_idx; - int el =3D arm_current_el(env); - bool secure =3D arm_is_secure_below_el3(env); - - switch (ri->opc2 & 6) { - case 0: - /* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP= */ - switch (el) { - case 3: - mmu_idx =3D ARMMMUIdx_SE3; - break; - case 2: - g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ - /* fall through */ - case 1: - if (ri->crm =3D=3D 9 && (env->uncached_cpsr & CPSR_PAN)) { - mmu_idx =3D (secure ? ARMMMUIdx_Stage1_SE1_PAN - : ARMMMUIdx_Stage1_E1_PAN); - } else { - mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stag= e1_E1; - } - break; - default: - g_assert_not_reached(); - } - break; - case 2: - /* stage 1 current state PL0: ATS1CUR, ATS1CUW */ - switch (el) { - case 3: - mmu_idx =3D ARMMMUIdx_SE10_0; - break; - case 2: - g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */ - mmu_idx =3D ARMMMUIdx_Stage1_E0; - break; - case 1: - mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E= 0; - break; - default: - g_assert_not_reached(); - } - break; - case 4: - /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */ - mmu_idx =3D ARMMMUIdx_E10_1; - break; - case 6: - /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */ - mmu_idx =3D ARMMMUIdx_E10_0; - break; - default: - g_assert_not_reached(); - } - - par64 =3D do_ats_write(env, value, access_type, mmu_idx); - - A32_BANKED_CURRENT_REG_SET(env, par, par64); -#else - /* Handled by hardware accelerator. */ - g_assert_not_reached(); -#endif /* CONFIG_TCG */ -} - -static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ -#ifdef CONFIG_TCG - MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; - uint64_t par64; - - par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2); - - A32_BANKED_CURRENT_REG_SET(env, par, par64); -#else - /* Handled by hardware accelerator. */ - g_assert_not_reached(); -#endif /* CONFIG_TCG */ -} - -static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo = *ri, - bool isread) -{ - if (arm_current_el(env) =3D=3D 3 && - !(env->cp15.scr_el3 & (SCR_NS | SCR_EEL2))) { - return CP_ACCESS_TRAP; - } - return CP_ACCESS_OK; -} - -static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ -#ifdef CONFIG_TCG - MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; - ARMMMUIdx mmu_idx; - int secure =3D arm_is_secure_below_el3(env); - - switch (ri->opc2 & 6) { - case 0: - switch (ri->opc1) { - case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */ - if (ri->crm =3D=3D 9 && (env->pstate & PSTATE_PAN)) { - mmu_idx =3D (secure ? ARMMMUIdx_Stage1_SE1_PAN - : ARMMMUIdx_Stage1_E1_PAN); - } else { - mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stag= e1_E1; - } - break; - case 4: /* AT S1E2R, AT S1E2W */ - mmu_idx =3D secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2; - break; - case 6: /* AT S1E3R, AT S1E3W */ - mmu_idx =3D ARMMMUIdx_SE3; - break; - default: - g_assert_not_reached(); - } - break; - case 2: /* AT S1E0R, AT S1E0W */ - mmu_idx =3D secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0; - break; - case 4: /* AT S12E1R, AT S12E1W */ - mmu_idx =3D secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1; - break; - case 6: /* AT S12E0R, AT S12E0W */ - mmu_idx =3D secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0; - break; - default: - g_assert_not_reached(); - } - - env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, mmu_idx); -#else - /* Handled by hardware accelerator. */ - g_assert_not_reached(); -#endif /* CONFIG_TCG */ -} -#endif - -static const ARMCPRegInfo vapa_cp_reginfo[] =3D { - { .name =3D "PAR", .cp =3D 15, .crn =3D 7, .crm =3D 4, .opc1 =3D 0, .o= pc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0, - .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.par_s), - offsetoflow32(CPUARMState, cp15.par_ns) }, - .writefn =3D par_write }, -#ifndef CONFIG_USER_ONLY - /* This underdecoding is safe because the reginfo is NO_RAW. */ - { .name =3D "ATS", .cp =3D 15, .crn =3D 7, .crm =3D 8, .opc1 =3D 0, .o= pc2 =3D CP_ANY, - .access =3D PL1_W, .accessfn =3D ats_access, - .writefn =3D ats_write, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC = }, -#endif - REGINFO_SENTINEL -}; - -/* Return basic MPU access permission bits. */ -static uint32_t simple_mpu_ap_bits(uint32_t val) -{ - uint32_t ret; - uint32_t mask; - int i; - ret =3D 0; - mask =3D 3; - for (i =3D 0; i < 16; i +=3D 2) { - ret |=3D (val >> i) & mask; - mask <<=3D 2; - } - return ret; -} - -/* Pad basic MPU access permission bits to extended format. */ -static uint32_t extended_mpu_ap_bits(uint32_t val) -{ - uint32_t ret; - uint32_t mask; - int i; - ret =3D 0; - mask =3D 3; - for (i =3D 0; i < 16; i +=3D 2) { - ret |=3D (val & mask) << i; - mask <<=3D 2; - } - return ret; -} - -static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.pmsav5_data_ap =3D extended_mpu_ap_bits(value); -} - -static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *= ri) -{ - return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap); -} - -static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.pmsav5_insn_ap =3D extended_mpu_ap_bits(value); -} - -static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *= ri) -{ - return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap); -} - -static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - uint32_t *u32p =3D *(uint32_t **)raw_ptr(env, ri); - - if (!u32p) { - return 0; - } - - u32p +=3D env->pmsav7.rnr[M_REG_NS]; - return *u32p; -} - -static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - uint32_t *u32p =3D *(uint32_t **)raw_ptr(env, ri); - - if (!u32p) { - return; - } - - u32p +=3D env->pmsav7.rnr[M_REG_NS]; - tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ - *u32p =3D value; -} - -static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - uint32_t nrgs =3D cpu->pmsav7_dregion; - - if (value >=3D nrgs) { - qemu_log_mask(LOG_GUEST_ERROR, - "PMSAv7 RGNR write >=3D # supported regions, %" PRIu= 32 - " > %" PRIu32 "\n", (uint32_t)value, nrgs); - return; - } - - raw_write(env, ri, value); -} - -static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { - /* - * Reset for all these registers is handled in arm_cpu_reset(), - * because the PMSAv7 is also used by M-profile CPUs, which do - * not register cpregs but still need the state to be reset. - */ - { .name =3D "DRBAR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, = .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, - .fieldoffset =3D offsetof(CPUARMState, pmsav7.drbar), - .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, - .resetfn =3D arm_cp_reset_ignore }, - { .name =3D "DRSR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, .= opc2 =3D 2, - .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, - .fieldoffset =3D offsetof(CPUARMState, pmsav7.drsr), - .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, - .resetfn =3D arm_cp_reset_ignore }, - { .name =3D "DRACR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, = .opc2 =3D 4, - .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, - .fieldoffset =3D offsetof(CPUARMState, pmsav7.dracr), - .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, - .resetfn =3D arm_cp_reset_ignore }, - { .name =3D "RGNR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 2, .= opc2 =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), - .writefn =3D pmsav7_rgnr_write, - .resetfn =3D arm_cp_reset_ignore }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo pmsav5_cp_reginfo[] =3D { - { .name =3D "DATA_AP", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.pmsav5_data_ap), - .readfn =3D pmsav5_data_ap_read, .writefn =3D pmsav5_data_ap_write, = }, - { .name =3D "INSN_AP", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.pmsav5_insn_ap), - .readfn =3D pmsav5_insn_ap_read, .writefn =3D pmsav5_insn_ap_write, = }, - { .name =3D "DATA_EXT_AP", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.pmsav5_data_ap), - .resetvalue =3D 0, }, - { .name =3D "INSN_EXT_AP", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 3, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.pmsav5_insn_ap), - .resetvalue =3D 0, }, - { .name =3D "DCACHE_CFG", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c2_data), .resetvalue = =3D 0, }, - { .name =3D "ICACHE_CFG", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c2_insn), .resetvalue = =3D 0, }, - /* Protection region base and size registers */ - { .name =3D "946_PRBS0", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 =3D= 0, - .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[0]) }, - { .name =3D "946_PRBS1", .cp =3D 15, .crn =3D 6, .crm =3D 1, .opc1 =3D= 0, - .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[1]) }, - { .name =3D "946_PRBS2", .cp =3D 15, .crn =3D 6, .crm =3D 2, .opc1 =3D= 0, - .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[2]) }, - { .name =3D "946_PRBS3", .cp =3D 15, .crn =3D 6, .crm =3D 3, .opc1 =3D= 0, - .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[3]) }, - { .name =3D "946_PRBS4", .cp =3D 15, .crn =3D 6, .crm =3D 4, .opc1 =3D= 0, - .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[4]) }, - { .name =3D "946_PRBS5", .cp =3D 15, .crn =3D 6, .crm =3D 5, .opc1 =3D= 0, - .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[5]) }, - { .name =3D "946_PRBS6", .cp =3D 15, .crn =3D 6, .crm =3D 6, .opc1 =3D= 0, - .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[6]) }, - { .name =3D "946_PRBS7", .cp =3D 15, .crn =3D 6, .crm =3D 7, .opc1 =3D= 0, - .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[7]) }, - REGINFO_SENTINEL -}; - -static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - TCR *tcr =3D raw_ptr(env, ri); - int maskshift =3D extract32(value, 0, 3); - - if (!arm_feature(env, ARM_FEATURE_V8)) { - if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) { - /* - * Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when - * using Long-desciptor translation table format - */ - value &=3D ~((7 << 19) | (3 << 14) | (0xf << 3)); - } else if (arm_feature(env, ARM_FEATURE_EL3)) { - /* - * In an implementation that includes the Security Extensions - * TTBCR has additional fields PD0 [4] and PD1 [5] for - * Short-descriptor translation table format. - */ - value &=3D TTBCR_PD1 | TTBCR_PD0 | TTBCR_N; - } else { - value &=3D TTBCR_N; - } - } - - /* - * Update the masks corresponding to the TCR bank being written - * Note that we always calculate mask and base_mask, but - * they are only used for short-descriptor tables (ie if EAE is 0); - * for long-descriptor tables the TCR fields are used differently - * and the mask and base_mask values are meaningless. - */ - tcr->raw_tcr =3D value; - tcr->mask =3D ~(((uint32_t)0xffffffffu) >> maskshift); - tcr->base_mask =3D ~((uint32_t)0x3fffu >> maskshift); -} - -static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - TCR *tcr =3D raw_ptr(env, ri); - - if (arm_feature(env, ARM_FEATURE_LPAE)) { - /* - * With LPAE the TTBCR could result in a change of ASID - * via the TTBCR.A1 bit, so do a TLB flush. - */ - tlb_flush(CPU(cpu)); - } - /* Preserve the high half of TCR_EL1, set via TTBCR2. */ - value =3D deposit64(tcr->raw_tcr, 0, 32, value); - vmsa_ttbcr_raw_write(env, ri, value); -} - -static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - TCR *tcr =3D raw_ptr(env, ri); - - /* - * Reset both the TCR as well as the masks corresponding to the bank of - * the TCR being reset. - */ - tcr->raw_tcr =3D 0; - tcr->mask =3D 0; - tcr->base_mask =3D 0xffffc000u; -} - -static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - TCR *tcr =3D raw_ptr(env, ri); - - /* For AArch64 the A1 bit could result in a change of ASID, so TLB flu= sh. */ - tlb_flush(CPU(cpu)); - tcr->raw_tcr =3D value; -} - -static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* If the ASID changes (with a 64-bit write), we must flush the TLB. = */ - if (cpreg_field_is_64bit(ri) && - extract64(raw_read(env, ri) ^ value, 48, 16) !=3D 0) { - ARMCPU *cpu =3D env_archcpu(env); - tlb_flush(CPU(cpu)); - } - raw_write(env, ri, value); -} - -static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *= ri, - uint64_t value) -{ - /* - * If we are running with E2&0 regime, then an ASID is active. - * Flush if that might be changing. Note we're not checking - * TCR_EL2.A1 to know if this is really the TTBRx_EL2 that - * holds the active ASID, only checking the field that might. - */ - if (extract64(raw_read(env, ri) ^ value, 48, 16) && - (arm_hcr_el2_eff(env) & HCR_E2H)) { - uint16_t mask =3D ARMMMUIdxBit_E20_2 | - ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E20_0; - - if (arm_is_secure_below_el3(env)) { - mask >>=3D ARM_MMU_IDX_A_NS; - } - - tlb_flush_by_mmuidx(env_cpu(env), mask); - } - raw_write(env, ri, value); -} - -static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); - - /* - * A change in VMID to the stage2 page table (Stage2) invalidates - * the combined stage 1&2 tlbs (EL10_1 and EL10_0). - */ - if (raw_read(env, ri) !=3D value) { - uint16_t mask =3D ARMMMUIdxBit_E10_1 | - ARMMMUIdxBit_E10_1_PAN | - ARMMMUIdxBit_E10_0; - - if (arm_is_secure_below_el3(env)) { - mask >>=3D ARM_MMU_IDX_A_NS; - } - - tlb_flush_by_mmuidx(cs, mask); - raw_write(env, ri, value); - } -} - -static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { - { .name =3D "DFSR", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .type =3D ARM_CP_= ALIAS, - .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dfsr_s), - offsetoflow32(CPUARMState, cp15.dfsr_ns) }, }, - { .name =3D "IFSR", .cp =3D 15, .crn =3D 5, .crm =3D 0, .opc1 =3D 0, .= opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, - .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.ifsr_s), - offsetoflow32(CPUARMState, cp15.ifsr_ns) } }, - { .name =3D "DFAR", .cp =3D 15, .opc1 =3D 0, .crn =3D 6, .crm =3D 0, .= opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.dfar_s), - offsetof(CPUARMState, cp15.dfar_ns) } }, - { .name =3D "FAR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .crn =3D 6, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .fieldoffset =3D offsetof(CPUARMState, cp15.far_el[1]), - .resetvalue =3D 0, }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { - { .name =3D "ESR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .crn =3D 5, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, - { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), - offsetof(CPUARMState, cp15.ttbr0_ns) } }, - { .name =3D "TTBR1_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), - offsetof(CPUARMState, cp15.ttbr1_ns) } }, - { .name =3D "TCR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .writefn =3D vmsa_tcr_el12_write, - .resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D raw_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[1]) }, - { .name =3D "TTBCR", .cp =3D 15, .crn =3D 2, .crm =3D 0, .opc1 =3D 0, = .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .type =3D ARM_CP_ALIAS, .writefn =3D vmsa_ttbcr_write, - .raw_writefn =3D vmsa_ttbcr_raw_write, - .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tcr_el[3]), - offsetoflow32(CPUARMState, cp15.tcr_el[1])} }, - REGINFO_SENTINEL -}; - -/* - * Note that unlike TTBCR, writing to TTBCR2 does not require flushing - * qemu tlbs nor adjusting cached masks. - */ -static const ARMCPRegInfo ttbcr2_reginfo =3D { - .name =3D "TTBCR2", .cp =3D 15, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .= opc2 =3D 3, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .type =3D ARM_CP_ALIAS, - .bank_fieldoffsets =3D { offsetofhigh32(CPUARMState, cp15.tcr_el[3]), - offsetofhigh32(CPUARMState, cp15.tcr_el[1]) }, -}; - -static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.c15_ticonfig =3D value & 0xe7; - /* The OS_TYPE bit in this register changes the reported CPUID! */ - env->cp15.c0_cpuid =3D (value & (1 << 5)) ? - ARM_CPUID_TI915T : ARM_CPUID_TI925T; -} - -static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.c15_threadid =3D value & 0xffff; -} - -static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Wait-for-interrupt (deprecated) */ - cpu_interrupt(env_cpu(env), CPU_INTERRUPT_HALT); -} - -static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* - * On OMAP there are registers indicating the max/min index of dcache = lines - * containing a dirty line; cache flush operations have to reset these. - */ - env->cp15.c15_i_max =3D 0x000; - env->cp15.c15_i_min =3D 0xff0; -} - -static const ARMCPRegInfo omap_cp_reginfo[] =3D { - { .name =3D "DFSR", .cp =3D 15, .crn =3D 5, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .type =3D AR= M_CP_OVERRIDE, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.esr_el[1]), - .resetvalue =3D 0, }, - { .name =3D "", .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D 0, .opc= 2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_NOP }, - { .name =3D "TICONFIG", .cp =3D 15, .crn =3D 15, .crm =3D 1, .opc1 =3D= 0, .opc2 =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_ticonfig), .resetval= ue =3D 0, - .writefn =3D omap_ticonfig_write }, - { .name =3D "IMAX", .cp =3D 15, .crn =3D 15, .crm =3D 2, .opc1 =3D 0, = .opc2 =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = =3D 0, }, - { .name =3D "IMIN", .cp =3D 15, .crn =3D 15, .crm =3D 3, .opc1 =3D 0, = .opc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0xff0, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_i_min) }, - { .name =3D "THREADID", .cp =3D 15, .crn =3D 15, .crm =3D 4, .opc1 =3D= 0, .opc2 =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_threadid), .resetval= ue =3D 0, - .writefn =3D omap_threadid_write }, - { .name =3D "TI925T_STATUS", .cp =3D 15, .crn =3D 15, - .crm =3D 8, .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, - .type =3D ARM_CP_NO_RAW, - .readfn =3D arm_cp_read_zero, .writefn =3D omap_wfi_write, }, - /* - * TODO: Peripheral port remap register: - * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller - * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff), - * when MMU is off. - */ - { .name =3D "OMAP_CACHEMAINT", .cp =3D 15, .crn =3D 7, .crm =3D CP_ANY, - .opc1 =3D 0, .opc2 =3D CP_ANY, .access =3D PL1_W, - .type =3D ARM_CP_OVERRIDE | ARM_CP_NO_RAW, - .writefn =3D omap_cachemaint_write }, - { .name =3D "C9", .cp =3D 15, .crn =3D 9, - .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1= _RW, - .type =3D ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.c15_cpar =3D value & 0x3fff; -} - -static const ARMCPRegInfo xscale_cp_reginfo[] =3D { - { .name =3D "XSCALE_CPAR", - .cp =3D 15, .crn =3D 15, .crm =3D 1, .opc1 =3D 0, .opc2 =3D 0, .acce= ss =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = =3D 0, - .writefn =3D xscale_cpar_write, }, - { .name =3D "XSCALE_AUXCR", - .cp =3D 15, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 1, .acces= s =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c1_xscaleauxcr), - .resetvalue =3D 0, }, - /* - * XScale specific cache-lockdown: since we have no cache we NOP these - * and hope the guest does not really rely on cache behaviour. - */ - { .name =3D "XSCALE_LOCK_ICACHE_LINE", - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, - { .name =3D "XSCALE_UNLOCK_ICACHE", - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, - { .name =3D "XSCALE_DCACHE_LOCK", - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_NOP }, - { .name =3D "XSCALE_UNLOCK_DCACHE", - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 2, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo dummy_c15_cp_reginfo[] =3D { - /* - * RAZ/WI the whole crn=3D15 space, when we don't have a more specific - * implementation of this implementation-defined space. - * Ideally this should eventually disappear in favour of actually - * implementing the correct behaviour for all cores. - */ - { .name =3D "C15_IMPDEF", .cp =3D 15, .crn =3D 15, - .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, - .access =3D PL1_RW, - .type =3D ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, - .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] =3D { - /* Cache status: RAZ because we have no cache so it's always clean */ - { .name =3D "CDSR", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 =3D 0, = .opc2 =3D 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, - .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo cache_block_ops_cp_reginfo[] =3D { - /* We never have a a block transfer operation in progress */ - { .name =3D "BXSR", .cp =3D 15, .crn =3D 7, .crm =3D 12, .opc1 =3D 0, = .opc2 =3D 4, - .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, - .resetvalue =3D 0 }, - /* The cache ops themselves: these all NOP for QEMU */ - { .name =3D "IICR", .cp =3D 15, .crm =3D 5, .opc1 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, - { .name =3D "IDCR", .cp =3D 15, .crm =3D 6, .opc1 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, - { .name =3D "CDCR", .cp =3D 15, .crm =3D 12, .opc1 =3D 0, - .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, - { .name =3D "PIR", .cp =3D 15, .crm =3D 12, .opc1 =3D 1, - .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, - { .name =3D "PDR", .cp =3D 15, .crm =3D 12, .opc1 =3D 2, - .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, - { .name =3D "CIDCR", .cp =3D 15, .crm =3D 14, .opc1 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo cache_test_clean_cp_reginfo[] =3D { - /* - * The cache test-and-clean instructions always return (1 << 30) - * to indicate that there are no dirty cache lines. - */ - { .name =3D "TC_DCACHE", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 = =3D 0, .opc2 =3D 3, - .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, - .resetvalue =3D (1 << 30) }, - { .name =3D "TCI_DCACHE", .cp =3D 15, .crn =3D 7, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 3, - .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, - .resetvalue =3D (1 << 30) }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo strongarm_cp_reginfo[] =3D { - /* Ignore ReadBuffer accesses */ - { .name =3D "C9_READBUFFER", .cp =3D 15, .crn =3D 9, - .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, - .access =3D PL1_RW, .resetvalue =3D 0, - .type =3D ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, - REGINFO_SENTINEL -}; - -static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - unsigned int cur_el =3D arm_current_el(env); - - if (arm_is_el2_enabled(env) && cur_el =3D=3D 1) { - return env->cp15.vpidr_el2; - } - return raw_read(env, ri); -} - -static uint64_t mpidr_read_val(CPUARMState *env) -{ - ARMCPU *cpu =3D env_archcpu(env); - uint64_t mpidr =3D cpu->mp_affinity; - - if (arm_feature(env, ARM_FEATURE_V7MP)) { - mpidr |=3D (1U << 31); - /* - * Cores which are uniprocessor (non-coherent) - * but still implement the MP extensions set - * bit 30. (For instance, Cortex-R5). - */ - if (cpu->mp_is_up) { - mpidr |=3D (1u << 30); - } - } - return mpidr; -} - -static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - unsigned int cur_el =3D arm_current_el(env); - - if (arm_is_el2_enabled(env) && cur_el =3D=3D 1) { - return env->cp15.vmpidr_el2; - } - return mpidr_read_val(env); -} - -static const ARMCPRegInfo lpae_cp_reginfo[] =3D { - /* NOP AMAIR0/1 */ - { .name =3D "AMAIR0", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .crn =3D 10, .crm =3D 3, .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ - { .name =3D "AMAIR1", .cp =3D 15, .crn =3D 10, .crm =3D 3, .opc1 =3D 0= , .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "PAR", .cp =3D 15, .crm =3D 7, .opc1 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_64BIT, .resetvalue =3D 0, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.par_s), - offsetof(CPUARMState, cp15.par_ns)} }, - { .name =3D "TTBR0", .cp =3D 15, .crm =3D 2, .opc1 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), - offsetof(CPUARMState, cp15.ttbr0_ns) }, - .writefn =3D vmsa_ttbr_write, }, - { .name =3D "TTBR1", .cp =3D 15, .crm =3D 2, .opc1 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), - offsetof(CPUARMState, cp15.ttbr1_ns) }, - .writefn =3D vmsa_ttbr_write, }, - REGINFO_SENTINEL -}; - -static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return vfp_get_fpcr(env); -} - -static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - vfp_set_fpcr(env, value); -} - -static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return vfp_get_fpsr(env); -} - -static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - vfp_set_fpsr(env, value); -} - -static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInf= o *ri, - bool isread) -{ - if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UMA)) { - return CP_ACCESS_TRAP; - } - return CP_ACCESS_OK; -} - -static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->daif =3D value & PSTATE_DAIF; -} - -static uint64_t aa64_pan_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return env->pstate & PSTATE_PAN; -} - -static void aa64_pan_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->pstate =3D (env->pstate & ~PSTATE_PAN) | (value & PSTATE_PAN); -} - -static const ARMCPRegInfo pan_reginfo =3D { - .name =3D "PAN", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 2, .opc2 =3D 3, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_RW, - .readfn =3D aa64_pan_read, .writefn =3D aa64_pan_write -}; - -static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return env->pstate & PSTATE_UAO; -} - -static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->pstate =3D (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO); -} - -static const ARMCPRegInfo uao_reginfo =3D { - .name =3D "UAO", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 2, .opc2 =3D 4, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_RW, - .readfn =3D aa64_uao_read, .writefn =3D aa64_uao_write -}; - -static uint64_t aa64_dit_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return env->pstate & PSTATE_DIT; -} - -static void aa64_dit_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->pstate =3D (env->pstate & ~PSTATE_DIT) | (value & PSTATE_DIT); -} - -static const ARMCPRegInfo dit_reginfo =3D { - .name =3D "DIT", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 5, - .type =3D ARM_CP_NO_RAW, .access =3D PL0_RW, - .readfn =3D aa64_dit_read, .writefn =3D aa64_dit_write -}; - -static uint64_t aa64_ssbs_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return env->pstate & PSTATE_SSBS; -} - -static void aa64_ssbs_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->pstate =3D (env->pstate & ~PSTATE_SSBS) | (value & PSTATE_SSBS); -} - -static const ARMCPRegInfo ssbs_reginfo =3D { - .name =3D "SSBS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 6, - .type =3D ARM_CP_NO_RAW, .access =3D PL0_RW, - .readfn =3D aa64_ssbs_read, .writefn =3D aa64_ssbs_write -}; - -static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - /* Cache invalidate/clean to Point of Coherency or Persistence... */ - switch (arm_current_el(env)) { - case 0: - /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ - if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { - return CP_ACCESS_TRAP; - } - /* fall through */ - case 1: - /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */ - if (arm_hcr_el2_eff(env) & HCR_TPCP) { - return CP_ACCESS_TRAP_EL2; - } - break; - } - return CP_ACCESS_OK; -} - -static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - /* Cache invalidate/clean to Point of Unification... */ - switch (arm_current_el(env)) { - case 0: - /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ - if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { - return CP_ACCESS_TRAP; - } - /* fall through */ - case 1: - /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */ - if (arm_hcr_el2_eff(env) & HCR_TPU) { - return CP_ACCESS_TRAP_EL2; - } - break; - } - return CP_ACCESS_OK; -} - -/* - * See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions - * Page D4-1736 (DDI0487A.b) - */ - -static int vae1_tlbmask(CPUARMState *env) -{ - uint64_t hcr =3D arm_hcr_el2_eff(env); - uint16_t mask; - - if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { - mask =3D ARMMMUIdxBit_E20_2 | - ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E20_0; - } else { - mask =3D ARMMMUIdxBit_E10_1 | - ARMMMUIdxBit_E10_1_PAN | - ARMMMUIdxBit_E10_0; - } - - if (arm_is_secure_below_el3(env)) { - mask >>=3D ARM_MMU_IDX_A_NS; - } - - return mask; -} - -/* Return 56 if TBI is enabled, 64 otherwise. */ -static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, - uint64_t addr) -{ - uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; - int tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); - int select =3D extract64(addr, 55, 1); - - return (tbi >> select) & 1 ? 56 : 64; -} - -static int vae1_tlbbits(CPUARMState *env, uint64_t addr) -{ - uint64_t hcr =3D arm_hcr_el2_eff(env); - ARMMMUIdx mmu_idx; - - /* Only the regime of the mmu_idx below is significant. */ - if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { - mmu_idx =3D ARMMMUIdx_E20_0; - } else { - mmu_idx =3D ARMMMUIdx_E10_0; - } - - if (arm_is_secure_below_el3(env)) { - mmu_idx &=3D ~ARM_MMU_IDX_A_NS; - } - - return tlbbits_for_regime(env, mmu_idx, addr); -} - -static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo= *ri, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - int mask =3D vae1_tlbmask(env); - - tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); -} - -static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *= ri, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - int mask =3D vae1_tlbmask(env); - - if (tlb_force_broadcast(env)) { - tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); - } else { - tlb_flush_by_mmuidx(cs, mask); - } -} - -static int alle1_tlbmask(CPUARMState *env) -{ - /* - * Note that the 'ALL' scope must invalidate both stage 1 and - * stage 2 translations, whereas most other scopes only invalidate - * stage 1 translations. - */ - if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE10_1 | - ARMMMUIdxBit_SE10_1_PAN | - ARMMMUIdxBit_SE10_0; - } else { - return ARMMMUIdxBit_E10_1 | - ARMMMUIdxBit_E10_1_PAN | - ARMMMUIdxBit_E10_0; - } -} - -static int e2_tlbmask(CPUARMState *env) -{ - if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE20_0 | - ARMMMUIdxBit_SE20_2 | - ARMMMUIdxBit_SE20_2_PAN | - ARMMMUIdxBit_SE2; - } else { - return ARMMMUIdxBit_E20_0 | - ARMMMUIdxBit_E20_2 | - ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E2; - } -} - -static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - int mask =3D alle1_tlbmask(env); - - tlb_flush_by_mmuidx(cs, mask); -} - -static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - int mask =3D e2_tlbmask(env); - - tlb_flush_by_mmuidx(cs, mask); -} - -static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); - - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3); -} - -static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - int mask =3D alle1_tlbmask(env); - - tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); -} - -static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *= ri, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - int mask =3D e2_tlbmask(env); - - tlb_flush_by_mmuidx_all_cpus_synced(cs, mask); -} - -static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *= ri, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3); -} - -static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* - * Invalidate by VA, EL2 - * Currently handles both VAE2 and VALE2, since we don't support - * flush-last-level-only. - */ - CPUState *cs =3D env_cpu(env); - int mask =3D e2_tlbmask(env); - uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - - tlb_flush_page_by_mmuidx(cs, pageaddr, mask); -} - -static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* - * Invalidate by VA, EL3 - * Currently handles both VAE3 and VALE3, since we don't support - * flush-last-level-only. - */ - ARMCPU *cpu =3D env_archcpu(env); - CPUState *cs =3D CPU(cpu); - uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3); -} - -static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r= i, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - int mask =3D vae1_tlbmask(env); - uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - int bits =3D vae1_tlbbits(env, pageaddr); - - tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits= ); -} - -static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* - * Invalidate by VA, EL1&0 (AArch64 version). - * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1, - * since we don't support flush-for-specific-ASID-only or - * flush-last-level-only. - */ - CPUState *cs =3D env_cpu(env); - int mask =3D vae1_tlbmask(env); - uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - int bits =3D vae1_tlbbits(env, pageaddr); - - if (tlb_force_broadcast(env)) { - tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, = bits); - } else { - tlb_flush_page_bits_by_mmuidx(cs, pageaddr, mask, bits); - } -} - -static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *r= i, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - bool secure =3D arm_is_secure_below_el3(env); - int mask =3D secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; - int bits =3D tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUId= x_E2, - pageaddr); - - tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits= ); -} - -static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *r= i, - uint64_t value) -{ - CPUState *cs =3D env_cpu(env); - uint64_t pageaddr =3D sextract64(value << 12, 0, 56); - int bits =3D tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr); - - tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_SE3, bits); -} - -#ifdef TARGET_AARCH64 -static uint64_t tlbi_aa64_range_get_length(CPUARMState *env, - uint64_t value) -{ - unsigned int page_shift; - unsigned int page_size_granule; - uint64_t num; - uint64_t scale; - uint64_t exponent; - uint64_t length; - - num =3D extract64(value, 39, 4); - scale =3D extract64(value, 44, 2); - page_size_granule =3D extract64(value, 46, 2); - - page_shift =3D page_size_granule * 2 + 12; - - if (page_size_granule =3D=3D 0) { - qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", - page_size_granule); - return 0; - } - - exponent =3D (5 * scale) + 1; - length =3D (num + 1) << (exponent + page_shift); - - return length; -} - -static uint64_t tlbi_aa64_range_get_base(CPUARMState *env, uint64_t value, - bool two_ranges) -{ - /* TODO: ARMv8.7 FEAT_LPA2 */ - uint64_t pageaddr; - - if (two_ranges) { - pageaddr =3D sextract64(value, 0, 37) << TARGET_PAGE_BITS; - } else { - pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; - } - - return pageaddr; -} - -static void do_rvae_write(CPUARMState *env, uint64_t value, - int idxmap, bool synced) -{ - ARMMMUIdx one_idx =3D ARM_MMU_IDX_A | ctz32(idxmap); - bool two_ranges =3D regime_has_2_ranges(one_idx); - uint64_t baseaddr, length; - int bits; - - baseaddr =3D tlbi_aa64_range_get_base(env, value, two_ranges); - length =3D tlbi_aa64_range_get_length(env, value); - bits =3D tlbbits_for_regime(env, one_idx, baseaddr); - - if (synced) { - tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env), - baseaddr, - length, - idxmap, - bits); - } else { - tlb_flush_range_by_mmuidx(env_cpu(env), baseaddr, - length, idxmap, bits); - } -} - -static void tlbi_aa64_rvae1_write(CPUARMState *env, - const ARMCPRegInfo *ri, - uint64_t value) -{ - /* - * Invalidate by VA range, EL1&0. - * Currently handles all of RVAE1, RVAAE1, RVAALE1 and RVALE1, - * since we don't support flush-for-specific-ASID-only or - * flush-last-level-only. - */ - - do_rvae_write(env, value, vae1_tlbmask(env), - tlb_force_broadcast(env)); -} - -static void tlbi_aa64_rvae1is_write(CPUARMState *env, - const ARMCPRegInfo *ri, - uint64_t value) -{ - /* - * Invalidate by VA range, Inner/Outer Shareable EL1&0. - * Currently handles all of RVAE1IS, RVAE1OS, RVAAE1IS, RVAAE1OS, - * RVAALE1IS, RVAALE1OS, RVALE1IS and RVALE1OS, since we don't support - * flush-for-specific-ASID-only, flush-last-level-only or inner/outer - * shareable specific flushes. - */ - - do_rvae_write(env, value, vae1_tlbmask(env), true); -} - -static int vae2_tlbmask(CPUARMState *env) -{ - return (arm_is_secure_below_el3(env) - ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2); -} - -static void tlbi_aa64_rvae2_write(CPUARMState *env, - const ARMCPRegInfo *ri, - uint64_t value) -{ - /* - * Invalidate by VA range, EL2. - * Currently handles all of RVAE2 and RVALE2, - * since we don't support flush-for-specific-ASID-only or - * flush-last-level-only. - */ - - do_rvae_write(env, value, vae2_tlbmask(env), - tlb_force_broadcast(env)); - - -} - -static void tlbi_aa64_rvae2is_write(CPUARMState *env, - const ARMCPRegInfo *ri, - uint64_t value) -{ - /* - * Invalidate by VA range, Inner/Outer Shareable, EL2. - * Currently handles all of RVAE2IS, RVAE2OS, RVALE2IS and RVALE2OS, - * since we don't support flush-for-specific-ASID-only, - * flush-last-level-only or inner/outer shareable specific flushes. - */ - - do_rvae_write(env, value, vae2_tlbmask(env), true); - -} - -static void tlbi_aa64_rvae3_write(CPUARMState *env, - const ARMCPRegInfo *ri, - uint64_t value) -{ - /* - * Invalidate by VA range, EL3. - * Currently handles all of RVAE3 and RVALE3, - * since we don't support flush-for-specific-ASID-only or - * flush-last-level-only. - */ - - do_rvae_write(env, value, ARMMMUIdxBit_SE3, - tlb_force_broadcast(env)); -} - -static void tlbi_aa64_rvae3is_write(CPUARMState *env, - const ARMCPRegInfo *ri, - uint64_t value) -{ - /* - * Invalidate by VA range, EL3, Inner/Outer Shareable. - * Currently handles all of RVAE3IS, RVAE3OS, RVALE3IS and RVALE3OS, - * since we don't support flush-for-specific-ASID-only, - * flush-last-level-only or inner/outer specific flushes. - */ - - do_rvae_write(env, value, ARMMMUIdxBit_SE3, true); -} -#endif - -static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo= *ri, - bool isread) -{ - int cur_el =3D arm_current_el(env); - - if (cur_el < 2) { - uint64_t hcr =3D arm_hcr_el2_eff(env); - - if (cur_el =3D=3D 0) { - if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { - if (!(env->cp15.sctlr_el[2] & SCTLR_DZE)) { - return CP_ACCESS_TRAP_EL2; - } - } else { - if (!(env->cp15.sctlr_el[1] & SCTLR_DZE)) { - return CP_ACCESS_TRAP; - } - if (hcr & HCR_TDZ) { - return CP_ACCESS_TRAP_EL2; - } - } - } else if (hcr & HCR_TDZ) { - return CP_ACCESS_TRAP_EL2; - } - } - return CP_ACCESS_OK; -} - -static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - ARMCPU *cpu =3D env_archcpu(env); - int dzp_bit =3D 1 << 4; - - /* DZP indicates whether DC ZVA access is allowed */ - if (aa64_zva_access(env, NULL, false) =3D=3D CP_ACCESS_OK) { - dzp_bit =3D 0; - } - return cpu->dcz_blocksize | dzp_bit; -} - -static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *= ri, - bool isread) -{ - if (!(env->pstate & PSTATE_SP)) { - /* - * Access to SP_EL0 is undefined if it's being used as - * the stack pointer. - */ - return CP_ACCESS_TRAP_UNCATEGORIZED; - } - return CP_ACCESS_OK; -} - -static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return env->pstate & PSTATE_SP; -} - -static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t= val) -{ - update_spsel(env, val); -} - -static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - - if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { - /* M bit is RAZ/WI for PMSA with no MPU implemented */ - value &=3D ~SCTLR_M; - } - - /* ??? Lots of these bits are not implemented. */ - - if (ri->state =3D=3D ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, = cpu)) { - if (ri->opc1 =3D=3D 6) { /* SCTLR_EL3 */ - value &=3D ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); - } else { - value &=3D ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | - SCTLR_ATA0 | SCTLR_ATA); - } - } - - if (raw_read(env, ri) =3D=3D value) { - /* - * Skip the TLB flush if nothing actually changed; Linux likes - * to do a lot of pointless SCTLR writes. - */ - return; - } - - raw_write(env, ri, value); - - /* This may enable/disable the MMU, so do a TLB flush. */ - tlb_flush(CPU(cpu)); - - if (ri->type & ARM_CP_SUPPRESS_TB_END) { - /* - * Normally we would always end the TB on an SCTLR write; see the - * comment in ARMCPRegInfo sctlr initialization below for why Xsca= le - * is special. Setting ARM_CP_SUPPRESS_TB_END also stops the rebu= ild - * of hflags from the translator, so do it here. - */ - arm_rebuild_hflags(env); - } -} - -static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo = *ri, - bool isread) -{ - if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) =3D=3D 2)= { - return CP_ACCESS_TRAP_FP_EL2; - } - if (env->cp15.cptr_el[3] & CPTR_TFP) { - return CP_ACCESS_TRAP_FP_EL3; - } - return CP_ACCESS_OK; -} - -static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - env->cp15.mdcr_el3 =3D value & SDCR_VALID_MASK; -} - -static const ARMCPRegInfo v8_cp_reginfo[] =3D { - /* - * Minimal set of EL0-visible registers. This will need to be expanded - * significantly for system emulation of AArch64 CPUs. - */ - { .name =3D "NZCV", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 0, .crn =3D 4, .crm =3D 2, - .access =3D PL0_RW, .type =3D ARM_CP_NZCV }, - { .name =3D "DAIF", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 4, .crm =3D 2, - .type =3D ARM_CP_NO_RAW, - .access =3D PL0_RW, .accessfn =3D aa64_daif_access, - .fieldoffset =3D offsetof(CPUARMState, daif), - .writefn =3D aa64_daif_write, .resetfn =3D arm_cp_reset_ignore }, - { .name =3D "FPCR", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 0, .crn =3D 4, .crm =3D 4, - .access =3D PL0_RW, .type =3D ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, - .readfn =3D aa64_fpcr_read, .writefn =3D aa64_fpcr_write }, - { .name =3D "FPSR", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 4, .crm =3D 4, - .access =3D PL0_RW, .type =3D ARM_CP_FPU | ARM_CP_SUPPRESS_TB_END, - .readfn =3D aa64_fpsr_read, .writefn =3D aa64_fpsr_write }, - { .name =3D "DCZID_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 7, .crn =3D 0, .crm =3D 0, - .access =3D PL0_R, .type =3D ARM_CP_NO_RAW, - .readfn =3D aa64_dczid_read }, - { .name =3D "DC_ZVA", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 1, - .access =3D PL0_W, .type =3D ARM_CP_DC_ZVA, -#ifndef CONFIG_USER_ONLY - /* Avoid overhead of an access check that always passes in user-mode= */ - .accessfn =3D aa64_zva_access, -#endif - }, - { .name =3D "CURRENTEL", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 2, .crn =3D 4, .crm =3D 2, - .access =3D PL1_R, .type =3D ARM_CP_CURRENTEL }, - /* Cache ops: all NOPs since we don't emulate caches */ - { .name =3D "IC_IALLUIS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_pou_access }, - { .name =3D "IC_IALLU", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 5, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_pou_access }, - { .name =3D "IC_IVAU", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 5, .opc2 =3D 1, - .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_pou_access }, - { .name =3D "DC_IVAC", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 1, - .access =3D PL1_W, .accessfn =3D aa64_cacheop_poc_access, - .type =3D ARM_CP_NOP }, - { .name =3D "DC_ISW", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 2, - .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, - { .name =3D "DC_CVAC", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 1, - .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_poc_access }, - { .name =3D "DC_CSW", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 2, - .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, - { .name =3D "DC_CVAU", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 11, .opc2 =3D 1, - .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_pou_access }, - { .name =3D "DC_CIVAC", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, - .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_poc_access }, - { .name =3D "DC_CISW", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 2, - .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, - /* TLBI operations */ - { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_vmalle1is_write }, - { .name =3D "TLBI_VAE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_ASIDE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 2, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_vmalle1is_write }, - { .name =3D "TLBI_VAAE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 3, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_VALE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_VAALE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 7, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_vae1is_write }, - { .name =3D "TLBI_VMALLE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_vmalle1_write }, - { .name =3D "TLBI_VAE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_vae1_write }, - { .name =3D "TLBI_ASIDE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 2, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_vmalle1_write }, - { .name =3D "TLBI_VAAE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 3, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_vae1_write }, - { .name =3D "TLBI_VALE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_vae1_write }, - { .name =3D "TLBI_VAALE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 7, - .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, - .writefn =3D tlbi_aa64_vae1_write }, - { .name =3D "TLBI_IPAS2E1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_IPAS2LE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_ALLE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 4, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, - { .name =3D "TLBI_VMALLS12E1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 6, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, - { .name =3D "TLBI_IPAS2E1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_IPAS2LE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_ALLE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 4, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1_write }, - { .name =3D "TLBI_VMALLS12E1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 6, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, -#ifndef CONFIG_USER_ONLY - /* 64 bit address translation operations */ - { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn =3D ats_write64 }, - { .name =3D "AT_S1E1W", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn =3D ats_write64 }, - { .name =3D "AT_S1E0R", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn =3D ats_write64 }, - { .name =3D "AT_S1E0W", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 3, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn =3D ats_write64 }, - { .name =3D "AT_S12E1R", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 4, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn =3D ats_write64 }, - { .name =3D "AT_S12E1W", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn =3D ats_write64 }, - { .name =3D "AT_S12E0R", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 6, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn =3D ats_write64 }, - { .name =3D "AT_S12E0W", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 7, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn =3D ats_write64 }, - /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present= */ - { .name =3D "AT_S1E3R", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn =3D ats_write64 }, - { .name =3D "AT_S1E3W", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn =3D ats_write64 }, - { .name =3D "PAR_EL1", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 7, .crm =3D 4, .opc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.par_el[1]), - .writefn =3D par_write }, -#endif - /* TLB invalidate last level of translation table walk */ - { .name =3D "TLBIMVALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 5, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimva_is_write }, - { .name =3D "TLBIMVAALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 7, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimvaa_is_write }, - { .name =3D "TLBIMVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 5, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimva_write }, - { .name =3D "TLBIMVAAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 7, .opc2 =3D 7, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, - .writefn =3D tlbimvaa_write }, - { .name =3D "TLBIMVALH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D= 7, .opc2 =3D 5, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbimva_hyp_write }, - { .name =3D "TLBIMVALHIS", - .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbimva_hyp_is_write }, - { .name =3D "TLBIIPAS2", - .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL2_W }, - { .name =3D "TLBIIPAS2IS", - .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL2_W }, - { .name =3D "TLBIIPAS2L", - .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 5, - .type =3D ARM_CP_NOP, .access =3D PL2_W }, - { .name =3D "TLBIIPAS2LIS", - .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 5, - .type =3D ARM_CP_NOP, .access =3D PL2_W }, - /* 32 bit cache operations */ - { .name =3D "ICIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 0, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, - { .name =3D "BPIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 6, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, - { .name =3D "ICIALLU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5= , .opc2 =3D 0, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, - { .name =3D "ICIMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5= , .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, - { .name =3D "BPIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 6, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, - { .name =3D "BPIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 7, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, - { .name =3D "DCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6= , .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, - { .name =3D "DCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, = .opc2 =3D 2, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, - { .name =3D "DCCMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 0, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, - { .name =3D "DCCSW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 10,= .opc2 =3D 2, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, - { .name =3D "DCCMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 1, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, - { .name =3D "DCCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D = 14, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, - { .name =3D "DCCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 14= , .opc2 =3D 2, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, - /* MMU Domain access control / MPU write buffer control */ - { .name =3D "DACR", .cp =3D 15, .opc1 =3D 0, .crn =3D 3, .crm =3D 0, .= opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, - .writefn =3D dacr_write, .raw_writefn =3D raw_write, - .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.dacr_s), - offsetoflow32(CPUARMState, cp15.dacr_ns) } }, - { .name =3D "ELR_EL1", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, elr_el[1]) }, - { .name =3D "SPSR_EL1", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, - /* - * We rely on the access checks not allowing the guest to write to the - * state field when SPSel indicates that it's being used as the stack - * pointer. - */ - { .name =3D "SP_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D sp_el0_access, - .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, sp_el[0]) }, - { .name =3D "SP_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, sp_el[1]) }, - { .name =3D "SPSel", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 2, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, - .access =3D PL1_RW, .readfn =3D spsel_read, .writefn =3D spsel_write= }, - { .name =3D "FPEXC32_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, - .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), - .access =3D PL2_RW, .accessfn =3D fpexc32_access }, - { .name =3D "DACR32_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .resetvalue =3D 0, - .writefn =3D dacr_write, .raw_writefn =3D raw_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.dacr32_el2) }, - { .name =3D "IFSR32_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.ifsr32_el2) }, - { .name =3D "SPSR_IRQ", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_IRQ]) }, - { .name =3D "SPSR_ABT", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 1, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_ABT]) }, - { .name =3D "SPSR_UND", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 2, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_UND]) }, - { .name =3D "SPSR_FIQ", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 3, .opc2 =3D 3, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_FIQ]) }, - { .name =3D "MDCR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 3, .opc2 =3D 1, - .resetvalue =3D 0, - .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr= _el3) }, - { .name =3D "SDCR", .type =3D ARM_CP_ALIAS, - .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, - .writefn =3D sdcr_write, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.mdcr_el3) }, - REGINFO_SENTINEL -}; - -/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ -static const ARMCPRegInfo el3_no_el2_cp_reginfo[] =3D { - { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, - .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }, - { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HACR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 7, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "ESR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPTR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "MAIR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "AMAIR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "HAMAIR1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR0_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR1_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "VTTBR", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 6, .crm =3D 2, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetvalue =3D 0 }, - { .name =3D "VTTBR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "SCTLR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "TPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "CNTHCTL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTVOFF_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 0, .opc2 =3D 3, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTVOFF", .cp =3D 15, .opc1 =3D 4, .crm =3D 14, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "CNTHP_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTHP_CVAL", .cp =3D 15, .opc1 =3D 6, .crm =3D 14, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "CNTHP_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTHP_CTL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HPFAR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HSTR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 3, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "FAR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HIFAR", .state =3D ARM_CP_STATE_AA32, - .type =3D ARM_CP_CONST, - .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -/* Ditto, but for registers which exist in ARMv8 but not v7 */ -static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] =3D { - { .name =3D "HCR2", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, - .access =3D PL2_RW, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_= mask) -{ - ARMCPU *cpu =3D env_archcpu(env); - - if (arm_feature(env, ARM_FEATURE_V8)) { - valid_mask |=3D MAKE_64BIT_MASK(0, 34); /* ARMv8.0 */ - } else { - valid_mask |=3D MAKE_64BIT_MASK(0, 28); /* ARMv7VE */ - } - - if (arm_feature(env, ARM_FEATURE_EL3)) { - valid_mask &=3D ~HCR_HCD; - } else if (cpu->psci_conduit !=3D QEMU_PSCI_CONDUIT_SMC) { - /* - * Architecturally HCR.TSC is RES0 if EL3 is not implemented. - * However, if we're using the SMC PSCI conduit then QEMU is - * effectively acting like EL3 firmware and so the guest at - * EL2 should retain the ability to prevent EL1 from being - * able to make SMC calls into the ersatz firmware, so in - * that case HCR.TSC should be read/write. - */ - valid_mask &=3D ~HCR_TSC; - } - - if (arm_feature(env, ARM_FEATURE_AARCH64)) { - if (cpu_isar_feature(aa64_vh, cpu)) { - valid_mask |=3D HCR_E2H; - } - if (cpu_isar_feature(aa64_lor, cpu)) { - valid_mask |=3D HCR_TLOR; - } - if (cpu_isar_feature(aa64_pauth, cpu)) { - valid_mask |=3D HCR_API | HCR_APK; - } - if (cpu_isar_feature(aa64_mte, cpu)) { - valid_mask |=3D HCR_ATA | HCR_DCT | HCR_TID5; - } - } - - /* Clear RES0 bits. */ - value &=3D valid_mask; - - /* - * These bits change the MMU setup: - * HCR_VM enables stage 2 translation - * HCR_PTW forbids certain page-table setups - * HCR_DC disables stage1 and enables stage2 translation - * HCR_DCT enables tagging on (disabled) stage1 translation - */ - if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT= )) { - tlb_flush(CPU(cpu)); - } - env->cp15.hcr_el2 =3D value; - - /* - * Updates to VI and VF require us to update the status of - * virtual interrupts, which are the logical OR of these bits - * and the state of the input lines from the GIC. (This requires - * that we have the iothread lock, which is done by marking the - * reginfo structs as ARM_CP_IO.) - * Note that if a write to HCR pends a VIRQ or VFIQ it is never - * possible for it to be taken immediately, because VIRQ and - * VFIQ are masked unless running at EL0 or EL1, and HCR - * can only be written at EL2. - */ - g_assert(qemu_mutex_iothread_locked()); - arm_cpu_update_virq(cpu); - arm_cpu_update_vfiq(cpu); -} - -static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) -{ - do_hcr_write(env, value, 0); -} - -static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */ - value =3D deposit64(env->cp15.hcr_el2, 32, 32, value); - do_hcr_write(env, value, MAKE_64BIT_MASK(0, 32)); -} - -static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Handle HCR write, i.e. write to low half of HCR_EL2 */ - value =3D deposit64(env->cp15.hcr_el2, 0, 32, value); - do_hcr_write(env, value, MAKE_64BIT_MASK(32, 32)); -} - -/* - * Return the effective value of HCR_EL2. - * Bits that are not included here: - * RW (read from SCR_EL3.RW as needed) - */ -uint64_t arm_hcr_el2_eff(CPUARMState *env) -{ - uint64_t ret =3D env->cp15.hcr_el2; - - if (!arm_is_el2_enabled(env)) { - /* - * "This register has no effect if EL2 is not enabled in the - * current Security state". This is ARMv8.4-SecEL2 speak for - * !(SCR_EL3.NS=3D=3D1 || SCR_EL3.EEL2=3D=3D1). - * - * Prior to that, the language was "In an implementation that - * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves - * as if this field is 0 for all purposes other than a direct - * read or write access of HCR_EL2". With lots of enumeration - * on a per-field basis. In current QEMU, this is condition - * is arm_is_secure_below_el3. - * - * Since the v8.4 language applies to the entire register, and - * appears to be backward compatible, use that. - */ - return 0; - } - - /* - * For a cpu that supports both aarch64 and aarch32, we can set bits - * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32. - * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32. - */ - if (!arm_el_is_aa64(env, 2)) { - uint64_t aa32_valid; - - /* - * These bits are up-to-date as of ARMv8.6. - * For HCR, it's easiest to list just the 2 bits that are invalid. - * For HCR2, list those that are valid. - */ - aa32_valid =3D MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ); - aa32_valid |=3D (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNC= E | - HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS); - ret &=3D aa32_valid; - } - - if (ret & HCR_TGE) { - /* These bits are up-to-date as of ARMv8.6. */ - if (ret & HCR_E2H) { - ret &=3D ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | - HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | - HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | - HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE | - HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT | - HCR_TTLBIS | HCR_TTLBOS | HCR_TID5); - } else { - ret |=3D HCR_FMO | HCR_IMO | HCR_AMO; - } - ret &=3D ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | - HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | - HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | - HCR_TLOR); - } - - return ret; -} - -static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* - * For A-profile AArch32 EL3, if NSACR.CP10 - * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. - */ - if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && - !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { - value &=3D ~(0x3 << 10); - value |=3D env->cp15.cptr_el[2] & (0x3 << 10); - } - env->cp15.cptr_el[2] =3D value; -} - -static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - /* - * For A-profile AArch32 EL3, if NSACR.CP10 - * is 0 then HCPTR.{TCP11,TCP10} ignore writes and read as 1. - */ - uint64_t value =3D env->cp15.cptr_el[2]; - - if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && - !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { - value |=3D 0x3 << 10; - } - return value; -} - -static const ARMCPRegInfo el2_cp_reginfo[] =3D { - { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_IO, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), - .writefn =3D hcr_write }, - { .name =3D "HCR", .state =3D ARM_CP_STATE_AA32, - .type =3D ARM_CP_ALIAS | ARM_CP_IO, - .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), - .writefn =3D hcr_writelow }, - { .name =3D "HACR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 7, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "ELR_EL2", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, elr_el[2]) }, - { .name =3D "ESR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.esr_= el[2]) }, - { .name =3D "FAR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.far_= el[2]) }, - { .name =3D "HIFAR", .state =3D ARM_CP_STATE_AA32, - .type =3D ARM_CP_ALIAS, - .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, - .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.far_el[2]) }, - { .name =3D "SPSR_EL2", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, - { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .writefn =3D vbar_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.vbar_el[2]), - .resetvalue =3D 0 }, - { .name =3D "SP_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 1, .opc2 =3D 0, - .access =3D PL3_RW, .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, sp_el[2]) }, - { .name =3D "CPTR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, - .access =3D PL2_RW, .accessfn =3D cptr_access, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.cptr_el[2]), - .readfn =3D cptr_el2_read, .writefn =3D cptr_el2_write }, - { .name =3D "MAIR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[2]), - .resetvalue =3D 0 }, - { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, - { .name =3D "AMAIR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ - { .name =3D "HAMAIR1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR0_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR1_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .writefn =3D vmsa_tcr_el12_write, - /* no .raw_writefn or .resetfn needed as we never use mask/base_mask= */ - .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[2]) }, - { .name =3D "VTCR", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, - .type =3D ARM_CP_ALIAS, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .fieldoffset =3D offsetof(CPUARMState, cp15.vtcr_el2) }, - { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, - .access =3D PL2_RW, - /* - * no .writefn needed as this can't cause an ASID change; - * no .raw_writefn or .resetfn needed as we never use mask/base_mask - */ - .fieldoffset =3D offsetof(CPUARMState, cp15.vtcr_el2) }, - { .name =3D "VTTBR", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 6, .crm =3D 2, - .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .fieldoffset =3D offsetof(CPUARMState, cp15.vttbr_el2), - .writefn =3D vttbr_write }, - { .name =3D "VTTBR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .writefn =3D vttbr_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.vttbr_el2) }, - { .name =3D "SCTLR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .raw_writefn =3D raw_write, .writefn =3D sctlr_w= rite, - .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr_el[2]) }, - { .name =3D "TPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[2]) }, - { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .resetvalue =3D 0, .writefn =3D vmsa_tcr_ttbr_el= 2_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) }, - { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[2]) }, - { .name =3D "TLBIALLNSNH", - .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 4, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiall_nsnh_write }, - { .name =3D "TLBIALLNSNHIS", - .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 4, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiall_nsnh_is_write }, - { .name =3D "TLBIALLH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D = 7, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiall_hyp_write }, - { .name =3D "TLBIALLHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm = =3D 3, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbiall_hyp_is_write }, - { .name =3D "TLBIMVAH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D = 7, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbimva_hyp_write }, - { .name =3D "TLBIMVAHIS", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm = =3D 3, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbimva_hyp_is_write }, - { .name =3D "TLBI_ALLE2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbi_aa64_alle2_write }, - { .name =3D "TLBI_VAE2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbi_aa64_vae2_write }, - { .name =3D "TLBI_VALE2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae2_write }, - { .name =3D "TLBI_ALLE2IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle2is_write }, - { .name =3D "TLBI_VAE2IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, - .writefn =3D tlbi_aa64_vae2is_write }, - { .name =3D "TLBI_VALE2IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae2is_write }, -#ifndef CONFIG_USER_ONLY - /* - * Unlike the other EL2-related AT operations, these must - * UNDEF from EL3 if EL2 is not implemented, which is why we - * define them here rather than with the rest of the AT ops. - */ - { .name =3D "AT_S1E2R", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, - .access =3D PL2_W, .accessfn =3D at_s1e2_access, - .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write6= 4 }, - { .name =3D "AT_S1E2W", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, - .access =3D PL2_W, .accessfn =3D at_s1e2_access, - .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write6= 4 }, - /* - * The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE - * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 - * with SCR.NS =3D=3D 0 outside Monitor mode is UNPREDICTABLE; we choo= se - * to behave as if SCR.NS was 1. - */ - { .name =3D "ATS1HR", .cp =3D 15, .opc1 =3D 4, .crn =3D 7, .crm =3D 8,= .opc2 =3D 0, - .access =3D PL2_W, - .writefn =3D ats1h_write, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EX= C }, - { .name =3D "ATS1HW", .cp =3D 15, .opc1 =3D 4, .crn =3D 7, .crm =3D 8,= .opc2 =3D 1, - .access =3D PL2_W, - .writefn =3D ats1h_write, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EX= C }, - { .name =3D "CNTHCTL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, - /* - * ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the - * reset values as IMPDEF. We choose to reset to 3 to comply with - * both ARMv7 and ARMv8. - */ - .access =3D PL2_RW, .resetvalue =3D 3, - .fieldoffset =3D offsetof(CPUARMState, cp15.cnthctl_el2) }, - { .name =3D "CNTVOFF_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 0, .opc2 =3D 3, - .access =3D PL2_RW, .type =3D ARM_CP_IO, .resetvalue =3D 0, - .writefn =3D gt_cntvoff_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.cntvoff_el2) }, - { .name =3D "CNTVOFF", .cp =3D 15, .opc1 =3D 4, .crm =3D 14, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_I= O, - .writefn =3D gt_cntvoff_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.cntvoff_el2) }, - { .name =3D "CNTHP_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cv= al), - .type =3D ARM_CP_IO, .access =3D PL2_RW, - .writefn =3D gt_hyp_cval_write, .raw_writefn =3D raw_write }, - { .name =3D "CNTHP_CVAL", .cp =3D 15, .opc1 =3D 6, .crm =3D 14, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cv= al), - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_IO, - .writefn =3D gt_hyp_cval_write, .raw_writefn =3D raw_write }, - { .name =3D "CNTHP_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL2_RW, - .resetfn =3D gt_hyp_timer_reset, - .readfn =3D gt_hyp_tval_read, .writefn =3D gt_hyp_tval_write }, - { .name =3D "CNTHP_CTL_EL2", .state =3D ARM_CP_STATE_BOTH, - .type =3D ARM_CP_IO, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ct= l), - .resetvalue =3D 0, - .writefn =3D gt_hyp_ctl_write, .raw_writefn =3D raw_write }, -#endif - /* The only field of MDCR_EL2 that has a defined architectural reset v= alue - * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N. - */ - { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .resetvalue =3D PMCR_NUM_COUNTERS, - .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr_el2), }, - { .name =3D "HPFAR", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .fieldoffset =3D offsetof(CPUARMState, cp15.hpfar_el2) }, - { .name =3D "HPFAR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.hpfar_el2) }, - { .name =3D "HSTR_EL2", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 15, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 = =3D 3, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.hstr_el2) }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo el2_v8_cp_reginfo[] =3D { - { .name =3D "HCR2", .state =3D ARM_CP_STATE_AA32, - .type =3D ARM_CP_ALIAS | ARM_CP_IO, - .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, - .access =3D PL2_RW, - .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.hcr_el2), - .writefn =3D hcr_writehigh }, - REGINFO_SENTINEL -}; - -static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - if (arm_current_el(env) =3D=3D 3 || arm_is_secure_below_el3(env)) { - return CP_ACCESS_OK; - } - return CP_ACCESS_TRAP_UNCATEGORIZED; -} - -static const ARMCPRegInfo el2_sec_cp_reginfo[] =3D { - { .name =3D "VSTTBR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 6, .opc2 =3D 0, - .access =3D PL2_RW, .accessfn =3D sel2_access, - .fieldoffset =3D offsetof(CPUARMState, cp15.vsttbr_el2) }, - { .name =3D "VSTCR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 6, .opc2 =3D 2, - .access =3D PL2_RW, .accessfn =3D sel2_access, - .fieldoffset =3D offsetof(CPUARMState, cp15.vstcr_el2) }, - REGINFO_SENTINEL -}; - -static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *r= i, - bool isread) -{ - /* - * The NSACR is RW at EL3, and RO for NS EL1 and NS EL2. - * At Secure EL1 it traps to EL3 or EL2. - */ - if (arm_current_el(env) =3D=3D 3) { - return CP_ACCESS_OK; - } - if (arm_is_secure_below_el3(env)) { - if (env->cp15.scr_el3 & SCR_EEL2) { - return CP_ACCESS_TRAP_EL2; - } - return CP_ACCESS_TRAP_EL3; - } - /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads= . */ - if (isread) { - return CP_ACCESS_OK; - } - return CP_ACCESS_TRAP_UNCATEGORIZED; -} - -static const ARMCPRegInfo el3_cp_reginfo[] =3D { - { .name =3D "SCR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, - .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.scr_= el3), - .resetfn =3D scr_reset, .writefn =3D scr_write }, - { .name =3D "SCR", .type =3D ARM_CP_ALIAS | ARM_CP_NEWEL, - .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.scr_el3), - .writefn =3D scr_write }, - { .name =3D "SDER32_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, - .access =3D PL3_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.sder) }, - { .name =3D "SDER", - .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, - .access =3D PL3_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.sder) }, - { .name =3D "MVBAR", .cp =3D 15, .opc1 =3D 0, .crn =3D 12, .crm =3D 0,= .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, - .writefn =3D vbar_write, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.mvbar) }, - { .name =3D "TTBR0_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL3_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr0_el[3]) }, - { .name =3D "TCR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, - .access =3D PL3_RW, - /* - * no .writefn needed as this can't cause an ASID change; - * we must provide a .raw_writefn and .resetfn because we handle - * reset and migration for the AArch32 TTBCR(S), which might be - * using mask and base_mask. - */ - .resetfn =3D vmsa_ttbcr_reset, .raw_writefn =3D vmsa_ttbcr_raw_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.tcr_el[3]) }, - { .name =3D "ELR_EL3", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, - .access =3D PL3_RW, - .fieldoffset =3D offsetof(CPUARMState, elr_el[3]) }, - { .name =3D "ESR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, - .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.esr_= el[3]) }, - { .name =3D "FAR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 6, .crm =3D 0, .opc2 =3D 0, - .access =3D PL3_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.far_= el[3]) }, - { .name =3D "SPSR_EL3", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_ALIAS, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, - .access =3D PL3_RW, - .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_MON]) }, - { .name =3D "VBAR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, - .access =3D PL3_RW, .writefn =3D vbar_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.vbar_el[3]), - .resetvalue =3D 0 }, - { .name =3D "CPTR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, - .access =3D PL3_RW, .accessfn =3D cptr_access, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.cptr_el[3]) }, - { .name =3D "TPIDR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 13, .crm =3D 0, .opc2 =3D 2, - .access =3D PL3_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.tpidr_el[3]) }, - { .name =3D "AMAIR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, - .access =3D PL3_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR0_EL3", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, - .access =3D PL3_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR1_EL3", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, - .access =3D PL3_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "TLBI_ALLE3IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle3is_write }, - { .name =3D "TLBI_VAE3IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3is_write }, - { .name =3D "TLBI_VALE3IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3is_write }, - { .name =3D "TLBI_ALLE3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle3_write }, - { .name =3D "TLBI_VAE3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3_write }, - { .name =3D "TLBI_VALE3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vae3_write }, - REGINFO_SENTINEL -}; - -#ifndef CONFIG_USER_ONLY -/* Test if system register redirection is to occur in the current state. = */ -static bool redirect_for_e2h(CPUARMState *env) -{ - return arm_current_el(env) =3D=3D 2 && (arm_hcr_el2_eff(env) & HCR_E2H= ); -} - -static uint64_t el2_e2h_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - CPReadFn *readfn; - - if (redirect_for_e2h(env)) { - /* Switch to the saved EL2 version of the register. */ - ri =3D ri->opaque; - readfn =3D ri->readfn; - } else { - readfn =3D ri->orig_readfn; - } - if (readfn =3D=3D NULL) { - readfn =3D raw_read; - } - return readfn(env, ri); -} - -static void el2_e2h_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - CPWriteFn *writefn; - - if (redirect_for_e2h(env)) { - /* Switch to the saved EL2 version of the register. */ - ri =3D ri->opaque; - writefn =3D ri->writefn; - } else { - writefn =3D ri->orig_writefn; - } - if (writefn =3D=3D NULL) { - writefn =3D raw_write; - } - writefn(env, ri, value); -} - -static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) -{ - struct E2HAlias { - uint32_t src_key, dst_key, new_key; - const char *src_name, *dst_name, *new_name; - bool (*feature)(const ARMISARegisters *id); - }; - -#define K(op0, op1, crn, crm, op2) \ - ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2) - - static const struct E2HAlias aliases[] =3D { - { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), - "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, - { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), - "CPACR", "CPTR_EL2", "CPACR_EL12" }, - { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), - "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, - { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), - "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, - { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), - "TCR_EL1", "TCR_EL2", "TCR_EL12" }, - { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), - "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, - { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), - "ELR_EL1", "ELR_EL2", "ELR_EL12" }, - { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0), - "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" }, - { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1), - "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" }, - { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0), - "ESR_EL1", "ESR_EL2", "ESR_EL12" }, - { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0), - "FAR_EL1", "FAR_EL2", "FAR_EL12" }, - { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), - "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, - { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), - "AMAIR0", "AMAIR_EL2", "AMAIR_EL12" }, - { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), - "VBAR", "VBAR_EL2", "VBAR_EL12" }, - { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), - "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, - { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), - "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" }, - - /* - * Note that redirection of ZCR is mentioned in the description - * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but - * not in the summary table. - */ - { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), - "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, - - { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), - "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, - - /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ - /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ - }; -#undef K - - size_t i; - - for (i =3D 0; i < ARRAY_SIZE(aliases); i++) { - const struct E2HAlias *a =3D &aliases[i]; - ARMCPRegInfo *src_reg, *dst_reg; - - if (a->feature && !a->feature(&cpu->isar)) { - continue; - } - - src_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->src_key); - dst_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->dst_key); - g_assert(src_reg !=3D NULL); - g_assert(dst_reg !=3D NULL); - - /* Cross-compare names to detect typos in the keys. */ - g_assert(strcmp(src_reg->name, a->src_name) =3D=3D 0); - g_assert(strcmp(dst_reg->name, a->dst_name) =3D=3D 0); - - /* None of the core system registers use opaque; we will. */ - g_assert(src_reg->opaque =3D=3D NULL); - - /* Create alias before redirection so we dup the right data. */ - if (a->new_key) { - ARMCPRegInfo *new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInf= o)); - uint32_t *new_key =3D g_memdup(&a->new_key, sizeof(uint32_t)); - bool ok; - - new_reg->name =3D a->new_name; - new_reg->type |=3D ARM_CP_ALIAS; - /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ - new_reg->access &=3D PL2_RW | PL3_RW; - - ok =3D g_hash_table_insert(cpu->cp_regs, new_key, new_reg); - g_assert(ok); - } - - src_reg->opaque =3D dst_reg; - src_reg->orig_readfn =3D src_reg->readfn ?: raw_read; - src_reg->orig_writefn =3D src_reg->writefn ?: raw_write; - if (!src_reg->raw_readfn) { - src_reg->raw_readfn =3D raw_read; - } - if (!src_reg->raw_writefn) { - src_reg->raw_writefn =3D raw_write; - } - src_reg->readfn =3D el2_e2h_read; - src_reg->writefn =3D el2_e2h_write; - } -} -#endif - -static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo = *ri, - bool isread) -{ - int cur_el =3D arm_current_el(env); - - if (cur_el < 2) { - uint64_t hcr =3D arm_hcr_el2_eff(env); - - if (cur_el =3D=3D 0) { - if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { - if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) { - return CP_ACCESS_TRAP_EL2; - } - } else { - if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) { - return CP_ACCESS_TRAP; - } - if (hcr & HCR_TID2) { - return CP_ACCESS_TRAP_EL2; - } - } - } else if (hcr & HCR_TID2) { - return CP_ACCESS_TRAP_EL2; - } - } - - if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) { - return CP_ACCESS_TRAP_EL2; - } - - return CP_ACCESS_OK; -} - -static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* - * Writes to OSLAR_EL1 may update the OS lock status, which can be - * read via a bit in OSLSR_EL1. - */ - int oslock; - - if (ri->state =3D=3D ARM_CP_STATE_AA32) { - oslock =3D (value =3D=3D 0xC5ACCE55); - } else { - oslock =3D value & 1; - } - - env->cp15.oslsr_el1 =3D deposit32(env->cp15.oslsr_el1, 1, 1, oslock); -} - -static const ARMCPRegInfo debug_cp_reginfo[] =3D { - /* - * DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped - * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1; - * unlike DBGDRAR it is never accessible from EL0. - * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AAr= ch64 - * accessor. - */ - { .name =3D "DBGDRAR", .cp =3D 14, .crn =3D 1, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, - .access =3D PL0_R, .accessfn =3D access_tdra, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "MDRAR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_R, .accessfn =3D access_tdra, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "DBGDSAR", .cp =3D 14, .crn =3D 2, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, - .access =3D PL0_R, .accessfn =3D access_tdra, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* Monitor debug system control register; the 32-bit alias is DBGDSCRe= xt. */ - { .name =3D "MDSCR_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 2, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), - .resetvalue =3D 0 }, - /* - * MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1. - * We don't implement the configurable EL0 access. - */ - { .name =3D "MDCCSR_EL0", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 = =3D 0, - .type =3D ARM_CP_ALIAS, - .access =3D PL1_R, .accessfn =3D access_tda, - .fieldoffset =3D offsetof(CPUARMState, cp15.mdscr_el1), }, - { .name =3D "OSLAR_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 = =3D 4, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .accessfn =3D access_tdosa, - .writefn =3D oslar_write }, - { .name =3D "OSLSR_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 = =3D 4, - .access =3D PL1_R, .resetvalue =3D 10, - .accessfn =3D access_tdosa, - .fieldoffset =3D offsetof(CPUARMState, cp15.oslsr_el1) }, - /* Dummy OSDLR_EL1: 32-bit Linux will read this */ - { .name =3D "OSDLR_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 1, .crm =3D 3, .opc2 = =3D 4, - .access =3D PL1_RW, .accessfn =3D access_tdosa, - .type =3D ARM_CP_NOP }, - /* - * Dummy DBGVCR: Linux wants to clear this on startup, but we don't - * implement vector catch debug events yet. - */ - { .name =3D "DBGVCR", - .cp =3D 14, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_NOP }, - /* - * Dummy DBGVCR32_EL2 (which is only for a 64-bit hypervisor - * to save and restore a 32-bit guest's DBGVCR) - */ - { .name =3D "DBGVCR32_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 2, .opc1 =3D 4, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, - .access =3D PL2_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_NOP }, - /* - * Dummy MDCCINT_EL1, since we don't implement the Debug Communications - * Channel but Linux may try to access this register. The 32-bit - * alias is DBGDCCINT. - */ - { .name =3D "MDCCINT_EL1", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D { - /* 64 bit access versions of the (dummy) debug registers */ - { .name =3D "DBGDRAR", .cp =3D 14, .crm =3D 1, .opc1 =3D 0, - .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, - { .name =3D "DBGDSAR", .cp =3D 14, .crm =3D 2, .opc1 =3D 0, - .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, - REGINFO_SENTINEL -}; - -/* Return the exception level to which exceptions should be taken - * via SVEAccessTrap. If an exception should be routed through - * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should - * take care of raising that exception. - * C.f. the ARM pseudocode function CheckSVEEnabled. - */ -int sve_exception_el(CPUARMState *env, int el) -{ -#ifndef CONFIG_USER_ONLY - uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); - - if (el <=3D 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { - bool disabled =3D false; - - /* The CPACR.ZEN controls traps to EL1: - * 0, 2 : trap EL0 and EL1 accesses - * 1 : trap only EL0 accesses - * 3 : trap no accesses - */ - if (!extract32(env->cp15.cpacr_el1, 16, 1)) { - disabled =3D true; - } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) { - disabled =3D el =3D=3D 0; - } - if (disabled) { - /* route_to_el2 */ - return hcr_el2 & HCR_TGE ? 2 : 1; - } - - /* Check CPACR.FPEN. */ - if (!extract32(env->cp15.cpacr_el1, 20, 1)) { - disabled =3D true; - } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) { - disabled =3D el =3D=3D 0; - } - if (disabled) { - return 0; - } - } - - /* CPTR_EL2. Since TZ and TFP are positive, - * they will be zero when EL2 is not present. - */ - if (el <=3D 2 && arm_is_el2_enabled(env)) { - if (env->cp15.cptr_el[2] & CPTR_TZ) { - return 2; - } - if (env->cp15.cptr_el[2] & CPTR_TFP) { - return 0; - } - } - - /* CPTR_EL3. Since EZ is negative we must check for EL3. */ - if (arm_feature(env, ARM_FEATURE_EL3) - && !(env->cp15.cptr_el[3] & CPTR_EZ)) { - return 3; - } -#endif - return 0; -} - -static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) -{ - uint32_t end_len; - - end_len =3D start_len &=3D 0xf; - if (!test_bit(start_len, cpu->sve_vq_map)) { - end_len =3D find_last_bit(cpu->sve_vq_map, start_len); - assert(end_len < start_len); - } - return end_len; -} - -/* - * Given that SVE is enabled, return the vector length for EL. - */ -uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) -{ - ARMCPU *cpu =3D env_archcpu(env); - uint32_t zcr_len =3D cpu->sve_max_vq - 1; - - if (el <=3D 1) { - zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); - } - if (el <=3D 2 && arm_feature(env, ARM_FEATURE_EL2)) { - zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); - } - if (arm_feature(env, ARM_FEATURE_EL3)) { - zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); - } - - return sve_zcr_get_valid_len(cpu, zcr_len); -} - -static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - int cur_el =3D arm_current_el(env); - int old_len =3D sve_zcr_len_for_el(env, cur_el); - int new_len; - - /* Bits other than [3:0] are RAZ/WI. */ - QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16); - raw_write(env, ri, value & 0xf); - - /* - * Because we arrived here, we know both FP and SVE are enabled; - * otherwise we would have trapped access to the ZCR_ELn register. - */ - new_len =3D sve_zcr_len_for_el(env, cur_el); - if (new_len < old_len) { - aarch64_sve_narrow_vq(env, new_len + 1); - } -} - -static const ARMCPRegInfo zcr_el1_reginfo =3D { - .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_SVE, - .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), - .writefn =3D zcr_write, .raw_writefn =3D raw_write -}; - -static const ARMCPRegInfo zcr_el2_reginfo =3D { - .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_SVE, - .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), - .writefn =3D zcr_write, .raw_writefn =3D raw_write -}; - -static const ARMCPRegInfo zcr_no_el2_reginfo =3D { - .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_SVE, - .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore -}; - -static const ARMCPRegInfo zcr_el3_reginfo =3D { - .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL3_RW, .type =3D ARM_CP_SVE, - .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), - .writefn =3D zcr_write, .raw_writefn =3D raw_write -}; - -void hw_watchpoint_update(ARMCPU *cpu, int n) -{ - CPUARMState *env =3D &cpu->env; - vaddr len =3D 0; - vaddr wvr =3D env->cp15.dbgwvr[n]; - uint64_t wcr =3D env->cp15.dbgwcr[n]; - int mask; - int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; - - if (env->cpu_watchpoint[n]) { - cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]); - env->cpu_watchpoint[n] =3D NULL; - } - - if (!extract64(wcr, 0, 1)) { - /* E bit clear : watchpoint disabled */ - return; - } - - switch (extract64(wcr, 3, 2)) { - case 0: - /* LSC 00 is reserved and must behave as if the wp is disabled */ - return; - case 1: - flags |=3D BP_MEM_READ; - break; - case 2: - flags |=3D BP_MEM_WRITE; - break; - case 3: - flags |=3D BP_MEM_ACCESS; - break; - } - - /* Attempts to use both MASK and BAS fields simultaneously are - * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, - * thus generating a watchpoint for every byte in the masked region. - */ - mask =3D extract64(wcr, 24, 4); - if (mask =3D=3D 1 || mask =3D=3D 2) { - /* Reserved values of MASK; we must act as if the mask value was - * some non-reserved value, or as if the watchpoint were disabled. - * We choose the latter. - */ - return; - } else if (mask) { - /* Watchpoint covers an aligned area up to 2GB in size */ - len =3D 1ULL << mask; - /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTAB= LE - * whether the watchpoint fires when the unmasked bits match; we o= pt - * to generate the exceptions. - */ - wvr &=3D ~(len - 1); - } else { - /* Watchpoint covers bytes defined by the byte address select bits= */ - int bas =3D extract64(wcr, 5, 8); - int basstart; - - if (extract64(wvr, 2, 1)) { - /* Deprecated case of an only 4-aligned address. BAS[7:4] are - * ignored, and BAS[3:0] define which bytes to watch. - */ - bas &=3D 0xf; - } - - if (bas =3D=3D 0) { - /* This must act as if the watchpoint is disabled */ - return; - } - - /* The BAS bits are supposed to be programmed to indicate a contig= uous - * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE wheth= er - * we fire for each byte in the word/doubleword addressed by the W= VR. - * We choose to ignore any non-zero bits after the first range of = 1s. - */ - basstart =3D ctz32(bas); - len =3D cto32(bas >> basstart); - wvr +=3D basstart; - } - - cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, - &env->cpu_watchpoint[n]); -} - -void hw_watchpoint_update_all(ARMCPU *cpu) -{ - int i; - CPUARMState *env =3D &cpu->env; - - /* Completely clear out existing QEMU watchpoints and our array, to - * avoid possible stale entries following migration load. - */ - cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); - memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); - - for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { - hw_watchpoint_update(cpu, i); - } -} - -static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - int i =3D ri->crm; - - /* - * Bits [63:49] are hardwired to the value of bit [48]; that is, the - * register reads and behaves as if values written are sign extended. - * Bits [1:0] are RES0. - */ - value =3D sextract64(value, 0, 49) & ~3ULL; - - raw_write(env, ri, value); - hw_watchpoint_update(cpu, i); -} - -static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - int i =3D ri->crm; - - raw_write(env, ri, value); - hw_watchpoint_update(cpu, i); -} - -void hw_breakpoint_update(ARMCPU *cpu, int n) -{ - CPUARMState *env =3D &cpu->env; - uint64_t bvr =3D env->cp15.dbgbvr[n]; - uint64_t bcr =3D env->cp15.dbgbcr[n]; - vaddr addr; - int bt; - int flags =3D BP_CPU; - - if (env->cpu_breakpoint[n]) { - cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); - env->cpu_breakpoint[n] =3D NULL; - } - - if (!extract64(bcr, 0, 1)) { - /* E bit clear : watchpoint disabled */ - return; - } - - bt =3D extract64(bcr, 20, 4); - - switch (bt) { - case 4: /* unlinked address mismatch (reserved if AArch64) */ - case 5: /* linked address mismatch (reserved if AArch64) */ - qemu_log_mask(LOG_UNIMP, - "arm: address mismatch breakpoint types not implemen= ted\n"); - return; - case 0: /* unlinked address match */ - case 1: /* linked address match */ - { - /* Bits [63:49] are hardwired to the value of bit [48]; that is, - * we behave as if the register was sign extended. Bits [1:0] are - * RES0. The BAS field is used to allow setting breakpoints on 16 - * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether - * a bp will fire if the addresses covered by the bp and the addre= sses - * covered by the insn overlap but the insn doesn't start at the - * start of the bp address range. We choose to require the insn and - * the bp to have the same address. The constraints on writing to - * BAS enforced in dbgbcr_write mean we have only four cases: - * 0b0000 =3D> no breakpoint - * 0b0011 =3D> breakpoint on addr - * 0b1100 =3D> breakpoint on addr + 2 - * 0b1111 =3D> breakpoint on addr - * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). - */ - int bas =3D extract64(bcr, 5, 4); - addr =3D sextract64(bvr, 0, 49) & ~3ULL; - if (bas =3D=3D 0) { - return; - } - if (bas =3D=3D 0xc) { - addr +=3D 2; - } - break; - } - case 2: /* unlinked context ID match */ - case 8: /* unlinked VMID match (reserved if no EL2) */ - case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ - qemu_log_mask(LOG_UNIMP, - "arm: unlinked context breakpoint types not implemen= ted\n"); - return; - case 9: /* linked VMID match (reserved if no EL2) */ - case 11: /* linked context ID and VMID match (reserved if no EL2) */ - case 3: /* linked context ID match */ - default: - /* We must generate no events for Linked context matches (unless - * they are linked to by some other bp/wp, which is handled in - * updates for the linking bp/wp). We choose to also generate no e= vents - * for reserved values. - */ - return; - } - - cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); -} - -void hw_breakpoint_update_all(ARMCPU *cpu) -{ - int i; - CPUARMState *env =3D &cpu->env; - - /* Completely clear out existing QEMU breakpoints and our array, to - * avoid possible stale entries following migration load. - */ - cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); - memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); - - for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { - hw_breakpoint_update(cpu, i); - } -} - -static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - int i =3D ri->crm; - - raw_write(env, ri, value); - hw_breakpoint_update(cpu, i); -} - -static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - int i =3D ri->crm; - - /* - * BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only - * copy of BAS[0]. - */ - value =3D deposit64(value, 6, 1, extract64(value, 5, 1)); - value =3D deposit64(value, 8, 1, extract64(value, 7, 1)); - - raw_write(env, ri, value); - hw_breakpoint_update(cpu, i); -} - -static void define_debug_regs(ARMCPU *cpu) -{ - /* - * Define v7 and v8 architectural debug registers. - * These are just dummy implementations for now. - */ - int i; - int wrps, brps, ctx_cmps; - - /* - * The Arm ARM says DBGDIDR is optional and deprecated if EL1 cannot - * use AArch32. Given that bit 15 is RES1, if the value is 0 then - * the register must not exist for this cpu. - */ - if (cpu->isar.dbgdidr !=3D 0) { - ARMCPRegInfo dbgdidr =3D { - .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, - .opc1 =3D 0, .opc2 =3D 0, - .access =3D PL0_R, .accessfn =3D access_tda, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->isar.dbgdidr, - }; - define_one_arm_cp_reg(cpu, &dbgdidr); - } - - /* Note that all these register fields hold "number of Xs minus 1". */ - brps =3D arm_num_brps(cpu); - wrps =3D arm_num_wrps(cpu); - ctx_cmps =3D arm_num_ctx_cmps(cpu); - - assert(ctx_cmps <=3D brps); - - define_arm_cp_regs(cpu, debug_cp_reginfo); - - if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) { - define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); - } - - for (i =3D 0; i < brps; i++) { - ARMCPRegInfo dbgregs[] =3D { - { .name =3D "DBGBVR", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 4, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbvr[i]), - .writefn =3D dbgbvr_write, .raw_writefn =3D raw_write - }, - { .name =3D "DBGBCR", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 5, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbcr[i]), - .writefn =3D dbgbcr_write, .raw_writefn =3D raw_write - }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, dbgregs); - } - - for (i =3D 0; i < wrps; i++) { - ARMCPRegInfo dbgregs[] =3D { - { .name =3D "DBGWVR", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 6, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwvr[i]), - .writefn =3D dbgwvr_write, .raw_writefn =3D raw_write - }, - { .name =3D "DBGWCR", .state =3D ARM_CP_STATE_BOTH, - .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 7, - .access =3D PL1_RW, .accessfn =3D access_tda, - .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwcr[i]), - .writefn =3D dbgwcr_write, .raw_writefn =3D raw_write - }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, dbgregs); - } -} - -static void define_pmu_regs(ARMCPU *cpu) -{ - /* - * v7 performance monitor control register: same implementor - * field as main ID register, and we implement four counters in - * addition to the cycle count register. - */ - unsigned int i, pmcrn =3D PMCR_NUM_COUNTERS; - ARMCPRegInfo pmcr =3D { - .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 0, - .access =3D PL0_RW, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcr), - .accessfn =3D pmreg_access, .writefn =3D pmcr_write, - .raw_writefn =3D raw_write, - }; - ARMCPRegInfo pmcr64 =3D { - .name =3D "PMCR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 0, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .type =3D ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue =3D (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) | - PMCRLC, - .writefn =3D pmcr_write, .raw_writefn =3D raw_write, - }; - define_one_arm_cp_reg(cpu, &pmcr); - define_one_arm_cp_reg(cpu, &pmcr64); - for (i =3D 0; i < pmcrn; i++) { - char *pmevcntr_name =3D g_strdup_printf("PMEVCNTR%d", i); - char *pmevcntr_el0_name =3D g_strdup_printf("PMEVCNTR%d_EL0", i); - char *pmevtyper_name =3D g_strdup_printf("PMEVTYPER%d", i); - char *pmevtyper_el0_name =3D g_strdup_printf("PMEVTYPER%d_EL0", i); - ARMCPRegInfo pmev_regs[] =3D { - { .name =3D pmevcntr_name, .cp =3D 15, .crn =3D 14, - .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, - .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, - .accessfn =3D pmreg_access }, - { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 8 | (3 & (i = >> 3)), - .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess, - .type =3D ARM_CP_IO, - .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, - .raw_readfn =3D pmevcntr_rawread, - .raw_writefn =3D pmevcntr_rawwrite }, - { .name =3D pmevtyper_name, .cp =3D 15, .crn =3D 14, - .crm =3D 12 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, - .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, - .accessfn =3D pmreg_access }, - { .name =3D pmevtyper_el0_name, .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 12 | (3 & (i= >> 3)), - .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess, - .type =3D ARM_CP_IO, - .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, - .raw_writefn =3D pmevtyper_rawwrite }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, pmev_regs); - g_free(pmevcntr_name); - g_free(pmevcntr_el0_name); - g_free(pmevtyper_name); - g_free(pmevtyper_el0_name); - } - if (cpu_isar_feature(aa32_pmu_8_1, cpu)) { - ARMCPRegInfo v81_pmu_regs[] =3D { - { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 4, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D extract64(cpu->pmceid0, 32, 32) }, - { .name =3D "PMCEID3", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 5, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, v81_pmu_regs); - } - if (cpu_isar_feature(any_pmu_8_4, cpu)) { - static const ARMCPRegInfo v84_pmmir =3D { - .name =3D "PMMIR_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 6, - .access =3D PL1_R, .accessfn =3D pmreg_access, .type =3D ARM_C= P_CONST, - .resetvalue =3D 0 - }; - define_one_arm_cp_reg(cpu, &v84_pmmir); - } -} - -/* - * We don't know until after realize whether there's a GICv3 - * attached, and that is what registers the gicv3 sysregs. - * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_= EL1 - * at runtime. - */ -static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - ARMCPU *cpu =3D env_archcpu(env); - uint64_t pfr1 =3D cpu->isar.id_pfr1; - - if (env->gicv3state) { - pfr1 |=3D 1 << 28; - } - return pfr1; -} - -#ifndef CONFIG_USER_ONLY -static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - ARMCPU *cpu =3D env_archcpu(env); - uint64_t pfr0 =3D cpu->isar.id_aa64pfr0; - - if (env->gicv3state) { - pfr0 |=3D 1 << 24; - } - return pfr0; -} -#endif - -/* - * Shared logic between LORID and the rest of the LOR* registers. - * Secure state exclusion has already been dealt with. - */ -static CPAccessResult access_lor_ns(CPUARMState *env, - const ARMCPRegInfo *ri, bool isread) -{ - int el =3D arm_current_el(env); - - if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) { - return CP_ACCESS_TRAP_EL2; - } - if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) { - return CP_ACCESS_TRAP_EL3; - } - return CP_ACCESS_OK; -} - -static CPAccessResult access_lor_other(CPUARMState *env, - const ARMCPRegInfo *ri, bool isread) -{ - if (arm_is_secure_below_el3(env)) { - /* Access denied in secure mode. */ - return CP_ACCESS_TRAP; - } - return access_lor_ns(env, ri, isread); -} - -/* - * A trivial implementation of ARMv8.1-LOR leaves all of these - * registers fixed at 0, which indicates that there are zero - * supported Limited Ordering regions. - */ -static const ARMCPRegInfo lor_reginfo[] =3D { - { .name =3D "LORSA_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LOREA_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LORN_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LORC_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 3, - .access =3D PL1_RW, .accessfn =3D access_lor_other, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "LORID_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 7, - .access =3D PL1_R, .accessfn =3D access_lor_ns, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -#ifdef TARGET_AARCH64 -static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *r= i, - bool isread) -{ - int el =3D arm_current_el(env); - - if (el < 2 && - arm_feature(env, ARM_FEATURE_EL2) && - !(arm_hcr_el2_eff(env) & HCR_APK)) { - return CP_ACCESS_TRAP_EL2; - } - if (el < 3 && - arm_feature(env, ARM_FEATURE_EL3) && - !(env->cp15.scr_el3 & SCR_APK)) { - return CP_ACCESS_TRAP_EL3; - } - return CP_ACCESS_OK; -} - -static const ARMCPRegInfo pauth_reginfo[] =3D { - { .name =3D "APDAKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_pauth, - .fieldoffset =3D offsetof(CPUARMState, keys.apda.lo) }, - { .name =3D "APDAKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_pauth, - .fieldoffset =3D offsetof(CPUARMState, keys.apda.hi) }, - { .name =3D "APDBKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_pauth, - .fieldoffset =3D offsetof(CPUARMState, keys.apdb.lo) }, - { .name =3D "APDBKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 2, .opc2 =3D 3, - .access =3D PL1_RW, .accessfn =3D access_pauth, - .fieldoffset =3D offsetof(CPUARMState, keys.apdb.hi) }, - { .name =3D "APGAKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 3, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_pauth, - .fieldoffset =3D offsetof(CPUARMState, keys.apga.lo) }, - { .name =3D "APGAKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 3, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_pauth, - .fieldoffset =3D offsetof(CPUARMState, keys.apga.hi) }, - { .name =3D "APIAKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_pauth, - .fieldoffset =3D offsetof(CPUARMState, keys.apia.lo) }, - { .name =3D "APIAKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_pauth, - .fieldoffset =3D offsetof(CPUARMState, keys.apia.hi) }, - { .name =3D "APIBKEYLO_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, - .access =3D PL1_RW, .accessfn =3D access_pauth, - .fieldoffset =3D offsetof(CPUARMState, keys.apib.lo) }, - { .name =3D "APIBKEYHI_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 3, - .access =3D PL1_RW, .accessfn =3D access_pauth, - .fieldoffset =3D offsetof(CPUARMState, keys.apib.hi) }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo tlbirange_reginfo[] =3D { - { .name =3D "TLBI_RVAE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVAAE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 3, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVALE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVAALE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 2, .opc2 =3D 7, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVAE1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVAAE1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 3, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVALE1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVAALE1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 5, .opc2 =3D 7, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae1is_write }, - { .name =3D "TLBI_RVAE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae1_write }, - { .name =3D "TLBI_RVAAE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 3, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae1_write }, - { .name =3D "TLBI_RVALE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae1_write }, - { .name =3D "TLBI_RVAALE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 6, .opc2 =3D 7, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae1_write }, - { .name =3D "TLBI_RIPAS2E1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_RIPAS2LE1IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 6, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_RVAE2IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae2is_write }, - { .name =3D "TLBI_RVALE2IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae2is_write }, - { .name =3D "TLBI_RIPAS2E1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 2, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_RIPAS2LE1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 6, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_RVAE2OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae2is_write }, - { .name =3D "TLBI_RVALE2OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae2is_write }, - { .name =3D "TLBI_RVAE2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae2_write }, - { .name =3D "TLBI_RVALE2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae2_write }, - { .name =3D "TLBI_RVAE3IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae3is_write }, - { .name =3D "TLBI_RVALE3IS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae3is_write }, - { .name =3D "TLBI_RVAE3OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae3is_write }, - { .name =3D "TLBI_RVALE3OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae3is_write }, - { .name =3D "TLBI_RVAE3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae3_write }, - { .name =3D "TLBI_RVALE3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_rvae3_write }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo tlbios_reginfo[] =3D { - { .name =3D "TLBI_VMALLE1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vmalle1is_write }, - { .name =3D "TLBI_ASIDE1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 1, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_vmalle1is_write }, - { .name =3D "TLBI_ALLE2OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle2is_write }, - { .name =3D "TLBI_ALLE1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 4, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, - { .name =3D "TLBI_VMALLS12E1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 6, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle1is_write }, - { .name =3D "TLBI_IPAS2E1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 0, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_RIPAS2E1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 3, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_IPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 4, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_RIPAS2LE1OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 7, - .access =3D PL2_W, .type =3D ARM_CP_NOP }, - { .name =3D "TLBI_ALLE3OS", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, - .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, - .writefn =3D tlbi_aa64_alle3is_write }, - REGINFO_SENTINEL -}; - -static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) -{ - Error *err =3D NULL; - uint64_t ret; - - /* Success sets NZCV =3D 0000. */ - env->NF =3D env->CF =3D env->VF =3D 0, env->ZF =3D 1; - - if (qemu_guest_getrandom(&ret, sizeof(ret), &err) < 0) { - /* - * ??? Failed, for unknown reasons in the crypto subsystem. - * The best we can do is log the reason and return the - * timed-out indication to the guest. There is no reason - * we know to expect this failure to be transitory, so the - * guest may well hang retrying the operation. - */ - qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", - ri->name, error_get_pretty(err)); - error_free(err); - - env->ZF =3D 0; /* NZCF =3D 0100 */ - return 0; - } - return ret; -} - -/* We do not support re-seeding, so the two registers operate the same. */ -static const ARMCPRegInfo rndr_reginfo[] =3D { - { .name =3D "RNDR", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 2, .crm =3D 4, .opc2 =3D 0, - .access =3D PL0_R, .readfn =3D rndr_readfn }, - { .name =3D "RNDRRS", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 2, .crm =3D 4, .opc2 =3D 1, - .access =3D PL0_R, .readfn =3D rndr_readfn }, - REGINFO_SENTINEL -}; - -#ifndef CONFIG_USER_ONLY -static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - /* CTR_EL0 System register -> DminLine, bits [19:16] */ - uint64_t dline_size =3D 4 << ((cpu->ctr >> 16) & 0xF); - uint64_t vaddr_in =3D (uint64_t) value; - uint64_t vaddr =3D vaddr_in & ~(dline_size - 1); - void *haddr; - int mem_idx =3D cpu_mmu_index(env, false); - - /* This won't be crossing page boundaries */ - haddr =3D probe_read(env, vaddr, dline_size, mem_idx, GETPC()); - if (haddr) { - - ram_addr_t offset; - MemoryRegion *mr; - - /* RCU lock is already being held */ - mr =3D memory_region_from_host(haddr, &offset); - - if (mr) { - memory_region_writeback(mr, offset, dline_size); - } - } -} - -static const ARMCPRegInfo dcpop_reg[] =3D { - { .name =3D "DC_CVAP", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 1, - .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, - .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo dcpodp_reg[] =3D { - { .name =3D "DC_CVADP", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 1, - .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, - .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, - REGINFO_SENTINEL -}; -#endif /*CONFIG_USER_ONLY*/ - -static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInf= o *ri, - bool isread) -{ - if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID5)) { - return CP_ACCESS_TRAP_EL2; - } - - return CP_ACCESS_OK; -} - -static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - int el =3D arm_current_el(env); - - if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { - uint64_t hcr =3D arm_hcr_el2_eff(env); - if (!(hcr & HCR_ATA) && (!(hcr & HCR_E2H) || !(hcr & HCR_TGE))) { - return CP_ACCESS_TRAP_EL2; - } - } - if (el < 3 && - arm_feature(env, ARM_FEATURE_EL3) && - !(env->cp15.scr_el3 & SCR_ATA)) { - return CP_ACCESS_TRAP_EL3; - } - return CP_ACCESS_OK; -} - -static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - return env->pstate & PSTATE_TCO; -} - -static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= al) -{ - env->pstate =3D (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO); -} - -static const ARMCPRegInfo mte_reginfo[] =3D { - { .name =3D "TFSRE0_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 6, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_mte, - .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[0]) }, - { .name =3D "TFSR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 6, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_mte, - .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[1]) }, - { .name =3D "TFSR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 6, .opc2 =3D 0, - .access =3D PL2_RW, .accessfn =3D access_mte, - .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[2]) }, - { .name =3D "TFSR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 6, .opc2 =3D 0, - .access =3D PL3_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[3]) }, - { .name =3D "RGSR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 5, - .access =3D PL1_RW, .accessfn =3D access_mte, - .fieldoffset =3D offsetof(CPUARMState, cp15.rgsr_el1) }, - { .name =3D "GCR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 6, - .access =3D PL1_RW, .accessfn =3D access_mte, - .fieldoffset =3D offsetof(CPUARMState, cp15.gcr_el1) }, - { .name =3D "GMID_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 4, - .access =3D PL1_R, .accessfn =3D access_aa64_tid5, - .type =3D ARM_CP_CONST, .resetvalue =3D GMID_EL1_BS }, - { .name =3D "TCO", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 7, - .type =3D ARM_CP_NO_RAW, - .access =3D PL0_RW, .readfn =3D tco_read, .writefn =3D tco_write }, - { .name =3D "DC_IGVAC", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 3, - .type =3D ARM_CP_NOP, .access =3D PL1_W, - .accessfn =3D aa64_cacheop_poc_access }, - { .name =3D "DC_IGSW", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 4, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, - { .name =3D "DC_IGDVAC", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 5, - .type =3D ARM_CP_NOP, .access =3D PL1_W, - .accessfn =3D aa64_cacheop_poc_access }, - { .name =3D "DC_IGDSW", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 6, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, - { .name =3D "DC_CGSW", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 4, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, - { .name =3D "DC_CGDSW", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 6, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, - { .name =3D "DC_CIGSW", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 4, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, - { .name =3D "DC_CIGDSW", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 6, - .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo mte_tco_ro_reginfo[] =3D { - { .name =3D "TCO", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 7, - .type =3D ARM_CP_CONST, .access =3D PL0_RW, }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo mte_el0_cacheop_reginfo[] =3D { - { .name =3D "DC_CGVAC", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 3, - .type =3D ARM_CP_NOP, .access =3D PL0_W, - .accessfn =3D aa64_cacheop_poc_access }, - { .name =3D "DC_CGDVAC", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 5, - .type =3D ARM_CP_NOP, .access =3D PL0_W, - .accessfn =3D aa64_cacheop_poc_access }, - { .name =3D "DC_CGVAP", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 3, - .type =3D ARM_CP_NOP, .access =3D PL0_W, - .accessfn =3D aa64_cacheop_poc_access }, - { .name =3D "DC_CGDVAP", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 5, - .type =3D ARM_CP_NOP, .access =3D PL0_W, - .accessfn =3D aa64_cacheop_poc_access }, - { .name =3D "DC_CGVADP", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 3, - .type =3D ARM_CP_NOP, .access =3D PL0_W, - .accessfn =3D aa64_cacheop_poc_access }, - { .name =3D "DC_CGDVADP", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 5, - .type =3D ARM_CP_NOP, .access =3D PL0_W, - .accessfn =3D aa64_cacheop_poc_access }, - { .name =3D "DC_CIGVAC", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 3, - .type =3D ARM_CP_NOP, .access =3D PL0_W, - .accessfn =3D aa64_cacheop_poc_access }, - { .name =3D "DC_CIGDVAC", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 5, - .type =3D ARM_CP_NOP, .access =3D PL0_W, - .accessfn =3D aa64_cacheop_poc_access }, - { .name =3D "DC_GVA", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 3, - .access =3D PL0_W, .type =3D ARM_CP_DC_GVA, -#ifndef CONFIG_USER_ONLY - /* Avoid overhead of an access check that always passes in user-mode= */ - .accessfn =3D aa64_zva_access, -#endif - }, - { .name =3D "DC_GZVA", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 4, - .access =3D PL0_W, .type =3D ARM_CP_DC_GZVA, -#ifndef CONFIG_USER_ONLY - /* Avoid overhead of an access check that always passes in user-mode= */ - .accessfn =3D aa64_zva_access, -#endif - }, - REGINFO_SENTINEL -}; - -#endif - -static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, - bool isread) -{ - int el =3D arm_current_el(env); - - if (el =3D=3D 0) { - uint64_t sctlr =3D arm_sctlr(env, el); - if (!(sctlr & SCTLR_EnRCTX)) { - return CP_ACCESS_TRAP; - } - } else if (el =3D=3D 1) { - uint64_t hcr =3D arm_hcr_el2_eff(env); - if (hcr & HCR_NV) { - return CP_ACCESS_TRAP_EL2; - } - } - return CP_ACCESS_OK; -} - -static const ARMCPRegInfo predinv_reginfo[] =3D { - { .name =3D "CFP_RCTX", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 4, - .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, - { .name =3D "DVP_RCTX", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 5, - .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, - { .name =3D "CPP_RCTX", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, - .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, - /* - * Note the AArch32 opcodes have a different OPC1. - */ - { .name =3D "CFPRCTX", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 4, - .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, - { .name =3D "DVPRCTX", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 5, - .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, - { .name =3D "CPPRCTX", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, - .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, - REGINFO_SENTINEL -}; - -static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - /* Read the high 32 bits of the current CCSIDR */ - return extract64(ccsidr_read(env, ri), 32, 32); -} - -static const ARMCPRegInfo ccsidr2_reginfo[] =3D { - { .name =3D "CCSIDR2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 2, - .access =3D PL1_R, - .accessfn =3D access_aa64_tid2, - .readfn =3D ccsidr2_read, .type =3D ARM_CP_NO_RAW }, - REGINFO_SENTINEL -}; - -static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInf= o *ri, - bool isread) -{ - if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) { - return CP_ACCESS_TRAP_EL2; - } - - return CP_ACCESS_OK; -} - -static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInf= o *ri, - bool isread) -{ - if (arm_feature(env, ARM_FEATURE_V8)) { - return access_aa64_tid3(env, ri, isread); - } - - return CP_ACCESS_OK; -} - -static CPAccessResult access_jazelle(CPUARMState *env, const ARMCPRegInfo = *ri, - bool isread) -{ - if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TID0))= { - return CP_ACCESS_TRAP_EL2; - } - - return CP_ACCESS_OK; -} - -static const ARMCPRegInfo jazelle_regs[] =3D { - { .name =3D "JIDR", - .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D 7, .opc2 =3D 0, - .access =3D PL1_R, .accessfn =3D access_jazelle, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "JOSCR", - .cp =3D 14, .crn =3D 1, .crm =3D 0, .opc1 =3D 7, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "JMCR", - .cp =3D 14, .crn =3D 2, .crm =3D 0, .opc1 =3D 7, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo vhe_reginfo[] =3D { - { .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]) }, - { .name =3D "TTBR1_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.ttbr1_el[2]) }, -#ifndef CONFIG_USER_ONLY - { .name =3D "CNTHV_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, - .fieldoffset =3D - offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT].cval), - .type =3D ARM_CP_IO, .access =3D PL2_RW, - .writefn =3D gt_hv_cval_write, .raw_writefn =3D raw_write }, - { .name =3D "CNTHV_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .access =3D PL2_RW, - .resetfn =3D gt_hv_timer_reset, - .readfn =3D gt_hv_tval_read, .writefn =3D gt_hv_tval_write }, - { .name =3D "CNTHV_CTL_EL2", .state =3D ARM_CP_STATE_BOTH, - .type =3D ARM_CP_IO, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYPVIRT= ].ctl), - .writefn =3D gt_hv_ctl_write, .raw_writefn =3D raw_write }, - { .name =3D "CNTP_CTL_EL02", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .access =3D PL2_RW, .accessfn =3D e2h_access, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= tl), - .writefn =3D gt_phys_ctl_write, .raw_writefn =3D raw_write }, - { .name =3D "CNTV_CTL_EL02", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 1, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .access =3D PL2_RW, .accessfn =3D e2h_access, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= tl), - .writefn =3D gt_virt_ctl_write, .raw_writefn =3D raw_write }, - { .name =3D "CNTP_TVAL_EL02", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, - .access =3D PL2_RW, .accessfn =3D e2h_access, - .readfn =3D gt_phys_tval_read, .writefn =3D gt_phys_tval_write }, - { .name =3D "CNTV_TVAL_EL02", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW | ARM_CP_IO | ARM_CP_ALIAS, - .access =3D PL2_RW, .accessfn =3D e2h_access, - .readfn =3D gt_virt_tval_read, .writefn =3D gt_virt_tval_write }, - { .name =3D "CNTP_CVAL_EL02", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].c= val), - .access =3D PL2_RW, .accessfn =3D e2h_access, - .writefn =3D gt_phys_cval_write, .raw_writefn =3D raw_write }, - { .name =3D "CNTV_CVAL_EL02", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 5, .crn =3D 14, .crm =3D 3, .opc2 =3D 2, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].c= val), - .access =3D PL2_RW, .accessfn =3D e2h_access, - .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write }, -#endif - REGINFO_SENTINEL -}; - -#ifndef CONFIG_USER_ONLY -static const ARMCPRegInfo ats1e1_reginfo[] =3D { - { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn =3D ats_write64 }, - { .name =3D "AT_S1E1W", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn =3D ats_write64 }, - REGINFO_SENTINEL -}; - -static const ARMCPRegInfo ats1cp_reginfo[] =3D { - { .name =3D "ATS1CPRP", - .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn =3D ats_write }, - { .name =3D "ATS1CPWP", - .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, - .writefn =3D ats_write }, - REGINFO_SENTINEL -}; -#endif - -/* - * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and - * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field - * is non-zero, which is never for ARMv7, optionally in ARMv8 - * and mandatorily for ARMv8.2 and up. - * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's - * implementation is RAZ/WI we can ignore this detail, as we - * do for ACTLR. - */ -static const ARMCPRegInfo actlr2_hactlr2_reginfo[] =3D { - { .name =3D "ACTLR2", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, - .access =3D PL1_RW, .accessfn =3D access_tacr, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HACTLR2", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - -void register_cp_regs_for_features(ARMCPU *cpu) -{ - /* Register all the coprocessor registers based on feature bits */ - CPUARMState *env =3D &cpu->env; - if (arm_feature(env, ARM_FEATURE_M)) { - /* M profile has no coprocessor registers */ + switch (extract64(wcr, 3, 2)) { + case 0: + /* LSC 00 is reserved and must behave as if the wp is disabled */ return; + case 1: + flags |=3D BP_MEM_READ; + break; + case 2: + flags |=3D BP_MEM_WRITE; + break; + case 3: + flags |=3D BP_MEM_ACCESS; + break; } =20 - define_arm_cp_regs(cpu, cp_reginfo); - if (!arm_feature(env, ARM_FEATURE_V8)) { - /* - * Must go early as it is full of wildcards that may be - * overridden by later definitions. - */ - define_arm_cp_regs(cpu, not_v8_cp_reginfo); - } - - if (arm_feature(env, ARM_FEATURE_V6)) { - /* The ID registers all have impdef reset values */ - ARMCPRegInfo v6_idregs[] =3D { - { .name =3D "ID_PFR0", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_pfr0 }, - /* - * ID_PFR1 is not a plain ARM_CP_CONST because we don't know - * the value of the GIC field until after we define these regs. - */ - { .name =3D "ID_PFR1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, - .accessfn =3D access_aa32_tid3, - .readfn =3D id_pfr1_read, - .writefn =3D arm_cp_write_ignore }, - { .name =3D "ID_DFR0", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 2, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_dfr0 }, - { .name =3D "ID_AFR0", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 3, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->id_afr0 }, - { .name =3D "ID_MMFR0", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 4, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr0 }, - { .name =3D "ID_MMFR1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 5, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr1 }, - { .name =3D "ID_MMFR2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr2 }, - { .name =3D "ID_MMFR3", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 7, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr3 }, - { .name =3D "ID_ISAR0", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar0 }, - { .name =3D "ID_ISAR1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar1 }, - { .name =3D "ID_ISAR2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 2, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar2 }, - { .name =3D "ID_ISAR3", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 3, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar3 }, - { .name =3D "ID_ISAR4", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 4, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar4 }, - { .name =3D "ID_ISAR5", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 5, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar5 }, - { .name =3D "ID_MMFR4", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_mmfr4 }, - { .name =3D "ID_ISAR6", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 7, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->isar.id_isar6 }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, v6_idregs); - define_arm_cp_regs(cpu, v6_cp_reginfo); - } else { - define_arm_cp_regs(cpu, not_v6_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_V6K)) { - define_arm_cp_regs(cpu, v6k_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_V7MP) && - !arm_feature(env, ARM_FEATURE_PMSA)) { - define_arm_cp_regs(cpu, v7mp_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_V7VE)) { - define_arm_cp_regs(cpu, pmovsset_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_V7)) { - ARMCPRegInfo clidr =3D { - .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid2, - .resetvalue =3D cpu->clidr - }; - define_one_arm_cp_reg(cpu, &clidr); - define_arm_cp_regs(cpu, v7_cp_reginfo); - define_debug_regs(cpu); - define_pmu_regs(cpu); - } else { - define_arm_cp_regs(cpu, not_v7_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_V8)) { - /* - * AArch64 ID registers, which all have impdef reset values. - * Note that within the ID register ranges the unused slots - * must all RAZ, not UNDEF; future architecture versions may - * define new registers here. + /* Attempts to use both MASK and BAS fields simultaneously are + * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, + * thus generating a watchpoint for every byte in the masked region. + */ + mask =3D extract64(wcr, 24, 4); + if (mask =3D=3D 1 || mask =3D=3D 2) { + /* Reserved values of MASK; we must act as if the mask value was + * some non-reserved value, or as if the watchpoint were disabled. + * We choose the latter. */ - ARMCPRegInfo v8_idregs[] =3D { - /* - * ID_AA64PFR0_EL1 is not a plain ARM_CP_CONST in system - * emulation because we don't know the right value for the - * GIC field until after we define these regs. - */ - { .name =3D "ID_AA64PFR0_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 0, - .access =3D PL1_R, -#ifdef CONFIG_USER_ONLY - .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->isar.id_aa64pfr0 -#else - .type =3D ARM_CP_NO_RAW, - .accessfn =3D access_aa64_tid3, - .readfn =3D id_aa64pfr0_read, - .writefn =3D arm_cp_write_ignore -#endif - }, - { .name =3D "ID_AA64PFR1_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64pfr1}, - { .name =3D "ID_AA64PFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 2, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64PFR3_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 3, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64ZFR0_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 4, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64zfr0 }, - { .name =3D "ID_AA64PFR5_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 5, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64PFR6_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64PFR7_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 4, .opc2 =3D = 7, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64DFR0_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64dfr0 }, - { .name =3D "ID_AA64DFR1_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64dfr1 }, - { .name =3D "ID_AA64DFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 2, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64DFR3_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 3, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64AFR0_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 4, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->id_aa64afr0 }, - { .name =3D "ID_AA64AFR1_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 5, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->id_aa64afr1 }, - { .name =3D "ID_AA64AFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64AFR3_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 7, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64ISAR0_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64isar0 }, - { .name =3D "ID_AA64ISAR1_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64isar1 }, - { .name =3D "ID_AA64ISAR2_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 2, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64ISAR3_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 3, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64ISAR4_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 4, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64ISAR5_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 5, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64ISAR6_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64ISAR7_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 6, .opc2 =3D = 7, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64MMFR0_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64mmfr0 }, - { .name =3D "ID_AA64MMFR1_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64mmfr1 }, - { .name =3D "ID_AA64MMFR2_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 2, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_aa64mmfr2 }, - { .name =3D "ID_AA64MMFR3_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 3, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64MMFR4_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 4, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64MMFR5_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 5, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64MMFR6_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_AA64MMFR7_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 7, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "MVFR0_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.mvfr0 }, - { .name =3D "MVFR1_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 1, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.mvfr1 }, - { .name =3D "MVFR2_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 2, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.mvfr2 }, - { .name =3D "MVFR3_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 3, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "ID_PFR2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 4, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->isar.id_pfr2 }, - { .name =3D "MVFR5_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 5, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "MVFR6_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 6, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "MVFR7_EL1_RESERVED", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 3, .opc2 =3D = 7, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, - { .name =3D "PMCEID0", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 6, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D extract64(cpu->pmceid0, 0, 32) }, - { .name =3D "PMCEID0_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 6, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D cpu->pmceid0 }, - { .name =3D "PMCEID1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 12, .opc2 =3D = 7, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D extract64(cpu->pmceid1, 0, 32) }, - { .name =3D "PMCEID1_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 7, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D cpu->pmceid1 }, - REGINFO_SENTINEL - }; -#ifdef CONFIG_USER_ONLY - ARMCPRegUserSpaceInfo v8_user_idregs[] =3D { - { .name =3D "ID_AA64PFR0_EL1", - .exported_bits =3D 0x000f000f00ff0000, - .fixed_bits =3D 0x0000000000000011 }, - { .name =3D "ID_AA64PFR1_EL1", - .exported_bits =3D 0x00000000000000f0 }, - { .name =3D "ID_AA64PFR*_EL1_RESERVED", - .is_glob =3D true }, - { .name =3D "ID_AA64ZFR0_EL1" }, - { .name =3D "ID_AA64MMFR0_EL1", - .fixed_bits =3D 0x00000000ff000000 }, - { .name =3D "ID_AA64MMFR1_EL1" }, - { .name =3D "ID_AA64MMFR*_EL1_RESERVED", - .is_glob =3D true }, - { .name =3D "ID_AA64DFR0_EL1", - .fixed_bits =3D 0x0000000000000006 }, - { .name =3D "ID_AA64DFR1_EL1" }, - { .name =3D "ID_AA64DFR*_EL1_RESERVED", - .is_glob =3D true }, - { .name =3D "ID_AA64AFR*", - .is_glob =3D true }, - { .name =3D "ID_AA64ISAR0_EL1", - .exported_bits =3D 0x00fffffff0fffff0 }, - { .name =3D "ID_AA64ISAR1_EL1", - .exported_bits =3D 0x000000f0ffffffff }, - { .name =3D "ID_AA64ISAR*_EL1_RESERVED", - .is_glob =3D true }, - REGUSERINFO_SENTINEL - }; - modify_arm_cp_regs(v8_idregs, v8_user_idregs); -#endif - /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ - if (!arm_feature(env, ARM_FEATURE_EL3) && - !arm_feature(env, ARM_FEATURE_EL2)) { - ARMCPRegInfo rvbar =3D { - .name =3D "RVBAR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 0, .opc2 = =3D 1, - .type =3D ARM_CP_CONST, .access =3D PL1_R, .resetvalue =3D= cpu->rvbar - }; - define_one_arm_cp_reg(cpu, &rvbar); - } - define_arm_cp_regs(cpu, v8_idregs); - define_arm_cp_regs(cpu, v8_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_EL2)) { - uint64_t vmpidr_def =3D mpidr_read_val(env); - ARMCPRegInfo vpidr_regs[] =3D { - { .name =3D "VPIDR", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .resetvalue =3D cpu->midr, .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.vpidr_el2) = }, - { .name =3D "VPIDR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D = 0, - .access =3D PL2_RW, .resetvalue =3D cpu->midr, - .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, - { .name =3D "VMPIDR", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 5, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .resetvalue =3D vmpidr_def, .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.vmpidr_el2)= }, - { .name =3D "VMPIDR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D = 5, - .access =3D PL2_RW, - .resetvalue =3D vmpidr_def, - .fieldoffset =3D offsetof(CPUARMState, cp15.vmpidr_el2) }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, vpidr_regs); - define_arm_cp_regs(cpu, el2_cp_reginfo); - if (arm_feature(env, ARM_FEATURE_V8)) { - define_arm_cp_regs(cpu, el2_v8_cp_reginfo); - } - if (cpu_isar_feature(aa64_sel2, cpu)) { - define_arm_cp_regs(cpu, el2_sec_cp_reginfo); - } - /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ - if (!arm_feature(env, ARM_FEATURE_EL3)) { - ARMCPRegInfo rvbar =3D { - .name =3D "RVBAR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 = =3D 1, - .type =3D ARM_CP_CONST, .access =3D PL2_R, .resetvalue =3D= cpu->rvbar - }; - define_one_arm_cp_reg(cpu, &rvbar); - } - } else { - /* - * If EL2 is missing but higher ELs are enabled, we need to - * register the no_el2 reginfos. + return; + } else if (mask) { + /* Watchpoint covers an aligned area up to 2GB in size */ + len =3D 1ULL << mask; + /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTAB= LE + * whether the watchpoint fires when the unmasked bits match; we o= pt + * to generate the exceptions. */ - if (arm_feature(env, ARM_FEATURE_EL3)) { - /* - * When EL3 exists but not EL2, VPIDR and VMPIDR take the value - * of MIDR_EL1 and MPIDR_EL1. - */ - ARMCPRegInfo vpidr_regs[] =3D { - { .name =3D "VPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 = =3D 0, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->midr, - .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, - { .name =3D "VMPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 = =3D 5, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_NO_RAW, - .writefn =3D arm_cp_write_ignore, .readfn =3D mpidr_read= }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, vpidr_regs); - define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); - if (arm_feature(env, ARM_FEATURE_V8)) { - define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo); - } - } - } - if (arm_feature(env, ARM_FEATURE_EL3)) { - define_arm_cp_regs(cpu, el3_cp_reginfo); - ARMCPRegInfo el3_regs[] =3D { - { .name =3D "RVBAR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 12, .crm =3D 0, .opc2 =3D= 1, - .type =3D ARM_CP_CONST, .access =3D PL3_R, .resetvalue =3D c= pu->rvbar }, - { .name =3D "SCTLR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 0, .opc2 =3D = 0, - .access =3D PL3_RW, - .raw_writefn =3D raw_write, .writefn =3D sctlr_write, - .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr_el[3]), - .resetvalue =3D cpu->reset_sctlr }, - REGINFO_SENTINEL - }; - - define_arm_cp_regs(cpu, el3_regs); - } - /* - * The behaviour of NSACR is sufficiently various that we don't - * try to describe it in a single reginfo: - * if EL3 is 64 bit, then trap to EL3 from S EL1, - * reads as constant 0xc00 from NS EL1 and NS EL2 - * if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2 - * if v7 without EL3, register doesn't exist - * if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2 - */ - if (arm_feature(env, ARM_FEATURE_EL3)) { - if (arm_feature(env, ARM_FEATURE_AARCH64)) { - ARMCPRegInfo nsacr =3D { - .name =3D "NSACR", .type =3D ARM_CP_CONST, - .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, - .access =3D PL1_RW, .accessfn =3D nsacr_access, - .resetvalue =3D 0xc00 - }; - define_one_arm_cp_reg(cpu, &nsacr); - } else { - ARMCPRegInfo nsacr =3D { - .name =3D "NSACR", - .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, - .access =3D PL3_RW | PL1_R, - .resetvalue =3D 0, - .fieldoffset =3D offsetof(CPUARMState, cp15.nsacr) - }; - define_one_arm_cp_reg(cpu, &nsacr); - } + wvr &=3D ~(len - 1); } else { - if (arm_feature(env, ARM_FEATURE_V8)) { - ARMCPRegInfo nsacr =3D { - .name =3D "NSACR", .type =3D ARM_CP_CONST, - .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, - .access =3D PL1_R, - .resetvalue =3D 0xc00 - }; - define_one_arm_cp_reg(cpu, &nsacr); - } - } + /* Watchpoint covers bytes defined by the byte address select bits= */ + int bas =3D extract64(wcr, 5, 8); + int basstart; =20 - if (arm_feature(env, ARM_FEATURE_PMSA)) { - if (arm_feature(env, ARM_FEATURE_V6)) { - /* PMSAv6 not implemented */ - assert(arm_feature(env, ARM_FEATURE_V7)); - define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); - define_arm_cp_regs(cpu, pmsav7_cp_reginfo); - } else { - define_arm_cp_regs(cpu, pmsav5_cp_reginfo); - } - } else { - define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); - define_arm_cp_regs(cpu, vmsa_cp_reginfo); - /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */ - if (cpu_isar_feature(aa32_hpd, cpu)) { - define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); - } - } - if (arm_feature(env, ARM_FEATURE_THUMB2EE)) { - define_arm_cp_regs(cpu, t2ee_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { - define_arm_cp_regs(cpu, generic_timer_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_VAPA)) { - define_arm_cp_regs(cpu, vapa_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) { - define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) { - define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) { - define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_OMAPCP)) { - define_arm_cp_regs(cpu, omap_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_STRONGARM)) { - define_arm_cp_regs(cpu, strongarm_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - define_arm_cp_regs(cpu, xscale_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) { - define_arm_cp_regs(cpu, dummy_c15_cp_reginfo); - } - if (arm_feature(env, ARM_FEATURE_LPAE)) { - define_arm_cp_regs(cpu, lpae_cp_reginfo); - } - if (cpu_isar_feature(aa32_jazelle, cpu)) { - define_arm_cp_regs(cpu, jazelle_regs); - } - /* - * Slightly awkwardly, the OMAP and StrongARM cores need all of - * cp15 crn=3D0 to be writes-ignored, whereas for other cores they sho= uld - * be read-only (ie write causes UNDEF exception). - */ - { - ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] =3D { - /* - * Pre-v8 MIDR space. - * Note that the MIDR isn't a simple constant register because - * of the TI925 behaviour where writes to another register can - * cause the MIDR value to change. - * - * Unimplemented registers in the c15 0 0 0 space default to - * MIDR. Define MIDR first as this entire space, then CTR, TCM= TR - * and friends override accordingly. - */ - { .name =3D "MIDR", - .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D C= P_ANY, - .access =3D PL1_R, .resetvalue =3D cpu->midr, - .writefn =3D arm_cp_write_ignore, .raw_writefn =3D raw_write, - .readfn =3D midr_read, - .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), - .type =3D ARM_CP_OVERRIDE }, - /* crn =3D 0 op1 =3D 0 crm =3D 3..7 : currently unassigned; we= RAZ. */ - { .name =3D "DUMMY", - .cp =3D 15, .crn =3D 0, .crm =3D 3, .opc1 =3D 0, .opc2 =3D C= P_ANY, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, - { .name =3D "DUMMY", - .cp =3D 15, .crn =3D 0, .crm =3D 4, .opc1 =3D 0, .opc2 =3D C= P_ANY, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, - { .name =3D "DUMMY", - .cp =3D 15, .crn =3D 0, .crm =3D 5, .opc1 =3D 0, .opc2 =3D C= P_ANY, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, - { .name =3D "DUMMY", - .cp =3D 15, .crn =3D 0, .crm =3D 6, .opc1 =3D 0, .opc2 =3D C= P_ANY, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, - { .name =3D "DUMMY", - .cp =3D 15, .crn =3D 0, .crm =3D 7, .opc1 =3D 0, .opc2 =3D C= P_ANY, - .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, - REGINFO_SENTINEL - }; - ARMCPRegInfo id_v8_midr_cp_reginfo[] =3D { - { .name =3D "MIDR_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 0, - .access =3D PL1_R, .type =3D ARM_CP_NO_RAW, .resetvalue =3D = cpu->midr, - .fieldoffset =3D offsetof(CPUARMState, cp15.c0_cpuid), - .readfn =3D midr_read }, - /* crn =3D 0 op1 =3D 0 crm =3D 0 op2 =3D 4,7 : AArch32 aliases= of MIDR */ - { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, - .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4, - .access =3D PL1_R, .resetvalue =3D cpu->midr }, - { .name =3D "MIDR", .type =3D ARM_CP_ALIAS | ARM_CP_CONST, - .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 7, - .access =3D PL1_R, .resetvalue =3D cpu->midr }, - { .name =3D "REVIDR_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 0, .opc2 =3D = 6, - .access =3D PL1_R, - .accessfn =3D access_aa64_tid1, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->revidr }, - REGINFO_SENTINEL - }; - ARMCPRegInfo id_cp_reginfo[] =3D { - /* These are common to v8 and pre-v8 */ - { .name =3D "CTR", - .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 1, - .access =3D PL1_R, .accessfn =3D ctr_el0_access, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->ctr }, - { .name =3D "CTR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .opc2 =3D 1, .crn =3D 0, .crm =3D = 0, - .access =3D PL0_R, .accessfn =3D ctr_el0_access, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->ctr }, - /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */ - { .name =3D "TCMTR", - .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, - .access =3D PL1_R, - .accessfn =3D access_aa32_tid1, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL - }; - /* TLBTR is specific to VMSA */ - ARMCPRegInfo id_tlbtr_reginfo =3D { - .name =3D "TLBTR", - .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 3, - .access =3D PL1_R, - .accessfn =3D access_aa32_tid1, - .type =3D ARM_CP_CONST, .resetvalue =3D 0, - }; - /* MPUIR is specific to PMSA V6+ */ - ARMCPRegInfo id_mpuir_reginfo =3D { - .name =3D "MPUIR", - .cp =3D 15, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 4, - .access =3D PL1_R, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->pmsav7_dregion << 8 - }; - ARMCPRegInfo crn0_wi_reginfo =3D { - .name =3D "CRN0_WI", .cp =3D 15, .crn =3D 0, .crm =3D CP_ANY, - .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_W, - .type =3D ARM_CP_NOP | ARM_CP_OVERRIDE - }; -#ifdef CONFIG_USER_ONLY - ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] =3D { - { .name =3D "MIDR_EL1", - .exported_bits =3D 0x00000000ffffffff }, - { .name =3D "REVIDR_EL1" }, - REGUSERINFO_SENTINEL - }; - modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_regin= fo); -#endif - if (arm_feature(env, ARM_FEATURE_OMAPCP) || - arm_feature(env, ARM_FEATURE_STRONGARM)) { - ARMCPRegInfo *r; - /* - * Register the blanket "writes ignored" value first to cover = the - * whole space. Then update the specific ID registers to allow= write - * access, so that they ignore writes rather than causing them= to - * UNDEF. + if (extract64(wvr, 2, 1)) { + /* Deprecated case of an only 4-aligned address. BAS[7:4] are + * ignored, and BAS[3:0] define which bytes to watch. */ - define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); - for (r =3D id_pre_v8_midr_cp_reginfo; - r->type !=3D ARM_CP_SENTINEL; r++) { - r->access =3D PL1_RW; - } - for (r =3D id_cp_reginfo; r->type !=3D ARM_CP_SENTINEL; r++) { - r->access =3D PL1_RW; - } - id_mpuir_reginfo.access =3D PL1_RW; - id_tlbtr_reginfo.access =3D PL1_RW; - } - if (arm_feature(env, ARM_FEATURE_V8)) { - define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); - } else { - define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); - } - define_arm_cp_regs(cpu, id_cp_reginfo); - if (!arm_feature(env, ARM_FEATURE_PMSA)) { - define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo); - } else if (arm_feature(env, ARM_FEATURE_V7)) { - define_one_arm_cp_reg(cpu, &id_mpuir_reginfo); + bas &=3D 0xf; } - } =20 - if (arm_feature(env, ARM_FEATURE_MPIDR)) { - ARMCPRegInfo mpidr_cp_reginfo[] =3D { - { .name =3D "MPIDR_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D = 5, - .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D ARM_CP_= NO_RAW }, - REGINFO_SENTINEL - }; -#ifdef CONFIG_USER_ONLY - ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] =3D { - { .name =3D "MPIDR_EL1", - .fixed_bits =3D 0x0000000080000000 }, - REGUSERINFO_SENTINEL - }; - modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); -#endif - define_arm_cp_regs(cpu, mpidr_cp_reginfo); - } - - if (arm_feature(env, ARM_FEATURE_AUXCR)) { - ARMCPRegInfo auxcr_reginfo[] =3D { - { .name =3D "ACTLR_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, - .access =3D PL1_RW, .accessfn =3D access_tacr, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->reset_auxcr }, - { .name =3D "ACTLR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "ACTLR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, - .access =3D PL3_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, auxcr_reginfo); - if (cpu_isar_feature(aa32_ac2, cpu)) { - define_arm_cp_regs(cpu, actlr2_hactlr2_reginfo); + if (bas =3D=3D 0) { + /* This must act as if the watchpoint is disabled */ + return; } - } =20 - if (arm_feature(env, ARM_FEATURE_CBAR)) { - /* - * CBAR is IMPDEF, but common on Arm Cortex-A implementations. - * There are two flavours: - * (1) older 32-bit only cores have a simple 32-bit CBAR - * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a - * 32-bit register visible to AArch32 at a different encoding - * to the "flavour 1" register and with the bits rearranged to - * be able to squash a 64-bit address into the 32-bit view. - * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but - * in future if we support AArch32-only configs of some of the - * AArch64 cores we might need to add a specific feature flag - * to indicate cores with "flavour 2" CBAR. + /* The BAS bits are supposed to be programmed to indicate a contig= uous + * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE wheth= er + * we fire for each byte in the word/doubleword addressed by the W= VR. + * We choose to ignore any non-zero bits after the first range of = 1s. */ - if (arm_feature(env, ARM_FEATURE_AARCH64)) { - /* 32 bit view is [31:18] 0...0 [43:32]. */ - uint32_t cbar32 =3D (extract64(cpu->reset_cbar, 18, 14) << 18) - | extract64(cpu->reset_cbar, 32, 12); - ARMCPRegInfo cbar_reginfo[] =3D { - { .name =3D "CBAR", - .type =3D ARM_CP_CONST, - .cp =3D 15, .crn =3D 15, .crm =3D 3, .opc1 =3D 1, .opc2 = =3D 0, - .access =3D PL1_R, .resetvalue =3D cbar32 }, - { .name =3D "CBAR_EL1", .state =3D ARM_CP_STATE_AA64, - .type =3D ARM_CP_CONST, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 3, .opc2= =3D 0, - .access =3D PL1_R, .resetvalue =3D cpu->reset_cbar }, - REGINFO_SENTINEL - }; - /* We don't implement a r/w 64 bit CBAR currently */ - assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); - define_arm_cp_regs(cpu, cbar_reginfo); - } else { - ARMCPRegInfo cbar =3D { - .name =3D "CBAR", - .cp =3D 15, .crn =3D 15, .crm =3D 0, .opc1 =3D 4, .opc2 = =3D 0, - .access =3D PL1_R|PL3_W, .resetvalue =3D cpu->reset_cbar, - .fieldoffset =3D offsetof(CPUARMState, - cp15.c15_config_base_address) - }; - if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { - cbar.access =3D PL1_R; - cbar.fieldoffset =3D 0; - cbar.type =3D ARM_CP_CONST; - } - define_one_arm_cp_reg(cpu, &cbar); - } + basstart =3D ctz32(bas); + len =3D cto32(bas >> basstart); + wvr +=3D basstart; } =20 - if (arm_feature(env, ARM_FEATURE_VBAR)) { - ARMCPRegInfo vbar_cp_reginfo[] =3D { - { .name =3D "VBAR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .crn =3D 12, .crm =3D 0, .opc1 =3D 0, .opc2 =3D= 0, - .access =3D PL1_RW, .writefn =3D vbar_write, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.vbar_s), - offsetof(CPUARMState, cp15.vbar_ns) }, - .resetvalue =3D 0 }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, vbar_cp_reginfo); - } + cpu_watchpoint_insert(CPU(cpu), wvr, len, flags, + &env->cpu_watchpoint[n]); +} =20 - /* Generic registers whose values depend on the implementation */ - { - ARMCPRegInfo sctlr =3D { - .name =3D "SCTLR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, - .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.sctlr_s), - offsetof(CPUARMState, cp15.sctlr_ns) }, - .writefn =3D sctlr_write, .resetvalue =3D cpu->reset_sctlr, - .raw_writefn =3D raw_write, - }; - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - /* Normally we would always end the TB on an SCTLR write, but = Linux - * arch/arm/mach-pxa/sleep.S expects two instructions following - * an MMU enable to execute from cache. Imitate this behaviou= r. - */ - sctlr.type |=3D ARM_CP_SUPPRESS_TB_END; - } - define_one_arm_cp_reg(cpu, &sctlr); - } +void hw_watchpoint_update_all(ARMCPU *cpu) +{ + int i; + CPUARMState *env =3D &cpu->env; =20 - if (cpu_isar_feature(aa64_lor, cpu)) { - define_arm_cp_regs(cpu, lor_reginfo); - } - if (cpu_isar_feature(aa64_pan, cpu)) { - define_one_arm_cp_reg(cpu, &pan_reginfo); - } -#ifndef CONFIG_USER_ONLY - if (cpu_isar_feature(aa64_ats1e1, cpu)) { - define_arm_cp_regs(cpu, ats1e1_reginfo); - } - if (cpu_isar_feature(aa32_ats1e1, cpu)) { - define_arm_cp_regs(cpu, ats1cp_reginfo); - } -#endif - if (cpu_isar_feature(aa64_uao, cpu)) { - define_one_arm_cp_reg(cpu, &uao_reginfo); - } + /* Completely clear out existing QEMU watchpoints and our array, to + * avoid possible stale entries following migration load. + */ + cpu_watchpoint_remove_all(CPU(cpu), BP_CPU); + memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint)); =20 - if (cpu_isar_feature(aa64_dit, cpu)) { - define_one_arm_cp_reg(cpu, &dit_reginfo); - } - if (cpu_isar_feature(aa64_ssbs, cpu)) { - define_one_arm_cp_reg(cpu, &ssbs_reginfo); + for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) { + hw_watchpoint_update(cpu, i); } +} =20 - if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { - define_arm_cp_regs(cpu, vhe_reginfo); - } +void hw_breakpoint_update(ARMCPU *cpu, int n) +{ + CPUARMState *env =3D &cpu->env; + uint64_t bvr =3D env->cp15.dbgbvr[n]; + uint64_t bcr =3D env->cp15.dbgbcr[n]; + vaddr addr; + int bt; + int flags =3D BP_CPU; =20 - if (cpu_isar_feature(aa64_sve, cpu)) { - define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); - if (arm_feature(env, ARM_FEATURE_EL2)) { - define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); - } else { - define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo); - } - if (arm_feature(env, ARM_FEATURE_EL3)) { - define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); - } + if (env->cpu_breakpoint[n]) { + cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]); + env->cpu_breakpoint[n] =3D NULL; } =20 -#ifdef TARGET_AARCH64 - if (cpu_isar_feature(aa64_pauth, cpu)) { - define_arm_cp_regs(cpu, pauth_reginfo); - } - if (cpu_isar_feature(aa64_rndr, cpu)) { - define_arm_cp_regs(cpu, rndr_reginfo); - } - if (cpu_isar_feature(aa64_tlbirange, cpu)) { - define_arm_cp_regs(cpu, tlbirange_reginfo); - } - if (cpu_isar_feature(aa64_tlbios, cpu)) { - define_arm_cp_regs(cpu, tlbios_reginfo); + if (!extract64(bcr, 0, 1)) { + /* E bit clear : watchpoint disabled */ + return; } -#ifndef CONFIG_USER_ONLY - /* Data Cache clean instructions up to PoP */ - if (cpu_isar_feature(aa64_dcpop, cpu)) { - define_one_arm_cp_reg(cpu, dcpop_reg); =20 - if (cpu_isar_feature(aa64_dcpodp, cpu)) { - define_one_arm_cp_reg(cpu, dcpodp_reg); + bt =3D extract64(bcr, 20, 4); + + switch (bt) { + case 4: /* unlinked address mismatch (reserved if AArch64) */ + case 5: /* linked address mismatch (reserved if AArch64) */ + qemu_log_mask(LOG_UNIMP, + "arm: address mismatch breakpoint types not implemen= ted\n"); + return; + case 0: /* unlinked address match */ + case 1: /* linked address match */ + { + /* Bits [63:49] are hardwired to the value of bit [48]; that is, + * we behave as if the register was sign extended. Bits [1:0] are + * RES0. The BAS field is used to allow setting breakpoints on 16 + * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether + * a bp will fire if the addresses covered by the bp and the addre= sses + * covered by the insn overlap but the insn doesn't start at the + * start of the bp address range. We choose to require the insn and + * the bp to have the same address. The constraints on writing to + * BAS enforced in dbgbcr_write mean we have only four cases: + * 0b0000 =3D> no breakpoint + * 0b0011 =3D> breakpoint on addr + * 0b1100 =3D> breakpoint on addr + 2 + * 0b1111 =3D> breakpoint on addr + * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c). + */ + int bas =3D extract64(bcr, 5, 4); + addr =3D sextract64(bvr, 0, 49) & ~3ULL; + if (bas =3D=3D 0) { + return; + } + if (bas =3D=3D 0xc) { + addr +=3D 2; } + break; } -#endif /*CONFIG_USER_ONLY*/ - - /* - * If full MTE is enabled, add all of the system registers. - * If only "instructions available at EL0" are enabled, - * then define only a RAZ/WI version of PSTATE.TCO. - */ - if (cpu_isar_feature(aa64_mte, cpu)) { - define_arm_cp_regs(cpu, mte_reginfo); - define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); - } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { - define_arm_cp_regs(cpu, mte_tco_ro_reginfo); - define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); + case 2: /* unlinked context ID match */ + case 8: /* unlinked VMID match (reserved if no EL2) */ + case 10: /* unlinked context ID and VMID match (reserved if no EL2) */ + qemu_log_mask(LOG_UNIMP, + "arm: unlinked context breakpoint types not implemen= ted\n"); + return; + case 9: /* linked VMID match (reserved if no EL2) */ + case 11: /* linked context ID and VMID match (reserved if no EL2) */ + case 3: /* linked context ID match */ + default: + /* We must generate no events for Linked context matches (unless + * they are linked to by some other bp/wp, which is handled in + * updates for the linking bp/wp). We choose to also generate no e= vents + * for reserved values. + */ + return; } -#endif =20 - if (cpu_isar_feature(any_predinv, cpu)) { - define_arm_cp_regs(cpu, predinv_reginfo); - } + cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]); +} =20 - if (cpu_isar_feature(any_ccidx, cpu)) { - define_arm_cp_regs(cpu, ccsidr2_reginfo); - } +void hw_breakpoint_update_all(ARMCPU *cpu) +{ + int i; + CPUARMState *env =3D &cpu->env; =20 -#ifndef CONFIG_USER_ONLY - /* - * Register redirections and aliases must be done last, - * after the registers from the other extensions have been defined. + /* Completely clear out existing QEMU breakpoints and our array, to + * avoid possible stale entries following migration load. */ - if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { - define_arm_vh_e2h_redirects_aliases(cpu); + cpu_breakpoint_remove_all(CPU(cpu), BP_CPU); + memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint)); + + for (i =3D 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) { + hw_breakpoint_update(cpu, i); } -#endif } =20 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) @@ -8835,397 +725,6 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Err= or **errp) return cpu_list; } =20 -static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, - void *opaque, int state, int secstate, - int crm, int opc1, int opc2, - const char *name) -{ - /* - * Private utility function for define_one_arm_cp_reg_with_opaque(): - * add a single reginfo struct to the hash table. - */ - uint32_t *key =3D g_new(uint32_t, 1); - ARMCPRegInfo *r2 =3D g_memdup(r, sizeof(ARMCPRegInfo)); - int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0; - int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; - - r2->name =3D g_strdup(name); - /* - * Reset the secure state to the specific incoming state. This is - * necessary as the register may have been defined with both states. - */ - r2->secure =3D secstate; - - if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { - /* - * Register is banked (using both entries in array). - * Overwriting fieldoffset as the array is only used to define - * banked registers but later only fieldoffset is used. - */ - r2->fieldoffset =3D r->bank_fieldoffsets[ns]; - } - - if (state =3D=3D ARM_CP_STATE_AA32) { - if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { - /* - * If the register is banked then we don't need to migrate or - * reset the 32-bit instance in certain cases: - * - * 1) If the register has both 32-bit and 64-bit instances the= n we - * can count on the 64-bit instance taking care of the - * non-secure bank. - * 2) If ARMv8 is enabled then we can count on a 64-bit version - * taking care of the secure bank. This requires that sepa= rate - * 32 and 64-bit definitions are provided. - */ - if ((r->state =3D=3D ARM_CP_STATE_BOTH && ns) || - (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { - r2->type |=3D ARM_CP_ALIAS; - } - } else if ((secstate !=3D r->secure) && !ns) { - /* - * The register is not banked so we only want to allow migrati= on of - * the non-secure instance. - */ - r2->type |=3D ARM_CP_ALIAS; - } - - if (r->state =3D=3D ARM_CP_STATE_BOTH) { - /* We assume it is a cp15 register if the .cp field is left un= set */ - if (r2->cp =3D=3D 0) { - r2->cp =3D 15; - } - -#ifdef HOST_WORDS_BIGENDIAN - if (r2->fieldoffset) { - r2->fieldoffset +=3D sizeof(uint32_t); - } -#endif - } - } - if (state =3D=3D ARM_CP_STATE_AA64) { - /* - * To allow abbreviation of ARMCPRegInfo - * definitions, we treat cp =3D=3D 0 as equivalent to - * the value for "standard guest-visible sysreg". - * STATE_BOTH definitions are also always "standard - * sysreg" in their AArch64 view (the .cp value may - * be non-zero for the benefit of the AArch32 view). - */ - if (r->cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH) { - r2->cp =3D CP_REG_ARM64_SYSREG_CP; - } - *key =3D ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, - r2->opc0, opc1, opc2); - } else { - *key =3D ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); - } - if (opaque) { - r2->opaque =3D opaque; - } - /* - * reginfo passed to helpers is correct for the actual access, - * and is never ARM_CP_STATE_BOTH: - */ - r2->state =3D state; - /* - * Make sure reginfo passed to helpers for wildcarded regs - * has the correct crm/opc1/opc2 for this reg, not CP_ANY: - */ - r2->crm =3D crm; - r2->opc1 =3D opc1; - r2->opc2 =3D opc2; - /* - * By convention, for wildcarded registers only the first - * entry is used for migration; the others are marked as - * ALIAS so we don't try to transfer the register - * multiple times. Special registers (ie NOP/WFI) are - * never migratable and not even raw-accessible. - */ - if ((r->type & ARM_CP_SPECIAL)) { - r2->type |=3D ARM_CP_NO_RAW; - } - if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || - ((r->opc1 =3D=3D CP_ANY) && opc1 !=3D 0) || - ((r->opc2 =3D=3D CP_ANY) && opc2 !=3D 0)) { - r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; - } - - /* - * Check that raw accesses are either forbidden or handled. Note that - * we can't assert this earlier because the setup of fieldoffset for - * banked registers has to be done first. - */ - if (!(r2->type & ARM_CP_NO_RAW)) { - assert(!raw_accessors_invalid(r2)); - } - - /* Overriding of an existing definition must be explicitly requested. = */ - if (!(r->type & ARM_CP_OVERRIDE)) { - ARMCPRegInfo *oldreg; - oldreg =3D g_hash_table_lookup(cpu->cp_regs, key); - if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { - fprintf(stderr, "Register redefined: cp=3D%d %d bit " - "crn=3D%d crm=3D%d opc1=3D%d opc2=3D%d, " - "was %s, now %s\n", r2->cp, 32 + 32 * is64, - r2->crn, r2->crm, r2->opc1, r2->opc2, - oldreg->name, r2->name); - g_assert_not_reached(); - } - } - g_hash_table_insert(cpu->cp_regs, key, r2); -} - - -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *r, void *opaque) -{ - /* - * Define implementations of coprocessor registers. - * We store these in a hashtable because typically - * there are less than 150 registers in a space which - * is 16*16*16*8*8 =3D 262144 in size. - * Wildcarding is supported for the crm, opc1 and opc2 fields. - * If a register is defined twice then the second definition is - * used, so this can be used to define some generic registers and - * then override them with implementation specific variations. - * At least one of the original and the second definition should - * include ARM_CP_OVERRIDE in its type bits -- this is just a guard - * against accidental use. - * - * The state field defines whether the register is to be - * visible in the AArch32 or AArch64 execution state. If the - * state is set to ARM_CP_STATE_BOTH then we synthesise a - * reginfo structure for the AArch32 view, which sees the lower - * 32 bits of the 64 bit register. - * - * Only registers visible in AArch64 may set r->opc0; opc0 cannot - * be wildcarded. AArch64 registers are always considered to be 64 - * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of - * the register, if any. - */ - int crm, opc1, opc2, state; - int crmmin =3D (r->crm =3D=3D CP_ANY) ? 0 : r->crm; - int crmmax =3D (r->crm =3D=3D CP_ANY) ? 15 : r->crm; - int opc1min =3D (r->opc1 =3D=3D CP_ANY) ? 0 : r->opc1; - int opc1max =3D (r->opc1 =3D=3D CP_ANY) ? 7 : r->opc1; - int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2; - int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2; - /* 64 bit registers have only CRm and Opc1 fields */ - assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); - /* op0 only exists in the AArch64 encodings */ - assert((r->state !=3D ARM_CP_STATE_AA32) || (r->opc0 =3D=3D 0)); - /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */ - assert((r->state !=3D ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT)); - /* - * This API is only for Arm's system coprocessors (14 and 15) or - * (M-profile or v7A-and-earlier only) for implementation defined - * coprocessors in the range 0..7. Our decode assumes this, since - * 8..13 can be used for other insns including VFP and Neon. See - * valid_cp() in translate.c. Assert here that we haven't tried - * to use an invalid coprocessor number. - */ - switch (r->state) { - case ARM_CP_STATE_BOTH: - /* 0 has a special meaning, but otherwise the same rules as AA32. = */ - if (r->cp =3D=3D 0) { - break; - } - /* fall through */ - case ARM_CP_STATE_AA32: - if (arm_feature(&cpu->env, ARM_FEATURE_V8) && - !arm_feature(&cpu->env, ARM_FEATURE_M)) { - assert(r->cp >=3D 14 && r->cp <=3D 15); - } else { - assert(r->cp < 8 || (r->cp >=3D 14 && r->cp <=3D 15)); - } - break; - case ARM_CP_STATE_AA64: - assert(r->cp =3D=3D 0 || r->cp =3D=3D CP_REG_ARM64_SYSREG_CP); - break; - default: - g_assert_not_reached(); - } - /* - * The AArch64 pseudocode CheckSystemAccess() specifies that op1 - * encodes a minimum access level for the register. We roll this - * runtime check into our general permission check code, so check - * here that the reginfo's specified permissions are strict enough - * to encompass the generic architectural permission check. - */ - if (r->state !=3D ARM_CP_STATE_AA32) { - int mask =3D 0; - switch (r->opc1) { - case 0: - /* min_EL EL1, but some accessible to EL0 via kernel ABI */ - mask =3D PL0U_R | PL1_RW; - break; - case 1: case 2: - /* min_EL EL1 */ - mask =3D PL1_RW; - break; - case 3: - /* min_EL EL0 */ - mask =3D PL0_RW; - break; - case 4: - case 5: - /* min_EL EL2 */ - mask =3D PL2_RW; - break; - case 6: - /* min_EL EL3 */ - mask =3D PL3_RW; - break; - case 7: - /* min_EL EL1, secure mode only (we don't check the latter) */ - mask =3D PL1_RW; - break; - default: - /* broken reginfo with out-of-range opc1 */ - assert(false); - break; - } - /* assert our permissions are not too lax (stricter is fine) */ - assert((r->access & ~mask) =3D=3D 0); - } - - /* - * Check that the register definition has enough info to handle - * reads and writes if they are permitted. - */ - if (!(r->type & (ARM_CP_SPECIAL | ARM_CP_CONST))) { - if (r->access & PL3_R) { - assert((r->fieldoffset || - (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || - r->readfn); - } - if (r->access & PL3_W) { - assert((r->fieldoffset || - (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || - r->writefn); - } - } - /* Bad type field probably means missing sentinel at end of reg list */ - assert(cptype_valid(r->type)); - for (crm =3D crmmin; crm <=3D crmmax; crm++) { - for (opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { - for (opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { - for (state =3D ARM_CP_STATE_AA32; - state <=3D ARM_CP_STATE_AA64; state++) { - if (r->state !=3D state && r->state !=3D ARM_CP_STATE_= BOTH) { - continue; - } - if (state =3D=3D ARM_CP_STATE_AA32) { - /* - * Under AArch32 CP registers can be common - * (same for secure and non-secure world) or banke= d. - */ - char *name; - - switch (r->secure) { - case ARM_CP_SECSTATE_S: - case ARM_CP_SECSTATE_NS: - add_cpreg_to_hashtable(cpu, r, opaque, state, - r->secure, crm, opc1, o= pc2, - r->name); - break; - default: - name =3D g_strdup_printf("%s_S", r->name); - add_cpreg_to_hashtable(cpu, r, opaque, state, - ARM_CP_SECSTATE_S, - crm, opc1, opc2, name); - g_free(name); - add_cpreg_to_hashtable(cpu, r, opaque, state, - ARM_CP_SECSTATE_NS, - crm, opc1, opc2, r->nam= e); - break; - } - } else { - /* - * AArch64 registers get mapped to non-secure - * instance of AArch32 - */ - add_cpreg_to_hashtable(cpu, r, opaque, state, - ARM_CP_SECSTATE_NS, - crm, opc1, opc2, r->name); - } - } - } - } - } -} - -void define_arm_cp_regs_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *regs, void *opaque) -{ - /* Define a whole list of registers */ - const ARMCPRegInfo *r; - for (r =3D regs; r->type !=3D ARM_CP_SENTINEL; r++) { - define_one_arm_cp_reg_with_opaque(cpu, r, opaque); - } -} - -/* - * Modify ARMCPRegInfo for access from userspace. - * - * This is a data driven modification directed by - * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as - * user-space cannot alter any values and dynamic values pertaining to - * execution state are hidden from user space view anyway. - */ -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods) -{ - const ARMCPRegUserSpaceInfo *m; - ARMCPRegInfo *r; - - for (m =3D mods; m->name; m++) { - GPatternSpec *pat =3D NULL; - if (m->is_glob) { - pat =3D g_pattern_spec_new(m->name); - } - for (r =3D regs; r->type !=3D ARM_CP_SENTINEL; r++) { - if (pat && g_pattern_match_string(pat, r->name)) { - r->type =3D ARM_CP_CONST; - r->access =3D PL0U_R; - r->resetvalue =3D 0; - /* continue */ - } else if (strcmp(r->name, m->name) =3D=3D 0) { - r->type =3D ARM_CP_CONST; - r->access =3D PL0U_R; - r->resetvalue &=3D m->exported_bits; - r->resetvalue |=3D m->fixed_bits; - break; - } - } - if (pat) { - g_pattern_spec_free(pat); - } - } -} - -const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp) -{ - return g_hash_table_lookup(cpregs, &encoded_cp); -} - -void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - /* Helper coprocessor write function for write-ignore registers */ -} - -uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri) -{ - /* Helper coprocessor write function for read-as-zero registers */ - return 0; -} - -void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque) -{ - /* Helper coprocessor reset function for do-nothing-on-reset registers= */ -} - static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write= _type) { /* Return true if it is not valid for us to switch to diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index efcb600992..8c95d7773d 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "cpu.h" +#include "cpregs.h" #include "exec/helper-proto.h" #include "internals.h" #include "exec/exec-all.h" diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index ceac0ee2bd..26ed1f2e02 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" =20 #include "cpu.h" +#include "cpregs.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 8e0e55c1e0..2e626a1a93 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -22,6 +22,7 @@ =20 #include "cpu.h" #include "internals.h" +#include "cpregs.h" #include "disas/disas.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" diff --git a/target/arm/meson.build b/target/arm/meson.build index 3e7cea7604..5fb34c1af1 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -1,7 +1,9 @@ arm_ss =3D ss.source_set() arm_ss.add(files( + 'cpregs.c', 'cpu.c', 'cpu-mmu.c', + 'cpustate-list.c', 'gdbstub.c', 'cpu_tcg.c', )) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 3503ad96c8..3d34723eee 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -20,6 +20,7 @@ arm_ss.add(when: 'CONFIG_TCG', if_true: files( 'translate-neon.c', 'translate-vfp.c', 'helper.c', + 'cpregs.c', 'iwmmxt_helper.c', 'm_helper.c', 'neon_helper.c', --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622823921; cv=none; d=zohomail.com; s=zohoarc; b=HUummAuVAQAS8FlSsFvEbeDdIvyJ2lKLoOwfatpWV6oB+h7QsFvYSpHZ9Ai5kHSgOcLdKi7OwANziTUVGEYrUufrLp0/fLVDkMLKp6WdDUEIquaHNkYw6r5SXrralksry5zXZ3RJEN8/0lbfP+HTOGAnnWbcn3a/Jsc7o+4cbJw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622823921; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zBvCfaGTlADJ93Rev0o5Ivgyc3KA6JcHQPgwZFaWAco=; b=MXfCknGsJejMXP8zfa81L/fITSoEhx+zJJppq6cOCTBYEbqEW1UMT+qCF4jVXFr33WiImVnTkpQArLW/uTru5pJ8oElQOi28qwR3MpOUHPnXXXx8Nho0jCgIKDFf1UEWRE+bysiolcxD8SKyVGE5dg4gYf8Bl0+Lmvwi8M0teAg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622823921810639.4673248319738; Fri, 4 Jun 2021 09:25:21 -0700 (PDT) Received: from localhost ([::1]:59850 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCdN-000602-5R for importer@patchew.org; Fri, 04 Jun 2021 12:25:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48104) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCHW-0007aN-NB for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:02:46 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:35697) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHP-0005h7-Rq for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:02:46 -0400 Received: by mail-wr1-x433.google.com with SMTP id m18so9836576wrv.2 for ; Fri, 04 Jun 2021 09:02:39 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id w23sm7610085wmi.0.2021.06.04.09.02.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:37 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 941A71FFB4; Fri, 4 Jun 2021 16:53:16 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zBvCfaGTlADJ93Rev0o5Ivgyc3KA6JcHQPgwZFaWAco=; b=jFn7/emm2wEAbeqKtehC4ildRuKyLj4XMDN3iPwIHRYhGb3yWor9sGmXqXgRf88OwS zSPRkto9317bz6L5sy9Sai2C3ni6sHpcFf7Oz+rXsZSVSm/BqVTPnKMuTau7/1x80rni OJg02CCg932HUosPXBlSjnlqNBVejSJDB+WqUVkJkZfwam9FM4QNYMFwHRNngUkTNBma Eb2Yxi7cheizAMbEdH2Njd3uKLvNuscNEzw4V5rOrxq/iq+JUSolwn0Gk3wgwVgGX/o7 3TrQcxKOwuyVSlqHL9ZDvSINSaQq01MH+zE8tgdUJESTx1W1MguNvBSQwty4oi9s7FZg 4rvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zBvCfaGTlADJ93Rev0o5Ivgyc3KA6JcHQPgwZFaWAco=; b=Xh9inQWHFnV7XY7nGs3p+pOmle2XLJN1yIJbd44jkluuKDsTQgpF8DWsgwG0yXqbWN 5E0ObnXE+LsI5A9ajfp0hWiKt+zuISVxPwTHCA2P2BJ2/saUYFuw8Z3ygzbGqnTdPsc8 +pWxh85fJ99HYqdUhC+ll1EZarhaYgEPwMBQC42Zl8QyuEZP9Um3QpOQqcscZ8C6b9D7 E5fBhbgBTUGq8fdKj1qqbS3Lc2sRndw4DnGIGkgggGyZ1AZ5BWsTAdeDsInUI2+2Rz/D 9g1makDMXwftJfmILghT+WzpykoB+Vw5BscoLBQiMMbLwL+VZ254Fo5G0NRWPrY4OhfC ic7g== X-Gm-Message-State: AOAM531V4KggVsDlr+mSHHZPso5Fwtrkwh8uo3iWHlj1PMDe9tDoYc80 NJHjM97lYFPP89pvWLJ3n4KgiQ== X-Google-Smtp-Source: ABdhPJx8dOrR1MH5XXZ8eTHK2PQtJ2MAQLxmcAlxzHxI6fEulSC1VyymwSB7NKGKbo8T7F/YXD2qsQ== X-Received: by 2002:adf:8bc9:: with SMTP id w9mr4578743wra.378.1622822558358; Fri, 04 Jun 2021 09:02:38 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 29/99] target/arm: move cpu definitions to common cpu module Date: Fri, 4 Jun 2021 16:52:02 +0100 Message-Id: <20210604155312.15902-30-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-common.c | 41 +++++++++++++++++++++++++++++++++++++++++ target/arm/tcg/helper.c | 29 ----------------------------- target/arm/meson.build | 1 + 3 files changed, 42 insertions(+), 29 deletions(-) create mode 100644 target/arm/cpu-common.c diff --git a/target/arm/cpu-common.c b/target/arm/cpu-common.c new file mode 100644 index 0000000000..0f8ca94815 --- /dev/null +++ b/target/arm/cpu-common.c @@ -0,0 +1,41 @@ +/* + * ARM CPU common definitions + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qom/object.h" +#include "qapi/qapi-commands-machine-target.h" +#include "qapi/error.h" +#include "cpu.h" + +static void arm_cpu_add_definition(gpointer data, gpointer user_data) +{ + ObjectClass *oc =3D data; + CpuDefinitionInfoList **cpu_list =3D user_data; + CpuDefinitionInfo *info; + const char *typename; + + typename =3D object_class_get_name(oc); + info =3D g_malloc0(sizeof(*info)); + info->name =3D g_strndup(typename, + strlen(typename) - strlen("-" TYPE_ARM_CPU)); + info->q_typename =3D g_strdup(typename); + + QAPI_LIST_PREPEND(*cpu_list, info); +} + +CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) +{ + CpuDefinitionInfoList *cpu_list =3D NULL; + GSList *list; + + list =3D object_class_get_list(TYPE_ARM_CPU, false); + g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); + g_slist_free(list); + + return cpu_list; +} diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index 09503db37b..f54ece9b42 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -28,7 +28,6 @@ #include "sysemu/kvm.h" #include "sysemu/tcg.h" #include "qemu/range.h" -#include "qapi/qapi-commands-machine-target.h" #include "qapi/error.h" #include "qemu/guest-random.h" #ifdef CONFIG_TCG @@ -697,34 +696,6 @@ void arm_cpu_list(void) g_slist_free(list); } =20 -static void arm_cpu_add_definition(gpointer data, gpointer user_data) -{ - ObjectClass *oc =3D data; - CpuDefinitionInfoList **cpu_list =3D user_data; - CpuDefinitionInfo *info; - const char *typename; - - typename =3D object_class_get_name(oc); - info =3D g_malloc0(sizeof(*info)); - info->name =3D g_strndup(typename, - strlen(typename) - strlen("-" TYPE_ARM_CPU)); - info->q_typename =3D g_strdup(typename); - - QAPI_LIST_PREPEND(*cpu_list, info); -} - -CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) -{ - CpuDefinitionInfoList *cpu_list =3D NULL; - GSList *list; - - list =3D object_class_get_list(TYPE_ARM_CPU, false); - g_slist_foreach(list, arm_cpu_add_definition, &cpu_list); - g_slist_free(list); - - return cpu_list; -} - static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write= _type) { /* Return true if it is not valid for us to switch to diff --git a/target/arm/meson.build b/target/arm/meson.build index 5fb34c1af1..8d6177c1fb 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -2,6 +2,7 @@ arm_ss =3D ss.source_set() arm_ss.add(files( 'cpregs.c', 'cpu.c', + 'cpu-common.c', 'cpu-mmu.c', 'cpustate-list.c', 'gdbstub.c', --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622826865; cv=none; d=zohomail.com; s=zohoarc; b=Wg6kO8cqo8zECfyOihor8tNx/fZdgNeXLY1l4RFJX4gmBJxmXguYcAx1xhzwZuFmCXAe8mzAUZ7r2hgG7/xa+AufuYZQ1dP0DmwCFafjLk0c18PdYJrgUTZidRGKoJbT3Hv53PoHDQddSKpArA4wdEEACd88/9xB6zHhbz0rUos= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622826865; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PhGU2QFq4twF/mv+HlJpA4XPpT43a+FIEkesYvvyBBs=; b=aTK5T1HHLlkCft1IVPADQesIdA4FvcrWv4Dm9L0c6YPIP25hlBVCT7NbYgsi0o2/b72QuvGxcik9zuQBU6Yg61IIS+GZvyo/7tNL8dG7gXHTQjPUCgzGvkpa3BQcjmHcc52qkjDg08g0bwllXxUSsG0VrfG3r0USLS/3cjmq5nQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622826865803425.74125692501116; Fri, 4 Jun 2021 10:14:25 -0700 (PDT) Received: from localhost ([::1]:55912 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDOp-0001Yc-S6 for importer@patchew.org; Fri, 04 Jun 2021 13:14:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33436) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCkb-00089e-4O for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:32:49 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:46699) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCkY-00028Z-6F for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:32:48 -0400 Received: by mail-wr1-x42d.google.com with SMTP id a11so8036049wrt.13 for ; Fri, 04 Jun 2021 09:32:45 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id k8sm4338274wrp.3.2021.06.04.09.32.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:43 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id AEA5F1FFB5; Fri, 4 Jun 2021 16:53:16 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PhGU2QFq4twF/mv+HlJpA4XPpT43a+FIEkesYvvyBBs=; b=h9SfbPu3XAsH6gTS4+glqg4BVSYXE3ystjWl5UfeVBGIR7c0nvlHUXLPBR58jRfz4G 9ydX21jUr+FtU/Bmpyn2DhonFzPpKhvyOzi5UqpFDsU+54nzoDLzfOInMdSAWIWYsWXZ 2U5/3D3Osjpia3iFEQuNNC/yvlwGeYaRrwPKIhTPfjzsVA91xop7f/4VkypNSlSj+Y0a mdQkMBP2Y9oCnqsdhNBuUiP8LqntVRLCBO2issiELmxV1HNwxgPiZ7xgq/NqBfkY7gZ+ xcJ8RqAFZHpyk9Cksv1lRGmklHilMXwFhxNlaYokwWQpxhQWa6lJ5Cp9wSMKw7x8wk5i 7/4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PhGU2QFq4twF/mv+HlJpA4XPpT43a+FIEkesYvvyBBs=; b=Pp5Wcs5F6B19noLxwnzoFZPBlRMvlKjM6cdcwjHUffcyK/45OnM4x+VTV8BUNnVw5d GSoCGk9ktUiJbtyeE0I1/tQ5TS4p96lvm0l39RHEHZpnQoPN/ZR2IFVT4kwN66LCxqaw KpbFN2X8scRQbTu/q3MRIyou/leCWtTmNGcJnQf0jx1xkUtDKx20kbBT8MOUhm0BGkGw hhe2bcesLyz2hG08QVaI33yKos7+8StFEh3hOdOY8XKWzZpC0/dYy6ehoG60CJ/qwnAZ rucNRLC137/NqJLHHwWyh4rVh1pD0ADgUdeNie89J4W/AnTrXvnLGkVlR5GBx0RAhHDc APFA== X-Gm-Message-State: AOAM531klN4CSZRNKqwUqmytGXX7GRHFPEirCLi+AFZwdYryYC9cYPQ2 oUTt9p5CkiJY6H2W1Ebk9Daq6g== X-Google-Smtp-Source: ABdhPJyAPNd40ouHkfmsLaYOhJcoMcXHosmRWbUmwQLxSIIGk+lntH54mAtX58C4+ZvrYx/zMsblpg== X-Received: by 2002:adf:f1c3:: with SMTP id z3mr4647776wro.375.1622824364849; Fri, 04 Jun 2021 09:32:44 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 30/99] target/arm: only perform TCG cpu and machine inits if TCG enabled Date: Fri, 4 Jun 2021 16:52:03 +0100 Message-Id: <20210604155312.15902-31-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "open list:Overall KVM CPUs" , Richard Henderson , qemu-arm@nongnu.org, Claudio Fontana , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana of note, cpreg lists were previously initialized by TCG first, and then thrown away and replaced with the data coming from KVM. Now we just initialize once, either for TCG or for KVM. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu.c | 32 ++++++++++++++++++-------------- target/arm/kvm.c | 18 +++++++++--------- target/arm/machine.c | 20 +++++++++++++------- 3 files changed, 40 insertions(+), 30 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9e616a15e1..7bb406efd2 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -435,9 +435,11 @@ static void arm_cpu_reset(DeviceState *dev) } #endif =20 - hw_breakpoint_update_all(cpu); - hw_watchpoint_update_all(cpu); - arm_rebuild_hflags(env); + if (tcg_enabled()) { + hw_breakpoint_update_all(cpu); + hw_watchpoint_update_all(cpu); + arm_rebuild_hflags(env); + } } =20 static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, @@ -1318,6 +1320,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) } } =20 +#ifdef CONFIG_TCG { uint64_t scale; =20 @@ -1343,7 +1346,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) cpu->gt_timer[GTIMER_HYPVIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, sc= ale, arm_gt_hvtimer_cb, cpu); } -#endif +#endif /* CONFIG_TCG */ +#endif /* !CONFIG_USER_ONLY */ =20 cpu_exec_realizefn(cs, &local_err); if (local_err !=3D NULL) { @@ -1646,17 +1650,16 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) unset_feature(env, ARM_FEATURE_PMU); } if (arm_feature(env, ARM_FEATURE_PMU)) { - pmu_init(cpu); - - if (!kvm_enabled()) { + if (tcg_enabled()) { + pmu_init(cpu); arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0); arm_register_el_change_hook(cpu, &pmu_post_el_change, 0); - } =20 #ifndef CONFIG_USER_ONLY - cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_= cb, - cpu); + cpu->pmu_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_ti= mer_cb, + cpu); #endif + } } else { cpu->isar.id_aa64dfr0 =3D FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); @@ -1739,10 +1742,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) set_feature(env, ARM_FEATURE_VBAR); } =20 - register_cp_regs_for_features(cpu); - arm_cpu_register_gdb_regs_for_features(cpu); - - init_cpreg_list(cpu); + if (tcg_enabled()) { + register_cp_regs_for_features(cpu); + arm_cpu_register_gdb_regs_for_features(cpu); + init_cpreg_list(cpu); + } =20 #ifndef CONFIG_USER_ONLY MachineState *ms =3D MACHINE(qdev_get_machine()); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index d8381ba224..1b093cc52f 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -431,9 +431,11 @@ static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, ui= nt64_t regidx) return &cpu->cpreg_values[res - cpu->cpreg_indexes]; } =20 -/* Initialize the ARMCPU cpreg list according to the kernel's - * definition of what CPU registers it knows about (and throw away - * the previous TCG-created cpreg list). +/* + * Initialize the ARMCPU cpreg list according to the kernel's + * definition of what CPU registers it knows about. + * + * The parallel for TCG is init_cpreg_list() in tcg/ */ int kvm_arm_init_cpreg_list(ARMCPU *cpu) { @@ -475,12 +477,10 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu) arraylen++; } =20 - cpu->cpreg_indexes =3D g_renew(uint64_t, cpu->cpreg_indexes, arraylen); - cpu->cpreg_values =3D g_renew(uint64_t, cpu->cpreg_values, arraylen); - cpu->cpreg_vmstate_indexes =3D g_renew(uint64_t, cpu->cpreg_vmstate_in= dexes, - arraylen); - cpu->cpreg_vmstate_values =3D g_renew(uint64_t, cpu->cpreg_vmstate_val= ues, - arraylen); + cpu->cpreg_indexes =3D g_new(uint64_t, arraylen); + cpu->cpreg_values =3D g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_indexes =3D g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_values =3D g_new(uint64_t, arraylen); cpu->cpreg_array_len =3D arraylen; cpu->cpreg_vmstate_array_len =3D arraylen; =20 diff --git a/target/arm/machine.c b/target/arm/machine.c index e568662cca..2982e8d7f4 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -2,6 +2,7 @@ #include "cpu.h" #include "qemu/error-report.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "kvm_arm.h" #include "internals.h" #include "migration/cpu.h" @@ -635,7 +636,7 @@ static int cpu_pre_save(void *opaque) { ARMCPU *cpu =3D opaque; =20 - if (!kvm_enabled()) { + if (tcg_enabled()) { pmu_op_start(&cpu->env); } =20 @@ -670,7 +671,7 @@ static int cpu_post_save(void *opaque) { ARMCPU *cpu =3D opaque; =20 - if (!kvm_enabled()) { + if (tcg_enabled()) { pmu_op_finish(&cpu->env); } =20 @@ -689,7 +690,7 @@ static int cpu_pre_load(void *opaque) */ env->irq_line_state =3D UINT32_MAX; =20 - if (!kvm_enabled()) { + if (tcg_enabled()) { pmu_op_start(&cpu->env); } =20 @@ -759,13 +760,13 @@ static int cpu_post_load(void *opaque, int version_id) } } =20 - hw_breakpoint_update_all(cpu); - hw_watchpoint_update_all(cpu); + if (tcg_enabled()) { + hw_breakpoint_update_all(cpu); + hw_watchpoint_update_all(cpu); =20 - if (!kvm_enabled()) { pmu_op_finish(&cpu->env); + arm_rebuild_hflags(&cpu->env); } - arm_rebuild_hflags(&cpu->env); =20 return 0; } @@ -815,8 +816,13 @@ const VMStateDescription vmstate_arm_cpu =3D { VMSTATE_UINT32(env.exception.syndrome, ARMCPU), VMSTATE_UINT32(env.exception.fsr, ARMCPU), VMSTATE_UINT64(env.exception.vaddress, ARMCPU), +#ifdef CONFIG_TCG VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), +#else + VMSTATE_UNUSED(sizeof(QEMUTimer *)), + VMSTATE_UNUSED(sizeof(QEMUTimer *)), +#endif /* CONFIG_TCG */ { .name =3D "power_state", .version_id =3D 0, --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622825642; cv=none; d=zohomail.com; s=zohoarc; b=dXUOWuCodw1R5QhIwzW9x4jhdjocvWwxddmMWEmvlvXmtsQu7ZjyRb+5Bj3+MMdonfxhGgKKButUFtFoZ4kQfH/iMGdMrTmxE+R2SLZz89ZQaNfMbZd6RNn1V8CMtrIsX2hyN6dYVfGpX2spt9nTC/3brfFNZJfHeRl1fImRH5Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622825642; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jHTHPK7EVjgaDIrR0C18cgN5rIwMNuNIJkwhJ0GA1a8=; b=Q3vxwN9caEgxmSCgOs4gebJLYYfXhkUkF9ylhz6KAucjQvL0c7WY+MW9xjHTa2wOsxKucV2UiYkcjE1PluKBozouCz7NxFAMnw4V9B4IUPL2kOoK4IS4qq5e14Z+dr49dfGOsBFeVbNBeLqZkmXP7NpDhCt7hOx/fNRpGKIyU1I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622825642773356.5251639889949; Fri, 4 Jun 2021 09:54:02 -0700 (PDT) Received: from localhost ([::1]:42430 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpD57-0004E1-GF for importer@patchew.org; Fri, 04 Jun 2021 12:54:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52156) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCRZ-0003Sp-Ul for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:13:09 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:40624) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCRQ-0003tH-U7 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:13:09 -0400 Received: by mail-wr1-x435.google.com with SMTP id y7so5220350wrh.7 for ; Fri, 04 Jun 2021 09:12:59 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id c12sm8185315wrr.90.2021.06.04.09.12.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:12:53 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id C61851FFB7; Fri, 4 Jun 2021 16:53:16 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jHTHPK7EVjgaDIrR0C18cgN5rIwMNuNIJkwhJ0GA1a8=; b=adNs06f9qKR686LUipzpgnO+ktPDZyAZz6BNdqaxK+SMqnDN7ZKkXPaZY9cc5aLNvL eccy7qRHtop8bTWC3TEF1cdc5OLXmDj4EoQ3b736zv0F2YFWRcHwb1UogNMLagnLGrXf INh7lnm+32pIVeZF+GGxN+RxD1/BnMMwbAlXiBpqnqIaCgfepnFC15pziSyKfJ6Cq7GT eYdG3GVdDGQqTCEn/643ailO5lRD7kdBHAwkyWh0gd1LG9ro1hcprFvMOycpxacRs4nN jRy678TwxR+h35AkoFBywm0oK/zoFwlprsSPoNt9r0xaPBUWjxfgojhCX6vYNgLRZFvO FEMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jHTHPK7EVjgaDIrR0C18cgN5rIwMNuNIJkwhJ0GA1a8=; b=G4ajDCoEkZSJi7QmutXpBq0hGHsRIRq1m3lY4lroOUBMLGFIbHu4Ljl9PJNZ5i/9uz Qc6JgSZjBD7UTPJmXcnpqgtSa4mp3xwrQZ3NvghqqmRPNsAib0S++6gnVNN8UqRRzzeP aS+92hhWl1xU5f4Nr5G0f7ksPi0Oyqf9Pb6a4DpvkEcyokufeOBtzdZy4goqMJRqdIfo DAJngBJ9TtrCn4L9bbtCRbOYX0eJlZTCJ0jXjYRjmrjkxwASFnZreTiKCU/KO7hkn7Th X0zeX5tmhfTABqoAm8KRmFA0xxDPxpFc6jF7qBLxekainoTeEmCanBAMBv75QAHCesa1 CnDw== X-Gm-Message-State: AOAM531oBHSO/pOdryZGXpl+ZTAOEDjh5d3zcJfAMpmWRju4FXzriG96 TtT7brjv7TNUVyNKc1mJ3NfEtw== X-Google-Smtp-Source: ABdhPJw8JKdOgVEzNPYzlOp1VdPwfqBZPzYztvQfZx+o+A2q3L13WcoxfUg9D1tQvEeDTG9Vnfx67Q== X-Received: by 2002:a5d:4fc6:: with SMTP id h6mr4820531wrw.1.1622823178645; Fri, 04 Jun 2021 09:12:58 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 31/99] target/arm: tcg: add stubs for some helpers for non-tcg builds Date: Fri, 4 Jun 2021 16:52:04 +0100 Message-Id: <20210604155312.15902-32-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana this first armv7m one should go away with proper configuration changes (only enabling possible boards for KVM). Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/tcg-stubs.c | 16 ++++++++++++++++ target/arm/tcg/meson.build | 3 +++ 2 files changed, 19 insertions(+) create mode 100644 target/arm/tcg/tcg-stubs.c diff --git a/target/arm/tcg/tcg-stubs.c b/target/arm/tcg/tcg-stubs.c new file mode 100644 index 0000000000..14220d59a1 --- /dev/null +++ b/target/arm/tcg/tcg-stubs.c @@ -0,0 +1,16 @@ +/* + * QEMU ARM stubs for some TCG helper functions + * + * Copyright 2021 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "cpu.h" + +void write_v7m_exception(CPUARMState *env, uint32_t new_exc) +{ + g_assert_not_reached(); +} diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 3d34723eee..78c34742ec 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -30,6 +30,9 @@ arm_ss.add(when: 'CONFIG_TCG', if_true: files( 'vfp_helper.c', 'crypto_helper.c', 'debug_helper.c', + +), if_false: files( + 'tcg-stubs.c', )) =20 arm_ss.add(when: ['TARGET_AARCH64','CONFIG_TCG'], if_true: files( --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622825299; cv=none; d=zohomail.com; s=zohoarc; b=gnfJ9Kv7UQnnrxJFta3TT8hwZwQqpn/6GiITho9Ech/EdC3XEdl4M3Ka/QzqCQi8VJIP2EoYyxNGcMgVS1w6VDEQ8SGQQkn5IOBE2Yn/5zxBnQDEknjd2QLWFxe8ZXtyeBXnsLiueDkodVHp5P17QfB8LdWRwlo6ZxagWfv+YEU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622825299; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cQ2ujkUUxMglVlDp0hN1+qrHfRzklbjMoNxNds9wJe8=; b=a5oZqaKPHG4vWZG/gLmTz+YIR0IMvAzcvcrtP2La3dr/SWBUezJMVhZyUWyBU6e4W3AtMAvi/LptGmCv5cYBv7OZjZIS3+PJ8YTNO/avpib2/QCEYsg/Thi2+30wM+koD9pJq8Llod7Lj5h8i47vkT/9CcguOzA/lnWeNigzmD0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622825299535343.57767080650547; Fri, 4 Jun 2021 09:48:19 -0700 (PDT) Received: from localhost ([::1]:48578 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCza-0006I6-4f for importer@patchew.org; Fri, 04 Jun 2021 12:48:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48700) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCIC-00004y-Jd for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:29 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:43961) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHm-0005vb-TY for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:28 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 3-20020a05600c0243b029019f2f9b2b8aso5901890wmj.2 for ; Fri, 04 Jun 2021 09:03:01 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id z3sm7565593wrl.13.2021.06.04.09.02.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:56 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id E95011FFB8; Fri, 4 Jun 2021 16:53:16 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cQ2ujkUUxMglVlDp0hN1+qrHfRzklbjMoNxNds9wJe8=; b=MunX7wJysLY09AHzntU+rLHcprV9jFfSAE39+dP0Eh5PnMCxtJTB93rmun2c5Gjesh /hGkWMqW70Mx0C2E8a7r6evcWfT5N3QuVCVpMrHpl1PmJYnNzt2EiaVN1fH0eySaoxIB 5CnamhDHDazJmamWDOEQmGXTpaHpvyg9METK1GlzRDwT/aUb/CzGKTKuB3b3O0UIQg7i 9nUgykAfYKwrygtAy2zgsthNdduBZyUwMXjVFSEW9K6JOpXwCw6JlV+Y3LmPh8Klmo+s 5oBcBR2uY4ZL+HD5rvu8M0F7typmXzUwd1e/ultDHwi6tiQX3/jpcyVNYalvf0r3pqBt mEcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cQ2ujkUUxMglVlDp0hN1+qrHfRzklbjMoNxNds9wJe8=; b=AV2f6KC+MZPD528E+0H1HvHRalV/8Ic0peJ0uZ9Z5yu1tqPt7+GbVoCJOF6PQY19BF N5c02T/fwE21qiNymFm0ohVJwUK62joW1hRPPDC3febqyxlTSkyMHu1MaRrbcM6sEYio R7PJ/DwQicwFtySVBLAuwhiaohgmxcmDJQT12J7iGj76nc1jMc9mIAVvSOqpIZ3D3JDF YMQTLAQgkyicUVBLcwBQMEu/xGN0rsowVmX7EffQGGsfxQ9eIUrmTZWEqRdtycUfR6cF 1kuRvm34dKZyZ7aMFZ/tkGWJIQlysRQLKlCR9xx9imjBUcu1GtzgNIVvJfKInQRnWoWH 86pw== X-Gm-Message-State: AOAM531dHlKfAY/5wTDgVByc3bnV30vIx6y0ev9p6H7D07TJlLV/Ryzw J2VWXm994Wh/z88Md69u0E9PMTy2Wyx3SQ== X-Google-Smtp-Source: ABdhPJynXuvrHSks0BbxL8DrsEVRcFUt2Vt9kXixx7+Sd6r0KPwDniRo1PeSxSDgSm+zNAFpwSTzzA== X-Received: by 2002:a7b:c935:: with SMTP id h21mr4334812wml.183.1622822580448; Fri, 04 Jun 2021 09:03:00 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 32/99] target/arm: move cpsr_read, cpsr_write to cpu_common Date: Fri, 4 Jun 2021 16:52:05 +0100 Message-Id: <20210604155312.15902-33-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana we need as a result to move switch_mode too, so we put an implementation into cpu_user and cpu_sysemu. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 2 + target/arm/cpu-common.c | 192 +++++++++++++++++++++++++++++++++++ target/arm/cpu-sysemu.c | 30 ++++++ target/arm/cpu-user.c | 24 +++++ target/arm/tcg/helper.c | 220 ---------------------------------------- target/arm/meson.build | 3 + 6 files changed, 251 insertions(+), 220 deletions(-) create mode 100644 target/arm/cpu-user.c diff --git a/target/arm/cpu.h b/target/arm/cpu.h index adb9d2828d..c5ead3365f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1390,6 +1390,8 @@ typedef enum CPSRWriteType { void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, CPSRWriteType write_type); =20 +void switch_mode(CPUARMState *env, int mode); + /* Return the current xPSR value. */ static inline uint32_t xpsr_read(CPUARMState *env) { diff --git a/target/arm/cpu-common.c b/target/arm/cpu-common.c index 0f8ca94815..694e5d73f3 100644 --- a/target/arm/cpu-common.c +++ b/target/arm/cpu-common.c @@ -7,10 +7,12 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" #include "qom/object.h" #include "qapi/qapi-commands-machine-target.h" #include "qapi/error.h" #include "cpu.h" +#include "internals.h" =20 static void arm_cpu_add_definition(gpointer data, gpointer user_data) { @@ -39,3 +41,193 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error = **errp) =20 return cpu_list; } + +uint32_t cpsr_read(CPUARMState *env) +{ + int ZF; + ZF =3D (env->ZF =3D=3D 0); + return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | + (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) + | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) + | ((env->condexec_bits & 0xfc) << 8) + | (env->GE << 16) | (env->daif & CPSR_AIF); +} + +static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write= _type) +{ + /* + * Return true if it is not valid for us to switch to + * this CPU mode (ie all the UNPREDICTABLE cases in + * the ARM ARM CPSRWriteByInstr pseudocode). + */ + + /* Changes to or from Hyp via MSR and CPS are illegal. */ + if (write_type =3D=3D CPSRWriteByInstr && + ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_HYP || + mode =3D=3D ARM_CPU_MODE_HYP)) { + return 1; + } + + switch (mode) { + case ARM_CPU_MODE_USR: + return 0; + case ARM_CPU_MODE_SYS: + case ARM_CPU_MODE_SVC: + case ARM_CPU_MODE_ABT: + case ARM_CPU_MODE_UND: + case ARM_CPU_MODE_IRQ: + case ARM_CPU_MODE_FIQ: + /* + * Note that we don't implement the IMPDEF NSACR.RFR which in v7 + * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) + * + * If HCR.TGE is set then changes from Monitor to NS PL1 via MSR + * and CPS are treated as illegal mode changes. + */ + if (write_type =3D=3D CPSRWriteByInstr && + (env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_MON && + (arm_hcr_el2_eff(env) & HCR_TGE)) { + return 1; + } + return 0; + case ARM_CPU_MODE_HYP: + return !arm_is_el2_enabled(env) || arm_current_el(env) < 2; + case ARM_CPU_MODE_MON: + return arm_current_el(env) < 3; + default: + return 1; + } +} + +void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, + CPSRWriteType write_type) +{ + uint32_t changed_daif; + + if (mask & CPSR_NZCV) { + env->ZF =3D (~val) & CPSR_Z; + env->NF =3D val; + env->CF =3D (val >> 29) & 1; + env->VF =3D (val << 3) & 0x80000000; + } + if (mask & CPSR_Q) { + env->QF =3D ((val & CPSR_Q) !=3D 0); + } + if (mask & CPSR_T) { + env->thumb =3D ((val & CPSR_T) !=3D 0); + } + if (mask & CPSR_IT_0_1) { + env->condexec_bits &=3D ~3; + env->condexec_bits |=3D (val >> 25) & 3; + } + if (mask & CPSR_IT_2_7) { + env->condexec_bits &=3D 3; + env->condexec_bits |=3D (val >> 8) & 0xfc; + } + if (mask & CPSR_GE) { + env->GE =3D (val >> 16) & 0xf; + } + + /* + * In a V7 implementation that includes the security extensions but do= es + * not include Virtualization Extensions the SCR.FW and SCR.AW bits co= ntrol + * whether non-secure software is allowed to change the CPSR_F and CPS= R_A + * bits respectively. + * + * In a V8 implementation, it is permitted for privileged software to + * change the CPSR A/F bits regardless of the SCR.AW/FW bits. + */ + if (write_type !=3D CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) = && + arm_feature(env, ARM_FEATURE_EL3) && + !arm_feature(env, ARM_FEATURE_EL2) && + !arm_is_secure(env)) { + + changed_daif =3D (env->daif ^ val) & mask; + + if (changed_daif & CPSR_A) { + /* + * Check to see if we are allowed to change the masking of asy= nc + * abort exceptions from a non-secure state. + */ + if (!(env->cp15.scr_el3 & SCR_AW)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Ignoring attempt to switch CPSR_A flag from= " + "non-secure world with SCR.AW bit clear\n"); + mask &=3D ~CPSR_A; + } + } + + if (changed_daif & CPSR_F) { + /* + * Check to see if we are allowed to change the masking of FIQ + * exceptions from a non-secure state. + */ + if (!(env->cp15.scr_el3 & SCR_FW)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Ignoring attempt to switch CPSR_F flag from= " + "non-secure world with SCR.FW bit clear\n"); + mask &=3D ~CPSR_F; + } + + /* + * Check whether non-maskable FIQ (NMFI) support is enabled. + * If this bit is set software is not allowed to mask + * FIQs, but is allowed to set CPSR_F to 0. + */ + if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && + (val & CPSR_F)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Ignoring attempt to enable CPSR_F flag " + "(non-maskable FIQ [NMFI] support enabled)\n= "); + mask &=3D ~CPSR_F; + } + } + } + + env->daif &=3D ~(CPSR_AIF & mask); + env->daif |=3D val & CPSR_AIF & mask; + + if (write_type !=3D CPSRWriteRaw && + ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { + if ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_USR) { + /* + * Note that we can only get here in USR mode if this is a + * gdb stub write; for this case we follow the architectural + * behaviour for guest writes in USR mode of ignoring an attem= pt + * to switch mode. (Those are caught by translate.c for writes + * triggered by guest instructions.) + */ + mask &=3D ~CPSR_M; + } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { + /* + * Attempt to switch to an invalid mode: this is UNPREDICTABLE= in + * v7, and has defined behaviour in v8: + * + leave CPSR.M untouched + * + allow changes to the other CPSR fields + * + set PSTATE.IL + * For user changes via the GDB stub, we don't set PSTATE.IL, + * as this would be unnecessarily harsh for a user error. + */ + mask &=3D ~CPSR_M; + if (write_type !=3D CPSRWriteByGDBStub && + arm_feature(env, ARM_FEATURE_V8)) { + mask |=3D CPSR_IL; + val |=3D CPSR_IL; + } + qemu_log_mask(LOG_GUEST_ERROR, + "Illegal AArch32 mode switch attempt from %s to = %s\n", + aarch32_mode_name(env->uncached_cpsr), + aarch32_mode_name(val)); + } else { + qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n", + write_type =3D=3D CPSRWriteExceptionReturn ? + "Exception return from AArch32" : + "AArch32 mode switch from", + aarch32_mode_name(env->uncached_cpsr), + aarch32_mode_name(val), env->regs[15]); + switch_mode(env, val & CPSR_M); + } + } + mask &=3D ~CACHED_CPSR_BITS; + env->uncached_cpsr =3D (env->uncached_cpsr & ~mask) | (val & mask); +} diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c index db1c8cb245..3add2c2439 100644 --- a/target/arm/cpu-sysemu.c +++ b/target/arm/cpu-sysemu.c @@ -103,3 +103,33 @@ bool arm_cpu_virtio_is_big_endian(CPUState *cs) cpu_synchronize_state(cs); return arm_cpu_data_is_big_endian(env); } + +void switch_mode(CPUARMState *env, int mode) +{ + int old_mode; + int i; + + old_mode =3D env->uncached_cpsr & CPSR_M; + if (mode =3D=3D old_mode) { + return; + } + + if (old_mode =3D=3D ARM_CPU_MODE_FIQ) { + memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); + memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); + } else if (mode =3D=3D ARM_CPU_MODE_FIQ) { + memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); + memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); + } + + i =3D bank_number(old_mode); + env->banked_r13[i] =3D env->regs[13]; + env->banked_spsr[i] =3D env->spsr; + + i =3D bank_number(mode); + env->regs[13] =3D env->banked_r13[i]; + env->spsr =3D env->banked_spsr[i]; + + env->banked_r14[r14_bank_number(old_mode)] =3D env->regs[14]; + env->regs[14] =3D env->banked_r14[r14_bank_number(mode)]; +} diff --git a/target/arm/cpu-user.c b/target/arm/cpu-user.c new file mode 100644 index 0000000000..a72b7f5703 --- /dev/null +++ b/target/arm/cpu-user.c @@ -0,0 +1,24 @@ +/* + * ARM CPU user-mode only code + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qom/object.h" +#include "qapi/qapi-commands-machine-target.h" +#include "qapi/error.h" +#include "cpu.h" +#include "internals.h" + +void switch_mode(CPUARMState *env, int mode) +{ + ARMCPU *cpu =3D env_archcpu(env); + + if (mode !=3D ARM_CPU_MODE_USR) { + cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); + } +} diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index f54ece9b42..d32f9659bc 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -38,8 +38,6 @@ #include "cpu-mmu.h" #include "cpregs.h" =20 -static void switch_mode(CPUARMState *env, int mode); - static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) { ARMCPU *cpu =3D env_archcpu(env); @@ -696,186 +694,6 @@ void arm_cpu_list(void) g_slist_free(list); } =20 -static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write= _type) -{ - /* Return true if it is not valid for us to switch to - * this CPU mode (ie all the UNPREDICTABLE cases in - * the ARM ARM CPSRWriteByInstr pseudocode). - */ - - /* Changes to or from Hyp via MSR and CPS are illegal. */ - if (write_type =3D=3D CPSRWriteByInstr && - ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_HYP || - mode =3D=3D ARM_CPU_MODE_HYP)) { - return 1; - } - - switch (mode) { - case ARM_CPU_MODE_USR: - return 0; - case ARM_CPU_MODE_SYS: - case ARM_CPU_MODE_SVC: - case ARM_CPU_MODE_ABT: - case ARM_CPU_MODE_UND: - case ARM_CPU_MODE_IRQ: - case ARM_CPU_MODE_FIQ: - /* Note that we don't implement the IMPDEF NSACR.RFR which in v7 - * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.) - */ - /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR - * and CPS are treated as illegal mode changes. - */ - if (write_type =3D=3D CPSRWriteByInstr && - (env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_MON && - (arm_hcr_el2_eff(env) & HCR_TGE)) { - return 1; - } - return 0; - case ARM_CPU_MODE_HYP: - return !arm_is_el2_enabled(env) || arm_current_el(env) < 2; - case ARM_CPU_MODE_MON: - return arm_current_el(env) < 3; - default: - return 1; - } -} - -uint32_t cpsr_read(CPUARMState *env) -{ - int ZF; - ZF =3D (env->ZF =3D=3D 0); - return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) | - (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27) - | (env->thumb << 5) | ((env->condexec_bits & 3) << 25) - | ((env->condexec_bits & 0xfc) << 8) - | (env->GE << 16) | (env->daif & CPSR_AIF); -} - -void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, - CPSRWriteType write_type) -{ - uint32_t changed_daif; - - if (mask & CPSR_NZCV) { - env->ZF =3D (~val) & CPSR_Z; - env->NF =3D val; - env->CF =3D (val >> 29) & 1; - env->VF =3D (val << 3) & 0x80000000; - } - if (mask & CPSR_Q) - env->QF =3D ((val & CPSR_Q) !=3D 0); - if (mask & CPSR_T) - env->thumb =3D ((val & CPSR_T) !=3D 0); - if (mask & CPSR_IT_0_1) { - env->condexec_bits &=3D ~3; - env->condexec_bits |=3D (val >> 25) & 3; - } - if (mask & CPSR_IT_2_7) { - env->condexec_bits &=3D 3; - env->condexec_bits |=3D (val >> 8) & 0xfc; - } - if (mask & CPSR_GE) { - env->GE =3D (val >> 16) & 0xf; - } - - /* In a V7 implementation that includes the security extensions but do= es - * not include Virtualization Extensions the SCR.FW and SCR.AW bits co= ntrol - * whether non-secure software is allowed to change the CPSR_F and CPS= R_A - * bits respectively. - * - * In a V8 implementation, it is permitted for privileged software to - * change the CPSR A/F bits regardless of the SCR.AW/FW bits. - */ - if (write_type !=3D CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) = && - arm_feature(env, ARM_FEATURE_EL3) && - !arm_feature(env, ARM_FEATURE_EL2) && - !arm_is_secure(env)) { - - changed_daif =3D (env->daif ^ val) & mask; - - if (changed_daif & CPSR_A) { - /* Check to see if we are allowed to change the masking of asy= nc - * abort exceptions from a non-secure state. - */ - if (!(env->cp15.scr_el3 & SCR_AW)) { - qemu_log_mask(LOG_GUEST_ERROR, - "Ignoring attempt to switch CPSR_A flag from= " - "non-secure world with SCR.AW bit clear\n"); - mask &=3D ~CPSR_A; - } - } - - if (changed_daif & CPSR_F) { - /* Check to see if we are allowed to change the masking of FIQ - * exceptions from a non-secure state. - */ - if (!(env->cp15.scr_el3 & SCR_FW)) { - qemu_log_mask(LOG_GUEST_ERROR, - "Ignoring attempt to switch CPSR_F flag from= " - "non-secure world with SCR.FW bit clear\n"); - mask &=3D ~CPSR_F; - } - - /* Check whether non-maskable FIQ (NMFI) support is enabled. - * If this bit is set software is not allowed to mask - * FIQs, but is allowed to set CPSR_F to 0. - */ - if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) && - (val & CPSR_F)) { - qemu_log_mask(LOG_GUEST_ERROR, - "Ignoring attempt to enable CPSR_F flag " - "(non-maskable FIQ [NMFI] support enabled)\n= "); - mask &=3D ~CPSR_F; - } - } - } - - env->daif &=3D ~(CPSR_AIF & mask); - env->daif |=3D val & CPSR_AIF & mask; - - if (write_type !=3D CPSRWriteRaw && - ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { - if ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_USR) { - /* Note that we can only get here in USR mode if this is a - * gdb stub write; for this case we follow the architectural - * behaviour for guest writes in USR mode of ignoring an attem= pt - * to switch mode. (Those are caught by translate.c for writes - * triggered by guest instructions.) - */ - mask &=3D ~CPSR_M; - } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { - /* Attempt to switch to an invalid mode: this is UNPREDICTABLE= in - * v7, and has defined behaviour in v8: - * + leave CPSR.M untouched - * + allow changes to the other CPSR fields - * + set PSTATE.IL - * For user changes via the GDB stub, we don't set PSTATE.IL, - * as this would be unnecessarily harsh for a user error. - */ - mask &=3D ~CPSR_M; - if (write_type !=3D CPSRWriteByGDBStub && - arm_feature(env, ARM_FEATURE_V8)) { - mask |=3D CPSR_IL; - val |=3D CPSR_IL; - } - qemu_log_mask(LOG_GUEST_ERROR, - "Illegal AArch32 mode switch attempt from %s to = %s\n", - aarch32_mode_name(env->uncached_cpsr), - aarch32_mode_name(val)); - } else { - qemu_log_mask(CPU_LOG_INT, "%s %s to %s PC 0x%" PRIx32 "\n", - write_type =3D=3D CPSRWriteExceptionReturn ? - "Exception return from AArch32" : - "AArch32 mode switch from", - aarch32_mode_name(env->uncached_cpsr), - aarch32_mode_name(val), env->regs[15]); - switch_mode(env, val & CPSR_M); - } - } - mask &=3D ~CACHED_CPSR_BITS; - env->uncached_cpsr =3D (env->uncached_cpsr & ~mask) | (val & mask); -} - /* Sign/zero extend */ uint32_t HELPER(sxtb16)(uint32_t x) { @@ -916,15 +734,6 @@ uint32_t HELPER(rbit)(uint32_t x) =20 #ifdef CONFIG_USER_ONLY =20 -static void switch_mode(CPUARMState *env, int mode) -{ - ARMCPU *cpu =3D env_archcpu(env); - - if (mode !=3D ARM_CPU_MODE_USR) { - cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); - } -} - uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, uint32_t cur_el, bool secure) { @@ -938,35 +747,6 @@ void aarch64_sync_64_to_32(CPUARMState *env) =20 #else =20 -static void switch_mode(CPUARMState *env, int mode) -{ - int old_mode; - int i; - - old_mode =3D env->uncached_cpsr & CPSR_M; - if (mode =3D=3D old_mode) - return; - - if (old_mode =3D=3D ARM_CPU_MODE_FIQ) { - memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); - memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); - } else if (mode =3D=3D ARM_CPU_MODE_FIQ) { - memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); - memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); - } - - i =3D bank_number(old_mode); - env->banked_r13[i] =3D env->regs[13]; - env->banked_spsr[i] =3D env->spsr; - - i =3D bank_number(mode); - env->regs[13] =3D env->banked_r13[i]; - env->spsr =3D env->banked_spsr[i]; - - env->banked_r14[r14_bank_number(old_mode)] =3D env->regs[14]; - env->regs[14] =3D env->banked_r14[r14_bank_number(mode)]; -} - /* Physical Interrupt Target EL Lookup Table * * [ From ARM ARM section G1.13.4 (Table G1-15) ] diff --git a/target/arm/meson.build b/target/arm/meson.build index 8d6177c1fb..1f7375375e 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -32,6 +32,9 @@ arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( )) =20 arm_user_ss =3D ss.source_set() +arm_user_ss.add(files( + 'cpu-user.c', +)) =20 subdir('tcg') =20 --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622825397; cv=none; d=zohomail.com; s=zohoarc; b=lnAfDi438bKoOXU6oPKpHq977ZpmsZzenTafySby0b57uvFq2nlFehPgkFuodx3Ful1jDtGp3LsqdEJMY21jyHlM9X47PcKjJub8ZmeIPE++hgS4QPz8T1omZbUgN8eZf1QnGiyh6vabgrqX/QnLqqDWJcGsXhZQB0/tmSEq7dw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622825397; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1niJS7hSglD8mEiCtLQ9fXnqmC61tEmzNc7ZOj4a5VQ=; b=P4/l71CwM8enMe3cr5Welqxxr55uFqTHOGP6ourGWe8l0sISCSyDRWknR0t2uTfA14AKtBGb6Jjybv/F1zYnnT6YaVXAeJ7ck4v1mAJySuhEnSSA9BZVEaVftbCdK8AiPKxXCYDpvOyjBgwBhKvo/TZ0G7Pjs2+hZ/WcgrnkCsk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622825397276977.3881884076028; Fri, 4 Jun 2021 09:49:57 -0700 (PDT) Received: from localhost ([::1]:54530 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpD19-0001nt-7q for importer@patchew.org; Fri, 04 Jun 2021 12:49:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52108) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCRX-0003Hs-Cn for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:13:07 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:47041) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCRO-0003si-90 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:13:07 -0400 Received: by mail-wr1-x434.google.com with SMTP id a11so7976638wrt.13 for ; Fri, 04 Jun 2021 09:12:57 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id s128sm6256282wme.6.2021.06.04.09.12.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:12:52 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 0EECA1FFBA; Fri, 4 Jun 2021 16:53:17 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1niJS7hSglD8mEiCtLQ9fXnqmC61tEmzNc7ZOj4a5VQ=; b=kc9bC2bxV3woV3SDD6n85+Q/HlLWOtCSuOMUG86UL7O+llzIcSVvnTAZmB+Fd9Da2u LRFC6IYt2IclWWcT2IAyDzAGbnF77oHyucOCFy+OIeVFYBCkksuaqWLsHbScwbxMG8Cu SdS5Rls9e7TXxeYeJJTk8qhx+QutkRb1EmPc5dy2CrN4VhXn2VRkVESgTHPLpeqq7Qhk IhiqzVG4qT0hYBWBj9zjCDCYHr1Dc80FGpYv2xKYJ+xwAR3c71Rp7gS4KN+JH+2ZIglo towCNMFvSfY3iZNYDdJrBlJq07SJBvuYUh3KlYuQKkHhLlXbMNImJMKcz8H31xVO/pAr mw/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1niJS7hSglD8mEiCtLQ9fXnqmC61tEmzNc7ZOj4a5VQ=; b=X3WLglTi+XCpG1exBECN4TZpbwwp9bNW9SV+yOdCjVOcdtVUjIERNcPLCRuWF8xyc1 7ewi3ge6+qLTi6hMW/I4iIF2j2Kb7VZmrHx9/hivnWMJXkjPlS6CXau3JR74hvEJQ+It BOE6PcjymFFnwJ0RBjNtv6HLYQ+Vu4fVqnrp9/TB9lyKQJqNSOVurT7RVqc/zvgpJVMD ZD/7lshjkeRHz8b5wGYxFuNYVMaVOR2NWWR2O3In62QS5n3lcFUvWRtTj4MygtdNTe0K CM8LjVtxpiQA32kMap0jCx305xtDIlNtHJdDnOokjN4xVWDgVjdhiH6YYPZXhEEL7yVx 2GtQ== X-Gm-Message-State: AOAM533BZ4Y+ShGJV1OwX8TbtxH/6uKvjYubzaDPnK6mbGow4YPN9Jxg kZhzZk9jejwxzgXBJ3qKb8nL2A== X-Google-Smtp-Source: ABdhPJwGKQZxHCbnss+doiH+gk7+Fsl7FF4XKGSs2CnotzPKgF993rmUoaRkKSrc7GN3S+jQy0hoJQ== X-Received: by 2002:a5d:51c3:: with SMTP id n3mr4679437wrv.322.1622823176253; Fri, 04 Jun 2021 09:12:56 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 33/99] target/arm: add temporary stub for arm_rebuild_hflags Date: Fri, 4 Jun 2021 16:52:06 +0100 Message-Id: <20210604155312.15902-34-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana this should go away once the configuration and hw/arm is clean Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- hw/arm/boot.c | 5 ++++- target/arm/arm-powerctl.c | 8 +++++--- target/arm/tcg/tcg-stubs.c | 5 +++++ 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index d7b059225e..13eea9e372 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -26,6 +26,7 @@ #include "qemu/config-file.h" #include "qemu/option.h" #include "qemu/units.h" +#include "sysemu/tcg.h" =20 /* Kernel boot protocol is specified in the kernel docs * Documentation/arm/Booting and Documentation/arm64/booting.txt @@ -796,7 +797,9 @@ static void do_cpu_reset(void *opaque) info->secondary_cpu_reset_hook(cpu, info); } } - arm_rebuild_hflags(env); + if (tcg_enabled()) { + arm_rebuild_hflags(env); + } } } =20 diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index b75f813b40..a00624876c 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -15,6 +15,7 @@ #include "arm-powerctl.h" #include "qemu/log.h" #include "qemu/main-loop.h" +#include "sysemu/tcg.h" =20 #ifndef DEBUG_ARM_POWERCTL #define DEBUG_ARM_POWERCTL 0 @@ -127,9 +128,10 @@ static void arm_set_cpu_on_async_work(CPUState *target= _cpu_state, target_cpu->env.regs[0] =3D info->context_id; } =20 - /* CP15 update requires rebuilding hflags */ - arm_rebuild_hflags(&target_cpu->env); - + if (tcg_enabled()) { + /* CP15 update requires rebuilding hflags */ + arm_rebuild_hflags(&target_cpu->env); + } /* Start the new CPU at the requested address */ cpu_set_pc(target_cpu_state, info->entry); =20 diff --git a/target/arm/tcg/tcg-stubs.c b/target/arm/tcg/tcg-stubs.c index 14220d59a1..332f1b9cfb 100644 --- a/target/arm/tcg/tcg-stubs.c +++ b/target/arm/tcg/tcg-stubs.c @@ -14,3 +14,8 @@ void write_v7m_exception(CPUARMState *env, uint32_t new_e= xc) { g_assert_not_reached(); } + +void arm_rebuild_hflags(CPUARMState *env) +{ + g_assert_not_reached(); +} --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622831247; cv=none; d=zohomail.com; s=zohoarc; b=R9UJ2hbUxMJB1UOMFYuTpnoDPN5mydhBDRftcI0oy9a1VBDWz9ia42hJLbNx0zL9u0gqwXlYPc8/0l8lhKpOOMtxTzTP03wNmLO7is/r94Zx9cMKLG6MAyk8evJ/y0zgtbWVaWIhcTQ/Cav4M3RwcaeBEOsjR7WiHsGvT8xEeDE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622831247; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Z78Q04mjV1LVORaYbrxDOeNi35S151UOcJPYVSic2GM=; b=cZ1GSJnJUVXF6xDggZxhtv5+q1c3xQqQcRQZq9EDcXQijaPnS6nm4u0UsYgEsMlZ8pXaxjwWlRXuWofpanz4DKMz9cD4SpK6aXRGVde7B0FWyccvZ6Ti77/MU0jIiZg83/7RVrstkyFuhZ0llkfOTM1kC0b98JZ/d+y/eRRiWfM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16228312475711023.7613954671326; Fri, 4 Jun 2021 11:27:27 -0700 (PDT) Received: from localhost ([::1]:53278 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpEXV-00064H-PX for importer@patchew.org; Fri, 04 Jun 2021 14:27:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42416) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpET5-00011x-I5 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 14:22:51 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:43682) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpET3-0000Pe-BV for qemu-devel@nongnu.org; Fri, 04 Jun 2021 14:22:51 -0400 Received: by mail-wr1-x430.google.com with SMTP id u7so4751492wrs.10 for ; Fri, 04 Jun 2021 11:22:48 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id x7sm8156479wre.8.2021.06.04.11.22.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 11:22:45 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 2F1161FF7E; Fri, 4 Jun 2021 16:53:17 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z78Q04mjV1LVORaYbrxDOeNi35S151UOcJPYVSic2GM=; b=pLtkDC7HeIb5DEaEcC2s1iOeouuq9rjcmMc+Kk30tJVcE1JDU/4vmaqp5SmD5mCm5M 9hj+qudJQ5wpDfqSmCPh/lyYumOBD6tOLgRFB1M+1ueJlBUnp6v3azI9VPbOlZz5Fpc1 MeAj7MYliku+hdpw28dZui6NktZB51xZ0PkoO2CHR11jOqw7LJlplIo/bXUqvMdDKfc8 9OUCrlAqhWCteLCR2SRfV5R5UwCO61Y162qoxVO/dm2TPwrMkv1rmXeQ0ZofhBbsKShW Vh4SQR2uvuRCKV3QSJDuVYkwaX8mag4gZaEWTcZnZz5Wn0R+7xMiBYpVdPpwOjjD/XEq sPRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z78Q04mjV1LVORaYbrxDOeNi35S151UOcJPYVSic2GM=; b=cC/ZsI4gexJONXIQ1hAt8tutFr5lsbZ1WG3d8OEzm3Mr3N46eRROqxyBgp3LBQoK3u GqE9QLrcavmrJcI1KwyokUA5QqIDB3/Ot+k2U2Qa4daDFvWDG4im9IOBNDq8YWv8yX5p MH5H6yab8lI1wWi5ABmaxry5xX+erfv6N+539GdNYAKLg/K+0m1ZAKIUXH2lnoR8ET7s 4gFM8cOaGv3n9dUlZs7rHK9imavzDUH1toS/W4NOfnKoIciuljGp9Oof9g7mgrkIHSY6 ZVBx26eN9nwKlAXFADNqJRskWQiCzTptqAV72KpngJS//FDifQudVBulr+J+OEbRrlss 8Yqw== X-Gm-Message-State: AOAM530Dsyt1TxifY5NYd6nKSgWEcEF5a6MzqGetCLYDg/u6QEJEszhg vG5F4FNgJQDj4RBeZ8zWco47JA== X-Google-Smtp-Source: ABdhPJxBP2fgeakgxaALJTsQCBA5MGIMYnHyB/Sz+ndNiq80a0IfaBGzZL4/61IFdt+q0TVeu3i9Sg== X-Received: by 2002:adf:ee85:: with SMTP id b5mr5168329wro.95.1622830967926; Fri, 04 Jun 2021 11:22:47 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 34/99] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu Date: Fri, 4 Jun 2021 16:52:07 +0100 Message-Id: <20210604155312.15902-35-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana we will need this for KVM too, especially for Nested support. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-common.c | 68 +++++++++++++++++++++++++++++++++++++++++ target/arm/tcg/helper.c | 68 ----------------------------------------- 2 files changed, 68 insertions(+), 68 deletions(-) diff --git a/target/arm/cpu-common.c b/target/arm/cpu-common.c index 694e5d73f3..040e06392a 100644 --- a/target/arm/cpu-common.c +++ b/target/arm/cpu-common.c @@ -231,3 +231,71 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32= _t mask, mask &=3D ~CACHED_CPSR_BITS; env->uncached_cpsr =3D (env->uncached_cpsr & ~mask) | (val & mask); } + +/* + * Return the effective value of HCR_EL2. + * Bits that are not included here: + * RW (read from SCR_EL3.RW as needed) + */ +uint64_t arm_hcr_el2_eff(CPUARMState *env) +{ + uint64_t ret =3D env->cp15.hcr_el2; + + if (!arm_is_el2_enabled(env)) { + /* + * "This register has no effect if EL2 is not enabled in the + * current Security state". This is ARMv8.4-SecEL2 speak for + * !(SCR_EL3.NS=3D=3D1 || SCR_EL3.EEL2=3D=3D1). + * + * Prior to that, the language was "In an implementation that + * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves + * as if this field is 0 for all purposes other than a direct + * read or write access of HCR_EL2". With lots of enumeration + * on a per-field basis. In current QEMU, this is condition + * is arm_is_secure_below_el3. + * + * Since the v8.4 language applies to the entire register, and + * appears to be backward compatible, use that. + */ + return 0; + } + + /* + * For a cpu that supports both aarch64 and aarch32, we can set bits + * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32. + * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32. + */ + if (!arm_el_is_aa64(env, 2)) { + uint64_t aa32_valid; + + /* + * These bits are up-to-date as of ARMv8.6. + * For HCR, it's easiest to list just the 2 bits that are invalid. + * For HCR2, list those that are valid. + */ + aa32_valid =3D MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ); + aa32_valid |=3D (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNC= E | + HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS); + ret &=3D aa32_valid; + } + + if (ret & HCR_TGE) { + /* These bits are up-to-date as of ARMv8.6. */ + if (ret & HCR_E2H) { + ret &=3D ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | + HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | + HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | + HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE | + HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT | + HCR_TTLBIS | HCR_TTLBOS | HCR_TID5); + } else { + ret |=3D HCR_FMO | HCR_IMO | HCR_AMO; + } + ret &=3D ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | + HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | + HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | + HCR_TLOR); + } + + return ret; +} diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index d32f9659bc..e85e2bfed9 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -261,74 +261,6 @@ static int arm_gdb_set_svereg(CPUARMState *env, uint8_= t *buf, int reg) } #endif /* TARGET_AARCH64 */ =20 -/* - * Return the effective value of HCR_EL2. - * Bits that are not included here: - * RW (read from SCR_EL3.RW as needed) - */ -uint64_t arm_hcr_el2_eff(CPUARMState *env) -{ - uint64_t ret =3D env->cp15.hcr_el2; - - if (!arm_is_el2_enabled(env)) { - /* - * "This register has no effect if EL2 is not enabled in the - * current Security state". This is ARMv8.4-SecEL2 speak for - * !(SCR_EL3.NS=3D=3D1 || SCR_EL3.EEL2=3D=3D1). - * - * Prior to that, the language was "In an implementation that - * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves - * as if this field is 0 for all purposes other than a direct - * read or write access of HCR_EL2". With lots of enumeration - * on a per-field basis. In current QEMU, this is condition - * is arm_is_secure_below_el3. - * - * Since the v8.4 language applies to the entire register, and - * appears to be backward compatible, use that. - */ - return 0; - } - - /* - * For a cpu that supports both aarch64 and aarch32, we can set bits - * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32. - * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32. - */ - if (!arm_el_is_aa64(env, 2)) { - uint64_t aa32_valid; - - /* - * These bits are up-to-date as of ARMv8.6. - * For HCR, it's easiest to list just the 2 bits that are invalid. - * For HCR2, list those that are valid. - */ - aa32_valid =3D MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ); - aa32_valid |=3D (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNC= E | - HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS); - ret &=3D aa32_valid; - } - - if (ret & HCR_TGE) { - /* These bits are up-to-date as of ARMv8.6. */ - if (ret & HCR_E2H) { - ret &=3D ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | - HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | - HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | - HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE | - HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT | - HCR_TTLBIS | HCR_TTLBOS | HCR_TID5); - } else { - ret |=3D HCR_FMO | HCR_IMO | HCR_AMO; - } - ret &=3D ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE | - HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR | - HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM | - HCR_TLOR); - } - - return ret; -} - /* Return the exception level to which exceptions should be taken * via SVEAccessTrap. If an exception should be routed through * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622823994; cv=none; d=zohomail.com; s=zohoarc; b=BaIPX+Ugzg3jY8Mv8xPyonujUR9X+phpagdju4MAbxbow1h0EPVcjdeAgHqG54aB9+vh30uoCKlD6bRax/+m4/F5V/vgglP/vmWBwOdYg0W/Hh71thNy32lByiPBT7Ip5HuhOrr7qG8Jhak6t4vfNfzx9vhcNZzBNvXNaDdm2uI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622823994; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PY6Huc02/raAvhVa8/W7Vw34VyLEbcG3dvBisB2BlcU=; b=gbfDWORjEL218KNkgB4+DJyJJt9lLQRcHRAmzsFaNPH13I/uiXvEewwmaXah08S6xNmTozn9r48vnlzgT77x46Cjd9+l05x3V/lB8R4Jfm1skrwV4dNHCyrODcxV6243zNN+d/DC+CvjneeT8yusTxgMlLvLkrnL4CmkuMPBiCg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162282399426931.100817250888213; Fri, 4 Jun 2021 09:26:34 -0700 (PDT) Received: from localhost ([::1]:35886 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCeX-0000W0-Go for importer@patchew.org; Fri, 04 Jun 2021 12:26:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48230) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCHc-0007jV-6h for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:02:52 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:37687) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHU-0005kQ-TO for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:02:51 -0400 Received: by mail-wr1-x431.google.com with SMTP id i94so4783159wri.4 for ; Fri, 04 Jun 2021 09:02:44 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id q11sm6996052wrx.80.2021.06.04.09.02.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:37 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 537FD1FFBB; Fri, 4 Jun 2021 16:53:17 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PY6Huc02/raAvhVa8/W7Vw34VyLEbcG3dvBisB2BlcU=; b=kjeZQjCZt9waA3GNBOzI5cTzOh2r0A7BOvskq7Ngzd30S6Zlinjpv+LLiHKDv2RjOy m27jcqnnu343yFmvDXJHzkGC62WNCa42I5Uhd2Z1ls5Do5utolGKtORZsa4cNz3QmPee hzhqXqBAeIEZ5O70vMxMBOCsfTufSVSUBd62ruB+zYXZWRpfKCg70pzwWW4Ncmv54pzr XDYPc0DDBr9Q+kMbmWj08Qdf+BApsSyxDzBD5O3fIgNOOm28nMxNLWktfUcO1Ws58Ljt B6DEXf9BV/n5rIxlQPME1r6cIgJh6hSOGP0daw2nNx3kWoQRdh0NfAgbQXPMQvnRjBh3 l0bQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PY6Huc02/raAvhVa8/W7Vw34VyLEbcG3dvBisB2BlcU=; b=DNQFQLEHYm6lHPVEZJlf4rSfoRsw2obLIXCJSXWCdPj//JcZPV45h4Jh25r1zrbzEg Oqa2W+BHUg5hxI+oym4nTWJnjQ6iiE6AFferFWLT2lxQ1sA6D8oCLakEoEL6uuRLO+sm RkfTE11WDzhsvctPjtnGgTwNViyVmTH9W2xxbjlmoa1K5n1DVbDkYkd9SbTwLJfrgljd ZJ1H0yjwBL4yJ7LDmmNfikwYq39b7Upp8mX0hS5rMC3MZv2P23xt8k3BR8Er+Ewm4UzU HbbsXn77+3jJbYUe6UpQa/lf6Co4y+lUBAVY0c4n6PIkOc/NeWEeRcnqGYJGqrJvHWGi mz/A== X-Gm-Message-State: AOAM5317/I9s+P3YD+UV9FU2szZHFgbjrMN7UZjLIJBnfVgcmAQd5/T/ O1cROdnR0jm9ggm4pDKoVCvGH2LM/93IaA== X-Google-Smtp-Source: ABdhPJzQWTz4SPv2KoG/u3iCtQQGiWk2ugKBRH5szv48+RMz1mZYkMDoxa5y3CTEwBkTYooopIKjpA== X-Received: by 2002:a5d:6443:: with SMTP id d3mr4726439wrw.389.1622822563407; Fri, 04 Jun 2021 09:02:43 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 35/99] target/arm: split vfp state setting from tcg helpers Date: Fri, 4 Jun 2021 16:52:08 +0100 Message-Id: <20210604155312.15902-36-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana cpu-vfp.c: vfp_get_fpsr and vfp_set_fpsr are needed also for KVM, so create a new cpu-vfp.c tcg/cpu-vfp.c: vfp_get_fpscr_from_host and vv are TCG-only, so we move the implementation to tcg/cpu-vfp.c Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-vfp.h | 29 +++++ target/arm/cpu-vfp.c | 97 +++++++++++++++++ target/arm/tcg/cpu-vfp.c | 146 +++++++++++++++++++++++++ target/arm/tcg/vfp_helper.c | 210 +----------------------------------- target/arm/meson.build | 1 + target/arm/tcg/meson.build | 1 + 6 files changed, 276 insertions(+), 208 deletions(-) create mode 100644 target/arm/cpu-vfp.h create mode 100644 target/arm/cpu-vfp.c create mode 100644 target/arm/tcg/cpu-vfp.c diff --git a/target/arm/cpu-vfp.h b/target/arm/cpu-vfp.h new file mode 100644 index 0000000000..41e0d710a0 --- /dev/null +++ b/target/arm/cpu-vfp.h @@ -0,0 +1,29 @@ +/* + * ARM VFP floating-point operations internals + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#ifndef CPU_VFP_H +#define CPU_VFP_H + +#include "qemu/osdep.h" +#include "cpu.h" + +uint32_t vfp_get_fpscr_from_host(CPUARMState *env); +void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val); + +#endif /* CPU_VFP_H */ diff --git a/target/arm/cpu-vfp.c b/target/arm/cpu-vfp.c new file mode 100644 index 0000000000..8ea615a916 --- /dev/null +++ b/target/arm/cpu-vfp.c @@ -0,0 +1,97 @@ +/* + * ARM VFP floating-point operations + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "cpu-vfp.h" +#include "sysemu/tcg.h" + +uint32_t vfp_get_fpscr(CPUARMState *env) +{ + uint32_t i, fpscr; + + fpscr =3D env->vfp.xregs[ARM_VFP_FPSCR] + | (env->vfp.vec_len << 16) + | (env->vfp.vec_stride << 20); + + /* + * M-profile LTPSIZE overlaps A-profile Stride; whichever of the + * two is not applicable to this CPU will always be zero. + */ + fpscr |=3D env->v7m.ltpsize << 16; + + if (tcg_enabled()) { + fpscr |=3D vfp_get_fpscr_from_host(env); + } + + i =3D env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3= ]; + fpscr |=3D i ? FPCR_QC : 0; + + return fpscr; +} + +void vfp_set_fpscr(CPUARMState *env, uint32_t val) +{ + /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ + if (!cpu_isar_feature(any_fp16, env_archcpu(env))) { + val &=3D ~FPCR_FZ16; + } + + if (tcg_enabled()) { + vfp_set_fpscr_to_host(env, val); + } + + if (!arm_feature(env, ARM_FEATURE_M)) { + /* + * Short-vector length and stride; on M-profile these bits + * are used for different purposes. + * We can't make this conditional be "if MVFR0.FPShVec !=3D 0", + * because in v7A no-short-vector-support cores still had to + * allow Stride/Len to be written with the only effect that + * some insns are required to UNDEF if the guest sets them. + * + * TODO: if M-profile MVE implemented, set LTPSIZE. + */ + env->vfp.vec_len =3D extract32(val, 16, 3); + env->vfp.vec_stride =3D extract32(val, 20, 2); + } + + if (arm_feature(env, ARM_FEATURE_NEON)) { + /* + * The bit we set within fpscr_q is arbitrary; the register as a + * whole being zero/non-zero is what counts. + * TODO: M-profile MVE also has a QC bit. + */ + env->vfp.qc[0] =3D val & FPCR_QC; + env->vfp.qc[1] =3D 0; + env->vfp.qc[2] =3D 0; + env->vfp.qc[3] =3D 0; + } + + /* + * We don't implement trapped exception handling, so the + * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) + * + * The exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in + * fp_status; QC, Len and Stride are stored separately earlier. + * Clear out all of those and the RES0 bits: only NZCV, AHP, DN, + * FZ, RMode and FZ16 are kept in vfp.xregs[FPSCR]. + */ + env->vfp.xregs[ARM_VFP_FPSCR] =3D val & 0xf7c80000; +} diff --git a/target/arm/tcg/cpu-vfp.c b/target/arm/tcg/cpu-vfp.c new file mode 100644 index 0000000000..bb88abf1ba --- /dev/null +++ b/target/arm/tcg/cpu-vfp.c @@ -0,0 +1,146 @@ +/* + * ARM VFP floating-point operations + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "qemu/log.h" +#include "internals.h" +#include "fpu/softfloat.h" +#include "cpu-vfp.h" + +/* Convert host exception flags to vfp form. */ +static inline int vfp_exceptbits_from_host(int host_bits) +{ + int target_bits =3D 0; + + if (host_bits & float_flag_invalid) { + target_bits |=3D 1; + } + if (host_bits & float_flag_divbyzero) { + target_bits |=3D 2; + } + if (host_bits & float_flag_overflow) { + target_bits |=3D 4; + } + if (host_bits & (float_flag_underflow | float_flag_output_denormal)) { + target_bits |=3D 8; + } + if (host_bits & float_flag_inexact) { + target_bits |=3D 0x10; + } + if (host_bits & float_flag_input_denormal) { + target_bits |=3D 0x80; + } + return target_bits; +} + +/* Convert vfp exception flags to target form. */ +static inline int vfp_exceptbits_to_host(int target_bits) +{ + int host_bits =3D 0; + + if (target_bits & 1) { + host_bits |=3D float_flag_invalid; + } + if (target_bits & 2) { + host_bits |=3D float_flag_divbyzero; + } + if (target_bits & 4) { + host_bits |=3D float_flag_overflow; + } + if (target_bits & 8) { + host_bits |=3D float_flag_underflow; + } + if (target_bits & 0x10) { + host_bits |=3D float_flag_inexact; + } + if (target_bits & 0x80) { + host_bits |=3D float_flag_input_denormal; + } + return host_bits; +} + +uint32_t vfp_get_fpscr_from_host(CPUARMState *env) +{ + uint32_t i; + + i =3D get_float_exception_flags(&env->vfp.fp_status); + i |=3D get_float_exception_flags(&env->vfp.standard_fp_status); + /* FZ16 does not generate an input denormal exception. */ + i |=3D (get_float_exception_flags(&env->vfp.fp_status_f16) + & ~float_flag_input_denormal); + i |=3D (get_float_exception_flags(&env->vfp.standard_fp_status_f16) + & ~float_flag_input_denormal); + return vfp_exceptbits_from_host(i); +} + +void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val) +{ + int i; + uint32_t changed =3D env->vfp.xregs[ARM_VFP_FPSCR]; + + changed ^=3D val; + if (changed & (3 << 22)) { + i =3D (val >> 22) & 3; + switch (i) { + case FPROUNDING_TIEEVEN: + i =3D float_round_nearest_even; + break; + case FPROUNDING_POSINF: + i =3D float_round_up; + break; + case FPROUNDING_NEGINF: + i =3D float_round_down; + break; + case FPROUNDING_ZERO: + i =3D float_round_to_zero; + break; + } + set_float_rounding_mode(i, &env->vfp.fp_status); + set_float_rounding_mode(i, &env->vfp.fp_status_f16); + } + if (changed & FPCR_FZ16) { + bool ftz_enabled =3D val & FPCR_FZ16; + set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16); + set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16); + set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16); + set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status= _f16); + } + if (changed & FPCR_FZ) { + bool ftz_enabled =3D val & FPCR_FZ; + set_flush_to_zero(ftz_enabled, &env->vfp.fp_status); + set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status); + } + if (changed & FPCR_DN) { + bool dnan_enabled =3D val & FPCR_DN; + set_default_nan_mode(dnan_enabled, &env->vfp.fp_status); + set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16); + } + + /* + * The exception flags are ORed together when we read fpscr so we + * only need to preserve the current state in one of our + * float_status values. + */ + i =3D vfp_exceptbits_to_host(val); + set_float_exception_flags(i, &env->vfp.fp_status); + set_float_exception_flags(0, &env->vfp.fp_status_f16); + set_float_exception_flags(0, &env->vfp.standard_fp_status); + set_float_exception_flags(0, &env->vfp.standard_fp_status_f16); +} diff --git a/target/arm/tcg/vfp_helper.c b/target/arm/tcg/vfp_helper.c index 01b9d8557f..521719f327 100644 --- a/target/arm/tcg/vfp_helper.c +++ b/target/arm/tcg/vfp_helper.c @@ -30,220 +30,14 @@ Single precision routines have a "s" suffix, double precision a "d" suffix. */ =20 -#ifdef CONFIG_TCG - -/* Convert host exception flags to vfp form. */ -static inline int vfp_exceptbits_from_host(int host_bits) -{ - int target_bits =3D 0; - - if (host_bits & float_flag_invalid) { - target_bits |=3D 1; - } - if (host_bits & float_flag_divbyzero) { - target_bits |=3D 2; - } - if (host_bits & float_flag_overflow) { - target_bits |=3D 4; - } - if (host_bits & (float_flag_underflow | float_flag_output_denormal)) { - target_bits |=3D 8; - } - if (host_bits & float_flag_inexact) { - target_bits |=3D 0x10; - } - if (host_bits & float_flag_input_denormal) { - target_bits |=3D 0x80; - } - return target_bits; -} - -/* Convert vfp exception flags to target form. */ -static inline int vfp_exceptbits_to_host(int target_bits) -{ - int host_bits =3D 0; - - if (target_bits & 1) { - host_bits |=3D float_flag_invalid; - } - if (target_bits & 2) { - host_bits |=3D float_flag_divbyzero; - } - if (target_bits & 4) { - host_bits |=3D float_flag_overflow; - } - if (target_bits & 8) { - host_bits |=3D float_flag_underflow; - } - if (target_bits & 0x10) { - host_bits |=3D float_flag_inexact; - } - if (target_bits & 0x80) { - host_bits |=3D float_flag_input_denormal; - } - return host_bits; -} - -static uint32_t vfp_get_fpscr_from_host(CPUARMState *env) -{ - uint32_t i; - - i =3D get_float_exception_flags(&env->vfp.fp_status); - i |=3D get_float_exception_flags(&env->vfp.standard_fp_status); - /* FZ16 does not generate an input denormal exception. */ - i |=3D (get_float_exception_flags(&env->vfp.fp_status_f16) - & ~float_flag_input_denormal); - i |=3D (get_float_exception_flags(&env->vfp.standard_fp_status_f16) - & ~float_flag_input_denormal); - return vfp_exceptbits_from_host(i); -} - -static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val) -{ - int i; - uint32_t changed =3D env->vfp.xregs[ARM_VFP_FPSCR]; - - changed ^=3D val; - if (changed & (3 << 22)) { - i =3D (val >> 22) & 3; - switch (i) { - case FPROUNDING_TIEEVEN: - i =3D float_round_nearest_even; - break; - case FPROUNDING_POSINF: - i =3D float_round_up; - break; - case FPROUNDING_NEGINF: - i =3D float_round_down; - break; - case FPROUNDING_ZERO: - i =3D float_round_to_zero; - break; - } - set_float_rounding_mode(i, &env->vfp.fp_status); - set_float_rounding_mode(i, &env->vfp.fp_status_f16); - } - if (changed & FPCR_FZ16) { - bool ftz_enabled =3D val & FPCR_FZ16; - set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16); - set_flush_to_zero(ftz_enabled, &env->vfp.standard_fp_status_f16); - set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16); - set_flush_inputs_to_zero(ftz_enabled, &env->vfp.standard_fp_status= _f16); - } - if (changed & FPCR_FZ) { - bool ftz_enabled =3D val & FPCR_FZ; - set_flush_to_zero(ftz_enabled, &env->vfp.fp_status); - set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status); - } - if (changed & FPCR_DN) { - bool dnan_enabled =3D val & FPCR_DN; - set_default_nan_mode(dnan_enabled, &env->vfp.fp_status); - set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16); - } - - /* - * The exception flags are ORed together when we read fpscr so we - * only need to preserve the current state in one of our - * float_status values. - */ - i =3D vfp_exceptbits_to_host(val); - set_float_exception_flags(i, &env->vfp.fp_status); - set_float_exception_flags(0, &env->vfp.fp_status_f16); - set_float_exception_flags(0, &env->vfp.standard_fp_status); - set_float_exception_flags(0, &env->vfp.standard_fp_status_f16); -} - -#else - -static uint32_t vfp_get_fpscr_from_host(CPUARMState *env) -{ - return 0; -} - -static void vfp_set_fpscr_to_host(CPUARMState *env, uint32_t val) -{ -} - -#endif - uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) { - uint32_t i, fpscr; - - fpscr =3D env->vfp.xregs[ARM_VFP_FPSCR] - | (env->vfp.vec_len << 16) - | (env->vfp.vec_stride << 20); - - /* - * M-profile LTPSIZE overlaps A-profile Stride; whichever of the - * two is not applicable to this CPU will always be zero. - */ - fpscr |=3D env->v7m.ltpsize << 16; - - fpscr |=3D vfp_get_fpscr_from_host(env); - - i =3D env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3= ]; - fpscr |=3D i ? FPCR_QC : 0; - - return fpscr; -} - -uint32_t vfp_get_fpscr(CPUARMState *env) -{ - return HELPER(vfp_get_fpscr)(env); + return vfp_get_fpscr(env); } =20 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) { - /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ - if (!cpu_isar_feature(any_fp16, env_archcpu(env))) { - val &=3D ~FPCR_FZ16; - } - - vfp_set_fpscr_to_host(env, val); - - if (!arm_feature(env, ARM_FEATURE_M)) { - /* - * Short-vector length and stride; on M-profile these bits - * are used for different purposes. - * We can't make this conditional be "if MVFR0.FPShVec !=3D 0", - * because in v7A no-short-vector-support cores still had to - * allow Stride/Len to be written with the only effect that - * some insns are required to UNDEF if the guest sets them. - * - * TODO: if M-profile MVE implemented, set LTPSIZE. - */ - env->vfp.vec_len =3D extract32(val, 16, 3); - env->vfp.vec_stride =3D extract32(val, 20, 2); - } - - if (arm_feature(env, ARM_FEATURE_NEON)) { - /* - * The bit we set within fpscr_q is arbitrary; the register as a - * whole being zero/non-zero is what counts. - * TODO: M-profile MVE also has a QC bit. - */ - env->vfp.qc[0] =3D val & FPCR_QC; - env->vfp.qc[1] =3D 0; - env->vfp.qc[2] =3D 0; - env->vfp.qc[3] =3D 0; - } - - /* - * We don't implement trapped exception handling, so the - * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) - * - * The exception flags IOC|DZC|OFC|UFC|IXC|IDC are stored in - * fp_status; QC, Len and Stride are stored separately earlier. - * Clear out all of those and the RES0 bits: only NZCV, AHP, DN, - * FZ, RMode and FZ16 are kept in vfp.xregs[FPSCR]. - */ - env->vfp.xregs[ARM_VFP_FPSCR] =3D val & 0xf7c80000; -} - -void vfp_set_fpscr(CPUARMState *env, uint32_t val) -{ - HELPER(vfp_set_fpscr)(env, val); + vfp_set_fpscr(env, val); } =20 #ifdef CONFIG_TCG diff --git a/target/arm/meson.build b/target/arm/meson.build index 1f7375375e..4bc44e1db2 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -4,6 +4,7 @@ arm_ss.add(files( 'cpu.c', 'cpu-common.c', 'cpu-mmu.c', + 'cpu-vfp.c', 'cpustate-list.c', 'gdbstub.c', 'cpu_tcg.c', diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 78c34742ec..64a86fd94c 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -21,6 +21,7 @@ arm_ss.add(when: 'CONFIG_TCG', if_true: files( 'translate-vfp.c', 'helper.c', 'cpregs.c', + 'cpu-vfp.c', 'iwmmxt_helper.c', 'm_helper.c', 'neon_helper.c', --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622823370; cv=none; d=zohomail.com; s=zohoarc; b=HNb54HCzMxBLXHAC52pqM9Mdc4cnyGuL4oQ9ka77Vd9unjRYrrNNvPz5G4MBdP9WU6ki9XvwToY9roTTqZ7SvHDnwufgrg+dUuK9vkvf8KKZB9bppLnMlLtf8oYCkl+RB1aqWjiuOWd272JiX33jVGv5+SHnbtjRN5BuimCnmdE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622823370; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Cn3xyAgideBI5BCmgu7Gt0NwbqrNIOTnH45mDz31IIw=; b=TmPu811D1pseGtZofe9q8w0LTSnSB2QA5LJywX1rFinG5Mpk85q/LZWxnDy1PnMquLUdK9UEN5k3dTM1oq1ToTqrHxDGdfjgLQ2cmA4OR/zyfA/Vd1KLhoXpXXD5ibFNAD9WwbqkyrYqYwCzuwV3XLrBmwdOxQ5s7343Y0TjU+o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622823370215371.1206090635545; Fri, 4 Jun 2021 09:16:10 -0700 (PDT) Received: from localhost ([::1]:55844 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCUS-0000W0-Ux for importer@patchew.org; Fri, 04 Jun 2021 12:16:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44724) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8g-0003Hd-VL for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:39 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:46609) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8d-00009c-OD for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:38 -0400 Received: by mail-wm1-x332.google.com with SMTP id h22-20020a05600c3516b02901a826f84095so915817wmq.5 for ; Fri, 04 Jun 2021 08:53:35 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id l16sm9356859wmj.47.2021.06.04.08.53.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:31 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 7295E1FFBC; Fri, 4 Jun 2021 16:53:17 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Cn3xyAgideBI5BCmgu7Gt0NwbqrNIOTnH45mDz31IIw=; b=lmCmFVu9dBcfNaXqIg9xLnLz+tn44MNuz1dERwHLoNAp82MxyQSMST+TUpv0nodjLo 54e+QIEwYcLla+Y8P4Z9bfwiFKmHe9lEfGrH8zqcIgcD/FjOY/pobgtVE4YGQ+mxlSs1 kUDBHI/LimmZAFUj3FRbVIIAER5YsdHugARyQ+6LvGND8l5JetIJD2+mj09gLhcYYndt m16/noRk3QkM3dH3bXoQCDly5DF8v4jxskroqA4ZLpiqcggCNCr2qVibTgUM7WPkWRQt TW0QXBii/yUnvvkLievncYSMP9aezfqVN9+OhreBMqwfdBDgacCRHXt2qF+ZjICLFg9Z TEhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Cn3xyAgideBI5BCmgu7Gt0NwbqrNIOTnH45mDz31IIw=; b=EPdbJwOaTupMydd9DpCtaBxgVTMSaixiFBrPwjhZ4fHAJg+6xHMgvesiUMmU/S+O0M BTyus8qBiIUBK2PVbhz03Nvuez8jHzQfuW1wHf1Vazy0gDMPEauefH3wfSleZbu01Yud g6WLBDe/e2b/wE2vs/tFrTtfEIEQ5ZmDq0o1SlrwZEpL7iMTOxylh6Q8VbR/NAaQSRsE xyOdXAJpeMYVna77AYoJroFCZpObIgHfRRSSD6tp0fpipXXgASKR4sVJ/r203wE79r1H E1P99MkcZJvNZ0R/oOV9FbnNrKN6MdKtLYfbS2u2VLY4lV5vFxZkircDay5yaoO2nlW6 llDQ== X-Gm-Message-State: AOAM530CAEZASON1sei8MgBXolxFe66Fmr9I7ADzZ+9lOXDwcX7dIMXi z2Q2OJZkEEBpUMSQCdpcm8FxkA== X-Google-Smtp-Source: ABdhPJwBGgHeEMNoNt4zieUKiCx3Xl7I2U0WrGF3GT77SV0h/Bfo0zjl50HLoqof395zvHzWxUbNsA== X-Received: by 2002:a1c:7402:: with SMTP id p2mr4273222wmc.88.1622822014181; Fri, 04 Jun 2021 08:53:34 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 36/99] target/arm: move arm_mmu_idx* to cpu-mmu Date: Fri, 4 Jun 2021 16:52:09 +0100 Message-Id: <20210604155312.15902-37-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-mmu.c | 95 +++++++++++++++++++++++++++++++++++++++++ target/arm/tcg/helper.c | 95 ----------------------------------------- 2 files changed, 95 insertions(+), 95 deletions(-) diff --git a/target/arm/cpu-mmu.c b/target/arm/cpu-mmu.c index f463f8458e..c6ac90a61e 100644 --- a/target/arm/cpu-mmu.c +++ b/target/arm/cpu-mmu.c @@ -122,3 +122,98 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, u= int64_t va, .using64k =3D using64k, }; } + +/* Return the exception level we're running at if this is our mmu_idx */ +int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) +{ + if (mmu_idx & ARM_MMU_IDX_M) { + return mmu_idx & ARM_MMU_IDX_M_PRIV; + } + + switch (mmu_idx) { + case ARMMMUIdx_E10_0: + case ARMMMUIdx_E20_0: + case ARMMMUIdx_SE10_0: + case ARMMMUIdx_SE20_0: + return 0; + case ARMMMUIdx_E10_1: + case ARMMMUIdx_E10_1_PAN: + case ARMMMUIdx_SE10_1: + case ARMMMUIdx_SE10_1_PAN: + return 1; + case ARMMMUIdx_E2: + case ARMMMUIdx_E20_2: + case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_SE2: + case ARMMMUIdx_SE20_2: + case ARMMMUIdx_SE20_2_PAN: + return 2; + case ARMMMUIdx_SE3: + return 3; + default: + g_assert_not_reached(); + } +} + +#ifndef CONFIG_TCG +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +{ + g_assert_not_reached(); +} +#endif + +ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) +{ + ARMMMUIdx idx; + uint64_t hcr; + + if (arm_feature(env, ARM_FEATURE_M)) { + return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); + } + + /* See ARM pseudo-function ELIsInHost. */ + switch (el) { + case 0: + hcr =3D arm_hcr_el2_eff(env); + if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { + idx =3D ARMMMUIdx_E20_0; + } else { + idx =3D ARMMMUIdx_E10_0; + } + break; + case 1: + if (env->pstate & PSTATE_PAN) { + idx =3D ARMMMUIdx_E10_1_PAN; + } else { + idx =3D ARMMMUIdx_E10_1; + } + break; + case 2: + /* Note that TGE does not apply at EL2. */ + if (arm_hcr_el2_eff(env) & HCR_E2H) { + if (env->pstate & PSTATE_PAN) { + idx =3D ARMMMUIdx_E20_2_PAN; + } else { + idx =3D ARMMMUIdx_E20_2; + } + } else { + idx =3D ARMMMUIdx_E2; + } + break; + case 3: + return ARMMMUIdx_SE3; + default: + g_assert_not_reached(); + } + + if (arm_is_secure_below_el3(env)) { + idx &=3D ~ARM_MMU_IDX_A_NS; + } + + return idx; +} + +ARMMMUIdx arm_mmu_idx(CPUARMState *env) +{ + return arm_mmu_idx_el(env, arm_current_el(env)); +} diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index e85e2bfed9..a4630b4039 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -2093,101 +2093,6 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 0; } =20 -/* Return the exception level we're running at if this is our mmu_idx */ -int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) -{ - if (mmu_idx & ARM_MMU_IDX_M) { - return mmu_idx & ARM_MMU_IDX_M_PRIV; - } - - switch (mmu_idx) { - case ARMMMUIdx_E10_0: - case ARMMMUIdx_E20_0: - case ARMMMUIdx_SE10_0: - case ARMMMUIdx_SE20_0: - return 0; - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_SE10_1: - case ARMMMUIdx_SE10_1_PAN: - return 1; - case ARMMMUIdx_E2: - case ARMMMUIdx_E20_2: - case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_SE2: - case ARMMMUIdx_SE20_2: - case ARMMMUIdx_SE20_2_PAN: - return 2; - case ARMMMUIdx_SE3: - return 3; - default: - g_assert_not_reached(); - } -} - -#ifndef CONFIG_TCG -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) -{ - g_assert_not_reached(); -} -#endif - -ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) -{ - ARMMMUIdx idx; - uint64_t hcr; - - if (arm_feature(env, ARM_FEATURE_M)) { - return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); - } - - /* See ARM pseudo-function ELIsInHost. */ - switch (el) { - case 0: - hcr =3D arm_hcr_el2_eff(env); - if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { - idx =3D ARMMMUIdx_E20_0; - } else { - idx =3D ARMMMUIdx_E10_0; - } - break; - case 1: - if (env->pstate & PSTATE_PAN) { - idx =3D ARMMMUIdx_E10_1_PAN; - } else { - idx =3D ARMMMUIdx_E10_1; - } - break; - case 2: - /* Note that TGE does not apply at EL2. */ - if (arm_hcr_el2_eff(env) & HCR_E2H) { - if (env->pstate & PSTATE_PAN) { - idx =3D ARMMMUIdx_E20_2_PAN; - } else { - idx =3D ARMMMUIdx_E20_2; - } - } else { - idx =3D ARMMMUIdx_E2; - } - break; - case 3: - return ARMMMUIdx_SE3; - default: - g_assert_not_reached(); - } - - if (arm_is_secure_below_el3(env)) { - idx &=3D ~ARM_MMU_IDX_A_NS; - } - - return idx; -} - -ARMMMUIdx arm_mmu_idx(CPUARMState *env) -{ - return arm_mmu_idx_el(env, arm_current_el(env)); -} - #ifndef CONFIG_USER_ONLY ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) { --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622831053; cv=none; d=zohomail.com; s=zohoarc; b=U/mGYVJW3pqjdFWoUx+UOV28pxHkCuMaczbI2YQjidfX0QunVir46ZFN7AonXEwGyQdsbPdVY7MB2tw6UhjQKowpT9pyTcQcZQS/A/p368u8lj//kMwN0P2yflemNajPkgjmH6SOlmw1KPDI/sHA7FosDW6IJeS2oAcR7x6/NPI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622831053; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Fs4mHduSC7s6AOHhF5ZFH6VJI9TQw9c8e27N4ga4IHk=; b=S9GXq/k4wfg54DGXQod7cj7AxPUD+fy5kLBGkdCL/WyfoNZzKAad8nLw4npH/5PRS+bnIcScGM3DfZDoIjbbvORS+F3mByTLubFayTi4fx8TM7i8N66rLHxLuCsaAAtSaJLuZVZWEXmF48xdMzOqizpt9A3W6r2VBrRUhUboiaA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622831053924874.775920257969; Fri, 4 Jun 2021 11:24:13 -0700 (PDT) Received: from localhost ([::1]:38212 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpEUO-0004Pn-Pu for importer@patchew.org; Fri, 04 Jun 2021 14:24:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42370) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpET4-0000w1-6Q for qemu-devel@nongnu.org; Fri, 04 Jun 2021 14:22:50 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:46755) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpET0-0000Nr-RO for qemu-devel@nongnu.org; Fri, 04 Jun 2021 14:22:49 -0400 Received: by mail-wm1-x32f.google.com with SMTP id h22-20020a05600c3516b02901a826f84095so1132628wmq.5 for ; Fri, 04 Jun 2021 11:22:46 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id q19sm9085241wmc.44.2021.06.04.11.22.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 11:22:38 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 8F0421FFBD; Fri, 4 Jun 2021 16:53:17 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Fs4mHduSC7s6AOHhF5ZFH6VJI9TQw9c8e27N4ga4IHk=; b=Zh1DBO0X4/prlBXa4eTG/cGDvDbmsYYxiDHeHH9PZIqK0MpqCcOy7uFZdUBwJr21Bz kYWhxtwC8YrhMEV6UP8OKobH2ZnOQcH2ZVGI0dJ3fxU/ewTm1EQhHVwSwsajpmTHUssB piqKQ981vZQE/WI3JvPk/uCSE6qQieRdb3C6ohSPkb0YneMxPqL5WTMzJfFCCm3cSHer CzY2310Dbbnf6Aue0xfxGh8s7VH3D2lJcuWrFvlAr811KKEKRNX50V1u75UQfQPDLpmw sBO14K8fqQumR6v9fX9lUlXt8/KCOAUiNixfT6iV5hEQqqkBlY/u6n0wGcvYkZIlUVIy BnBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Fs4mHduSC7s6AOHhF5ZFH6VJI9TQw9c8e27N4ga4IHk=; b=ah/yPV2MHxoEaW5qLDZYEsVAvEsLwTco1x+pPwfB5m2hz/AFu7TwHi5KneYhmuWw0/ wjlLHDGQfmJzTxIhvGJX0LE7hFXtPPsBpqCan0+aWyhD98Fng/34xrXh9/EocyX9ZQLs On7zdOF4rHrnmXg5CabqZtQVgwgYxlDKLghC/ZPcSmKYtODUKygKhHOgem9Z+IWeCP6t Y5249oym6sm1ZSVNMOfjQK1N5g0I/F1De3XcM7aFbzB8D2T4Lg6PRPsimTPI0YakytHk Jllg/UuhMx7gqH9Lb866t7HFc93SwGMzpw8H/ZIpUMV0fVwqC51jRq3xsQrCPMBh5caE 2Avg== X-Gm-Message-State: AOAM532w9mJHZ4tHleSewpJIgclDK6PkHS+80bD9BO/pAuHS1KSA6P/+ gCXhr0jKNB67eHWEEZ3bGdqSIg== X-Google-Smtp-Source: ABdhPJwlQaIdkNsdFsknvM0aojJ5EidOEExpMRnPs4QLGrEd/w/BBGqXRCUDYfhQGgfYx7d58QKawg== X-Received: by 2002:a1c:bc06:: with SMTP id m6mr4965227wmf.74.1622830965405; Fri, 04 Jun 2021 11:22:45 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 37/99] target/arm: move sve_zcr_len_for_el to common_cpu Date: Fri, 4 Jun 2021 16:52:10 +0100 Message-Id: <20210604155312.15902-38-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana it is required by arch-dump.c and cpu.c, so apparently we need this for KVM too Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-common.c | 43 +++++++++++++++++++++++++++++++++++++++++ target/arm/tcg/helper.c | 33 ------------------------------- 2 files changed, 43 insertions(+), 33 deletions(-) diff --git a/target/arm/cpu-common.c b/target/arm/cpu-common.c index 040e06392a..a34f7f19d8 100644 --- a/target/arm/cpu-common.c +++ b/target/arm/cpu-common.c @@ -299,3 +299,46 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) =20 return ret; } + +/* + * these are AARCH64-only, but due to the chain of dependencies, + * between HELPER prototypes, hflags, cpreg definitions and functions in + * tcg/ etc, it becomes incredibly messy to add what should be here: + * + * #ifdef TARGET_AARCH64 + */ + +static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) +{ + uint32_t end_len; + + end_len =3D start_len &=3D 0xf; + if (!test_bit(start_len, cpu->sve_vq_map)) { + end_len =3D find_last_bit(cpu->sve_vq_map, start_len); + assert(end_len < start_len); + } + return end_len; +} + +/* + * Given that SVE is enabled, return the vector length for EL. + */ +uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) +{ + ARMCPU *cpu =3D env_archcpu(env); + uint32_t zcr_len =3D cpu->sve_max_vq - 1; + + if (el <=3D 1) { + zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); + } + if (el <=3D 2 && arm_feature(env, ARM_FEATURE_EL2)) { + zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); + } + if (arm_feature(env, ARM_FEATURE_EL3)) { + zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); + } + + return sve_zcr_get_valid_len(cpu, zcr_len); +} + +/* #endif TARGET_AARCH64 , see matching comment above */ diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index a4630b4039..93fa3fa2a9 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -322,39 +322,6 @@ int sve_exception_el(CPUARMState *env, int el) return 0; } =20 -static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) -{ - uint32_t end_len; - - end_len =3D start_len &=3D 0xf; - if (!test_bit(start_len, cpu->sve_vq_map)) { - end_len =3D find_last_bit(cpu->sve_vq_map, start_len); - assert(end_len < start_len); - } - return end_len; -} - -/* - * Given that SVE is enabled, return the vector length for EL. - */ -uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) -{ - ARMCPU *cpu =3D env_archcpu(env); - uint32_t zcr_len =3D cpu->sve_max_vq - 1; - - if (el <=3D 1) { - zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); - } - if (el <=3D 2 && arm_feature(env, ARM_FEATURE_EL2)) { - zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); - } - if (arm_feature(env, ARM_FEATURE_EL3)) { - zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); - } - - return sve_zcr_get_valid_len(cpu, zcr_len); -} - void hw_watchpoint_update(ARMCPU *cpu, int n) { CPUARMState *env =3D &cpu->env; --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622825577; cv=none; d=zohomail.com; s=zohoarc; b=czLxkGuL10i4/ZtWYsHeznRrSDmn9zZdFwm7fWOrWDMhd8TFiYQo8otqpBLKs5c5jmFQ1oNP4JaNq/etEeewkdJ2r2p8uJyX/4843OGomIusngl+bps477bVP62Ih6av98HAID6IJmSns6g7MwN50Al4j+Ke+Fb7+G6KoE6JhJo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622825577; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=g+Q0O4/5dNcGlD5UswsObaT0lA+we8GvoPB9oAtz7uU=; b=KBEMuoJuFOOM3sx47J9z0K+RwJcrrzc3jgfFPFT45YqyNgIGDFLf8kBMwOmF320xSNcI/XmVL7962wtR2bnzZLixeTisSIy//o55bjC1d8fPbXZzzAg0B2GL9gN80oorsPsTojGgt4coGjsHyELWPMQ+ToKMv2+k3JLSyHCjcJo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162282557767086.68215711414314; Fri, 4 Jun 2021 09:52:57 -0700 (PDT) Received: from localhost ([::1]:38500 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpD44-0001d0-Dz for importer@patchew.org; Fri, 04 Jun 2021 12:52:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33714) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCkq-0008UQ-GM for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:06 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:33391) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCke-0002Ci-Bv for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:04 -0400 Received: by mail-wr1-x433.google.com with SMTP id a20so9970592wrc.0 for ; Fri, 04 Jun 2021 09:32:51 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id m11sm5748495wmq.33.2021.06.04.09.32.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:43 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A8E821FF8F; Fri, 4 Jun 2021 16:53:17 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g+Q0O4/5dNcGlD5UswsObaT0lA+we8GvoPB9oAtz7uU=; b=ZUqdxDtOXBlUTU70E4QInDY4qg3i0sn6r4uCyhH4FcORUrlcmUbbb066JybG0E5tgl zN/5YDs1jwsArbJa0ViqtUITGzqr5aW4+hHDncXPx7P9YHH/30MLRienUPO1kL960nwE SkB5m35SdySz4NmDgKEAWMB04gEfIQVtZlwHoEalOhPKEIhTnppnIwPNrpA4j9oVzGwU 5OIl684i6YYmyv4QjsHLAeSTkiaz4N3yI59yIw6saEq455CdtcGHm+T1v9ztqUrV1ovc a5MNtl9hifxKHik8We3xKiGhovBj2HhJt8ndh5m32mpCjNYdPn0VJoyJvL6MBuBu2oNJ hMpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g+Q0O4/5dNcGlD5UswsObaT0lA+we8GvoPB9oAtz7uU=; b=V4UFSPb/i+PdjTxdvKK4wWH1YxPOh8Ah0kWYw1Y8vmE1CFA+ITdBGi6TQ+owJUrxQB Mx69zkfyJDX82B35m5e/gZxrPjaUZQoO0nt07dJ4+Vp9NeJxkOzpUfeajkfW3tgm806+ 45tzCjL/JgQk/TrfiAHU80+KlwICBaOIqJxsjgvN9r5wLiEuY76D6IAbQMRDtS0yo6vP G9ouwuLQFIGJfjLW3A+0d7P6KK95ODYGw5dqsou0NPz7TDQAOnN0CXrPQoMON2XC4d7u sLGrsOfB9PZ/w7H04Ap3bf7sIVfwaEie9HyTuSszAsXYXNfP2Z3QRPiauS7Nq2PJSP7o ud7w== X-Gm-Message-State: AOAM532EqgwVS7Opc7IgtLFcDkjEyCoTKjHHBnGVD2kAcAL63qRkq0gf pJY0m05QZiKFzoPAY8cBngJN8Q== X-Google-Smtp-Source: ABdhPJyz3iDA2pzrdJQCz+DUQDsJMf3BZJoQ51Ct4UOvdiO+XwfxCDeiL7zreld2GdS0OQNnkLgLwg== X-Received: by 2002:a05:6000:18ac:: with SMTP id b12mr4660754wri.44.1622824371142; Fri, 04 Jun 2021 09:32:51 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 38/99] target/arm: move arm_sctlr away from tcg helpers Date: Fri, 4 Jun 2021 16:52:11 +0100 Message-Id: <20210604155312.15902-39-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana this function is used for kvm too, add it to the cpu-common module. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-common.c | 11 +++++++++++ target/arm/tcg/helper.c | 11 ----------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu-common.c b/target/arm/cpu-common.c index a34f7f19d8..93aea216cc 100644 --- a/target/arm/cpu-common.c +++ b/target/arm/cpu-common.c @@ -342,3 +342,14 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) } =20 /* #endif TARGET_AARCH64 , see matching comment above */ + +uint64_t arm_sctlr(CPUARMState *env, int el) +{ + /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ + if (el =3D=3D 0) { + ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, 0); + el =3D (mmu_idx =3D=3D ARMMMUIdx_E20_0 || mmu_idx =3D=3D ARMMMUIdx= _SE20_0) + ? 2 : 1; + } + return env->cp15.sctlr_el[el]; +} diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index 93fa3fa2a9..b9ea043f20 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -1675,17 +1675,6 @@ void arm_cpu_do_interrupt(CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ =20 -uint64_t arm_sctlr(CPUARMState *env, int el) -{ - /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ - if (el =3D=3D 0) { - ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, 0); - el =3D (mmu_idx =3D=3D ARMMMUIdx_E20_0 || mmu_idx =3D=3D ARMMMUIdx= _SE20_0) - ? 2 : 1; - } - return env->cp15.sctlr_el[el]; -} - /* Returns true if the stage 1 translation regime is using LPAE format page * tables. Used when raising alignment exceptions, whose FSR changes depen= ding * on whether the long or short descriptor format is in use. */ --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622825648; cv=none; d=zohomail.com; s=zohoarc; b=g58BHjUjLjAPu1qDEZt6C+zc6m8TYeu6UaBakd09r05nOXrpd/ZrTOHJbzRlt6H2DwBK9pKwjM5cWUQteEApAAqyRE0oItLUpudhcLjceEYswPkjHo6bF0i1bHvtlPgD4E8oitNRXC/S2eF/iASl7qWWZzf/1g6IgyIh20iTh1o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622825648; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FmT2fJZ1uVMYQwf4DRBAass7AtI+GiCA7uzNGZJ41H4=; b=W4YX4E0Yz6w3GvL2CjoL8kqv9i1U6zaiyaATqT9cwovAMrlzmglh1Cie1ksV10GojGVIwo+ZFrG+C+6YVRWoNBTIyjMWv7l8FQ1q8FRMPP6EhphgWrV/gUuZSip6cBeb5q0Z0L3Aagyr9WElCASHLv+WBcoLoXaHQZyIb5G8I9Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622825648967388.7668331686722; Fri, 4 Jun 2021 09:54:08 -0700 (PDT) Received: from localhost ([::1]:43090 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpD5D-0004eC-Qg for importer@patchew.org; Fri, 04 Jun 2021 12:54:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCIP-0000gO-Lx for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:41 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:54131) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHw-0005w9-Uw for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:41 -0400 Received: by mail-wm1-x330.google.com with SMTP id h3so5688469wmq.3 for ; Fri, 04 Jun 2021 09:03:04 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id d5sm6880344wrb.16.2021.06.04.09.02.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:56 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id C398B1FFBE; Fri, 4 Jun 2021 16:53:17 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FmT2fJZ1uVMYQwf4DRBAass7AtI+GiCA7uzNGZJ41H4=; b=aJ3Haq27l0iwFoE1JmwazN5DPDWmaUuaHsv+xhvf3wHRhwjr+9bVy/TbWVhgNdkPuw 8apDTzuGa3tBoVdM2hDMreL7RW5q2f6Yw6J/HvMzpWmNdEPzcZ4yVpiwff/ER8QHuzqf bmJtN2xUChF2RQFHMIt0/qhIu4/DPmH4Ewti5qT4SMFvE1m90Rpm87ZW3I6c4YeUS9YA juZ41HPWv2cRaWScnDy/1PbbQyViWPbRKFkr6uuJ0ffeAkLMZml02WQSENFgDDrAHv7x RYrbufQMbINQ/eZ1DTem8dsRAcMLfmgJIo/0RKlXnQnUYpzAVocc0CrmCOwQ+mQJW1cl 0SUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FmT2fJZ1uVMYQwf4DRBAass7AtI+GiCA7uzNGZJ41H4=; b=cHVDYFPWRKFwd/Zl7QJO8EOg6LxcgwKEyMACL2EyIgReHSkP4y5C1BfdMH59OGkJzs JgFVaD9VQlkG8BnjynIADPhA7GlCGiOjYhfJPymEubwCTqLJhLvjUKopJrHc7hcVsvCR rI3CTpPFQOKqjqNylXfkvfaQbvLVxnSvmFew+1yIrTeWXz/FJ1x+9raRGr60lGzogYtM Sbg1PvBZSDVF3FjM4Q9A9Ohhy8cBn6JvEJE+5oGmzs+90f75xHpO5I/miWLaslArlvGb cuviN9YbDhh9msV655iqE4ZD/pGaoLsdzKlE+NYs13BiZft+2VYYBriFnj8z2CXsAnDz GTJQ== X-Gm-Message-State: AOAM531T3HVegAKC1eKjfN6BXOsyaFoFUvl2IYSm96a5dPfKp92vHNFT VPJusBHSkKyafyjlXepIRH2vCA== X-Google-Smtp-Source: ABdhPJzETa4MczoRGs7mYQ0dXnKrOtMxvES9MyWi4u+wA7dj9vd6Y/oCpSpW9KkSVn3FTXPKVneP8w== X-Received: by 2002:a1c:e409:: with SMTP id b9mr4220413wmh.63.1622822583730; Fri, 04 Jun 2021 09:03:03 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 39/99] target/arm: move arm_cpu_list to common_cpu Date: Fri, 4 Jun 2021 16:52:12 +0100 Message-Id: <20210604155312.15902-40-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-common.c | 42 +++++++++++++++++++++++++++++++++++++++++ target/arm/tcg/helper.c | 41 ---------------------------------------- 2 files changed, 42 insertions(+), 41 deletions(-) diff --git a/target/arm/cpu-common.c b/target/arm/cpu-common.c index 93aea216cc..f4a3780e9e 100644 --- a/target/arm/cpu-common.c +++ b/target/arm/cpu-common.c @@ -8,6 +8,7 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/qemu-print.h" #include "qom/object.h" #include "qapi/qapi-commands-machine-target.h" #include "qapi/error.h" @@ -353,3 +354,44 @@ uint64_t arm_sctlr(CPUARMState *env, int el) } return env->cp15.sctlr_el[el]; } + +/* Sort alphabetically by type name, except for "any". */ +static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) +{ + ObjectClass *class_a =3D (ObjectClass *)a; + ObjectClass *class_b =3D (ObjectClass *)b; + const char *name_a, *name_b; + + name_a =3D object_class_get_name(class_a); + name_b =3D object_class_get_name(class_b); + if (strcmp(name_a, "any-" TYPE_ARM_CPU) =3D=3D 0) { + return 1; + } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) =3D=3D 0) { + return -1; + } else { + return strcmp(name_a, name_b); + } +} + +static void arm_cpu_list_entry(gpointer data, gpointer user_data) +{ + ObjectClass *oc =3D data; + const char *typename; + char *name; + + typename =3D object_class_get_name(oc); + name =3D g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CP= U)); + qemu_printf(" %s\n", name); + g_free(name); +} + +void arm_cpu_list(void) +{ + GSList *list; + + list =3D object_class_get_list(TYPE_ARM_CPU, false); + list =3D g_slist_sort(list, arm_cpu_list_compare); + qemu_printf("Available CPUs:\n"); + g_slist_foreach(list, arm_cpu_list_entry, NULL); + g_slist_free(list); +} diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index b9ea043f20..0e3f403e56 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -552,47 +552,6 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cp= u) =20 } =20 -/* Sort alphabetically by type name, except for "any". */ -static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b) -{ - ObjectClass *class_a =3D (ObjectClass *)a; - ObjectClass *class_b =3D (ObjectClass *)b; - const char *name_a, *name_b; - - name_a =3D object_class_get_name(class_a); - name_b =3D object_class_get_name(class_b); - if (strcmp(name_a, "any-" TYPE_ARM_CPU) =3D=3D 0) { - return 1; - } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) =3D=3D 0) { - return -1; - } else { - return strcmp(name_a, name_b); - } -} - -static void arm_cpu_list_entry(gpointer data, gpointer user_data) -{ - ObjectClass *oc =3D data; - const char *typename; - char *name; - - typename =3D object_class_get_name(oc); - name =3D g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CP= U)); - qemu_printf(" %s\n", name); - g_free(name); -} - -void arm_cpu_list(void) -{ - GSList *list; - - list =3D object_class_get_list(TYPE_ARM_CPU, false); - list =3D g_slist_sort(list, arm_cpu_list_compare); - qemu_printf("Available CPUs:\n"); - g_slist_foreach(list, arm_cpu_list_entry, NULL); - g_slist_free(list); -} - /* Sign/zero extend */ uint32_t HELPER(sxtb16)(uint32_t x) { --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622826678; cv=none; d=zohomail.com; s=zohoarc; b=byTHo+O9Gyw8y/CPXyWUK5T1R8NKy199j/XLcA6DiEWJ6h/IS1uYcNNzR50fpFm3mKeWASsYzimeHhDRtf5RJEin/YGIzvw52Yfzir0DZdcCoo0yZpYDtLnFlO5YvSHQ5E1u1TZNsRdp3XEfnCgj/AbGO805qiMxCmqbgzuVs8Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622826678; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sclbEbvsQp39DT+lWM9cgWgO57dq75LgW1XTapf4q3Q=; b=ReQHMLBgDH6b2GJ5GejiDKwhggSZNcUkZ5OHL4wBPq26G+mUomPbyU7ohGffLKSoiJZKKMPqH37Hb5NdgH1jd+AfLGtZluqyG/NTX9Op+OvRmYB/4jNDW93cntkTpJ7gDd+/Dc+pDOIZ2mt31KrBoTLO2v41WgEZZH/8zyaAVLQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622826678192234.12322962059193; Fri, 4 Jun 2021 10:11:18 -0700 (PDT) Received: from localhost ([::1]:46502 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDLp-0003aD-24 for importer@patchew.org; Fri, 04 Jun 2021 13:11:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33438) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCkb-0008AE-BH for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:32:49 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:39909) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCkX-00027b-7g for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:32:48 -0400 Received: by mail-wr1-x431.google.com with SMTP id l2so9930301wrw.6 for ; Fri, 04 Jun 2021 09:32:44 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id t1sm7060818wrx.28.2021.06.04.09.32.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:38 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id DFC9D1FFBF; Fri, 4 Jun 2021 16:53:17 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sclbEbvsQp39DT+lWM9cgWgO57dq75LgW1XTapf4q3Q=; b=XWV4BxMGDDYyrNfsy2t0fB53nHMyJiexRzNeodEeSMtYK65mTPv6dp9f7xfrPfTxUr oEsHLHIsVqosHsKFK45wTioim0tiphz35AivQHYwZNwCtxuta9V1LZ1pcpls4U0q9tNz 9X8xQJ+3TaPIutIYw6ewAWOLTukmep38nCYq5GC/gfWb4hyUbAEfZw5ugr6s/Pddxytt +Hb3Ur/Z6tvath79yyW/xtQQWXCCc5/Q8YrnMMqT9javWFrYBDRu9N4FUuyAJZr4Zo3w UHQZUgw2P1T39DKrBFpJ5+lBhRBdEbjhXUwewgLbuCqI1sSJiuzPv9JEqTFCHifP9cIZ lwSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sclbEbvsQp39DT+lWM9cgWgO57dq75LgW1XTapf4q3Q=; b=GKEkvxZB2L1PcDj6z45q2E1bCmoREfGyVBZfeW3iRpLQCap1kSBC68j6y1cZdvoha6 thQEQmKESVq4xVgxNJnB7WDiAuLNWsg0sPFE2asuWAY7pV5U9gczpKDpIsOEZQIB9Z+V DKU3I6w+kNLqLzjTKV5pU3eZrkKJoLYeoGqihL+Uqz3jjeYc53aUlUfqBkEO92vQbOVd a0kq/kKjPXkJCdclXBa7CY4JsmK9mkkcQyra97e4RZX4VuPm5mtDE8aoTnBmWITu1lGA jFvfipIFQggoszoh9/owoctc3bhwIkJq+uCB+zi71N0Ot5LaYOE9Njaf9BrHVEVbuo3v pAlw== X-Gm-Message-State: AOAM532rNtLwOrQ1oANPu8A4ABfxMZtyXzUW+bJwp16BKPzdXBhhRIr0 MZ2/NvlDlKyLGUgVcXoZoTvtGQ== X-Google-Smtp-Source: ABdhPJwNPvC/dnaM71qA22G3vFe6WdJuEWSptiOmig9X8J34jNsX5oemiZjJTwQwHfDUUNGnxQ6oxw== X-Received: by 2002:adf:bc07:: with SMTP id s7mr4848885wrg.301.1622824363286; Fri, 04 Jun 2021 09:32:43 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 40/99] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code Date: Fri, 4 Jun 2021 16:52:13 +0100 Message-Id: <20210604155312.15902-41-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana and arm_phys_excp_target_el since it is tied up inside the same #ifdef block. aarch64_sync_32_to_64 and aarch64_sync_64_to_32 are mixed in with the TCG helpers, but they shouldn't, as they are needed for KVM too. kvm_arch_get_registers() { if (!is_a64(env)) { aarch64_sync_64_to_32(env); } write_kvmstate_to_list(cpu); write_list_to_cpustate(cpu); ... } kvm_arch_put_registers() { if (!is_a64(env)) { aarch64_sync_32_to_64(env); } write_cpustate_to_list(cpu, true); write_list_to_kvmstate(cpu, level) ... } Move to the cpu module. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-sysemu.c | 215 +++++++++++++++++++++++++++++++++++++ target/arm/cpu-user.c | 11 ++ target/arm/tcg/helper.c | 232 +--------------------------------------- 3 files changed, 229 insertions(+), 229 deletions(-) diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c index 3add2c2439..7a314bf805 100644 --- a/target/arm/cpu-sysemu.c +++ b/target/arm/cpu-sysemu.c @@ -133,3 +133,218 @@ void switch_mode(CPUARMState *env, int mode) env->banked_r14[r14_bank_number(old_mode)] =3D env->regs[14]; env->regs[14] =3D env->banked_r14[r14_bank_number(mode)]; } + +/* + * Function used to synchronize QEMU's AArch64 register set with AArch32 + * register set. This is necessary when switching between AArch32 and AAr= ch64 + * execution state. + */ +void aarch64_sync_32_to_64(CPUARMState *env) +{ + int i; + uint32_t mode =3D env->uncached_cpsr & CPSR_M; + + /* We can blanket copy R[0:7] to X[0:7] */ + for (i =3D 0; i < 8; i++) { + env->xregs[i] =3D env->regs[i]; + } + + /* + * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r= 12. + * Otherwise, they come from the banked user regs. + */ + if (mode =3D=3D ARM_CPU_MODE_FIQ) { + for (i =3D 8; i < 13; i++) { + env->xregs[i] =3D env->usr_regs[i - 8]; + } + } else { + for (i =3D 8; i < 13; i++) { + env->xregs[i] =3D env->regs[i]; + } + } + + /* + * Registers x13-x23 are the various mode SP and FP registers. Registe= rs + * r13 and r14 are only copied if we are in that mode, otherwise we co= py + * from the mode banked register. + */ + if (mode =3D=3D ARM_CPU_MODE_USR || mode =3D=3D ARM_CPU_MODE_SYS) { + env->xregs[13] =3D env->regs[13]; + env->xregs[14] =3D env->regs[14]; + } else { + env->xregs[13] =3D env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; + /* HYP is an exception in that it is copied from r14 */ + if (mode =3D=3D ARM_CPU_MODE_HYP) { + env->xregs[14] =3D env->regs[14]; + } else { + env->xregs[14] =3D env->banked_r14[r14_bank_number(ARM_CPU_MOD= E_USR)]; + } + } + + if (mode =3D=3D ARM_CPU_MODE_HYP) { + env->xregs[15] =3D env->regs[13]; + } else { + env->xregs[15] =3D env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; + } + + if (mode =3D=3D ARM_CPU_MODE_IRQ) { + env->xregs[16] =3D env->regs[14]; + env->xregs[17] =3D env->regs[13]; + } else { + env->xregs[16] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_IR= Q)]; + env->xregs[17] =3D env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; + } + + if (mode =3D=3D ARM_CPU_MODE_SVC) { + env->xregs[18] =3D env->regs[14]; + env->xregs[19] =3D env->regs[13]; + } else { + env->xregs[18] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_SV= C)]; + env->xregs[19] =3D env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; + } + + if (mode =3D=3D ARM_CPU_MODE_ABT) { + env->xregs[20] =3D env->regs[14]; + env->xregs[21] =3D env->regs[13]; + } else { + env->xregs[20] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_AB= T)]; + env->xregs[21] =3D env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; + } + + if (mode =3D=3D ARM_CPU_MODE_UND) { + env->xregs[22] =3D env->regs[14]; + env->xregs[23] =3D env->regs[13]; + } else { + env->xregs[22] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_UN= D)]; + env->xregs[23] =3D env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; + } + + /* + * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in F= IQ + * mode, then we can copy from r8-r14. Otherwise, we copy from the + * FIQ bank for r8-r14. + */ + if (mode =3D=3D ARM_CPU_MODE_FIQ) { + for (i =3D 24; i < 31; i++) { + env->xregs[i] =3D env->regs[i - 16]; /* X[24:30] <- R[8:14] = */ + } + } else { + for (i =3D 24; i < 29; i++) { + env->xregs[i] =3D env->fiq_regs[i - 24]; + } + env->xregs[29] =3D env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; + env->xregs[30] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_FI= Q)]; + } + + env->pc =3D env->regs[15]; +} + +/* + * Function used to synchronize QEMU's AArch32 register set with AArch64 + * register set. This is necessary when switching between AArch32 and AAr= ch64 + * execution state. + */ +void aarch64_sync_64_to_32(CPUARMState *env) +{ + int i; + uint32_t mode =3D env->uncached_cpsr & CPSR_M; + + /* We can blanket copy X[0:7] to R[0:7] */ + for (i =3D 0; i < 8; i++) { + env->regs[i] =3D env->xregs[i]; + } + + /* + * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x= 12. + * Otherwise, we copy x8-x12 into the banked user regs. + */ + if (mode =3D=3D ARM_CPU_MODE_FIQ) { + for (i =3D 8; i < 13; i++) { + env->usr_regs[i - 8] =3D env->xregs[i]; + } + } else { + for (i =3D 8; i < 13; i++) { + env->regs[i] =3D env->xregs[i]; + } + } + + /* + * Registers r13 & r14 depend on the current mode. + * If we are in a given mode, we copy the corresponding x registers to= r13 + * and r14. Otherwise, we copy the x register to the banked r13 and r= 14 + * for the mode. + */ + if (mode =3D=3D ARM_CPU_MODE_USR || mode =3D=3D ARM_CPU_MODE_SYS) { + env->regs[13] =3D env->xregs[13]; + env->regs[14] =3D env->xregs[14]; + } else { + env->banked_r13[bank_number(ARM_CPU_MODE_USR)] =3D env->xregs[13]; + + /* + * HYP is an exception in that it does not have its own banked r14= but + * shares the USR r14 + */ + if (mode =3D=3D ARM_CPU_MODE_HYP) { + env->regs[14] =3D env->xregs[14]; + } else { + env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] =3D env->xr= egs[14]; + } + } + + if (mode =3D=3D ARM_CPU_MODE_HYP) { + env->regs[13] =3D env->xregs[15]; + } else { + env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] =3D env->xregs[15]; + } + + if (mode =3D=3D ARM_CPU_MODE_IRQ) { + env->regs[14] =3D env->xregs[16]; + env->regs[13] =3D env->xregs[17]; + } else { + env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] =3D env->xregs[= 16]; + env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] =3D env->xregs[17]; + } + + if (mode =3D=3D ARM_CPU_MODE_SVC) { + env->regs[14] =3D env->xregs[18]; + env->regs[13] =3D env->xregs[19]; + } else { + env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] =3D env->xregs[= 18]; + env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] =3D env->xregs[19]; + } + + if (mode =3D=3D ARM_CPU_MODE_ABT) { + env->regs[14] =3D env->xregs[20]; + env->regs[13] =3D env->xregs[21]; + } else { + env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] =3D env->xregs[= 20]; + env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] =3D env->xregs[21]; + } + + if (mode =3D=3D ARM_CPU_MODE_UND) { + env->regs[14] =3D env->xregs[22]; + env->regs[13] =3D env->xregs[23]; + } else { + env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] =3D env->xregs[= 22]; + env->banked_r13[bank_number(ARM_CPU_MODE_UND)] =3D env->xregs[23]; + } + + /* + * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in F= IQ + * mode, then we can copy to r8-r14. Otherwise, we copy to the + * FIQ bank for r8-r14. + */ + if (mode =3D=3D ARM_CPU_MODE_FIQ) { + for (i =3D 24; i < 31; i++) { + env->regs[i - 16] =3D env->xregs[i]; /* X[24:30] -> R[8:14] = */ + } + } else { + for (i =3D 24; i < 29; i++) { + env->fiq_regs[i - 24] =3D env->xregs[i]; + } + env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] =3D env->xregs[29]; + env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] =3D env->xregs[= 30]; + } + + env->regs[15] =3D env->pc; +} diff --git a/target/arm/cpu-user.c b/target/arm/cpu-user.c index a72b7f5703..0225089e46 100644 --- a/target/arm/cpu-user.c +++ b/target/arm/cpu-user.c @@ -22,3 +22,14 @@ void switch_mode(CPUARMState *env, int mode) cpu_abort(CPU(cpu), "Tried to switch out of user mode\n"); } } + +void aarch64_sync_64_to_32(CPUARMState *env) +{ + g_assert_not_reached(); +} + +uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, + uint32_t cur_el, bool secure) +{ + return 1; +} diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index 0e3f403e56..9dd83911f2 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -590,22 +590,10 @@ uint32_t HELPER(rbit)(uint32_t x) return revbit32(x); } =20 -#ifdef CONFIG_USER_ONLY - -uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, - uint32_t cur_el, bool secure) -{ - return 1; -} - -void aarch64_sync_64_to_32(CPUARMState *env) -{ - g_assert_not_reached(); -} - -#else +#ifndef CONFIG_USER_ONLY =20 -/* Physical Interrupt Target EL Lookup Table +/* + * Physical Interrupt Target EL Lookup Table * * [ From ARM ARM section G1.13.4 (Table G1-15) ] * @@ -754,220 +742,6 @@ void arm_log_exception(int idx) } } =20 -/* - * Function used to synchronize QEMU's AArch64 register set with AArch32 - * register set. This is necessary when switching between AArch32 and AAr= ch64 - * execution state. - */ -void aarch64_sync_32_to_64(CPUARMState *env) -{ - int i; - uint32_t mode =3D env->uncached_cpsr & CPSR_M; - - /* We can blanket copy R[0:7] to X[0:7] */ - for (i =3D 0; i < 8; i++) { - env->xregs[i] =3D env->regs[i]; - } - - /* - * Unless we are in FIQ mode, x8-x12 come from the user registers r8-r= 12. - * Otherwise, they come from the banked user regs. - */ - if (mode =3D=3D ARM_CPU_MODE_FIQ) { - for (i =3D 8; i < 13; i++) { - env->xregs[i] =3D env->usr_regs[i - 8]; - } - } else { - for (i =3D 8; i < 13; i++) { - env->xregs[i] =3D env->regs[i]; - } - } - - /* - * Registers x13-x23 are the various mode SP and FP registers. Registe= rs - * r13 and r14 are only copied if we are in that mode, otherwise we co= py - * from the mode banked register. - */ - if (mode =3D=3D ARM_CPU_MODE_USR || mode =3D=3D ARM_CPU_MODE_SYS) { - env->xregs[13] =3D env->regs[13]; - env->xregs[14] =3D env->regs[14]; - } else { - env->xregs[13] =3D env->banked_r13[bank_number(ARM_CPU_MODE_USR)]; - /* HYP is an exception in that it is copied from r14 */ - if (mode =3D=3D ARM_CPU_MODE_HYP) { - env->xregs[14] =3D env->regs[14]; - } else { - env->xregs[14] =3D env->banked_r14[r14_bank_number(ARM_CPU_MOD= E_USR)]; - } - } - - if (mode =3D=3D ARM_CPU_MODE_HYP) { - env->xregs[15] =3D env->regs[13]; - } else { - env->xregs[15] =3D env->banked_r13[bank_number(ARM_CPU_MODE_HYP)]; - } - - if (mode =3D=3D ARM_CPU_MODE_IRQ) { - env->xregs[16] =3D env->regs[14]; - env->xregs[17] =3D env->regs[13]; - } else { - env->xregs[16] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_IR= Q)]; - env->xregs[17] =3D env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)]; - } - - if (mode =3D=3D ARM_CPU_MODE_SVC) { - env->xregs[18] =3D env->regs[14]; - env->xregs[19] =3D env->regs[13]; - } else { - env->xregs[18] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_SV= C)]; - env->xregs[19] =3D env->banked_r13[bank_number(ARM_CPU_MODE_SVC)]; - } - - if (mode =3D=3D ARM_CPU_MODE_ABT) { - env->xregs[20] =3D env->regs[14]; - env->xregs[21] =3D env->regs[13]; - } else { - env->xregs[20] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_AB= T)]; - env->xregs[21] =3D env->banked_r13[bank_number(ARM_CPU_MODE_ABT)]; - } - - if (mode =3D=3D ARM_CPU_MODE_UND) { - env->xregs[22] =3D env->regs[14]; - env->xregs[23] =3D env->regs[13]; - } else { - env->xregs[22] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_UN= D)]; - env->xregs[23] =3D env->banked_r13[bank_number(ARM_CPU_MODE_UND)]; - } - - /* - * Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in F= IQ - * mode, then we can copy from r8-r14. Otherwise, we copy from the - * FIQ bank for r8-r14. - */ - if (mode =3D=3D ARM_CPU_MODE_FIQ) { - for (i =3D 24; i < 31; i++) { - env->xregs[i] =3D env->regs[i - 16]; /* X[24:30] <- R[8:14] = */ - } - } else { - for (i =3D 24; i < 29; i++) { - env->xregs[i] =3D env->fiq_regs[i - 24]; - } - env->xregs[29] =3D env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)]; - env->xregs[30] =3D env->banked_r14[r14_bank_number(ARM_CPU_MODE_FI= Q)]; - } - - env->pc =3D env->regs[15]; -} - -/* - * Function used to synchronize QEMU's AArch32 register set with AArch64 - * register set. This is necessary when switching between AArch32 and AAr= ch64 - * execution state. - */ -void aarch64_sync_64_to_32(CPUARMState *env) -{ - int i; - uint32_t mode =3D env->uncached_cpsr & CPSR_M; - - /* We can blanket copy X[0:7] to R[0:7] */ - for (i =3D 0; i < 8; i++) { - env->regs[i] =3D env->xregs[i]; - } - - /* - * Unless we are in FIQ mode, r8-r12 come from the user registers x8-x= 12. - * Otherwise, we copy x8-x12 into the banked user regs. - */ - if (mode =3D=3D ARM_CPU_MODE_FIQ) { - for (i =3D 8; i < 13; i++) { - env->usr_regs[i - 8] =3D env->xregs[i]; - } - } else { - for (i =3D 8; i < 13; i++) { - env->regs[i] =3D env->xregs[i]; - } - } - - /* - * Registers r13 & r14 depend on the current mode. - * If we are in a given mode, we copy the corresponding x registers to= r13 - * and r14. Otherwise, we copy the x register to the banked r13 and r= 14 - * for the mode. - */ - if (mode =3D=3D ARM_CPU_MODE_USR || mode =3D=3D ARM_CPU_MODE_SYS) { - env->regs[13] =3D env->xregs[13]; - env->regs[14] =3D env->xregs[14]; - } else { - env->banked_r13[bank_number(ARM_CPU_MODE_USR)] =3D env->xregs[13]; - - /* - * HYP is an exception in that it does not have its own banked r14= but - * shares the USR r14 - */ - if (mode =3D=3D ARM_CPU_MODE_HYP) { - env->regs[14] =3D env->xregs[14]; - } else { - env->banked_r14[r14_bank_number(ARM_CPU_MODE_USR)] =3D env->xr= egs[14]; - } - } - - if (mode =3D=3D ARM_CPU_MODE_HYP) { - env->regs[13] =3D env->xregs[15]; - } else { - env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] =3D env->xregs[15]; - } - - if (mode =3D=3D ARM_CPU_MODE_IRQ) { - env->regs[14] =3D env->xregs[16]; - env->regs[13] =3D env->xregs[17]; - } else { - env->banked_r14[r14_bank_number(ARM_CPU_MODE_IRQ)] =3D env->xregs[= 16]; - env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] =3D env->xregs[17]; - } - - if (mode =3D=3D ARM_CPU_MODE_SVC) { - env->regs[14] =3D env->xregs[18]; - env->regs[13] =3D env->xregs[19]; - } else { - env->banked_r14[r14_bank_number(ARM_CPU_MODE_SVC)] =3D env->xregs[= 18]; - env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] =3D env->xregs[19]; - } - - if (mode =3D=3D ARM_CPU_MODE_ABT) { - env->regs[14] =3D env->xregs[20]; - env->regs[13] =3D env->xregs[21]; - } else { - env->banked_r14[r14_bank_number(ARM_CPU_MODE_ABT)] =3D env->xregs[= 20]; - env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] =3D env->xregs[21]; - } - - if (mode =3D=3D ARM_CPU_MODE_UND) { - env->regs[14] =3D env->xregs[22]; - env->regs[13] =3D env->xregs[23]; - } else { - env->banked_r14[r14_bank_number(ARM_CPU_MODE_UND)] =3D env->xregs[= 22]; - env->banked_r13[bank_number(ARM_CPU_MODE_UND)] =3D env->xregs[23]; - } - - /* Registers x24-x30 are mapped to r8-r14 in FIQ mode. If we are in F= IQ - * mode, then we can copy to r8-r14. Otherwise, we copy to the - * FIQ bank for r8-r14. - */ - if (mode =3D=3D ARM_CPU_MODE_FIQ) { - for (i =3D 24; i < 31; i++) { - env->regs[i - 16] =3D env->xregs[i]; /* X[24:30] -> R[8:14] = */ - } - } else { - for (i =3D 24; i < 29; i++) { - env->fiq_regs[i - 24] =3D env->xregs[i]; - } - env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] =3D env->xregs[29]; - env->banked_r14[r14_bank_number(ARM_CPU_MODE_FIQ)] =3D env->xregs[= 30]; - } - - env->regs[15] =3D env->pc; -} - static void take_aarch32_exception(CPUARMState *env, int new_mode, uint32_t mask, uint32_t offset, uint32_t newpc) --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622824796; cv=none; d=zohomail.com; s=zohoarc; b=F0VtnsiavXWOo2NC6Hyfh3zoYNXUdUXisVrwpM7owpmD9ZsEXGMxrcR27qJ9mPNhMWWRIwKMad+8PVItzIkKacwhEMZzwFlpD41IE7AdhbZThh+jQFPWKzxMX6S8En2Mp8pXGr+DIiqb8t7rZeSAqsw+uoT/V37ZNJnEA+O10ic= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622824796; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YEMn/TZVYqcd/40Lz0kIER2IvEdqHAsgJm9milarnoM=; b=GBDjkc5h4bxL9BCNGaJjJvQk/72ap2P97Ucuq3q2Fww3vDkpMGhX8+TFxW1vZyakUsAXFDLmzbz5vIsIyguIergIltcofsWGNErlJRsz5p+ZNwH0M5p/U4AP2AjiJtHO0vMPxIoaBbkClEcM7d23dAKkWa+hCV1ilvyzUcdtiyw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622824796821589.0531224833677; Fri, 4 Jun 2021 09:39:56 -0700 (PDT) Received: from localhost ([::1]:50842 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCrT-0004oc-PX for importer@patchew.org; Fri, 04 Jun 2021 12:39:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52090) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCRW-0003F2-HH for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:13:06 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:53128) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCRM-0003sC-Ic for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:13:06 -0400 Received: by mail-wm1-x330.google.com with SMTP id f17so5706777wmf.2 for ; Fri, 04 Jun 2021 09:12:55 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id f20sm7039580wmh.41.2021.06.04.09.12.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:12:50 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 0EE2D1FFC0; Fri, 4 Jun 2021 16:53:18 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YEMn/TZVYqcd/40Lz0kIER2IvEdqHAsgJm9milarnoM=; b=qoeJ8YdJYYO8fyGjxeRqyN87qqRw/OYj45ViDUyZGOWQXyQOcpGI3HKTSH737TVZCk OpTEPYM/3MzolXCetO1MvtGI9G6OiG9dV4B5f4LpN7dfu/7cnDD+bx0bkCJV9WpWT3Ie l1HMOxmJRtShK+mszU+2WPxxLgkA5nDOf6ADXZbpR+GBTsvaaFcBPKVsqt88n7DlczD/ U4/szyu43EjP1zVYs65I5VK7bkc2uNUCDcDG9zJzwliozClMgHOujOK+ZOSXdV5NF3JH XFXdMoXPXJXjis+2HW0zxs/FFgNMpFxlCFXAm8+XFPmtRfCVcWUW6kQz2BcVy5lar5r7 9aCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YEMn/TZVYqcd/40Lz0kIER2IvEdqHAsgJm9milarnoM=; b=af8a+Z542+etVLKM0Wse53wCJYMTJLDMqx36PWlUMF63ErVS3X0o4BtYNgbc+oEFzf vStmSjeQ65A+xw8wB+cySwIUEvGvWu1IcDDwvuZqrd84C0a0hJeX0Sk37/hZ5OKt1FZc 3SYxRK7j3munRaR3HIjPa3a5VL2UdBOxh3zbUgkyU61uJly9Ye0zYAVetYN8BHC1J7Hk T2xKNVfUg1YUE27YEvIs685CKA8Gxa9fTZphGLGlkMi4CkpO2Twal8xHU8LFNm/a1L+s +J8tPx42fmGPREC+rAmT9nyAY7jP9s08smisIpsK7T5m8kRMbhxmhCn8PmgwDHQlEpLW OQ3w== X-Gm-Message-State: AOAM5331k1gY4mPnS5v3QfBRXPAAOF82O0wOaXWr2shBSo4iuGxFFAsj xLi2Aek2ocoW3msSR9/h3mkzhQ== X-Google-Smtp-Source: ABdhPJxaNgaUupzTYFAOUwcG0a/HCBNAsRTnHqyJYlfDlSRlTt2jz+uze1mYNdlYAvggp/UT7vsE9A== X-Received: by 2002:a7b:ce8a:: with SMTP id q10mr4477404wmj.184.1622823174713; Fri, 04 Jun 2021 09:12:54 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 41/99] target/arm: new cpu32 ARM 32 bit CPU Class Date: Fri, 4 Jun 2021 16:52:14 +0100 Message-Id: <20210604155312.15902-42-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana In the ARM CPU class hierarchy, the ancestor TYPE_ARM_CPU is fundamentally a 32 bit CPU Class. The child TYPE_AARCH64_CPU overrides the class to make it a 64 bit CPU Class. Explicitly put the 32bit CPU Class implementation in a cpu32.c, along with the 32bit CPU Class model registration function. In later changes, we will further split 32bit and 64bit code. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-qom.h | 3 -- target/arm/cpu32.h | 28 ++++++++++ target/arm/cpu.c | 55 ++----------------- target/arm/cpu32.c | 118 +++++++++++++++++++++++++++++++++++++++++ target/arm/cpu64.c | 2 +- target/arm/cpu_tcg.c | 3 +- target/arm/meson.build | 6 ++- 7 files changed, 159 insertions(+), 56 deletions(-) create mode 100644 target/arm/cpu32.h create mode 100644 target/arm/cpu32.c diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index a22bd506d0..0d41a346b9 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -38,9 +38,6 @@ typedef struct ARMCPUInfo { void (*class_init)(ObjectClass *oc, void *data); } ARMCPUInfo; =20 -void arm_cpu_register(const ARMCPUInfo *info); -void aarch64_cpu_register(const ARMCPUInfo *info); - /** * ARMCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/arm/cpu32.h b/target/arm/cpu32.h new file mode 100644 index 0000000000..211fad6f55 --- /dev/null +++ b/target/arm/cpu32.h @@ -0,0 +1,28 @@ +/* + * QEMU ARM CPU models (32bit) + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#ifndef ARM_CPU32_H +#define ARM_CPU32_H + +void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags); +void arm32_cpu_class_init(ObjectClass *oc, void *data); +void arm32_cpu_register(const ARMCPUInfo *info); + +#endif /* ARM_CPU32_H */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7bb406efd2..b9b300944d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -30,6 +30,7 @@ #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" #endif /* CONFIG_TCG */ +#include "cpu32.h" #include "internals.h" #include "exec/exec-all.h" #include "hw/qdev-properties.h" @@ -853,7 +854,7 @@ static inline void aarch64_cpu_dump_state(CPUState *cs,= FILE *f, int flags) =20 #endif =20 -static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) +void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -1856,17 +1857,6 @@ static Property arm_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 -static gchar *arm_gdb_arch_name(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - if (arm_feature(env, ARM_FEATURE_IWMMXT)) { - return g_strdup("iwmmxt"); - } - return g_strdup("arm"); -} - #ifndef CONFIG_USER_ONLY #include "hw/core/sysemu-cpu-ops.h" =20 @@ -1912,16 +1902,11 @@ static void arm_cpu_class_init(ObjectClass *oc, voi= d *data) =20 cc->class_by_name =3D arm_cpu_class_by_name; cc->has_work =3D arm_cpu_has_work; - cc->dump_state =3D arm_cpu_dump_state; cc->set_pc =3D arm_cpu_set_pc; - cc->gdb_read_register =3D arm_cpu_gdb_read_register; - cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &arm_sysemu_ops; #endif - cc->gdb_num_core_regs =3D 26; - cc->gdb_core_xml_file =3D "arm-core.xml"; - cc->gdb_arch_name =3D arm_gdb_arch_name; + cc->gdb_get_dynamic_xml =3D arm_gdb_get_dynamic_xml; cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D arm_disas_set_info; @@ -1929,6 +1914,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifdef CONFIG_TCG cc->tcg_ops =3D &arm_tcg_ops; #endif /* CONFIG_TCG */ + + arm32_cpu_class_init(oc, data); } =20 #ifdef CONFIG_KVM @@ -1951,38 +1938,6 @@ static const TypeInfo host_arm_cpu_type_info =3D { =20 #endif =20 -static void arm_cpu_instance_init(Object *obj) -{ - ARMCPUClass *acc =3D ARM_CPU_GET_CLASS(obj); - - acc->info->initfn(obj); - arm_cpu_post_init(obj); -} - -static void cpu_register_class_init(ObjectClass *oc, void *data) -{ - ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); - - acc->info =3D data; -} - -void arm_cpu_register(const ARMCPUInfo *info) -{ - TypeInfo type_info =3D { - .parent =3D TYPE_ARM_CPU, - .instance_size =3D sizeof(ARMCPU), - .instance_align =3D __alignof__(ARMCPU), - .instance_init =3D arm_cpu_instance_init, - .class_size =3D sizeof(ARMCPUClass), - .class_init =3D info->class_init ?: cpu_register_class_init, - .class_data =3D (void *)info, - }; - - type_info.name =3D g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); - type_register(&type_info); - g_free((void *)type_info.name); -} - static const TypeInfo arm_cpu_type_info =3D { .name =3D TYPE_ARM_CPU, .parent =3D TYPE_CPU, diff --git a/target/arm/cpu32.c b/target/arm/cpu32.c new file mode 100644 index 0000000000..39fb112a04 --- /dev/null +++ b/target/arm/cpu32.c @@ -0,0 +1,118 @@ +/* + * QEMU ARM CPU models (32bit) + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "qemu/osdep.h" +#include "qemu/qemu-print.h" +#include "qemu-common.h" +#include "target/arm/idau.h" +#include "qemu/module.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "cpu.h" +#include "cpregs.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "hw/qdev-properties.h" +#if !defined(CONFIG_USER_ONLY) +#include "hw/loader.h" +#include "hw/boards.h" +#endif +#include "sysemu/sysemu.h" +#include "sysemu/tcg.h" +#include "sysemu/hw_accel.h" +#include "kvm_arm.h" +#include "disas/capstone.h" +#include "fpu/softfloat.h" +#include "cpu-mmu.h" +#include "cpu32.h" + +/* we can move this to tcg/ after the cleanup of ARM boards configurations= */ +static const ARMCPUInfo arm32_cpus[] =3D { +}; + +static gchar *arm_gdb_arch_name(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + if (arm_feature(env, ARM_FEATURE_IWMMXT)) { + return g_strdup("iwmmxt"); + } + return g_strdup("arm"); +} + +void arm32_cpu_class_init(ObjectClass *oc, void *data) +{ + CPUClass *cc =3D CPU_CLASS(oc); + + cc->gdb_read_register =3D arm_cpu_gdb_read_register; + cc->gdb_write_register =3D arm_cpu_gdb_write_register; + cc->gdb_num_core_regs =3D 26; + cc->gdb_core_xml_file =3D "arm-core.xml"; + cc->gdb_arch_name =3D arm_gdb_arch_name; + cc->dump_state =3D arm_cpu_dump_state; +} + +static void arm32_cpu_instance_init(Object *obj) +{ + ARMCPUClass *acc =3D ARM_CPU_GET_CLASS(obj); + + acc->info->initfn(obj); + arm_cpu_post_init(obj); +} + +static void arm32_cpu_register_class_init(ObjectClass *oc, void *data) +{ + ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); + + acc->info =3D data; +} + +void arm32_cpu_register(const ARMCPUInfo *info) +{ + TypeInfo type_info =3D { + .parent =3D TYPE_ARM_CPU, + .instance_size =3D sizeof(ARMCPU), + .instance_align =3D __alignof__(ARMCPU), + .instance_init =3D arm32_cpu_instance_init, + .class_size =3D sizeof(ARMCPUClass), + .class_init =3D info->class_init ?: arm32_cpu_register_class_init, + .class_data =3D (void *)info, + }; + + type_info.name =3D g_strdup_printf("%s-" TYPE_ARM_CPU, info->name); + type_register(&type_info); + g_free((void *)type_info.name); +} + +static void arm32_cpu_register_types(void) +{ + const size_t cpu_count =3D ARRAY_SIZE(arm32_cpus); + + if (cpu_count) { + size_t i; + + for (i =3D 0; i < cpu_count; ++i) { + arm32_cpu_register(&arm32_cpus[i]); + } + } +} + +type_init(arm32_cpu_register_types) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 5354069c63..4ff55fb0f0 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -860,7 +860,7 @@ static void cpu_register_class_init(ObjectClass *oc, vo= id *data) acc->info =3D data; } =20 -void aarch64_cpu_register(const ARMCPUInfo *info) +static void aarch64_cpu_register(const ARMCPUInfo *info) { TypeInfo type_info =3D { .parent =3D TYPE_AARCH64_CPU, diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index d973239d78..09eff9bfd2 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -19,6 +19,7 @@ #include "hw/boards.h" #endif #include "cpregs.h" +#include "cpu32.h" =20 /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) @@ -1072,7 +1073,7 @@ static void arm_tcg_cpu_register_types(void) =20 type_register_static(&idau_interface_type_info); for (i =3D 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) { - arm_cpu_register(&arm_tcg_cpus[i]); + arm32_cpu_register(&arm_tcg_cpus[i]); } } =20 diff --git a/target/arm/meson.build b/target/arm/meson.build index 4bc44e1db2..0ccd2fb0bc 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -2,12 +2,12 @@ arm_ss =3D ss.source_set() arm_ss.add(files( 'cpregs.c', 'cpu.c', + 'cpu32.c', 'cpu-common.c', 'cpu-mmu.c', 'cpu-vfp.c', 'cpustate-list.c', 'gdbstub.c', - 'cpu_tcg.c', )) arm_ss.add(zlib) =20 @@ -18,6 +18,10 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'gdbstub64.c', )) =20 +arm_ss.add(when: 'CONFIG_TCG', if_true: files( + 'cpu_tcg.c', +)) + arm_softmmu_ss =3D ss.source_set() arm_softmmu_ss.add(files( 'arch_dump.c', --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622831094; cv=none; d=zohomail.com; s=zohoarc; b=mH5CzbQvQaPEFNJySlU4XSTSPWCxnv9VBEYQ609Cgy5n3AObcAy3uryc23A+NKIorBO8HNhgEdi5kntpViKHWT2WULp4Vz7ILDxGxCg2axFcpvFZYO8o4pP1/CIhfVSYoXxEjZFicnn/UB3bxTkM1jkfrbnh7GGKz3ZY5IEjyaA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622831094; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DaG++NcIdtxVqAad7Vs0R6dhTvromA2j7N2Qe9wv/vA=; b=bkacGF3Qenfgk2cFwf/Q2PNo0sFZcTcrftwyJtBH2K6kZ60aT7vEfREyEXjQJoonsAIh7jv4MmVaHBQexIDCakIjUdSnv9H4mS+3romF39BYLrwHCDdBjloNi47hglY+FytvH1Ix57spL8CTM9zorT5CJ9xv1mAI3eNq0sKIEUc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622831094359422.9188758367467; Fri, 4 Jun 2021 11:24:54 -0700 (PDT) Received: from localhost ([::1]:42480 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpEV3-0007FT-0i for importer@patchew.org; Fri, 04 Jun 2021 14:24:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42504) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpETB-0001PH-FP for qemu-devel@nongnu.org; Fri, 04 Jun 2021 14:22:57 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:33773) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpET6-0000Re-89 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 14:22:57 -0400 Received: by mail-wr1-x429.google.com with SMTP id a20so10249620wrc.0 for ; Fri, 04 Jun 2021 11:22:51 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id f8sm6094773wmg.43.2021.06.04.11.22.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 11:22:45 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 2B1411FFC1; Fri, 4 Jun 2021 16:53:18 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DaG++NcIdtxVqAad7Vs0R6dhTvromA2j7N2Qe9wv/vA=; b=HXw8oYR/a2DyitOFpiiPG/gdcoWC/t+xIkIbZ0ylTzKPhPm9QmR0jg9EW8i2O5K2zW FkKd/MB32M5KfDvXfvxTw/qh/6WQ7BigWQPeNfMrIRO9d+Ib/duYUJsec85WQOag037Q Dip7TqOPFqGMGotLh/rLAeJjYS+VJphopkfzLkczHq+Tpoc7GgMXjfS9WEbvo48UJiiu Cpkp1hyKinOKJXKx8NR9ppaSMZCvV0lq992Fk9ycPAFB15fmTPx7IPIX48Mi1/kkTz6Z iOkb2BMpDAZcPNxUUm9ux4xijMRRzhD05chi74Ai8+HYZKBRmkE6jATcZYFvzlcPJfkZ hQlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DaG++NcIdtxVqAad7Vs0R6dhTvromA2j7N2Qe9wv/vA=; b=DHNPQxXJ7FwLBF5OSH5EKJhNJEVArjEnpkz1/pAuKo7N0L0nPjEsrIZzMr5skRBMCc rn25eIu4ZLw7N9gT2ZjefUew9qQO3N7y6CuxTwfqopiQw3s0sEjVu8d2/HenIkMWWCVu ZPjA77VGXy16y6t6HAwv7tNNFpelHuK25NhgwXdsHadqHULoiHWVDfOI5ZJKjCZuzUDa nYGRhApJeegeTV0bNtNYLsGCOJ+GIGUY/7Wjld9EHKET+z3jVegQ6VUAC+WUymkdyuFz EyovUDGdsHdEY6BOBJAf7wlMO2HNCrvhVeHOZfS9tunBVeLhBgZ++N1SXwDACxML++Dq 7DSg== X-Gm-Message-State: AOAM5311GauEKTINeu2eaDu+S0xPimmsSlAXeN5/g4ykt9ETTyO1mLsD XbybbzoR/7tANppV4YOBexidWg== X-Google-Smtp-Source: ABdhPJzWNXkSK9ujF8WZ/+fbVOnSXE2A2qoO2aDdWwLcBiSQr42XMTJCq7HceWNzMuk+fu5rF1gLNg== X-Received: by 2002:a5d:6a02:: with SMTP id m2mr5290785wru.77.1622830970818; Fri, 04 Jun 2021 11:22:50 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 42/99] target/arm: split 32bit and 64bit arm dump state Date: Fri, 4 Jun 2021 16:52:15 +0100 Message-Id: <20210604155312.15902-43-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu32.h | 2 +- target/arm/cpu.c | 225 --------------------------------------------- target/arm/cpu32.c | 85 ++++++++++++++++- target/arm/cpu64.c | 142 ++++++++++++++++++++++++++++ 4 files changed, 227 insertions(+), 227 deletions(-) diff --git a/target/arm/cpu32.h b/target/arm/cpu32.h index 211fad6f55..128d0c9247 100644 --- a/target/arm/cpu32.h +++ b/target/arm/cpu32.h @@ -21,7 +21,7 @@ #ifndef ARM_CPU32_H #define ARM_CPU32_H =20 -void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags); +void arm32_cpu_dump_state(CPUState *cs, FILE *f, int flags); void arm32_cpu_class_init(ObjectClass *oc, void *data); void arm32_cpu_register(const ARMCPUInfo *info); =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b9b300944d..97d562bbd5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -19,7 +19,6 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/qemu-print.h" #include "qemu-common.h" #include "target/arm/idau.h" #include "qemu/module.h" @@ -716,230 +715,6 @@ static void arm_disas_set_info(CPUState *cpu, disasse= mble_info *info) #endif } =20 -#ifdef TARGET_AARCH64 - -static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - uint32_t psr =3D pstate_read(env); - int i; - int el =3D arm_current_el(env); - const char *ns_status; - - qemu_fprintf(f, " PC=3D%016" PRIx64 " ", env->pc); - for (i =3D 0; i < 32; i++) { - if (i =3D=3D 31) { - qemu_fprintf(f, " SP=3D%016" PRIx64 "\n", env->xregs[i]); - } else { - qemu_fprintf(f, "X%02d=3D%016" PRIx64 "%s", i, env->xregs[i], - (i + 2) % 3 ? " " : "\n"); - } - } - - if (arm_feature(env, ARM_FEATURE_EL3) && el !=3D 3) { - ns_status =3D env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; - } else { - ns_status =3D ""; - } - qemu_fprintf(f, "PSTATE=3D%08x %c%c%c%c %sEL%d%c", - psr, - psr & PSTATE_N ? 'N' : '-', - psr & PSTATE_Z ? 'Z' : '-', - psr & PSTATE_C ? 'C' : '-', - psr & PSTATE_V ? 'V' : '-', - ns_status, - el, - psr & PSTATE_SP ? 'h' : 't'); - - if (cpu_isar_feature(aa64_bti, cpu)) { - qemu_fprintf(f, " BTYPE=3D%d", (psr & PSTATE_BTYPE) >> 10); - } - if (!(flags & CPU_DUMP_FPU)) { - qemu_fprintf(f, "\n"); - return; - } - if (fp_exception_el(env, el) !=3D 0) { - qemu_fprintf(f, " FPU disabled\n"); - return; - } - qemu_fprintf(f, " FPCR=3D%08x FPSR=3D%08x\n", - vfp_get_fpcr(env), vfp_get_fpsr(env)); - - if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) =3D= =3D 0) { - int j, zcr_len =3D sve_zcr_len_for_el(env, el); - - for (i =3D 0; i <=3D FFR_PRED_NUM; i++) { - bool eol; - if (i =3D=3D FFR_PRED_NUM) { - qemu_fprintf(f, "FFR=3D"); - /* It's last, so end the line. */ - eol =3D true; - } else { - qemu_fprintf(f, "P%02d=3D", i); - switch (zcr_len) { - case 0: - eol =3D i % 8 =3D=3D 7; - break; - case 1: - eol =3D i % 6 =3D=3D 5; - break; - case 2: - case 3: - eol =3D i % 3 =3D=3D 2; - break; - default: - /* More than one quadword per predicate. */ - eol =3D true; - break; - } - } - for (j =3D zcr_len / 4; j >=3D 0; j--) { - int digits; - if (j * 4 + 4 <=3D zcr_len + 1) { - digits =3D 16; - } else { - digits =3D (zcr_len % 4 + 1) * 4; - } - qemu_fprintf(f, "%0*" PRIx64 "%s", digits, - env->vfp.pregs[i].p[j], - j ? ":" : eol ? "\n" : " "); - } - } - - for (i =3D 0; i < 32; i++) { - if (zcr_len =3D=3D 0) { - qemu_fprintf(f, "Z%02d=3D%016" PRIx64 ":%016" PRIx64 "%s", - i, env->vfp.zregs[i].d[1], - env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); - } else if (zcr_len =3D=3D 1) { - qemu_fprintf(f, "Z%02d=3D%016" PRIx64 ":%016" PRIx64 - ":%016" PRIx64 ":%016" PRIx64 "\n", - i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].= d[2], - env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0= ]); - } else { - for (j =3D zcr_len; j >=3D 0; j--) { - bool odd =3D (zcr_len - j) % 2 !=3D 0; - if (j =3D=3D zcr_len) { - qemu_fprintf(f, "Z%02d[%x-%x]=3D", i, j, j - 1); - } else if (!odd) { - if (j > 0) { - qemu_fprintf(f, " [%x-%x]=3D", j, j - 1); - } else { - qemu_fprintf(f, " [%x]=3D", j); - } - } - qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", - env->vfp.zregs[i].d[j * 2 + 1], - env->vfp.zregs[i].d[j * 2], - odd || j =3D=3D 0 ? "\n" : ":"); - } - } - } - } else { - for (i =3D 0; i < 32; i++) { - uint64_t *q =3D aa64_vfp_qreg(env, i); - qemu_fprintf(f, "Q%02d=3D%016" PRIx64 ":%016" PRIx64 "%s", - i, q[1], q[0], (i & 1 ? "\n" : " ")); - } - } -} - -#else - -static inline void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - g_assert_not_reached(); -} - -#endif - -void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - int i; - - if (is_a64(env)) { - aarch64_cpu_dump_state(cs, f, flags); - return; - } - - for (i =3D 0; i < 16; i++) { - qemu_fprintf(f, "R%02d=3D%08x", i, env->regs[i]); - if ((i % 4) =3D=3D 3) { - qemu_fprintf(f, "\n"); - } else { - qemu_fprintf(f, " "); - } - } - - if (arm_feature(env, ARM_FEATURE_M)) { - uint32_t xpsr =3D xpsr_read(env); - const char *mode; - const char *ns_status =3D ""; - - if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - ns_status =3D env->v7m.secure ? "S " : "NS "; - } - - if (xpsr & XPSR_EXCP) { - mode =3D "handler"; - } else { - if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MA= SK) { - mode =3D "unpriv-thread"; - } else { - mode =3D "priv-thread"; - } - } - - qemu_fprintf(f, "XPSR=3D%08x %c%c%c%c %c %s%s\n", - xpsr, - xpsr & XPSR_N ? 'N' : '-', - xpsr & XPSR_Z ? 'Z' : '-', - xpsr & XPSR_C ? 'C' : '-', - xpsr & XPSR_V ? 'V' : '-', - xpsr & XPSR_T ? 'T' : 'A', - ns_status, - mode); - } else { - uint32_t psr =3D cpsr_read(env); - const char *ns_status =3D ""; - - if (arm_feature(env, ARM_FEATURE_EL3) && - (psr & CPSR_M) !=3D ARM_CPU_MODE_MON) { - ns_status =3D env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; - } - - qemu_fprintf(f, "PSR=3D%08x %c%c%c%c %c %s%s%d\n", - psr, - psr & CPSR_N ? 'N' : '-', - psr & CPSR_Z ? 'Z' : '-', - psr & CPSR_C ? 'C' : '-', - psr & CPSR_V ? 'V' : '-', - psr & CPSR_T ? 'T' : 'A', - ns_status, - aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); - } - - if (flags & CPU_DUMP_FPU) { - int numvfpregs =3D 0; - if (cpu_isar_feature(aa32_simd_r32, cpu)) { - numvfpregs =3D 32; - } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { - numvfpregs =3D 16; - } - for (i =3D 0; i < numvfpregs; i++) { - uint64_t v =3D *aa32_vfp_dreg(env, i); - qemu_fprintf(f, "s%02d=3D%08x s%02d=3D%08x d%02d=3D%016" PRIx6= 4 "\n", - i * 2, (uint32_t)v, - i * 2 + 1, (uint32_t)(v >> 32), - i, v); - } - qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); - } -} - uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) { uint32_t Aff1 =3D idx / clustersz; diff --git a/target/arm/cpu32.c b/target/arm/cpu32.c index 39fb112a04..c03f420ba2 100644 --- a/target/arm/cpu32.c +++ b/target/arm/cpu32.c @@ -58,6 +58,89 @@ static gchar *arm_gdb_arch_name(CPUState *cs) return g_strdup("arm"); } =20 +void arm32_cpu_dump_state(CPUState *cs, FILE *f, int flags) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + int i; + + assert(!is_a64(env)); + + for (i =3D 0; i < 16; i++) { + qemu_fprintf(f, "R%02d=3D%08x", i, env->regs[i]); + if ((i % 4) =3D=3D 3) { + qemu_fprintf(f, "\n"); + } else { + qemu_fprintf(f, " "); + } + } + + if (arm_feature(env, ARM_FEATURE_M)) { + uint32_t xpsr =3D xpsr_read(env); + const char *mode; + const char *ns_status =3D ""; + + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + ns_status =3D env->v7m.secure ? "S " : "NS "; + } + + if (xpsr & XPSR_EXCP) { + mode =3D "handler"; + } else { + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MA= SK) { + mode =3D "unpriv-thread"; + } else { + mode =3D "priv-thread"; + } + } + + qemu_fprintf(f, "XPSR=3D%08x %c%c%c%c %c %s%s\n", + xpsr, + xpsr & XPSR_N ? 'N' : '-', + xpsr & XPSR_Z ? 'Z' : '-', + xpsr & XPSR_C ? 'C' : '-', + xpsr & XPSR_V ? 'V' : '-', + xpsr & XPSR_T ? 'T' : 'A', + ns_status, + mode); + } else { + uint32_t psr =3D cpsr_read(env); + const char *ns_status =3D ""; + + if (arm_feature(env, ARM_FEATURE_EL3) && + (psr & CPSR_M) !=3D ARM_CPU_MODE_MON) { + ns_status =3D env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; + } + + qemu_fprintf(f, "PSR=3D%08x %c%c%c%c %c %s%s%d\n", + psr, + psr & CPSR_N ? 'N' : '-', + psr & CPSR_Z ? 'Z' : '-', + psr & CPSR_C ? 'C' : '-', + psr & CPSR_V ? 'V' : '-', + psr & CPSR_T ? 'T' : 'A', + ns_status, + aarch32_mode_name(psr), (psr & 0x10) ? 32 : 26); + } + + if (flags & CPU_DUMP_FPU) { + int numvfpregs =3D 0; + if (cpu_isar_feature(aa32_simd_r32, cpu)) { + numvfpregs =3D 32; + } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { + numvfpregs =3D 16; + } + for (i =3D 0; i < numvfpregs; i++) { + uint64_t v =3D *aa32_vfp_dreg(env, i); + qemu_fprintf(f, "s%02d=3D%08x s%02d=3D%08x d%02d=3D%016" PRIx6= 4 "\n", + i * 2, (uint32_t)v, + i * 2 + 1, (uint32_t)(v >> 32), + i, v); + } + qemu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); + } +} + void arm32_cpu_class_init(ObjectClass *oc, void *data) { CPUClass *cc =3D CPU_CLASS(oc); @@ -67,7 +150,7 @@ void arm32_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_num_core_regs =3D 26; cc->gdb_core_xml_file =3D "arm-core.xml"; cc->gdb_arch_name =3D arm_gdb_arch_name; - cc->dump_state =3D arm_cpu_dump_state; + cc->dump_state =3D arm32_cpu_dump_state; } =20 static void arm32_cpu_instance_init(Object *obj) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4ff55fb0f0..7cd73ae0b6 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -20,7 +20,9 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" +#include "qemu/qemu-print.h" #include "cpu.h" +#include "cpu32.h" #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" #endif /* CONFIG_TCG */ @@ -828,6 +830,145 @@ static gchar *aarch64_gdb_arch_name(CPUState *cs) return g_strdup("aarch64"); } =20 +static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + uint32_t psr =3D pstate_read(env); + int i; + int el =3D arm_current_el(env); + const char *ns_status; + + qemu_fprintf(f, " PC=3D%016" PRIx64 " ", env->pc); + for (i =3D 0; i < 32; i++) { + if (i =3D=3D 31) { + qemu_fprintf(f, " SP=3D%016" PRIx64 "\n", env->xregs[i]); + } else { + qemu_fprintf(f, "X%02d=3D%016" PRIx64 "%s", i, env->xregs[i], + (i + 2) % 3 ? " " : "\n"); + } + } + + if (arm_feature(env, ARM_FEATURE_EL3) && el !=3D 3) { + ns_status =3D env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; + } else { + ns_status =3D ""; + } + qemu_fprintf(f, "PSTATE=3D%08x %c%c%c%c %sEL%d%c", + psr, + psr & PSTATE_N ? 'N' : '-', + psr & PSTATE_Z ? 'Z' : '-', + psr & PSTATE_C ? 'C' : '-', + psr & PSTATE_V ? 'V' : '-', + ns_status, + el, + psr & PSTATE_SP ? 'h' : 't'); + + if (cpu_isar_feature(aa64_bti, cpu)) { + qemu_fprintf(f, " BTYPE=3D%d", (psr & PSTATE_BTYPE) >> 10); + } + if (!(flags & CPU_DUMP_FPU)) { + qemu_fprintf(f, "\n"); + return; + } + if (fp_exception_el(env, el) !=3D 0) { + qemu_fprintf(f, " FPU disabled\n"); + return; + } + qemu_fprintf(f, " FPCR=3D%08x FPSR=3D%08x\n", + vfp_get_fpcr(env), vfp_get_fpsr(env)); + + if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) =3D= =3D 0) { + int j, zcr_len =3D sve_zcr_len_for_el(env, el); + + for (i =3D 0; i <=3D FFR_PRED_NUM; i++) { + bool eol; + if (i =3D=3D FFR_PRED_NUM) { + qemu_fprintf(f, "FFR=3D"); + /* It's last, so end the line. */ + eol =3D true; + } else { + qemu_fprintf(f, "P%02d=3D", i); + switch (zcr_len) { + case 0: + eol =3D i % 8 =3D=3D 7; + break; + case 1: + eol =3D i % 6 =3D=3D 5; + break; + case 2: + case 3: + eol =3D i % 3 =3D=3D 2; + break; + default: + /* More than one quadword per predicate. */ + eol =3D true; + break; + } + } + for (j =3D zcr_len / 4; j >=3D 0; j--) { + int digits; + if (j * 4 + 4 <=3D zcr_len + 1) { + digits =3D 16; + } else { + digits =3D (zcr_len % 4 + 1) * 4; + } + qemu_fprintf(f, "%0*" PRIx64 "%s", digits, + env->vfp.pregs[i].p[j], + j ? ":" : eol ? "\n" : " "); + } + } + + for (i =3D 0; i < 32; i++) { + if (zcr_len =3D=3D 0) { + qemu_fprintf(f, "Z%02d=3D%016" PRIx64 ":%016" PRIx64 "%s", + i, env->vfp.zregs[i].d[1], + env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); + } else if (zcr_len =3D=3D 1) { + qemu_fprintf(f, "Z%02d=3D%016" PRIx64 ":%016" PRIx64 + ":%016" PRIx64 ":%016" PRIx64 "\n", + i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].= d[2], + env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0= ]); + } else { + for (j =3D zcr_len; j >=3D 0; j--) { + bool odd =3D (zcr_len - j) % 2 !=3D 0; + if (j =3D=3D zcr_len) { + qemu_fprintf(f, "Z%02d[%x-%x]=3D", i, j, j - 1); + } else if (!odd) { + if (j > 0) { + qemu_fprintf(f, " [%x-%x]=3D", j, j - 1); + } else { + qemu_fprintf(f, " [%x]=3D", j); + } + } + qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", + env->vfp.zregs[i].d[j * 2 + 1], + env->vfp.zregs[i].d[j * 2], + odd || j =3D=3D 0 ? "\n" : ":"); + } + } + } + } else { + for (i =3D 0; i < 32; i++) { + uint64_t *q =3D aa64_vfp_qreg(env, i); + qemu_fprintf(f, "Q%02d=3D%016" PRIx64 ":%016" PRIx64 "%s", + i, q[1], q[0], (i & 1 ? "\n" : " ")); + } + } +} + +static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + if (is_a64(env)) { + aarch64_cpu_dump_state(cs, f, flags); + } else { + arm32_cpu_dump_state(cs, f, flags); + } +} + static void aarch64_cpu_class_init(ObjectClass *oc, void *data) { CPUClass *cc =3D CPU_CLASS(oc); @@ -837,6 +978,7 @@ static void aarch64_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_num_core_regs =3D 34; cc->gdb_core_xml_file =3D "aarch64-core.xml"; cc->gdb_arch_name =3D aarch64_gdb_arch_name; + cc->dump_state =3D arm_cpu_dump_state; =20 object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64, aarch64_cpu_set_aarch64); --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622824751; cv=none; d=zohomail.com; s=zohoarc; b=EGu4TJ+f3ZkOcIPZii8HskypFPQy1TX0vgo6XHLaFVSmO36v8casLupLVxlhnUzUyH4v3VtYFer9FusD4yEwS9D6nC5PGwy8XmhM9wlij47OHKumQ0bQK2YUS1YOLotyb5QIfXmTk19ZJMpD/WehspJpsME2ffrVOCv4U/utLMY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622824751; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pdzAt2AXoQ9lDlpGyixAMgmXVwO3iRo3io77IDow6qA=; b=TtjFnI1DVIYf+BL2FEH8ku61uUv3UM3lI6cKCSVeb3GJ5MNPzAjUwCLSdNqF2CJoIUc+4eXs1psTs2YCVjAzpseMCgKdkM4TN9pdlKcvOICaaz/WULlE/xHnE8GOWO07t7dP9UVvg04lsyU6sjxEnQFrVQs2X1xY/9TILY0NdnQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622824751164308.3453332878886; Fri, 4 Jun 2021 09:39:11 -0700 (PDT) Received: from localhost ([::1]:49402 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCqk-0003gN-1b for importer@patchew.org; Fri, 04 Jun 2021 12:39:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48930) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCIT-0000oO-SM for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:45 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:34524) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHy-0005wT-48 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:45 -0400 Received: by mail-wm1-x330.google.com with SMTP id u5-20020a7bc0450000b02901480e40338bso4509129wmc.1 for ; Fri, 04 Jun 2021 09:03:06 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id r7sm11380294wma.9.2021.06.04.09.02.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:56 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 455B01FFC2; Fri, 4 Jun 2021 16:53:18 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pdzAt2AXoQ9lDlpGyixAMgmXVwO3iRo3io77IDow6qA=; b=SQwdWupWuVopNCIEc/t23+QezyJZGaovRIliiKt2U9V3Op00Yl5bJlEbyEXdYtMH8X EpLpAWljNaRn1hn7vda6/LVVJAicIUk6kc5TAzIXILxujTM2Et1Iqac4mYGSXY8HfGjz hhOmDvQZqqBJjX2RTfMwc3wJnRi8NHrILaRoTb4V59+QAb7zZ5YTgcaurAWv2ShcpxXi JWqf/yRjvOXG/gthaknmD8myejdZgjHo9RWRzoltujdmoW7l25lYwHvFB1ctsiwrD9BI QpDRIZ7no008gl5ofVa4eV7wr23lZYNjED81G5rM8rAXvU7tv+YDHdEKnu4SdyHcAY5X R4jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pdzAt2AXoQ9lDlpGyixAMgmXVwO3iRo3io77IDow6qA=; b=CxyHMCAZMob5ZJ8bRzMHX+gx4EFXLXvv0wAdKSLJmuoSDbMz/NlTSvxqx3L/R8aXx5 BzDiBTt/dJxuHp7BRBp1uQi/9E8Fj+QvgvE0kXn72TBBjkYAM5OKSPrdnmPHZzzi9aVh O84drVFG0uuak/PoK8UZfncq+odIpz6CsMlnVL3zd45i8lWfeHvqsGG6j2ol+LBJWvJi V1Tb08l0cljtVljp7hp8QX6UF3lGw6mj5nl11YvU0fNzA+ih2oISXBP7Ost3FCxsRFNb PjFwLglzJCXDV2QxRfPDCDeFdQ8pVM5cg0j8s3UetO0Z8wHiC8WJptvL98RrDYwVs0+9 1nUQ== X-Gm-Message-State: AOAM533EGP5/dGxBErLqMsXLFc6vjy7WnrngkUX2emsWAEHQ6uZGSNDF zKT7MEAWO5aa+BzbDOiX52+L0g== X-Google-Smtp-Source: ABdhPJxFZyWrY6CVppaRmUsSYj1Ec5/KlmbX717CKXs9sfM0imnuQxprKctoxFhlq66lDRKa4PuAHA== X-Received: by 2002:a7b:c853:: with SMTP id c19mr4464373wml.30.1622822585348; Fri, 04 Jun 2021 09:03:05 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 43/99] target/arm: move a15 cpu model away from the TCG-only models Date: Fri, 4 Jun 2021 16:52:16 +0100 Message-Id: <20210604155312.15902-44-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana Cortex-A15 is the only ARM cpu class we need in KVM too. We will be able to move it to tcg/ once the board code and configurations are fixed. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu32.h | 4 +++ target/arm/cpu32.c | 73 ++++++++++++++++++++++++++++++++++++++++++++ target/arm/cpu_tcg.c | 67 ---------------------------------------- 3 files changed, 77 insertions(+), 67 deletions(-) diff --git a/target/arm/cpu32.h b/target/arm/cpu32.h index 128d0c9247..abd575d47d 100644 --- a/target/arm/cpu32.h +++ b/target/arm/cpu32.h @@ -21,8 +21,12 @@ #ifndef ARM_CPU32_H #define ARM_CPU32_H =20 +#include "cpregs.h" + void arm32_cpu_dump_state(CPUState *cs, FILE *f, int flags); void arm32_cpu_class_init(ObjectClass *oc, void *data); void arm32_cpu_register(const ARMCPUInfo *info); +void cortex_a15_initfn(Object *obj); +extern const ARMCPRegInfo cortexa15_cp_reginfo[]; =20 #endif /* ARM_CPU32_H */ diff --git a/target/arm/cpu32.c b/target/arm/cpu32.c index c03f420ba2..a6ba91ae08 100644 --- a/target/arm/cpu32.c +++ b/target/arm/cpu32.c @@ -43,8 +43,81 @@ #include "cpu-mmu.h" #include "cpu32.h" =20 +#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) + +#ifndef CONFIG_USER_ONLY +static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + + /* + * Linux wants the number of processors from here. + * Might as well set the interrupt-controller bit too. + */ + return ((ms->smp.cpus - 1) << 24) | (1 << 23); +} +#endif + +const ARMCPRegInfo cortexa15_cp_reginfo[] =3D { +#ifndef CONFIG_USER_ONLY + { .name =3D "L2CTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1,= .opc2 =3D 2, + .access =3D PL1_RW, .resetvalue =3D 0, .readfn =3D a15_l2ctlr_read, + .writefn =3D arm_cp_write_ignore, }, +#endif + { .name =3D "L2ECTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +void cortex_a15_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a15"; + set_feature(&cpu->env, ARM_FEATURE_V7VE); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A15; + cpu->midr =3D 0x412fc0f1; + cpu->reset_fpsid =3D 0x410430f0; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x11111111; + cpu->ctr =3D 0x8444c004; + cpu->reset_sctlr =3D 0x00c50078; + cpu->isar.id_pfr0 =3D 0x00001131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x02010555; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x20000000; + cpu->isar.id_mmfr2 =3D 0x01240000; + cpu->isar.id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232041; + cpu->isar.id_isar3 =3D 0x11112131; + cpu->isar.id_isar4 =3D 0x10011142; + cpu->isar.dbgdidr =3D 0x3515f021; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ + cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ + define_arm_cp_regs(cpu, cortexa15_cp_reginfo); +} + +#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */ + /* we can move this to tcg/ after the cleanup of ARM boards configurations= */ static const ARMCPUInfo arm32_cpus[] =3D { +#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) + { .name =3D "cortex-a15", .initfn =3D cortex_a15_initfn }, +#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */ }; =20 static gchar *arm_gdb_arch_name(CPUState *cs) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 09eff9bfd2..fe422498c7 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -378,30 +378,6 @@ static void cortex_a9_initfn(Object *obj) define_arm_cp_regs(cpu, cortexa9_cp_reginfo); } =20 -#ifndef CONFIG_USER_ONLY -static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) -{ - MachineState *ms =3D MACHINE(qdev_get_machine()); - - /* - * Linux wants the number of processors from here. - * Might as well set the interrupt-controller bit too. - */ - return ((ms->smp.cpus - 1) << 24) | (1 << 23); -} -#endif - -static const ARMCPRegInfo cortexa15_cp_reginfo[] =3D { -#ifndef CONFIG_USER_ONLY - { .name =3D "L2CTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1,= .opc2 =3D 2, - .access =3D PL1_RW, .resetvalue =3D 0, .readfn =3D a15_l2ctlr_read, - .writefn =3D arm_cp_write_ignore, }, -#endif - { .name =3D "L2ECTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL -}; - static void cortex_a7_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -448,48 +424,6 @@ static void cortex_a7_initfn(Object *obj) define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */ } =20 -static void cortex_a15_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,cortex-a15"; - set_feature(&cpu->env, ARM_FEATURE_V7VE); - set_feature(&cpu->env, ARM_FEATURE_NEON); - set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); - set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); - set_feature(&cpu->env, ARM_FEATURE_EL2); - set_feature(&cpu->env, ARM_FEATURE_EL3); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_CORTEX_A15; - cpu->midr =3D 0x412fc0f1; - cpu->reset_fpsid =3D 0x410430f0; - cpu->isar.mvfr0 =3D 0x10110222; - cpu->isar.mvfr1 =3D 0x11111111; - cpu->ctr =3D 0x8444c004; - cpu->reset_sctlr =3D 0x00c50078; - cpu->isar.id_pfr0 =3D 0x00001131; - cpu->isar.id_pfr1 =3D 0x00011011; - cpu->isar.id_dfr0 =3D 0x02010555; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x10201105; - cpu->isar.id_mmfr1 =3D 0x20000000; - cpu->isar.id_mmfr2 =3D 0x01240000; - cpu->isar.id_mmfr3 =3D 0x02102211; - cpu->isar.id_isar0 =3D 0x02101110; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232041; - cpu->isar.id_isar3 =3D 0x11112131; - cpu->isar.id_isar4 =3D 0x10011142; - cpu->isar.dbgdidr =3D 0x3515f021; - cpu->clidr =3D 0x0a200023; - cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ - cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ - cpu->ccsidr[2] =3D 0x711fe07a; /* 4096K L2 unified cache */ - define_arm_cp_regs(cpu, cortexa15_cp_reginfo); -} - static void cortex_m0_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -1022,7 +956,6 @@ static const ARMCPUInfo arm_tcg_cpus[] =3D { { .name =3D "cortex-a7", .initfn =3D cortex_a7_initfn }, { .name =3D "cortex-a8", .initfn =3D cortex_a8_initfn }, { .name =3D "cortex-a9", .initfn =3D cortex_a9_initfn }, - { .name =3D "cortex-a15", .initfn =3D cortex_a15_initfn }, { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622824545; cv=none; d=zohomail.com; s=zohoarc; b=QTIk20+cTL2jilo2/81T2WE+WVGbjd9y1jgdZU2XcygwxYWaR1nQkVmyyfEAu27oKs6za/hMh5WQGWU0eLwzRrIBT8CWCSBVveEFufL7lXU4y+GlEA5+t6EP31TwHnsedGfTksdHiayhMduWeR4ueBhaq62a8S20mmA8uy6x+Yw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622824545; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CQtnS34z/bTDeAgJgcVIAWI8dJCWeYn70HUU46NLGbY=; b=VstFHvSz291+YvusU/aNSgLY5jIBnjNLawAZJtFKT9/6wNlLJw7r6l7Qkjs529rAvDokAxJmb28N1YRz1kwNypxFpOliEChXIoiEkX4XJNdb7Rpphq1cl9OUOMP+0wgrWDWe43HFKv39sUW2C+rjVabvZppsXvg3yLZUbtGyzoc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622824545036555.6072769964172; Fri, 4 Jun 2021 09:35:45 -0700 (PDT) Received: from localhost ([::1]:39522 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCnP-0005J2-Rg for importer@patchew.org; Fri, 04 Jun 2021 12:35:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48250) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCHd-0007mT-2k for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:02:53 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:46941) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHW-0005lY-Fo for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:02:52 -0400 Received: by mail-wr1-x434.google.com with SMTP id a11so7945916wrt.13 for ; Fri, 04 Jun 2021 09:02:46 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id p1sm6127310wmc.11.2021.06.04.09.02.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:43 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 5A4751FFC3; Fri, 4 Jun 2021 16:53:18 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CQtnS34z/bTDeAgJgcVIAWI8dJCWeYn70HUU46NLGbY=; b=H0rLFfDc/pCqx9gywa70LgA0sqr+1pwSHDZ5ngyterzlPj3IH3yrQdI5bLBbXVJJLr jdmc70IcuslrmQ2O7hz9DXhd3AjHVNvsxy8RcMKakr88RhbxsGmD5+cAhE/75auadcYk SEEufDxnaMPvUy+IRqaWWuUPhcmKVZVCf0K54lLn65Hwx+PbVo4ztol9Ed3NduddEw2+ JyD1odli0EoBxDPM+vngFKhBQXrCS9AvMvb/SDYmxWiQbh6Qbl3L+8Zc94rhkFQmPeZx YRdEH3LBbcD38fj5fplHGBFOUptDDgilijaKQtsRDz1Yge4DHl2N63AmRpvPthm+OXdb atVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CQtnS34z/bTDeAgJgcVIAWI8dJCWeYn70HUU46NLGbY=; b=BYnhGMpNIhk1ib0L+H84+5rXubrrjjbeDhSpMWySzGOYWBQiAQkl/KG648+dFBvvSJ M9mN516NxhxPwSu2GxwgAhk+x0RSM+K9jpYYFJURRzZnStIcoDb2Ev2DM59X7rMjPYSf F8prIRkYoWlIFRV44p7SznbsNudPCPmEC+ra0RuhhU9Mx9jeqbyBYBkQVweMjX7e+qyQ yRmx3VV3a3QkXreBD4Ia9kLGna+Ko55E2H5SE9D9CPi4H1zjUnO8AgYXAHb8bZoGgt3m +cqKSU1gn/qQ7l5UCznpvAJFqYbZqeKMfn37ZUtZxwGSNFfi5Hi420B2e55ponieHOLy ODSw== X-Gm-Message-State: AOAM533AT65owVk5Bvg40e0b38DU5EwSi4wb7V+cTaQX3tL4NRXKxGn1 Oy6E3NPtC8Xh6MJiBXSAceDDLg== X-Google-Smtp-Source: ABdhPJxFeXOQi0NKJJPefjGea33wcnMzfjCBVdkvzknTv7zPjZz8E660Ym9vaT4QPChZhvZ9Gj6yVg== X-Received: by 2002:a05:6000:1282:: with SMTP id f2mr4511680wrx.67.1622822565245; Fri, 04 Jun 2021 09:02:45 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 44/99] target/arm: fixup sve_exception_el code style before move Date: Fri, 4 Jun 2021 16:52:17 +0100 Message-Id: <20210604155312.15902-45-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana before moving over sve_exception_el from the helper code, cleanup the style. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/helper.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index 9dd83911f2..1c69a69d5a 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -261,7 +261,8 @@ static int arm_gdb_set_svereg(CPUARMState *env, uint8_t= *buf, int reg) } #endif /* TARGET_AARCH64 */ =20 -/* Return the exception level to which exceptions should be taken +/* + * Return the exception level to which exceptions should be taken * via SVEAccessTrap. If an exception should be routed through * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should * take care of raising that exception. @@ -275,7 +276,8 @@ int sve_exception_el(CPUARMState *env, int el) if (el <=3D 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { bool disabled =3D false; =20 - /* The CPACR.ZEN controls traps to EL1: + /* + * The CPACR.ZEN controls traps to EL1: * 0, 2 : trap EL0 and EL1 accesses * 1 : trap only EL0 accesses * 3 : trap no accesses @@ -301,7 +303,8 @@ int sve_exception_el(CPUARMState *env, int el) } } =20 - /* CPTR_EL2. Since TZ and TFP are positive, + /* + * CPTR_EL2. Since TZ and TFP are positive, * they will be zero when EL2 is not present. */ if (el <=3D 2 && arm_is_el2_enabled(env)) { --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622828488; cv=none; d=zohomail.com; s=zohoarc; b=ATV6735pBH7mXqUMQrcd577wyV+dPYs6W1Kjoh9SK6nvx2bezUYz84CXZphUTBxWanheh99MFEqsEkNm6fRwMaxAJiucrmTwMD2+1wYk51i3a3VSIg2TYWOCwB2bgk7Vw6tKPC534JrtH7kAoUGF+M70jYvyM/Pu5Rv9MSF76mQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622828488; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=05nkHLjcRHyfDukFJajvGPGtE1+ijrzLS+mVjmVHqf8=; b=iwJFXGO3/Mmc5iWzjIKEKpUBV67p3GfBQnBxfg4eIvYQmK4sI/t3Z47/cAsGdsZNpXc/lgmVHODKUG1LSOc1DUIlgv2K3D+vUl0s4XzM7XA3kALaOvTc7J/e1BKGvbmgIWG7A6Oiwbm719X0MmwjUMlvB0pEWg9mVfMJ9lZjyGw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622828488050617.8770035700877; Fri, 4 Jun 2021 10:41:28 -0700 (PDT) Received: from localhost ([::1]:60174 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDp0-0004P0-Vp for importer@patchew.org; Fri, 04 Jun 2021 13:41:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48960) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpDNY-0000TB-0L for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:13:04 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:40637) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpDNR-00028f-QQ for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:13:03 -0400 Received: by mail-wr1-x42d.google.com with SMTP id y7so5387707wrh.7 for ; Fri, 04 Jun 2021 10:12:57 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id q20sm9145301wrf.45.2021.06.04.10.12.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 10:12:46 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 73FBC1FFC4; Fri, 4 Jun 2021 16:53:18 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=05nkHLjcRHyfDukFJajvGPGtE1+ijrzLS+mVjmVHqf8=; b=DodAKl7esocnjjL/SdHyoskpdivSLAuDP3NAJ35wJcmxAE4rrmKaa80TM3hjYhxRHN QFmSCWX/2cRPrLgWyhCMUdfn4CB4Z1omc9RE4J7Ajdmvx7r42a4x+ZpVzxP1lggrmOjV m2alL0J3LugU5AD0DUBWpMCt1J5iQ7nXFe/yqmelp7axmiiGCQm5kWGoKgrm2fbwxLn0 3RX7LhRBGrH+6BOZde8sKNjrtj1r3mFcZ/YufbJUt5BMz7u861Bhlo2+19KPZxYHc6xa fJuUSElnLblI87nvh+vacSW5fBsdHUnzIu78FA3MW0/Sk+RH4qp2ZQBkoe05NITs1B5R GtIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=05nkHLjcRHyfDukFJajvGPGtE1+ijrzLS+mVjmVHqf8=; b=Bc33fV12hdXf1bNSuTwWDBD4VB9q6A9JVrxTnOaAdzHR3KWdCnUUkQKfsew7l++tad Bw/u82sZM/+Qa799MyT+UgeQv9uDRxcZsYodFNcpcLd5wwaSmWXnVmFuuD4Yev+FqFoe 9CCatuQx0wy4jM8KQdYAXS3mfgKPMJ9IJYy/1PuAnwlztoqoAx6txLciwjAVTAxudHEL KzM1uCch0PCryZ+iP2+qU/yzSph/KYxaAHAKz8/vV9V+XyN8IX3oJ517KmMZVHiPa5pP Babkc59f04m4Qfws7qajcU3MpUzYMwZGs7fpyvVAOizUvO1S4D91vfU8Zjr/2beTwuru 76Lw== X-Gm-Message-State: AOAM531tMs0s1x123I/jcyGFWHc7SuNElJTbthoOP4JSRbIRbbfGIELp tEGkIYOrxnSeO7BoNu0IVcW9aQ== X-Google-Smtp-Source: ABdhPJzjIwtDlBNItvYql7yYx8wUbO6NCDfp+azpt35Qz2Mc0XiyIvuv/7VqCc5gfFAMuLBRQdpEZQ== X-Received: by 2002:adf:f382:: with SMTP id m2mr4983685wro.394.1622826776475; Fri, 04 Jun 2021 10:12:56 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 45/99] target/arm: move sve_exception_el out of TCG helpers Date: Fri, 4 Jun 2021 16:52:18 +0100 Message-Id: <20210604155312.15902-46-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana we need this for KVM too. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-sysemu.c | 62 +++++++++++++++++++++++++++++++++++++++ target/arm/cpu-user.c | 5 ++++ target/arm/tcg/helper.c | 64 ----------------------------------------- 3 files changed, 67 insertions(+), 64 deletions(-) diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c index 7a314bf805..7cc721fe68 100644 --- a/target/arm/cpu-sysemu.c +++ b/target/arm/cpu-sysemu.c @@ -348,3 +348,65 @@ void aarch64_sync_64_to_32(CPUARMState *env) =20 env->regs[15] =3D env->pc; } + +/* + * Return the exception level to which exceptions should be taken + * via SVEAccessTrap. If an exception should be routed through + * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should + * take care of raising that exception. + * C.f. the ARM pseudocode function CheckSVEEnabled. + */ +int sve_exception_el(CPUARMState *env, int el) +{ + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); + + if (el <=3D 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { + bool disabled =3D false; + + /* + * The CPACR.ZEN controls traps to EL1: + * 0, 2 : trap EL0 and EL1 accesses + * 1 : trap only EL0 accesses + * 3 : trap no accesses + */ + if (!extract32(env->cp15.cpacr_el1, 16, 1)) { + disabled =3D true; + } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) { + disabled =3D el =3D=3D 0; + } + if (disabled) { + /* route_to_el2 */ + return hcr_el2 & HCR_TGE ? 2 : 1; + } + + /* Check CPACR.FPEN. */ + if (!extract32(env->cp15.cpacr_el1, 20, 1)) { + disabled =3D true; + } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) { + disabled =3D el =3D=3D 0; + } + if (disabled) { + return 0; + } + } + + /* + * CPTR_EL2. Since TZ and TFP are positive, + * they will be zero when EL2 is not present. + */ + if (el <=3D 2 && arm_is_el2_enabled(env)) { + if (env->cp15.cptr_el[2] & CPTR_TZ) { + return 2; + } + if (env->cp15.cptr_el[2] & CPTR_TFP) { + return 0; + } + } + + /* CPTR_EL3. Since EZ is negative we must check for EL3. */ + if (arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.cptr_el[3] & CPTR_EZ)) { + return 3; + } + return 0; +} diff --git a/target/arm/cpu-user.c b/target/arm/cpu-user.c index 0225089e46..39093ade76 100644 --- a/target/arm/cpu-user.c +++ b/target/arm/cpu-user.c @@ -33,3 +33,8 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t e= xcp_idx, { return 1; } + +int sve_exception_el(CPUARMState *env, int el) +{ + return 0; +} diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index 1c69a69d5a..8372089260 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -261,70 +261,6 @@ static int arm_gdb_set_svereg(CPUARMState *env, uint8_= t *buf, int reg) } #endif /* TARGET_AARCH64 */ =20 -/* - * Return the exception level to which exceptions should be taken - * via SVEAccessTrap. If an exception should be routed through - * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should - * take care of raising that exception. - * C.f. the ARM pseudocode function CheckSVEEnabled. - */ -int sve_exception_el(CPUARMState *env, int el) -{ -#ifndef CONFIG_USER_ONLY - uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); - - if (el <=3D 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { - bool disabled =3D false; - - /* - * The CPACR.ZEN controls traps to EL1: - * 0, 2 : trap EL0 and EL1 accesses - * 1 : trap only EL0 accesses - * 3 : trap no accesses - */ - if (!extract32(env->cp15.cpacr_el1, 16, 1)) { - disabled =3D true; - } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) { - disabled =3D el =3D=3D 0; - } - if (disabled) { - /* route_to_el2 */ - return hcr_el2 & HCR_TGE ? 2 : 1; - } - - /* Check CPACR.FPEN. */ - if (!extract32(env->cp15.cpacr_el1, 20, 1)) { - disabled =3D true; - } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) { - disabled =3D el =3D=3D 0; - } - if (disabled) { - return 0; - } - } - - /* - * CPTR_EL2. Since TZ and TFP are positive, - * they will be zero when EL2 is not present. - */ - if (el <=3D 2 && arm_is_el2_enabled(env)) { - if (env->cp15.cptr_el[2] & CPTR_TZ) { - return 2; - } - if (env->cp15.cptr_el[2] & CPTR_TFP) { - return 0; - } - } - - /* CPTR_EL3. Since EZ is negative we must check for EL3. */ - if (arm_feature(env, ARM_FEATURE_EL3) - && !(env->cp15.cptr_el[3] & CPTR_EZ)) { - return 3; - } -#endif - return 0; -} - void hw_watchpoint_update(ARMCPU *cpu, int n) { CPUARMState *env =3D &cpu->env; --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622831118; cv=none; d=zohomail.com; s=zohoarc; b=aSHP+6AUWa/jlGeev5mhcxAk2P3jl3X7wQeA6hWNJwU9KxuzZYc6D2aKQAxer6j62SRdu/Q3xsc8umx1wjIO2HYCgEMCAzVlGNkhUywlV8SyCNFTYZB92u8HA7TbG5MzuRg6SKMye7Oy/wXkVwuzaBWMXl1hZ3XCJFnq3iBH6Gs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622831118; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3KAvFYDicdu7I7b7IT8uHA37bMcceuspcA95AajAGsA=; b=R7y/NhQTyxaIl3Pmv9l01hsGalTSGq+pIDtt86qCGg4rtSiWzftqp2Ves2yMZxIVaqCUQmwbRxQiFXv02YeRiCon6/659kNiQKV2ZYDnQ9NaugX7qFQThVh/eAwooBRjqMreMuTLXoJFePe1jjc64rSWGbIkM8IkKkvY+Grj93w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622831118523722.0288314226221; Fri, 4 Jun 2021 11:25:18 -0700 (PDT) Received: from localhost ([::1]:45092 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpEVR-0000YO-ED for importer@patchew.org; Fri, 04 Jun 2021 14:25:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42348) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpET3-0000sR-98 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 14:22:49 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:39770) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpESx-0000LY-N6 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 14:22:49 -0400 Received: by mail-wr1-x42a.google.com with SMTP id l2so10209678wrw.6 for ; Fri, 04 Jun 2021 11:22:43 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id n9sm6505994wmc.20.2021.06.04.11.22.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 11:22:38 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 88BB61FFC5; Fri, 4 Jun 2021 16:53:18 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3KAvFYDicdu7I7b7IT8uHA37bMcceuspcA95AajAGsA=; b=GI+fjp4jLaxZpQN5torVy0zwYR8zaOzI5CHG5ZYstagfUGHVKfx2vkG8tBc80c1MTS yEu4K5O/KlfZzokVbggY5rqI3SamKAG2Jd4IxC7KYDgNiyq7WshXs8TCjGLall/vbl3u A4z5GfWxEy8ttjkyEsbVnOE0HRg8CgLcA6adD1R5oi8M9cVdD4rCZ3MrBDQ9ruDZWIoJ MXsSdReA35V17MlW1oR5TvWnwWmmt7MxKcLCOHn1MyZE2FjOVw67x1r4p4iWuJ5Mku42 psh7l7mC0aogOtAMENmZoc7/xWlMx0CtdJAhckZXMSqXAKGg+K6921xWGcN5Vx+3UTmP wV/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3KAvFYDicdu7I7b7IT8uHA37bMcceuspcA95AajAGsA=; b=KxU6UQKumX4d6cNKhpbm+Iiox/UYgewgzbIs53tGKbYz2MNvu59Vs9LmG4EnTXODO2 z8Hg06r7+BvAZhvkDwhODv4qclRNs7ah+HwJ/KAV4FZja6piCjp4ItwYWyIFmriWM4Xi 0UWymeZXbszpfCo1fQ2jx16O/HhT64WRi67GeroliiCBiNFIQwftReAKGXguecuplwHA rOrhxhDpio3kNzKVzW4T1dhv51eAyK0r9eUZhojwyAIuujtbgQP8lUjJXbb5+V5fkQO2 Bbm6W5orS0C3gtqB74M9Lb8D7/Lwt7WKxpB3zwHmwZPPsews6YHzEgyZdbsGevG7PzyP fgHg== X-Gm-Message-State: AOAM5328ReBCStpr5r5kVuLWJwk3D7D66Kj8dyezAVEPZtK1aA5alN0/ EwrxXhvVWEyq3ElQ/Em0lzoKlg== X-Google-Smtp-Source: ABdhPJzIMCZIK0Z9HYPc827mDj2CuvEe9FxCKtHpWigzurSkYxSr/2ipMkGi5CaCpryxW1oRUf93QQ== X-Received: by 2002:adf:d204:: with SMTP id j4mr5196908wrh.3.1622830962339; Fri, 04 Jun 2021 11:22:42 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 46/99] target/arm: fix comments style of fp_exception_el before moving it Date: Fri, 4 Jun 2021 16:52:19 +0100 Message-Id: <20210604155312.15902-47-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/helper.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index 8372089260..d4cafdbd95 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -1625,13 +1625,15 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val,= uint32_t bytes) return crc32c(acc, buf, bytes) ^ 0xffffffff; } =20 -/* Return the exception level to which FP-disabled exceptions should +/* + * Return the exception level to which FP-disabled exceptions should * be taken, or 0 if FP is enabled. */ int fp_exception_el(CPUARMState *env, int cur_el) { #ifndef CONFIG_USER_ONLY - /* CPACR and the CPTR registers don't exist before v6, so FP is + /* + * CPACR and the CPTR registers don't exist before v6, so FP is * always accessible */ if (!arm_feature(env, ARM_FEATURE_V6)) { @@ -1654,7 +1656,8 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 0; } =20 - /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: + /* + * The CPACR controls traps to EL1, or PL1 if we're 32 bit: * 0, 2 : trap EL0 and EL1/PL1 accesses * 1 : trap only EL0 accesses * 3 : trap no accesses @@ -1701,7 +1704,8 @@ int fp_exception_el(CPUARMState *env, int cur_el) } } =20 - /* For the CPTR registers we don't need to guard with an ARM_FEATURE + /* + * For the CPTR registers we don't need to guard with an ARM_FEATURE * check because zero bits in the registers mean "don't trap". */ =20 --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622827260; cv=none; d=zohomail.com; s=zohoarc; b=eNrYYxkH0/BErkljC5X4egFHvi9iFsH8Je3ISFsX2dNYJBL3QJT2W6smptc4jsTHIubdgF62qwxUbYfTyQJ/+wZgr3DfxOLz60jX20ChdkSLZ/7GBim6/ZFbSufRwMUe5CSb8tP+gMNBXDo8MJqkzOSnFOLj0ynzcpkIZL4rUzY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622827260; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=U5Xfw9YPhDKbocOUkGJ6dyaTOmUWedj5SAgt0+6wAY8=; b=a4ziw9rKA3KnIDsviO/UOkunIhyxBG466lDz4orxegK34WF3d0DhqhYWam74pCWI6YOimmhP+H47Do0nZfqO98N0znIRWFL22II3XhZmCeOPELFK0aHIeXkJFYyHWshtyr2fH5FzQneAK8PWnsJCU/wUFQIA8TAAH0bG+TFMiHo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622827260274902.4143779452996; Fri, 4 Jun 2021 10:21:00 -0700 (PDT) Received: from localhost ([::1]:51754 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDVB-0001yr-1W for importer@patchew.org; Fri, 04 Jun 2021 13:20:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33554) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCkg-0008Gt-8F for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:32:54 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:45676) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCkY-00028v-VE for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:32:54 -0400 Received: by mail-wr1-x430.google.com with SMTP id z8so9890074wrp.12 for ; Fri, 04 Jun 2021 09:32:46 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id z3sm7638834wrl.13.2021.06.04.09.32.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:43 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A38E51FFC6; Fri, 4 Jun 2021 16:53:18 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=U5Xfw9YPhDKbocOUkGJ6dyaTOmUWedj5SAgt0+6wAY8=; b=dvCxY719d/0Gualat41bhM6mcAkf30N5uTmv8+TgAlljASfURjug1+inD/wQOSZjmW PI40sntvmkx7vY45zvYLrpyqowP8rzKUMCORsKlb+EYsM5rLyJYmsSxKDrkMplUyvtDi re+8zdsgdwLkIT6iJ7gLQKcGEFvXlnRPKCupEI5I8dYNlxYNB5ewa9qZHp3UXw+CB5iu J0qoOX3BHIRJUTLL4/1s1Z5jOUqkYWMNNHEjDe155aWtdl6QBk4HZSPbOdI6TcdKwQSm 3WRR+ZHph0SNRoxdYBTEczRJVosgj3uEa9RJ3+heR7UuYoiq5jX/EpVzjUcydAfU5mz7 gPig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=U5Xfw9YPhDKbocOUkGJ6dyaTOmUWedj5SAgt0+6wAY8=; b=o6b1Ke27aYqkod5PcoEqWiYhtLIbx1OQtX8Q7cdYaJKGFPyDZtIEL/BLPlfPYJ0Mvj gbyAVfwWyZFFNQ7l2irom+rKseD3A0468lPmlFRfp8chcKlru3mwGU0r439NXesx21QW onEOFjsxWUV8zWY8k1zk6JqVqP0tJiEXU5PWhNMTRewOs6QjIE4kyZdfqvRcqvRAKS4R S7hmkBcGAAs7yRviQXGypnm02Lv8LGMJdspPiNH/I7Xz3BEjlFTZ8UGZX5Dt33X7XWJx KbKxKSaTgn/oLHoevnWMq9NcADacpeoMIbJtGGD66NV40qEEk9yTS9YYhgv4qjQg7IxP IvRg== X-Gm-Message-State: AOAM531YONSBfOvP3D3bommppgQs84iA2bO8MurcuZWTr6Izx11FGIJ5 zDadCFslpBY+7nS9sZhl6Wg0jvDHoDF3+Q== X-Google-Smtp-Source: ABdhPJxHpS+GVDfK7kko4JAzVgMoqxILFFXUl5oQkDMOA6oNHAU0BxJsSihPgNJzivByqEaFfUxnag== X-Received: by 2002:adf:e507:: with SMTP id j7mr4685178wrm.178.1622824365471; Fri, 04 Jun 2021 09:32:45 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 47/99] target/arm: move fp_exception_el out of TCG helpers Date: Fri, 4 Jun 2021 16:52:20 +0100 Message-Id: <20210604155312.15902-48-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-sysemu.c | 100 ++++++++++++++++++++++++++++++++++++++++ target/arm/cpu-user.c | 5 ++ target/arm/tcg/helper.c | 100 ---------------------------------------- 3 files changed, 105 insertions(+), 100 deletions(-) diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c index 7cc721fe68..128616d90d 100644 --- a/target/arm/cpu-sysemu.c +++ b/target/arm/cpu-sysemu.c @@ -410,3 +410,103 @@ int sve_exception_el(CPUARMState *env, int el) } return 0; } + +/* + * Return the exception level to which FP-disabled exceptions should + * be taken, or 0 if FP is enabled. + */ +int fp_exception_el(CPUARMState *env, int cur_el) +{ +#ifndef CONFIG_USER_ONLY + /* + * CPACR and the CPTR registers don't exist before v6, so FP is + * always accessible + */ + if (!arm_feature(env, ARM_FEATURE_V6)) { + return 0; + } + + if (arm_feature(env, ARM_FEATURE_M)) { + /* CPACR can cause a NOCP UsageFault taken to current security sta= te */ + if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el !=3D 0)) { + return 1; + } + + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) { + if (!extract32(env->v7m.nsacr, 10, 1)) { + /* FP insns cause a NOCP UsageFault taken to Secure */ + return 3; + } + } + + return 0; + } + + /* + * The CPACR controls traps to EL1, or PL1 if we're 32 bit: + * 0, 2 : trap EL0 and EL1/PL1 accesses + * 1 : trap only EL0 accesses + * 3 : trap no accesses + * This register is ignored if E2H+TGE are both set. + */ + if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { + int fpen =3D extract32(env->cp15.cpacr_el1, 20, 2); + + switch (fpen) { + case 0: + case 2: + if (cur_el =3D=3D 0 || cur_el =3D=3D 1) { + /* Trap to PL1, which might be EL1 or EL3 */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { + return 3; + } + return 1; + } + if (cur_el =3D=3D 3 && !is_a64(env)) { + /* Secure PL1 running at EL3 */ + return 3; + } + break; + case 1: + if (cur_el =3D=3D 0) { + return 1; + } + break; + case 3: + break; + } + } + + /* + * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode + * to control non-secure access to the FPU. It doesn't have any + * effect if EL3 is AArch64 or if EL3 doesn't exist at all. + */ + if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && + cur_el <=3D 2 && !arm_is_secure_below_el3(env))) { + if (!extract32(env->cp15.nsacr, 10, 1)) { + /* FP insns act as UNDEF */ + return cur_el =3D=3D 2 ? 2 : 1; + } + } + + /* + * For the CPTR registers we don't need to guard with an ARM_FEATURE + * check because zero bits in the registers mean "don't trap". + */ + + /* CPTR_EL2 : present in v7VE or v8 */ + if (cur_el <=3D 2 && extract32(env->cp15.cptr_el[2], 10, 1) + && arm_is_el2_enabled(env)) { + /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ + return 2; + } + + /* CPTR_EL3 : present in v8 */ + if (extract32(env->cp15.cptr_el[3], 10, 1)) { + /* Trap all FP ops to EL3 */ + return 3; + } +#endif + return 0; +} diff --git a/target/arm/cpu-user.c b/target/arm/cpu-user.c index 39093ade76..6a1a1fa273 100644 --- a/target/arm/cpu-user.c +++ b/target/arm/cpu-user.c @@ -38,3 +38,8 @@ int sve_exception_el(CPUARMState *env, int el) { return 0; } + +int fp_exception_el(CPUARMState *env, int el) +{ + return 0; +} diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index d4cafdbd95..e55209491f 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -1625,106 +1625,6 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val,= uint32_t bytes) return crc32c(acc, buf, bytes) ^ 0xffffffff; } =20 -/* - * Return the exception level to which FP-disabled exceptions should - * be taken, or 0 if FP is enabled. - */ -int fp_exception_el(CPUARMState *env, int cur_el) -{ -#ifndef CONFIG_USER_ONLY - /* - * CPACR and the CPTR registers don't exist before v6, so FP is - * always accessible - */ - if (!arm_feature(env, ARM_FEATURE_V6)) { - return 0; - } - - if (arm_feature(env, ARM_FEATURE_M)) { - /* CPACR can cause a NOCP UsageFault taken to current security sta= te */ - if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el !=3D 0)) { - return 1; - } - - if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) { - if (!extract32(env->v7m.nsacr, 10, 1)) { - /* FP insns cause a NOCP UsageFault taken to Secure */ - return 3; - } - } - - return 0; - } - - /* - * The CPACR controls traps to EL1, or PL1 if we're 32 bit: - * 0, 2 : trap EL0 and EL1/PL1 accesses - * 1 : trap only EL0 accesses - * 3 : trap no accesses - * This register is ignored if E2H+TGE are both set. - */ - if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { - int fpen =3D extract32(env->cp15.cpacr_el1, 20, 2); - - switch (fpen) { - case 0: - case 2: - if (cur_el =3D=3D 0 || cur_el =3D=3D 1) { - /* Trap to PL1, which might be EL1 or EL3 */ - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { - return 3; - } - return 1; - } - if (cur_el =3D=3D 3 && !is_a64(env)) { - /* Secure PL1 running at EL3 */ - return 3; - } - break; - case 1: - if (cur_el =3D=3D 0) { - return 1; - } - break; - case 3: - break; - } - } - - /* - * The NSACR allows A-profile AArch32 EL3 and M-profile secure mode - * to control non-secure access to the FPU. It doesn't have any - * effect if EL3 is AArch64 or if EL3 doesn't exist at all. - */ - if ((arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && - cur_el <=3D 2 && !arm_is_secure_below_el3(env))) { - if (!extract32(env->cp15.nsacr, 10, 1)) { - /* FP insns act as UNDEF */ - return cur_el =3D=3D 2 ? 2 : 1; - } - } - - /* - * For the CPTR registers we don't need to guard with an ARM_FEATURE - * check because zero bits in the registers mean "don't trap". - */ - - /* CPTR_EL2 : present in v7VE or v8 */ - if (cur_el <=3D 2 && extract32(env->cp15.cptr_el[2], 10, 1) - && arm_is_el2_enabled(env)) { - /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ - return 2; - } - - /* CPTR_EL3 : present in v8 */ - if (extract32(env->cp15.cptr_el[3], 10, 1)) { - /* Trap all FP ops to EL3 */ - return 3; - } -#endif - return 0; -} - #ifndef CONFIG_USER_ONLY ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) { --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622827416; cv=none; d=zohomail.com; s=zohoarc; b=g0kTrYOss1pX2WbdGz9r5H81RHgFBWl6icw5oEl0p2hAYUWEeKge/ilXqO6bAYAy9ap9rCXmAgo3coczscsIRFOrKHgzpbJwAdpi6NT40ZuzlPm/BDA7LNxoRW6HFd9HZXTb9wFwRFxtvPITbsV/oeC44cZgIQBrKX3EsZZ70cE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622827416; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LPmHXyzWsrCuMzUxwCKFj0W0fSkTFbn/I48VNDyaKbw=; b=GwQBlD8vsoZ8GiivDS2oCdA4BwhaBSASBJ46nebjlCbgohQIVmWF//f7yH7a+CIvQNGtFSqyZ5MQY6aZZjmLyXIa/xWaLK9e4uNc2i+fDnOgpcu1rQpDFx67WoK7ImN08wWlTVEPwJ/kObbk55DyE8fjWf9g/HqDqkKWQL3qb+c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622827416433152.7843589320173; Fri, 4 Jun 2021 10:23:36 -0700 (PDT) Received: from localhost ([::1]:33916 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDXj-00015i-G8 for importer@patchew.org; Fri, 04 Jun 2021 13:23:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33804) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCkv-0000Fj-Bp for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:09 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:53775) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCkh-0002DX-U1 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:09 -0400 Received: by mail-wm1-x32f.google.com with SMTP id h3so5739613wmq.3 for ; Fri, 04 Jun 2021 09:32:54 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id w8sm7616636wre.70.2021.06.04.09.32.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:51 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id B876F1FFC7; Fri, 4 Jun 2021 16:53:18 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LPmHXyzWsrCuMzUxwCKFj0W0fSkTFbn/I48VNDyaKbw=; b=Hp5Um09J0bXhrMEoUkbEEzJATqdnAgYzcIYwuG/zu5QbZYX5AU48t5a+Icee38RnVH XHtBQwqixuvqTyK5SsGCb6C+pxCTluBaYwTHut1bFGBXDLJhzj3EHJfyKwYxe3hC5OA/ H3oitPRdFDyW7nEAu+HkD2XpphTkwjoZ4UwOOIjm1w1pysPEMNSP03txpzJ9v9p8dVcx GjaRdehBX7m8wX+lGJqFLwtggfbkbI/EDonV77D4jbzHCD5KdjHHXPwzlZymmx0+fENo A/s7YiMTeatI00xvZ/k05to6gjLh6fbGP6YnJD4dsjQafIgCBTIdShBc1CwrF1wlwKzv bEjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LPmHXyzWsrCuMzUxwCKFj0W0fSkTFbn/I48VNDyaKbw=; b=nO9IukVspBBxKGAoqUb8CvE6kOX/LJ623jIo502T29i34SsH2M4aabnrBWZrxze2n0 MO/Dtzg1bKhTyxvqs9yINRtEFUASuLGXoHpEanThLyA4Co8ArHQ0agSAgJVuNswTx1Mk 16T4vEfimnEHnMVeaNCgd9AM/wYF1GOgIgMFw9GswV8e2jFzA0Jq9mwdVhpAvCGFnEK/ f4YVONG8JqJfGQdU8D+5m9vWTlzDfvmb42HzZs4xxPy/Qf2wRIHQFg4Nyhg1+asZqkUg mey0L4UuPH3pa+91qSJt8BKzMVh6o1MAEfTVi6mYHlhiydgORarQervzoHUZfGgkDwTp 7FDA== X-Gm-Message-State: AOAM533XiQkpcpLoeIHIikOJL8vUdivU26V76oduL+8pKus5mS6gjxfK v3eKu+vZ3590gnbmR1enl2nwgQ== X-Google-Smtp-Source: ABdhPJzQWRpTiuOlBVh1aivSVmUKFvbq7GGemfUc34ENzVSb5lrFsMruDvCRetmkD9bWn7D4ZjhdIQ== X-Received: by 2002:a1c:e409:: with SMTP id b9mr4350498wmh.63.1622824374142; Fri, 04 Jun 2021 09:32:54 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 48/99] target/arm: remove now useless ifndef from fp_exception_el Date: Fri, 4 Jun 2021 16:52:21 +0100 Message-Id: <20210604155312.15902-49-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana after moving the code of fp_exception_el to a sysemu-only module, we can remove the #ifndef CONFIG_USER_ONLY. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-sysemu.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c index 128616d90d..0d80a0161c 100644 --- a/target/arm/cpu-sysemu.c +++ b/target/arm/cpu-sysemu.c @@ -417,7 +417,6 @@ int sve_exception_el(CPUARMState *env, int el) */ int fp_exception_el(CPUARMState *env, int cur_el) { -#ifndef CONFIG_USER_ONLY /* * CPACR and the CPTR registers don't exist before v6, so FP is * always accessible @@ -507,6 +506,5 @@ int fp_exception_el(CPUARMState *env, int cur_el) /* Trap all FP ops to EL3 */ return 3; } -#endif return 0; } --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622827556; cv=none; d=zohomail.com; s=zohoarc; b=nRMWFBSkXDYKB9L+6w8nnpjIfXvJQGb64+GuVRpGvCJaQIGWqJ+7JfyXuAw1GOZnThXy+NmcLWFXtQmgOqwxqVoyfizSJFvxY586Q4/SHgb3Osc6O+FrurJxSIMW4jGtN5VYS31oOlNQhbjhuD9eNesqcVLZFGSgc8AZbR42YSk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622827556; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TGls5/xkSiHs03kC6I1GwTGP4oM62lUtA402V/b7XoA=; b=NnOEHsH3ZuU3pBNSgdricoYQYrllm7TVFyl1YgUb7DhFaTRMp+/o+QjBO8ayCUyJroKdOF6pDxT3jsSc8l1rZEzNKNNBIFmF7m5VHP/1opsIMLn0IjJpNW1tDSW7io+lKA0KFD5cZ3t8XtK44UonK3z1E4VZjIg8rVenywF9LIw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622827556051849.4563284903579; Fri, 4 Jun 2021 10:25:56 -0700 (PDT) Received: from localhost ([::1]:40724 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDZy-0005fC-VO for importer@patchew.org; Fri, 04 Jun 2021 13:25:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33840) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCkx-0000Ob-3A for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:11 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:40802) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCkj-0002E0-EN for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:10 -0400 Received: by mail-wr1-x431.google.com with SMTP id y7so5278165wrh.7 for ; Fri, 04 Jun 2021 09:32:56 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id z188sm6319994wme.38.2021.06.04.09.32.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:51 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id CDBD01FFC8; Fri, 4 Jun 2021 16:53:18 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TGls5/xkSiHs03kC6I1GwTGP4oM62lUtA402V/b7XoA=; b=AWlGkHoBjDmLboTSeIgJAIFnHs3uSzsXAglphhqsOnLeoWXAk5rJpXknTQnefHCY8O tPvsg6BCnNmX/N/65jZpUL/4uUuTJnLkAsLnBxIw4tA4rJcNW325hSpJTS5yzMdmFSd0 rRh/uxrr5nfzHz1H5Wyk53vIFqfts2LzIHAgYdUp+M8Zh/jbtY4qkVU+BrKPW7RwVFLU le4/tX1K8l+oQS7P0pO4qIO9phPrv6X/MLN8YD4NU+3ukWxnWynWSmV0Ayp5TPB6D6gh laI0jpB8AmZwo4DKpltJTN+Hu/J339fcOFJGxxM4iTSA4AzPIpDnRnp0D0o4j2pfCSZo wvuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TGls5/xkSiHs03kC6I1GwTGP4oM62lUtA402V/b7XoA=; b=UcrMmBuQt8hIq/FGWm/j0laQWKCjoAh7hd6gO7lhxV7TshJVgynIBzr5k8r+aQ0hxl B6+1tKlu5V5c9zO0eu56RxuONSBVZgrxLeUtFTe4wXBicq4ANL5aehk6EMO4Ly9VFJGs qGeXIu/siZgL7It84GtXSTjKI9FV0k76MSFP3vgx8UEIK/tJZ5j55xmJ7BGYK8MuNO8h +dswEAocVIY7BpIJW167T1aiy/b6qGnqU39QrQvFyBKvAAuKkgK7KCvSkCK75WB4ch4m wr0aX4nvbmH3oNjsZvdi9+gxknuHwn+mxrxVRHsURBIEqu2OLRRIwZQsvaNZ2Q/kPirO KZrg== X-Gm-Message-State: AOAM530ZrGfhIjNZAGIghKY2tTcTqssYpGjMRjQDA+TLqkSOjWPg2g2x +c+yvhl7zp2QHl9FapY3RS9COQ== X-Google-Smtp-Source: ABdhPJzbo3W+julGBk+CbWKKadH49wN6Yl1QZyP9dZ29zTzVpGlEHvkazrJr6hAKX05FmzGwncqO2A== X-Received: by 2002:a5d:6e92:: with SMTP id k18mr4873333wrz.94.1622824375706; Fri, 04 Jun 2021 09:32:55 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 49/99] target/arm: make further preparation for the exception code to move Date: Fri, 4 Jun 2021 16:52:22 +0100 Message-Id: <20210604155312.15902-50-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana the exception code in tcg/ needs some adjustment before being exposed to KVM-only builds. We need to call arm_rebuild_hflags only when TCG is enabled, or we will error out. The direct call to helper_rebuild_hflags_a64(env, new_el) will not be possible when extracting out to common code, it seems safe to replace it with a call to arm_rebuild_hflags, since the write to pstate is already done. Also, some CONFIG_TCG needs to be extended further, so that all the tcg-only code is marked as such. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/helper.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index e55209491f..7a9eaec5cb 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -755,7 +755,9 @@ static void take_aarch32_exception(CPUARMState *env, in= t new_mode, env->regs[14] =3D env->regs[15] + offset; } env->regs[15] =3D newpc; - arm_rebuild_hflags(env); + if (tcg_enabled()) { + arm_rebuild_hflags(env); + } } =20 static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) @@ -1242,7 +1244,11 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *c= s) pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 =3D 1; aarch64_restore_sp(env, new_el); - helper_rebuild_hflags_a64(env, new_el); + + if (tcg_enabled()) { + /* pstate already written, so we can use arm_rebuild_hflags here */ + arm_rebuild_hflags(env); + } =20 env->pc =3D addr; =20 @@ -1306,6 +1312,7 @@ void arm_cpu_do_interrupt(CPUState *cs) env->exception.syndrome); } =20 +#ifdef CONFIG_TCG if (arm_is_psci_call(cpu, cs->exception_index)) { arm_handle_psci_call(cpu); qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); @@ -1317,7 +1324,6 @@ void arm_cpu_do_interrupt(CPUState *cs) * that caused the exception, not the target exception level, so * must be handled here. */ -#ifdef CONFIG_TCG if (cs->exception_index =3D=3D EXCP_SEMIHOST) { handle_semihosting(cs); return; --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622827330; cv=none; d=zohomail.com; s=zohoarc; b=IqVeH2fVa5NfxfDb9MFExlaETFlnvgo1d+WgBVGd+yCV9HuptNHbJzZhxYrWgELZH+D4C3yxX3+M1laPDAQUoXmraDbTwoQ4HpWhqOjXuF6l8moURpiCw4t4SB1lWxU5ZCYPguBiGSXun3K4sBkqY0SfnvBtvtXiuuYIP6n0KZ0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622827330; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mjzS7rj1kweufgd0g3lBR+KBKwJLQAXc4Hnok/aBO4c=; b=eGQmU0CaqK7btDa1nj6xU+V732rGtNPvzCefMJMDfextAUecU8nIM7b/VfGiVDiFFXA0BDB/E0Ccu9w9TvqHLFn7iumLBylFmoIFfYU+z5G49zZw20CN4kwDC1e/yUukGe9nPG/uudofWJcX7iVykkBmDZ6MxUESGnTmS/9nfOU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16228273300436.3913387438985865; Fri, 4 Jun 2021 10:22:10 -0700 (PDT) Received: from localhost ([::1]:55848 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDWK-00052h-Uk for importer@patchew.org; Fri, 04 Jun 2021 13:22:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48834) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpDNN-0008NF-HE for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:53 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:39734) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpDNK-00024l-8b for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:53 -0400 Received: by mail-wr1-x432.google.com with SMTP id l2so10038347wrw.6 for ; Fri, 04 Jun 2021 10:12:49 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id c7sm7120966wrs.23.2021.06.04.10.12.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 10:12:46 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id E742A1FFC9; Fri, 4 Jun 2021 16:53:18 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mjzS7rj1kweufgd0g3lBR+KBKwJLQAXc4Hnok/aBO4c=; b=m+OG1jD3er5DoGVh6n5An8FjIQSgCK2ZHONXOzHjAEQAdYg/xighy0WgtT6+cWr7y6 /HXEOXnxbQWVo/0Ny9Ejk23ggbTMVqx3Od24w9xXZFsuEf5T8PkvX4+UNtY8WYGQ5EC7 YKVy7zbHZr0S0NG1/i/GRaq5xJT+hnUcFkY7D+5xL9NaqOFtTuQ2rWJ94og9n4VgNZH3 cybkqigSVvx67ymJU8nMRLvZAcboWRwUNSceK3j9SYowuqh7hdxyopm+jazgE8Zxyebb jV7T1TRP4Dn2Mnfru0nKvInur1VnfXQFSJUocMIhxARhVqMU33bvY78Y1TZR4XAYx/lW GnMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mjzS7rj1kweufgd0g3lBR+KBKwJLQAXc4Hnok/aBO4c=; b=URE++Eb1XoNNYduZ4gopnmscVo6ROW8RdA2OXWHMhmjYXxNBZQIHDtHj+2FaWZC4T5 7Uu24s0moiAgb75VM2YFI0UGfWUQGzBmssV7YcCsCAoPYuOVZUOpToSGLCOYYprBohlw ZZ6b5Mtlr0vux07VEsyQcMU4gLjy4MeB2xx8Ni2VHGv51oO4k5ejblCEwLBi+ScTnIc+ o4ToU/2bT12h6ox5T7G1juMrlyxtzwEmlnmVZmqY2N+LDMD1E6KkTo9dpAmEGjrPgiMO FXSa/WUL8NY5pgUd7jT2iCXimbuTc6qSXcOlFHntcMUbT3owfzqLtXs2yVtRBLeH6fNo ZCpw== X-Gm-Message-State: AOAM5308q/Uwlfg8vlfJee1XdqkUbtxVWXDh3EXx5lhh4y10b0yQ201k R9YUc0A/hFtNQUpHVmRedzJsqg== X-Google-Smtp-Source: ABdhPJxvRMYt3LOwSK4GtYWdpSmfnq6rEyTqjm8e2iJuXeKmGd/Zc8j8NgClAiz93F9FdaP/reBa7g== X-Received: by 2002:a5d:4304:: with SMTP id h4mr5051852wrq.210.1622826768904; Fri, 04 Jun 2021 10:12:48 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 50/99] target/arm: fix style of arm_cpu_do_interrupt functions before move Date: Fri, 4 Jun 2021 16:52:23 +0100 Message-Id: <20210604155312.15902-51-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana before refactoring the exception code, fix the style of the functions being moved. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/helper.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index 7a9eaec5cb..5b32329895 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -896,10 +896,11 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) new_mode =3D ARM_CPU_MODE_UND; addr =3D 0x04; mask =3D CPSR_I; - if (env->thumb) + if (env->thumb) { offset =3D 2; - else + } else { offset =3D 4; + } break; case EXCP_SWI: new_mode =3D ARM_CPU_MODE_SVC; @@ -985,7 +986,8 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *cs) /* High vectors. When enabled, base address cannot be remapped. */ addr +=3D 0xffff0000; } else { - /* ARM v7 architectures provide a vector base address register to = remap + /* + * ARM v7 architectures provide a vector base address register to = remap * the interrupt vector table. * This register is only followed in non-monitor mode, and is bank= ed. * Note: only bits 31:5 are valid. @@ -1094,7 +1096,8 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); =20 if (cur_el < new_el) { - /* Entry vector offset depends on whether the implemented EL + /* + * Entry vector offset depends on whether the implemented EL * immediately lower than the target level is using AArch32 or AAr= ch64 */ bool is_aa64; @@ -1285,7 +1288,8 @@ static void handle_semihosting(CPUState *cs) } #endif =20 -/* Handle a CPU exception for A and R profile CPUs. +/* + * Handle a CPU exception for A and R profile CPUs. * Do any appropriate logging, handle PSCI calls, and then hand off * to the AArch64-entry or AArch32-entry function depending on the * target exception level's register width. @@ -1330,7 +1334,8 @@ void arm_cpu_do_interrupt(CPUState *cs) } #endif =20 - /* Hooks may change global state so BQL should be held, also the + /* + * Hooks may change global state so BQL should be held, also the * BQL needs to be held for any modification of * cs->interrupt_request. */ --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622825524; cv=none; d=zohomail.com; s=zohoarc; b=PgjCgBAoI21sf5L2q+DZ+fx3fwU5DPx3mIaIJv3RaRbidS6w0r7oDsJz7JXjKIdIlTZTSH07/rmjljYb2iW08AYdphEhDlWFXIB/368jnEiNy3DcsXpWlAqr7LGUO3yheTS2QgRVXeon8ntCMROruEhT7d1ybekLbtPrH5SJAlc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622825524; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=P3B7XmJwW9fFwkfNwwGD8GDyI0xFISRu6PoXARUE8XU=; b=jYGbVAYbTL3aDM7UBTYX0fpSdoLvtduexg3IhmKKTNF2y6j7hNoqVhZEki/WCk7w4OpqCJxYgGXKS+vttOkPz5R3DUREN8T42Uo/Le4PoP7W6hz1Tjnk7ABo6ma5Axw27v9479U0SIGG7pELaJtWKglDiJeuqlJ3H8HXgfTae3w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622825524875590.7394511714904; Fri, 4 Jun 2021 09:52:04 -0700 (PDT) Received: from localhost ([::1]:35044 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpD3C-0007it-PE for importer@patchew.org; Fri, 04 Jun 2021 12:52:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52124) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCRY-0003ME-A3 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:13:08 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:39471) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCRK-0003rV-Ew for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:13:08 -0400 Received: by mail-wm1-x32d.google.com with SMTP id l18-20020a1ced120000b029014c1adff1edso8239198wmh.4 for ; Fri, 04 Jun 2021 09:12:53 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id g205sm2396764wme.6.2021.06.04.09.12.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:12:42 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 162A21FFCA; Fri, 4 Jun 2021 16:53:19 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P3B7XmJwW9fFwkfNwwGD8GDyI0xFISRu6PoXARUE8XU=; b=nIZ7ql/DP/LRM+EE1HRrFHKirq+xHTtxtqUeVS93dgsG5PmdmBUclcxNOkIp5rYdZw ylunbUnggtTqJdwy1HPiQIp/GqsqozCfwSIBx85DjWHtNZSPIzjqO+dflVoIYAf/cPmB uqC2MaO6UoVyCAEK1x7MnX0scHdwVCIWaxUlTCqnY3PybuN28FPEAWA70quvyZkWnQT+ n9xwpD24FG9rbfQPwbVv82AhD8TVa4rQ4qO1oGdmjDEybETY17zssCmI3NGouu/X7UT5 gts9+V+821d4TWv2kDC+u/Jwm1Ju8U4hr5lQavVOc5QaqQk8HEw6Zwz9IsBLvEk1avyj O8KQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P3B7XmJwW9fFwkfNwwGD8GDyI0xFISRu6PoXARUE8XU=; b=S64GC5pVgzNBSsg9tCEwutmXotIYatxA7GoXzsQOYr4O3qCy5W2X0jcjp43vlI6Dq3 vBW8ako49tGESDj6U0fMOMbmmMhzI+/nIHDAVS7G8JfHkOYGnFBfTmJE2twB29EM/w5A esE4hZZG5NRJK9yMa1/u81skb1hi4pE0O5tR9mQJB6NoyBPWwCL52qHlKbwiTjuetzFH Fqijk0dfcw9kqbciEt2+cQ1sIMzsDP6GMPnwPHHHBndCU9+MQBzTBx0SYpHRSdxWViR+ Qy+1boHPfd9azpTFwzwjnPmoSEdEz8H4l0dkuVv1bp6BwJP/nq9rkX0dQQJhqTrqAX6b ayyQ== X-Gm-Message-State: AOAM533BEcPvn8R7oZvZzXMm1iT6EEiiK4RPClahU0JI9pWsG9lD8jUd ZWF55EPjY5kDvR5qvzcpKkyWdwlBVDCY5A== X-Google-Smtp-Source: ABdhPJzbVat36lOa2SUwHE8hupjKhlmHNO9TnL4cBukCwnReu/pciGqqq/HUR3PoQDOeqpVwW3ClSw== X-Received: by 2002:a05:600c:2054:: with SMTP id p20mr4099638wmg.175.1622823172554; Fri, 04 Jun 2021 09:12:52 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 51/99] target/arm: move exception code out of tcg/helper.c Date: Fri, 4 Jun 2021 16:52:24 +0100 Message-Id: <20210604155312.15902-52-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana cpu-sysemu.c: we need this sysemu code for KVM too, so we move the code to cpu-sysemu.c so we can reach a builable state. There will be further split later on in dedicated exception modules for 32 and 64bit, after we make more necessary changes to be able to split TARGET_AARCH64-only code. tcg/sysemu/tcg-cpu.c: the TCG-specific code we put in tcg/sysemu/, in preparation for the addition of the tcg-cpu accel-cpu ARM subclass. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/tcg-cpu.h | 31 ++ target/arm/cpu-sysemu.c | 670 +++++++++++++++++++++++++++ target/arm/tcg/helper.c | 734 ------------------------------ target/arm/tcg/sysemu/tcg-cpu.c | 73 +++ target/arm/tcg/sysemu/meson.build | 1 + 5 files changed, 775 insertions(+), 734 deletions(-) create mode 100644 target/arm/tcg/tcg-cpu.h create mode 100644 target/arm/tcg/sysemu/tcg-cpu.c diff --git a/target/arm/tcg/tcg-cpu.h b/target/arm/tcg/tcg-cpu.h new file mode 100644 index 0000000000..0ee8ba073b --- /dev/null +++ b/target/arm/tcg/tcg-cpu.h @@ -0,0 +1,31 @@ +/* + * QEMU ARM CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ +#ifndef ARM_TCG_CPU_H +#define ARM_TCG_CPU_H + +#include "cpu.h" + +#ifndef CONFIG_USER_ONLY +/* Do semihosting call and set the appropriate return value. */ +void handle_semihosting(CPUState *cs); + +#endif /* !CONFIG_USER_ONLY */ + +#endif /* ARM_TCG_CPU_H */ diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c index 0d80a0161c..0e872b2e55 100644 --- a/target/arm/cpu-sysemu.c +++ b/target/arm/cpu-sysemu.c @@ -19,10 +19,14 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/main-loop.h" #include "cpu.h" #include "internals.h" #include "sysemu/hw_accel.h" #include "kvm_arm.h" +#include "sysemu/tcg.h" +#include "tcg/tcg-cpu.h" =20 void arm_cpu_set_irq(void *opaque, int irq, int level) { @@ -508,3 +512,669 @@ int fp_exception_el(CPUARMState *env, int cur_el) } return 0; } + +static void take_aarch32_exception(CPUARMState *env, int new_mode, + uint32_t mask, uint32_t offset, + uint32_t newpc) +{ + int new_el; + + /* Change the CPU state so as to actually take the exception. */ + switch_mode(env, new_mode); + + /* + * For exceptions taken to AArch32 we must clear the SS bit in both + * PSTATE and in the old-state value we save to SPSR_, so zero i= t now. + */ + env->pstate &=3D ~PSTATE_SS; + env->spsr =3D cpsr_read(env); + /* Clear IT bits. */ + env->condexec_bits =3D 0; + /* Switch to the new mode, and to the correct instruction set. */ + env->uncached_cpsr =3D (env->uncached_cpsr & ~CPSR_M) | new_mode; + + /* This must be after mode switching. */ + new_el =3D arm_current_el(env); + + /* Set new mode endianness */ + env->uncached_cpsr &=3D ~CPSR_E; + if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { + env->uncached_cpsr |=3D CPSR_E; + } + /* J and IL must always be cleared for exception entry */ + env->uncached_cpsr &=3D ~(CPSR_IL | CPSR_J); + env->daif |=3D mask; + + if (new_mode =3D=3D ARM_CPU_MODE_HYP) { + env->thumb =3D (env->cp15.sctlr_el[2] & SCTLR_TE) !=3D 0; + env->elr_el[2] =3D env->regs[15]; + } else { + /* CPSR.PAN is normally preserved preserved unless... */ + if (cpu_isar_feature(aa32_pan, env_archcpu(env))) { + switch (new_el) { + case 3: + if (!arm_is_secure_below_el3(env)) { + /* ... the target is EL3, from non-secure state. */ + env->uncached_cpsr &=3D ~CPSR_PAN; + break; + } + /* ... the target is EL3, from secure state ... */ + /* fall through */ + case 1: + /* ... the target is EL1 and SCTLR.SPAN is 0. */ + if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { + env->uncached_cpsr |=3D CPSR_PAN; + } + break; + } + } + /* + * this is a lie, as there was no c1_sys on V4T/V5, but who cares + * and we should just guard the thumb mode on V4 + */ + if (arm_feature(env, ARM_FEATURE_V4T)) { + env->thumb =3D + (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) !=3D 0; + } + env->regs[14] =3D env->regs[15] + offset; + } + env->regs[15] =3D newpc; + if (tcg_enabled()) { + arm_rebuild_hflags(env); + } +} + +static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) +{ + /* + * Handle exception entry to Hyp mode; this is sufficiently + * different to entry to other AArch32 modes that we handle it + * separately here. + * + * The vector table entry used is always the 0x14 Hyp mode entry point, + * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp. + * The offset applied to the preferred return address is always zero + * (see DDI0487C.a section G1.12.3). + * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. + */ + uint32_t addr, mask; + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (cs->exception_index) { + case EXCP_UDEF: + addr =3D 0x04; + break; + case EXCP_SWI: + addr =3D 0x14; + break; + case EXCP_BKPT: + /* Fall through to prefetch abort. */ + case EXCP_PREFETCH_ABORT: + env->cp15.ifar_s =3D env->exception.vaddress; + qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n", + (uint32_t)env->exception.vaddress); + addr =3D 0x0c; + break; + case EXCP_DATA_ABORT: + env->cp15.dfar_s =3D env->exception.vaddress; + qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n", + (uint32_t)env->exception.vaddress); + addr =3D 0x10; + break; + case EXCP_IRQ: + addr =3D 0x18; + break; + case EXCP_FIQ: + addr =3D 0x1c; + break; + case EXCP_HVC: + addr =3D 0x08; + break; + case EXCP_HYP_TRAP: + addr =3D 0x14; + break; + default: + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); + } + + if (cs->exception_index !=3D EXCP_IRQ && cs->exception_index !=3D EXCP= _FIQ) { + if (!arm_feature(env, ARM_FEATURE_V8)) { + /* + * QEMU syndrome values are v8-style. v7 has the IL bit + * UNK/SBZP for "field not valid" cases, where v8 uses RES1. + * If this is a v7 CPU, squash the IL bit in those cases. + */ + if (cs->exception_index =3D=3D EXCP_PREFETCH_ABORT || + (cs->exception_index =3D=3D EXCP_DATA_ABORT && + !(env->exception.syndrome & ARM_EL_ISV)) || + syn_get_ec(env->exception.syndrome) =3D=3D EC_UNCATEGORIZE= D) { + env->exception.syndrome &=3D ~ARM_EL_IL; + } + } + env->cp15.esr_el[2] =3D env->exception.syndrome; + } + + if (arm_current_el(env) !=3D 2 && addr < 0x14) { + addr =3D 0x14; + } + + mask =3D 0; + if (!(env->cp15.scr_el3 & SCR_EA)) { + mask |=3D CPSR_A; + } + if (!(env->cp15.scr_el3 & SCR_IRQ)) { + mask |=3D CPSR_I; + } + if (!(env->cp15.scr_el3 & SCR_FIQ)) { + mask |=3D CPSR_F; + } + + addr +=3D env->cp15.hvbar; + + take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr); +} + +static void arm_cpu_do_interrupt_aarch32(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + uint32_t addr; + uint32_t mask; + int new_mode; + uint32_t offset; + uint32_t moe; + + /* If this is a debug exception we must update the DBGDSCR.MOE bits */ + switch (syn_get_ec(env->exception.syndrome)) { + case EC_BREAKPOINT: + case EC_BREAKPOINT_SAME_EL: + moe =3D 1; + break; + case EC_WATCHPOINT: + case EC_WATCHPOINT_SAME_EL: + moe =3D 10; + break; + case EC_AA32_BKPT: + moe =3D 3; + break; + case EC_VECTORCATCH: + moe =3D 5; + break; + default: + moe =3D 0; + break; + } + + if (moe) { + env->cp15.mdscr_el1 =3D deposit64(env->cp15.mdscr_el1, 2, 4, moe); + } + + if (env->exception.target_el =3D=3D 2) { + arm_cpu_do_interrupt_aarch32_hyp(cs); + return; + } + + switch (cs->exception_index) { + case EXCP_UDEF: + new_mode =3D ARM_CPU_MODE_UND; + addr =3D 0x04; + mask =3D CPSR_I; + if (env->thumb) { + offset =3D 2; + } else { + offset =3D 4; + } + break; + case EXCP_SWI: + new_mode =3D ARM_CPU_MODE_SVC; + addr =3D 0x08; + mask =3D CPSR_I; + /* The PC already points to the next instruction. */ + offset =3D 0; + break; + case EXCP_BKPT: + /* Fall through to prefetch abort. */ + case EXCP_PREFETCH_ABORT: + A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); + A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); + qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", + env->exception.fsr, (uint32_t)env->exception.vaddres= s); + new_mode =3D ARM_CPU_MODE_ABT; + addr =3D 0x0c; + mask =3D CPSR_A | CPSR_I; + offset =3D 4; + break; + case EXCP_DATA_ABORT: + A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); + A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); + qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", + env->exception.fsr, + (uint32_t)env->exception.vaddress); + new_mode =3D ARM_CPU_MODE_ABT; + addr =3D 0x10; + mask =3D CPSR_A | CPSR_I; + offset =3D 8; + break; + case EXCP_IRQ: + new_mode =3D ARM_CPU_MODE_IRQ; + addr =3D 0x18; + /* Disable IRQ and imprecise data aborts. */ + mask =3D CPSR_A | CPSR_I; + offset =3D 4; + if (env->cp15.scr_el3 & SCR_IRQ) { + /* IRQ routed to monitor mode */ + new_mode =3D ARM_CPU_MODE_MON; + mask |=3D CPSR_F; + } + break; + case EXCP_FIQ: + new_mode =3D ARM_CPU_MODE_FIQ; + addr =3D 0x1c; + /* Disable FIQ, IRQ and imprecise data aborts. */ + mask =3D CPSR_A | CPSR_I | CPSR_F; + if (env->cp15.scr_el3 & SCR_FIQ) { + /* FIQ routed to monitor mode */ + new_mode =3D ARM_CPU_MODE_MON; + } + offset =3D 4; + break; + case EXCP_VIRQ: + new_mode =3D ARM_CPU_MODE_IRQ; + addr =3D 0x18; + /* Disable IRQ and imprecise data aborts. */ + mask =3D CPSR_A | CPSR_I; + offset =3D 4; + break; + case EXCP_VFIQ: + new_mode =3D ARM_CPU_MODE_FIQ; + addr =3D 0x1c; + /* Disable FIQ, IRQ and imprecise data aborts. */ + mask =3D CPSR_A | CPSR_I | CPSR_F; + offset =3D 4; + break; + case EXCP_SMC: + new_mode =3D ARM_CPU_MODE_MON; + addr =3D 0x08; + mask =3D CPSR_A | CPSR_I | CPSR_F; + offset =3D 0; + break; + default: + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); + return; /* Never happens. Keep compiler happy. */ + } + + if (new_mode =3D=3D ARM_CPU_MODE_MON) { + addr +=3D env->cp15.mvbar; + } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { + /* High vectors. When enabled, base address cannot be remapped. */ + addr +=3D 0xffff0000; + } else { + /* + * ARM v7 architectures provide a vector base address register to = remap + * the interrupt vector table. + * This register is only followed in non-monitor mode, and is bank= ed. + * Note: only bits 31:5 are valid. + */ + addr +=3D A32_BANKED_CURRENT_REG_GET(env, vbar); + } + + if ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_MON) { + env->cp15.scr_el3 &=3D ~SCR_NS; + } + + take_aarch32_exception(env, new_mode, mask, offset, addr); +} + +static int aarch64_regnum(CPUARMState *env, int aarch32_reg) +{ + /* + * Return the register number of the AArch64 view of the AArch32 + * register @aarch32_reg. The CPUARMState CPSR is assumed to still + * be that of the AArch32 mode the exception came from. + */ + int mode =3D env->uncached_cpsr & CPSR_M; + + switch (aarch32_reg) { + case 0 ... 7: + return aarch32_reg; + case 8 ... 12: + return mode =3D=3D ARM_CPU_MODE_FIQ ? aarch32_reg + 16 : aarch32_r= eg; + case 13: + switch (mode) { + case ARM_CPU_MODE_USR: + case ARM_CPU_MODE_SYS: + return 13; + case ARM_CPU_MODE_HYP: + return 15; + case ARM_CPU_MODE_IRQ: + return 17; + case ARM_CPU_MODE_SVC: + return 19; + case ARM_CPU_MODE_ABT: + return 21; + case ARM_CPU_MODE_UND: + return 23; + case ARM_CPU_MODE_FIQ: + return 29; + default: + g_assert_not_reached(); + } + case 14: + switch (mode) { + case ARM_CPU_MODE_USR: + case ARM_CPU_MODE_SYS: + case ARM_CPU_MODE_HYP: + return 14; + case ARM_CPU_MODE_IRQ: + return 16; + case ARM_CPU_MODE_SVC: + return 18; + case ARM_CPU_MODE_ABT: + return 20; + case ARM_CPU_MODE_UND: + return 22; + case ARM_CPU_MODE_FIQ: + return 30; + default: + g_assert_not_reached(); + } + case 15: + return 31; + default: + g_assert_not_reached(); + } +} + +static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env) +{ + uint32_t ret =3D cpsr_read(env); + + /* Move DIT to the correct location for SPSR_ELx */ + if (ret & CPSR_DIT) { + ret &=3D ~CPSR_DIT; + ret |=3D PSTATE_DIT; + } + /* Merge PSTATE.SS into SPSR_ELx */ + ret |=3D env->pstate & PSTATE_SS; + + return ret; +} + +/* Handle exception entry to a target EL which is using AArch64 */ +static void arm_cpu_do_interrupt_aarch64(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + unsigned int new_el =3D env->exception.target_el; + target_ulong addr =3D env->cp15.vbar_el[new_el]; + unsigned int new_mode =3D aarch64_pstate_mode(new_el, true); + unsigned int old_mode; + unsigned int cur_el =3D arm_current_el(env); + int rt; + + /* + * Note that new_el can never be 0. If cur_el is 0, then + * el0_a64 is is_a64(), else el0_a64 is ignored. + */ + aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); + + if (cur_el < new_el) { + /* + * Entry vector offset depends on whether the implemented EL + * immediately lower than the target level is using AArch32 or AAr= ch64 + */ + bool is_aa64; + uint64_t hcr; + + switch (new_el) { + case 3: + is_aa64 =3D (env->cp15.scr_el3 & SCR_RW) !=3D 0; + break; + case 2: + hcr =3D arm_hcr_el2_eff(env); + if ((hcr & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_TGE)) { + is_aa64 =3D (hcr & HCR_RW) !=3D 0; + break; + } + /* fall through */ + case 1: + is_aa64 =3D is_a64(env); + break; + default: + g_assert_not_reached(); + } + + if (is_aa64) { + addr +=3D 0x400; + } else { + addr +=3D 0x600; + } + } else if (pstate_read(env) & PSTATE_SP) { + addr +=3D 0x200; + } + + switch (cs->exception_index) { + case EXCP_PREFETCH_ABORT: + case EXCP_DATA_ABORT: + env->cp15.far_el[new_el] =3D env->exception.vaddress; + qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", + env->cp15.far_el[new_el]); + /* fall through */ + case EXCP_BKPT: + case EXCP_UDEF: + case EXCP_SWI: + case EXCP_HVC: + case EXCP_HYP_TRAP: + case EXCP_SMC: + switch (syn_get_ec(env->exception.syndrome)) { + case EC_ADVSIMDFPACCESSTRAP: + /* + * QEMU internal FP/SIMD syndromes from AArch32 include the + * TA and coproc fields which are only exposed if the exception + * is taken to AArch32 Hyp mode. Mask them out to get a valid + * AArch64 format syndrome. + */ + env->exception.syndrome &=3D ~MAKE_64BIT_MASK(0, 20); + break; + case EC_CP14RTTRAP: + case EC_CP15RTTRAP: + case EC_CP14DTTRAP: + /* + * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is curre= ntly + * the raw register field from the insn; when taking this to + * AArch64 we must convert it to the AArch64 view of the regis= ter + * number. Notice that we read a 4-bit AArch32 register number= and + * write back a 5-bit AArch64 one. + */ + rt =3D extract32(env->exception.syndrome, 5, 4); + rt =3D aarch64_regnum(env, rt); + env->exception.syndrome =3D deposit32(env->exception.syndrome, + 5, 5, rt); + break; + case EC_CP15RRTTRAP: + case EC_CP14RRTTRAP: + /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */ + rt =3D extract32(env->exception.syndrome, 5, 4); + rt =3D aarch64_regnum(env, rt); + env->exception.syndrome =3D deposit32(env->exception.syndrome, + 5, 5, rt); + rt =3D extract32(env->exception.syndrome, 10, 4); + rt =3D aarch64_regnum(env, rt); + env->exception.syndrome =3D deposit32(env->exception.syndrome, + 10, 5, rt); + break; + } + env->cp15.esr_el[new_el] =3D env->exception.syndrome; + break; + case EXCP_IRQ: + case EXCP_VIRQ: + addr +=3D 0x80; + break; + case EXCP_FIQ: + case EXCP_VFIQ: + addr +=3D 0x100; + break; + default: + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); + } + + if (is_a64(env)) { + old_mode =3D pstate_read(env); + aarch64_save_sp(env, arm_current_el(env)); + env->elr_el[new_el] =3D env->pc; + } else { + old_mode =3D cpsr_read_for_spsr_elx(env); + env->elr_el[new_el] =3D env->regs[15]; + + aarch64_sync_32_to_64(env); + + env->condexec_bits =3D 0; + } + env->banked_spsr[aarch64_banked_spsr_index(new_el)] =3D old_mode; + + qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", + env->elr_el[new_el]); + + if (cpu_isar_feature(aa64_pan, cpu)) { + /* The value of PSTATE.PAN is normally preserved, except when ... = */ + new_mode |=3D old_mode & PSTATE_PAN; + switch (new_el) { + case 2: + /* ... the target is EL2 with HCR_EL2.{E2H,TGE} =3D=3D '11' ..= . */ + if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) + !=3D (HCR_E2H | HCR_TGE)) { + break; + } + /* fall through */ + case 1: + /* ... the target is EL1 ... */ + /* ... and SCTLR_ELx.SPAN =3D=3D 0, then set to 1. */ + if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) =3D=3D 0) { + new_mode |=3D PSTATE_PAN; + } + break; + } + } + if (cpu_isar_feature(aa64_mte, cpu)) { + new_mode |=3D PSTATE_TCO; + } + + pstate_write(env, PSTATE_DAIF | new_mode); + env->aarch64 =3D 1; + aarch64_restore_sp(env, new_el); + + if (tcg_enabled()) { + /* pstate already written, so we can use arm_rebuild_hflags here */ + arm_rebuild_hflags(env); + } + + env->pc =3D addr; + + qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", + new_el, env->pc, pstate_read(env)); +} + +void arm_log_exception(int idx) +{ + if (qemu_loglevel_mask(CPU_LOG_INT)) { + const char *exc =3D NULL; + static const char * const excnames[] =3D { + [EXCP_UDEF] =3D "Undefined Instruction", + [EXCP_SWI] =3D "SVC", + [EXCP_PREFETCH_ABORT] =3D "Prefetch Abort", + [EXCP_DATA_ABORT] =3D "Data Abort", + [EXCP_IRQ] =3D "IRQ", + [EXCP_FIQ] =3D "FIQ", + [EXCP_BKPT] =3D "Breakpoint", + [EXCP_EXCEPTION_EXIT] =3D "QEMU v7M exception exit", + [EXCP_KERNEL_TRAP] =3D "QEMU intercept of kernel commpage", + [EXCP_HVC] =3D "Hypervisor Call", + [EXCP_HYP_TRAP] =3D "Hypervisor Trap", + [EXCP_SMC] =3D "Secure Monitor Call", + [EXCP_VIRQ] =3D "Virtual IRQ", + [EXCP_VFIQ] =3D "Virtual FIQ", + [EXCP_SEMIHOST] =3D "Semihosting call", + [EXCP_NOCP] =3D "v7M NOCP UsageFault", + [EXCP_INVSTATE] =3D "v7M INVSTATE UsageFault", + [EXCP_STKOF] =3D "v8M STKOF UsageFault", + [EXCP_LAZYFP] =3D "v7M exception during lazy FP stacking", + [EXCP_LSERR] =3D "v8M LSERR UsageFault", + [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", + }; + + if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { + exc =3D excnames[idx]; + } + if (!exc) { + exc =3D "unknown"; + } + qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); + } +} + +/* + * Handle a CPU exception for A and R profile CPUs. + * Do any appropriate logging, handle PSCI calls, and then hand off + * to the AArch64-entry or AArch32-entry function depending on the + * target exception level's register width. + * + * Note: this is used for both TCG (as the do_interrupt tcg op), + * and KVM to re-inject guest debug exceptions, and to + * inject a Synchronous-External-Abort. + */ +void arm_cpu_do_interrupt(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + unsigned int new_el =3D env->exception.target_el; + + assert(!arm_feature(env, ARM_FEATURE_M)); + + arm_log_exception(cs->exception_index); + qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(en= v), + new_el); + if (qemu_loglevel_mask(CPU_LOG_INT) + && !excp_is_internal(cs->exception_index)) { + qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", + syn_get_ec(env->exception.syndrome), + env->exception.syndrome); + } + +#ifdef CONFIG_TCG + if (arm_is_psci_call(cpu, cs->exception_index)) { + arm_handle_psci_call(cpu); + qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); + return; + } + /* + * Semihosting semantics depend on the register width of the code + * that caused the exception, not the target exception level, so + * must be handled here. + */ + if (cs->exception_index =3D=3D EXCP_SEMIHOST) { + handle_semihosting(cs); + return; + } +#endif /* CONFIG_TCG */ + /* + * Hooks may change global state so BQL should be held, also the + * BQL needs to be held for any modification of + * cs->interrupt_request. + */ + g_assert(qemu_mutex_iothread_locked()); + arm_call_pre_el_change_hook(cpu); + + assert(!excp_is_internal(cs->exception_index)); + if (arm_el_is_aa64(env, new_el)) { + arm_cpu_do_interrupt_aarch64(cs); + } else { + arm_cpu_do_interrupt_aarch32(cs); + } + + arm_call_el_change_hook(cpu); + + if (tcg_enabled()) { + cs->interrupt_request |=3D CPU_INTERRUPT_EXITTB; + } +} diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index 5b32329895..a8b1efdb36 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -7,34 +7,13 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/units.h" -#include "target/arm/idau.h" -#include "trace.h" #include "cpu.h" #include "internals.h" #include "exec/gdbstub.h" #include "exec/helper-proto.h" -#include "qemu/host-utils.h" -#include "qemu/main-loop.h" -#include "qemu/bitops.h" #include "qemu/crc32c.h" -#include "qemu/qemu-print.h" -#include "exec/exec-all.h" #include /* For crc32 */ -#include "hw/irq.h" -#include "semihosting/semihost.h" -#include "sysemu/cpus.h" -#include "sysemu/cpu-timers.h" -#include "sysemu/kvm.h" -#include "sysemu/tcg.h" -#include "qemu/range.h" -#include "qapi/error.h" -#include "qemu/guest-random.h" -#ifdef CONFIG_TCG #include "arm_ldst.h" -#include "exec/cpu_ldst.h" -#include "semihosting/common-semi.h" -#endif #include "cpu-mmu.h" #include "cpregs.h" =20 @@ -643,719 +622,6 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32= _t excp_idx, return target_el; } =20 -void arm_log_exception(int idx) -{ - if (qemu_loglevel_mask(CPU_LOG_INT)) { - const char *exc =3D NULL; - static const char * const excnames[] =3D { - [EXCP_UDEF] =3D "Undefined Instruction", - [EXCP_SWI] =3D "SVC", - [EXCP_PREFETCH_ABORT] =3D "Prefetch Abort", - [EXCP_DATA_ABORT] =3D "Data Abort", - [EXCP_IRQ] =3D "IRQ", - [EXCP_FIQ] =3D "FIQ", - [EXCP_BKPT] =3D "Breakpoint", - [EXCP_EXCEPTION_EXIT] =3D "QEMU v7M exception exit", - [EXCP_KERNEL_TRAP] =3D "QEMU intercept of kernel commpage", - [EXCP_HVC] =3D "Hypervisor Call", - [EXCP_HYP_TRAP] =3D "Hypervisor Trap", - [EXCP_SMC] =3D "Secure Monitor Call", - [EXCP_VIRQ] =3D "Virtual IRQ", - [EXCP_VFIQ] =3D "Virtual FIQ", - [EXCP_SEMIHOST] =3D "Semihosting call", - [EXCP_NOCP] =3D "v7M NOCP UsageFault", - [EXCP_INVSTATE] =3D "v7M INVSTATE UsageFault", - [EXCP_STKOF] =3D "v8M STKOF UsageFault", - [EXCP_LAZYFP] =3D "v7M exception during lazy FP stacking", - [EXCP_LSERR] =3D "v8M LSERR UsageFault", - [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", - }; - - if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { - exc =3D excnames[idx]; - } - if (!exc) { - exc =3D "unknown"; - } - qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); - } -} - -static void take_aarch32_exception(CPUARMState *env, int new_mode, - uint32_t mask, uint32_t offset, - uint32_t newpc) -{ - int new_el; - - /* Change the CPU state so as to actually take the exception. */ - switch_mode(env, new_mode); - - /* - * For exceptions taken to AArch32 we must clear the SS bit in both - * PSTATE and in the old-state value we save to SPSR_, so zero i= t now. - */ - env->pstate &=3D ~PSTATE_SS; - env->spsr =3D cpsr_read(env); - /* Clear IT bits. */ - env->condexec_bits =3D 0; - /* Switch to the new mode, and to the correct instruction set. */ - env->uncached_cpsr =3D (env->uncached_cpsr & ~CPSR_M) | new_mode; - - /* This must be after mode switching. */ - new_el =3D arm_current_el(env); - - /* Set new mode endianness */ - env->uncached_cpsr &=3D ~CPSR_E; - if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { - env->uncached_cpsr |=3D CPSR_E; - } - /* J and IL must always be cleared for exception entry */ - env->uncached_cpsr &=3D ~(CPSR_IL | CPSR_J); - env->daif |=3D mask; - - if (cpu_isar_feature(aa32_ssbs, env_archcpu(env))) { - if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_32) { - env->uncached_cpsr |=3D CPSR_SSBS; - } else { - env->uncached_cpsr &=3D ~CPSR_SSBS; - } - } - - if (new_mode =3D=3D ARM_CPU_MODE_HYP) { - env->thumb =3D (env->cp15.sctlr_el[2] & SCTLR_TE) !=3D 0; - env->elr_el[2] =3D env->regs[15]; - } else { - /* CPSR.PAN is normally preserved preserved unless... */ - if (cpu_isar_feature(aa32_pan, env_archcpu(env))) { - switch (new_el) { - case 3: - if (!arm_is_secure_below_el3(env)) { - /* ... the target is EL3, from non-secure state. */ - env->uncached_cpsr &=3D ~CPSR_PAN; - break; - } - /* ... the target is EL3, from secure state ... */ - /* fall through */ - case 1: - /* ... the target is EL1 and SCTLR.SPAN is 0. */ - if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { - env->uncached_cpsr |=3D CPSR_PAN; - } - break; - } - } - /* - * this is a lie, as there was no c1_sys on V4T/V5, but who cares - * and we should just guard the thumb mode on V4 - */ - if (arm_feature(env, ARM_FEATURE_V4T)) { - env->thumb =3D - (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) !=3D 0; - } - env->regs[14] =3D env->regs[15] + offset; - } - env->regs[15] =3D newpc; - if (tcg_enabled()) { - arm_rebuild_hflags(env); - } -} - -static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) -{ - /* - * Handle exception entry to Hyp mode; this is sufficiently - * different to entry to other AArch32 modes that we handle it - * separately here. - * - * The vector table entry used is always the 0x14 Hyp mode entry point, - * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp. - * The offset applied to the preferred return address is always zero - * (see DDI0487C.a section G1.12.3). - * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. - */ - uint32_t addr, mask; - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - switch (cs->exception_index) { - case EXCP_UDEF: - addr =3D 0x04; - break; - case EXCP_SWI: - addr =3D 0x14; - break; - case EXCP_BKPT: - /* Fall through to prefetch abort. */ - case EXCP_PREFETCH_ABORT: - env->cp15.ifar_s =3D env->exception.vaddress; - qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n", - (uint32_t)env->exception.vaddress); - addr =3D 0x0c; - break; - case EXCP_DATA_ABORT: - env->cp15.dfar_s =3D env->exception.vaddress; - qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n", - (uint32_t)env->exception.vaddress); - addr =3D 0x10; - break; - case EXCP_IRQ: - addr =3D 0x18; - break; - case EXCP_FIQ: - addr =3D 0x1c; - break; - case EXCP_HVC: - addr =3D 0x08; - break; - case EXCP_HYP_TRAP: - addr =3D 0x14; - break; - default: - cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); - } - - if (cs->exception_index !=3D EXCP_IRQ && cs->exception_index !=3D EXCP= _FIQ) { - if (!arm_feature(env, ARM_FEATURE_V8)) { - /* - * QEMU syndrome values are v8-style. v7 has the IL bit - * UNK/SBZP for "field not valid" cases, where v8 uses RES1. - * If this is a v7 CPU, squash the IL bit in those cases. - */ - if (cs->exception_index =3D=3D EXCP_PREFETCH_ABORT || - (cs->exception_index =3D=3D EXCP_DATA_ABORT && - !(env->exception.syndrome & ARM_EL_ISV)) || - syn_get_ec(env->exception.syndrome) =3D=3D EC_UNCATEGORIZE= D) { - env->exception.syndrome &=3D ~ARM_EL_IL; - } - } - env->cp15.esr_el[2] =3D env->exception.syndrome; - } - - if (arm_current_el(env) !=3D 2 && addr < 0x14) { - addr =3D 0x14; - } - - mask =3D 0; - if (!(env->cp15.scr_el3 & SCR_EA)) { - mask |=3D CPSR_A; - } - if (!(env->cp15.scr_el3 & SCR_IRQ)) { - mask |=3D CPSR_I; - } - if (!(env->cp15.scr_el3 & SCR_FIQ)) { - mask |=3D CPSR_F; - } - - addr +=3D env->cp15.hvbar; - - take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr); -} - -static void arm_cpu_do_interrupt_aarch32(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - uint32_t addr; - uint32_t mask; - int new_mode; - uint32_t offset; - uint32_t moe; - - /* If this is a debug exception we must update the DBGDSCR.MOE bits */ - switch (syn_get_ec(env->exception.syndrome)) { - case EC_BREAKPOINT: - case EC_BREAKPOINT_SAME_EL: - moe =3D 1; - break; - case EC_WATCHPOINT: - case EC_WATCHPOINT_SAME_EL: - moe =3D 10; - break; - case EC_AA32_BKPT: - moe =3D 3; - break; - case EC_VECTORCATCH: - moe =3D 5; - break; - default: - moe =3D 0; - break; - } - - if (moe) { - env->cp15.mdscr_el1 =3D deposit64(env->cp15.mdscr_el1, 2, 4, moe); - } - - if (env->exception.target_el =3D=3D 2) { - arm_cpu_do_interrupt_aarch32_hyp(cs); - return; - } - - switch (cs->exception_index) { - case EXCP_UDEF: - new_mode =3D ARM_CPU_MODE_UND; - addr =3D 0x04; - mask =3D CPSR_I; - if (env->thumb) { - offset =3D 2; - } else { - offset =3D 4; - } - break; - case EXCP_SWI: - new_mode =3D ARM_CPU_MODE_SVC; - addr =3D 0x08; - mask =3D CPSR_I; - /* The PC already points to the next instruction. */ - offset =3D 0; - break; - case EXCP_BKPT: - /* Fall through to prefetch abort. */ - case EXCP_PREFETCH_ABORT: - A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); - A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); - qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", - env->exception.fsr, (uint32_t)env->exception.vaddres= s); - new_mode =3D ARM_CPU_MODE_ABT; - addr =3D 0x0c; - mask =3D CPSR_A | CPSR_I; - offset =3D 4; - break; - case EXCP_DATA_ABORT: - A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); - A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); - qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", - env->exception.fsr, - (uint32_t)env->exception.vaddress); - new_mode =3D ARM_CPU_MODE_ABT; - addr =3D 0x10; - mask =3D CPSR_A | CPSR_I; - offset =3D 8; - break; - case EXCP_IRQ: - new_mode =3D ARM_CPU_MODE_IRQ; - addr =3D 0x18; - /* Disable IRQ and imprecise data aborts. */ - mask =3D CPSR_A | CPSR_I; - offset =3D 4; - if (env->cp15.scr_el3 & SCR_IRQ) { - /* IRQ routed to monitor mode */ - new_mode =3D ARM_CPU_MODE_MON; - mask |=3D CPSR_F; - } - break; - case EXCP_FIQ: - new_mode =3D ARM_CPU_MODE_FIQ; - addr =3D 0x1c; - /* Disable FIQ, IRQ and imprecise data aborts. */ - mask =3D CPSR_A | CPSR_I | CPSR_F; - if (env->cp15.scr_el3 & SCR_FIQ) { - /* FIQ routed to monitor mode */ - new_mode =3D ARM_CPU_MODE_MON; - } - offset =3D 4; - break; - case EXCP_VIRQ: - new_mode =3D ARM_CPU_MODE_IRQ; - addr =3D 0x18; - /* Disable IRQ and imprecise data aborts. */ - mask =3D CPSR_A | CPSR_I; - offset =3D 4; - break; - case EXCP_VFIQ: - new_mode =3D ARM_CPU_MODE_FIQ; - addr =3D 0x1c; - /* Disable FIQ, IRQ and imprecise data aborts. */ - mask =3D CPSR_A | CPSR_I | CPSR_F; - offset =3D 4; - break; - case EXCP_SMC: - new_mode =3D ARM_CPU_MODE_MON; - addr =3D 0x08; - mask =3D CPSR_A | CPSR_I | CPSR_F; - offset =3D 0; - break; - default: - cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); - return; /* Never happens. Keep compiler happy. */ - } - - if (new_mode =3D=3D ARM_CPU_MODE_MON) { - addr +=3D env->cp15.mvbar; - } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { - /* High vectors. When enabled, base address cannot be remapped. */ - addr +=3D 0xffff0000; - } else { - /* - * ARM v7 architectures provide a vector base address register to = remap - * the interrupt vector table. - * This register is only followed in non-monitor mode, and is bank= ed. - * Note: only bits 31:5 are valid. - */ - addr +=3D A32_BANKED_CURRENT_REG_GET(env, vbar); - } - - if ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_MON) { - env->cp15.scr_el3 &=3D ~SCR_NS; - } - - take_aarch32_exception(env, new_mode, mask, offset, addr); -} - -static int aarch64_regnum(CPUARMState *env, int aarch32_reg) -{ - /* - * Return the register number of the AArch64 view of the AArch32 - * register @aarch32_reg. The CPUARMState CPSR is assumed to still - * be that of the AArch32 mode the exception came from. - */ - int mode =3D env->uncached_cpsr & CPSR_M; - - switch (aarch32_reg) { - case 0 ... 7: - return aarch32_reg; - case 8 ... 12: - return mode =3D=3D ARM_CPU_MODE_FIQ ? aarch32_reg + 16 : aarch32_r= eg; - case 13: - switch (mode) { - case ARM_CPU_MODE_USR: - case ARM_CPU_MODE_SYS: - return 13; - case ARM_CPU_MODE_HYP: - return 15; - case ARM_CPU_MODE_IRQ: - return 17; - case ARM_CPU_MODE_SVC: - return 19; - case ARM_CPU_MODE_ABT: - return 21; - case ARM_CPU_MODE_UND: - return 23; - case ARM_CPU_MODE_FIQ: - return 29; - default: - g_assert_not_reached(); - } - case 14: - switch (mode) { - case ARM_CPU_MODE_USR: - case ARM_CPU_MODE_SYS: - case ARM_CPU_MODE_HYP: - return 14; - case ARM_CPU_MODE_IRQ: - return 16; - case ARM_CPU_MODE_SVC: - return 18; - case ARM_CPU_MODE_ABT: - return 20; - case ARM_CPU_MODE_UND: - return 22; - case ARM_CPU_MODE_FIQ: - return 30; - default: - g_assert_not_reached(); - } - case 15: - return 31; - default: - g_assert_not_reached(); - } -} - -static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env) -{ - uint32_t ret =3D cpsr_read(env); - - /* Move DIT to the correct location for SPSR_ELx */ - if (ret & CPSR_DIT) { - ret &=3D ~CPSR_DIT; - ret |=3D PSTATE_DIT; - } - /* Merge PSTATE.SS into SPSR_ELx */ - ret |=3D env->pstate & PSTATE_SS; - - return ret; -} - -/* Handle exception entry to a target EL which is using AArch64 */ -static void arm_cpu_do_interrupt_aarch64(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - unsigned int new_el =3D env->exception.target_el; - target_ulong addr =3D env->cp15.vbar_el[new_el]; - unsigned int new_mode =3D aarch64_pstate_mode(new_el, true); - unsigned int old_mode; - unsigned int cur_el =3D arm_current_el(env); - int rt; - - /* - * Note that new_el can never be 0. If cur_el is 0, then - * el0_a64 is is_a64(), else el0_a64 is ignored. - */ - aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); - - if (cur_el < new_el) { - /* - * Entry vector offset depends on whether the implemented EL - * immediately lower than the target level is using AArch32 or AAr= ch64 - */ - bool is_aa64; - uint64_t hcr; - - switch (new_el) { - case 3: - is_aa64 =3D (env->cp15.scr_el3 & SCR_RW) !=3D 0; - break; - case 2: - hcr =3D arm_hcr_el2_eff(env); - if ((hcr & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_TGE)) { - is_aa64 =3D (hcr & HCR_RW) !=3D 0; - break; - } - /* fall through */ - case 1: - is_aa64 =3D is_a64(env); - break; - default: - g_assert_not_reached(); - } - - if (is_aa64) { - addr +=3D 0x400; - } else { - addr +=3D 0x600; - } - } else if (pstate_read(env) & PSTATE_SP) { - addr +=3D 0x200; - } - - switch (cs->exception_index) { - case EXCP_PREFETCH_ABORT: - case EXCP_DATA_ABORT: - env->cp15.far_el[new_el] =3D env->exception.vaddress; - qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", - env->cp15.far_el[new_el]); - /* fall through */ - case EXCP_BKPT: - case EXCP_UDEF: - case EXCP_SWI: - case EXCP_HVC: - case EXCP_HYP_TRAP: - case EXCP_SMC: - switch (syn_get_ec(env->exception.syndrome)) { - case EC_ADVSIMDFPACCESSTRAP: - /* - * QEMU internal FP/SIMD syndromes from AArch32 include the - * TA and coproc fields which are only exposed if the exception - * is taken to AArch32 Hyp mode. Mask them out to get a valid - * AArch64 format syndrome. - */ - env->exception.syndrome &=3D ~MAKE_64BIT_MASK(0, 20); - break; - case EC_CP14RTTRAP: - case EC_CP15RTTRAP: - case EC_CP14DTTRAP: - /* - * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is curre= ntly - * the raw register field from the insn; when taking this to - * AArch64 we must convert it to the AArch64 view of the regis= ter - * number. Notice that we read a 4-bit AArch32 register number= and - * write back a 5-bit AArch64 one. - */ - rt =3D extract32(env->exception.syndrome, 5, 4); - rt =3D aarch64_regnum(env, rt); - env->exception.syndrome =3D deposit32(env->exception.syndrome, - 5, 5, rt); - break; - case EC_CP15RRTTRAP: - case EC_CP14RRTTRAP: - /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */ - rt =3D extract32(env->exception.syndrome, 5, 4); - rt =3D aarch64_regnum(env, rt); - env->exception.syndrome =3D deposit32(env->exception.syndrome, - 5, 5, rt); - rt =3D extract32(env->exception.syndrome, 10, 4); - rt =3D aarch64_regnum(env, rt); - env->exception.syndrome =3D deposit32(env->exception.syndrome, - 10, 5, rt); - break; - } - env->cp15.esr_el[new_el] =3D env->exception.syndrome; - break; - case EXCP_IRQ: - case EXCP_VIRQ: - addr +=3D 0x80; - break; - case EXCP_FIQ: - case EXCP_VFIQ: - addr +=3D 0x100; - break; - default: - cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); - } - - if (is_a64(env)) { - old_mode =3D pstate_read(env); - aarch64_save_sp(env, arm_current_el(env)); - env->elr_el[new_el] =3D env->pc; - } else { - old_mode =3D cpsr_read_for_spsr_elx(env); - env->elr_el[new_el] =3D env->regs[15]; - - aarch64_sync_32_to_64(env); - - env->condexec_bits =3D 0; - } - env->banked_spsr[aarch64_banked_spsr_index(new_el)] =3D old_mode; - - qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", - env->elr_el[new_el]); - - if (cpu_isar_feature(aa64_pan, cpu)) { - /* The value of PSTATE.PAN is normally preserved, except when ... = */ - new_mode |=3D old_mode & PSTATE_PAN; - switch (new_el) { - case 2: - /* ... the target is EL2 with HCR_EL2.{E2H,TGE} =3D=3D '11' ..= . */ - if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) - !=3D (HCR_E2H | HCR_TGE)) { - break; - } - /* fall through */ - case 1: - /* ... the target is EL1 ... */ - /* ... and SCTLR_ELx.SPAN =3D=3D 0, then set to 1. */ - if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) =3D=3D 0) { - new_mode |=3D PSTATE_PAN; - } - break; - } - } - if (cpu_isar_feature(aa64_mte, cpu)) { - new_mode |=3D PSTATE_TCO; - } - - if (cpu_isar_feature(aa64_ssbs, cpu)) { - if (env->cp15.sctlr_el[new_el] & SCTLR_DSSBS_64) { - new_mode |=3D PSTATE_SSBS; - } else { - new_mode &=3D ~PSTATE_SSBS; - } - } - - pstate_write(env, PSTATE_DAIF | new_mode); - env->aarch64 =3D 1; - aarch64_restore_sp(env, new_el); - - if (tcg_enabled()) { - /* pstate already written, so we can use arm_rebuild_hflags here */ - arm_rebuild_hflags(env); - } - - env->pc =3D addr; - - qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", - new_el, env->pc, pstate_read(env)); -} - -/* - * Do semihosting call and set the appropriate return value. All the - * permission and validity checks have been done at translate time. - * - * We only see semihosting exceptions in TCG only as they are not - * trapped to the hypervisor in KVM. - */ -#ifdef CONFIG_TCG -static void handle_semihosting(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - if (is_a64(env)) { - qemu_log_mask(CPU_LOG_INT, - "...handling as semihosting call 0x%" PRIx64 "\n", - env->xregs[0]); - env->xregs[0] =3D do_common_semihosting(cs); - env->pc +=3D 4; - } else { - qemu_log_mask(CPU_LOG_INT, - "...handling as semihosting call 0x%x\n", - env->regs[0]); - env->regs[0] =3D do_common_semihosting(cs); - env->regs[15] +=3D env->thumb ? 2 : 4; - } -} -#endif - -/* - * Handle a CPU exception for A and R profile CPUs. - * Do any appropriate logging, handle PSCI calls, and then hand off - * to the AArch64-entry or AArch32-entry function depending on the - * target exception level's register width. - * - * Note: this is used for both TCG (as the do_interrupt tcg op), - * and KVM to re-inject guest debug exceptions, and to - * inject a Synchronous-External-Abort. - */ -void arm_cpu_do_interrupt(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - unsigned int new_el =3D env->exception.target_el; - - assert(!arm_feature(env, ARM_FEATURE_M)); - - arm_log_exception(cs->exception_index); - qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(en= v), - new_el); - if (qemu_loglevel_mask(CPU_LOG_INT) - && !excp_is_internal(cs->exception_index)) { - qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", - syn_get_ec(env->exception.syndrome), - env->exception.syndrome); - } - -#ifdef CONFIG_TCG - if (arm_is_psci_call(cpu, cs->exception_index)) { - arm_handle_psci_call(cpu); - qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); - return; - } - - /* - * Semihosting semantics depend on the register width of the code - * that caused the exception, not the target exception level, so - * must be handled here. - */ - if (cs->exception_index =3D=3D EXCP_SEMIHOST) { - handle_semihosting(cs); - return; - } -#endif - - /* - * Hooks may change global state so BQL should be held, also the - * BQL needs to be held for any modification of - * cs->interrupt_request. - */ - g_assert(qemu_mutex_iothread_locked()); - - arm_call_pre_el_change_hook(cpu); - - assert(!excp_is_internal(cs->exception_index)); - if (arm_el_is_aa64(env, new_el)) { - arm_cpu_do_interrupt_aarch64(cs); - } else { - arm_cpu_do_interrupt_aarch32(cs); - } - - arm_call_el_change_hook(cpu); - - if (!kvm_enabled()) { - cs->interrupt_request |=3D CPU_INTERRUPT_EXITTB; - } -} #endif /* !CONFIG_USER_ONLY */ =20 /* Returns true if the stage 1 translation regime is using LPAE format page diff --git a/target/arm/tcg/sysemu/tcg-cpu.c b/target/arm/tcg/sysemu/tcg-cp= u.c new file mode 100644 index 0000000000..af9d3905d7 --- /dev/null +++ b/target/arm/tcg/sysemu/tcg-cpu.c @@ -0,0 +1,73 @@ +/* + * QEMU ARM TCG CPU (sysemu code) + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "qemu/osdep.h" +#include "qemu/qemu-print.h" +#include "qemu-common.h" +#include "target/arm/idau.h" +#include "qemu/module.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "cpu.h" +#include "hw/core/tcg-cpu-ops.h" +#include "semihosting/common-semi.h" +#include "cpregs.h" +#include "internals.h" +#include "exec/exec-all.h" +#include "hw/qdev-properties.h" +#if !defined(CONFIG_USER_ONLY) +#include "hw/loader.h" +#include "hw/boards.h" +#endif +#include "sysemu/sysemu.h" +#include "sysemu/tcg.h" +#include "sysemu/hw_accel.h" +#include "kvm_arm.h" +#include "disas/capstone.h" +#include "fpu/softfloat.h" +#include "cpu-mmu.h" +#include "tcg/tcg-cpu.h" + +/* + * Do semihosting call and set the appropriate return value. All the + * permission and validity checks have been done at translate time. + * + * We only see semihosting exceptions in TCG only as they are not + * trapped to the hypervisor in KVM. + */ +void handle_semihosting(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + if (is_a64(env)) { + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%" PRIx64 "\n", + env->xregs[0]); + env->xregs[0] =3D do_common_semihosting(cs); + env->pc +=3D 4; + } else { + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%x\n", + env->regs[0]); + env->regs[0] =3D do_common_semihosting(cs); + env->regs[15] +=3D env->thumb ? 2 : 4; + } +} diff --git a/target/arm/tcg/sysemu/meson.build b/target/arm/tcg/sysemu/meso= n.build index 26014851bd..56e4b5ccea 100644 --- a/target/arm/tcg/sysemu/meson.build +++ b/target/arm/tcg/sysemu/meson.build @@ -2,5 +2,6 @@ arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( 'debug_helper.c', 'm_helper.c', 'mte_helper.c', + 'tcg-cpu.c', 'tlb_helper.c', )) --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622824542; cv=none; d=zohomail.com; s=zohoarc; b=lU7KZx9gxYFxpw8gcNcPITXWOm/rt3S2773ijHPk0BxBX3T7hxC9WEYQAcUYl0G+Ds+i9Lz1XKnNzIldlCnUUMIrSkhUvIWKosdpFJ86qKZYGBn2HDC9XJxx+80N285UGKENorgf7jRTLTqWZIPEUQWz5I6H79gvPNW1Bl3ckE4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622824542; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LGeDOwWwESs2gGWztkDCsxwH9lAbDgWWcLiqhQ1nuks=; b=k5jrX3PlNl/Kk7AyNtjI0mycVYrOiR9hqAjFchEjVOXxCWJ2hqYicFVfFrfSXOkM+uKxUZkUOy7dKaAz51v6ufU3zbT7WRCpAgKi6NZLieOoGN1/W1u7fw6sa6BaDpQpFb7Tk4uI5BuDtJwh7SVt+tuZOuiUFQDv4qQThDHVxeg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622824542157565.9532093105366; Fri, 4 Jun 2021 09:35:42 -0700 (PDT) Received: from localhost ([::1]:39314 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCnN-0005B1-Fl for importer@patchew.org; Fri, 04 Jun 2021 12:35:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48668) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCI8-0008U9-P6 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:25 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:45917) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHf-0005rw-OP for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:24 -0400 Received: by mail-wr1-x433.google.com with SMTP id z8so9801943wrp.12 for ; Fri, 04 Jun 2021 09:02:55 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id e27sm7421445wra.50.2021.06.04.09.02.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:53 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 322761FFCB; Fri, 4 Jun 2021 16:53:19 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LGeDOwWwESs2gGWztkDCsxwH9lAbDgWWcLiqhQ1nuks=; b=hVeY+N7UJ5et154mehRHnRJzJGgbp6XaKvWItU7A/3rgLqBR3rBdNSkWExUdU0ZEUZ wFG5aqQoqI2mfSyuLKvsYw/67HV50BVqWEWpVBraEdpQ2iX2ehB4L0BSDjSCNfilmmW8 TCjPvmM8KxWP98yUHOANBY9t34wnQvNfUJ8TutmTd4OxQnv0M7+fmbqG2MfXxrEJSB5X YX7//QICp46LtXEIdXRrXotqnuA9wlf6QWFhG6Gdb1mS0Mf9Jo+F+T3q5JeCVn4YJ3wq /WbBZDi1pn8voRQ5Hr6lrs0b4Lqma0yehoLpxgb1Gxr3pvmYihGORlppyYvHU4rCdzaK nFCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LGeDOwWwESs2gGWztkDCsxwH9lAbDgWWcLiqhQ1nuks=; b=KOBk9kc2ze0KKt0Pa2Ba6g7rIn0L5SoI45MPSGLfiBefrRRqk0gE1fmWEbk6/cKl2e VUW6gItYhbG/InuxgVcaSTlqL9WTlxd+zCh9A/ejffVmiNSRiKNq5CTj7Sgc3gNveVL6 2OrcmSWWr6ZY+R9jSr3LtQIF8QzEdsD51RuhYXpFUbT5+T95n641QiU9KHZd/kahXkm5 Aln90ANsgkGCG/52TwjAqQHE3FMtolicU8ju+6y6gr5LGhgW8RvTJIGvH+TGOfyMR6EY MfZVMuzV+/EhqFkIf9mxq9wFp0rdl2EPezt+CSJkK+1MaYJ/DwvjqhfbXLW84OZ9CXbs xrZA== X-Gm-Message-State: AOAM532+IJu9yoWqaofKgrOfTR3EKREMbAZ9DqE1uWj9UJ5YLJJXAPMg Hsrq6Wjwl/gi1Y8nnbFPgDcSjQ== X-Google-Smtp-Source: ABdhPJwcNbZVK++BkKK9TWzZm4+G96dB4jZAXsgR9Aj2f3SvGT5ZSP9XpD3p37EDsInv423HVIk9ZQ== X-Received: by 2002:adf:e109:: with SMTP id t9mr4610797wrz.372.1622822574450; Fri, 04 Jun 2021 09:02:54 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 52/99] target/arm: rename handle_semihosting to tcg_handle_semihosting Date: Fri, 4 Jun 2021 16:52:25 +0100 Message-Id: <20210604155312.15902-53-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana make it clearer from the name that this is a tcg-only function. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/tcg-cpu.h | 2 +- target/arm/cpu-sysemu.c | 2 +- target/arm/tcg/sysemu/tcg-cpu.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/tcg-cpu.h b/target/arm/tcg/tcg-cpu.h index 0ee8ba073b..7e62f92d16 100644 --- a/target/arm/tcg/tcg-cpu.h +++ b/target/arm/tcg/tcg-cpu.h @@ -24,7 +24,7 @@ =20 #ifndef CONFIG_USER_ONLY /* Do semihosting call and set the appropriate return value. */ -void handle_semihosting(CPUState *cs); +void tcg_handle_semihosting(CPUState *cs); =20 #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c index 0e872b2e55..7569241339 100644 --- a/target/arm/cpu-sysemu.c +++ b/target/arm/cpu-sysemu.c @@ -1153,7 +1153,7 @@ void arm_cpu_do_interrupt(CPUState *cs) * must be handled here. */ if (cs->exception_index =3D=3D EXCP_SEMIHOST) { - handle_semihosting(cs); + tcg_handle_semihosting(cs); return; } #endif /* CONFIG_TCG */ diff --git a/target/arm/tcg/sysemu/tcg-cpu.c b/target/arm/tcg/sysemu/tcg-cp= u.c index af9d3905d7..2c395f47e7 100644 --- a/target/arm/tcg/sysemu/tcg-cpu.c +++ b/target/arm/tcg/sysemu/tcg-cpu.c @@ -52,7 +52,7 @@ * We only see semihosting exceptions in TCG only as they are not * trapped to the hypervisor in KVM. */ -void handle_semihosting(CPUState *cs) +void tcg_handle_semihosting(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622826416; cv=none; d=zohomail.com; s=zohoarc; b=MiXpXPfHLrPiPy0rl0zPFNa1EXRaQBR/RLPqCAHMgJP+okYFMFt6aCKypvooYQ8FWfLx+YbwM/mVbP8nZh2o3XfGUSFLCIOcleoLzvbLrx5/GAYC4KiyhqUkelEQanmH2TH4Oas318DBTh4Kg1Kq7oBBw6SQxZrAWefZsYjjCQc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622826416; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wznjsiz23B2i+j4Jb69yS0BiQR4HsYX/WkLwF6wNHTg=; b=T9Oqx5Pi0jJCpHRQifGlJOACWC5/kjP/2/eSaJY6DfgMykW3QAZ10eIzQybvQB0EZdEZ5lHt9BGdgUnF3m4KDvNCZHdiSqaBJVZD3MKMD9YI6ZsHUvsoqviGPqv66Qsho9GGx5Ymsn/r6rmQ38F/Z1Yo8ueBeXmk0aO+HYLryg4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622826416839892.4943250126278; Fri, 4 Jun 2021 10:06:56 -0700 (PDT) Received: from localhost ([::1]:59018 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDHb-0000rJ-9X for importer@patchew.org; Fri, 04 Jun 2021 13:06:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33232) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCkU-0007tH-Aj for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:32:42 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:39910) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCkS-00025T-DP for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:32:42 -0400 Received: by mail-wr1-x433.google.com with SMTP id l2so9930108wrw.6 for ; Fri, 04 Jun 2021 09:32:39 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id a77sm7630225wmd.14.2021.06.04.09.32.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:37 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 4A9B41FFCC; Fri, 4 Jun 2021 16:53:19 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wznjsiz23B2i+j4Jb69yS0BiQR4HsYX/WkLwF6wNHTg=; b=X/drSWWOPGk5OgiTbAmO0AX/ImlgJgeiLiTuEI3GrTYxtsWCa/KhrhFcfqHuaGiULC FnJonLSWN+vIAfDYQV1TO71GTAvpagvy2GVS2n+KSw8xqZ/JmCFsvvsm9K4NqRImxeGq ZVKtjfMiYVSXdplnNicjULyqQHKCEjPrAmbpV6IfYEtvb8783qy/MUUO/WAjlm1TxXw9 UbYL9zrI/fBeQs/VFQwuRrma9csH6q+tlCxl6d1jqHrwHpgDEIYJkI+PodB7xkPEl/6L upnvd1cJl64bdrqS+LEQ4ZS35SzlQs8ox7sI8BI/eldQOgXS2Kj0OKE+sVNfBdmwLx8t 5cUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wznjsiz23B2i+j4Jb69yS0BiQR4HsYX/WkLwF6wNHTg=; b=KinOLTZwtxBEojrEzHSsACTSYRfTx1nK2B4APWfUXkB/ApcWl0sX+OFhqnm3/IhFCZ GmfDbq5cA3mtyecDWBLBYNVuoJjMfLAkvbMiAbpnrttVr+9L9Jtv0fzFT86DVUy09i08 Ef+IRXmHrjrI69r4Ep2PY9CWGo3+yp3M1ugRdrD74TPNhclMWYkenhTeWnLhUUZkBCxp fGGXTrs60ZZ2hzwZ/FPWytxriIfSpLmDUKs8Uqwc2enAE3zcnnlpsmPvMjmBEBUVfwA1 Mq4hxuhTkfEslV6ZsDfzQgzt/IAKUyh227NxKyNctUJC28qRvMiqMmlRqmzs/e0Ovn/c jyUQ== X-Gm-Message-State: AOAM533jja/QIXnM2lfPgUj9RqY7i3vyDRBE92D4/R54WDsaFQA3cgI9 qGviOayNMhlioYrdW/4y13cLsQ== X-Google-Smtp-Source: ABdhPJyf4YrHSwNuI6nmyErgckfo7XyTL62AryAaML8Yp0U9dt439tUai+DM77ySCNBksXzkBMy7EA== X-Received: by 2002:adf:df86:: with SMTP id z6mr4798136wrl.255.1622824359086; Fri, 04 Jun 2021 09:32:39 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 53/99] target/arm: replace CONFIG_TCG with tcg_enabled Date: Fri, 4 Jun 2021 16:52:26 +0100 Message-Id: <20210604155312.15902-54-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana for "all" builds (tcg + kvm), we want to avoid doing the psci and semihosting checks if tcg is built-in, but not enabled. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-sysemu.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c index 7569241339..e83d55b9f7 100644 --- a/target/arm/cpu-sysemu.c +++ b/target/arm/cpu-sysemu.c @@ -1141,22 +1141,22 @@ void arm_cpu_do_interrupt(CPUState *cs) env->exception.syndrome); } =20 -#ifdef CONFIG_TCG - if (arm_is_psci_call(cpu, cs->exception_index)) { - arm_handle_psci_call(cpu); - qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); - return; - } - /* - * Semihosting semantics depend on the register width of the code - * that caused the exception, not the target exception level, so - * must be handled here. - */ - if (cs->exception_index =3D=3D EXCP_SEMIHOST) { - tcg_handle_semihosting(cs); - return; + if (tcg_enabled()) { + if (arm_is_psci_call(cpu, cs->exception_index)) { + arm_handle_psci_call(cpu); + qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); + return; + } + /* + * Semihosting semantics depend on the register width of the code + * that caused the exception, not the target exception level, so + * must be handled here. + */ + if (cs->exception_index =3D=3D EXCP_SEMIHOST) { + tcg_handle_semihosting(cs); + return; + } } -#endif /* CONFIG_TCG */ /* * Hooks may change global state so BQL should be held, also the * BQL needs to be held for any modification of --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622828262; cv=none; d=zohomail.com; s=zohoarc; b=JG9kup4biCogQ9+Si058ZKeUviwqMRNSdlbfd0Pe4zsk6kVi2LpgWOeoNCPrtuhHJuGmZRAY7VSFW2E2sTD3rd0mJj7Y2E3I6rLgExhPX++QpBA0n2Jlc+nZPrqYPhfYxMQWEMKWbusYsjMaRJFd0JjHqSihzzgdeFy/lUlg9u8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622828262; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lmCIQoI/Hkin0XFZ5JHEI3PAYwX9z71nEbOHIAi16Pg=; b=RxrUhTDeE0v9Ld6uRoJ/KGwgL/0F6qGwJeGhvusiteSQvOxUVvm3FLrquQaQ5sMh/0A5WMEne+k23+KvcdinipLtvwr7QfgYGF3iq6yzxYZKt+I1F12A0EXcW5FT4hYrHFtzGMYBMpNpCytV1sGbHsbqiqymCYujFbrnDEQC6cE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622828262260303.7975458848251; Fri, 4 Jun 2021 10:37:42 -0700 (PDT) Received: from localhost ([::1]:50596 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDlN-0006OE-1L for importer@patchew.org; Fri, 04 Jun 2021 13:37:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48892) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpDNQ-0000B2-TO for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:56 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:42557) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpDNN-00026i-Kb for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:56 -0400 Received: by mail-wm1-x331.google.com with SMTP id o2-20020a05600c4fc2b029019a0a8f959dso6023646wmq.1 for ; Fri, 04 Jun 2021 10:12:53 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id q5sm6172567wmc.0.2021.06.04.10.12.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 10:12:46 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 744F01FFCD; Fri, 4 Jun 2021 16:53:19 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lmCIQoI/Hkin0XFZ5JHEI3PAYwX9z71nEbOHIAi16Pg=; b=x0K7/fo1kZ7VOCuu1I82VF1/QpE4oHyI4nH9FqDjSzQ2GkZFh60QFERWEgRoOdlMae 6LMirwwZU3Lxy5dx/WTMCyM+JK2pvfrfxoHBS8g9uVQcJAZumEN6aO6D41H5gR4UcL9I tf2HSnF68SqBsFzjIVpUNcop0yfDwmGbhbtwsEhCjQxadyCdkexV71AGVEtWY1HSRuZE SMd5wrNVtuWWV+GMZXWBVl2mRtX2nzeJ8UeGisYVufhIr/dblrgrWKdiq91qG3nlQm1z 3pVj80KEU9jGDOIqnzRVO36UeHJBn1z8JPAUSWspXkUa8sIVd2wV3uMlKrF/CehmaZCK 4gAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lmCIQoI/Hkin0XFZ5JHEI3PAYwX9z71nEbOHIAi16Pg=; b=tNNKR2qpXGdutqnmawQcBpU5xYF1BsR+StLCPC9/WvRU1b2ADUqUreNUbil175ZXua HweONR1WA8MGU2yHTB5Bd8b5mbV5KOrI0mwZ44i8gOXxkgYYuU5EtMoqNrTKRlkCmVMY SHij2fp6LyFuIxOw+cCE+Md70tzW5TufhDY0JRgDrVoU4Fy+rDpkfcAZU/R5IeqVkqzr RDbPYb1seNbOF9wH64jTnJAelL/SgYuyI9DBSbD1AJJKxDqxMaZwm3N//cmwKykpquUm ILEUeehvsZrLn3DfaM+Lckf49k9MiD40gXMwnodZvI79cjXWIBJIhQTmfabQIOn/mAkP 5fMw== X-Gm-Message-State: AOAM530rTYBZ0/i0IKbV4hFLlxjqNAomMJZyrgApcuGKXgRBDWCMM3jM IL9FicT6KO4HPruyiMycROUu/Q== X-Google-Smtp-Source: ABdhPJwXRLhcPNk6Y74xC5dyifuh2K3qI3mt+tvs1fj5B9oNesKLYnoC18U63Pp8Q5V7Q93lpOsY1A== X-Received: by 2002:a05:600c:4f48:: with SMTP id m8mr4621691wmq.169.1622826772025; Fri, 04 Jun 2021 10:12:52 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 54/99] target/arm: move TCGCPUOps to tcg/tcg-cpu.c Date: Fri, 4 Jun 2021 16:52:27 +0100 Message-Id: <20210604155312.15902-55-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana move the TCGCPUOps interface to tcg/tcg-cpu.c in preparation for the addition of the TCG accel-cpu class. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 1 - target/arm/internals.h | 5 - target/arm/tcg/tcg-cpu.h | 6 + target/arm/cpu-sysemu.c | 4 + target/arm/cpu.c | 210 +--------------------------------- target/arm/cpu_tcg.c | 2 +- target/arm/tcg/helper.c | 1 + target/arm/tcg/tcg-cpu.c | 229 +++++++++++++++++++++++++++++++++++++ target/arm/tcg/meson.build | 1 + 9 files changed, 244 insertions(+), 215 deletions(-) create mode 100644 target/arm/tcg/tcg-cpu.c diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c5ead3365f..e528873ed3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1031,7 +1031,6 @@ extern const VMStateDescription vmstate_arm_cpu; =20 void arm_cpu_do_interrupt(CPUState *cpu); void arm_v7m_cpu_do_interrupt(CPUState *cpu); -bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); =20 int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/arm/internals.h b/target/arm/internals.h index c41f91f1c0..227a80ec21 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -173,11 +173,6 @@ static inline int r14_bank_number(int mode) void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu); void arm_translate_init(void); =20 -#ifdef CONFIG_TCG -void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); -#endif /* CONFIG_TCG */ - - enum arm_fprounding { FPROUNDING_TIEEVEN, FPROUNDING_POSINF, diff --git a/target/arm/tcg/tcg-cpu.h b/target/arm/tcg/tcg-cpu.h index 7e62f92d16..d93c6a6749 100644 --- a/target/arm/tcg/tcg-cpu.h +++ b/target/arm/tcg/tcg-cpu.h @@ -21,6 +21,12 @@ #define ARM_TCG_CPU_H =20 #include "cpu.h" +#include "hw/core/tcg-cpu-ops.h" + +void arm_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb); + +extern struct TCGCPUOps arm_tcg_ops; =20 #ifndef CONFIG_USER_ONLY /* Do semihosting call and set the appropriate return value. */ diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c index e83d55b9f7..c09c89eeac 100644 --- a/target/arm/cpu-sysemu.c +++ b/target/arm/cpu-sysemu.c @@ -28,6 +28,10 @@ #include "sysemu/tcg.h" #include "tcg/tcg-cpu.h" =20 +#ifdef CONFIG_TCG +#include "tcg/tcg-cpu.h" +#endif /* CONFIG_TCG */ + void arm_cpu_set_irq(void *opaque, int irq, int level) { ARMCPU *cpu =3D opaque; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 97d562bbd5..192700fe8f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -27,7 +27,7 @@ #include "cpu.h" #include "cpregs.h" #ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" +#include "tcg/tcg-cpu.h" #endif /* CONFIG_TCG */ #include "cpu32.h" #include "internals.h" @@ -58,25 +58,6 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) } } =20 -#ifdef CONFIG_TCG -void arm_cpu_synchronize_from_tb(CPUState *cs, - const TranslationBlock *tb) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - /* - * It's OK to look at env for the current mode here, because it's - * never possible for an AArch64 TB to chain to an AArch32 TB. - */ - if (is_a64(env)) { - env->pc =3D tb->pc; - } else { - env->regs[15] =3D tb->pc; - } -} -#endif /* CONFIG_TCG */ - static bool arm_cpu_has_work(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -442,175 +423,6 @@ static void arm_cpu_reset(DeviceState *dev) } } =20 -static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, - unsigned int target_el, - unsigned int cur_el, bool secure, - uint64_t hcr_el2) -{ - CPUARMState *env =3D cs->env_ptr; - bool pstate_unmasked; - bool unmasked =3D false; - - /* - * Don't take exceptions if they target a lower EL. - * This check should catch any exceptions that would not be taken - * but left pending. - */ - if (cur_el > target_el) { - return false; - } - - switch (excp_idx) { - case EXCP_FIQ: - pstate_unmasked =3D !(env->daif & PSTATE_F); - break; - - case EXCP_IRQ: - pstate_unmasked =3D !(env->daif & PSTATE_I); - break; - - case EXCP_VFIQ: - if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { - /* VFIQs are only taken when hypervized. */ - return false; - } - return !(env->daif & PSTATE_F); - case EXCP_VIRQ: - if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { - /* VIRQs are only taken when hypervized. */ - return false; - } - return !(env->daif & PSTATE_I); - default: - g_assert_not_reached(); - } - - /* - * Use the target EL, current execution state and SCR/HCR settings to - * determine whether the corresponding CPSR bit is used to mask the - * interrupt. - */ - if ((target_el > cur_el) && (target_el !=3D 1)) { - /* Exceptions targeting a higher EL may not be maskable */ - if (arm_feature(env, ARM_FEATURE_AARCH64)) { - /* - * 64-bit masking rules are simple: exceptions to EL3 - * can't be masked, and exceptions to EL2 can only be - * masked from Secure state. The HCR and SCR settings - * don't affect the masking logic, only the interrupt routing. - */ - if (target_el =3D=3D 3 || !secure || (env->cp15.scr_el3 & SCR_= EEL2)) { - unmasked =3D true; - } - } else { - /* - * The old 32-bit-only environment has a more complicated - * masking setup. HCR and SCR bits not only affect interrupt - * routing but also change the behaviour of masking. - */ - bool hcr, scr; - - switch (excp_idx) { - case EXCP_FIQ: - /* - * If FIQs are routed to EL3 or EL2 then there are cases w= here - * we override the CPSR.F in determining if the exception = is - * masked or not. If neither of these are set then we fall= back - * to the CPSR.F setting otherwise we further assess the s= tate - * below. - */ - hcr =3D hcr_el2 & HCR_FMO; - scr =3D (env->cp15.scr_el3 & SCR_FIQ); - - /* - * When EL3 is 32-bit, the SCR.FW bit controls whether the - * CPSR.F bit masks FIQ interrupts when taken in non-secure - * state. If SCR.FW is set then FIQs can be masked by CPSR= .F - * when non-secure but only when FIQs are only routed to E= L3. - */ - scr =3D scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); - break; - case EXCP_IRQ: - /* - * When EL3 execution state is 32-bit, if HCR.IMO is set t= hen - * we may override the CPSR.I masking when in non-secure s= tate. - * The SCR.IRQ setting has already been taken into conside= ration - * when setting the target EL, so it does not have a furth= er - * affect here. - */ - hcr =3D hcr_el2 & HCR_IMO; - scr =3D false; - break; - default: - g_assert_not_reached(); - } - - if ((scr || hcr) && !secure) { - unmasked =3D true; - } - } - } - - /* - * The PSTATE bits only mask the interrupt if we have not overriden the - * ability above. - */ - return unmasked || pstate_unmasked; -} - -bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - CPUClass *cc =3D CPU_GET_CLASS(cs); - CPUARMState *env =3D cs->env_ptr; - uint32_t cur_el =3D arm_current_el(env); - bool secure =3D arm_is_secure(env); - uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); - uint32_t target_el; - uint32_t excp_idx; - - /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ - - if (interrupt_request & CPU_INTERRUPT_FIQ) { - excp_idx =3D EXCP_FIQ; - target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); - if (arm_excp_unmasked(cs, excp_idx, target_el, - cur_el, secure, hcr_el2)) { - goto found; - } - } - if (interrupt_request & CPU_INTERRUPT_HARD) { - excp_idx =3D EXCP_IRQ; - target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); - if (arm_excp_unmasked(cs, excp_idx, target_el, - cur_el, secure, hcr_el2)) { - goto found; - } - } - if (interrupt_request & CPU_INTERRUPT_VIRQ) { - excp_idx =3D EXCP_VIRQ; - target_el =3D 1; - if (arm_excp_unmasked(cs, excp_idx, target_el, - cur_el, secure, hcr_el2)) { - goto found; - } - } - if (interrupt_request & CPU_INTERRUPT_VFIQ) { - excp_idx =3D EXCP_VFIQ; - target_el =3D 1; - if (arm_excp_unmasked(cs, excp_idx, target_el, - cur_el, secure, hcr_el2)) { - goto found; - } - } - return false; - - found: - cs->exception_index =3D excp_idx; - env->exception.target_el =3D target_el; - cc->tcg_ops->do_interrupt(cs); - return true; -} - void arm_cpu_update_virq(ARMCPU *cpu) { /* @@ -1015,6 +827,7 @@ static void arm_cpu_finalizefn(Object *obj) QLIST_REMOVE(hook, node); g_free(hook); } + #ifndef CONFIG_USER_ONLY if (cpu->pmu_timer) { timer_free(cpu->pmu_timer); @@ -1644,25 +1457,6 @@ static const struct SysemuCPUOps arm_sysemu_ops =3D { .legacy_vmsd =3D &vmstate_arm_cpu, }; #endif - -#ifdef CONFIG_TCG -static const struct TCGCPUOps arm_tcg_ops =3D { - .initialize =3D arm_translate_init, - .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, - .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, - .tlb_fill =3D arm_cpu_tlb_fill, - .debug_excp_handler =3D arm_debug_excp_handler, - -#if !defined(CONFIG_USER_ONLY) - .do_interrupt =3D arm_cpu_do_interrupt, - .do_transaction_failed =3D arm_cpu_do_transaction_failed, - .do_unaligned_access =3D arm_cpu_do_unaligned_access, - .adjust_watchpoint_address =3D arm_adjust_watchpoint_address, - .debug_check_watchpoint =3D arm_debug_check_watchpoint, -#endif /* !CONFIG_USER_ONLY */ -}; -#endif /* CONFIG_TCG */ - static void arm_cpu_class_init(ObjectClass *oc, void *data) { ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index fe422498c7..4606ad8436 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -11,7 +11,7 @@ #include "qemu/osdep.h" #include "cpu.h" #ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" +#include "tcg/tcg-cpu.h" #endif /* CONFIG_TCG */ #include "internals.h" #include "target/arm/idau.h" diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index a8b1efdb36..38cc7c6a3d 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -16,6 +16,7 @@ #include "arm_ldst.h" #include "cpu-mmu.h" #include "cpregs.h" +#include "tcg-cpu.h" =20 static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) { diff --git a/target/arm/tcg/tcg-cpu.c b/target/arm/tcg/tcg-cpu.c new file mode 100644 index 0000000000..9fd996d908 --- /dev/null +++ b/target/arm/tcg/tcg-cpu.c @@ -0,0 +1,229 @@ +/* + * QEMU ARM CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "tcg-cpu.h" +#include "hw/core/tcg-cpu-ops.h" +#include "cpregs.h" +#include "internals.h" +#include "exec/exec-all.h" + +void arm_cpu_synchronize_from_tb(CPUState *cs, + const TranslationBlock *tb) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + /* + * It's OK to look at env for the current mode here, because it's + * never possible for an AArch64 TB to chain to an AArch32 TB. + */ + if (is_a64(env)) { + env->pc =3D tb->pc; + } else { + env->regs[15] =3D tb->pc; + } +} + +static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, + unsigned int target_el, + unsigned int cur_el, bool secure, + uint64_t hcr_el2) +{ + CPUARMState *env =3D cs->env_ptr; + bool pstate_unmasked; + bool unmasked =3D false; + + /* + * Don't take exceptions if they target a lower EL. + * This check should catch any exceptions that would not be taken + * but left pending. + */ + if (cur_el > target_el) { + return false; + } + + switch (excp_idx) { + case EXCP_FIQ: + pstate_unmasked =3D !(env->daif & PSTATE_F); + break; + + case EXCP_IRQ: + pstate_unmasked =3D !(env->daif & PSTATE_I); + break; + + case EXCP_VFIQ: + if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { + /* VFIQs are only taken when hypervized. */ + return false; + } + return !(env->daif & PSTATE_F); + case EXCP_VIRQ: + if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { + /* VIRQs are only taken when hypervized. */ + return false; + } + return !(env->daif & PSTATE_I); + default: + g_assert_not_reached(); + } + + /* + * Use the target EL, current execution state and SCR/HCR settings to + * determine whether the corresponding CPSR bit is used to mask the + * interrupt. + */ + if ((target_el > cur_el) && (target_el !=3D 1)) { + /* Exceptions targeting a higher EL may not be maskable */ + if (arm_feature(env, ARM_FEATURE_AARCH64)) { + /* + * 64-bit masking rules are simple: exceptions to EL3 + * can't be masked, and exceptions to EL2 can only be + * masked from Secure state. The HCR and SCR settings + * don't affect the masking logic, only the interrupt routing. + */ + if (target_el =3D=3D 3 || !secure || (env->cp15.scr_el3 & SCR_= EEL2)) { + unmasked =3D true; + } + } else { + /* + * The old 32-bit-only environment has a more complicated + * masking setup. HCR and SCR bits not only affect interrupt + * routing but also change the behaviour of masking. + */ + bool hcr, scr; + + switch (excp_idx) { + case EXCP_FIQ: + /* + * If FIQs are routed to EL3 or EL2 then there are cases w= here + * we override the CPSR.F in determining if the exception = is + * masked or not. If neither of these are set then we fall= back + * to the CPSR.F setting otherwise we further assess the s= tate + * below. + */ + hcr =3D hcr_el2 & HCR_FMO; + scr =3D (env->cp15.scr_el3 & SCR_FIQ); + + /* + * When EL3 is 32-bit, the SCR.FW bit controls whether the + * CPSR.F bit masks FIQ interrupts when taken in non-secure + * state. If SCR.FW is set then FIQs can be masked by CPSR= .F + * when non-secure but only when FIQs are only routed to E= L3. + */ + scr =3D scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr); + break; + case EXCP_IRQ: + /* + * When EL3 execution state is 32-bit, if HCR.IMO is set t= hen + * we may override the CPSR.I masking when in non-secure s= tate. + * The SCR.IRQ setting has already been taken into conside= ration + * when setting the target EL, so it does not have a furth= er + * affect here. + */ + hcr =3D hcr_el2 & HCR_IMO; + scr =3D false; + break; + default: + g_assert_not_reached(); + } + + if ((scr || hcr) && !secure) { + unmasked =3D true; + } + } + } + + /* + * The PSTATE bits only mask the interrupt if we have not overriden the + * ability above. + */ + return unmasked || pstate_unmasked; +} + +static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + CPUClass *cc =3D CPU_GET_CLASS(cs); + CPUARMState *env =3D cs->env_ptr; + uint32_t cur_el =3D arm_current_el(env); + bool secure =3D arm_is_secure(env); + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); + uint32_t target_el; + uint32_t excp_idx; + + /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */ + + if (interrupt_request & CPU_INTERRUPT_FIQ) { + excp_idx =3D EXCP_FIQ; + target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { + goto found; + } + } + if (interrupt_request & CPU_INTERRUPT_HARD) { + excp_idx =3D EXCP_IRQ; + target_el =3D arm_phys_excp_target_el(cs, excp_idx, cur_el, secure= ); + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { + goto found; + } + } + if (interrupt_request & CPU_INTERRUPT_VIRQ) { + excp_idx =3D EXCP_VIRQ; + target_el =3D 1; + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { + goto found; + } + } + if (interrupt_request & CPU_INTERRUPT_VFIQ) { + excp_idx =3D EXCP_VFIQ; + target_el =3D 1; + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { + goto found; + } + } + return false; + + found: + cs->exception_index =3D excp_idx; + env->exception.target_el =3D target_el; + cc->tcg_ops->do_interrupt(cs); + return true; +} + +struct TCGCPUOps arm_tcg_ops =3D { + .initialize =3D arm_translate_init, + .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, + .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, + .tlb_fill =3D arm_cpu_tlb_fill, + .debug_excp_handler =3D arm_debug_excp_handler, + +#if !defined(CONFIG_USER_ONLY) + .do_interrupt =3D arm_cpu_do_interrupt, + .do_transaction_failed =3D arm_cpu_do_transaction_failed, + .do_unaligned_access =3D arm_cpu_do_unaligned_access, + .adjust_watchpoint_address =3D arm_adjust_watchpoint_address, + .debug_check_watchpoint =3D arm_debug_check_watchpoint, +#endif /* !CONFIG_USER_ONLY */ +}; diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 64a86fd94c..4e690eea6c 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -31,6 +31,7 @@ arm_ss.add(when: 'CONFIG_TCG', if_true: files( 'vfp_helper.c', 'crypto_helper.c', 'debug_helper.c', + 'tcg-cpu.c', =20 ), if_false: files( 'tcg-stubs.c', --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622831048; cv=none; d=zohomail.com; s=zohoarc; b=QMpfGGzROjjME1L41WdMV05XBe6YV1r+4CqMXgWWGcNwbin+EL2PWaELiVPfftWqR4kiC24ZbI5ciFcIyuHebZjCRHPER1nIEcClqEwQX5EUN00OZFlSV97sTDd34uU9ITzwVVd2UbCGl4+RLtYj576wksJKYg5VNxuHxFzxFc4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622831048; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FUsBx0TJprnzGFmcrQF1BJlipqIhjCqwyWs1QwVqKdE=; b=jDgQ9owM13hBti71cGIDFqqGP+11AMlpVZcSeNEfmuAOl/QB806eqPzJftRW3JV0gpm6HZeUKHvustbgPy/QerJCZQ3dhi291iuPar/7RAH71YGXLkNc0zZwSCrdWzMEiWZTJ+5lDZVp1bIhcTXrcsSXz7edL03D8rJhQI+ZHys= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622831048761695.2936934967723; Fri, 4 Jun 2021 11:24:08 -0700 (PDT) Received: from localhost ([::1]:37646 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpEUJ-000437-IZ for importer@patchew.org; Fri, 04 Jun 2021 14:24:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42314) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpET1-0000lQ-IQ for qemu-devel@nongnu.org; Fri, 04 Jun 2021 14:22:47 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:38836) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpESx-0000L7-3Q for qemu-devel@nongnu.org; Fri, 04 Jun 2021 14:22:47 -0400 Received: by mail-wm1-x32b.google.com with SMTP id t4-20020a1c77040000b029019d22d84ebdso8434059wmi.3 for ; Fri, 04 Jun 2021 11:22:42 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id a12sm6236678wmj.36.2021.06.04.11.22.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 11:22:38 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 8D2041FF90; Fri, 4 Jun 2021 16:53:19 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FUsBx0TJprnzGFmcrQF1BJlipqIhjCqwyWs1QwVqKdE=; b=oV5RDrvNSAbsUtf5gqKc/5V9R99tlLG1WhiuoSlxkHsk7facSWO7BV9n9eAkqZBIqU CDrhWpjIdEBTJP9IrIQc4YLHPB6eeWI7vXui3ZweoQk4xCLo2dm+zzBq+/o3c/2GBwL4 WdKiv3swS6QmOzCEHRqinnVKCHQiTp34jK5OOBec2K9IKCMcofjdK/aqfdZtPjMi+YG1 vvjLwxVDiRhoxddoG6uz2riEfTyeJcaqfTtxjKxvkDCaew2Dk7ogU7GiV3ZhKrc5DDlK P7m/lDhSMEBPbCNeezVEXUjMJcO4N408zCnaYkdZKGDm7tR/cdWIUW2lwwBZ43xNJ5AO B4Ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FUsBx0TJprnzGFmcrQF1BJlipqIhjCqwyWs1QwVqKdE=; b=gSOmWo/Lw56jM2txa8N1q2eoin6eTwbaSC21blzsppDWKSigmQBbOpDbzEfwEfOzOs BLnQQ9U3wsVBe+6dB1dSLn5Sel5g1PPOp31Iz0vnOKzyVSNZox7t3ntTE7+u9Htoloah lhDyFhDqf/i/2ik5TwuYv1aTbpgz4fgW6YHlY/2OanvX78tCpo8m9Qd1l36s0bTJJPS1 4aIN7BdlpvKetjwytjULycLVA5gNVN/e8yDybW6Ih1Qj4X8IdbbeutotCz+Y55iDzh3Q 7OpeGL1iH+NIBg0W4l8/ktGDJqWhgarMCrnazJ00oa/qVRlponEXAsBPaWv7mgq5XL4/ 5GqQ== X-Gm-Message-State: AOAM5304dxO8FnxfrWc+itLBoD9Worq0EOiCJGR/wadYsJPdvPwDsuaj HYKSrgYTFZP89lK9KTWchvCW6A== X-Google-Smtp-Source: ABdhPJxqeeJp9ZounOIkwNB2tiqJAeAAtKpnDZ/PNTYNtbIDZRsSN12LcCmiyLul+kz7arS2U2CnHQ== X-Received: by 2002:a1c:67c3:: with SMTP id b186mr5015358wmc.12.1622830961673; Fri, 04 Jun 2021 11:22:41 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 55/99] target/arm: move cpu_tcg to tcg/tcg-cpu-models.c Date: Fri, 4 Jun 2021 16:52:28 +0100 Message-Id: <20210604155312.15902-56-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana move the module containing cpu models definitions for 32bit TCG-only CPUs to tcg/ and rename it for clarity. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/{cpu_tcg.c =3D> tcg/tcg-cpu-models.c} | 7 +------ target/arm/meson.build | 4 ---- target/arm/tcg/meson.build | 1 + 3 files changed, 2 insertions(+), 10 deletions(-) rename target/arm/{cpu_tcg.c =3D> tcg/tcg-cpu-models.c} (99%) diff --git a/target/arm/cpu_tcg.c b/target/arm/tcg/tcg-cpu-models.c similarity index 99% rename from target/arm/cpu_tcg.c rename to target/arm/tcg/tcg-cpu-models.c index 4606ad8436..91af2174a1 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/tcg/tcg-cpu-models.c @@ -1,5 +1,5 @@ /* - * QEMU ARM TCG CPUs. + * QEMU ARM TCG-only CPUs. * * Copyright (c) 2012 SUSE LINUX Products GmbH * @@ -9,10 +9,7 @@ */ =20 #include "qemu/osdep.h" -#include "cpu.h" -#ifdef CONFIG_TCG #include "tcg/tcg-cpu.h" -#endif /* CONFIG_TCG */ #include "internals.h" #include "target/arm/idau.h" #if !defined(CONFIG_USER_ONLY) @@ -24,7 +21,6 @@ /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) =20 -#ifdef CONFIG_TCG static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { CPUClass *cc =3D CPU_GET_CLASS(cs); @@ -48,7 +44,6 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) } return ret; } -#endif /* CONFIG_TCG */ =20 static void arm926_initfn(Object *obj) { diff --git a/target/arm/meson.build b/target/arm/meson.build index 0ccd2fb0bc..8d0c12b2fc 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -18,10 +18,6 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'gdbstub64.c', )) =20 -arm_ss.add(when: 'CONFIG_TCG', if_true: files( - 'cpu_tcg.c', -)) - arm_softmmu_ss =3D ss.source_set() arm_softmmu_ss.add(files( 'arch_dump.c', diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 4e690eea6c..5b36a13a24 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -32,6 +32,7 @@ arm_ss.add(when: 'CONFIG_TCG', if_true: files( 'crypto_helper.c', 'debug_helper.c', 'tcg-cpu.c', + 'tcg-cpu-models.c', =20 ), if_false: files( 'tcg-stubs.c', --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622827009; cv=none; d=zohomail.com; s=zohoarc; b=E5jq5Ok1VtD0NZw9LWexCUKxeDIU1CLkMEe/BE6b39Sq6BrBgkiLtkgWb0uQMz2WzEuy2if14yqj6Odn+CfVnUW+TlcjYCAROGwXtW3SGm90ffFq7jQf8AN0YjqNnUB5FvoqXN1YIWd2Gv4TKdeyFZKClMWlq13YiAdSUf/GTXo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622827009; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5E665klXVT6SgVYAKD/ACEUSAkv3dyFCri5JuwiYWIQ=; b=AiK3aq8C3jXnl3ckAqrYq0Yyn1J8Syx3MesWSH0prMrdn7qTHc1L0hvmYXWcENz03vwEPo9BzrqIeHVI92e51SvkPiaZLTYUhxzR+mAjQU+g0Dz62npz4HMQtOeTeRo7SJcYIoJQ9dUrgjFm6knutqaIdJawZZBkoIUaUJXPu0Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622827009315770.1022824874389; Fri, 4 Jun 2021 10:16:49 -0700 (PDT) Received: from localhost ([::1]:36632 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDRA-0007zK-F5 for importer@patchew.org; Fri, 04 Jun 2021 13:16:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33502) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCke-0008Da-Cr for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:32:53 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:34638) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCka-0002A0-PF for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:32:52 -0400 Received: by mail-wm1-x32c.google.com with SMTP id u5-20020a7bc0450000b02901480e40338bso4548699wmc.1 for ; Fri, 04 Jun 2021 09:32:48 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id b8sm5464966wmd.35.2021.06.04.09.32.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:43 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A236E1FFCE; Fri, 4 Jun 2021 16:53:19 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5E665klXVT6SgVYAKD/ACEUSAkv3dyFCri5JuwiYWIQ=; b=E5VZBNng/kVQRvDNyQZ6xIFIFh0io5q6S/g/QnrodIjXOZAep9gDcFhz2zlHj4+hPX PFrjs3KCp4Vupy18rFpz0pGME8NuyljiUaDcVUciwlNca8M3q26JnPhzY2U6BhgcYHar XVEzYcU6r26c77/C/6e1QVKfRw1BZZNIF4GW88u3rHzaQ7M7D5+gQrgN0LlvIn7OZAAQ slgukS01TUAHFfyGJFLcH1XPjIL4sEfiSoNe0DgnDNlt604bunngaC+sgjQ2XvM+jvG1 2TlhLVTGYl4YhWvplZmY54GbuR9iRp36XnYlJ7U0dNFr/rqRM08vaGC5dJpBgH8J8nyn OSfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5E665klXVT6SgVYAKD/ACEUSAkv3dyFCri5JuwiYWIQ=; b=mhVgKMmhHnGaRw7i4EYxIgfFYuS+ea/xWNJeddE+F4G7J5cC2KNnXywBxo3CO1fcty o19UVu7xn4z7klgOHh5tH3HO8t42+L1UDPQL5Ov5FdtoD0M16jLTmDebzbombKeg79aX i+CY+DqjrjefoJlANKLnDcuFk5wBSGeAqTFihZK0qeKbroMmKUFRSesmVsT75bMj4+Bo rPSHr5+Y6RO9Pt8TWqrZEJPS+pczL3ee1SGi7lWmz204b+qnTl9zCD+/JnY00+/WStzt T5ZfMM7C9/oBaYQU5gPRFyEGqSHqymNixYvm3lkZBI7qRZAXrIsQtbUEWbBl5aizIzXq cB4A== X-Gm-Message-State: AOAM530SNzp+WPoZqGI2cqU8r0KeP2foFWBAw+RbdrntUn+7ObrnhdGu 206mg5EFLT3II2BwBX4aZJsXMg== X-Google-Smtp-Source: ABdhPJzPuvsEG+Y5zHvPQbFx0daEuH/fcRnH40fmpMpukBt1C4vV+H+EcO7C1Tdttg6hL8rpJuDErg== X-Received: by 2002:a05:600c:2146:: with SMTP id v6mr4523210wml.131.1622824367342; Fri, 04 Jun 2021 09:32:47 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 56/99] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Date: Fri, 4 Jun 2021 16:52:29 +0100 Message-Id: <20210604155312.15902-57-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana After this patch it is possible to build only kvm: ./configure --disable-tcg --enable-kvm Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-sysemu.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c index c09c89eeac..2d3fe4f643 100644 --- a/target/arm/cpu-sysemu.c +++ b/target/arm/cpu-sysemu.c @@ -917,11 +917,13 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) unsigned int cur_el =3D arm_current_el(env); int rt; =20 - /* - * Note that new_el can never be 0. If cur_el is 0, then - * el0_a64 is is_a64(), else el0_a64 is ignored. - */ - aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); + if (tcg_enabled()) { + /* + * Note that new_el can never be 0. If cur_el is 0, then + * el0_a64 is is_a64(), else el0_a64 is ignored. + */ + aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); + } =20 if (cur_el < new_el) { /* --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622827280; cv=none; d=zohomail.com; s=zohoarc; b=UxI6Ca1FT9gpSzeqTmzmTJxa1vufJ+E4ozPgBUHFlmmCsgtR/6sVigYAKW6NlyuNSI0OvhgkFx59PmUcVqdESHklAKRaJkQ3j4n7wkQGj97fnM/uhTYsT8EZ0fBzfvt6nHzM4QuNeYhOIvaUr8mbj4tbpuKYDqDkpawYN6b+wGs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622827280; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6HF2MyB2aBKBLReV9F/D4V7kzFy2KuqmCJBZnZnN5/0=; b=ZFbBP7m67RT/30Yy/M8yjYHsIICzWoKJs5IFq/+OYHwPJv5+4OJqswzNtZoIrTcqXryC3tnceAC6ujVLsAtuofr8PJjLOSd61IGqdT17r4oaQjRiGHbaLy1pQ1BLcX7FC1f6Yf93qPPNb1fjSoKBncrnrme6yZfQpy1z7U6wv/A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162282728042221.25643860472303; Fri, 4 Jun 2021 10:21:20 -0700 (PDT) Received: from localhost ([::1]:53394 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDVX-0003Ho-6J for importer@patchew.org; Fri, 04 Jun 2021 13:21:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33768) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCkt-00007q-Gi for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:07 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:36769) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCkf-0002D5-N2 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:07 -0400 Received: by mail-wm1-x32b.google.com with SMTP id n17-20020a7bc5d10000b0290169edfadac9so8286499wmk.1 for ; Fri, 04 Jun 2021 09:32:53 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id l10sm7192329wrm.2.2021.06.04.09.32.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:51 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id B8E8E1FFCF; Fri, 4 Jun 2021 16:53:19 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6HF2MyB2aBKBLReV9F/D4V7kzFy2KuqmCJBZnZnN5/0=; b=JWn9SNFgYVkwm9qFq/ksZND+Q+z/XCqtk48kb3QP45cWyRSsmNqgqmsHUqttVuYsSe GLDs7ZsoewEUqx87JkjllAhteaaDzYlqbrdm2HYKXfNPG4/0YC0VmD7nnO+X2G7+BL0r eLKUCW8coqNhB3fbZn993pa21hz/mXbTTTxehLtXQ0rhpVXQU8LX0awYCbg/rYOLoXib ru8UftqTEIsFdFbAtIXjZQR5kTBLQaLmF18qU8RHN+sFSOgCrc5lcLPM+VBcir4cF1OJ QCSVxGT79Zwydj5v/K7b5GfZu2dBlQZIC1Zn8vZbYoMGGeG5qK6Pd8f+JXoXxZHOxjdp BNyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6HF2MyB2aBKBLReV9F/D4V7kzFy2KuqmCJBZnZnN5/0=; b=U1FamiIenaXQ8dD1LRhkBY/fvygukGbEpQfScfNkWfVrB5m5YHwtrwFr+ckYpFNB38 sEU7MTeXrn0QAw76VEkVCnwpwsYxUppaPZGW4ckWVuDPozqble/hf9LcAaVQTVS/fEqW 6Cer9rLF4Mc9PHQUYIazPxxFC2tzQRjcCa7Tm+1GY3qddFWQs0L9REXFkVjMFlcaiyec gKC53p2b/CiacOm7M0TRtRzWvJZ1GYyEv9Drt4tWd7wvnhA+BX/dSQgm852pEh4uZbpq NwJfmY+W1Ky8Alw585n81Xo7k3fH9MEZnlq5JkN1oYcERN5lIAnybwjqxm3pteXfj2HU osrQ== X-Gm-Message-State: AOAM5338cFIw1UQnVOUdvxaZikUajUM6ADWp+gfA/bzTPDYWcKklSBeK iffF7r0x39f3HwLs5E0HWm2ewg== X-Google-Smtp-Source: ABdhPJzlOqvd2yCmX9rj1EKu/hDCy4KqDY7vREHS4K8eOptVQ3tOi3B1Szy+ltFbBWknpSJL9WAK8A== X-Received: by 2002:a05:600c:3544:: with SMTP id i4mr4691118wmq.112.1622824372346; Fri, 04 Jun 2021 09:32:52 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 57/99] target/arm: remove kvm include file for PSCI and arm-powerctl Date: Fri, 4 Jun 2021 16:52:30 +0100 Message-Id: <20210604155312.15902-58-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana The QEMU PSCI implementation is not used for KVM, we do not need the kvm constants header. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/arm-powerctl.h | 2 -- target/arm/psci.c | 1 - 2 files changed, 3 deletions(-) diff --git a/target/arm/arm-powerctl.h b/target/arm/arm-powerctl.h index 37c8a04f0a..35e048ce14 100644 --- a/target/arm/arm-powerctl.h +++ b/target/arm/arm-powerctl.h @@ -11,8 +11,6 @@ #ifndef QEMU_ARM_POWERCTL_H #define QEMU_ARM_POWERCTL_H =20 -#include "kvm-consts.h" - #define QEMU_ARM_POWERCTL_RET_SUCCESS QEMU_PSCI_RET_SUCCESS #define QEMU_ARM_POWERCTL_INVALID_PARAM QEMU_PSCI_RET_INVALID_PARAMS #define QEMU_ARM_POWERCTL_ALREADY_ON QEMU_PSCI_RET_ALREADY_ON diff --git a/target/arm/psci.c b/target/arm/psci.c index 6709e28013..800c4a55d8 100644 --- a/target/arm/psci.c +++ b/target/arm/psci.c @@ -19,7 +19,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "kvm-consts.h" #include "qemu/main-loop.h" #include "sysemu/runstate.h" #include "internals.h" --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622825515; cv=none; d=zohomail.com; s=zohoarc; b=ApYN8sZGsgU3Q1UzYkjtjNdXBw8F9quvUnFTAd8IKM6FLs9aNbaTIgd6Hr/xrTnD/uLPspos5a2RCK6qa4fHCvHVG6iClikg7AwkwxP4UttcpucXZq4csPEjx32IlICXzAl0Q2bBxDYv3dRO2ZebodmaAhD68erD0FkNgDVFZMI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622825515; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eaey0oqZSKDutKn14TjZF2vUFk3jKdYZaYsrDxS3CSk=; b=hmvk6xI7gKidYhRrKtWqm1Sk8KdMxoccJyIgStcpgUNn/7MLG7fUwqMlqTeDfOq4VJq47d/ntttv/VxoZhzH9pPTPE2nEoKqJ7URErYO4iirIn08Ynt1TOlOjFMU713fjUjhtN5izXPnCWuKRcN3Tk1rX0ts7rZQqPzr7kcM1sg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622825514776331.4428661784858; Fri, 4 Jun 2021 09:51:54 -0700 (PDT) Received: from localhost ([::1]:34424 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpD31-0007JM-OX for importer@patchew.org; Fri, 04 Jun 2021 12:51:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48858) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCIP-0000em-86 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:41 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:41950) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHv-0005wJ-5C for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:40 -0400 Received: by mail-wr1-x432.google.com with SMTP id h8so9802598wrz.8 for ; Fri, 04 Jun 2021 09:03:05 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id p20sm8680500wmq.10.2021.06.04.09.02.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:56 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 06CC91FFD0; Fri, 4 Jun 2021 16:53:20 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eaey0oqZSKDutKn14TjZF2vUFk3jKdYZaYsrDxS3CSk=; b=yuTEgwM153O7/VZoMA1ldke6yzN3PW5rfzoTQjV9jcsS22OB7R9tZOoBR9VuIhm1Vy ++UeqDECAlhEQOvZmDW4eHY7+gL9KD+q9oE9eZGz/Gt9LZT+ZF1k8rKPldKb/EBCcGk0 PAWXeOHngAahsA/32SsH0tuuox+zr+VKRO0jygSmG0BMtfu8JI57Y6WvVr1ezMlEUpCL 9WLitbfPd7oo1cyvbOwPVlbTjjdNVn3tXo5SUn802imLBebuek5/YQ8tz4PD8We7HKxQ h6XZBgpCeqUVpcO3euHNL+4Lpft7cKwgsLRHRxCT+xEmAE9vqmKID841LRyVpeP6CS+M XLOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eaey0oqZSKDutKn14TjZF2vUFk3jKdYZaYsrDxS3CSk=; b=F5rCSsZS0AereCmnmpbuGGX+TAbCt0jUqx2iDkerikPdhDfBHNlhe5nIeF8cy/QLgh uckoki6gfqE0wXzyRz9/rN1CIW7FX3cHCHk5wkxmV55cYopj0ho6QcOc6GWqFzLn7jSK grb3b6Xnso4BNQLb07GoPkRfr80VW96uYuxCZyOa8FnGfR7GzvYAPJnLcvKbscfvwkUU xMWYTHsh6J/koHn9TFRtOy8ewCLw6gegZrbdziIQwww2CxeCkTD+NgUF9csCBQxjUxEi 9GgYYSyVXWE/h28wYl5jQMBWK7VulUuwsXaxeKVy83WrbUW11wZyrwmwmdIRhHMlUXbm /R6Q== X-Gm-Message-State: AOAM531k8KeAaiTBvfaDZANkEvmTDKASKgGyp3EgAh55v6WQd2/JTEVq aRdzIsaCQD5RjBhjCvcpzf/Nhw== X-Google-Smtp-Source: ABdhPJzNaVpkITuH0IIs93TOwu7gUMfgxXD+6ZmyCNlh1PHPWfH12CtZ8g4sjBvhinM/ZMUAhvS6RA== X-Received: by 2002:adf:e109:: with SMTP id t9mr4611736wrz.372.1622822584283; Fri, 04 Jun 2021 09:03:04 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 58/99] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/ Date: Fri, 4 Jun 2021 16:52:31 +0100 Message-Id: <20210604155312.15902-59-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , "Michael S. Tsirkin" , Radoslaw Biernacki , Richard Henderson , Shannon Zhao , qemu-arm@nongnu.org, Claudio Fontana , "Edgar E. Iglesias" , Igor Mammedov , Leif Lindholm , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana and adapt the code including the header references, and trace-events / trace.h Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- meson.build | 2 +- target/arm/cpu.h | 2 +- target/arm/{ =3D> kvm}/kvm-consts.h | 0 target/arm/{ =3D> kvm}/kvm_arm.h | 0 target/arm/kvm/trace.h | 1 + target/arm/trace.h | 1 - hw/arm/sbsa-ref.c | 2 +- hw/arm/virt-acpi-build.c | 2 +- hw/arm/virt.c | 2 +- hw/arm/xlnx-versal.c | 2 +- hw/arm/xlnx-zynqmp.c | 2 +- hw/cpu/a15mpcore.c | 2 +- hw/intc/arm_gic_kvm.c | 2 +- hw/intc/arm_gicv3_its_kvm.c | 2 +- hw/intc/arm_gicv3_kvm.c | 2 +- target/arm/cpu-sysemu.c | 2 +- target/arm/cpu.c | 2 +- target/arm/cpu32.c | 2 +- target/arm/cpu64.c | 2 +- target/arm/{ =3D> kvm}/kvm.c | 0 target/arm/{ =3D> kvm}/kvm64.c | 0 target/arm/machine.c | 2 +- target/arm/monitor.c | 2 +- target/arm/tcg/sysemu/tcg-cpu.c | 1 - MAINTAINERS | 2 +- target/arm/kvm/meson.build | 4 ++++ target/arm/{ =3D> kvm}/trace-events | 0 target/arm/meson.build | 3 +-- 28 files changed, 24 insertions(+), 22 deletions(-) rename target/arm/{ =3D> kvm}/kvm-consts.h (100%) rename target/arm/{ =3D> kvm}/kvm_arm.h (100%) create mode 100644 target/arm/kvm/trace.h delete mode 100644 target/arm/trace.h rename target/arm/{ =3D> kvm}/kvm.c (100%) rename target/arm/{ =3D> kvm}/kvm64.c (100%) create mode 100644 target/arm/kvm/meson.build rename target/arm/{ =3D> kvm}/trace-events (100%) diff --git a/meson.build b/meson.build index eb22030571..e2a22984b8 100644 --- a/meson.build +++ b/meson.build @@ -1859,8 +1859,8 @@ if have_system or have_user trace_events_subdirs +=3D [ 'accel/tcg', 'hw/core', - 'target/arm', 'target/arm/tcg', + 'target/arm/kvm', 'target/hppa', 'target/i386', 'target/i386/kvm', diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e528873ed3..f57fa9b9f5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -20,7 +20,7 @@ #ifndef ARM_CPU_H #define ARM_CPU_H =20 -#include "kvm-consts.h" +#include "kvm/kvm-consts.h" #include "hw/registerfields.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" diff --git a/target/arm/kvm-consts.h b/target/arm/kvm/kvm-consts.h similarity index 100% rename from target/arm/kvm-consts.h rename to target/arm/kvm/kvm-consts.h diff --git a/target/arm/kvm_arm.h b/target/arm/kvm/kvm_arm.h similarity index 100% rename from target/arm/kvm_arm.h rename to target/arm/kvm/kvm_arm.h diff --git a/target/arm/kvm/trace.h b/target/arm/kvm/trace.h new file mode 100644 index 0000000000..c688745b90 --- /dev/null +++ b/target/arm/kvm/trace.h @@ -0,0 +1 @@ +#include "trace/trace-target_arm_kvm.h" diff --git a/target/arm/trace.h b/target/arm/trace.h deleted file mode 100644 index 60372d8e26..0000000000 --- a/target/arm/trace.h +++ /dev/null @@ -1 +0,0 @@ -#include "trace/trace-target_arm.h" diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 43c19b4923..38ac4ca2cd 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -28,7 +28,7 @@ #include "sysemu/runstate.h" #include "sysemu/sysemu.h" #include "exec/hwaddr.h" -#include "kvm_arm.h" +#include "kvm/kvm_arm.h" #include "hw/arm/boot.h" #include "hw/block/flash.h" #include "hw/boards.h" diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 60fe2e65a7..bfd7f58eec 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -51,7 +51,7 @@ #include "sysemu/numa.h" #include "sysemu/reset.h" #include "sysemu/tpm.h" -#include "kvm_arm.h" +#include "kvm/kvm_arm.h" #include "migration/vmstate.h" #include "hw/acpi/ghes.h" =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 840758666d..4573c3daf5 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -63,7 +63,7 @@ #include "hw/intc/arm_gic.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/irq.h" -#include "kvm_arm.h" +#include "kvm/kvm_arm.h" #include "hw/firmware/smbios.h" #include "qapi/visitor.h" #include "qapi/qapi-visit-common.h" diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index fb776834f7..d42e19ab5a 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -18,7 +18,7 @@ #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "hw/arm/boot.h" -#include "kvm_arm.h" +#include "kvm/kvm_arm.h" #include "hw/misc/unimp.h" #include "hw/arm/xlnx-versal.h" =20 diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 3597e8db4d..0af49c713a 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -23,7 +23,7 @@ #include "hw/boards.h" #include "sysemu/kvm.h" #include "sysemu/sysemu.h" -#include "kvm_arm.h" +#include "kvm/kvm_arm.h" =20 #define GIC_NUM_SPI_INTR 160 =20 diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index 774ca9987a..670d07a98c 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -25,7 +25,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "sysemu/kvm.h" -#include "kvm_arm.h" +#include "kvm/kvm_arm.h" =20 static void a15mp_priv_set_irq(void *opaque, int irq, int level) { diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index 7d2a13273a..9b45b3cad4 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -24,7 +24,7 @@ #include "qemu/module.h" #include "migration/blocker.h" #include "sysemu/kvm.h" -#include "kvm_arm.h" +#include "kvm/kvm_arm.h" #include "gic_internal.h" #include "vgic_common.h" #include "qom/object.h" diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index b554d2ede0..5322e1bcaf 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -25,7 +25,7 @@ #include "hw/qdev-properties.h" #include "sysemu/runstate.h" #include "sysemu/kvm.h" -#include "kvm_arm.h" +#include "kvm/kvm_arm.h" #include "migration/blocker.h" #include "qom/object.h" =20 diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 96c7e8b80c..086b0ba0d3 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -26,7 +26,7 @@ #include "qemu/module.h" #include "sysemu/kvm.h" #include "sysemu/runstate.h" -#include "kvm_arm.h" +#include "kvm/kvm_arm.h" #include "gicv3_internal.h" #include "vgic_common.h" #include "migration/blocker.h" diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c index 2d3fe4f643..26467c640b 100644 --- a/target/arm/cpu-sysemu.c +++ b/target/arm/cpu-sysemu.c @@ -24,7 +24,7 @@ #include "cpu.h" #include "internals.h" #include "sysemu/hw_accel.h" -#include "kvm_arm.h" +#include "kvm/kvm_arm.h" #include "sysemu/tcg.h" #include "tcg/tcg-cpu.h" =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 192700fe8f..9b81cbe386 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -39,7 +39,7 @@ #endif #include "sysemu/tcg.h" #include "sysemu/hw_accel.h" -#include "kvm_arm.h" +#include "kvm/kvm_arm.h" #include "disas/capstone.h" #include "fpu/softfloat.h" #include "cpu-mmu.h" diff --git a/target/arm/cpu32.c b/target/arm/cpu32.c index a6ba91ae08..56f02ca891 100644 --- a/target/arm/cpu32.c +++ b/target/arm/cpu32.c @@ -37,7 +37,7 @@ #include "sysemu/sysemu.h" #include "sysemu/tcg.h" #include "sysemu/hw_accel.h" -#include "kvm_arm.h" +#include "kvm/kvm_arm.h" #include "disas/capstone.h" #include "fpu/softfloat.h" #include "cpu-mmu.h" diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 7cd73ae0b6..f5ead76374 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -31,7 +31,7 @@ #include "hw/loader.h" #endif #include "sysemu/kvm.h" -#include "kvm_arm.h" +#include "kvm/kvm_arm.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" #include "cpregs.h" diff --git a/target/arm/kvm.c b/target/arm/kvm/kvm.c similarity index 100% rename from target/arm/kvm.c rename to target/arm/kvm/kvm.c diff --git a/target/arm/kvm64.c b/target/arm/kvm/kvm64.c similarity index 100% rename from target/arm/kvm64.c rename to target/arm/kvm/kvm64.c diff --git a/target/arm/machine.c b/target/arm/machine.c index 2982e8d7f4..595ab94237 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -3,7 +3,7 @@ #include "qemu/error-report.h" #include "sysemu/kvm.h" #include "sysemu/tcg.h" -#include "kvm_arm.h" +#include "kvm/kvm_arm.h" #include "internals.h" #include "migration/cpu.h" #include "cpregs.h" diff --git a/target/arm/monitor.c b/target/arm/monitor.c index 80c64fa355..0c72bf7c31 100644 --- a/target/arm/monitor.c +++ b/target/arm/monitor.c @@ -22,7 +22,7 @@ =20 #include "qemu/osdep.h" #include "hw/boards.h" -#include "kvm_arm.h" +#include "kvm/kvm_arm.h" #include "qapi/error.h" #include "qapi/visitor.h" #include "qapi/qobject-input-visitor.h" diff --git a/target/arm/tcg/sysemu/tcg-cpu.c b/target/arm/tcg/sysemu/tcg-cp= u.c index 2c395f47e7..6ab49ba614 100644 --- a/target/arm/tcg/sysemu/tcg-cpu.c +++ b/target/arm/tcg/sysemu/tcg-cpu.c @@ -39,7 +39,6 @@ #include "sysemu/sysemu.h" #include "sysemu/tcg.h" #include "sysemu/hw_accel.h" -#include "kvm_arm.h" #include "disas/capstone.h" #include "fpu/softfloat.h" #include "cpu-mmu.h" diff --git a/MAINTAINERS b/MAINTAINERS index 1ff68116b0..24e55954d4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -373,7 +373,7 @@ ARM KVM CPUs M: Peter Maydell L: qemu-arm@nongnu.org S: Maintained -F: target/arm/kvm.c +F: target/arm/kvm/kvm.c =20 MIPS KVM CPUs M: Huacai Chen diff --git a/target/arm/kvm/meson.build b/target/arm/kvm/meson.build new file mode 100644 index 0000000000..e92010fa3f --- /dev/null +++ b/target/arm/kvm/meson.build @@ -0,0 +1,4 @@ +arm_ss.add(when: 'CONFIG_KVM', if_true: files( + 'kvm.c', + 'kvm64.c', +)) diff --git a/target/arm/trace-events b/target/arm/kvm/trace-events similarity index 100% rename from target/arm/trace-events rename to target/arm/kvm/trace-events diff --git a/target/arm/meson.build b/target/arm/meson.build index 8d0c12b2fc..448e94861f 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -11,8 +11,6 @@ arm_ss.add(files( )) arm_ss.add(zlib) =20 -arm_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c', 'kvm64.c'), if_fals= e: files('kvm-stub.c')) - arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'cpu64.c', 'gdbstub64.c', @@ -38,6 +36,7 @@ arm_user_ss.add(files( )) =20 subdir('tcg') +subdir('kvm') =20 target_arch +=3D {'arm': arm_ss} target_softmmu_arch +=3D {'arm': arm_softmmu_ss} --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622825295; cv=none; d=zohomail.com; s=zohoarc; b=j9CByhB1qYRU0UqwtDwLf9+jSKTE1gFzC8BaAd8m3dRMSfzE73yeAgI/M9odfTAKNyzdItO6PDgs3gGxWyN+qHplXr0LDdhjtWiSni3l/uVXi6HIuW0f07TbAW73EvFaLgsm2b27uEnNq85zgaOzlZeqt1a49E4RDZ7h0v8e3Yk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622825295; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wONPc0qYV05aYWd43IzxOdQbvCsObFB2L5QRCtxqT+c=; b=QfCC2DU1Ar5tXP8E4ykGfndlu29SiVUhnTIEq959SAwxVCamXhMg6XFRanVVWtOczlXVcHqfMTvi5GPR0oQNPQHb9I/tXbchc5dOCfGdXSuAL7btO3YUKXYnq+AaLOHvlHtTXYhVWiUjbdCFBmB6olu/iyzdDcI41O1AwZDrqVA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622825295470844.1424594667902; Fri, 4 Jun 2021 09:48:15 -0700 (PDT) Received: from localhost ([::1]:48288 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCzW-00066a-AO for importer@patchew.org; Fri, 04 Jun 2021 12:48:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51852) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCRJ-0002yp-Na for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:53 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:45657) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCRD-0003pT-A5 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:53 -0400 Received: by mail-wm1-x333.google.com with SMTP id v206-20020a1cded70000b02901a586d3fa23so1645978wmg.4 for ; Fri, 04 Jun 2021 09:12:46 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id c12sm8185002wrr.90.2021.06.04.09.12.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:12:42 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 1ABC41FFD1; Fri, 4 Jun 2021 16:53:20 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wONPc0qYV05aYWd43IzxOdQbvCsObFB2L5QRCtxqT+c=; b=blVjmi0T4xncD1CPiZb8+go4DchsTCsavQ/SW7q4YfAZ980JftA8hIkvZYSaKASpLL 1rBo3U9CbrOFqI/wFr+7tRE5wjXa34o0IVgmCGX9AOqCEXlp/zhhKLLlB8HbJy+AVxDJ eDYy/1IhmgVx6hzorf4Z50IX5HDkvz8SUh6QPjE2Ck22Z/FhTHi8EXNk9Ei60mqVA2yd U2DOgpBaSk2SnyqJIhAoN7y4ActZKm8fpvTqto3igWttCPxAb9DbuiZCo0U1yrgqTMiz uBRac7AEjuFes/jC2Y3kJh6JMsZ34ql+grXjTOXE6usMrx8SQwPG0SaSKYXxo3Nf5fUs VNVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wONPc0qYV05aYWd43IzxOdQbvCsObFB2L5QRCtxqT+c=; b=oXXnNVdhS0n4n6Czgf03P+WIOFuggXOrxwiqL2VVm7N9BSn9PKiNcZLN/s5GLYVaqI JQXxLiwWsA5icnWdECoBVnEd6s4ohtex3l8h/hfN5kjpQBvQTQO4kT21SXl2BAi2h1Ks bd6j2jnlceNaPict1A/5+u2ypAnVhWeYyS8m8KnflxRtz9Z/vRBZjL2KQ8mBOdZMzXtE ak+kVXJxzmyYDHGlCcjnyn77X4vZnlRS9vbJcz4JyMO9h72Fag8U9dxjw6l9YZpAnwFx ROw6wdPou68gxkUbHQk8+0B9E/XyC01h3wjsMphpjyGc7+RHGSuIoJ6a26G3CYB/puJu aZ7Q== X-Gm-Message-State: AOAM533kE+C9TebPHjLP0La6dDzKySGm4WweVXiMhI1iCIVgprmqGuGH 0y/ypVbe/49kJ9Po7NSCB0yF8A== X-Google-Smtp-Source: ABdhPJzfSjKX8Cx12RN/EsHmSi18yPKEKbQ7A08bsWGI6hH65+G0+S4+scRK9mhU+BsuPMwottzaeg== X-Received: by 2002:a05:600c:19c8:: with SMTP id u8mr4496800wmq.50.1622823165972; Fri, 04 Jun 2021 09:12:45 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 59/99] MAINTAINERS: update arm kvm maintained files to all in target/arm/kvm/ Date: Fri, 4 Jun 2021 16:52:32 +0100 Message-Id: <20210604155312.15902-60-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 24e55954d4..95e836af49 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -373,7 +373,7 @@ ARM KVM CPUs M: Peter Maydell L: qemu-arm@nongnu.org S: Maintained -F: target/arm/kvm/kvm.c +F: target/arm/kvm/ =20 MIPS KVM CPUs M: Huacai Chen --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622824965; cv=none; d=zohomail.com; s=zohoarc; b=CmpSKrDmD798gGm3ddzR0AJ/fBP0eXPtxlDngBOjMr+S3O/VuZXSSG3+aw5doq3ZkQuIZg8n8Ri+sgke9voGRHh0SVNbtMBJRxDhHu8iOApfU0kyY+PUh5V78SeSqDADdKhSyr3GwrwxSDxQoep1NFibGLoV29r3Lgv2TLVpXeg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622824965; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OjGXb7X5f/RV9s4a2gQrpM53TYKYVdPrN+K7LbjNZd0=; b=Srb55ZgWqK16tUfoQdDMTUWilSCoLPOUL9urlXy6F7SYZs9GnJMAAk9f7B7cK/oyB0s8eQ0PJhvlWVC0u4gG1oAfLOVvF9lHXLA2orNLdvJBwl9oTrNYSylYxrvkqUvmqcVsG3qmF7zcD55gwMIY+hK8oMwlG//TIy8fZxoeHbo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622824964998361.1740282456194; Fri, 4 Jun 2021 09:42:44 -0700 (PDT) Received: from localhost ([::1]:58854 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCuB-0002DX-W4 for importer@patchew.org; Fri, 04 Jun 2021 12:42:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51676) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCRC-0002iU-Tb for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:46 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:55930) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCR6-0003n3-J0 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:46 -0400 Received: by mail-wm1-x32e.google.com with SMTP id g204so5685922wmf.5 for ; Fri, 04 Jun 2021 09:12:40 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id y22sm10838514wma.36.2021.06.04.09.12.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:12:37 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 368EA1FF91; Fri, 4 Jun 2021 16:53:20 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OjGXb7X5f/RV9s4a2gQrpM53TYKYVdPrN+K7LbjNZd0=; b=DQPgJ414R5YMAqouvs6BLK9liTnc8PVZhojoyUvd8wVnLHDlCnCU1ZSrEu/IUHDsjA 3wecGKhPjUVBUvrMV8x8f7mGpIDjJedP68ThbWwlHIRU61T6RQN+mZV5DT/nusoAEnVx IomLez84oWWVRqmU0yOLLceBKqHbqZTv5zXKc/HqRhMCbcB4htifS03DAkAs8PBhWlhx 5Ltem084vwDTHx1oK3BH31a24Q8QPB7PtnwtQs46hnAg4s9ggR+yhdyXTgZ36h2g3eSH apwzL7BN4mCnGlEsqaSgJe/fj1DbcynPb/prQjr3oUnKH+zwDsBUW9BMdZc22k0EI3l4 EgyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OjGXb7X5f/RV9s4a2gQrpM53TYKYVdPrN+K7LbjNZd0=; b=QdZHewO/yGt8WwMeH1MgDhcjJB9QeL99s0+tEvqRNSs6rDoayjus4qK9XVbCPhFYfB /Ndaz+BwIrNNkTNi/veGpLoGHfoPI99xcdvF/pVnEWy47cpsFh7IefA9wa4yj9sFdTst UwdnBv0WDTaw5kjmL3suGyZvpckBWLC2yBeU+3aUubJUn3IVSn5/rQ4PlRvdBa5Jv/Qe PRzTXpRFcYABrDsZi/WnMf0d4Fv6k1qAVN/gs6Ko3yau0y1nQkDmtyAQnSGc5CutUNWT xqS/ofOEn5eN0nrM50Lmpc+aNJhVavtpwv08SbrXNG3gcOFDbo1a7YTX3kBgdX86x2ob Tgbg== X-Gm-Message-State: AOAM533IaNgCmSmDCKL+4ILZ6/ZDHbAjnoxj6wxtwswFNIcUXZUfhLF+ 0e292DXr4UiS6h/hkUzzdgo6dg== X-Google-Smtp-Source: ABdhPJyMnqLwFA2dcwldiDHwMbWIhNZx2GBj5e7OAqw86YSrXSFiaVyYXAKp8ByR4RHx2SdamtEscQ== X-Received: by 2002:a05:600c:3795:: with SMTP id o21mr4432038wmr.99.1622823159079; Fri, 04 Jun 2021 09:12:39 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 60/99] target/arm: cleanup cpu includes Date: Fri, 4 Jun 2021 16:52:33 +0100 Message-Id: <20210604155312.15902-61-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana cpu.c, cpu32.c, cpu64.c, tcg/sysemu/tcg-cpu.c, all need a good cleanup when it comes to included header files. Signed-off-by: Claudio Fontana Acked-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu.c | 6 ++---- target/arm/cpu32.c | 14 -------------- target/arm/cpu64.c | 6 ------ target/arm/tcg/sysemu/tcg-cpu.c | 22 +--------------------- 4 files changed, 3 insertions(+), 45 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9b81cbe386..7e3726ff00 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -21,24 +21,22 @@ #include "qemu/osdep.h" #include "qemu-common.h" #include "target/arm/idau.h" -#include "qemu/module.h" #include "qapi/error.h" -#include "qapi/visitor.h" #include "cpu.h" #include "cpregs.h" + #ifdef CONFIG_TCG #include "tcg/tcg-cpu.h" #endif /* CONFIG_TCG */ #include "cpu32.h" -#include "internals.h" #include "exec/exec-all.h" #include "hw/qdev-properties.h" #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" #include "hw/boards.h" #endif + #include "sysemu/tcg.h" -#include "sysemu/hw_accel.h" #include "kvm/kvm_arm.h" #include "disas/capstone.h" #include "fpu/softfloat.h" diff --git a/target/arm/cpu32.c b/target/arm/cpu32.c index 56f02ca891..6c53245d66 100644 --- a/target/arm/cpu32.c +++ b/target/arm/cpu32.c @@ -20,26 +20,12 @@ =20 #include "qemu/osdep.h" #include "qemu/qemu-print.h" -#include "qemu-common.h" -#include "target/arm/idau.h" #include "qemu/module.h" -#include "qapi/error.h" -#include "qapi/visitor.h" #include "cpu.h" #include "cpregs.h" -#include "internals.h" -#include "exec/exec-all.h" -#include "hw/qdev-properties.h" #if !defined(CONFIG_USER_ONLY) -#include "hw/loader.h" #include "hw/boards.h" #endif -#include "sysemu/sysemu.h" -#include "sysemu/tcg.h" -#include "sysemu/hw_accel.h" -#include "kvm/kvm_arm.h" -#include "disas/capstone.h" -#include "fpu/softfloat.h" #include "cpu-mmu.h" #include "cpu32.h" =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f5ead76374..a8ff1994ca 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -23,13 +23,7 @@ #include "qemu/qemu-print.h" #include "cpu.h" #include "cpu32.h" -#ifdef CONFIG_TCG -#include "hw/core/tcg-cpu-ops.h" -#endif /* CONFIG_TCG */ #include "qemu/module.h" -#if !defined(CONFIG_USER_ONLY) -#include "hw/loader.h" -#endif #include "sysemu/kvm.h" #include "kvm/kvm_arm.h" #include "qapi/visitor.h" diff --git a/target/arm/tcg/sysemu/tcg-cpu.c b/target/arm/tcg/sysemu/tcg-cp= u.c index 6ab49ba614..327b2a5073 100644 --- a/target/arm/tcg/sysemu/tcg-cpu.c +++ b/target/arm/tcg/sysemu/tcg-cpu.c @@ -19,29 +19,9 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/qemu-print.h" -#include "qemu-common.h" -#include "target/arm/idau.h" -#include "qemu/module.h" -#include "qapi/error.h" -#include "qapi/visitor.h" #include "cpu.h" -#include "hw/core/tcg-cpu-ops.h" #include "semihosting/common-semi.h" -#include "cpregs.h" -#include "internals.h" -#include "exec/exec-all.h" -#include "hw/qdev-properties.h" -#if !defined(CONFIG_USER_ONLY) -#include "hw/loader.h" -#include "hw/boards.h" -#endif -#include "sysemu/sysemu.h" -#include "sysemu/tcg.h" -#include "sysemu/hw_accel.h" -#include "disas/capstone.h" -#include "fpu/softfloat.h" -#include "cpu-mmu.h" +#include "qemu/log.h" #include "tcg/tcg-cpu.h" =20 /* --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622824119; cv=none; d=zohomail.com; s=zohoarc; b=k0Lw2mbey7v2xi8jth/5RH/Svqi6RnVRZ1voBfQN9CarqiwieUt61Z1x811OCzAApZwuIjqc2+5/stPx8HRAS5AowfsVxWSGs1QwELaZQleu8toX9OCmJ3rRSP5UFk357CN3vLsMDhNYXJ4sHQBM8rJ85ZXl3EZStiiH6YYBTY4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622824119; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1M9DSMG90oxpkIftDhmS6X3YTXP3prGe70gnCR2W/W0=; b=ALFw2n5YipErNODjRS3NyuDw0L+PDgmFwGcqlXdQ44tXX6Eh6XaRQze52RJ7kQSDuG4V/RglarWG4HhXxxKPYx8AxsCK4+Bw/3BxAhwROQ0fXUoEbt/0ICfMZUhKrShUJT56ZtdY95Vx9SI0n7HmcsuI3Rwvx/DvPGwGAemxaYI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622824119674368.1650212875943; Fri, 4 Jun 2021 09:28:39 -0700 (PDT) Received: from localhost ([::1]:43832 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCgY-0005rW-EH for importer@patchew.org; Fri, 04 Jun 2021 12:28:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48540) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCHy-0008Ec-B9 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:17 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:45608) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHZ-0005nE-DO for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:10 -0400 Received: by mail-wm1-x335.google.com with SMTP id v206-20020a1cded70000b02901a586d3fa23so1629616wmg.4 for ; Fri, 04 Jun 2021 09:02:48 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id s62sm9232329wms.13.2021.06.04.09.02.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:43 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 502211FFD2; Fri, 4 Jun 2021 16:53:20 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1M9DSMG90oxpkIftDhmS6X3YTXP3prGe70gnCR2W/W0=; b=zqBSpXrVgFZHYH3MLkjTX40nmjnrTG1dVG15IOZoP5dtK/dTwoU1jDxFRaYDKemzjC MDqy4P4LuUHz2d5UIuYPPW32W/5YTO1VP426Uh3Fi/MF6mqHWvHloBrAktplt+UJcyTa LJLwC820GlaD1qcJsIwWs2wz9xZdgA2d1JDUAzn4J2pDppTmSWWqWE5n09urgB1qjOTF j62jYZqYHOVjaSGVZyEs/BiG0zUyg66K3o8IlXeWfrtmQM8QvdanolHWNYiS2EE/RK0i cWBwB4HUPVu/ig3J8CPLA/aqoc6BnjR3DoTtP7hlmWNwOmCHyCg/lDO8sMMKGPdKSaYr TvbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1M9DSMG90oxpkIftDhmS6X3YTXP3prGe70gnCR2W/W0=; b=GsDEQTcRCNCz7zFUMhbHXxRqGoMtw/w3HbO1TGvQEGrHcQg2XwyqC4d6RinViB1Wyz +8LwVhvy9RSPR8/qFJ2JPeeRC5stZG7jtJKy3cK4p4a8H2g9XR03gJxgXulh0pd82i5V W0jqEmAuXvtvCeLwx8QXtGibIwpxf7vFUjHSz0ShLRW6VuKZFKWM3W1FONAdC2cryv/K SVRHd6bJqIfhc2OizxQrHqZ894Pdj/2zrHUk6+8ua8hBwbDrtz3pPjmhKyK3jZMoqhYR MfumONqaCOe3mKgtLeI7bRiSt9gB4CDdxsd0rmfwDLgg0rfLno4D14eg1KEpd7BVhl4s TTFw== X-Gm-Message-State: AOAM531VYAU0NJxJmC4riQ0nRSr/E2vOfyRMu9EZ22dLHRTo9rjF4M3y LW0MQZcyYrfdKqNRk6Urk3iXYg== X-Google-Smtp-Source: ABdhPJy5aJgTGsOdveDkCgsncsCH+sOgaRzZourWPm1MjJO5O+aRBnWWy/2e1OAHrWvsZGu/6wuheQ== X-Received: by 2002:a7b:c041:: with SMTP id u1mr4237576wmc.95.1622822567983; Fri, 04 Jun 2021 09:02:47 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 61/99] target/arm: remove broad "else" statements when checking accels Date: Fri, 4 Jun 2021 16:52:34 +0100 Message-Id: <20210604155312.15902-62-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Stefano Stabellini , Julien Grall , Olaf Hering , qemu-arm@nongnu.org, Claudio Fontana , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana There might be more than just KVM and TCG in the future, so where appropriate, replace broad "else" statements with the appropriate if (accel_enabled()) check. Also invert some checks for !kvm_enabled() or !tcg_enabled() where it seems appropriate to do so. Note that to make qtest happy we need to perform gpio initialization in the qtest_enabled() case as well. Hopefully we do not break any Xen stuff. Signed-off-by: Claudio Fontana Cc: Julien Grall Cc: Stefano Stabellini Cc: Olaf Hering Cc: Alex Benn=C3=A9e Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu.c | 9 +++++---- target/arm/cpu64.c | 9 +++++---- target/arm/machine.c | 18 ++++++------------ 3 files changed, 16 insertions(+), 20 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7e3726ff00..57f975f5dc 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -37,6 +37,7 @@ #endif =20 #include "sysemu/tcg.h" +#include "sysemu/qtest.h" #include "kvm/kvm_arm.h" #include "disas/capstone.h" #include "fpu/softfloat.h" @@ -564,7 +565,7 @@ static void arm_cpu_initfn(Object *obj) * the same interface as non-KVM CPUs. */ qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); - } else { + } else if (tcg_enabled() || qtest_enabled()) { qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); } =20 @@ -741,14 +742,14 @@ void arm_cpu_post_init(Object *obj) ? cpu_isar_feature(aa64_fp_simd, cpu) : cpu_isar_feature(aa32_vfp, cpu)) { cpu->has_vfp =3D true; - if (!kvm_enabled()) { + if (tcg_enabled()) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_propert= y); } } =20 if (arm_feature(&cpu->env, ARM_FEATURE_NEON)) { cpu->has_neon =3D true; - if (!kvm_enabled()) { + if (tcg_enabled()) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_neon_proper= ty); } } @@ -849,7 +850,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **err= p) * We have not registered the cpu properties when KVM * is in use, so the user will not be able to set them. */ - if (!kvm_enabled()) { + if (tcg_enabled()) { arm_cpu_pauth_finalize(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a8ff1994ca..e3d818275c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -24,6 +24,7 @@ #include "cpu.h" #include "cpu32.h" #include "qemu/module.h" +#include "sysemu/tcg.h" #include "sysemu/kvm.h" #include "kvm/kvm_arm.h" #include "qapi/visitor.h" @@ -297,7 +298,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) */ bitmap_andnot(tmp, kvm_supported, cpu->sve_vq_init, max_vq); bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); - } else { + } else if (tcg_enabled()) { /* Propagate enabled bits down through required powers-of-two.= */ for (vq =3D pow2floor(max_vq); vq >=3D 1; vq >>=3D 1) { if (!test_bit(vq - 1, cpu->sve_vq_init)) { @@ -334,7 +335,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) "vector length must be enabled.\n"); return; } - } else { + } else if (tcg_enabled()) { /* Disabling a power-of-two disables all larger lengths. */ if (test_bit(0, cpu->sve_vq_init)) { error_setg(errp, "cannot disable sve128"); @@ -416,7 +417,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) } return; } - } else { + } else if (tcg_enabled()) { /* Ensure all required powers-of-two are enabled. */ for (vq =3D pow2floor(max_vq); vq >=3D 1; vq >>=3D 1) { if (!test_bit(vq - 1, cpu->sve_vq_map)) { @@ -610,7 +611,7 @@ static void aarch64_max_initfn(Object *obj) =20 if (kvm_enabled()) { kvm_arm_set_cpu_features_from_host(cpu); - } else { + } else if (tcg_enabled()) { uint64_t t; uint32_t u; aarch64_a57_initfn(obj); diff --git a/target/arm/machine.c b/target/arm/machine.c index 595ab94237..4acdccc22d 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -638,9 +638,11 @@ static int cpu_pre_save(void *opaque) =20 if (tcg_enabled()) { pmu_op_start(&cpu->env); - } - - if (kvm_enabled()) { + if (!write_cpustate_to_list(cpu, false)) { + /* This should never fail. */ + abort(); + } + } else if (kvm_enabled()) { if (!write_kvmstate_to_list(cpu)) { /* This should never fail */ abort(); @@ -651,11 +653,6 @@ static int cpu_pre_save(void *opaque) * write_kvmstate_to_list() */ kvm_arm_cpu_pre_save(cpu); - } else { - if (!write_cpustate_to_list(cpu, false)) { - /* This should never fail. */ - abort(); - } } =20 cpu->cpreg_vmstate_array_len =3D cpu->cpreg_array_len; @@ -754,13 +751,10 @@ static int cpu_post_load(void *opaque, int version_id) */ write_list_to_cpustate(cpu); kvm_arm_cpu_post_load(cpu); - } else { + } else if (tcg_enabled()) { if (!write_list_to_cpustate(cpu)) { return -1; } - } - - if (tcg_enabled()) { hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); =20 --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622824942; cv=none; d=zohomail.com; s=zohoarc; b=F62fNgF07aA0znpwGRq5OIwXioE+DJK6Afu8anavmPc5VJ2Ub2uUw1tbJRa6pvVYeVB3kr4kftAdEs40Yma0x6OYOdMHodiOrJNrj3GN4J8+pkqOGCosE3e7ZDBTysPqWngFVPrVvwLDShCGcoGiPFqwjOqIXyju5eMpBGHCba4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622824942; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eiyi2LcRkeghzxLmudkb7UCv7ec33DEm9YuMgjwgL/o=; b=F3Bd0GOJ6vfsL49mxVZblE7DTt+ihl4lJYJXW3+U37HTeR/KNPBNaar9uFG7EP/embosPjMllcYOm2d8ULRI4bymh3xoEIeQsaVPDDR7lBvykZKqXqNFugNwdh58LtEtZ86n/ButSaR0TpUPPiV6KZY+iF3hjtLr/FiaFILm1/g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622824942849634.8585397847605; Fri, 4 Jun 2021 09:42:22 -0700 (PDT) Received: from localhost ([::1]:57518 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCtp-0001GP-Po for importer@patchew.org; Fri, 04 Jun 2021 12:42:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48536) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCHy-0008Eb-Ac for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:17 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:40492) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHa-0005np-SF for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:09 -0400 Received: by mail-wm1-x32f.google.com with SMTP id b145-20020a1c80970000b029019c8c824054so8223358wmd.5 for ; Fri, 04 Jun 2021 09:02:50 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id l16sm9378070wmj.47.2021.06.04.09.02.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:43 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 644F61FFD3; Fri, 4 Jun 2021 16:53:20 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eiyi2LcRkeghzxLmudkb7UCv7ec33DEm9YuMgjwgL/o=; b=vacE7HdjcpWPgUumrSNZEOF3qw07fr8B1Qu26YUcXuDLeqDZ0e1Qkt8ZO1TxFI1AqD y7XXzcXx2vaUqDrxko6A/BIRc9PEUGryjoLx8yLgBPYdEess0deUWI0j0vrH75CUj/Si ENV2+/aOkQiOmGIrMzBwUUnFJ2odvZc3gj6slnbi1pU6qXC8LzNDcSPRvp8yyRPuuYJ1 TJOSIQdDBDPW7A3Wk7OOMADWxho4OBUQElUoz4RIpBsjLAsb/pfBxBP9JAMDjCiThSwG jqJH/MuqkHnOVOXMAOIp0fp5lpK4ZbVOYdyFV+5EGmkQSv+oNCnguZDUNwcwj/dHiGxv /P3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eiyi2LcRkeghzxLmudkb7UCv7ec33DEm9YuMgjwgL/o=; b=T8xFFjvyINkTOnCW6yIqhe7m7TH7cgovdzMuc2bMCmP0nvQQC7bzqSnIzyWl8qrLAM siTsWUR1KsW2ElRYE66pZXrwupATGvFT0IgwpmTpQx++8TB8sSZjAWNVg6XBDSPaot6L /YChFGv7DeF94ANsqybBDFMFg2scVBWEGeCiu34km9nIPinKIfIlu+fMmaGJFs+YrvS2 ypcWrJZ/9fRPm7vx21uI27A31zkdAynDsO0Ga7+FDAxCuPTtutSVrMhPgm7kthbvSDjF AemXwMgVEez1o2q8pJEKM9xp3a/MIJGVGhZIkVsQEACI0We/t0mRwFJM/Y9wZLCJhXEz /myQ== X-Gm-Message-State: AOAM533PRTmZawQslD0ZE/cgUHfRIV96iCl/rwQ2bGwh/WZWaXy0Sni1 xb+9ruy03skW9Yad4ddC8UaCfw== X-Google-Smtp-Source: ABdhPJz3IqEecahNg5ErsLEktyvWhgf83rsd8EhhgL+rsVqMebH8qTatk4L7yNEr6FnYRfg7rfDcYQ== X-Received: by 2002:a05:600c:35c8:: with SMTP id r8mr3262410wmq.168.1622822569577; Fri, 04 Jun 2021 09:02:49 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 62/99] target/arm: remove kvm-stub.c Date: Fri, 4 Jun 2021 16:52:35 +0100 Message-Id: <20210604155312.15902-63-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana the functions used in machine.c are now protected via if (kvm_enabled()), so the stub is not needed. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/kvm-stub.c | 24 ------------------------ 1 file changed, 24 deletions(-) delete mode 100644 target/arm/kvm-stub.c diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c deleted file mode 100644 index 56a7099e6b..0000000000 --- a/target/arm/kvm-stub.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * QEMU KVM ARM specific function stubs - * - * Copyright Linaro Limited 2013 - * - * Author: Peter Maydell - * - * This work is licensed under the terms of the GNU GPL, version 2 or late= r. - * See the COPYING file in the top-level directory. - * - */ -#include "qemu/osdep.h" -#include "cpu.h" -#include "kvm_arm.h" - -bool write_kvmstate_to_list(ARMCPU *cpu) -{ - abort(); -} - -bool write_list_to_kvmstate(ARMCPU *cpu, int level) -{ - abort(); -} --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622828452; cv=none; d=zohomail.com; s=zohoarc; b=MVyk9qZT/ErX12FcMEdVJo/qbLyWRYCSZUNzpYqaaJDmI45y5+/7Htj+hYr1oGVZYQDuD6olsfUMnrPLWgmXTetUYtdL4lVYqC5rxxZevXxv6/mgQos7ZB81+MAQpjlEg+2EiH8IlSrGOFYS/6lJMphlBI2Aqtr7+fyL6dkygzg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622828452; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=N2NTbq9Py2mVkZ2OrcWx1tG3NJj+ueFdRocasaLiPrE=; b=KxrskfaYrUDgVKDtAdWOwogkijeeqStefZ911VEhg+oYOwylavqvhqvTjVww4hdRM3hkDAyWg1u6IFfaXkuWxqW1gWHcIsAeE43uuhe/wSvXU6uOOwLZJrNWOy2WdEfLoHk1PzGsySY8pInypw7rGLxRl+u4cydz7Tj5xZQrhEc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622828452099656.3073130241246; Fri, 4 Jun 2021 10:40:52 -0700 (PDT) Received: from localhost ([::1]:58646 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDoR-0003OT-14 for importer@patchew.org; Fri, 04 Jun 2021 13:40:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48894) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpDNR-0000C7-2p for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:57 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:39727) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpDNO-00026v-8d for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:56 -0400 Received: by mail-wr1-x42a.google.com with SMTP id l2so10038506wrw.6 for ; Fri, 04 Jun 2021 10:12:53 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id s7sm22532wmh.38.2021.06.04.10.12.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 10:12:46 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 79E9F1FFD4; Fri, 4 Jun 2021 16:53:20 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N2NTbq9Py2mVkZ2OrcWx1tG3NJj+ueFdRocasaLiPrE=; b=K6Ipp5UbFGTiZ7yJ0xV0HroliU+7IgUEBKIVe9AxjeCP+A/5S7bLlSk3dic9g3/NHw Ros0hQNEjdNBVKIQEsoiTXb6qE5L2IOt6yw0nedPoudxYQmbF7pCNl9zLTCCh32jJSiQ JZzMwjkZRY6AMGaiQoJKdgPUKpqziwfaLx7ICKuVwbf0p6ikA7JBmQKluzhxE4nc2jTN ZpGjjO6HM8DmAng9D3rQEBwCFXaVa5ofnGfsnOBHQrFONgBX6a2v5pd/q7gE9G6O6DV9 ir52Yz0/pLd2EhnkMwjXaAW0Yll2zqOEQlZAnuxZLq3FvzCOG7d1eU8ENSkWZfcxphhf YTXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N2NTbq9Py2mVkZ2OrcWx1tG3NJj+ueFdRocasaLiPrE=; b=CuCEYwHt2xSkYrr8F0BvyzWFtb5wx2xIQFqww4XRUFV4fnUjTcr/n8DpiE37Fa/PsQ fK8tE/CwyiyPb8ZpaCjk1JzdXRaueX82QeKE7rG4s7Nyely94ZlqSRYgmuA8v7f/Jtra tmo9WCGZdJI6M/JfUATBi0XIIpZkR0ngfkMpzcAfWklYZJeUq4vzdTir9GlP8RiPxqd+ Sud4tQ79zJjO5oY/V055kd4sD0QB8+3K/xPB4+dNYkriLoBuh4Je7Xczf2axl3+cUPIJ Wur9zzndnOpJXfWvGig6Xp7hHnEEcyM35lcWuQct48UdZ6r43ViGI7Orxpp2ciEcwgkw I0Qg== X-Gm-Message-State: AOAM533gS/HKHR3dvnTUdzmfTgX4a1RE1PYM4baJ8gSFn+f0cLbGgoy5 ziyJH94IwNhz+eNYonyTiY8fAg== X-Google-Smtp-Source: ABdhPJwPL829SA5abXI/tMRr3J/KLRiieXqWC2Hr2beErYmFIXgVCimpH2A5fuqIU6HGsYbj6kwgdg== X-Received: by 2002:adf:f1c3:: with SMTP id z3mr4807739wro.375.1622826772968; Fri, 04 Jun 2021 10:12:52 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 63/99] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM Date: Fri, 4 Jun 2021 16:52:36 +0100 Message-Id: <20210604155312.15902-64-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Michael S. Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Claudio Fontana , Igor Mammedov , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana test is TCG-only. Signed-off-by: Claudio Fontana Cc: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Alex Benn=C3=A9e --- tests/qtest/bios-tables-test.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 762d154b34..f8fe4b8efe 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -1484,6 +1484,13 @@ static void test_acpi_oem_fields_virt_tcg(void) }; char *args; =20 +#ifndef CONFIG_TCG + if (data.tcg_only) { + g_test_skip("TCG disabled, skipping ACPI tcg_only test"); + return; + } +#endif /* CONFIG_TCG */ + args =3D test_acpi_create_args(&data, "-cpu cortex-a57 "OEM_TEST_ARGS, true); data.qts =3D qtest_init(args); --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622823907; cv=none; d=zohomail.com; s=zohoarc; b=f0LQLQ+zH5AoYd0d7H/uUSfFlxt3DZFbtEYFNGmkB4S7nCbOnbzOuQvmhFs/RONXgqkUpjQtvQon258If8vOf9G+ffDmf+AYa9DTIlEZJbgTLWPLSrFxHkdhuYwLBALTOj07M8Kv4z7yI0ksggXoSuJwJbV+HStC3aQvgUFToV8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622823907; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TnqsqRW/fHAwL8iPmUyBN5YIVqEFRjRPuxkbEMdWync=; b=SBqUEAhP7W1tRyBpnW9A5PtOWTIYswc7JdSPMS2ZkPMxnsSwLrt8g6cGyEMYjBkIOh2gnVxs529y7gsNkBEoGmXsRkcku/5kvCRV0czAic70CnAGK4eAZOCVieVSUT78X2He7ZGwfPzImnzi2v6IqoI75T6P+6AvtqlQIAZkohs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622823907441819.8657752581175; Fri, 4 Jun 2021 09:25:07 -0700 (PDT) Received: from localhost ([::1]:58556 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCd8-00058c-Nk for importer@patchew.org; Fri, 04 Jun 2021 12:25:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48770) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCIJ-0000G7-G8 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:35 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:46651) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHo-0005vq-P7 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:35 -0400 Received: by mail-wm1-x331.google.com with SMTP id h22-20020a05600c3516b02901a826f84095so930629wmq.5 for ; Fri, 04 Jun 2021 09:03:02 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id t12sm9136988wre.9.2021.06.04.09.02.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:56 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 8F3BB1FFD5; Fri, 4 Jun 2021 16:53:20 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TnqsqRW/fHAwL8iPmUyBN5YIVqEFRjRPuxkbEMdWync=; b=lpGMZm1z7Q59Kou8ERYOuxJzhfCJ2ybQ8LuqQ83XyL89sjceMcIOq0bUKHr+t9Y8lI JpTjWl88OiHfUIg1h1J7xv0Z8hjeJ2Bzld2ebaOZeRVtGcUllUeeUkLSEceuA8xEv5y8 bwOsoEbBHmAyL6y48+gLtmEOnTUBV4TCu0aj6SEzeWq6tg6D29AamOr6n9OIiX97eUYI +FoOxac3NGbiJm9WP/wwcv/GDMp8oc8G1UGQqRO+ZSVbW0tmJ9x3eKBLONHrjDGcaTdM Y2IGJbDd3RORrUWGD9pqfKDdum+LJR5gI4O2BLLE+S5OjsildKVP4ahyUNdQxmHE1OEf OV8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TnqsqRW/fHAwL8iPmUyBN5YIVqEFRjRPuxkbEMdWync=; b=GaN44UDc8F749cofwL4djFoGk9mBGqLbMGBWqeBpScbDB9JYMW17j8tCv2QIcpIWmb MW8lifomv5rHrKiXhhXa17DK3ddPff8rqfwUGS5EFWwcvF/hO68nLZ1MODMi8zaKHL2L pkhAiVlu589DRr97A8emj9o9WwoJCU0ZQLY9x1lPGgwps1jYscseBPKONlxvM6gXxgj2 oxEmu6vScFC9Xp0+EPdJS53bWoWh5Jp8zNMprNx30yAVjxUCPcpUMInIbbf8wQhcroCq 0fr8NZozwyjXz2TRsbW9QxLG6L5IF0Bte6f5nEERLVq5jWUsb27rUFYGcf4YFo9CVWQz n1kA== X-Gm-Message-State: AOAM531dP5BevD5VsstGaotgsQD5U16tWZ+psoBJd9CnXQl8++AEAemR gEAqsHsZf5hs883Mqf2ED/FsPg== X-Google-Smtp-Source: ABdhPJyR5nzlyugXf2Fb94Arj1xmAmhiPXh/YhDi6VmBuZ427SOIu5kLyk+DmstrEHzykdb75Y0+ag== X-Received: by 2002:a7b:c852:: with SMTP id c18mr4315206wml.16.1622822581304; Fri, 04 Jun 2021 09:03:01 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 64/99] tests: do not run test-hmp on all machines for ARM KVM-only Date: Fri, 4 Jun 2021 16:52:37 +0100 Message-Id: <20210604155312.15902-65-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , "Dr. David Alan Gilbert" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Claudio Fontana , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana on ARM we currently list and build all machines, even when building KVM-only, without TCG. Until we fix this (and we only list and build machines that are compatible with KVM), only test specifically using the "virt" machine in this case. Signed-off-by: Claudio Fontana Cc: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Alex Benn=C3=A9e --- tests/qtest/test-hmp.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/tests/qtest/test-hmp.c b/tests/qtest/test-hmp.c index 413eb95d2a..1d4b4f2f0e 100644 --- a/tests/qtest/test-hmp.c +++ b/tests/qtest/test-hmp.c @@ -157,8 +157,28 @@ int main(int argc, char **argv) =20 g_test_init(&argc, &argv, NULL); =20 + /* + * XXX currently we build also boards for ARM that are incompatible wi= th KVM. + * We therefore need to check this explicitly, and only test virt for = kvm-only + * arm builds. + * After we do the work of Kconfig etc to ensure that only KVM-compati= ble boards + * are built for the kvm-only build, we could remove this. + */ +#ifndef CONFIG_TCG + { + const char *arch =3D qtest_get_arch(); + + if (strcmp(arch, "arm") =3D=3D 0 || strcmp(arch, "aarch64") =3D=3D= 0) { + add_machine_test_case("virt"); + goto add_machine_test_done; + } + } +#endif /* !CONFIG_TCG */ + qtest_cb_for_every_machine(add_machine_test_case, g_test_quick()); + goto add_machine_test_done; =20 + add_machine_test_done: /* as none machine has no memory by default, add a test case with memo= ry */ qtest_add_data_func("hmp/none+2MB", g_strdup("none -m 2"), test_machin= e); =20 --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622827023; cv=none; d=zohomail.com; s=zohoarc; b=YaVVfeNBRUkrNnSDAFkWdVraHEF1I0UeuH3qR8MwN9obyGb42EWqRWi63IeSbiDs/Tag3kwoTMY+f3j82TATsoHdxrlC7m1XPNU9kav35lLyYQ6gqGWY6IBTpo4cfhkdjmEwdvtZilS35yh4JOMYYZglFJk+EPYYKiKYkUU7qoA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622827023; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fVwtDg6NmbYUbWbKcWKwD4v1KnbubfIiGX4wXK52zzM=; b=H3jO9amSE69JWd5l/EuK5LroZnXS1S2Ovvg05q7rp4tCQ+vqQn3bmgfPAkzZFYcxxlK0a1N9dHfu5Sq8psB8p6mf9P1MKoIuRfcqzIkbtkjyTDoR1Boz8yEuRQXwsLdNfdVuY+Z/M/+IhjUQ+GYOrXJSmopDjfIcMt9hmRcJg1s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622827023198781.9071649901449; Fri, 4 Jun 2021 10:17:03 -0700 (PDT) Received: from localhost ([::1]:37994 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDRO-0000b4-FZ for importer@patchew.org; Fri, 04 Jun 2021 13:17:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48698) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpDNJ-000860-Fh for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:49 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:43792) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpDNH-00023E-Fr for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:49 -0400 Received: by mail-wm1-x335.google.com with SMTP id 3-20020a05600c0243b029019f2f9b2b8aso6011193wmj.2 for ; Fri, 04 Jun 2021 10:12:44 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id r4sm2614512wrt.26.2021.06.04.10.12.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 10:12:38 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A55A01FFD6; Fri, 4 Jun 2021 16:53:20 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fVwtDg6NmbYUbWbKcWKwD4v1KnbubfIiGX4wXK52zzM=; b=OLH7eO1BVxQh5ug2adTu2a83X1SkMbpcY1UBwmeZ1id1G8thQFyPecmAOGW+PujpY9 UY6BDvhqOYbxj8sjZ0WpvNvJ5sC1/b8L0TEe8PdX4Oa+gyTFnvftb/YSlOx01C0bfR5y gBr7U5PidbWbwR3359Fy2SOMdw+WHNTo14koav2SLGiSd4Ow7cASXq13rmVjvMkwsTI/ 9SRdrg+rK/yvjXyP06u24oYW/4DhqsVCBoifC4JBctypNLOUZxYJwSh8N43ZjTxL4AE4 7DbWU5gg4Ixa7jV6vjaMBQXGnXvWxCM0C5PctPIYFQVm8KgFblPB7tv0tg/zrmnsefr2 LqIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fVwtDg6NmbYUbWbKcWKwD4v1KnbubfIiGX4wXK52zzM=; b=k7YFZMNjkZjfTnSPX7DzvyRngpuQFpNiIUGNY+VD7wp+pOgMWAIL2d2YPsjW+Dxnvc 0QtSDPJJvx3SfQo4OG9L50NhIMGw4Y6ONk/Tzp1U9RJJuXZE7xoOj1unWHR8ZX8nKGvU W2LfQkBFkhpGk4ZEFQ4P0zT1ZHsWrqaBNdibad0zw95yqpx5q2H5gupR3Prl92WwgVHa CBaWkqmFz31sLDFEg3uTHyQ2XenI2xF+MI8V9p0qIThQHwuN04kQq9lQRD0MCNcDywoN DI56VjmgmIL8WE91k7Ua6Sg/h90xSSRF2gg80bCbSEotgo6itRMPPhJKOGZOfJ8tFIQT 5bgg== X-Gm-Message-State: AOAM533jf8r7zBUjN2ySrGpSDKD3XTNfDMbQLYGOjq2QdK9OldUJoQYq z+4Q/7vwp+LRYthfBuhZmbgu6Q== X-Google-Smtp-Source: ABdhPJzqmFc5Sye3awnzV+RZLn3bmLsb4kOEj0HE/lNSpyDqm+m8JYKlPFdLlVAoFyTooJ83MVfiqQ== X-Received: by 2002:a1c:6004:: with SMTP id u4mr4668413wmb.110.1622826763890; Fri, 04 Jun 2021 10:12:43 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 65/99] tests: device-introspect-test: cope with ARM TCG-only devices Date: Fri, 4 Jun 2021 16:52:38 +0100 Message-Id: <20210604155312.15902-66-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Claudio Fontana , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana Skip the test_device_intro_concrete for now for ARM KVM-only build, as on ARM we currently build devices for ARM that are not compatible with a KVM-only build. We can remove this workaround when we fix this in KConfig etc, and we only list and build machines that are compatible with KVM for KVM-only builds. Alternative implementation provided by Alex. Suggested-by: Alex Benn=C3=A9e Signed-off-by: Claudio Fontana Cc: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Alex Benn=C3=A9e --- tests/qtest/device-introspect-test.c | 32 +++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/tests/qtest/device-introspect-test.c b/tests/qtest/device-intr= ospect-test.c index bbec166dbc..cb8bf6e37d 100644 --- a/tests/qtest/device-introspect-test.c +++ b/tests/qtest/device-introspect-test.c @@ -305,6 +305,24 @@ static void test_abstract_interfaces(void) qtest_quit(qts); } =20 +/* + * XXX currently we build also boards for ARM that are incompatible with K= VM. + * We therefore need to check this explicitly, and only test virt for kvm-= only + * arm builds. + * After we do the work of Kconfig etc to ensure that only KVM-compatible = boards + * are built for the kvm-only build, we could remove this. + */ +static bool skip_machine_tests(void) +{ +#ifndef CONFIG_TCG + const char *arch =3D qtest_get_arch(); + if (strcmp(arch, "arm") =3D=3D 0 || strcmp(arch, "aarch64") =3D=3D 0) { + return true; + } +#endif /* !CONFIG_TCG */ + return false; +} + static void add_machine_test_case(const char *mname) { char *path, *args; @@ -329,11 +347,15 @@ int main(int argc, char **argv) qtest_add_func("device/introspect/none", test_device_intro_none); qtest_add_func("device/introspect/abstract", test_device_intro_abstrac= t); qtest_add_func("device/introspect/abstract-interfaces", test_abstract_= interfaces); - if (g_test_quick()) { - qtest_add_data_func("device/introspect/concrete/defaults/none", - g_strdup(common_args), test_device_intro_concr= ete); - } else { - qtest_cb_for_every_machine(add_machine_test_case, true); + + if (!skip_machine_tests()) { + if (g_test_quick()) { + qtest_add_data_func("device/introspect/concrete/defaults/none", + g_strdup(common_args), + test_device_intro_concrete); + } else { + qtest_cb_for_every_machine(add_machine_test_case, true); + } } =20 return g_test_run(); --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622828180; cv=none; d=zohomail.com; s=zohoarc; b=iWq+yKi7KV8xCsMiVS/3uicfdBRTdCTJpO+ZTPSbSg1xsr/rbwozAwQ3kr7Vp4cMo+HDx/mrbMZsSOjsViMwnFyvdtM5NZpDHIZOdv92bJagBTV8BUaYh1cq8dBzIK1XFHQOFRqktl70dcolk092E64YxuhSVEcM+4hb95eKDtE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622828180; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=o/tJR1h7wyxWfcVFJmfREs1+Cr3yNNSSbrFc5jF6cQA=; b=B/K+i6izvkq6PFw6RNIKjRxzh/I1r6SgUde7WJD5FJw0JbweDp7kBs7urnVxV/B1tdotX19oH5pu64ZfnJ19POi62bUdV0MvnHnKuY/dXwb60C0KyyEOYlWDZLk57HnZ4TA+4gACTwUx/HVndqvjf/J8sYrB6E1qRVaXkqr1EB8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622828180869320.5801625020367; Fri, 4 Jun 2021 10:36:20 -0700 (PDT) Received: from localhost ([::1]:45026 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDk3-0002e2-Hf for importer@patchew.org; Fri, 04 Jun 2021 13:36:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48694) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpDNJ-00085O-9j for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:49 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:44968) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpDND-000221-DN for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:49 -0400 Received: by mail-wr1-x42b.google.com with SMTP id f2so9990706wri.11 for ; Fri, 04 Jun 2021 10:12:42 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id 92sm7893175wrp.88.2021.06.04.10.12.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 10:12:38 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id BB9381FFD7; Fri, 4 Jun 2021 16:53:20 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=o/tJR1h7wyxWfcVFJmfREs1+Cr3yNNSSbrFc5jF6cQA=; b=F17fSk9tH+3glWMuB2pYiu12CQG/zDLd2tnt+EnAyX0IeSqzDIoPv5mfOure8ZXVyR Qp10cis8SUg8o9kwLqvxVS3SCMQFHUr0jktZeV6PkaVY0Y1eyIo5IUaiCHbnZhav08oS qlWW2DjOA6O70OXL/PV4fPVS6M9pzdTBwVcmQ+cRuM40JHH9jqeaxJAbmQUJPn+7ubrK VRkSRdf2fAdSmBsCDp7b5qX39ZCZcTAuHGzeH+yywdAJAXpIOZ1nFcdZSLYVRpYqO5Mr DlgDZk72YXd236CeJ18iePRpmkpOSVL7VeUQdlDGtZBE8dEqBFvuiaU779ZW4bJ07vzo G2sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o/tJR1h7wyxWfcVFJmfREs1+Cr3yNNSSbrFc5jF6cQA=; b=Uxg7vX5/ZClQv+RK2NQZl+d4B6EJT/rd44ANFkoaFlbziEGfhBlbg+xVohg30+Ieav FFMkV8gEU6TlVFLlZsAC/yGMOoubzDNsqd1UvI6PcUo14fwy4v7ytfYOULk0Y0SD4sUG CGo1IsV7BT+1Vr0ONppHdyi2IlDgV/okniw9IU0PmGiOVngfQecLAl10geeJFBAJx2aS m1bhbsy437MsYYul65ahWddOHd8PESPlfrzAkFUjTf8hTo6JNwXGGmi7Pt+Bvh3L6Nkw kIbjWxa1uQD4dxgiD8j2dWM6SxDiFkFIHsmhWf6d/h3CBN4TrmFQCou4TRKHlpVsQmNg urkw== X-Gm-Message-State: AOAM532NPpJCr5bH6QbbcXZjKNDFxfDWlK16+5L7yg8H6zJA8m+raohX e/Ov5cmBw6/Byq0lDmeTQVDb4JYBynE5xQ== X-Google-Smtp-Source: ABdhPJyDeD1zN6fJc3JKD9SywbNY00He/tlkwmdX/RiIdS3Cnttnnc/MxMJr1qWoLx7+p58lF0hb0w== X-Received: by 2002:adf:e54f:: with SMTP id z15mr4970797wrm.141.1622826761870; Fri, 04 Jun 2021 10:12:41 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 66/99] tests: do not run qom-test on all machines for ARM KVM-only Date: Fri, 4 Jun 2021 16:52:39 +0100 Message-Id: <20210604155312.15902-67-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Claudio Fontana , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana on ARM we currently list and build all machines, even when building KVM-only, without TCG. Until we fix this (and we only list and build machines that are compatible with KVM), only test specifically using the "virt" machine in this case. Signed-off-by: Claudio Fontana Cc: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Alex Benn=C3=A9e --- tests/qtest/qom-test.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/tests/qtest/qom-test.c b/tests/qtest/qom-test.c index eb34af843b..b0a6d10148 100644 --- a/tests/qtest/qom-test.c +++ b/tests/qtest/qom-test.c @@ -90,7 +90,27 @@ int main(int argc, char **argv) { g_test_init(&argc, &argv, NULL); =20 + /* + * XXX currently we build also boards for ARM that are incompatible wi= th KVM. + * We therefore need to check this explicitly, and only test virt for = kvm-only + * arm builds. + * After we do the work of Kconfig etc to ensure that only KVM-compati= ble boards + * are built for the kvm-only build, we could remove this. + */ +#ifndef CONFIG_TCG + { + const char *arch =3D qtest_get_arch(); + + if (strcmp(arch, "arm") =3D=3D 0 || strcmp(arch, "aarch64") =3D=3D= 0) { + add_machine_test_case("virt"); + goto add_machine_test_done; + } + } +#endif /* !CONFIG_TCG */ + qtest_cb_for_every_machine(add_machine_test_case, g_test_quick()); + goto add_machine_test_done; =20 + add_machine_test_done: return g_test_run(); } --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622826693; cv=none; d=zohomail.com; s=zohoarc; b=P+BLB1A40Do/ZlQKz43G7dHFj5P+IzeCtv2Kw2taJqc4Ae0Cs6fNDOTrHSiAYuOOk3qKJEc0h6r2nJG3mMWlVR+Il6Q2o45NVP44Tc1+J1pdehAMyayDFaPKS35gBnGRD+w1PMjmVd1ud5+XXZjjN07HVhtq32gb5heZm5wNQTc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622826693; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VxtZzAI4CoksM/sdPCcSUcUhaEvNzz/ZBq2sF1VS0fg=; b=KOi+/3r/fTOTCI/6sHO1UTDIuuCI9w22h1E01Fiqa+Vay8nEAKWcpoG7iq6kkRSp4/egVoTf+I2UPzGbXm0LWwvafrPfeT3GVC10z9gd7jqA/zfaBBwIDlgiYlABd9dqiQrFZ5nftD/EYi9Me1hZcptxxknz/Lo62jd8Mozk/Jk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622826693641671.2803617624286; Fri, 4 Jun 2021 10:11:33 -0700 (PDT) Received: from localhost ([::1]:47572 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDM4-0004Ho-Tn for importer@patchew.org; Fri, 04 Jun 2021 13:11:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33334) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCkY-00084E-5o for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:32:46 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:44624) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCkV-00026j-2d for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:32:45 -0400 Received: by mail-wr1-x42c.google.com with SMTP id f2so9882545wri.11 for ; Fri, 04 Jun 2021 09:32:42 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id g21sm7987458wrb.46.2021.06.04.09.32.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:38 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id DAD161FFD8; Fri, 4 Jun 2021 16:53:20 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VxtZzAI4CoksM/sdPCcSUcUhaEvNzz/ZBq2sF1VS0fg=; b=mmWyplAU8upfLswSrr+m05yMVAWbdOW3TAzzB6OOqRCpinTkj7rWSBHcX0TTPA85Qt qihUyS3q8WmsPwvmHceE15/Nm9NjJ6+aBTWBRYRNnteIwEB8QAcxwQj5Uv+36pG5NBHH g4g0Gd/9b5l8tgSDZUO8pCzMcJj7WC7fqHQ2Sfzn6Kdry1AMOvBWUYU7smdr67SJcbri raWrjfV8qAetNvuGeVSR2wUk5SHs5YBwuPp32RSDZ/ZdzPD52hbpWimak7z4iO651fly daGf5VCXVEU+sYqpSsjQajkeqoPd4OfMASmk8LN9ryl0xoWQliabbRcIzKprAOfjpxK0 7G/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VxtZzAI4CoksM/sdPCcSUcUhaEvNzz/ZBq2sF1VS0fg=; b=KEe9hUW+yInCByo0hu5BT6Czb6CoVJSsSJ0ss1MpU2gXXujgCMpZycfn9MK420UMMQ HTvFe2qhmQhDjy5mXMx5Gomgrw9ur84yDtj+xpAcD59kY0gbOlm8q4wiU/mqS6SLT7b8 hsigBwN/ctblzsEplKsCRQeFgrk6v5r8ncBi+UtuxS5Je/oH7p93K8JIRep7kNb6XyhE J0kELmBTObTC+MtKdKUdxTuCa0RWp9Jblou/Nvv0o9oZKfZNG6s4Oyo8xVva3UxfQPjx dE8hQ/zFhpNOu0RO52XQjOpAyBNK0UX4GKMsqQ4hRRro7A7DN5fZAK5DtgEnQkZtYD7B ujhg== X-Gm-Message-State: AOAM532LbVzMqAcCFiQqzbHYnRGvzCXKxRZPzJzgzAGNe7m8y3ysiwDJ aSXcnH5eBuFZvPaEhvL5WO1aKg== X-Google-Smtp-Source: ABdhPJzLSKYZwYVIi5dj2EnVUomz1ST+fL5MIYXzvpuOSYTJKoEnsFGvRsQNrFwzhxsdMXZc3tDaKg== X-Received: by 2002:a5d:4287:: with SMTP id k7mr4947896wrq.98.1622824361505; Fri, 04 Jun 2021 09:32:41 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 67/99] target/arm: create kvm cpu accel class Date: Fri, 4 Jun 2021 16:52:40 +0100 Message-Id: <20210604155312.15902-68-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana move init, realizefn and reset code into it. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/internals.h | 1 - target/arm/cpu-sysemu.c | 32 ---------- target/arm/cpu.c | 49 +++----------- target/arm/kvm/kvm-cpu.c | 128 +++++++++++++++++++++++++++++++++++++ target/arm/kvm/meson.build | 1 + 5 files changed, 137 insertions(+), 74 deletions(-) create mode 100644 target/arm/kvm/kvm-cpu.c diff --git a/target/arm/internals.h b/target/arm/internals.h index 227a80ec21..522596d15f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1165,7 +1165,6 @@ static inline uint64_t useronly_maybe_clean_ptr(uint3= 2_t desc, uint64_t ptr) =20 #ifndef CONFIG_USER_ONLY void arm_cpu_set_irq(void *opaque, int irq, int level); -void arm_cpu_kvm_set_irq(void *opaque, int irq, int level); bool arm_cpu_virtio_is_big_endian(CPUState *cs); #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c index 26467c640b..fff55311f4 100644 --- a/target/arm/cpu-sysemu.c +++ b/target/arm/cpu-sysemu.c @@ -24,7 +24,6 @@ #include "cpu.h" #include "internals.h" #include "sysemu/hw_accel.h" -#include "kvm/kvm_arm.h" #include "sysemu/tcg.h" #include "tcg/tcg-cpu.h" =20 @@ -72,37 +71,6 @@ void arm_cpu_set_irq(void *opaque, int irq, int level) } } =20 -void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) -{ -#ifdef CONFIG_KVM - ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; - CPUState *cs =3D CPU(cpu); - uint32_t linestate_bit; - int irq_id; - - switch (irq) { - case ARM_CPU_IRQ: - irq_id =3D KVM_ARM_IRQ_CPU_IRQ; - linestate_bit =3D CPU_INTERRUPT_HARD; - break; - case ARM_CPU_FIQ: - irq_id =3D KVM_ARM_IRQ_CPU_FIQ; - linestate_bit =3D CPU_INTERRUPT_FIQ; - break; - default: - g_assert_not_reached(); - } - - if (level) { - env->irq_line_state |=3D linestate_bit; - } else { - env->irq_line_state &=3D ~linestate_bit; - } - kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); -#endif -} - bool arm_cpu_virtio_is_big_endian(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 57f975f5dc..0ecbfa060c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -42,6 +42,7 @@ #include "disas/capstone.h" #include "fpu/softfloat.h" #include "cpu-mmu.h" +#include "qemu/accel.h" =20 static void arm_cpu_set_pc(CPUState *cs, vaddr value) { @@ -409,11 +410,6 @@ static void arm_cpu_reset(DeviceState *dev) &env->vfp.fp_status_f16); set_float_detect_tininess(float_tininess_before_rounding, &env->vfp.standard_fp_status_f16); -#ifndef CONFIG_USER_ONLY - if (kvm_enabled()) { - kvm_arm_reset_vcpu(cpu); - } -#endif =20 if (tcg_enabled()) { hw_breakpoint_update_all(cpu); @@ -560,12 +556,7 @@ static void arm_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY /* Our inbound IRQ and FIQ lines */ - if (kvm_enabled()) { - /* VIRQ and VFIQ are unused with KVM but we add them to maintain - * the same interface as non-KVM CPUs. - */ - qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4); - } else if (tcg_enabled() || qtest_enabled()) { + if (tcg_enabled() || qtest_enabled()) { qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4); } =20 @@ -809,6 +800,9 @@ void arm_cpu_post_init(Object *obj) } } #endif + + /* if required, do accelerator-specific cpu initializations */ + accel_cpu_instance_init(CPU(obj)); } =20 static void arm_cpu_finalizefn(Object *obj) @@ -878,16 +872,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) Error *local_err =3D NULL; bool no_aa32 =3D false; =20 - /* If we needed to query the host kernel for the CPU features + /* + * If we needed to query the host kernel for the CPU features * then it's possible that might have failed in the initfn, but * this is the first point where we can report it. */ if (cpu->host_cpu_probe_failed) { - if (!kvm_enabled()) { - error_setg(errp, "The 'host' CPU type can only be used with KV= M"); - } else { - error_setg(errp, "Failed to retrieve host CPU features"); - } + error_setg(errp, "The 'host' CPU type can only be used with KVM"); return; } =20 @@ -1486,26 +1477,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void= *data) arm32_cpu_class_init(oc, data); } =20 -#ifdef CONFIG_KVM -static void arm_host_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - kvm_arm_set_cpu_features_from_host(cpu); - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - aarch64_add_sve_properties(obj); - } - arm_cpu_post_init(obj); -} - -static const TypeInfo host_arm_cpu_type_info =3D { - .name =3D TYPE_ARM_HOST_CPU, - .parent =3D TYPE_AARCH64_CPU, - .instance_init =3D arm_host_initfn, -}; - -#endif - static const TypeInfo arm_cpu_type_info =3D { .name =3D TYPE_ARM_CPU, .parent =3D TYPE_CPU, @@ -1521,10 +1492,6 @@ static const TypeInfo arm_cpu_type_info =3D { static void arm_cpu_register_types(void) { type_register_static(&arm_cpu_type_info); - -#ifdef CONFIG_KVM - type_register_static(&host_arm_cpu_type_info); -#endif } =20 type_init(arm_cpu_register_types) diff --git a/target/arm/kvm/kvm-cpu.c b/target/arm/kvm/kvm-cpu.c new file mode 100644 index 0000000000..5fbb127e61 --- /dev/null +++ b/target/arm/kvm/kvm-cpu.c @@ -0,0 +1,128 @@ +/* + * QEMU ARM CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "cpu.h" +#include "hw/core/accel-cpu.h" +#include "qapi/error.h" + +#include "kvm/kvm_arm.h" +#include "internals.h" + +static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + uint32_t linestate_bit; + int irq_id; + + switch (irq) { + case ARM_CPU_IRQ: + irq_id =3D KVM_ARM_IRQ_CPU_IRQ; + linestate_bit =3D CPU_INTERRUPT_HARD; + break; + case ARM_CPU_FIQ: + irq_id =3D KVM_ARM_IRQ_CPU_FIQ; + linestate_bit =3D CPU_INTERRUPT_FIQ; + break; + default: + g_assert_not_reached(); + } + + if (level) { + env->irq_line_state |=3D linestate_bit; + } else { + env->irq_line_state &=3D ~linestate_bit; + } + kvm_arm_set_irq(cs->cpu_index, KVM_ARM_IRQ_TYPE_CPU, irq_id, !!level); +} + +static void kvm_cpu_instance_init(CPUState *cs) +{ + /* + * VIRQ and VFIQ are unused with KVM but we add them to maintain + * the same interface as non-KVM CPUs. + */ + qdev_init_gpio_in(DEVICE(cs), arm_cpu_kvm_set_irq, 4); +} + +static bool kvm_cpu_realizefn(CPUState *cs, Error **errp) +{ + /* + * If we needed to query the host kernel for the CPU features + * then it's possible that might have failed in the initfn, but + * this is the first point where we can report it. + */ + ARMCPU *cpu =3D ARM_CPU(cs); + + if (cpu->host_cpu_probe_failed) { + error_setg(errp, "Failed to retrieve host CPU features"); + return false; + } + return true; +} + +static void host_cpu_instance_init(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + kvm_arm_set_cpu_features_from_host(cpu); + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + aarch64_add_sve_properties(obj); + } + arm_cpu_post_init(obj); +} + +static void kvm_cpu_reset(CPUState *cs) +{ + kvm_arm_reset_vcpu(ARM_CPU(cs)); +} + +static const TypeInfo host_cpu_type_info =3D { + .name =3D ARM_CPU_TYPE_NAME("host"), + .parent =3D TYPE_AARCH64_CPU, + .instance_init =3D host_cpu_instance_init, +}; + +static void kvm_cpu_accel_class_init(ObjectClass *oc, void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + + acc->cpu_realizefn =3D kvm_cpu_realizefn; + acc->cpu_instance_init =3D kvm_cpu_instance_init; + acc->cpu_reset =3D kvm_cpu_reset; +} + +static const TypeInfo kvm_cpu_accel_type_info =3D { + .name =3D ACCEL_CPU_NAME("kvm"), + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D kvm_cpu_accel_class_init, + .abstract =3D true, +}; + +static void kvm_cpu_accel_register_types(void) +{ + type_register_static(&host_cpu_type_info); + type_register_static(&kvm_cpu_accel_type_info); +} + +type_init(kvm_cpu_accel_register_types); diff --git a/target/arm/kvm/meson.build b/target/arm/kvm/meson.build index e92010fa3f..ef58a29dd7 100644 --- a/target/arm/kvm/meson.build +++ b/target/arm/kvm/meson.build @@ -1,4 +1,5 @@ arm_ss.add(when: 'CONFIG_KVM', if_true: files( 'kvm.c', 'kvm64.c', + 'kvm-cpu.c', )) --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622826507; cv=none; d=zohomail.com; s=zohoarc; b=exmwkwyWmdtzkx6Wi6xDoAbiM53l1e0EiO02VqxeYB8luTuxEY32FtIRCPkpt/prH9UPZ49vFidBpZmUo4ykMIvNO7AtoE4rZQoOoHobtmFyjiReMjMkxK0ldvcu+k66YOgNMcEijUg/DogUxTDuhRysRvvoroEGk3Ja0S32WOE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622826507; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=D4Fg0Dja58X/pwaq0v8JkFhBHTMRtUReJTqk/3Hcw8E=; b=XG9+DvKVi1haX9GIY7XNy/SyqlMRecu7GtnrE4th+40s107+/D87TC+53ZdEaDvmr9VZQdfswY03RtR6+F+YlcpxGkDRCWk41COWdN2ArJUBpjsDloJ9/GXzIQYXPmP8ga+H1uKPcUtA2ocjIDvotMhnVG4fcdIjwo9GErhSWnI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622826507302273.55914124213734; Fri, 4 Jun 2021 10:08:27 -0700 (PDT) Received: from localhost ([::1]:38146 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDJ4-0006Ed-5m for importer@patchew.org; Fri, 04 Jun 2021 13:08:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33284) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCkV-0007vL-P3 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:32:43 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:46786) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCkU-00026G-49 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:32:43 -0400 Received: by mail-wm1-x334.google.com with SMTP id h22-20020a05600c3516b02901a826f84095so977393wmq.5 for ; Fri, 04 Jun 2021 09:32:41 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id w11sm7439148wrv.89.2021.06.04.09.32.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:38 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id F2F7F1FFDC; Fri, 4 Jun 2021 16:53:20 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D4Fg0Dja58X/pwaq0v8JkFhBHTMRtUReJTqk/3Hcw8E=; b=KBtW9owH4oqFDsQ/ei+FxAtn2PrZgaswjzShvdAI7I0dp6QEtTxRD4DwztT4zDlSYQ Fjs5coHf8Mf9grFOGpEik+zSUxyEWM14uFaNm69PGvKWG6IJikWrPA5FIcdveg+ZuEbn huO1IUDLKKjdrDsCAipIWlbARm9YkpsQwvVlrG9RIPMicT46QRQkKoEqRAc7pWFLY+6z SfoEHoedVc/tpdaa/sPonq/8Bk3Z7qkvxYDnydVBM+sAE2QS9LjY+y3NNohpFJjBLqVv SASzyHTlOnl0lSQ2O//o7js9vT0arieHEwYbRcychxMMYxtF36GETfFheMUN6m94HQId jdFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D4Fg0Dja58X/pwaq0v8JkFhBHTMRtUReJTqk/3Hcw8E=; b=YZngKqTyCBsvbLzIil0V/QGVh2tsT4vxgytavZe8LxIHCaJTC4i6cKWirBaEshwIxs K5A3U2fSALP1XnxFfIylbOCgKd5X31gt5lOJOEefr+yxfpzGf8cHXAkiH1/KMkbGT+Ej GsEV+7+KcQ7s5V13m0n+CXgo++/pN3iuGIJEDxpM1BUGzbU9QB6MIShgTET/zntkbW38 ZOVllWsOOJt6JgIqj8yl6S73a1tRUuoDMVYwAafAGk+jXNbOhB8s67GSQxbAWFY4lyJ9 tzDhbflqGw/Bi+zEvrj6pnwqBJ1bLMD2ADm4oZ7VRmBdhJt8umhIc/e2bAgbI2nt2oIq DncQ== X-Gm-Message-State: AOAM532srcy40JmUKnQj2RvqgXThKVdPabnfNiw4IeUOMhQOgWmgpYmR OZ5QGNsQumvwzwOgu0eXuYZloA== X-Google-Smtp-Source: ABdhPJzTUA6ppXOxACHc3JrYgxJJ1Fw9ae5mjC3r3XBuQMsjkOVjhyKS1JM/gPBBU3DA/Un+33Bn8A== X-Received: by 2002:a7b:c5d3:: with SMTP id n19mr4593580wmk.68.1622824360689; Fri, 04 Jun 2021 09:32:40 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 68/99] target/arm: move kvm post init initialization to kvm cpu accel Date: Fri, 4 Jun 2021 16:52:41 +0100 Message-Id: <20210604155312.15902-69-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu.c | 4 ---- target/arm/kvm/kvm-cpu.c | 1 + 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0ecbfa060c..003e58d8ee 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -778,10 +778,6 @@ void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(cpu), &arm_cpu_gt_cntfrq_property); } =20 - if (kvm_enabled()) { - kvm_arm_add_vcpu_properties(obj); - } - #ifndef CONFIG_USER_ONLY if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && cpu_isar_feature(aa64_mte, cpu)) { diff --git a/target/arm/kvm/kvm-cpu.c b/target/arm/kvm/kvm-cpu.c index 5fbb127e61..9f65010c0c 100644 --- a/target/arm/kvm/kvm-cpu.c +++ b/target/arm/kvm/kvm-cpu.c @@ -63,6 +63,7 @@ static void kvm_cpu_instance_init(CPUState *cs) * the same interface as non-KVM CPUs. */ qdev_init_gpio_in(DEVICE(cs), arm_cpu_kvm_set_irq, 4); + kvm_arm_add_vcpu_properties(OBJECT(cs)); } =20 static bool kvm_cpu_realizefn(CPUState *cs, Error **errp) --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622826177; cv=none; d=zohomail.com; s=zohoarc; b=m38UCi9C6gi5KM+zOW3mvlZ1/fSZfRwaOHiMOgjNpTbXcfCgEf6aa1xsj/0UYBQ6V21j06hMUyvBg8WAXSPd3xzwh8IN+nHC7iMoRWyyoqOg7kA8KxTVrmxAEoVTSUliH8OofHneSowP8LqPuWGBiQ00Og5UP5FehOI3zmxP5Gc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622826177; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IZcluuGH+rF7DI3dlOPWDCggxxQXhI+T0BM1IJZ8hik=; b=DLEX8RYTaq4ltZnEPyM/A3ojxrLcSKk5F5d0oB4ErjCRf0qNqyctLrytnRfMHeFlxWG6MRLLL8gTsTTo8w53QMg6z4rH8WsiCUCmMM/2savwXNVLI5Y3BkdXJaiA0ldODH6dZsULCyLsGgefOK8woj6ppHgoa79p/U3IGlAYxQU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622826177342305.6539456022457; Fri, 4 Jun 2021 10:02:57 -0700 (PDT) Received: from localhost ([::1]:45398 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDDF-0008Tr-4H for importer@patchew.org; Fri, 04 Jun 2021 13:02:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51740) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCRF-0002po-01 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:49 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:33714) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCRB-0003oJ-6b for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:48 -0400 Received: by mail-wr1-x42b.google.com with SMTP id a20so9911559wrc.0 for ; Fri, 04 Jun 2021 09:12:44 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id l10sm7144801wrm.2.2021.06.04.09.12.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:12:42 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 1DE7B1FFDD; Fri, 4 Jun 2021 16:53:21 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IZcluuGH+rF7DI3dlOPWDCggxxQXhI+T0BM1IJZ8hik=; b=jgqtgZh3OkQoHx0aooR74gfohMyDUIGBlhGfkcwgAMkkNJWJAM+Qbrhk/l4EJ7joac HzlOGrjNH9/ybbzz+R9UAZhrKF/QQXKqJGb+ndXZ5sVnDpBgI8modGF61owNzr0Cv6e8 i1dSPVU/yjBgYsvjQLVwVr04OpKNPMILH4bhlWgCn/45VVzf5IqTzoCGoiBEazJCINto PtNRCb4VIN0vo7aDxsL+xFb1Xw7uQhFVYqpS0L9x8piJn7m7E5HA3T8oMVgc2XOsQp/7 bHiJBnlh7J2RGoCllYVV56py6G71L+/44TBT94mo1R5yWp2OPyeQt/gSI9Hnrr7LEPV1 VliQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IZcluuGH+rF7DI3dlOPWDCggxxQXhI+T0BM1IJZ8hik=; b=KHEEBdmV8Ytzz28pRtpWqK06bKjDay2xy1PzCE+5jpWhLq9rv3qGjbtqtws74sJSq3 S3jMOm29OoWFtIBgRwtAzxC/g/hU0vmfRW+2cMT41c50KxMrpnS5YL8OKlp1TRCLrpdN y49pevxuJwMmdyOcXxbdN8GfXKkUW8t8pe/Vg7Y63D9r/laPBn6tSd/iN1KDt5MdwnAh mLM4SAM30odQYWTMHqrglX3XRmbICfLYovupyztDMP6MjS6heEckJlzL4GzfmSpuBgXM 11HteumgXJFzU65usG5/11HRSiZmFaNK9BZ+O/OTfgcPQXRt+mUs5OlFykpqT1B4s3Va XBOw== X-Gm-Message-State: AOAM533g8OdqMvk8/ADjjTqGC25MYbyi4bvFyCVO/WvxL3i4LFEJfJdf 67d3pkTI/HxBs6Y1GHgqoF2mKw== X-Google-Smtp-Source: ABdhPJyjKr3qnZ31tbvNc+dxjrynGFBWIjUPam75haAAiE3X/lqNbb88GowAOUpMB6S4aYiKp5vuKA== X-Received: by 2002:adf:eeca:: with SMTP id a10mr4651107wrp.184.1622823163871; Fri, 04 Jun 2021 09:12:43 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 69/99] target/arm: add tcg cpu accel class Date: Fri, 4 Jun 2021 16:52:42 +0100 Message-Id: <20210604155312.15902-70-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana move init, realizefn and reset code into it. Signed-off-by: Claudio Fontana Cc: Paolo Bonzini Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/tcg-cpu.h | 4 ++- target/arm/cpu.c | 44 ++------------------------ target/arm/tcg/sysemu/tcg-cpu.c | 27 ++++++++++++++++ target/arm/tcg/tcg-cpu-models.c | 10 +++--- target/arm/tcg/tcg-cpu.c | 55 +++++++++++++++++++++++++++++++-- 5 files changed, 92 insertions(+), 48 deletions(-) diff --git a/target/arm/tcg/tcg-cpu.h b/target/arm/tcg/tcg-cpu.h index d93c6a6749..dd08587949 100644 --- a/target/arm/tcg/tcg-cpu.h +++ b/target/arm/tcg/tcg-cpu.h @@ -22,15 +22,17 @@ =20 #include "cpu.h" #include "hw/core/tcg-cpu-ops.h" +#include "hw/core/accel-cpu.h" =20 void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); =20 -extern struct TCGCPUOps arm_tcg_ops; +void tcg_arm_init_accel_cpu(AccelCPUClass *accel_cpu, CPUClass *cc); =20 #ifndef CONFIG_USER_ONLY /* Do semihosting call and set the appropriate return value. */ void tcg_handle_semihosting(CPUState *cs); +bool tcg_cpu_realizefn(CPUState *cs, Error **errp); =20 #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 003e58d8ee..945dfbbe9d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -410,12 +410,6 @@ static void arm_cpu_reset(DeviceState *dev) &env->vfp.fp_status_f16); set_float_detect_tininess(float_tininess_before_rounding, &env->vfp.standard_fp_status_f16); - - if (tcg_enabled()) { - hw_breakpoint_update_all(cpu); - hw_watchpoint_update_all(cpu); - arm_rebuild_hflags(env); - } } =20 void arm_cpu_update_virq(ARMCPU *cpu) @@ -576,10 +570,6 @@ static void arm_cpu_initfn(Object *obj) cpu->dtb_compatible =3D "qemu,unknown"; cpu->psci_version =3D 1; /* By default assume PSCI v0.1 */ cpu->kvm_target =3D QEMU_KVM_ARM_TARGET_NONE; - - if (tcg_enabled()) { - cpu->psci_version =3D 2; /* TCG implements PSCI 0.2 */ - } } =20 static Property arm_cpu_gt_cntfrq_property =3D @@ -868,34 +858,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error = **errp) Error *local_err =3D NULL; bool no_aa32 =3D false; =20 - /* - * If we needed to query the host kernel for the CPU features - * then it's possible that might have failed in the initfn, but - * this is the first point where we can report it. - */ - if (cpu->host_cpu_probe_failed) { - error_setg(errp, "The 'host' CPU type can only be used with KVM"); - return; - } - -#ifndef CONFIG_USER_ONLY - /* The NVIC and M-profile CPU are two halves of a single piece of - * hardware; trying to use one without the other is a command line - * error and will result in segfaults if not caught here. - */ - if (arm_feature(env, ARM_FEATURE_M)) { - if (!env->nvic) { - error_setg(errp, "This board cannot be used with Cortex-M CPUs= "); - return; - } - } else { - if (env->nvic) { - error_setg(errp, "This board can only be used with Cortex-M CP= Us"); - return; - } - } - -#ifdef CONFIG_TCG +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) { uint64_t scale; =20 @@ -921,8 +884,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error *= *errp) cpu->gt_timer[GTIMER_HYPVIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, sc= ale, arm_gt_hvtimer_cb, cpu); } -#endif /* CONFIG_TCG */ -#endif /* !CONFIG_USER_ONLY */ +#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ =20 cpu_exec_realizefn(cs, &local_err); if (local_err !=3D NULL) { @@ -1467,7 +1429,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->disas_set_info =3D arm_disas_set_info; =20 #ifdef CONFIG_TCG - cc->tcg_ops =3D &arm_tcg_ops; + cc->init_accel_cpu =3D tcg_arm_init_accel_cpu; #endif /* CONFIG_TCG */ =20 arm32_cpu_class_init(oc, data); diff --git a/target/arm/tcg/sysemu/tcg-cpu.c b/target/arm/tcg/sysemu/tcg-cp= u.c index 327b2a5073..115ac523dc 100644 --- a/target/arm/tcg/sysemu/tcg-cpu.c +++ b/target/arm/tcg/sysemu/tcg-cpu.c @@ -19,10 +19,13 @@ */ =20 #include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/timer.h" #include "cpu.h" #include "semihosting/common-semi.h" #include "qemu/log.h" #include "tcg/tcg-cpu.h" +#include "internals.h" =20 /* * Do semihosting call and set the appropriate return value. All the @@ -50,3 +53,27 @@ void tcg_handle_semihosting(CPUState *cs) env->regs[15] +=3D env->thumb ? 2 : 4; } } + +bool tcg_cpu_realizefn(CPUState *cs, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + /* + * The NVIC and M-profile CPU are two halves of a single piece of + * hardware; trying to use one without the other is a command line + * error and will result in segfaults if not caught here. + */ + if (arm_feature(env, ARM_FEATURE_M)) { + if (!env->nvic) { + error_setg(errp, "This board cannot be used with Cortex-M CPUs= "); + return false; + } + } else { + if (env->nvic) { + error_setg(errp, "This board can only be used with Cortex-M CP= Us"); + return false; + } + } + return true; +} diff --git a/target/arm/tcg/tcg-cpu-models.c b/target/arm/tcg/tcg-cpu-model= s.c index 91af2174a1..975869f276 100644 --- a/target/arm/tcg/tcg-cpu-models.c +++ b/target/arm/tcg/tcg-cpu-models.c @@ -846,16 +846,18 @@ static const struct TCGCPUOps arm_v7m_tcg_ops =3D { }; #endif /* CONFIG_TCG */ =20 +static void arm_v7m_init_accel_cpu(AccelCPUClass *accel_cpu, CPUClass *cc) +{ + cc->tcg_ops =3D &arm_v7m_tcg_ops; +} + static void arm_v7m_class_init(ObjectClass *oc, void *data) { ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); CPUClass *cc =3D CPU_CLASS(oc); =20 acc->info =3D data; -#ifdef CONFIG_TCG - cc->tcg_ops =3D &arm_v7m_tcg_ops; -#endif /* CONFIG_TCG */ - + cc->init_accel_cpu =3D arm_v7m_init_accel_cpu; cc->gdb_core_xml_file =3D "arm-m-profile.xml"; } =20 diff --git a/target/arm/tcg/tcg-cpu.c b/target/arm/tcg/tcg-cpu.c index 9fd996d908..db677bc71c 100644 --- a/target/arm/tcg/tcg-cpu.c +++ b/target/arm/tcg/tcg-cpu.c @@ -20,8 +20,8 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "qapi/error.h" #include "tcg-cpu.h" -#include "hw/core/tcg-cpu-ops.h" #include "cpregs.h" #include "internals.h" #include "exec/exec-all.h" @@ -212,7 +212,7 @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int in= terrupt_request) return true; } =20 -struct TCGCPUOps arm_tcg_ops =3D { +static struct TCGCPUOps arm_tcg_ops =3D { .initialize =3D arm_translate_init, .synchronize_from_tb =3D arm_cpu_synchronize_from_tb, .cpu_exec_interrupt =3D arm_cpu_exec_interrupt, @@ -227,3 +227,54 @@ struct TCGCPUOps arm_tcg_ops =3D { .debug_check_watchpoint =3D arm_debug_check_watchpoint, #endif /* !CONFIG_USER_ONLY */ }; + +static void tcg_cpu_instance_init(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + + /* + * this would be the place to move TCG-specific props + * in future refactoring of cpu properties. + */ + + cpu->psci_version =3D 2; /* TCG implements PSCI 0.2 */ +} + +static void tcg_cpu_reset(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + hw_breakpoint_update_all(cpu); + hw_watchpoint_update_all(cpu); + arm_rebuild_hflags(env); +} + +void tcg_arm_init_accel_cpu(AccelCPUClass *accel_cpu, CPUClass *cc) +{ + cc->tcg_ops =3D &arm_tcg_ops; +} + +static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) +{ + AccelCPUClass *acc =3D ACCEL_CPU_CLASS(oc); + +#ifndef CONFIG_USER_ONLY + acc->cpu_realizefn =3D tcg_cpu_realizefn; +#endif /* CONFIG_USER_ONLY */ + + acc->cpu_instance_init =3D tcg_cpu_instance_init; + acc->cpu_reset =3D tcg_cpu_reset; +} +static const TypeInfo tcg_cpu_accel_type_info =3D { + .name =3D ACCEL_CPU_NAME("tcg"), + + .parent =3D TYPE_ACCEL_CPU, + .class_init =3D tcg_cpu_accel_class_init, + .abstract =3D true, +}; +static void tcg_cpu_accel_register_types(void) +{ + type_register_static(&tcg_cpu_accel_type_info); +} +type_init(tcg_cpu_accel_register_types); --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622824318; cv=none; d=zohomail.com; s=zohoarc; b=hvAvKtdVSMemuCIUNxKOMD3SuAMYAVmDGLT3dN3aOFziEO2LWYpBsj+jaMymcraMmJNJz0042vxIdVWNg5XOQ9woOOPBt2fi3dzVRuD7hvAj5Njau1xm2H5uMJsemI/BVqCe4CjI1nNgNoSrfLQD19mjpubmdSgxzNpOjuf5QVM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622824318; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wuU8nDRdcW3/99gtEo5hPanI3MwrgtDEgaxIpfRRswM=; b=aDY9F/6mmYeyk4Z3xQHjrcJGySkxPQeNbWUNo90Azcz0idKpUeUjWCplzf9d1I6nthKFvRjgDi4yh/ypnkiKiz1rPBSndTX9n88B+UO9CIWwUURFro/AeSkG8oaOjKoMH4AvGtJMVsVkzbIHGpsXayP3vadb2GK2QBXyVes9qe8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622824318415957.0757935942003; Fri, 4 Jun 2021 09:31:58 -0700 (PDT) Received: from localhost ([::1]:53730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCjl-00047W-OG for importer@patchew.org; Fri, 04 Jun 2021 12:31:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48620) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCI5-0008R1-1R for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:22 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:45919) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHh-0005s9-Bi for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:20 -0400 Received: by mail-wr1-x435.google.com with SMTP id z8so9801975wrp.12 for ; Fri, 04 Jun 2021 09:02:56 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id b8sm5400497wmd.35.2021.06.04.09.02.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:53 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 378FA1FFDE; Fri, 4 Jun 2021 16:53:21 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wuU8nDRdcW3/99gtEo5hPanI3MwrgtDEgaxIpfRRswM=; b=cUSanbjgU5p4C6tM8P66vDYmES/myvA0uhdkylnzBblqyHRqW9b0GNZmBQIqPbsa5r QHbpV/SzLedy8MGN9106VvzbIMxCWeSwNr8sQh0NWoEZzKA1Zrx4lSS+Xz41SWT8gHuv 3+shnUcvZLEwJ17aqehc0nul4DIUDcFN/E448E1uVg5QBnBD4Vk/G8RZAfpyDZScPzB+ k2gKGuaQF534bvGO31tmEfgY++6ZS/rSXDfzDwBCoy3GTVO1r+yTaKC+a44Kga7MA3Qg pJhDKskd/ngQMLLh77rBAi92pPNcfszJyVgS3IrfLZVPIzQlczb1FtXl9dgWNzJ51SBG TAiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wuU8nDRdcW3/99gtEo5hPanI3MwrgtDEgaxIpfRRswM=; b=ZPtS8SWCfKVbSZwBZmwKi//tQ+j2wLjYo6VBZxZBafF6W89NDX5m1ezxP/vbkUriCJ wbP/8y72UnoiPPqdMQPRwWbgcGL+XBO/xi/9TE/WYTn1eWgqiuibktQwWBIp7FkEXQkU 5DE87Agi2LPgC35MyYLaQ41u05tbPHh725y86GoUDaraMofeAGTllpyjbqA5IcCcMqmw aZ35PSTwfDRFFefLDpRaTPigr+Bu91V8zQektJTBjcpxkWMwHXthEzwvMt0XH9gk9X6D aDk/+TZ8KbSx63u+xQ8TEk+x5fCLwESryQYmeYt8a2aFsImfQvPQriNzPvTDvVivxU16 8jCw== X-Gm-Message-State: AOAM530h2UiRYqdkVocaOkxetmC87/UGuMsS4x7O4F4wjg9dhcu1pMPZ 1glW7PkJkcAEA9X/9R3xc1z+Yg== X-Google-Smtp-Source: ABdhPJxi821IHVetIh0prBnip7xTPC84KXgBTIX651edRhvxydKIdws+VxmgsMLQZuMe0gOcHAjiqg== X-Received: by 2002:a5d:4c48:: with SMTP id n8mr4493694wrt.327.1622822575116; Fri, 04 Jun 2021 09:02:55 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 70/99] target/arm: move TCG gt timer creation code in tcg/ Date: Fri, 4 Jun 2021 16:52:43 +0100 Message-Id: <20210604155312.15902-71-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana we need to be careful not to use if (tcg_enabled()) here, because of the VMSTATE definitions in machine.c, which are only protected by CONFIG_TCG, and thus it would break the --enable-tcg --enable-kvm build. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/tcg-cpu.h | 1 + target/arm/cpu.c | 30 ++++--------------------- target/arm/tcg/sysemu/tcg-cpu.c | 40 +++++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+), 26 deletions(-) diff --git a/target/arm/tcg/tcg-cpu.h b/target/arm/tcg/tcg-cpu.h index dd08587949..3e4ce2c355 100644 --- a/target/arm/tcg/tcg-cpu.h +++ b/target/arm/tcg/tcg-cpu.h @@ -33,6 +33,7 @@ void tcg_arm_init_accel_cpu(AccelCPUClass *accel_cpu, CPU= Class *cc); /* Do semihosting call and set the appropriate return value. */ void tcg_handle_semihosting(CPUState *cs); bool tcg_cpu_realizefn(CPUState *cs, Error **errp); +bool tcg_cpu_realize_gt_timers(CPUState *cs, Error **errp); =20 #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 945dfbbe9d..2fef8ca471 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -859,32 +859,10 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) bool no_aa32 =3D false; =20 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) - { - uint64_t scale; - - if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { - if (!cpu->gt_cntfrq_hz) { - error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", - cpu->gt_cntfrq_hz); - return; - } - scale =3D gt_cntfrq_period_ns(cpu); - } else { - scale =3D GTIMER_SCALE; - } - - cpu->gt_timer[GTIMER_PHYS] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, - arm_gt_ptimer_cb, cpu); - cpu->gt_timer[GTIMER_VIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, - arm_gt_vtimer_cb, cpu); - cpu->gt_timer[GTIMER_HYP] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, - arm_gt_htimer_cb, cpu); - cpu->gt_timer[GTIMER_SEC] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, - arm_gt_stimer_cb, cpu); - cpu->gt_timer[GTIMER_HYPVIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, sc= ale, - arm_gt_hvtimer_cb, cpu); - } -#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ + if (!tcg_cpu_realize_gt_timers(cs, errp)) { + return; + } +#endif =20 cpu_exec_realizefn(cs, &local_err); if (local_err !=3D NULL) { diff --git a/target/arm/tcg/sysemu/tcg-cpu.c b/target/arm/tcg/sysemu/tcg-cp= u.c index 115ac523dc..1c6df15092 100644 --- a/target/arm/tcg/sysemu/tcg-cpu.c +++ b/target/arm/tcg/sysemu/tcg-cpu.c @@ -54,6 +54,46 @@ void tcg_handle_semihosting(CPUState *cs) } } =20 +/* + * we cannot use tcg_enabled() to condition the call to this function, + * due to the fields VMSTATE definitions in machine.c : it would break + * the --enable-tcg --enable-kvm build. We need to run this code whenever + * CONFIG_TCG is true, regardless of the chosen accelerator. + * + * So we cannot call this from tcg_cpu_realizefn, as this needs to + * be called whenever TCG is built-in, regardless of whether it is + * enabled or not. + */ +bool tcg_cpu_realize_gt_timers(CPUState *cs, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + uint64_t scale; + + if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) { + if (!cpu->gt_cntfrq_hz) { + error_setg(errp, "Invalid CNTFRQ: %"PRId64"Hz", + cpu->gt_cntfrq_hz); + return false; + } + scale =3D gt_cntfrq_period_ns(cpu); + } else { + scale =3D GTIMER_SCALE; + } + + cpu->gt_timer[GTIMER_PHYS] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_ptimer_cb, cpu); + cpu->gt_timer[GTIMER_VIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_vtimer_cb, cpu); + cpu->gt_timer[GTIMER_HYP] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_htimer_cb, cpu); + cpu->gt_timer[GTIMER_SEC] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_stimer_cb, cpu); + cpu->gt_timer[GTIMER_HYPVIRT] =3D timer_new(QEMU_CLOCK_VIRTUAL, scale, + arm_gt_hvtimer_cb, cpu); + return true; +} + bool tcg_cpu_realizefn(CPUState *cs, Error **errp) { ARMCPU *cpu =3D ARM_CPU(cs); --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622825144; cv=none; d=zohomail.com; s=zohoarc; b=WkZ4mrOKz1hj8fePMRPTthR3zpqbkrS9/U/0zimjZ0Hu+CLJBL3cS/HcvW1zDgd7OO6ECsDpNt6Z2/Qv4OD1sPDtLUCs6f6H7OUimmm1SKdrXOyOzzsldjAwKuH67lWjCG2uW/L0TwODtUDVOwZn4wVgymmAuDVEsOJ7nXLZXeM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622825144; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+lRMEJ0Jroff3JWceP6oHhM/6tfNcxStzXU3u63x4aE=; b=l9+ifeYS7kgzt0fc7+2lwdP7394I3Fq8F66BFP+yAFj1cBsPIzXwo2Tx3a3O5uThP85xGoHxqihsY0mDbMxhsLZlZ5STcnA3DBmvRThcba3zIIgXFh3Uu2xrGgntHsHwy8NRMpwgBdTz5QmUvIf9c+QBspu7Oo9mOJS3qDc9fZI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162282514436428.436453380363332; Fri, 4 Jun 2021 09:45:44 -0700 (PDT) Received: from localhost ([::1]:38504 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCx5-0007jQ-8N for importer@patchew.org; Fri, 04 Jun 2021 12:45:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51730) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCRE-0002nr-D0 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:48 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:40614) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCR9-0003nT-0j for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:48 -0400 Received: by mail-wr1-x42d.google.com with SMTP id y7so5219503wrh.7 for ; Fri, 04 Jun 2021 09:12:42 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id a1sm8019703wrg.92.2021.06.04.09.12.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:12:37 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 61CD91FFDF; Fri, 4 Jun 2021 16:53:21 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+lRMEJ0Jroff3JWceP6oHhM/6tfNcxStzXU3u63x4aE=; b=Td5J72B76ZjB+Lvyb7YR0FE1MZCPDFVFdgMk9GQ6KdVCVasLJvy5GZDakMqID195rY pvjEOq8R+Y93fjTr38eUcUjnatgjuVZElFacOG844hadG+bPX9QKMmXeIHTziTq6OhQo UAr9U2XSuBlAAQ1KE5tOhIw+btsOK0tOZ30CpbosPqJuuap8UK4i6KCBVr3XLxOFHYkL a6mRDBg8Dysq4PD5VRudzoQoyP8d6/JkYj6pEalfdEQt02q7opnxgqinTr2jkKx9bagh tjdvPeu9cKRAV73w4zUKaYE0eQVBMdRoJuw6EIwpDXc7PdBMNaFsYf9Kob843T+mRU10 ktuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+lRMEJ0Jroff3JWceP6oHhM/6tfNcxStzXU3u63x4aE=; b=DUiSGbuuB34akZjsja8zPBdhK27G8lapMi6BmC2IIxaCO/dkocnyef03E+nCn9Y2MV wSzKBxbRN0Kzx1LTKgRKXGyqFRaRpo4FJTLES31SdCNFDpAi9ggUeCVeVPUCG8L6gWjx E5ZoooBHfMVyGHXd0eoRIWUU//68Ju5wkjrz7P2teFE8Onok4DXbOYv0EvFeRSt7FYt2 og2aj0xJKmEDGyf48GcZ17GMAK68cLRblunV4GCoHdgqWvzhm10in2dSYzwcOoy0DNst bIPB9R7GstL501Z34+yaZ+0LitN6ngY8zzOCzfRH8XVbS4+/ynLfYF52k4FvqOjr47Z4 CkhA== X-Gm-Message-State: AOAM531oGsdOp7J1VBqxHiioeCKXbVVowCw6hFin+6tdVeOoubh/D3Ze w/W3vFRiR66bx1csBxHhbXPZwg== X-Google-Smtp-Source: ABdhPJx/U5roY0oaCGusPRGp7nMGXEUcG1DNyO2kX+xu55oCAG1dXs+8mPL2SaqtHGybwVcvlxqH+w== X-Received: by 2002:adf:a401:: with SMTP id d1mr4646896wra.55.1622823161296; Fri, 04 Jun 2021 09:12:41 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 71/99] target/arm: cpu-sve: new module Date: Fri, 4 Jun 2021 16:52:44 +0100 Message-Id: <20210604155312.15902-72-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana extract the SVE-related cpu object properties and functions, and move them to a separate module. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-sve.h | 37 ++++ target/arm/cpu.h | 14 +- target/arm/cpu-sve.c | 358 +++++++++++++++++++++++++++++++++++++++ target/arm/cpu.c | 3 + target/arm/cpu64.c | 329 +---------------------------------- target/arm/kvm/kvm-cpu.c | 1 + target/arm/meson.build | 1 + 7 files changed, 408 insertions(+), 335 deletions(-) create mode 100644 target/arm/cpu-sve.h create mode 100644 target/arm/cpu-sve.c diff --git a/target/arm/cpu-sve.h b/target/arm/cpu-sve.h new file mode 100644 index 0000000000..692509d419 --- /dev/null +++ b/target/arm/cpu-sve.h @@ -0,0 +1,37 @@ +/* + * QEMU AArch64 CPU SVE Extensions for TARGET_AARCH64 + * + * Copyright (c) 2013 Linaro Ltd + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#ifndef CPU_SVE_H +#define CPU_SVE_H + +/* note: SVE is an AARCH64-only option, only include this for TARGET_AARCH= 64 */ + +#include "cpu.h" + +/* called by arm_cpu_finalize_features in realizefn */ +void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); + +/* add the CPU SVE properties */ +void aarch64_add_sve_properties(Object *obj); + +/* add the CPU SVE properties specific to the "MAX" CPU */ +void aarch64_add_sve_properties_max(Object *obj); + +#endif /* CPU_SVE_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f57fa9b9f5..b9b9bd8b01 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -173,7 +173,8 @@ typedef struct { #define VSTCR_SW VTCR_NSW #define VSTCR_SA VTCR_NSA =20 -/* Define a maximum sized vector register. +/* + * Define a maximum sized vector register. * For 32-bit, this is a 128-bit NEON/AdvSIMD register. * For 64-bit, this is a 2048-bit SVE register. * @@ -201,13 +202,9 @@ typedef struct { =20 #ifdef TARGET_AARCH64 # define ARM_MAX_VQ 16 -void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); -void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); #else # define ARM_MAX_VQ 1 -static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { } -static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } -#endif +#endif /* TARGET_AARCH64 */ =20 typedef struct ARMVectorReg { uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); @@ -219,10 +216,13 @@ typedef struct ARMPredicateReg { uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); } ARMPredicateReg; =20 +void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); /* In AArch32 mode, PAC keys do not exist at all. */ typedef struct ARMPACKey { uint64_t lo, hi; } ARMPACKey; +#else +static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } #endif =20 /* See the commentary above the TBFLAG field definitions. */ @@ -1059,7 +1059,6 @@ int aarch64_cpu_gdb_write_register(CPUState *cpu, uin= t8_t *buf, int reg); void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el, bool el0_a64); -void aarch64_add_sve_properties(Object *obj); =20 /* * SVE registers are encoded in KVM's memory in an endianness-invariant fo= rmat. @@ -1090,7 +1089,6 @@ static inline void aarch64_sve_narrow_vq(CPUARMState = *env, unsigned vq) { } static inline void aarch64_sve_change_el(CPUARMState *env, int o, int n, bool a) { } -static inline void aarch64_add_sve_properties(Object *obj) { } #endif =20 void aarch64_sync_32_to_64(CPUARMState *env); diff --git a/target/arm/cpu-sve.c b/target/arm/cpu-sve.c new file mode 100644 index 0000000000..129fb9586e --- /dev/null +++ b/target/arm/cpu-sve.c @@ -0,0 +1,358 @@ +/* + * QEMU ARM CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "cpu.h" +#include "sysemu/tcg.h" +#include "sysemu/kvm.h" +#include "kvm/kvm_arm.h" +#include "qapi/visitor.h" +#include "cpu-sve.h" + +void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) +{ + /* + * If any vector lengths are explicitly enabled with sve properties, + * then all other lengths are implicitly disabled. If sve-max-vq is + * specified then it is the same as explicitly enabling all lengths + * up to and including the specified maximum, which means all larger + * lengths will be implicitly disabled. If no sve properties + * are enabled and sve-max-vq is not specified, then all lengths not + * explicitly disabled will be enabled. Additionally, all power-of-two + * vector lengths less than the maximum enabled length will be + * automatically enabled and all vector lengths larger than the largest + * disabled power-of-two vector length will be automatically disabled. + * Errors are generated if the user provided input that interferes with + * any of the above. Finally, if SVE is not disabled, then at least o= ne + * vector length must be enabled. + */ + DECLARE_BITMAP(kvm_supported, ARM_MAX_VQ); + DECLARE_BITMAP(tmp, ARM_MAX_VQ); + uint32_t vq, max_vq =3D 0; + + /* Collect the set of vector lengths supported by KVM. */ + bitmap_zero(kvm_supported, ARM_MAX_VQ); + if (kvm_enabled() && kvm_arm_sve_supported()) { + kvm_arm_sve_get_vls(CPU(cpu), kvm_supported); + } else if (kvm_enabled()) { + assert(!cpu_isar_feature(aa64_sve, cpu)); + } + + /* + * Process explicit sve properties. + * From the properties, sve_vq_map implies sve_vq_init. + * Check first for any sve enabled. + */ + if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) { + max_vq =3D find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1; + + if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { + error_setg(errp, "cannot enable sve%d", max_vq * 128); + error_append_hint(errp, "sve%d is larger than the maximum vect= or " + "length, sve-max-vq=3D%d (%d bits)\n", + max_vq * 128, cpu->sve_max_vq, + cpu->sve_max_vq * 128); + return; + } + + if (kvm_enabled()) { + /* + * For KVM we have to automatically enable all supported uniti= alized + * lengths, even when the smaller lengths are not all powers-o= f-two. + */ + bitmap_andnot(tmp, kvm_supported, cpu->sve_vq_init, max_vq); + bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); + } else if (tcg_enabled()) { + /* Propagate enabled bits down through required powers-of-two.= */ + for (vq =3D pow2floor(max_vq); vq >=3D 1; vq >>=3D 1) { + if (!test_bit(vq - 1, cpu->sve_vq_init)) { + set_bit(vq - 1, cpu->sve_vq_map); + } + } + } + } else if (cpu->sve_max_vq =3D=3D 0) { + /* + * No explicit bits enabled, and no implicit bits from sve-max-vq. + */ + if (!cpu_isar_feature(aa64_sve, cpu)) { + /* SVE is disabled and so are all vector lengths. Good. */ + return; + } + + if (kvm_enabled()) { + /* Disabling a supported length disables all larger lengths. */ + for (vq =3D 1; vq <=3D ARM_MAX_VQ; ++vq) { + if (test_bit(vq - 1, cpu->sve_vq_init) && + test_bit(vq - 1, kvm_supported)) { + break; + } + } + max_vq =3D vq <=3D ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; + bitmap_andnot(cpu->sve_vq_map, kvm_supported, + cpu->sve_vq_init, max_vq); + if (max_vq =3D=3D 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) { + error_setg(errp, "cannot disable sve%d", vq * 128); + error_append_hint(errp, "Disabling sve%d results in all " + "vector lengths being disabled.\n", + vq * 128); + error_append_hint(errp, "With SVE enabled, at least one " + "vector length must be enabled.\n"); + return; + } + } else if (tcg_enabled()) { + /* Disabling a power-of-two disables all larger lengths. */ + if (test_bit(0, cpu->sve_vq_init)) { + error_setg(errp, "cannot disable sve128"); + error_append_hint(errp, "Disabling sve128 results in all " + "vector lengths being disabled.\n"); + error_append_hint(errp, "With SVE enabled, at least one " + "vector length must be enabled.\n"); + return; + } + for (vq =3D 2; vq <=3D ARM_MAX_VQ; vq <<=3D 1) { + if (test_bit(vq - 1, cpu->sve_vq_init)) { + break; + } + } + max_vq =3D vq <=3D ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; + bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq); + } + + max_vq =3D find_last_bit(cpu->sve_vq_map, max_vq) + 1; + } + + /* + * Process the sve-max-vq property. + * Note that we know from the above that no bit above + * sve-max-vq is currently set. + */ + if (cpu->sve_max_vq !=3D 0) { + max_vq =3D cpu->sve_max_vq; + + if (!test_bit(max_vq - 1, cpu->sve_vq_map) && + test_bit(max_vq - 1, cpu->sve_vq_init)) { + error_setg(errp, "cannot disable sve%d", max_vq * 128); + error_append_hint(errp, "The maximum vector length must be " + "enabled, sve-max-vq=3D%d (%d bits)\n", + max_vq, max_vq * 128); + return; + } + + /* Set all bits not explicitly set within sve-max-vq. */ + bitmap_complement(tmp, cpu->sve_vq_init, max_vq); + bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); + } + + /* + * We should know what max-vq is now. Also, as we're done + * manipulating sve-vq-map, we ensure any bits above max-vq + * are clear, just in case anybody looks. + */ + assert(max_vq !=3D 0); + bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq); + + if (kvm_enabled()) { + /* Ensure the set of lengths matches what KVM supports. */ + bitmap_xor(tmp, cpu->sve_vq_map, kvm_supported, max_vq); + if (!bitmap_empty(tmp, max_vq)) { + vq =3D find_last_bit(tmp, max_vq) + 1; + if (test_bit(vq - 1, cpu->sve_vq_map)) { + if (cpu->sve_max_vq) { + error_setg(errp, "cannot set sve-max-vq=3D%d", + cpu->sve_max_vq); + error_append_hint(errp, "This KVM host does not suppor= t " + "the vector length %d-bits.\n", + vq * 128); + error_append_hint(errp, "It may not be possible to use= " + "sve-max-vq with this KVM host. Try " + "using only sve properties.\n"); + } else { + error_setg(errp, "cannot enable sve%d", vq * 128); + error_append_hint(errp, "This KVM host does not suppor= t " + "the vector length %d-bits.\n", + vq * 128); + } + } else { + error_setg(errp, "cannot disable sve%d", vq * 128); + error_append_hint(errp, "The KVM host requires all " + "supported vector lengths smaller " + "than %d bits to also be enabled.\n", + max_vq * 128); + } + return; + } + } else if (tcg_enabled()) { + /* Ensure all required powers-of-two are enabled. */ + for (vq =3D pow2floor(max_vq); vq >=3D 1; vq >>=3D 1) { + if (!test_bit(vq - 1, cpu->sve_vq_map)) { + error_setg(errp, "cannot disable sve%d", vq * 128); + error_append_hint(errp, "sve%d is required as it " + "is a power-of-two length smaller than " + "the maximum, sve%d\n", + vq * 128, max_vq * 128); + return; + } + } + } + + /* + * Now that we validated all our vector lengths, the only question + * left to answer is if we even want SVE at all. + */ + if (!cpu_isar_feature(aa64_sve, cpu)) { + error_setg(errp, "cannot enable sve%d", max_vq * 128); + error_append_hint(errp, "SVE must be enabled to enable vector " + "lengths.\n"); + error_append_hint(errp, "Add sve=3Don to the CPU property list.\n"= ); + return; + } + + /* From now on sve_max_vq is the actual maximum supported length. */ + cpu->sve_max_vq =3D max_vq; +} + +static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *na= me, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t value; + + /* All vector lengths are disabled when SVE is off. */ + if (!cpu_isar_feature(aa64_sve, cpu)) { + value =3D 0; + } else { + value =3D cpu->sve_max_vq; + } + visit_type_uint32(v, name, &value, errp); +} + +static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *na= me, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t max_vq; + + if (!visit_type_uint32(v, name, &max_vq, errp)) { + return; + } + + if (kvm_enabled() && !kvm_arm_sve_supported()) { + error_setg(errp, "cannot set sve-max-vq"); + error_append_hint(errp, "SVE not supported by KVM on this host\n"); + return; + } + + if (max_vq =3D=3D 0 || max_vq > ARM_MAX_VQ) { + error_setg(errp, "unsupported SVE vector length"); + error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n", + ARM_MAX_VQ); + return; + } + + cpu->sve_max_vq =3D max_vq; +} + +/* + * Note that cpu_arm_get/set_sve_vq cannot use the simpler + * object_property_add_bool interface because they make use + * of the contents of "name" to determine which bit on which + * to operate. + */ +static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t vq =3D atoi(&name[3]) / 128; + bool value; + + /* All vector lengths are disabled when SVE is off. */ + if (!cpu_isar_feature(aa64_sve, cpu)) { + value =3D false; + } else { + value =3D test_bit(vq - 1, cpu->sve_vq_map); + } + visit_type_bool(v, name, &value, errp); +} + +static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t vq =3D atoi(&name[3]) / 128; + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + if (value && kvm_enabled() && !kvm_arm_sve_supported()) { + error_setg(errp, "cannot enable %s", name); + error_append_hint(errp, "SVE not supported by KVM on this host\n"); + return; + } + + if (value) { + set_bit(vq - 1, cpu->sve_vq_map); + } else { + clear_bit(vq - 1, cpu->sve_vq_map); + } + set_bit(vq - 1, cpu->sve_vq_init); +} + +static bool cpu_arm_get_sve(Object *obj, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + return cpu_isar_feature(aa64_sve, cpu); +} + +static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + uint64_t t; + + if (value && kvm_enabled() && !kvm_arm_sve_supported()) { + error_setg(errp, "'sve' feature not supported by KVM on this host"= ); + return; + } + + t =3D cpu->isar.id_aa64pfr0; + t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, value); + cpu->isar.id_aa64pfr0 =3D t; +} + +void aarch64_add_sve_properties(Object *obj) +{ + uint32_t vq; + + object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); + + for (vq =3D 1; vq <=3D ARM_MAX_VQ; ++vq) { + char name[8]; + sprintf(name, "sve%d", vq * 128); + object_property_add(obj, name, "bool", cpu_arm_get_sve_vq, cpu_arm= _set_sve_vq, NULL, NULL); + } +} + +/* properties added for MAX CPU */ +void aarch64_add_sve_properties_max(Object *obj) +{ + object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_v= q, cpu_max_set_sve_max_vq, NULL, NULL); +} diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2fef8ca471..6db37b42d1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -23,6 +23,7 @@ #include "target/arm/idau.h" #include "qapi/error.h" #include "cpu.h" +#include "cpu-sve.h" #include "cpregs.h" =20 #ifdef CONFIG_TCG @@ -818,6 +819,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **err= p) { Error *local_err =3D NULL; =20 +#ifdef TARGET_AARCH64 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { arm_cpu_sve_finalize(cpu, &local_err); if (local_err !=3D NULL) { @@ -838,6 +840,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **err= p) } } } +#endif /* TARGET_AARCH64 */ =20 if (kvm_enabled()) { kvm_arm_steal_time_finalize(cpu, &local_err); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e3d818275c..3a6b7cf5d1 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -23,6 +23,7 @@ #include "qemu/qemu-print.h" #include "cpu.h" #include "cpu32.h" +#include "cpu-sve.h" #include "qemu/module.h" #include "sysemu/tcg.h" #include "sysemu/kvm.h" @@ -245,331 +246,6 @@ static void aarch64_a72_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } =20 -void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) -{ - /* - * If any vector lengths are explicitly enabled with sve properties, - * then all other lengths are implicitly disabled. If sve-max-vq is - * specified then it is the same as explicitly enabling all lengths - * up to and including the specified maximum, which means all larger - * lengths will be implicitly disabled. If no sve properties - * are enabled and sve-max-vq is not specified, then all lengths not - * explicitly disabled will be enabled. Additionally, all power-of-two - * vector lengths less than the maximum enabled length will be - * automatically enabled and all vector lengths larger than the largest - * disabled power-of-two vector length will be automatically disabled. - * Errors are generated if the user provided input that interferes with - * any of the above. Finally, if SVE is not disabled, then at least o= ne - * vector length must be enabled. - */ - DECLARE_BITMAP(kvm_supported, ARM_MAX_VQ); - DECLARE_BITMAP(tmp, ARM_MAX_VQ); - uint32_t vq, max_vq =3D 0; - - /* Collect the set of vector lengths supported by KVM. */ - bitmap_zero(kvm_supported, ARM_MAX_VQ); - if (kvm_enabled() && kvm_arm_sve_supported()) { - kvm_arm_sve_get_vls(CPU(cpu), kvm_supported); - } else if (kvm_enabled()) { - assert(!cpu_isar_feature(aa64_sve, cpu)); - } - - /* - * Process explicit sve properties. - * From the properties, sve_vq_map implies sve_vq_init. - * Check first for any sve enabled. - */ - if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) { - max_vq =3D find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1; - - if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { - error_setg(errp, "cannot enable sve%d", max_vq * 128); - error_append_hint(errp, "sve%d is larger than the maximum vect= or " - "length, sve-max-vq=3D%d (%d bits)\n", - max_vq * 128, cpu->sve_max_vq, - cpu->sve_max_vq * 128); - return; - } - - if (kvm_enabled()) { - /* - * For KVM we have to automatically enable all supported uniti= alized - * lengths, even when the smaller lengths are not all powers-o= f-two. - */ - bitmap_andnot(tmp, kvm_supported, cpu->sve_vq_init, max_vq); - bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); - } else if (tcg_enabled()) { - /* Propagate enabled bits down through required powers-of-two.= */ - for (vq =3D pow2floor(max_vq); vq >=3D 1; vq >>=3D 1) { - if (!test_bit(vq - 1, cpu->sve_vq_init)) { - set_bit(vq - 1, cpu->sve_vq_map); - } - } - } - } else if (cpu->sve_max_vq =3D=3D 0) { - /* - * No explicit bits enabled, and no implicit bits from sve-max-vq. - */ - if (!cpu_isar_feature(aa64_sve, cpu)) { - /* SVE is disabled and so are all vector lengths. Good. */ - return; - } - - if (kvm_enabled()) { - /* Disabling a supported length disables all larger lengths. */ - for (vq =3D 1; vq <=3D ARM_MAX_VQ; ++vq) { - if (test_bit(vq - 1, cpu->sve_vq_init) && - test_bit(vq - 1, kvm_supported)) { - break; - } - } - max_vq =3D vq <=3D ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; - bitmap_andnot(cpu->sve_vq_map, kvm_supported, - cpu->sve_vq_init, max_vq); - if (max_vq =3D=3D 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) { - error_setg(errp, "cannot disable sve%d", vq * 128); - error_append_hint(errp, "Disabling sve%d results in all " - "vector lengths being disabled.\n", - vq * 128); - error_append_hint(errp, "With SVE enabled, at least one " - "vector length must be enabled.\n"); - return; - } - } else if (tcg_enabled()) { - /* Disabling a power-of-two disables all larger lengths. */ - if (test_bit(0, cpu->sve_vq_init)) { - error_setg(errp, "cannot disable sve128"); - error_append_hint(errp, "Disabling sve128 results in all " - "vector lengths being disabled.\n"); - error_append_hint(errp, "With SVE enabled, at least one " - "vector length must be enabled.\n"); - return; - } - for (vq =3D 2; vq <=3D ARM_MAX_VQ; vq <<=3D 1) { - if (test_bit(vq - 1, cpu->sve_vq_init)) { - break; - } - } - max_vq =3D vq <=3D ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; - bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq); - } - - max_vq =3D find_last_bit(cpu->sve_vq_map, max_vq) + 1; - } - - /* - * Process the sve-max-vq property. - * Note that we know from the above that no bit above - * sve-max-vq is currently set. - */ - if (cpu->sve_max_vq !=3D 0) { - max_vq =3D cpu->sve_max_vq; - - if (!test_bit(max_vq - 1, cpu->sve_vq_map) && - test_bit(max_vq - 1, cpu->sve_vq_init)) { - error_setg(errp, "cannot disable sve%d", max_vq * 128); - error_append_hint(errp, "The maximum vector length must be " - "enabled, sve-max-vq=3D%d (%d bits)\n", - max_vq, max_vq * 128); - return; - } - - /* Set all bits not explicitly set within sve-max-vq. */ - bitmap_complement(tmp, cpu->sve_vq_init, max_vq); - bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); - } - - /* - * We should know what max-vq is now. Also, as we're done - * manipulating sve-vq-map, we ensure any bits above max-vq - * are clear, just in case anybody looks. - */ - assert(max_vq !=3D 0); - bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq); - - if (kvm_enabled()) { - /* Ensure the set of lengths matches what KVM supports. */ - bitmap_xor(tmp, cpu->sve_vq_map, kvm_supported, max_vq); - if (!bitmap_empty(tmp, max_vq)) { - vq =3D find_last_bit(tmp, max_vq) + 1; - if (test_bit(vq - 1, cpu->sve_vq_map)) { - if (cpu->sve_max_vq) { - error_setg(errp, "cannot set sve-max-vq=3D%d", - cpu->sve_max_vq); - error_append_hint(errp, "This KVM host does not suppor= t " - "the vector length %d-bits.\n", - vq * 128); - error_append_hint(errp, "It may not be possible to use= " - "sve-max-vq with this KVM host. Try " - "using only sve properties.\n"); - } else { - error_setg(errp, "cannot enable sve%d", vq * 128); - error_append_hint(errp, "This KVM host does not suppor= t " - "the vector length %d-bits.\n", - vq * 128); - } - } else { - error_setg(errp, "cannot disable sve%d", vq * 128); - error_append_hint(errp, "The KVM host requires all " - "supported vector lengths smaller " - "than %d bits to also be enabled.\n", - max_vq * 128); - } - return; - } - } else if (tcg_enabled()) { - /* Ensure all required powers-of-two are enabled. */ - for (vq =3D pow2floor(max_vq); vq >=3D 1; vq >>=3D 1) { - if (!test_bit(vq - 1, cpu->sve_vq_map)) { - error_setg(errp, "cannot disable sve%d", vq * 128); - error_append_hint(errp, "sve%d is required as it " - "is a power-of-two length smaller than " - "the maximum, sve%d\n", - vq * 128, max_vq * 128); - return; - } - } - } - - /* - * Now that we validated all our vector lengths, the only question - * left to answer is if we even want SVE at all. - */ - if (!cpu_isar_feature(aa64_sve, cpu)) { - error_setg(errp, "cannot enable sve%d", max_vq * 128); - error_append_hint(errp, "SVE must be enabled to enable vector " - "lengths.\n"); - error_append_hint(errp, "Add sve=3Don to the CPU property list.\n"= ); - return; - } - - /* From now on sve_max_vq is the actual maximum supported length. */ - cpu->sve_max_vq =3D max_vq; -} - -static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *na= me, - void *opaque, Error **errp) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - uint32_t value; - - /* All vector lengths are disabled when SVE is off. */ - if (!cpu_isar_feature(aa64_sve, cpu)) { - value =3D 0; - } else { - value =3D cpu->sve_max_vq; - } - visit_type_uint32(v, name, &value, errp); -} - -static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *na= me, - void *opaque, Error **errp) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - uint32_t max_vq; - - if (!visit_type_uint32(v, name, &max_vq, errp)) { - return; - } - - if (kvm_enabled() && !kvm_arm_sve_supported()) { - error_setg(errp, "cannot set sve-max-vq"); - error_append_hint(errp, "SVE not supported by KVM on this host\n"); - return; - } - - if (max_vq =3D=3D 0 || max_vq > ARM_MAX_VQ) { - error_setg(errp, "unsupported SVE vector length"); - error_append_hint(errp, "Valid sve-max-vq in range [1-%d]\n", - ARM_MAX_VQ); - return; - } - - cpu->sve_max_vq =3D max_vq; -} - -/* - * Note that cpu_arm_get/set_sve_vq cannot use the simpler - * object_property_add_bool interface because they make use - * of the contents of "name" to determine which bit on which - * to operate. - */ -static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - uint32_t vq =3D atoi(&name[3]) / 128; - bool value; - - /* All vector lengths are disabled when SVE is off. */ - if (!cpu_isar_feature(aa64_sve, cpu)) { - value =3D false; - } else { - value =3D test_bit(vq - 1, cpu->sve_vq_map); - } - visit_type_bool(v, name, &value, errp); -} - -static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - uint32_t vq =3D atoi(&name[3]) / 128; - bool value; - - if (!visit_type_bool(v, name, &value, errp)) { - return; - } - - if (value && kvm_enabled() && !kvm_arm_sve_supported()) { - error_setg(errp, "cannot enable %s", name); - error_append_hint(errp, "SVE not supported by KVM on this host\n"); - return; - } - - if (value) { - set_bit(vq - 1, cpu->sve_vq_map); - } else { - clear_bit(vq - 1, cpu->sve_vq_map); - } - set_bit(vq - 1, cpu->sve_vq_init); -} - -static bool cpu_arm_get_sve(Object *obj, Error **errp) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - return cpu_isar_feature(aa64_sve, cpu); -} - -static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - uint64_t t; - - if (value && kvm_enabled() && !kvm_arm_sve_supported()) { - error_setg(errp, "'sve' feature not supported by KVM on this host"= ); - return; - } - - t =3D cpu->isar.id_aa64pfr0; - t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, value); - cpu->isar.id_aa64pfr0 =3D t; -} - -void aarch64_add_sve_properties(Object *obj) -{ - uint32_t vq; - - object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); - - for (vq =3D 1; vq <=3D ARM_MAX_VQ; ++vq) { - char name[8]; - sprintf(name, "sve%d", vq * 128); - object_property_add(obj, name, "bool", cpu_arm_get_sve_vq, - cpu_arm_set_sve_vq, NULL, NULL); - } -} - void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { int arch_val =3D 0, impdef_val =3D 0; @@ -777,8 +453,7 @@ static void aarch64_max_initfn(Object *obj) } =20 aarch64_add_sve_properties(obj); - object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_v= q, - cpu_max_set_sve_max_vq, NULL, NULL); + aarch64_add_sve_properties_max(obj); } =20 static const ARMCPUInfo aarch64_cpus[] =3D { diff --git a/target/arm/kvm/kvm-cpu.c b/target/arm/kvm/kvm-cpu.c index 9f65010c0c..a23831e3c6 100644 --- a/target/arm/kvm/kvm-cpu.c +++ b/target/arm/kvm/kvm-cpu.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qemu-common.h" #include "cpu.h" +#include "cpu-sve.h" #include "hw/core/accel-cpu.h" #include "qapi/error.h" =20 diff --git a/target/arm/meson.build b/target/arm/meson.build index 448e94861f..bad5a659a7 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -13,6 +13,7 @@ arm_ss.add(zlib) =20 arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'cpu64.c', + 'cpu-sve.c', 'gdbstub64.c', )) =20 --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622831038; cv=none; d=zohomail.com; s=zohoarc; b=VvoCj8oovh86BRXPEDqQWvt6VsjIQiOSSc7S2ie8b50IRfznBQONJhO5kGuaZXYQok2G+J0MY3kG/wnWcCAPE6rKZy6O/aIuOjv+vYXFYwl6xLOmSpTcB1pFvAehdpJ88T9BAZtJIpodZFf97B1L1nVcTSAyXLkfX9Zcbc4V07A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622831038; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9CUf/8kmWW8xLQQ+yY0pjmJPzJUFPuD+MEJ2WMvFClI=; b=ZBPHQucNk0eS3Xph947cBl6FL0nSxZMTBioHp1TDc+EE86DbszyAUH3T7o+Gk5ucw175M+1JYjwkpTgVOFZH7xWhcfUz4echjwjdbeE+0Y9OnHPB9Nlq8xxxvZTjWCzyblnZHHWcISLom57JSAlllk4GkmzOFWd9QDH6D6HpNmg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622831038310549.1574015604864; Fri, 4 Jun 2021 11:23:58 -0700 (PDT) Received: from localhost ([::1]:36490 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpEU8-0003HJ-Q2 for importer@patchew.org; Fri, 04 Jun 2021 14:23:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42218) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpESw-0000b4-Us for qemu-devel@nongnu.org; Fri, 04 Jun 2021 14:22:42 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:36584) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpESu-0000J7-Tw for qemu-devel@nongnu.org; Fri, 04 Jun 2021 14:22:42 -0400 Received: by mail-wr1-x432.google.com with SMTP id n4so10210319wrw.3 for ; Fri, 04 Jun 2021 11:22:40 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id b7sm7288622wri.83.2021.06.04.11.22.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 11:22:38 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 85BAB1FFE0; Fri, 4 Jun 2021 16:53:21 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9CUf/8kmWW8xLQQ+yY0pjmJPzJUFPuD+MEJ2WMvFClI=; b=I/eAYba+zTRXFyI/7v2n7HVFEJY4fpYSvErYW7LTPFPYdYjf57isXcijhX73Yseu2J S2PIY/tlsfwNRqfGgckJKhRksm/MTSVZnowDAQdCnEvUTvOfE1UjLKYaEyNRkqebFoI1 OLn9szFJrexJTTnhwXHA7yrGd0bX4NckrOzcSINc/873ikNRFj8P5R12fZoipUKSRfko gUupIC57fsimPOyLX09wb2sx4jv3DNgMHoBK1vS7dOJUQ16fHh0FrWkWBjuFM5mcyzW4 3a1Fwh0KlyUP9Gczy5++gAjV3kFZqmp4v2hlszSJcJphB6E6Lv0Un/cXvDpmO2v+/9wR lrFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9CUf/8kmWW8xLQQ+yY0pjmJPzJUFPuD+MEJ2WMvFClI=; b=IQzaEqLSKiNKIH+CCu4e4TprQr3xHuslpjIIW1EVEqRP8/jE9KDfsUFM7FdXuZTALg M9Vv0DqlGuY1Zfa+XpDqnrXkUXIsH+QRMRzlNhrB3wAmc75jJbwZyOW8YgH3e8ZmJtDh wNwAtkuyRWCP/zDrUtEq4WvpcHLgwZf+OPmNDnlV+p6mA5zzdJx92rQ0/WUaFVJsc4ps 4vuRG8HkyNG9FYVfXTA2l0+iMbXhPEAJ8FPRRHLVM5uRBhO/Lt4MOTb2iXz3mUJ3DEpp HMU9rjczigerg+qHzkf4TlHqSQecFBRSkAPYy/H+zQgZyOO+PAjbBlWBbDFW6Jc6vHfi Q6Pg== X-Gm-Message-State: AOAM531+/c9T6AXSDHDJXbZu5J5PWoyQ3kchJj9edzRA3gxzjDR9l9/c cuB9BQE8+cpvlNJdaqH33ayJsg== X-Google-Smtp-Source: ABdhPJwW9wjHHzPnDVUErFzDjOcdqFa6ixphe68cedWjADpidCW5UOpVRTENixIu2w8Zq0x2Q1OA2g== X-Received: by 2002:adf:a195:: with SMTP id u21mr5128992wru.367.1622830958710; Fri, 04 Jun 2021 11:22:38 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 72/99] target/arm: cpu-sve: rename functions according to module prefix Date: Fri, 4 Jun 2021 16:52:45 +0100 Message-Id: <20210604155312.15902-73-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana external functions have the cpu_sve prefix, while for static functions it can be omitted. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-sve.h | 6 +++--- target/arm/cpu-sve.c | 32 ++++++++++++++++---------------- target/arm/cpu.c | 2 +- target/arm/cpu64.c | 4 ++-- target/arm/kvm/kvm-cpu.c | 2 +- 5 files changed, 23 insertions(+), 23 deletions(-) diff --git a/target/arm/cpu-sve.h b/target/arm/cpu-sve.h index 692509d419..ece36d2a0c 100644 --- a/target/arm/cpu-sve.h +++ b/target/arm/cpu-sve.h @@ -26,12 +26,12 @@ #include "cpu.h" =20 /* called by arm_cpu_finalize_features in realizefn */ -void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp); +void cpu_sve_finalize_features(ARMCPU *cpu, Error **errp); =20 /* add the CPU SVE properties */ -void aarch64_add_sve_properties(Object *obj); +void cpu_sve_add_props(Object *obj); =20 /* add the CPU SVE properties specific to the "MAX" CPU */ -void aarch64_add_sve_properties_max(Object *obj); +void cpu_sve_add_props_max(Object *obj); =20 #endif /* CPU_SVE_H */ diff --git a/target/arm/cpu-sve.c b/target/arm/cpu-sve.c index 129fb9586e..da60330cc2 100644 --- a/target/arm/cpu-sve.c +++ b/target/arm/cpu-sve.c @@ -27,7 +27,7 @@ #include "qapi/visitor.h" #include "cpu-sve.h" =20 -void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) +void cpu_sve_finalize_features(ARMCPU *cpu, Error **errp) { /* * If any vector lengths are explicitly enabled with sve properties, @@ -229,8 +229,8 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) cpu->sve_max_vq =3D max_vq; } =20 -static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *na= me, - void *opaque, Error **errp) +static void get_prop_max_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); uint32_t value; @@ -244,8 +244,8 @@ static void cpu_max_get_sve_max_vq(Object *obj, Visitor= *v, const char *name, visit_type_uint32(v, name, &value, errp); } =20 -static void cpu_max_set_sve_max_vq(Object *obj, Visitor *v, const char *na= me, - void *opaque, Error **errp) +static void set_prop_max_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); uint32_t max_vq; @@ -276,8 +276,8 @@ static void cpu_max_set_sve_max_vq(Object *obj, Visitor= *v, const char *name, * of the contents of "name" to determine which bit on which * to operate. */ -static void cpu_arm_get_sve_vq(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) +static void get_prop_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); uint32_t vq =3D atoi(&name[3]) / 128; @@ -292,8 +292,8 @@ static void cpu_arm_get_sve_vq(Object *obj, Visitor *v,= const char *name, visit_type_bool(v, name, &value, errp); } =20 -static void cpu_arm_set_sve_vq(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) +static void set_prop_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); uint32_t vq =3D atoi(&name[3]) / 128; @@ -317,13 +317,13 @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *= v, const char *name, set_bit(vq - 1, cpu->sve_vq_init); } =20 -static bool cpu_arm_get_sve(Object *obj, Error **errp) +static bool get_prop_sve(Object *obj, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); return cpu_isar_feature(aa64_sve, cpu); } =20 -static void cpu_arm_set_sve(Object *obj, bool value, Error **errp) +static void set_prop_sve(Object *obj, bool value, Error **errp) { ARMCPU *cpu =3D ARM_CPU(obj); uint64_t t; @@ -338,21 +338,21 @@ static void cpu_arm_set_sve(Object *obj, bool value, = Error **errp) cpu->isar.id_aa64pfr0 =3D t; } =20 -void aarch64_add_sve_properties(Object *obj) +void cpu_sve_add_props(Object *obj) { uint32_t vq; =20 - object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve); + object_property_add_bool(obj, "sve", get_prop_sve, set_prop_sve); =20 for (vq =3D 1; vq <=3D ARM_MAX_VQ; ++vq) { char name[8]; sprintf(name, "sve%d", vq * 128); - object_property_add(obj, name, "bool", cpu_arm_get_sve_vq, cpu_arm= _set_sve_vq, NULL, NULL); + object_property_add(obj, name, "bool", get_prop_vq, set_prop_vq, N= ULL, NULL); } } =20 /* properties added for MAX CPU */ -void aarch64_add_sve_properties_max(Object *obj) +void cpu_sve_add_props_max(Object *obj) { - object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_max_v= q, cpu_max_set_sve_max_vq, NULL, NULL); + object_property_add(obj, "sve-max-vq", "uint32", get_prop_max_vq, set_= prop_max_vq, NULL, NULL); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6db37b42d1..e4ad92ffec 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -821,7 +821,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **err= p) =20 #ifdef TARGET_AARCH64 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - arm_cpu_sve_finalize(cpu, &local_err); + cpu_sve_finalize_features(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3a6b7cf5d1..03ed637bdb 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -452,8 +452,8 @@ static void aarch64_max_initfn(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_proper= ty); } =20 - aarch64_add_sve_properties(obj); - aarch64_add_sve_properties_max(obj); + cpu_sve_add_props(obj); + cpu_sve_add_props_max(obj); } =20 static const ARMCPUInfo aarch64_cpus[] =3D { diff --git a/target/arm/kvm/kvm-cpu.c b/target/arm/kvm/kvm-cpu.c index a23831e3c6..09aede9319 100644 --- a/target/arm/kvm/kvm-cpu.c +++ b/target/arm/kvm/kvm-cpu.c @@ -89,7 +89,7 @@ static void host_cpu_instance_init(Object *obj) =20 kvm_arm_set_cpu_features_from_host(cpu); if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - aarch64_add_sve_properties(obj); + cpu_sve_add_props(obj); } arm_cpu_post_init(obj); } --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622827127; cv=none; d=zohomail.com; s=zohoarc; b=NrqF9Z1QHOUpY3opCG9edkr8cNpa//Of3WixtxfEHeseqdQfkOLsNo9xgtZouMqoP87Pn9j86dEkpHJ8qCQYEOT2eokieXmqegL6uRSylRWc4e0jqIdIZYdtdEnrJEimya3J78ze2wvXzoS2qCpS5sa06D6v5XlxqjbJrvw5Vs0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622827127; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ofbUZYQxVSTX2zCLFpcrYT6uJV2+s+AkgpY/MjopHLY=; b=Cf3deNZIGpSwRKxjZ+Xkv8M1H0Qmsy9a6p7zDfcvA0i/g5mZu4gSJiTxd+xs19N2ApyZ/luG6hOhFl0jKjHFqqU9t2R8td+mHTDoMyRIGBzW+/dHeAEkrsXwSfq3CREWE+CnS6oZWSSr3lGy6RjBQLhkDUiDY54D4a2/7AOdiWk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622827127437445.36494655675267; Fri, 4 Jun 2021 10:18:47 -0700 (PDT) Received: from localhost ([::1]:45084 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDT4-0005rv-7c for importer@patchew.org; Fri, 04 Jun 2021 13:18:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33680) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCkn-0008T8-E0 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:02 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:40646) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCke-0002BW-3y for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:01 -0400 Received: by mail-wm1-x330.google.com with SMTP id b145-20020a1c80970000b029019c8c824054so8275642wmd.5 for ; Fri, 04 Jun 2021 09:32:50 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id 32sm8072606wrs.5.2021.06.04.09.32.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:43 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id AB3721FFE1; Fri, 4 Jun 2021 16:53:21 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ofbUZYQxVSTX2zCLFpcrYT6uJV2+s+AkgpY/MjopHLY=; b=TwV39QrtePGMEnp/LpXVEHnxUiUIMF823KJph6yhqs+h9TAfkvJGfBg+4XncSu5WcQ WyuSJ5YG+ye2Y/rGJgPAHgUqYAYJuORrx0VaR1p16/FpPK38oOlrSsfw397Sr8dNa0WE YRUwsHLLpHeJZdXoCbsa1gEnU9sMdAhZe+CPmNLTKLWPI9qCc6SUBWbzRF+V1p7HswM/ 5osonvrjTZuDDgP5XZxKtJectD0A0vMYVwPJojAF6ea85psbV7NtxuMPLhtktoRBP5N2 Pk5TuQcPlHc9WJTZQ9bykUjQcDCJTSTPArI5jmh7HZDiBFQVu4N52y/bNYHSRtjFNvUK jhPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ofbUZYQxVSTX2zCLFpcrYT6uJV2+s+AkgpY/MjopHLY=; b=sFaDA3cG5QdmGzpaGXdJkt7xrR2VW+kY+GhRcm7hsnq38q6kjMVrXd5cYLZHvG5GL1 D4RvPV8eryOsLSz7tNgZeU0mRnMbcMtdKteppVOk9y9vnUbVzwF6FAKEnkOSm4yUUfj6 gLP6pfUCjKm10yrvj+dARwh7ahi4dDApgT9qKVYbn5N0iH6x1mL4GmHZ/9+7yaaOEWOz Wsekdi5kbdjw3xloUBu9Bp9Brkg+Ud6OvGGKDYPlm1lg0a8C3oxHeXuyJOyGKV37mAl+ IUqbBlhnil50OVv+BpiYRXFceGHAi01eFOj0fxiLhFpAA+9Ugr5z9MWPjvGHO4b8sFe/ tFBw== X-Gm-Message-State: AOAM531rDk00aaW/tcfLh/ANGQm9DjcNPkynGvpLg/HXco/bM9hqGeHj uGJO/XaDeYT0kYkt49ePbanqI30BncRtWQ== X-Google-Smtp-Source: ABdhPJysFNdNUT5eeehi2/j3hjLBnxewGfxBtvyhXg3lUKPSCN3LRnEmETuU6peZ9usylYLlutagbA== X-Received: by 2002:a1c:4d09:: with SMTP id o9mr4612477wmh.149.1622824369449; Fri, 04 Jun 2021 09:32:49 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 73/99] target/arm: cpu-sve: split TCG and KVM functionality Date: Fri, 4 Jun 2021 16:52:46 +0100 Message-Id: <20210604155312.15902-74-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana put the KVM-specific and TCG-specific functionality in the respective subdirectories kvm/ and tcg/ Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/kvm/kvm-sve.h | 28 +++++++ target/arm/tcg/tcg-sve.h | 24 ++++++ target/arm/cpu-sve.c | 155 ++++++++++--------------------------- target/arm/kvm/kvm-sve.c | 118 ++++++++++++++++++++++++++++ target/arm/tcg/tcg-sve.c | 81 +++++++++++++++++++ target/arm/kvm/meson.build | 1 + target/arm/tcg/meson.build | 1 + 7 files changed, 296 insertions(+), 112 deletions(-) create mode 100644 target/arm/kvm/kvm-sve.h create mode 100644 target/arm/tcg/tcg-sve.h create mode 100644 target/arm/kvm/kvm-sve.c create mode 100644 target/arm/tcg/tcg-sve.c diff --git a/target/arm/kvm/kvm-sve.h b/target/arm/kvm/kvm-sve.h new file mode 100644 index 0000000000..9a9556b916 --- /dev/null +++ b/target/arm/kvm/kvm-sve.h @@ -0,0 +1,28 @@ +/* + * QEMU AArch64 CPU SVE KVM interface + * + * Copyright 2021 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef KVM_SVE_H +#define KVM_SVE_H + +void kvm_sve_get_supported_lens(ARMCPU *cpu, + unsigned long *kvm_supported); + +void kvm_sve_enable_lens(unsigned long *sve_vq_map, + unsigned long *sve_vq_init, uint32_t max_vq, + unsigned long *kvm_supported); + +uint32_t kvm_sve_disable_lens(unsigned long *sve_vq_map, + unsigned long *sve_vq_init, + unsigned long *kvm_supported, Error **errp); + +bool kvm_sve_validate_lens(unsigned long *sve_vq_map, uint32_t max_vq, + unsigned long *kvm_supported, Error **errp, + uint32_t sve_max_vq); + +#endif /* KVM_SVE_H */ diff --git a/target/arm/tcg/tcg-sve.h b/target/arm/tcg/tcg-sve.h new file mode 100644 index 0000000000..4bed809b9a --- /dev/null +++ b/target/arm/tcg/tcg-sve.h @@ -0,0 +1,24 @@ +/* + * QEMU AArch64 CPU SVE TCG interface + * + * Copyright 2021 SUSE LLC + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef TCG_SVE_H +#define TCG_SVE_H + +/* note: SVE is an AARCH64-only option, only include this for TARGET_AARCH= 64 */ + +void tcg_sve_enable_lens(unsigned long *sve_vq_map, + unsigned long *sve_vq_init, uint32_t max_vq); + +uint32_t tcg_sve_disable_lens(unsigned long *sve_vq_map, + unsigned long *sve_vq_init, Error **errp); + +bool tcg_sve_validate_lens(unsigned long *sve_vq_map, uint32_t max_vq, + Error **errp); + +#endif /* TCG_SVE_H */ diff --git a/target/arm/cpu-sve.c b/target/arm/cpu-sve.c index da60330cc2..5190e4a639 100644 --- a/target/arm/cpu-sve.c +++ b/target/arm/cpu-sve.c @@ -27,6 +27,28 @@ #include "qapi/visitor.h" #include "cpu-sve.h" =20 +#include "tcg/tcg-sve.h" +#include "kvm/kvm-sve.h" + +static bool apply_max_vq(unsigned long *sve_vq_map, unsigned long *sve_vq_= init, + uint32_t max_vq, Error **errp) +{ + DECLARE_BITMAP(tmp, ARM_MAX_VQ); + + if (!test_bit(max_vq - 1, sve_vq_map) && + test_bit(max_vq - 1, sve_vq_init)) { + error_setg(errp, "cannot disable sve%d", max_vq * 128); + error_append_hint(errp, "The maximum vector length must be " + "enabled, sve-max-vq=3D%d (%d bits)\n", + max_vq, max_vq * 128); + return false; + } + /* Set all bits not explicitly set within sve-max-vq. */ + bitmap_complement(tmp, sve_vq_init, max_vq); + bitmap_or(sve_vq_map, sve_vq_map, tmp, max_vq); + return true; +} + void cpu_sve_finalize_features(ARMCPU *cpu, Error **errp) { /* @@ -45,17 +67,11 @@ void cpu_sve_finalize_features(ARMCPU *cpu, Error **err= p) * vector length must be enabled. */ DECLARE_BITMAP(kvm_supported, ARM_MAX_VQ); - DECLARE_BITMAP(tmp, ARM_MAX_VQ); - uint32_t vq, max_vq =3D 0; - - /* Collect the set of vector lengths supported by KVM. */ - bitmap_zero(kvm_supported, ARM_MAX_VQ); - if (kvm_enabled() && kvm_arm_sve_supported()) { - kvm_arm_sve_get_vls(CPU(cpu), kvm_supported); - } else if (kvm_enabled()) { - assert(!cpu_isar_feature(aa64_sve, cpu)); - } + uint32_t max_vq =3D 0; =20 + if (kvm_enabled()) { + kvm_sve_get_supported_lens(cpu, kvm_supported); + } /* * Process explicit sve properties. * From the properties, sve_vq_map implies sve_vq_init. @@ -72,70 +88,28 @@ void cpu_sve_finalize_features(ARMCPU *cpu, Error **err= p) cpu->sve_max_vq * 128); return; } - if (kvm_enabled()) { - /* - * For KVM we have to automatically enable all supported uniti= alized - * lengths, even when the smaller lengths are not all powers-o= f-two. - */ - bitmap_andnot(tmp, kvm_supported, cpu->sve_vq_init, max_vq); - bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); + kvm_sve_enable_lens(cpu->sve_vq_map, cpu->sve_vq_init, max_vq, + kvm_supported); } else if (tcg_enabled()) { - /* Propagate enabled bits down through required powers-of-two.= */ - for (vq =3D pow2floor(max_vq); vq >=3D 1; vq >>=3D 1) { - if (!test_bit(vq - 1, cpu->sve_vq_init)) { - set_bit(vq - 1, cpu->sve_vq_map); - } - } + tcg_sve_enable_lens(cpu->sve_vq_map, cpu->sve_vq_init, max_vq); } } else if (cpu->sve_max_vq =3D=3D 0) { - /* - * No explicit bits enabled, and no implicit bits from sve-max-vq. - */ + /* No explicit bits enabled, and no implicit bits from sve-max-vq.= */ if (!cpu_isar_feature(aa64_sve, cpu)) { /* SVE is disabled and so are all vector lengths. Good. */ return; } - if (kvm_enabled()) { - /* Disabling a supported length disables all larger lengths. */ - for (vq =3D 1; vq <=3D ARM_MAX_VQ; ++vq) { - if (test_bit(vq - 1, cpu->sve_vq_init) && - test_bit(vq - 1, kvm_supported)) { - break; - } - } - max_vq =3D vq <=3D ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; - bitmap_andnot(cpu->sve_vq_map, kvm_supported, - cpu->sve_vq_init, max_vq); - if (max_vq =3D=3D 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) { - error_setg(errp, "cannot disable sve%d", vq * 128); - error_append_hint(errp, "Disabling sve%d results in all " - "vector lengths being disabled.\n", - vq * 128); - error_append_hint(errp, "With SVE enabled, at least one " - "vector length must be enabled.\n"); - return; - } + max_vq =3D kvm_sve_disable_lens(cpu->sve_vq_map, cpu->sve_vq_i= nit, + kvm_supported, errp); } else if (tcg_enabled()) { - /* Disabling a power-of-two disables all larger lengths. */ - if (test_bit(0, cpu->sve_vq_init)) { - error_setg(errp, "cannot disable sve128"); - error_append_hint(errp, "Disabling sve128 results in all " - "vector lengths being disabled.\n"); - error_append_hint(errp, "With SVE enabled, at least one " - "vector length must be enabled.\n"); - return; - } - for (vq =3D 2; vq <=3D ARM_MAX_VQ; vq <<=3D 1) { - if (test_bit(vq - 1, cpu->sve_vq_init)) { - break; - } - } - max_vq =3D vq <=3D ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; - bitmap_complement(cpu->sve_vq_map, cpu->sve_vq_init, max_vq); + max_vq =3D tcg_sve_disable_lens(cpu->sve_vq_map, cpu->sve_vq_i= nit, + errp); + } + if (!max_vq) { + return; } - max_vq =3D find_last_bit(cpu->sve_vq_map, max_vq) + 1; } =20 @@ -146,21 +120,11 @@ void cpu_sve_finalize_features(ARMCPU *cpu, Error **e= rrp) */ if (cpu->sve_max_vq !=3D 0) { max_vq =3D cpu->sve_max_vq; - - if (!test_bit(max_vq - 1, cpu->sve_vq_map) && - test_bit(max_vq - 1, cpu->sve_vq_init)) { - error_setg(errp, "cannot disable sve%d", max_vq * 128); - error_append_hint(errp, "The maximum vector length must be " - "enabled, sve-max-vq=3D%d (%d bits)\n", - max_vq, max_vq * 128); + if (!apply_max_vq(cpu->sve_vq_map, cpu->sve_vq_init, max_vq, + errp)) { return; } - - /* Set all bits not explicitly set within sve-max-vq. */ - bitmap_complement(tmp, cpu->sve_vq_init, max_vq); - bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); } - /* * We should know what max-vq is now. Also, as we're done * manipulating sve-vq-map, we ensure any bits above max-vq @@ -170,46 +134,13 @@ void cpu_sve_finalize_features(ARMCPU *cpu, Error **e= rrp) bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq); =20 if (kvm_enabled()) { - /* Ensure the set of lengths matches what KVM supports. */ - bitmap_xor(tmp, cpu->sve_vq_map, kvm_supported, max_vq); - if (!bitmap_empty(tmp, max_vq)) { - vq =3D find_last_bit(tmp, max_vq) + 1; - if (test_bit(vq - 1, cpu->sve_vq_map)) { - if (cpu->sve_max_vq) { - error_setg(errp, "cannot set sve-max-vq=3D%d", - cpu->sve_max_vq); - error_append_hint(errp, "This KVM host does not suppor= t " - "the vector length %d-bits.\n", - vq * 128); - error_append_hint(errp, "It may not be possible to use= " - "sve-max-vq with this KVM host. Try " - "using only sve properties.\n"); - } else { - error_setg(errp, "cannot enable sve%d", vq * 128); - error_append_hint(errp, "This KVM host does not suppor= t " - "the vector length %d-bits.\n", - vq * 128); - } - } else { - error_setg(errp, "cannot disable sve%d", vq * 128); - error_append_hint(errp, "The KVM host requires all " - "supported vector lengths smaller " - "than %d bits to also be enabled.\n", - max_vq * 128); - } + if (!kvm_sve_validate_lens(cpu->sve_vq_map, max_vq, kvm_supported, + errp, cpu->sve_max_vq)) { return; } } else if (tcg_enabled()) { - /* Ensure all required powers-of-two are enabled. */ - for (vq =3D pow2floor(max_vq); vq >=3D 1; vq >>=3D 1) { - if (!test_bit(vq - 1, cpu->sve_vq_map)) { - error_setg(errp, "cannot disable sve%d", vq * 128); - error_append_hint(errp, "sve%d is required as it " - "is a power-of-two length smaller than " - "the maximum, sve%d\n", - vq * 128, max_vq * 128); - return; - } + if (!tcg_sve_validate_lens(cpu->sve_vq_map, max_vq, errp)) { + return; } } =20 diff --git a/target/arm/kvm/kvm-sve.c b/target/arm/kvm/kvm-sve.c new file mode 100644 index 0000000000..21dfee5b5c --- /dev/null +++ b/target/arm/kvm/kvm-sve.c @@ -0,0 +1,118 @@ +/* + * QEMU ARM CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "cpu.h" +#include "sysemu/kvm.h" +#include "kvm/kvm_arm.h" +#include "kvm/kvm-sve.h" + +void kvm_sve_get_supported_lens(ARMCPU *cpu, unsigned long *kvm_supported) +{ + /* Collect the set of vector lengths supported by KVM. */ + bitmap_zero(kvm_supported, ARM_MAX_VQ); + + if (kvm_arm_sve_supported()) { + kvm_arm_sve_get_vls(CPU(cpu), kvm_supported); + } else { + assert(!cpu_isar_feature(aa64_sve, cpu)); + } +} + +void kvm_sve_enable_lens(unsigned long *sve_vq_map, + unsigned long *sve_vq_init, uint32_t max_vq, + unsigned long *kvm_supported) +{ + /* + * For KVM we have to automatically enable all supported unitialized + * lengths, even when the smaller lengths are not all powers-of-two. + */ + DECLARE_BITMAP(tmp, ARM_MAX_VQ); + + bitmap_andnot(tmp, kvm_supported, sve_vq_init, max_vq); + bitmap_or(sve_vq_map, sve_vq_map, tmp, max_vq); +} + +uint32_t kvm_sve_disable_lens(unsigned long *sve_vq_map, + unsigned long *sve_vq_init, + unsigned long *kvm_supported, Error **errp) +{ + uint32_t max_vq, vq; + + /* Disabling a supported length disables all larger lengths. */ + for (vq =3D 1; vq <=3D ARM_MAX_VQ; ++vq) { + if (test_bit(vq - 1, sve_vq_init) && + test_bit(vq - 1, kvm_supported)) { + break; + } + } + + max_vq =3D vq <=3D ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; + bitmap_andnot(sve_vq_map, kvm_supported, sve_vq_init, max_vq); + + if (max_vq =3D=3D 0 || bitmap_empty(sve_vq_map, max_vq)) { + error_setg(errp, "cannot disable sve%d", vq * 128); + error_append_hint(errp, "Disabling sve%d results in all " + "vector lengths being disabled.\n", + vq * 128); + error_append_hint(errp, "With SVE enabled, at least one " + "vector length must be enabled.\n"); + return 0; + } + + return max_vq; +} + +bool kvm_sve_validate_lens(unsigned long *sve_vq_map, uint32_t max_vq, + unsigned long *kvm_supported, Error **errp, + uint32_t sve_max_vq) +{ + /* Ensure the set of lengths matches what KVM supports. */ + DECLARE_BITMAP(tmp, ARM_MAX_VQ); + uint32_t vq; + + bitmap_xor(tmp, sve_vq_map, kvm_supported, max_vq); + if (bitmap_empty(tmp, max_vq)) { + return true; + } + + vq =3D find_last_bit(tmp, max_vq) + 1; + if (test_bit(vq - 1, sve_vq_map)) { + if (sve_max_vq) { + error_setg(errp, "cannot set sve-max-vq=3D%d", sve_max_vq); + error_append_hint(errp, "This KVM host does not support " + "the vector length %d-bits.\n", vq * 128); + error_append_hint(errp, "It may not be possible to use " + "sve-max-vq with this KVM host. Try " + "using only sve properties.\n"); + } else { + error_setg(errp, "cannot enable sve%d", vq * 128); + error_append_hint(errp, "This KVM host does not support " + "the vector length %d-bits.\n", vq * 128); + } + } else { + error_setg(errp, "cannot disable sve%d", vq * 128); + error_append_hint(errp, "The KVM host requires all " + "supported vector lengths smaller " + "than %d bits to also be enabled.\n", max_vq * 1= 28); + } + return false; +} diff --git a/target/arm/tcg/tcg-sve.c b/target/arm/tcg/tcg-sve.c new file mode 100644 index 0000000000..99cfde1f41 --- /dev/null +++ b/target/arm/tcg/tcg-sve.c @@ -0,0 +1,81 @@ +/* + * QEMU ARM CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "cpu.h" +#include "sysemu/tcg.h" +#include "cpu-sve.h" +#include "tcg-sve.h" + +void tcg_sve_enable_lens(unsigned long *sve_vq_map, + unsigned long *sve_vq_init, uint32_t max_vq) +{ + /* Propagate enabled bits down through required powers-of-two. */ + uint32_t vq; + + for (vq =3D pow2floor(max_vq); vq >=3D 1; vq >>=3D 1) { + if (!test_bit(vq - 1, sve_vq_init)) { + set_bit(vq - 1, sve_vq_map); + } + } +} + +uint32_t tcg_sve_disable_lens(unsigned long *sve_vq_map, + unsigned long *sve_vq_init, Error **errp) +{ + /* Disabling a power-of-two disables all larger lengths. */ + uint32_t max_vq, vq; + + if (test_bit(0, sve_vq_init)) { + error_setg(errp, "cannot disable sve128"); + error_append_hint(errp, "Disabling sve128 results in all " + "vector lengths being disabled.\n"); + error_append_hint(errp, "With SVE enabled, at least one " + "vector length must be enabled.\n"); + return 0; + } + for (vq =3D 2; vq <=3D ARM_MAX_VQ; vq <<=3D 1) { + if (test_bit(vq - 1, sve_vq_init)) { + break; + } + } + max_vq =3D vq <=3D ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; + bitmap_complement(sve_vq_map, sve_vq_init, max_vq); + return max_vq; +} + +bool tcg_sve_validate_lens(unsigned long *sve_vq_map, uint32_t max_vq, + Error **errp) +{ + /* Ensure all required powers-of-two are enabled. */ + uint32_t vq; + + for (vq =3D pow2floor(max_vq); vq >=3D 1; vq >>=3D 1) { + if (!test_bit(vq - 1, sve_vq_map)) { + error_setg(errp, "cannot disable sve%d", vq * 128); + error_append_hint(errp, "sve%d is required as it " + "is a power-of-two length smaller than " + "the maximum, sve%d\n", vq * 128, max_vq * 1= 28); + return false; + } + } + return true; +} diff --git a/target/arm/kvm/meson.build b/target/arm/kvm/meson.build index ef58a29dd7..1ae62bd65c 100644 --- a/target/arm/kvm/meson.build +++ b/target/arm/kvm/meson.build @@ -2,4 +2,5 @@ arm_ss.add(when: 'CONFIG_KVM', if_true: files( 'kvm.c', 'kvm64.c', 'kvm-cpu.c', + 'kvm-sve.c', )) diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 5b36a13a24..c289771e97 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -45,6 +45,7 @@ arm_ss.add(when: ['TARGET_AARCH64','CONFIG_TCG'], if_true= : files( 'mte_helper.c', 'pauth_helper.c', 'sve_helper.c', + 'tcg-sve.c', )) =20 subdir('user') --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622828146; cv=none; d=zohomail.com; s=zohoarc; b=MGV4C4KUZph9QdeZi0vRJ9lG3TKpJdnYcqIeGW+VowfFpDSKZruIe7pPqCsyeIHi+HutLAn6+lw5Uk5JIMry4i7M/c3Iyu6vxeESLxd7YH6ruP6zTWFs6BpCJ/6g2bV5ctp0lEeSJolJZHmFriiRdvDLueZJOWhqw1qUG0csvew= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622828146; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OyxWPhUmqlvRtQOK1rZ3n99TcV2f8SKQ96wxoL9+DN8=; b=SxjXbzyQZQn25rwbiiWa6d1IytdyOlXA5p+UtYu0zc3Xn7zU8Z2HBoh454gsxXZAGUYMLJU+h2t8lH0kLu2ARFh8yM88wnhSQnbi/vfWBK7Jr2Dxj8QQ4wRvI52XH86sUYrzrF4el8PIDMYMRfu3DVQP6ntyNnzwaWjQ1XYT3x4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622828146903812.9525553045479; Fri, 4 Jun 2021 10:35:46 -0700 (PDT) Received: from localhost ([::1]:43926 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDjV-0001qE-R5 for importer@patchew.org; Fri, 04 Jun 2021 13:35:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48794) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpDNM-0008H3-2f for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:52 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:39725) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpDNH-00023P-GO for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:51 -0400 Received: by mail-wr1-x429.google.com with SMTP id l2so10038197wrw.6 for ; Fri, 04 Jun 2021 10:12:45 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id m132sm6351030wmf.10.2021.06.04.10.12.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 10:12:38 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id CAC8E1FFE6; Fri, 4 Jun 2021 16:53:21 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OyxWPhUmqlvRtQOK1rZ3n99TcV2f8SKQ96wxoL9+DN8=; b=BxJmN116dfKYjZlKy++1ajEbL+naUiUruIVUyq8HsrKkI6C0E7jmcGmI8pmBI1wMG8 Rlh+HwvqY/rvxOoJIlbTbh+Vn+kMpRkW15OcCvehSorYhBcTuw4lFOI4/+N96hWofZM8 Ri5mDsKDgsv/jrhl5/byOg+z3E6nI2lq9wSKQ089gRAX88RSQolz19OafQio39zb1TBO AxSaL0smXJ3xdXH5FsJKfSjXdKfdfdFN+PaXtuqwmLmydASyCcCBu/OrpKXCD+okm/K5 8BOTkdDMCysUG7CbZiMnsgc4YjYKR5fYc5IG44GjxbtY+8fltKkhxK54vNaEPhIx51Ic H1Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OyxWPhUmqlvRtQOK1rZ3n99TcV2f8SKQ96wxoL9+DN8=; b=hNzHQWD7qtz1H9Rc0mjtiLNRa2AAugpo24Drd+7DRF/5kwr5Wc++0TJ8RpO6ybUXn5 rjv+wepZ9B23jrxHBO0c9HtuK9hfwMc6iGZ34gzX3nPcNaSPhbML4oslGyGB1IGyTLYE ttOwK0v5T92moVccdUqoC/j0Si3LktixXa6WQA2o2NWjZFoLdjzOvaPygq4CGtamjLLk O8VfLMjjKWi/MtYr9v4H9LF7ZM7TeFY3TtPb3VU++0dQ2iWSyZ+2NLIZ+SNQq6F1KMzD 7h58be7+Ol6zJkwpKGyJ6KIvAwW+WTuqmfIl9gx+fSXaAirjKEvHG1QseYCkBSd3Ogjo vtwg== X-Gm-Message-State: AOAM533+Q35M+Y6SMRFx6gS9SJ3xqXjfXOdoIBGcd+EMQ+nvkVBb4lAg ZSiGiUb88J+XiGTpjWJzBclKZQ== X-Google-Smtp-Source: ABdhPJyu0IeJSDouvD43+NpgBUFrxcj0SOFXdYpom/GmLalQzpOxhKMSeQYEKwRG4qS6BA6VKkNtJw== X-Received: by 2002:a5d:4f8f:: with SMTP id d15mr4815833wru.85.1622826764825; Fri, 04 Jun 2021 10:12:44 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 74/99] target/arm: cpu-sve: make cpu_sve_finalize_features return bool Date: Fri, 4 Jun 2021 16:52:47 +0100 Message-Id: <20210604155312.15902-75-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana return false on error, true on success. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-sve.h | 2 +- target/arm/cpu-sve.c | 17 +++++++++-------- target/arm/cpu.c | 3 +-- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu-sve.h b/target/arm/cpu-sve.h index ece36d2a0c..6ab74b1d8f 100644 --- a/target/arm/cpu-sve.h +++ b/target/arm/cpu-sve.h @@ -26,7 +26,7 @@ #include "cpu.h" =20 /* called by arm_cpu_finalize_features in realizefn */ -void cpu_sve_finalize_features(ARMCPU *cpu, Error **errp); +bool cpu_sve_finalize_features(ARMCPU *cpu, Error **errp); =20 /* add the CPU SVE properties */ void cpu_sve_add_props(Object *obj); diff --git a/target/arm/cpu-sve.c b/target/arm/cpu-sve.c index 5190e4a639..24bffbba8b 100644 --- a/target/arm/cpu-sve.c +++ b/target/arm/cpu-sve.c @@ -49,7 +49,7 @@ static bool apply_max_vq(unsigned long *sve_vq_map, unsig= ned long *sve_vq_init, return true; } =20 -void cpu_sve_finalize_features(ARMCPU *cpu, Error **errp) +bool cpu_sve_finalize_features(ARMCPU *cpu, Error **errp) { /* * If any vector lengths are explicitly enabled with sve properties, @@ -86,7 +86,7 @@ void cpu_sve_finalize_features(ARMCPU *cpu, Error **errp) "length, sve-max-vq=3D%d (%d bits)\n", max_vq * 128, cpu->sve_max_vq, cpu->sve_max_vq * 128); - return; + return false; } if (kvm_enabled()) { kvm_sve_enable_lens(cpu->sve_vq_map, cpu->sve_vq_init, max_vq, @@ -98,7 +98,7 @@ void cpu_sve_finalize_features(ARMCPU *cpu, Error **errp) /* No explicit bits enabled, and no implicit bits from sve-max-vq.= */ if (!cpu_isar_feature(aa64_sve, cpu)) { /* SVE is disabled and so are all vector lengths. Good. */ - return; + return true; } if (kvm_enabled()) { max_vq =3D kvm_sve_disable_lens(cpu->sve_vq_map, cpu->sve_vq_i= nit, @@ -108,7 +108,7 @@ void cpu_sve_finalize_features(ARMCPU *cpu, Error **err= p) errp); } if (!max_vq) { - return; + return false; } max_vq =3D find_last_bit(cpu->sve_vq_map, max_vq) + 1; } @@ -122,7 +122,7 @@ void cpu_sve_finalize_features(ARMCPU *cpu, Error **err= p) max_vq =3D cpu->sve_max_vq; if (!apply_max_vq(cpu->sve_vq_map, cpu->sve_vq_init, max_vq, errp)) { - return; + return false; } } /* @@ -136,11 +136,11 @@ void cpu_sve_finalize_features(ARMCPU *cpu, Error **e= rrp) if (kvm_enabled()) { if (!kvm_sve_validate_lens(cpu->sve_vq_map, max_vq, kvm_supported, errp, cpu->sve_max_vq)) { - return; + return false; } } else if (tcg_enabled()) { if (!tcg_sve_validate_lens(cpu->sve_vq_map, max_vq, errp)) { - return; + return false; } } =20 @@ -153,11 +153,12 @@ void cpu_sve_finalize_features(ARMCPU *cpu, Error **e= rrp) error_append_hint(errp, "SVE must be enabled to enable vector " "lengths.\n"); error_append_hint(errp, "Add sve=3Don to the CPU property list.\n"= ); - return; + return false; } =20 /* From now on sve_max_vq is the actual maximum supported length. */ cpu->sve_max_vq =3D max_vq; + return true; } =20 static void get_prop_max_vq(Object *obj, Visitor *v, const char *name, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e4ad92ffec..0b20faaca0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -821,8 +821,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **err= p) =20 #ifdef TARGET_AARCH64 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - cpu_sve_finalize_features(cpu, &local_err); - if (local_err !=3D NULL) { + if (!cpu_sve_finalize_features(cpu, &local_err)) { error_propagate(errp, local_err); return; } --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622823036; cv=none; d=zohomail.com; s=zohoarc; b=KzgQw4SnPAwY9l2KZGmgadnykXcHciWDvL0EJZtBAvpMHFXpoCUGhzpZfP9uFPUVCWkPL/Ea0gxUiFdq2efPe94BBLkx/sW3+lRWlEg0hUsYOYU7YyajPbpgFgjZjGQGMYwALCCyEope+oZnBE5X8sLHd8mg8oTjn+vgyb+CKnE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622823036; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5gJQqbGfLehWu6/WKjXXSxpXerROzKZPZuw1dGRbuWs=; b=HIWGY1smPsTx0bkAeds/G3W4e9Ys/q7UhPItQ7d4IX8KfEugqTF9PnAGNapGVewBPj1AAUrSTpsJt6Tx+DTmGbSAqEjeKiv0BkkGYWsnQMzE2ulUC9jqfmIVQ5DBSqDa+gKoxY39UgS0V6WJlk39Cfm+YNosYgdFgEzeKNINpF0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622823036779845.3147364919199; Fri, 4 Jun 2021 09:10:36 -0700 (PDT) Received: from localhost ([::1]:36928 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCP5-0003XS-Ob for importer@patchew.org; Fri, 04 Jun 2021 12:10:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44952) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8t-0003iU-Vj for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:52 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:35601) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8k-0000FN-08 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:51 -0400 Received: by mail-wr1-x42b.google.com with SMTP id m18so9808618wrv.2 for ; Fri, 04 Jun 2021 08:53:41 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id a15sm8466956wrs.63.2021.06.04.08.53.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:31 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id E274D1FF96; Fri, 4 Jun 2021 16:53:21 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5gJQqbGfLehWu6/WKjXXSxpXerROzKZPZuw1dGRbuWs=; b=ecI5C9iHpGahiuAd6kGHn2T1Vgm+O82KxDUcwAyMKnqWUORmt2zoxH498n4KK8Pmbs qfnhh8mUH35HxneeHDpcEaF/PjZfwvukOVx0lbCVg+fTCZqRwQFdnjYU0HvYOnmXH7ZZ cAICKEU71eYBaXKMOl9Ch/GcR0xjTCZgHwOW3LNPMB8ABrok3E5oTuUgwLDRu0G+e0zN hfOJgwGktA/O1MC2zqXfS1kwKunato2WTFHuIhJWqWCbDN4EGFpFVW6UAVW/E/oinmVB 4jSd+pAtEyn5tfiSs8fhR6tmtkZtmUhEpyWARSOz4oZMqvQBAGSUCRzqv8tH/PoPeHVe AxbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5gJQqbGfLehWu6/WKjXXSxpXerROzKZPZuw1dGRbuWs=; b=E9RkODmx6pE+ymtoA5KcvJ9GXkd+ge4Nm+bd2YKPfgh1ogVZsp+VU3fKieXZTnn4Yz +zIjVr53pPxwfo25FEV5NK4+G7rQJ9dB1KTXCwv0vMnesxx1C6EwSMWWJHjt9RxqgD0W r0WrSefhyWk6njd5Omh4xgKrVo6AJ6J3QEowWrXFNFStKYdxHHkdg7XZgNxw62XPkIrQ 6ntN90lcDIT0Rd19RoBaABke41oZIroTJVHtBxcjd5gU+bnTnFQBd9iZlsexQpUmZKI7 J81s/MxqgJhyun3ND72NifrpCeGwgggEU8fw26kx1BhoQQ8jJPLZ02/6l858FBSauoXe Cy8Q== X-Gm-Message-State: AOAM5304w6XQNwvXyUWic9kT+Sq7tNIryXRRBUgivMmRNPtLgtS8O952 YVIeZ1GGiRi1dIXQ+VCtWZN3+A== X-Google-Smtp-Source: ABdhPJy6FsJlKu+8lAGw7npdL0tsj5q5RDxAR5Y95f+MtvZ99/q5SzbuXO5UzRNL8+UcmBd8/f6HPA== X-Received: by 2002:adf:fe8c:: with SMTP id l12mr4722858wrr.26.1622822020659; Fri, 04 Jun 2021 08:53:40 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 75/99] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64 Date: Fri, 4 Jun 2021 16:52:48 +0100 Message-Id: <20210604155312.15902-76-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana when TARGET_AARCH64 is not defined, it is helpful to make is_aa64() and arm_el_is_aa64 macros defined to "false". This way we can make more code TARGET_AARCH64-only. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 37 ++++++++++++++++++++++++------------- 1 file changed, 24 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b9b9bd8b01..8614948543 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1060,6 +1060,11 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigne= d vq); void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el, bool el0_a64); =20 +static inline bool is_a64(CPUARMState *env) +{ + return env->aarch64; +} + /* * SVE registers are encoded in KVM's memory in an endianness-invariant fo= rmat. * The byte at offset i from the start of the in-memory representation con= tains @@ -1089,7 +1094,10 @@ static inline void aarch64_sve_narrow_vq(CPUARMState= *env, unsigned vq) { } static inline void aarch64_sve_change_el(CPUARMState *env, int o, int n, bool a) { } -#endif + +#define is_a64(env) ((void)env, false) + +#endif /* TARGET_AARCH64 */ =20 void aarch64_sync_32_to_64(CPUARMState *env); void aarch64_sync_64_to_32(CPUARMState *env); @@ -1098,11 +1106,6 @@ int fp_exception_el(CPUARMState *env, int cur_el); int sve_exception_el(CPUARMState *env, int cur_el); uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); =20 -static inline bool is_a64(CPUARMState *env) -{ - return env->aarch64; -} - /* you can call this signal handler from your SIGBUS and SIGSEGV signal handlers to inform the virtual CPU of exceptions. non zero is returned if the signal was handled by the virtual CPU. */ @@ -2212,13 +2215,7 @@ static inline bool arm_is_el2_enabled(CPUARMState *e= nv) } #endif =20 -/** - * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. - * E.g. when in secure state, fields in HCR_EL2 are suppressed, - * "for all purposes other than a direct read or write access of HCR_EL2." - * Not included here is HCR_RW. - */ -uint64_t arm_hcr_el2_eff(CPUARMState *env); +#ifdef TARGET_AARCH64 =20 /* Return true if the specified exception level is running in AArch64 stat= e. */ static inline bool arm_el_is_aa64(CPUARMState *env, int el) @@ -2253,6 +2250,20 @@ static inline bool arm_el_is_aa64(CPUARMState *env, = int el) return aa64; } =20 +#else + +#define arm_el_is_aa64(env, el) ((void)env, (void)el, false) + +#endif /* TARGET_AARCH64 */ + +/** + * arm_hcr_el2_eff(): Return the effective value of HCR_EL2. + * E.g. when in secure state, fields in HCR_EL2 are suppressed, + * "for all purposes other than a direct read or write access of HCR_EL2." + * Not included here is HCR_RW. + */ +uint64_t arm_hcr_el2_eff(CPUARMState *env); + /* Function for determing whether guest cp register reads and writes should * access the secure or non-secure bank of a cp register. When EL3 is * operating in AArch32 state, the NS-bit determines whether the secure --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622824318; cv=none; d=zohomail.com; s=zohoarc; b=Fdm5eyQnkZfpRngIzThQGZG3Ini4Vg6iz2bld8/gk0MqppfL5bIhkKbTIJCGuA6inB5vG9mLUOHabtDeBCNSp8tdRpWWYolqmIlKqgrLqi4rdH/niVasChIHGXGSJPrk33QGjfVQI8jqK+bBMp4xja5cT57eWypp5ntAyhhCNfM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622824318; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aJVHeJ+pGUaeyhH82Xlk1CVXigUjkgZJpWNOfvUWY7I=; b=VK5Y94JSqMQ86rR/X38LtaTTLDVONuyXldTsAUYkUAp/+bqB+XqG8/Ti0lQ7XoirImVfEq9l/ASMchCsoDWOvE3oiWDikNyGEK6VDypv96lUlWpkNWLpAKkTuy+kgLWV2pohqt59Vxc4K42KL9uAQabwGyPc2UuMrfkzIuKLSes= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162282431855678.76981701403543; Fri, 4 Jun 2021 09:31:58 -0700 (PDT) Received: from localhost ([::1]:53726 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCjl-00047M-RH for importer@patchew.org; Fri, 04 Jun 2021 12:31:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51914) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCRM-00033k-5G for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:56 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:54183) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCRF-0003qI-Jr for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:55 -0400 Received: by mail-wm1-x32c.google.com with SMTP id h3so5705257wmq.3 for ; Fri, 04 Jun 2021 09:12:49 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id h1sm10457784wmq.0.2021.06.04.09.12.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:12:43 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 0ECFD1FFE7; Fri, 4 Jun 2021 16:53:22 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aJVHeJ+pGUaeyhH82Xlk1CVXigUjkgZJpWNOfvUWY7I=; b=PY8oliISMAt52zE7hZsr9LggbMNl1bp9EeWSqY8xK51X9QvcsR4jbQqJbQvGts43Po AKGV6IsvAZ1fl/YZCtcVQSsC0chw76tmhbYghNA4/Oxtz41KX5X/ZxlaC56LrxqVHx8U PbxzVKYdqS23JEOZwJpWdieQn5VXVJeYWZsEVB9nBCQPJH/hgwgFUBzNdeNWT2tRvAgN C06ChacCiSspBaOL1N3IaD/TGjCEdPD2zx6DWx4zFBgqo6RaTeUbGE+PbLaH6u71ZV3l Y9X8kTLT9QhEePgvfrvon9MjUpc5gg0oeRPI1jwbWLtoYe/ZUJDUUzx5nxr9FjB8ZkQW 4ZNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aJVHeJ+pGUaeyhH82Xlk1CVXigUjkgZJpWNOfvUWY7I=; b=XF8Eu1qyzk8okgk4HQXXYqREl79WGaGgBM5uxy12Mcvn9sGvP7IDYXQgNuif69Txs0 +4FVgRkBCE9tnrXciWlLbBilu6nGuAYe8IoFZrimAYDzjX2ltMO/U48BFsRkTbMNzy1O 6iCZo8mekN7HMwJ1ygJ7T6SZmMcBfD5t+aiUfyUo6R2c7zB1jW3SKzmUh4GuqhwFcBva VZav2VX+B26DdCpYOdsfC8rWC5A8JJZ310jG6had0MKVI7ggvbKzwC3LKhOy/1vbVOUZ kf3ZE95WzivSDJ0G2FqfTTW65LTFqp/d8XndEBG5QWYmfuYB/YDNpF0Vyrg/48j+RG4T fjPA== X-Gm-Message-State: AOAM533QJwdNnI4z2LSc0iZ02UYpJ0wr1uaehiCe2U4hEidQq45hh1qm L0SndWG1+aUMYHENp3zI+3BZmg== X-Google-Smtp-Source: ABdhPJz0QBWmax7VXt+wuolZVhD6Q26mlg/JFKKYs17/UwILdzxHzv50D3fhS+HhLX5ZjjfajL2nrg== X-Received: by 2002:a1c:4d13:: with SMTP id o19mr4474528wmh.100.1622823168394; Fri, 04 Jun 2021 09:12:48 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 76/99] target/arm: restrict rebuild_hflags_a64 to TARGET_AARCH64 Date: Fri, 4 Jun 2021 16:52:49 +0100 Message-Id: <20210604155312.15902-77-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana this work is in preparation of making sve_zcr_len_for_el AARCH64-only. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- v14 - fix merge failure with CPUARMTBflags update --- target/arm/helper-a64.h | 2 ++ target/arm/helper.h | 1 - target/arm/tcg/helper.c | 12 ++++++++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 7b706571bb..c89406e656 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -118,3 +118,5 @@ DEF_HELPER_FLAGS_2(st2g_stub, TCG_CALL_NO_WG, void, env= , i64) DEF_HELPER_FLAGS_2(ldgm, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_3(stgm, TCG_CALL_NO_WG, void, env, i64, i64) DEF_HELPER_FLAGS_3(stzgm_tags, TCG_CALL_NO_WG, void, env, i64, i64) + +DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) diff --git a/target/arm/helper.h b/target/arm/helper.h index 23ccb0f72f..e8df4f7625 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -94,7 +94,6 @@ DEF_HELPER_FLAGS_1(rebuild_hflags_m32_newel, TCG_CALL_NO_= RWG, void, env) DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int) DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int) -DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) =20 DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, tl, i32, i32, = i32) =20 diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index 38cc7c6a3d..7136c82795 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -999,6 +999,8 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *en= v, int fp_el, return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags); } =20 +#ifdef TARGET_AARCH64 + static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_e= l, ARMMMUIdx mmu_idx) { @@ -1122,6 +1124,14 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState = *env, int el, int fp_el, return rebuild_hflags_common(env, fp_el, mmu_idx, flags); } =20 +#else + +QEMU_ERROR("this should have been optimized away!") +CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, + ARMMMUIdx mmu_idx); + +#endif /* TARGET_AARCH64 */ + static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env) { int el =3D arm_current_el(env); @@ -1183,6 +1193,7 @@ void HELPER(rebuild_hflags_a32)(CPUARMState *env, int= el) env->hflags =3D rebuild_hflags_a32(env, fp_el, mmu_idx); } =20 +#ifdef TARGET_AARCH64 void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el) { int fp_el =3D fp_exception_el(env, el); @@ -1190,6 +1201,7 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env, int= el) =20 env->hflags =3D rebuild_hflags_a64(env, el, fp_el, mmu_idx); } +#endif /* TARGET_AARCH64 */ =20 static inline void assert_hflags_rebuild_correctly(CPUARMState *env) { --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622822759; cv=none; d=zohomail.com; s=zohoarc; b=maV+TV/AbBXXWn01eMZasxJXtUqfA0B4Jl3Pr0Apr69hi1DphN5wJDHTIQe/e26wX78mRZ6ArerLkirXcWkCXQyq5bK9xwMD2HCv3XokZ1xb+7zlVtcj8u11yGeyXu9h+8eSP5bT4Hw3+KgXei8MVidxUVXCQ1TCMMY8WJBTlmU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622822759; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PvoZ38UPnJd1eKmSeIml7qGU1C99SJRJFwjVwPNmxyQ=; b=Ey0VpoVOr+T/lMCs+H9zj7+wJnPDX4z6YWQaWNKR9XXhd4wKiVbNeRVIZmx6hNYBbAAsUZPiETc+iao5GDl8+v9Rg/qptqhAcqq8v7XDvCl8TjOcHWkQWJLEPSwOOrOEYsnez8VsLWOTwPyHOEUl7MkvGnUzd8xOlT2jUl3IKKA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622822759441737.9846122688882; Fri, 4 Jun 2021 09:05:59 -0700 (PDT) Received: from localhost ([::1]:55134 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCKc-0004i3-8c for importer@patchew.org; Fri, 04 Jun 2021 12:05:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44740) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8h-0003JE-Fg for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:39 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:43961) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8f-0000BZ-7u for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:39 -0400 Received: by mail-wr1-x434.google.com with SMTP id u7so4356061wrs.10 for ; Fri, 04 Jun 2021 08:53:36 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id k5sm7410470wrv.85.2021.06.04.08.53.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:31 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 2B8701FFE8; Fri, 4 Jun 2021 16:53:22 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PvoZ38UPnJd1eKmSeIml7qGU1C99SJRJFwjVwPNmxyQ=; b=WhDJQAnY3k93ah2JXs8svrOJqarM9rzDCIGg2lCLXaLb1MB+qwEKlXbJUck6ARlEMU xkxDelggXdNRmv7U9pZciDXaJ7AHDQMSSuYUsEGQzxwtAoOz1L0n+U5WuI1LZ2pEMK0s AALde1wF1pJG+vxWOF0dTy7glllusqHIxpV+u0gpMNkmljll/GsDgiYTeEJ8xVQIrKDa LhpH98TFSn/UFhGsUlpc+28UClrKMaNcIvyYKXc/Tejf3BCk98VOaY5AMImwgvZqutk8 zVtBQKwwtZcA6tjJbioIbqEfkvrqxW/gQMA1UaIwkyi6gR7sQ4jQeFgvHrRdp89q+gpZ Z+QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PvoZ38UPnJd1eKmSeIml7qGU1C99SJRJFwjVwPNmxyQ=; b=Rn0dp0UJd4ZPgqUJ881yRw6AyKhL+SUr4JfBFubELlZ4BYGLXvABvKEehEZgAVv5kN w+B6q/F4RjX96nzc3ZPfS+RBtUg8Kc+vTFAVuCE7VWXArMumv3zeZlPpCtx/NPs0Obft +Ja7wNRJH2MYlKi1yeg8wvQ9tWUpIlC1ZPW+FxYQuILK55RYaq5l7KO4lBvjf5LuIbC2 EDAvhgHCNY0G7B+823XqXvZzxNad/kI3ZbpbRi+gIH0rfrp/uQ/uf+k39Lp8Tnx3RIFI wGBCgTS0NYDdgW9xTl8ssXbFZ0yWdgUTFFETD41lpTJ3fEvIXM6ETRY6MAGkVinCCLlT xYPA== X-Gm-Message-State: AOAM530ZK52WGdQ/pFsxZXObiQdXNxdYj4z5nBe/Nriufy5wg7V5EGhG CVtxHBhjkNQlLil76hGuoK+9kg== X-Google-Smtp-Source: ABdhPJzd71KTg8NS+O7HlSHid/SqIqWQggSrjeGg4w0PjiY2HoSfVdHKWbTz/EXFKyI+FjMphwLZkw== X-Received: by 2002:a5d:50ca:: with SMTP id f10mr4460353wrt.411.1622822015734; Fri, 04 Jun 2021 08:53:35 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 77/99] target/arm: arch_dump: restrict ELFCLASS64 to AArch64 Date: Fri, 4 Jun 2021 16:52:50 +0100 Message-Id: <20210604155312.15902-78-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana this will allow us to restrict more code to TARGET_AARCH64 Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- v16 - fix conflict now notes in arm_sysemu_ops --- target/arm/arch_dump.c | 12 +++++++----- target/arm/cpu.c | 2 ++ roms/u-boot | 2 +- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 0184845310..9cc75a6fda 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -23,6 +23,8 @@ #include "elf.h" #include "sysemu/dump.h" =20 +#ifdef TARGET_AARCH64 + /* struct user_pt_regs from arch/arm64/include/uapi/asm/ptrace.h */ struct aarch64_user_regs { uint64_t regs[31]; @@ -141,7 +143,6 @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFun= ction f, return 0; } =20 -#ifdef TARGET_AARCH64 static off_t sve_zreg_offset(uint32_t vq, int n) { off_t off =3D sizeof(struct aarch64_user_sve_header); @@ -229,7 +230,6 @@ static int aarch64_write_elf64_sve(WriteCoreDumpFunctio= n f, =20 return 0; } -#endif =20 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, void *opaque) @@ -272,15 +272,15 @@ int arm_cpu_write_elf64_note(WriteCoreDumpFunction f,= CPUState *cs, return ret; } =20 -#ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sve, cpu)) { ret =3D aarch64_write_elf64_sve(f, env, cpuid, s); } -#endif =20 return ret; } =20 +#endif /* TARGET_AARCH64 */ + /* struct pt_regs from arch/arm/include/asm/ptrace.h */ struct arm_user_regs { uint32_t regs[17]; @@ -449,12 +449,14 @@ ssize_t cpu_get_note_size(int class, int machine, int= nr_cpus) size_t note_size; =20 if (class =3D=3D ELFCLASS64) { +#ifdef TARGET_AARCH64 note_size =3D AARCH64_PRSTATUS_NOTE_SIZE; note_size +=3D AARCH64_PRFPREG_NOTE_SIZE; -#ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sve, cpu)) { note_size +=3D AARCH64_SVE_NOTE_SIZE(&cpu->env); } +#else + return -1; /* unsupported */ #endif } else { note_size =3D ARM_PRSTATUS_NOTE_SIZE; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0b20faaca0..b297d0e6aa 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1380,7 +1380,9 @@ static const struct SysemuCPUOps arm_sysemu_ops =3D { .get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, +#ifdef TARGET_AARCH64 .write_elf64_note =3D arm_cpu_write_elf64_note, +#endif .virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian, .legacy_vmsd =3D &vmstate_arm_cpu, }; diff --git a/roms/u-boot b/roms/u-boot index b46dd116ce..d3689267f9 160000 --- a/roms/u-boot +++ b/roms/u-boot @@ -1 +1 @@ -Subproject commit b46dd116ce03e235f2a7d4843c6278e1da44b5e1 +Subproject commit d3689267f92c5956e09cc7d1baa4700141662bff --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622824718; cv=none; d=zohomail.com; s=zohoarc; b=hoVEUl8CasRjm2mWWTilLn7Co6oKgB6HoMdxpazqFWTGBmDDB/SJ/qikEiSN6FGxY7Wpv/EsVaUJmWiL6SYIUIzcsubYnZutQGac4v6jHkzMsk+np386uAw002aic3hLtu6yU77A77zQeoTZnLqBBakLPuel/J9yKbEDnEsIbM4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622824718; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+xCvg7WwfIT24y4D/0f7rlElM8hXlhFx8JmBGskyndc=; b=h3pdEct7lYZFV6ddoBATXj6ZINm3yFIxDWgeGiY7Cg+iBKtulEpc/4cvzOAXIYSHs/+yF08AXeMpYOvWZPeYW3oKsJGxUjPTaQnkH//TuemLtK0brwYqscQ0e6HPnIjeWeDi1ADRRoH04RRiI/cIvrdGVQ9WU7stulXQkNlUjcQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16228247181461001.7536670060606; Fri, 4 Jun 2021 09:38:38 -0700 (PDT) Received: from localhost ([::1]:47268 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCqC-00029z-Nt for importer@patchew.org; Fri, 04 Jun 2021 12:38:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48466) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCHs-00089R-L4 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:09 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:40491) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHa-0005nd-BT for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:04 -0400 Received: by mail-wm1-x32e.google.com with SMTP id b145-20020a1c80970000b029019c8c824054so8223342wmd.5 for ; Fri, 04 Jun 2021 09:02:49 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id f5sm7980459wrf.22.2021.06.04.09.02.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:43 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 5340A1FFE9; Fri, 4 Jun 2021 16:53:22 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+xCvg7WwfIT24y4D/0f7rlElM8hXlhFx8JmBGskyndc=; b=HRFEWZ53PHocg/8Rr20fOP1MAwcz1r4ZKTi3MhV1ndCca5LV5redkEYyQtAiRH+EbI MFtHV52I1iWzjRuUKOfMTqbBNQgcbsZ4bYZBxiNdmjnh1+ZFdcqCtfwaDD1GPOp0jZRW IQHJilAjJkwldjASwhqFIyM8YZkYanfxXXRpHCYo5AADfiZqsrl0eP3gEFeYh7X0AjCu FmNVGhYUF4zrYruH26umT+MUybXwQT+/+IGLUO4PB8hhxYbRO+HypxNTweRi05D9exA2 ToWOcP0cx/MYJwZwncCai6yracmSRrzMaZawgTN5+lex82VD+bgt6iIWv3ZQGXC0nfl+ E12A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+xCvg7WwfIT24y4D/0f7rlElM8hXlhFx8JmBGskyndc=; b=JPwbMaB5ezeqRR79Og0ZnPTXPL4CJSzA7EEM5jqckdlDcpgB06xgQZR2Jb00ybnMde 5u1R+unbisRY+zdbfMCY+EwDZSOesSpKPiGcS27/4wJNZt5l05NJ8U7kfNGUqh7WfL67 ctdfHRlld0cemeihnWeUdbwzQh7IrRsuohur5XIYgPvNl6PIAFxP05w3GMhl70r6L/S3 vdgDi4trt5XSKpooF6JAktZ+PYj4dHICGTSbO5ByFJeSYfsh+H2F7osXa923AsUUcL1Y gkp05xPtfXC27I5wfZno0O16VBtJIt0ZrwEA9mKf5OJGUrAMWd6EL1VN7QF7JKpH2ltc aErg== X-Gm-Message-State: AOAM530JQnAbutE3NQRxBAWUHtJJQpWDdHvNJ6cYwwZc+CILUGmY8mmG FZuHUaROU3S4ze7D0AHWFDXgFQ== X-Google-Smtp-Source: ABdhPJxDLyWyqnBpswAxsX198ysw2KHy7Ibz9jyZHnv8T7fYyKC5dN67EU0boQe+WsrC/7aiEmbQbw== X-Received: by 2002:a7b:c34a:: with SMTP id l10mr4393788wmj.46.1622822568533; Fri, 04 Jun 2021 09:02:48 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 78/99] target/arm: cpu-exceptions, cpu-exceptions-aa64: new modules Date: Fri, 4 Jun 2021 16:52:51 +0100 Message-Id: <20210604155312.15902-79-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana after restricting AArch64-specific code to TARGET_AARCH64 builds, we can now extract the exception handling code from cpu-sysemu, and split its AArch64-specific part into its own module. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-exceptions-aa64.h | 28 ++ target/arm/cpu-exceptions-aa64.c | 276 +++++++++++++ target/arm/cpu-exceptions.c | 445 ++++++++++++++++++++ target/arm/cpu-sysemu.c | 672 ------------------------------- target/arm/cpu-user.c | 1 + target/arm/meson.build | 5 + 6 files changed, 755 insertions(+), 672 deletions(-) create mode 100644 target/arm/cpu-exceptions-aa64.h create mode 100644 target/arm/cpu-exceptions-aa64.c create mode 100644 target/arm/cpu-exceptions.c diff --git a/target/arm/cpu-exceptions-aa64.h b/target/arm/cpu-exceptions-a= a64.h new file mode 100644 index 0000000000..64f800a15d --- /dev/null +++ b/target/arm/cpu-exceptions-aa64.h @@ -0,0 +1,28 @@ +/* + * QEMU AArch64 CPU Exceptions Sysemu code + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#ifndef CPU_EXCEPTIONS_AA64_H +#define CPU_EXCEPTIONS_AA64_H + +#include "cpu.h" + +void arm_cpu_do_interrupt_aarch64(CPUState *cs); + +#endif /* CPU_EXCEPTIONS_AA64_H */ diff --git a/target/arm/cpu-exceptions-aa64.c b/target/arm/cpu-exceptions-a= a64.c new file mode 100644 index 0000000000..7daaba0426 --- /dev/null +++ b/target/arm/cpu-exceptions-aa64.c @@ -0,0 +1,276 @@ +/* + * QEMU AArch64 CPU Exceptions Sysemu code + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "cpu.h" +#include "internals.h" +#include "sysemu/tcg.h" + +#include "cpu-exceptions-aa64.h" + +static int aarch64_regnum(CPUARMState *env, int aarch32_reg) +{ + /* + * Return the register number of the AArch64 view of the AArch32 + * register @aarch32_reg. The CPUARMState CPSR is assumed to still + * be that of the AArch32 mode the exception came from. + */ + int mode =3D env->uncached_cpsr & CPSR_M; + + switch (aarch32_reg) { + case 0 ... 7: + return aarch32_reg; + case 8 ... 12: + return mode =3D=3D ARM_CPU_MODE_FIQ ? aarch32_reg + 16 : aarch32_r= eg; + case 13: + switch (mode) { + case ARM_CPU_MODE_USR: + case ARM_CPU_MODE_SYS: + return 13; + case ARM_CPU_MODE_HYP: + return 15; + case ARM_CPU_MODE_IRQ: + return 17; + case ARM_CPU_MODE_SVC: + return 19; + case ARM_CPU_MODE_ABT: + return 21; + case ARM_CPU_MODE_UND: + return 23; + case ARM_CPU_MODE_FIQ: + return 29; + default: + g_assert_not_reached(); + } + case 14: + switch (mode) { + case ARM_CPU_MODE_USR: + case ARM_CPU_MODE_SYS: + case ARM_CPU_MODE_HYP: + return 14; + case ARM_CPU_MODE_IRQ: + return 16; + case ARM_CPU_MODE_SVC: + return 18; + case ARM_CPU_MODE_ABT: + return 20; + case ARM_CPU_MODE_UND: + return 22; + case ARM_CPU_MODE_FIQ: + return 30; + default: + g_assert_not_reached(); + } + case 15: + return 31; + default: + g_assert_not_reached(); + } +} + +static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env) +{ + uint32_t ret =3D cpsr_read(env); + + /* Move DIT to the correct location for SPSR_ELx */ + if (ret & CPSR_DIT) { + ret &=3D ~CPSR_DIT; + ret |=3D PSTATE_DIT; + } + /* Merge PSTATE.SS into SPSR_ELx */ + ret |=3D env->pstate & PSTATE_SS; + + return ret; +} + +/* Handle exception entry to a target EL which is using AArch64 */ +void arm_cpu_do_interrupt_aarch64(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + unsigned int new_el =3D env->exception.target_el; + target_ulong addr =3D env->cp15.vbar_el[new_el]; + unsigned int new_mode =3D aarch64_pstate_mode(new_el, true); + unsigned int old_mode; + unsigned int cur_el =3D arm_current_el(env); + int rt; + + if (tcg_enabled()) { + /* + * Note that new_el can never be 0. If cur_el is 0, then + * el0_a64 is is_a64(), else el0_a64 is ignored. + */ + aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); + } + + if (cur_el < new_el) { + /* + * Entry vector offset depends on whether the implemented EL + * immediately lower than the target level is using AArch32 or AAr= ch64 + */ + bool is_aa64; + uint64_t hcr; + + switch (new_el) { + case 3: + is_aa64 =3D (env->cp15.scr_el3 & SCR_RW) !=3D 0; + break; + case 2: + hcr =3D arm_hcr_el2_eff(env); + if ((hcr & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_TGE)) { + is_aa64 =3D (hcr & HCR_RW) !=3D 0; + break; + } + /* fall through */ + case 1: + is_aa64 =3D is_a64(env); + break; + default: + g_assert_not_reached(); + } + + if (is_aa64) { + addr +=3D 0x400; + } else { + addr +=3D 0x600; + } + } else if (pstate_read(env) & PSTATE_SP) { + addr +=3D 0x200; + } + + switch (cs->exception_index) { + case EXCP_PREFETCH_ABORT: + case EXCP_DATA_ABORT: + env->cp15.far_el[new_el] =3D env->exception.vaddress; + qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", + env->cp15.far_el[new_el]); + /* fall through */ + case EXCP_BKPT: + case EXCP_UDEF: + case EXCP_SWI: + case EXCP_HVC: + case EXCP_HYP_TRAP: + case EXCP_SMC: + switch (syn_get_ec(env->exception.syndrome)) { + case EC_ADVSIMDFPACCESSTRAP: + /* + * QEMU internal FP/SIMD syndromes from AArch32 include the + * TA and coproc fields which are only exposed if the exception + * is taken to AArch32 Hyp mode. Mask them out to get a valid + * AArch64 format syndrome. + */ + env->exception.syndrome &=3D ~MAKE_64BIT_MASK(0, 20); + break; + case EC_CP14RTTRAP: + case EC_CP15RTTRAP: + case EC_CP14DTTRAP: + /* + * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is curre= ntly + * the raw register field from the insn; when taking this to + * AArch64 we must convert it to the AArch64 view of the regis= ter + * number. Notice that we read a 4-bit AArch32 register number= and + * write back a 5-bit AArch64 one. + */ + rt =3D extract32(env->exception.syndrome, 5, 4); + rt =3D aarch64_regnum(env, rt); + env->exception.syndrome =3D deposit32(env->exception.syndrome, + 5, 5, rt); + break; + case EC_CP15RRTTRAP: + case EC_CP14RRTTRAP: + /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */ + rt =3D extract32(env->exception.syndrome, 5, 4); + rt =3D aarch64_regnum(env, rt); + env->exception.syndrome =3D deposit32(env->exception.syndrome, + 5, 5, rt); + rt =3D extract32(env->exception.syndrome, 10, 4); + rt =3D aarch64_regnum(env, rt); + env->exception.syndrome =3D deposit32(env->exception.syndrome, + 10, 5, rt); + break; + } + env->cp15.esr_el[new_el] =3D env->exception.syndrome; + break; + case EXCP_IRQ: + case EXCP_VIRQ: + addr +=3D 0x80; + break; + case EXCP_FIQ: + case EXCP_VFIQ: + addr +=3D 0x100; + break; + default: + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); + } + + if (is_a64(env)) { + old_mode =3D pstate_read(env); + aarch64_save_sp(env, arm_current_el(env)); + env->elr_el[new_el] =3D env->pc; + } else { + old_mode =3D cpsr_read_for_spsr_elx(env); + env->elr_el[new_el] =3D env->regs[15]; + + aarch64_sync_32_to_64(env); + + env->condexec_bits =3D 0; + } + env->banked_spsr[aarch64_banked_spsr_index(new_el)] =3D old_mode; + + qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", + env->elr_el[new_el]); + + if (cpu_isar_feature(aa64_pan, cpu)) { + /* The value of PSTATE.PAN is normally preserved, except when ... = */ + new_mode |=3D old_mode & PSTATE_PAN; + switch (new_el) { + case 2: + /* ... the target is EL2 with HCR_EL2.{E2H,TGE} =3D=3D '11' ..= . */ + if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) + !=3D (HCR_E2H | HCR_TGE)) { + break; + } + /* fall through */ + case 1: + /* ... the target is EL1 ... */ + /* ... and SCTLR_ELx.SPAN =3D=3D 0, then set to 1. */ + if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) =3D=3D 0) { + new_mode |=3D PSTATE_PAN; + } + break; + } + } + if (cpu_isar_feature(aa64_mte, cpu)) { + new_mode |=3D PSTATE_TCO; + } + + pstate_write(env, PSTATE_DAIF | new_mode); + env->aarch64 =3D 1; + aarch64_restore_sp(env, new_el); + if (tcg_enabled()) { + arm_rebuild_hflags(env); + } + + env->pc =3D addr; + + qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", + new_el, env->pc, pstate_read(env)); +} diff --git a/target/arm/cpu-exceptions.c b/target/arm/cpu-exceptions.c new file mode 100644 index 0000000000..9526436e5d --- /dev/null +++ b/target/arm/cpu-exceptions.c @@ -0,0 +1,445 @@ +/* + * QEMU ARM CPU Exceptions Sysemu code + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/main-loop.h" +#include "cpu.h" +#include "internals.h" +#include "sysemu/tcg.h" +#include "tcg/tcg-cpu.h" +#include "cpu-exceptions-aa64.h" + +static void take_aarch32_exception(CPUARMState *env, int new_mode, + uint32_t mask, uint32_t offset, + uint32_t newpc) +{ + int new_el; + + /* Change the CPU state so as to actually take the exception. */ + switch_mode(env, new_mode); + + /* + * For exceptions taken to AArch32 we must clear the SS bit in both + * PSTATE and in the old-state value we save to SPSR_, so zero i= t now. + */ + env->pstate &=3D ~PSTATE_SS; + env->spsr =3D cpsr_read(env); + /* Clear IT bits. */ + env->condexec_bits =3D 0; + /* Switch to the new mode, and to the correct instruction set. */ + env->uncached_cpsr =3D (env->uncached_cpsr & ~CPSR_M) | new_mode; + + /* This must be after mode switching. */ + new_el =3D arm_current_el(env); + + /* Set new mode endianness */ + env->uncached_cpsr &=3D ~CPSR_E; + if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { + env->uncached_cpsr |=3D CPSR_E; + } + /* J and IL must always be cleared for exception entry */ + env->uncached_cpsr &=3D ~(CPSR_IL | CPSR_J); + env->daif |=3D mask; + + if (new_mode =3D=3D ARM_CPU_MODE_HYP) { + env->thumb =3D (env->cp15.sctlr_el[2] & SCTLR_TE) !=3D 0; + env->elr_el[2] =3D env->regs[15]; + } else { + /* CPSR.PAN is normally preserved preserved unless... */ + if (cpu_isar_feature(aa32_pan, env_archcpu(env))) { + switch (new_el) { + case 3: + if (!arm_is_secure_below_el3(env)) { + /* ... the target is EL3, from non-secure state. */ + env->uncached_cpsr &=3D ~CPSR_PAN; + break; + } + /* ... the target is EL3, from secure state ... */ + /* fall through */ + case 1: + /* ... the target is EL1 and SCTLR.SPAN is 0. */ + if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { + env->uncached_cpsr |=3D CPSR_PAN; + } + break; + } + } + /* + * this is a lie, as there was no c1_sys on V4T/V5, but who cares + * and we should just guard the thumb mode on V4 + */ + if (arm_feature(env, ARM_FEATURE_V4T)) { + env->thumb =3D + (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) !=3D 0; + } + env->regs[14] =3D env->regs[15] + offset; + } + env->regs[15] =3D newpc; + if (tcg_enabled()) { + arm_rebuild_hflags(env); + } +} + +static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) +{ + /* + * Handle exception entry to Hyp mode; this is sufficiently + * different to entry to other AArch32 modes that we handle it + * separately here. + * + * The vector table entry used is always the 0x14 Hyp mode entry point, + * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp. + * The offset applied to the preferred return address is always zero + * (see DDI0487C.a section G1.12.3). + * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. + */ + uint32_t addr, mask; + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (cs->exception_index) { + case EXCP_UDEF: + addr =3D 0x04; + break; + case EXCP_SWI: + addr =3D 0x14; + break; + case EXCP_BKPT: + /* Fall through to prefetch abort. */ + case EXCP_PREFETCH_ABORT: + env->cp15.ifar_s =3D env->exception.vaddress; + qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n", + (uint32_t)env->exception.vaddress); + addr =3D 0x0c; + break; + case EXCP_DATA_ABORT: + env->cp15.dfar_s =3D env->exception.vaddress; + qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n", + (uint32_t)env->exception.vaddress); + addr =3D 0x10; + break; + case EXCP_IRQ: + addr =3D 0x18; + break; + case EXCP_FIQ: + addr =3D 0x1c; + break; + case EXCP_HVC: + addr =3D 0x08; + break; + case EXCP_HYP_TRAP: + addr =3D 0x14; + break; + default: + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); + } + + if (cs->exception_index !=3D EXCP_IRQ && cs->exception_index !=3D EXCP= _FIQ) { + if (!arm_feature(env, ARM_FEATURE_V8)) { + /* + * QEMU syndrome values are v8-style. v7 has the IL bit + * UNK/SBZP for "field not valid" cases, where v8 uses RES1. + * If this is a v7 CPU, squash the IL bit in those cases. + */ + if (cs->exception_index =3D=3D EXCP_PREFETCH_ABORT || + (cs->exception_index =3D=3D EXCP_DATA_ABORT && + !(env->exception.syndrome & ARM_EL_ISV)) || + syn_get_ec(env->exception.syndrome) =3D=3D EC_UNCATEGORIZE= D) { + env->exception.syndrome &=3D ~ARM_EL_IL; + } + } + env->cp15.esr_el[2] =3D env->exception.syndrome; + } + + if (arm_current_el(env) !=3D 2 && addr < 0x14) { + addr =3D 0x14; + } + + mask =3D 0; + if (!(env->cp15.scr_el3 & SCR_EA)) { + mask |=3D CPSR_A; + } + if (!(env->cp15.scr_el3 & SCR_IRQ)) { + mask |=3D CPSR_I; + } + if (!(env->cp15.scr_el3 & SCR_FIQ)) { + mask |=3D CPSR_F; + } + + addr +=3D env->cp15.hvbar; + + take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr); +} + +static void arm_cpu_do_interrupt_aarch32(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + uint32_t addr; + uint32_t mask; + int new_mode; + uint32_t offset; + uint32_t moe; + + /* If this is a debug exception we must update the DBGDSCR.MOE bits */ + switch (syn_get_ec(env->exception.syndrome)) { + case EC_BREAKPOINT: + case EC_BREAKPOINT_SAME_EL: + moe =3D 1; + break; + case EC_WATCHPOINT: + case EC_WATCHPOINT_SAME_EL: + moe =3D 10; + break; + case EC_AA32_BKPT: + moe =3D 3; + break; + case EC_VECTORCATCH: + moe =3D 5; + break; + default: + moe =3D 0; + break; + } + + if (moe) { + env->cp15.mdscr_el1 =3D deposit64(env->cp15.mdscr_el1, 2, 4, moe); + } + + if (env->exception.target_el =3D=3D 2) { + arm_cpu_do_interrupt_aarch32_hyp(cs); + return; + } + + switch (cs->exception_index) { + case EXCP_UDEF: + new_mode =3D ARM_CPU_MODE_UND; + addr =3D 0x04; + mask =3D CPSR_I; + if (env->thumb) { + offset =3D 2; + } else { + offset =3D 4; + } + break; + case EXCP_SWI: + new_mode =3D ARM_CPU_MODE_SVC; + addr =3D 0x08; + mask =3D CPSR_I; + /* The PC already points to the next instruction. */ + offset =3D 0; + break; + case EXCP_BKPT: + /* Fall through to prefetch abort. */ + case EXCP_PREFETCH_ABORT: + A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); + A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); + qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", + env->exception.fsr, (uint32_t)env->exception.vaddres= s); + new_mode =3D ARM_CPU_MODE_ABT; + addr =3D 0x0c; + mask =3D CPSR_A | CPSR_I; + offset =3D 4; + break; + case EXCP_DATA_ABORT: + A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); + A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); + qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", + env->exception.fsr, + (uint32_t)env->exception.vaddress); + new_mode =3D ARM_CPU_MODE_ABT; + addr =3D 0x10; + mask =3D CPSR_A | CPSR_I; + offset =3D 8; + break; + case EXCP_IRQ: + new_mode =3D ARM_CPU_MODE_IRQ; + addr =3D 0x18; + /* Disable IRQ and imprecise data aborts. */ + mask =3D CPSR_A | CPSR_I; + offset =3D 4; + if (env->cp15.scr_el3 & SCR_IRQ) { + /* IRQ routed to monitor mode */ + new_mode =3D ARM_CPU_MODE_MON; + mask |=3D CPSR_F; + } + break; + case EXCP_FIQ: + new_mode =3D ARM_CPU_MODE_FIQ; + addr =3D 0x1c; + /* Disable FIQ, IRQ and imprecise data aborts. */ + mask =3D CPSR_A | CPSR_I | CPSR_F; + if (env->cp15.scr_el3 & SCR_FIQ) { + /* FIQ routed to monitor mode */ + new_mode =3D ARM_CPU_MODE_MON; + } + offset =3D 4; + break; + case EXCP_VIRQ: + new_mode =3D ARM_CPU_MODE_IRQ; + addr =3D 0x18; + /* Disable IRQ and imprecise data aborts. */ + mask =3D CPSR_A | CPSR_I; + offset =3D 4; + break; + case EXCP_VFIQ: + new_mode =3D ARM_CPU_MODE_FIQ; + addr =3D 0x1c; + /* Disable FIQ, IRQ and imprecise data aborts. */ + mask =3D CPSR_A | CPSR_I | CPSR_F; + offset =3D 4; + break; + case EXCP_SMC: + new_mode =3D ARM_CPU_MODE_MON; + addr =3D 0x08; + mask =3D CPSR_A | CPSR_I | CPSR_F; + offset =3D 0; + break; + default: + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); + return; /* Never happens. Keep compiler happy. */ + } + + if (new_mode =3D=3D ARM_CPU_MODE_MON) { + addr +=3D env->cp15.mvbar; + } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { + /* High vectors. When enabled, base address cannot be remapped. */ + addr +=3D 0xffff0000; + } else { + /* + * ARM v7 architectures provide a vector base address register to = remap + * the interrupt vector table. + * This register is only followed in non-monitor mode, and is bank= ed. + * Note: only bits 31:5 are valid. + */ + addr +=3D A32_BANKED_CURRENT_REG_GET(env, vbar); + } + + if ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_MON) { + env->cp15.scr_el3 &=3D ~SCR_NS; + } + + take_aarch32_exception(env, new_mode, mask, offset, addr); +} + +void arm_log_exception(int idx) +{ + if (qemu_loglevel_mask(CPU_LOG_INT)) { + const char *exc =3D NULL; + static const char * const excnames[] =3D { + [EXCP_UDEF] =3D "Undefined Instruction", + [EXCP_SWI] =3D "SVC", + [EXCP_PREFETCH_ABORT] =3D "Prefetch Abort", + [EXCP_DATA_ABORT] =3D "Data Abort", + [EXCP_IRQ] =3D "IRQ", + [EXCP_FIQ] =3D "FIQ", + [EXCP_BKPT] =3D "Breakpoint", + [EXCP_EXCEPTION_EXIT] =3D "QEMU v7M exception exit", + [EXCP_KERNEL_TRAP] =3D "QEMU intercept of kernel commpage", + [EXCP_HVC] =3D "Hypervisor Call", + [EXCP_HYP_TRAP] =3D "Hypervisor Trap", + [EXCP_SMC] =3D "Secure Monitor Call", + [EXCP_VIRQ] =3D "Virtual IRQ", + [EXCP_VFIQ] =3D "Virtual FIQ", + [EXCP_SEMIHOST] =3D "Semihosting call", + [EXCP_NOCP] =3D "v7M NOCP UsageFault", + [EXCP_INVSTATE] =3D "v7M INVSTATE UsageFault", + [EXCP_STKOF] =3D "v8M STKOF UsageFault", + [EXCP_LAZYFP] =3D "v7M exception during lazy FP stacking", + [EXCP_LSERR] =3D "v8M LSERR UsageFault", + [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", + }; + + if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { + exc =3D excnames[idx]; + } + if (!exc) { + exc =3D "unknown"; + } + qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); + } +} + +/* + * Handle a CPU exception for A and R profile CPUs. + * Do any appropriate logging, handle PSCI calls, and then hand off + * to the AArch64-entry or AArch32-entry function depending on the + * target exception level's register width. + * + * Note: this is used for both TCG (as the do_interrupt tcg op), + * and KVM to re-inject guest debug exceptions, and to + * inject a Synchronous-External-Abort. + */ +void arm_cpu_do_interrupt(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + unsigned int new_el =3D env->exception.target_el; + + assert(!arm_feature(env, ARM_FEATURE_M)); + + arm_log_exception(cs->exception_index); + qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(en= v), + new_el); + if (qemu_loglevel_mask(CPU_LOG_INT) + && !excp_is_internal(cs->exception_index)) { + qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", + syn_get_ec(env->exception.syndrome), + env->exception.syndrome); + } + + if (tcg_enabled()) { + if (arm_is_psci_call(cpu, cs->exception_index)) { + arm_handle_psci_call(cpu); + qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); + return; + } + /* + * Semihosting semantics depend on the register width of the code + * that caused the exception, not the target exception level, so + * must be handled here. + */ + if (cs->exception_index =3D=3D EXCP_SEMIHOST) { + tcg_handle_semihosting(cs); + return; + } + } + /* + * Hooks may change global state so BQL should be held, also the + * BQL needs to be held for any modification of + * cs->interrupt_request. + */ + g_assert(qemu_mutex_iothread_locked()); + arm_call_pre_el_change_hook(cpu); + + assert(!excp_is_internal(cs->exception_index)); + if (arm_el_is_aa64(env, new_el)) { + arm_cpu_do_interrupt_aarch64(cs); + } else { + arm_cpu_do_interrupt_aarch32(cs); + } + + arm_call_el_change_hook(cpu); + + if (tcg_enabled()) { + cs->interrupt_request |=3D CPU_INTERRUPT_EXITTB; + } +} diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c index fff55311f4..4bccf74996 100644 --- a/target/arm/cpu-sysemu.c +++ b/target/arm/cpu-sysemu.c @@ -19,13 +19,9 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/log.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "internals.h" #include "sysemu/hw_accel.h" -#include "sysemu/tcg.h" -#include "tcg/tcg-cpu.h" =20 #ifdef CONFIG_TCG #include "tcg/tcg-cpu.h" @@ -484,671 +480,3 @@ int fp_exception_el(CPUARMState *env, int cur_el) } return 0; } - -static void take_aarch32_exception(CPUARMState *env, int new_mode, - uint32_t mask, uint32_t offset, - uint32_t newpc) -{ - int new_el; - - /* Change the CPU state so as to actually take the exception. */ - switch_mode(env, new_mode); - - /* - * For exceptions taken to AArch32 we must clear the SS bit in both - * PSTATE and in the old-state value we save to SPSR_, so zero i= t now. - */ - env->pstate &=3D ~PSTATE_SS; - env->spsr =3D cpsr_read(env); - /* Clear IT bits. */ - env->condexec_bits =3D 0; - /* Switch to the new mode, and to the correct instruction set. */ - env->uncached_cpsr =3D (env->uncached_cpsr & ~CPSR_M) | new_mode; - - /* This must be after mode switching. */ - new_el =3D arm_current_el(env); - - /* Set new mode endianness */ - env->uncached_cpsr &=3D ~CPSR_E; - if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { - env->uncached_cpsr |=3D CPSR_E; - } - /* J and IL must always be cleared for exception entry */ - env->uncached_cpsr &=3D ~(CPSR_IL | CPSR_J); - env->daif |=3D mask; - - if (new_mode =3D=3D ARM_CPU_MODE_HYP) { - env->thumb =3D (env->cp15.sctlr_el[2] & SCTLR_TE) !=3D 0; - env->elr_el[2] =3D env->regs[15]; - } else { - /* CPSR.PAN is normally preserved preserved unless... */ - if (cpu_isar_feature(aa32_pan, env_archcpu(env))) { - switch (new_el) { - case 3: - if (!arm_is_secure_below_el3(env)) { - /* ... the target is EL3, from non-secure state. */ - env->uncached_cpsr &=3D ~CPSR_PAN; - break; - } - /* ... the target is EL3, from secure state ... */ - /* fall through */ - case 1: - /* ... the target is EL1 and SCTLR.SPAN is 0. */ - if (!(env->cp15.sctlr_el[new_el] & SCTLR_SPAN)) { - env->uncached_cpsr |=3D CPSR_PAN; - } - break; - } - } - /* - * this is a lie, as there was no c1_sys on V4T/V5, but who cares - * and we should just guard the thumb mode on V4 - */ - if (arm_feature(env, ARM_FEATURE_V4T)) { - env->thumb =3D - (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) !=3D 0; - } - env->regs[14] =3D env->regs[15] + offset; - } - env->regs[15] =3D newpc; - if (tcg_enabled()) { - arm_rebuild_hflags(env); - } -} - -static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) -{ - /* - * Handle exception entry to Hyp mode; this is sufficiently - * different to entry to other AArch32 modes that we handle it - * separately here. - * - * The vector table entry used is always the 0x14 Hyp mode entry point, - * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp. - * The offset applied to the preferred return address is always zero - * (see DDI0487C.a section G1.12.3). - * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. - */ - uint32_t addr, mask; - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - - switch (cs->exception_index) { - case EXCP_UDEF: - addr =3D 0x04; - break; - case EXCP_SWI: - addr =3D 0x14; - break; - case EXCP_BKPT: - /* Fall through to prefetch abort. */ - case EXCP_PREFETCH_ABORT: - env->cp15.ifar_s =3D env->exception.vaddress; - qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n", - (uint32_t)env->exception.vaddress); - addr =3D 0x0c; - break; - case EXCP_DATA_ABORT: - env->cp15.dfar_s =3D env->exception.vaddress; - qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n", - (uint32_t)env->exception.vaddress); - addr =3D 0x10; - break; - case EXCP_IRQ: - addr =3D 0x18; - break; - case EXCP_FIQ: - addr =3D 0x1c; - break; - case EXCP_HVC: - addr =3D 0x08; - break; - case EXCP_HYP_TRAP: - addr =3D 0x14; - break; - default: - cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); - } - - if (cs->exception_index !=3D EXCP_IRQ && cs->exception_index !=3D EXCP= _FIQ) { - if (!arm_feature(env, ARM_FEATURE_V8)) { - /* - * QEMU syndrome values are v8-style. v7 has the IL bit - * UNK/SBZP for "field not valid" cases, where v8 uses RES1. - * If this is a v7 CPU, squash the IL bit in those cases. - */ - if (cs->exception_index =3D=3D EXCP_PREFETCH_ABORT || - (cs->exception_index =3D=3D EXCP_DATA_ABORT && - !(env->exception.syndrome & ARM_EL_ISV)) || - syn_get_ec(env->exception.syndrome) =3D=3D EC_UNCATEGORIZE= D) { - env->exception.syndrome &=3D ~ARM_EL_IL; - } - } - env->cp15.esr_el[2] =3D env->exception.syndrome; - } - - if (arm_current_el(env) !=3D 2 && addr < 0x14) { - addr =3D 0x14; - } - - mask =3D 0; - if (!(env->cp15.scr_el3 & SCR_EA)) { - mask |=3D CPSR_A; - } - if (!(env->cp15.scr_el3 & SCR_IRQ)) { - mask |=3D CPSR_I; - } - if (!(env->cp15.scr_el3 & SCR_FIQ)) { - mask |=3D CPSR_F; - } - - addr +=3D env->cp15.hvbar; - - take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr); -} - -static void arm_cpu_do_interrupt_aarch32(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - uint32_t addr; - uint32_t mask; - int new_mode; - uint32_t offset; - uint32_t moe; - - /* If this is a debug exception we must update the DBGDSCR.MOE bits */ - switch (syn_get_ec(env->exception.syndrome)) { - case EC_BREAKPOINT: - case EC_BREAKPOINT_SAME_EL: - moe =3D 1; - break; - case EC_WATCHPOINT: - case EC_WATCHPOINT_SAME_EL: - moe =3D 10; - break; - case EC_AA32_BKPT: - moe =3D 3; - break; - case EC_VECTORCATCH: - moe =3D 5; - break; - default: - moe =3D 0; - break; - } - - if (moe) { - env->cp15.mdscr_el1 =3D deposit64(env->cp15.mdscr_el1, 2, 4, moe); - } - - if (env->exception.target_el =3D=3D 2) { - arm_cpu_do_interrupt_aarch32_hyp(cs); - return; - } - - switch (cs->exception_index) { - case EXCP_UDEF: - new_mode =3D ARM_CPU_MODE_UND; - addr =3D 0x04; - mask =3D CPSR_I; - if (env->thumb) { - offset =3D 2; - } else { - offset =3D 4; - } - break; - case EXCP_SWI: - new_mode =3D ARM_CPU_MODE_SVC; - addr =3D 0x08; - mask =3D CPSR_I; - /* The PC already points to the next instruction. */ - offset =3D 0; - break; - case EXCP_BKPT: - /* Fall through to prefetch abort. */ - case EXCP_PREFETCH_ABORT: - A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr); - A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress); - qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n", - env->exception.fsr, (uint32_t)env->exception.vaddres= s); - new_mode =3D ARM_CPU_MODE_ABT; - addr =3D 0x0c; - mask =3D CPSR_A | CPSR_I; - offset =3D 4; - break; - case EXCP_DATA_ABORT: - A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); - A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress); - qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", - env->exception.fsr, - (uint32_t)env->exception.vaddress); - new_mode =3D ARM_CPU_MODE_ABT; - addr =3D 0x10; - mask =3D CPSR_A | CPSR_I; - offset =3D 8; - break; - case EXCP_IRQ: - new_mode =3D ARM_CPU_MODE_IRQ; - addr =3D 0x18; - /* Disable IRQ and imprecise data aborts. */ - mask =3D CPSR_A | CPSR_I; - offset =3D 4; - if (env->cp15.scr_el3 & SCR_IRQ) { - /* IRQ routed to monitor mode */ - new_mode =3D ARM_CPU_MODE_MON; - mask |=3D CPSR_F; - } - break; - case EXCP_FIQ: - new_mode =3D ARM_CPU_MODE_FIQ; - addr =3D 0x1c; - /* Disable FIQ, IRQ and imprecise data aborts. */ - mask =3D CPSR_A | CPSR_I | CPSR_F; - if (env->cp15.scr_el3 & SCR_FIQ) { - /* FIQ routed to monitor mode */ - new_mode =3D ARM_CPU_MODE_MON; - } - offset =3D 4; - break; - case EXCP_VIRQ: - new_mode =3D ARM_CPU_MODE_IRQ; - addr =3D 0x18; - /* Disable IRQ and imprecise data aborts. */ - mask =3D CPSR_A | CPSR_I; - offset =3D 4; - break; - case EXCP_VFIQ: - new_mode =3D ARM_CPU_MODE_FIQ; - addr =3D 0x1c; - /* Disable FIQ, IRQ and imprecise data aborts. */ - mask =3D CPSR_A | CPSR_I | CPSR_F; - offset =3D 4; - break; - case EXCP_SMC: - new_mode =3D ARM_CPU_MODE_MON; - addr =3D 0x08; - mask =3D CPSR_A | CPSR_I | CPSR_F; - offset =3D 0; - break; - default: - cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); - return; /* Never happens. Keep compiler happy. */ - } - - if (new_mode =3D=3D ARM_CPU_MODE_MON) { - addr +=3D env->cp15.mvbar; - } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) { - /* High vectors. When enabled, base address cannot be remapped. */ - addr +=3D 0xffff0000; - } else { - /* - * ARM v7 architectures provide a vector base address register to = remap - * the interrupt vector table. - * This register is only followed in non-monitor mode, and is bank= ed. - * Note: only bits 31:5 are valid. - */ - addr +=3D A32_BANKED_CURRENT_REG_GET(env, vbar); - } - - if ((env->uncached_cpsr & CPSR_M) =3D=3D ARM_CPU_MODE_MON) { - env->cp15.scr_el3 &=3D ~SCR_NS; - } - - take_aarch32_exception(env, new_mode, mask, offset, addr); -} - -static int aarch64_regnum(CPUARMState *env, int aarch32_reg) -{ - /* - * Return the register number of the AArch64 view of the AArch32 - * register @aarch32_reg. The CPUARMState CPSR is assumed to still - * be that of the AArch32 mode the exception came from. - */ - int mode =3D env->uncached_cpsr & CPSR_M; - - switch (aarch32_reg) { - case 0 ... 7: - return aarch32_reg; - case 8 ... 12: - return mode =3D=3D ARM_CPU_MODE_FIQ ? aarch32_reg + 16 : aarch32_r= eg; - case 13: - switch (mode) { - case ARM_CPU_MODE_USR: - case ARM_CPU_MODE_SYS: - return 13; - case ARM_CPU_MODE_HYP: - return 15; - case ARM_CPU_MODE_IRQ: - return 17; - case ARM_CPU_MODE_SVC: - return 19; - case ARM_CPU_MODE_ABT: - return 21; - case ARM_CPU_MODE_UND: - return 23; - case ARM_CPU_MODE_FIQ: - return 29; - default: - g_assert_not_reached(); - } - case 14: - switch (mode) { - case ARM_CPU_MODE_USR: - case ARM_CPU_MODE_SYS: - case ARM_CPU_MODE_HYP: - return 14; - case ARM_CPU_MODE_IRQ: - return 16; - case ARM_CPU_MODE_SVC: - return 18; - case ARM_CPU_MODE_ABT: - return 20; - case ARM_CPU_MODE_UND: - return 22; - case ARM_CPU_MODE_FIQ: - return 30; - default: - g_assert_not_reached(); - } - case 15: - return 31; - default: - g_assert_not_reached(); - } -} - -static uint32_t cpsr_read_for_spsr_elx(CPUARMState *env) -{ - uint32_t ret =3D cpsr_read(env); - - /* Move DIT to the correct location for SPSR_ELx */ - if (ret & CPSR_DIT) { - ret &=3D ~CPSR_DIT; - ret |=3D PSTATE_DIT; - } - /* Merge PSTATE.SS into SPSR_ELx */ - ret |=3D env->pstate & PSTATE_SS; - - return ret; -} - -/* Handle exception entry to a target EL which is using AArch64 */ -static void arm_cpu_do_interrupt_aarch64(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - unsigned int new_el =3D env->exception.target_el; - target_ulong addr =3D env->cp15.vbar_el[new_el]; - unsigned int new_mode =3D aarch64_pstate_mode(new_el, true); - unsigned int old_mode; - unsigned int cur_el =3D arm_current_el(env); - int rt; - - if (tcg_enabled()) { - /* - * Note that new_el can never be 0. If cur_el is 0, then - * el0_a64 is is_a64(), else el0_a64 is ignored. - */ - aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); - } - - if (cur_el < new_el) { - /* - * Entry vector offset depends on whether the implemented EL - * immediately lower than the target level is using AArch32 or AAr= ch64 - */ - bool is_aa64; - uint64_t hcr; - - switch (new_el) { - case 3: - is_aa64 =3D (env->cp15.scr_el3 & SCR_RW) !=3D 0; - break; - case 2: - hcr =3D arm_hcr_el2_eff(env); - if ((hcr & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_TGE)) { - is_aa64 =3D (hcr & HCR_RW) !=3D 0; - break; - } - /* fall through */ - case 1: - is_aa64 =3D is_a64(env); - break; - default: - g_assert_not_reached(); - } - - if (is_aa64) { - addr +=3D 0x400; - } else { - addr +=3D 0x600; - } - } else if (pstate_read(env) & PSTATE_SP) { - addr +=3D 0x200; - } - - switch (cs->exception_index) { - case EXCP_PREFETCH_ABORT: - case EXCP_DATA_ABORT: - env->cp15.far_el[new_el] =3D env->exception.vaddress; - qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n", - env->cp15.far_el[new_el]); - /* fall through */ - case EXCP_BKPT: - case EXCP_UDEF: - case EXCP_SWI: - case EXCP_HVC: - case EXCP_HYP_TRAP: - case EXCP_SMC: - switch (syn_get_ec(env->exception.syndrome)) { - case EC_ADVSIMDFPACCESSTRAP: - /* - * QEMU internal FP/SIMD syndromes from AArch32 include the - * TA and coproc fields which are only exposed if the exception - * is taken to AArch32 Hyp mode. Mask them out to get a valid - * AArch64 format syndrome. - */ - env->exception.syndrome &=3D ~MAKE_64BIT_MASK(0, 20); - break; - case EC_CP14RTTRAP: - case EC_CP15RTTRAP: - case EC_CP14DTTRAP: - /* - * For a trap on AArch32 MRC/MCR/LDC/STC the Rt field is curre= ntly - * the raw register field from the insn; when taking this to - * AArch64 we must convert it to the AArch64 view of the regis= ter - * number. Notice that we read a 4-bit AArch32 register number= and - * write back a 5-bit AArch64 one. - */ - rt =3D extract32(env->exception.syndrome, 5, 4); - rt =3D aarch64_regnum(env, rt); - env->exception.syndrome =3D deposit32(env->exception.syndrome, - 5, 5, rt); - break; - case EC_CP15RRTTRAP: - case EC_CP14RRTTRAP: - /* Similarly for MRRC/MCRR traps for Rt and Rt2 fields */ - rt =3D extract32(env->exception.syndrome, 5, 4); - rt =3D aarch64_regnum(env, rt); - env->exception.syndrome =3D deposit32(env->exception.syndrome, - 5, 5, rt); - rt =3D extract32(env->exception.syndrome, 10, 4); - rt =3D aarch64_regnum(env, rt); - env->exception.syndrome =3D deposit32(env->exception.syndrome, - 10, 5, rt); - break; - } - env->cp15.esr_el[new_el] =3D env->exception.syndrome; - break; - case EXCP_IRQ: - case EXCP_VIRQ: - addr +=3D 0x80; - break; - case EXCP_FIQ: - case EXCP_VFIQ: - addr +=3D 0x100; - break; - default: - cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); - } - - if (is_a64(env)) { - old_mode =3D pstate_read(env); - aarch64_save_sp(env, arm_current_el(env)); - env->elr_el[new_el] =3D env->pc; - } else { - old_mode =3D cpsr_read_for_spsr_elx(env); - env->elr_el[new_el] =3D env->regs[15]; - - aarch64_sync_32_to_64(env); - - env->condexec_bits =3D 0; - } - env->banked_spsr[aarch64_banked_spsr_index(new_el)] =3D old_mode; - - qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", - env->elr_el[new_el]); - - if (cpu_isar_feature(aa64_pan, cpu)) { - /* The value of PSTATE.PAN is normally preserved, except when ... = */ - new_mode |=3D old_mode & PSTATE_PAN; - switch (new_el) { - case 2: - /* ... the target is EL2 with HCR_EL2.{E2H,TGE} =3D=3D '11' ..= . */ - if ((arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) - !=3D (HCR_E2H | HCR_TGE)) { - break; - } - /* fall through */ - case 1: - /* ... the target is EL1 ... */ - /* ... and SCTLR_ELx.SPAN =3D=3D 0, then set to 1. */ - if ((env->cp15.sctlr_el[new_el] & SCTLR_SPAN) =3D=3D 0) { - new_mode |=3D PSTATE_PAN; - } - break; - } - } - if (cpu_isar_feature(aa64_mte, cpu)) { - new_mode |=3D PSTATE_TCO; - } - - pstate_write(env, PSTATE_DAIF | new_mode); - env->aarch64 =3D 1; - aarch64_restore_sp(env, new_el); - - if (tcg_enabled()) { - /* pstate already written, so we can use arm_rebuild_hflags here */ - arm_rebuild_hflags(env); - } - - env->pc =3D addr; - - qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", - new_el, env->pc, pstate_read(env)); -} - -void arm_log_exception(int idx) -{ - if (qemu_loglevel_mask(CPU_LOG_INT)) { - const char *exc =3D NULL; - static const char * const excnames[] =3D { - [EXCP_UDEF] =3D "Undefined Instruction", - [EXCP_SWI] =3D "SVC", - [EXCP_PREFETCH_ABORT] =3D "Prefetch Abort", - [EXCP_DATA_ABORT] =3D "Data Abort", - [EXCP_IRQ] =3D "IRQ", - [EXCP_FIQ] =3D "FIQ", - [EXCP_BKPT] =3D "Breakpoint", - [EXCP_EXCEPTION_EXIT] =3D "QEMU v7M exception exit", - [EXCP_KERNEL_TRAP] =3D "QEMU intercept of kernel commpage", - [EXCP_HVC] =3D "Hypervisor Call", - [EXCP_HYP_TRAP] =3D "Hypervisor Trap", - [EXCP_SMC] =3D "Secure Monitor Call", - [EXCP_VIRQ] =3D "Virtual IRQ", - [EXCP_VFIQ] =3D "Virtual FIQ", - [EXCP_SEMIHOST] =3D "Semihosting call", - [EXCP_NOCP] =3D "v7M NOCP UsageFault", - [EXCP_INVSTATE] =3D "v7M INVSTATE UsageFault", - [EXCP_STKOF] =3D "v8M STKOF UsageFault", - [EXCP_LAZYFP] =3D "v7M exception during lazy FP stacking", - [EXCP_LSERR] =3D "v8M LSERR UsageFault", - [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", - }; - - if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { - exc =3D excnames[idx]; - } - if (!exc) { - exc =3D "unknown"; - } - qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc); - } -} - -/* - * Handle a CPU exception for A and R profile CPUs. - * Do any appropriate logging, handle PSCI calls, and then hand off - * to the AArch64-entry or AArch32-entry function depending on the - * target exception level's register width. - * - * Note: this is used for both TCG (as the do_interrupt tcg op), - * and KVM to re-inject guest debug exceptions, and to - * inject a Synchronous-External-Abort. - */ -void arm_cpu_do_interrupt(CPUState *cs) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - unsigned int new_el =3D env->exception.target_el; - - assert(!arm_feature(env, ARM_FEATURE_M)); - - arm_log_exception(cs->exception_index); - qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(en= v), - new_el); - if (qemu_loglevel_mask(CPU_LOG_INT) - && !excp_is_internal(cs->exception_index)) { - qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", - syn_get_ec(env->exception.syndrome), - env->exception.syndrome); - } - - if (tcg_enabled()) { - if (arm_is_psci_call(cpu, cs->exception_index)) { - arm_handle_psci_call(cpu); - qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n"); - return; - } - /* - * Semihosting semantics depend on the register width of the code - * that caused the exception, not the target exception level, so - * must be handled here. - */ - if (cs->exception_index =3D=3D EXCP_SEMIHOST) { - tcg_handle_semihosting(cs); - return; - } - } - /* - * Hooks may change global state so BQL should be held, also the - * BQL needs to be held for any modification of - * cs->interrupt_request. - */ - g_assert(qemu_mutex_iothread_locked()); - arm_call_pre_el_change_hook(cpu); - - assert(!excp_is_internal(cs->exception_index)); - if (arm_el_is_aa64(env, new_el)) { - arm_cpu_do_interrupt_aarch64(cs); - } else { - arm_cpu_do_interrupt_aarch32(cs); - } - - arm_call_el_change_hook(cpu); - - if (tcg_enabled()) { - cs->interrupt_request |=3D CPU_INTERRUPT_EXITTB; - } -} diff --git a/target/arm/cpu-user.c b/target/arm/cpu-user.c index 6a1a1fa273..a8e6f28ec6 100644 --- a/target/arm/cpu-user.c +++ b/target/arm/cpu-user.c @@ -12,6 +12,7 @@ #include "qapi/qapi-commands-machine-target.h" #include "qapi/error.h" #include "cpu.h" +#include "cpu-exceptions-aa64.h" #include "internals.h" =20 void switch_mode(CPUARMState *env, int mode) diff --git a/target/arm/meson.build b/target/arm/meson.build index bad5a659a7..8bcd394828 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -21,12 +21,17 @@ arm_softmmu_ss =3D ss.source_set() arm_softmmu_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', + 'cpu-exceptions.c', 'cpu-mmu-sysemu.c', 'cpu-sysemu.c', 'machine.c', 'monitor.c', )) =20 +arm_softmmu_ss.add(when: 'TARGET_AARCH64', if_true: files( + 'cpu-exceptions-aa64.c' +)) + arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( 'psci.c', )) --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622825097; cv=none; d=zohomail.com; s=zohoarc; b=eF56xAnvnrdA8YRa9dyjXJtLVHgDVKTX5/9wvKLz8x+sulWuhd4AEqXpORH8URG388esMaP3n28ma5ZZCGa5lxbZc8GhhOC4B/AskhPVqEmmQWml8nmfvpsMYTcNvHFkTJCRPzQlrzR8oeyP79GWJ67PL2Djr1sg47FGMrJhRio= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622825097; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4nGP6Z5x0fcvCA1VqJc1xqqHTfKci3f1/omLPFccgrE=; b=nlOZpnB8NUQXTOa6sy0h1fwFLjBvO2rDy+30P468rnqFsbzjkKiUtN2yLfvtgzOSma212nU6YxOa9uQwi8gGD13RZukG3I7lKVmpjjrFHQrGAuKzwbi6xaReU3Oqyo7RJ/9s5oY8UWiZ2a7QUS3IoXWi7ecXsScKtUQB3n0oxWo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622825097947706.3707400000035; Fri, 4 Jun 2021 09:44:57 -0700 (PDT) Received: from localhost ([::1]:37756 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCwK-0007AK-Ou for importer@patchew.org; Fri, 04 Jun 2021 12:44:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48578) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCI3-0008Jt-7q for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:19 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:43960) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHc-0005pv-Ro for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:18 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 3-20020a05600c0243b029019f2f9b2b8aso5901647wmj.2 for ; Fri, 04 Jun 2021 09:02:52 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id a123sm10341991wmd.2.2021.06.04.09.02.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:43 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 6CD941FFF1; Fri, 4 Jun 2021 16:53:22 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4nGP6Z5x0fcvCA1VqJc1xqqHTfKci3f1/omLPFccgrE=; b=rYrBGRRKUpmtFoVFXwQDQZhTI56HGv0MSBw/8FGkC1Wcjuet3fUoIZiQjf+DQuUqwC z4HprW60hoQme4+MsVmcNa6ubCxEJHr7owrpzpAXlqHruAp3/wKRshqydHctNhVCuP/v TpXU3bwe7feRBXO//YJ+UHkQ4Dzc24DngLhNnYHOFXOGUd05Xc8zIAUYfpRDtJk9N7wo p3pdHe3MdTT/CdiChZvFd3mY3KUSjidE3fLkk6H310oPCsY6qKGyJFxQbWh2dvDBFZcv 4zdJXvaiihDdbV3PRa+3fF8VDS1EwPU+OQbLytjuTP6I8s6aldexm74oOyFu3AAIUB1Z 8ldg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4nGP6Z5x0fcvCA1VqJc1xqqHTfKci3f1/omLPFccgrE=; b=Mczs4lj9PXRVS7+ejAazDKr8V/HOdbgrkpVz5Wo3nkJbUmMc6XhmPDM3T3sgJhCTNk 0jqBQOnvl2iLy8oh4UC76Zd8S+DsddObzx3T9tiaFvRi6m85S8jgMWr0cSHfmsUukrwW v+xsdHr4dWf5cYooh9G9vwTHpMWQFh+BDSbpwt0lyBpX4NWU5spWdW1MHrUS1ipv+D8b S8JaDYGVsosJqu4LBFSGMQ+HBgXcdgzn0/RNaoUYB7/G8TIuxw+ZBPmkzqwMmJcoHOi2 asfYwGTT+r2oKEC5XEQ4y7YEYGKVmOFD3+OB0G/NYpUg7J02ZqQ9achzQW7/ek5COUGd e1jQ== X-Gm-Message-State: AOAM5339HLIEubiRga9YpfiZ2B/vYJYFHhKGS5XCpDvrf6YnhRNsr3Q4 o0SmqNreqBCuH+KBU3d74lP+CA== X-Google-Smtp-Source: ABdhPJyj39mimfWxe+zWeLQCaYyqe044Jcf1UlOUjY0dBWSagS2u1SYw1YMMMc5Lpr2+tv6RT7gFSg== X-Received: by 2002:a05:600c:21cf:: with SMTP id x15mr4323372wmj.174.1622822571487; Fri, 04 Jun 2021 09:02:51 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 79/99] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64 Date: Fri, 4 Jun 2021 16:52:52 +0100 Message-Id: <20210604155312.15902-80-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana restrict zcr_el1, zcr_el2, zcr_no_el2, zcr_el3 reginfo, and the related SVE functions to TARGET_AARCH64. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/cpregs.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/cpregs.c b/target/arm/tcg/cpregs.c index 8422da4335..56d56f7f81 100644 --- a/target/arm/tcg/cpregs.c +++ b/target/arm/tcg/cpregs.c @@ -5791,6 +5791,8 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D= { REGINFO_SENTINEL }; =20 +#ifdef TARGET_AARCH64 + static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -5843,6 +5845,8 @@ static const ARMCPRegInfo zcr_el3_reginfo =3D { .writefn =3D zcr_write, .raw_writefn =3D raw_write }; =20 +#endif /* TARGET_AARCH64 */ + static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -7572,6 +7576,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, vhe_reginfo); } =20 +#ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sve, cpu)) { define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); if (arm_feature(env, ARM_FEATURE_EL2)) { @@ -7584,7 +7589,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) } } =20 -#ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_pauth, cpu)) { define_arm_cp_regs(cpu, pauth_reginfo); } @@ -7614,7 +7618,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, mte_tco_ro_reginfo); define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); } -#endif +#endif /* TARGET_AARCH64 */ =20 if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622822294; cv=none; d=zohomail.com; s=zohoarc; b=Y8CUyAeQKUakZVunEG/dMVY7fuDTToirhdFpaXC/40G/cpvW38SvWEfE5PUMBL2YL6WqRCRWprW7K8FKTAAakZPuEDyopI3Ah2HbSIPrvx/Q0XgLvbwj5fOGvTUm1aGnuJM9CAVdJPy/qvxShfAkkvGrIOOoQWJi9+V9cj1G8y0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622822294; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZEqovDXWlP3I0jnR9ymxC8JazCNBkqL0mUNiGG3NMBI=; b=f1LHEuMklVBzHSHybA7GpYf8RQt73jMPYyRBK9zZJrI/efJxVri0NLRzJsZ1Sf/GbONghbYwqR8GLyPHpYVdBUn4reMNlMSDxzo03mOSye4fy4Y3owILr4E96ztqkDy8CXafcP8ssaBn/Q9gkPx88ccRlXoeWV37eKIdLLXL1Bo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622822294697812.9478685372512; Fri, 4 Jun 2021 08:58:14 -0700 (PDT) Received: from localhost ([::1]:34608 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCD7-0007Bc-IA for importer@patchew.org; Fri, 04 Jun 2021 11:58:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44950) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8t-0003iT-VX for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:52 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:55832) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8m-0000Fm-3L for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:51 -0400 Received: by mail-wm1-x330.google.com with SMTP id g204so5652788wmf.5 for ; Fri, 04 Jun 2021 08:53:42 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id 89sm7541924wrq.14.2021.06.04.08.53.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:31 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 912CF1FF93; Fri, 4 Jun 2021 16:53:22 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZEqovDXWlP3I0jnR9ymxC8JazCNBkqL0mUNiGG3NMBI=; b=lion6DlwoGdXl51iAkhbyqqhUua9KEMa2tNoCUFwvf7VGvoBPNU1MRNyjqigLqb6A5 FUFg+AT3QHwQfZZkBuVWA2am6fmVoYGoEpfbUzg9my/umiSaHDg5M+7GbgaZfpEdh5ZC FTGmniQDqQ+jOqd5VXDcX7+Jb7BvhbU1s8Y+RAktg2MoH1bg1UlRHvSbJ6eXGBtRFGyA /3IvkLU9kXPHuFdfkpmRFx8NpaCYknVcVYF1+v7DbYfk/vye6EPR49h+KUc1hRaN44AI SRm4+4xrUrGLl6jzsdvsd9ucXkrPdHAD5iwE+AyIqvVc0LVet3OajJKfbTkYW6nFX1n2 kSqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZEqovDXWlP3I0jnR9ymxC8JazCNBkqL0mUNiGG3NMBI=; b=jq6HGwJ+7p827uvu1S8/yHYdQi21ifS61/3QEvuQxQmD1AlyOk3N/Jok6sWeN1mHIF f1vOx746tzDB3YbwxcViMK0xvFXQ2H9fUO+zTs4YZz6uJ6uBnI36euT8lUpyMzL+14r8 Yi6FNynzR1mcf1TXcly5jIjn/Wk0yDYHWvWpOBSMrX+MgZGXGvhTURd10wftV/lylHmw EUr0iHwvFDxiHzRAEjcJMxXh+udCY52dbtYAP/bi5aYeMV3qYWTxfE/2koVzzQzSJmfN vBJ9xDywehrkPsbRSggWnVdtw7r+6p9EUHoHuLH+ILssXHgtiODKHTLXjcCHkU+TTQU7 vS1A== X-Gm-Message-State: AOAM532FAqazY+ay0HcodFbAQdfHFh1pAq7QeiN7UT/BuuqDnQXDhZU4 39YGeA6TdETy2KO20mt3ScT2pE7NJoYmKQ== X-Google-Smtp-Source: ABdhPJzovU5SVQnn/QWv95yKC/tJjgyrO0pp8ipdjGhtY72wF+uf13J1bEi/YW2FotSN3D4kwWYHqw== X-Received: by 2002:a05:600c:c9:: with SMTP id u9mr4292927wmm.156.1622822021494; Fri, 04 Jun 2021 08:53:41 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 80/99] target/arm: tcg-sve: import narrow_vq and change_el functions Date: Fri, 4 Jun 2021 16:52:53 +0100 Message-Id: <20210604155312.15902-81-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , Laurent Vivier , qemu-arm@nongnu.org, Claudio Fontana , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana aarch64_sve_narrow_vq and aarch64_sve_change_el are SVE-related functions only used for TCG, so we can put them in the tcg-sve.c module. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 7 --- target/arm/tcg/tcg-sve.h | 5 ++ linux-user/syscall.c | 4 ++ target/arm/cpu-exceptions-aa64.c | 1 + target/arm/tcg/cpregs.c | 4 ++ target/arm/tcg/helper-a64.c | 1 + target/arm/tcg/helper.c | 87 -------------------------------- target/arm/tcg/tcg-sve.c | 86 +++++++++++++++++++++++++++++++ 8 files changed, 101 insertions(+), 94 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8614948543..3edf8bb4ec 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1056,9 +1056,6 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f,= CPUState *cs, #ifdef TARGET_AARCH64 int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); -void aarch64_sve_change_el(CPUARMState *env, int old_el, - int new_el, bool el0_a64); =20 static inline bool is_a64(CPUARMState *env) { @@ -1090,10 +1087,6 @@ static inline uint64_t *sve_bswap64(uint64_t *dst, u= int64_t *src, int nr) } =20 #else -static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } -static inline void aarch64_sve_change_el(CPUARMState *env, int o, - int n, bool a) -{ } =20 #define is_a64(env) ((void)env, false) =20 diff --git a/target/arm/tcg/tcg-sve.h b/target/arm/tcg/tcg-sve.h index 4bed809b9a..5855bb4289 100644 --- a/target/arm/tcg/tcg-sve.h +++ b/target/arm/tcg/tcg-sve.h @@ -21,4 +21,9 @@ uint32_t tcg_sve_disable_lens(unsigned long *sve_vq_map, bool tcg_sve_validate_lens(unsigned long *sve_vq_map, uint32_t max_vq, Error **errp); =20 +void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); + +void aarch64_sve_change_el(CPUARMState *env, int old_el, + int new_el, bool el0_a64); + #endif /* TCG_SVE_H */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index c9f812091c..db4b7b1e46 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -134,6 +134,10 @@ #include "fd-trans.h" #include "tcg/tcg.h" =20 +#ifdef TARGET_AARCH64 +#include "tcg/tcg-sve.h" +#endif /* TARGET_AARCH64 */ + #ifndef CLONE_IO #define CLONE_IO 0x80000000 /* Clone io context */ #endif diff --git a/target/arm/cpu-exceptions-aa64.c b/target/arm/cpu-exceptions-a= a64.c index 7daaba0426..adaf3bab17 100644 --- a/target/arm/cpu-exceptions-aa64.c +++ b/target/arm/cpu-exceptions-aa64.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" +#include "tcg/tcg-sve.h" #include "internals.h" #include "sysemu/tcg.h" =20 diff --git a/target/arm/tcg/cpregs.c b/target/arm/tcg/cpregs.c index 56d56f7f81..9d3c9ae841 100644 --- a/target/arm/tcg/cpregs.c +++ b/target/arm/tcg/cpregs.c @@ -16,6 +16,10 @@ #include "cpu-mmu.h" #include "cpregs.h" =20 +#ifdef TARGET_AARCH64 +#include "tcg/tcg-sve.h" +#endif /* TARGET_AARCH64 */ + #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ #define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */ =20 diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 9cc3b066e2..f261f13b2c 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "cpu.h" +#include "tcg/tcg-sve.h" #include "exec/gdbstub.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index 7136c82795..edc4b4cb4e 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -1294,90 +1294,3 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_u= long *pc, *pflags =3D flags.flags; *cs_base =3D flags.flags2; } - -#ifdef TARGET_AARCH64 -/* - * The manual says that when SVE is enabled and VQ is widened the - * implementation is allowed to zero the previously inaccessible - * portion of the registers. The corollary to that is that when - * SVE is enabled and VQ is narrowed we are also allowed to zero - * the now inaccessible portion of the registers. - * - * The intent of this is that no predicate bit beyond VQ is ever set. - * Which means that some operations on predicate registers themselves - * may operate on full uint64_t or even unrolled across the maximum - * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally - * may well be cheaper than conditionals to restrict the operation - * to the relevant portion of a uint16_t[16]. - */ -void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) -{ - int i, j; - uint64_t pmask; - - assert(vq >=3D 1 && vq <=3D ARM_MAX_VQ); - assert(vq <=3D env_archcpu(env)->sve_max_vq); - - /* Zap the high bits of the zregs. */ - for (i =3D 0; i < 32; i++) { - memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)); - } - - /* Zap the high bits of the pregs and ffr. */ - pmask =3D 0; - if (vq & 3) { - pmask =3D ~(-1ULL << (16 * (vq & 3))); - } - for (j =3D vq / 4; j < ARM_MAX_VQ / 4; j++) { - for (i =3D 0; i < 17; ++i) { - env->vfp.pregs[i].p[j] &=3D pmask; - } - pmask =3D 0; - } -} - -/* - * Notice a change in SVE vector size when changing EL. - */ -void aarch64_sve_change_el(CPUARMState *env, int old_el, - int new_el, bool el0_a64) -{ - ARMCPU *cpu =3D env_archcpu(env); - int old_len, new_len; - bool old_a64, new_a64; - - /* Nothing to do if no SVE. */ - if (!cpu_isar_feature(aa64_sve, cpu)) { - return; - } - - /* Nothing to do if FP is disabled in either EL. */ - if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) { - return; - } - - /* - * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped - * at ELx, or not available because the EL is in AArch32 state, then - * for all purposes other than a direct read, the ZCR_ELx.LEN field - * has an effective value of 0". - * - * Consider EL2 (aa64, vq=3D4) -> EL0 (aa32) -> EL1 (aa64, vq=3D0). - * If we ignore aa32 state, we would fail to see the vq4->vq0 transiti= on - * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so t= hat - * we already have the correct register contents when encountering the - * vq0->vq0 transition between EL0->EL1. - */ - old_a64 =3D old_el ? arm_el_is_aa64(env, old_el) : el0_a64; - old_len =3D (old_a64 && !sve_exception_el(env, old_el) - ? sve_zcr_len_for_el(env, old_el) : 0); - new_a64 =3D new_el ? arm_el_is_aa64(env, new_el) : el0_a64; - new_len =3D (new_a64 && !sve_exception_el(env, new_el) - ? sve_zcr_len_for_el(env, new_el) : 0); - - /* When changing vector length, clear inaccessible state. */ - if (new_len < old_len) { - aarch64_sve_narrow_vq(env, new_len + 1); - } -} -#endif diff --git a/target/arm/tcg/tcg-sve.c b/target/arm/tcg/tcg-sve.c index 99cfde1f41..908d2c2f2c 100644 --- a/target/arm/tcg/tcg-sve.c +++ b/target/arm/tcg/tcg-sve.c @@ -24,6 +24,7 @@ #include "sysemu/tcg.h" #include "cpu-sve.h" #include "tcg-sve.h" +#include "cpu-exceptions-aa64.h" =20 void tcg_sve_enable_lens(unsigned long *sve_vq_map, unsigned long *sve_vq_init, uint32_t max_vq) @@ -79,3 +80,88 @@ bool tcg_sve_validate_lens(unsigned long *sve_vq_map, ui= nt32_t max_vq, } return true; } + +/* + * The manual says that when SVE is enabled and VQ is widened the + * implementation is allowed to zero the previously inaccessible + * portion of the registers. The corollary to that is that when + * SVE is enabled and VQ is narrowed we are also allowed to zero + * the now inaccessible portion of the registers. + * + * The intent of this is that no predicate bit beyond VQ is ever set. + * Which means that some operations on predicate registers themselves + * may operate on full uint64_t or even unrolled across the maximum + * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally + * may well be cheaper than conditionals to restrict the operation + * to the relevant portion of a uint16_t[16]. + */ +void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) +{ + int i, j; + uint64_t pmask; + + assert(vq >=3D 1 && vq <=3D ARM_MAX_VQ); + assert(vq <=3D env_archcpu(env)->sve_max_vq); + + /* Zap the high bits of the zregs. */ + for (i =3D 0; i < 32; i++) { + memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq)); + } + + /* Zap the high bits of the pregs and ffr. */ + pmask =3D 0; + if (vq & 3) { + pmask =3D ~(-1ULL << (16 * (vq & 3))); + } + for (j =3D vq / 4; j < ARM_MAX_VQ / 4; j++) { + for (i =3D 0; i < 17; ++i) { + env->vfp.pregs[i].p[j] &=3D pmask; + } + pmask =3D 0; + } +} + +/* + * Notice a change in SVE vector size when changing EL. + */ +void aarch64_sve_change_el(CPUARMState *env, int old_el, + int new_el, bool el0_a64) +{ + ARMCPU *cpu =3D env_archcpu(env); + int old_len, new_len; + bool old_a64, new_a64; + + /* Nothing to do if no SVE. */ + if (!cpu_isar_feature(aa64_sve, cpu)) { + return; + } + + /* Nothing to do if FP is disabled in either EL. */ + if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) { + return; + } + + /* + * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped + * at ELx, or not available because the EL is in AArch32 state, then + * for all purposes other than a direct read, the ZCR_ELx.LEN field + * has an effective value of 0". + * + * Consider EL2 (aa64, vq=3D4) -> EL0 (aa32) -> EL1 (aa64, vq=3D0). + * If we ignore aa32 state, we would fail to see the vq4->vq0 transiti= on + * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so t= hat + * we already have the correct register contents when encountering the + * vq0->vq0 transition between EL0->EL1. + */ + old_a64 =3D old_el ? arm_el_is_aa64(env, old_el) : el0_a64; + old_len =3D (old_a64 && !sve_exception_el(env, old_el) + ? sve_zcr_len_for_el(env, old_el) : 0); + new_a64 =3D new_el ? arm_el_is_aa64(env, new_el) : el0_a64; + new_len =3D (new_a64 && !sve_exception_el(env, new_el) + ? sve_zcr_len_for_el(env, new_el) : 0); + + /* When changing vector length, clear inaccessible state. */ + if (new_len < old_len) { + aarch64_sve_narrow_vq(env, new_len + 1); + } +} --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622826886; cv=none; d=zohomail.com; s=zohoarc; b=Bye99w/B2KjN7VufaDxtUJqI1fAAwqxGxEDmSv5tHbGiw1cEvrULI0zSf8AD5wtvyv8JiD0/pEZ/HEDstYnFOTBIPOwS3MWBOsfHmgGuq0YSBbTeSETt22hqtg9dDP2y5QmDEHENu+rm5IJAzyMsL5yDeLbDjIJUpAF/fFrhjIA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622826886; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Q8h+n24TrWRUxnaytAqdbGvuFIoi1mcRJzQRuLb50YQ=; b=Hley9cV7QR9XtCGwQb6ihV6WBJ8w7ydQeROBmhkD+EQTqsbvMRlB+q//MA3qja3r/SpYUKcszgE6wNfLM3ystx7dg/TMvSORl9zFquYscr2+yKiduZnoUOzG3kU1um2GKGnTK3yWn77uaIPGalLazfsh85Xag/1KLS6TkxLHHeQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622826886400912.649979964741; Fri, 4 Jun 2021 10:14:46 -0700 (PDT) Received: from localhost ([::1]:57306 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDPB-0002Xj-LN for importer@patchew.org; Fri, 04 Jun 2021 13:14:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48602) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpDNC-0007ur-UT for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:42 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:46023) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpDNA-00020l-Tv for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:42 -0400 Received: by mail-wr1-x42d.google.com with SMTP id z8so9998281wrp.12 for ; Fri, 04 Jun 2021 10:12:40 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id c23sm9282915wme.37.2021.06.04.10.12.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 10:12:38 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id B17C01FFF5; Fri, 4 Jun 2021 16:53:22 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Q8h+n24TrWRUxnaytAqdbGvuFIoi1mcRJzQRuLb50YQ=; b=OVAumHYklZRMtwRNTiCaSZlgF4QkU5a0aQPMUKMfJ67aVsDtkJxZ4wXFMgJNg2jNRE R7EbQqyN3+zU8k3ian76Gpyor1iea8pwgjfaUz6VLIFHNeMnfc3ciQRomR78kMSDxxH6 z8Qpz1qGrieO5m/3CjzZfnw+t374pgevuuuWxOmIEAjgTySUmMbLWMyU3xu2ScejJewP d3cSE+BwNpTAJxCg2KabRaJ2jEXDTc229qqRTh0OXooR1QxvYpztjanGMggl3lUbK3Vz Z7sggk9piSf7TTBJY6CfVEr0mreZAw1qZsvYLWgLZ+P8dfgpEAk0iYh4iALznyCAJ8H8 IX7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q8h+n24TrWRUxnaytAqdbGvuFIoi1mcRJzQRuLb50YQ=; b=ZbkH9kG0F4YMJpmqf5jK/iQd1K3vdjHvZoVMLm6836on76hyl30IMpN75w6HkVtlNR OgLrr7XMJAVZgHBtekOtaFbyI5YH45y2TMieWu4vWbSipIkoY3KH06EaXcBGEJkbRz+F Bdac8GbLPwBRwMsGwag/8qkFJK1lmrkelk7J2jFI2BCibsfRWZUVhaa4tSl+wPwhlbcB /GMQsoNE1gsyYm6Lzi8rEGJO9fZoNcXdvm09a2+Hf08C7x4Zd8nELA7ymjkJ4n6YHcDm cPw+lEG4InBdvERKRcgfcFUNYajvaEaIjX5WxMXA5dJosG8z6vJ2YRjdGT2cEa19GYJx 47LQ== X-Gm-Message-State: AOAM532glOAUe04gwwM/gFc2tod5aFwrhaf0YzW+gY0CWGc3UlgqAZYS 4marMSeItJDU5d4qKcBnH5uWmQ== X-Google-Smtp-Source: ABdhPJxweXeM0C8cPpbzf4aVKymFRYAbku1nYroKp34BFmbglNMoAWh7IUpWB5XTXFRwS1Tqcr1tVw== X-Received: by 2002:adf:bc06:: with SMTP id s6mr5147755wrg.250.1622826759038; Fri, 04 Jun 2021 10:12:39 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 81/99] target/arm: tcg-sve: rename the narrow_vq and change_el functions Date: Fri, 4 Jun 2021 16:52:54 +0100 Message-Id: <20210604155312.15902-82-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , Laurent Vivier , qemu-arm@nongnu.org, Claudio Fontana , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana make them canonical for the module name. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/tcg-sve.h | 6 +++--- linux-user/syscall.c | 2 +- target/arm/cpu-exceptions-aa64.c | 2 +- target/arm/tcg/cpregs.c | 2 +- target/arm/tcg/helper-a64.c | 2 +- target/arm/tcg/tcg-sve.c | 6 +++--- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/arm/tcg/tcg-sve.h b/target/arm/tcg/tcg-sve.h index 5855bb4289..46e42d1139 100644 --- a/target/arm/tcg/tcg-sve.h +++ b/target/arm/tcg/tcg-sve.h @@ -21,9 +21,9 @@ uint32_t tcg_sve_disable_lens(unsigned long *sve_vq_map, bool tcg_sve_validate_lens(unsigned long *sve_vq_map, uint32_t max_vq, Error **errp); =20 -void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); +void tcg_sve_narrow_vq(CPUARMState *env, unsigned vq); =20 -void aarch64_sve_change_el(CPUARMState *env, int old_el, - int new_el, bool el0_a64); +void tcg_sve_change_el(CPUARMState *env, int old_el, + int new_el, bool el0_a64); =20 #endif /* TCG_SVE_H */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index db4b7b1e46..4cfbe72b21 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10877,7 +10877,7 @@ static abi_long do_syscall1(void *cpu_env, int num,= abi_long arg1, vq =3D MIN(vq, cpu->sve_max_vq); =20 if (vq < old_vq) { - aarch64_sve_narrow_vq(env, vq); + tcg_sve_narrow_vq(env, vq); } env->vfp.zcr_el[1] =3D vq - 1; arm_rebuild_hflags(env); diff --git a/target/arm/cpu-exceptions-aa64.c b/target/arm/cpu-exceptions-a= a64.c index adaf3bab17..1a3e1d6458 100644 --- a/target/arm/cpu-exceptions-aa64.c +++ b/target/arm/cpu-exceptions-aa64.c @@ -119,7 +119,7 @@ void arm_cpu_do_interrupt_aarch64(CPUState *cs) * Note that new_el can never be 0. If cur_el is 0, then * el0_a64 is is_a64(), else el0_a64 is ignored. */ - aarch64_sve_change_el(env, cur_el, new_el, is_a64(env)); + tcg_sve_change_el(env, cur_el, new_el, is_a64(env)); } =20 if (cur_el < new_el) { diff --git a/target/arm/tcg/cpregs.c b/target/arm/tcg/cpregs.c index 9d3c9ae841..9d4ac66281 100644 --- a/target/arm/tcg/cpregs.c +++ b/target/arm/tcg/cpregs.c @@ -5814,7 +5814,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, */ new_len =3D sve_zcr_len_for_el(env, cur_el); if (new_len < old_len) { - aarch64_sve_narrow_vq(env, new_len + 1); + tcg_sve_narrow_vq(env, new_len + 1); } } =20 diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index f261f13b2c..e169c03c63 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -1042,7 +1042,7 @@ void HELPER(exception_return)(CPUARMState *env, uint6= 4_t new_pc) * Note that cur_el can never be 0. If new_el is 0, then * el0_a64 is return_to_aa64, else el0_a64 is ignored. */ - aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64); + tcg_sve_change_el(env, cur_el, new_el, return_to_aa64); =20 qemu_mutex_lock_iothread(); arm_call_el_change_hook(env_archcpu(env)); diff --git a/target/arm/tcg/tcg-sve.c b/target/arm/tcg/tcg-sve.c index 908d2c2f2c..25d5a5867c 100644 --- a/target/arm/tcg/tcg-sve.c +++ b/target/arm/tcg/tcg-sve.c @@ -95,7 +95,7 @@ bool tcg_sve_validate_lens(unsigned long *sve_vq_map, uin= t32_t max_vq, * may well be cheaper than conditionals to restrict the operation * to the relevant portion of a uint16_t[16]. */ -void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) +void tcg_sve_narrow_vq(CPUARMState *env, unsigned vq) { int i, j; uint64_t pmask; @@ -124,7 +124,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned v= q) /* * Notice a change in SVE vector size when changing EL. */ -void aarch64_sve_change_el(CPUARMState *env, int old_el, +void tcg_sve_change_el(CPUARMState *env, int old_el, int new_el, bool el0_a64) { ARMCPU *cpu =3D env_archcpu(env); @@ -162,6 +162,6 @@ void aarch64_sve_change_el(CPUARMState *env, int old_el, =20 /* When changing vector length, clear inaccessible state. */ if (new_len < old_len) { - aarch64_sve_narrow_vq(env, new_len + 1); + tcg_sve_narrow_vq(env, new_len + 1); } } --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622824608; cv=none; d=zohomail.com; s=zohoarc; b=eC0W+j5ZEfnc6Zgk1wizP3T1XUzhtf4wLukYmBlDUy/WN4LCA+IYg1S4tgzHiFWOk3NhMpfm6Z9tOElzKKf7JZCLIPce7gmSdAf+g97CLZDCl/bllvyXBcQQ4uVm+UB4JeTFnLq/dM8/rE/8T4WRKOba/scMx+lP+KqkiAlujTg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622824608; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YLNKH6WMEOpMy9rbclft4o2lCy4Z7+mVhGSkPGtULLE=; b=OAR2DhRtlDNUd7g8ku5O1pAvA6p+l2ieZm2TLqZ5hFY0Gz3lZn0woHXA0wUtGwPCEQBCFATxvyFEha+dXaFIHc51c+fGruOJtlf0Q9CwadDDtbh6wXx3vYx6itWWzC7k4KLwN4QDAqJlYozFYwWFXk2Ypo24Dyd71v1FSqPNuwY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622824608045781.668510269991; Fri, 4 Jun 2021 09:36:48 -0700 (PDT) Received: from localhost ([::1]:43716 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCoQ-0008Ca-SE for importer@patchew.org; Fri, 04 Jun 2021 12:36:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52066) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCRU-0003E0-PV for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:13:06 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:55149) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCRL-0003rr-E9 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:13:04 -0400 Received: by mail-wm1-x329.google.com with SMTP id o127so5694414wmo.4 for ; Fri, 04 Jun 2021 09:12:54 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id a12sm5974399wmj.36.2021.06.04.09.12.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:12:52 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id D4AA71FFF6; Fri, 4 Jun 2021 16:53:22 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YLNKH6WMEOpMy9rbclft4o2lCy4Z7+mVhGSkPGtULLE=; b=EknOOgdUdP7RZfsZU2t6/2TJqfmiN7AvQ7GY/cTZ0Iei400/sBpXExpok5jn6i/mjF mve4BU73qU4B3sORAkOAgjnDZSt802eUqDVleFLRQbw1Z/MAU0xIBcvwRi8hNbNnHtNX ZeRQYlACHiFWPdgUlzJVag4i4UU3TXk0N2KTSmov3VuPl18R5nTSe2J5Jq8pi2YutFh6 vBNtntVGf909NpqPpdAp37HU1MUTusNODW3/NFEBLftAQx/6ZV+Els3vHSIcBWqIYz8f 4AiVOslN4ieIF96iPobJcMz/6IDA4sPnjuJ+Ocmii431oxEi+g1jQCpWMWyNlVpUKmYc OIrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YLNKH6WMEOpMy9rbclft4o2lCy4Z7+mVhGSkPGtULLE=; b=UGqJbwfFpZYxFugHNlWxoJhZAxD9ZOQqDKkedcIOrrtK4gpzU5sSM2ZVrf2ltcO66G AWc/7whEW2l3I+FG8fqhF6lMNbZEP7X6dzIhcH9fOzzYteS0BXNsdPVQQ6iUprLECTle nsZ2dToVm8F77gWW+BFuNm9VzRm6ACRcRN5cipklHYnG93oCBOjNFCe3s2NaX5z0J3y+ LMvPpoWSOgLGeVHNFNFzzs011HJroZGcdEilr+WvBcFdgz5+Y3OvswvVZvGaPUXvjb7W JcixxSzIfvYW4OSFXusDEsyYbQyVIPI5HbIzAHF8Y14m5fzNmxoNP0th3e3AfUvemP56 x1Vg== X-Gm-Message-State: AOAM53163r5oLP5kK/s5wswS6cS9gOiOQc37lGRCz900nXi86OSmy5hC yX+enyHQBRLJZKY8uFTHn3eJHw== X-Google-Smtp-Source: ABdhPJw/CQLfVlqV4ClCXY5KLfMzQ+VT98gmjQQAQGb124xUO9CausihVeJ6y7lTV0GHoyffryjLzA== X-Received: by 2002:a05:600c:4ba4:: with SMTP id e36mr3799460wmp.28.1622823173878; Fri, 04 Jun 2021 09:12:53 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 82/99] target/arm: move sve_zcr_len_for_el to TARGET_AARCH64-only cpu-sve Date: Fri, 4 Jun 2021 16:52:55 +0100 Message-Id: <20210604155312.15902-83-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana now that we handled the dependency between HELPER(), cpregs defs and functions in tcg/, we can make sve_zcr_len_for_el TARGET_AARCH64-only, and move it to the cpu-sve module. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-sve.h | 3 +++ target/arm/cpu.h | 4 ++-- target/arm/arch_dump.c | 1 + target/arm/cpu-common.c | 43 ----------------------------------------- target/arm/cpu-sve.c | 33 +++++++++++++++++++++++++++++++ target/arm/cpu.c | 4 ++++ target/arm/tcg/cpregs.c | 1 + target/arm/tcg/helper.c | 4 ++++ 8 files changed, 48 insertions(+), 45 deletions(-) diff --git a/target/arm/cpu-sve.h b/target/arm/cpu-sve.h index 6ab74b1d8f..1512c56a6b 100644 --- a/target/arm/cpu-sve.h +++ b/target/arm/cpu-sve.h @@ -34,4 +34,7 @@ void cpu_sve_add_props(Object *obj); /* add the CPU SVE properties specific to the "MAX" CPU */ void cpu_sve_add_props_max(Object *obj); =20 +/* return the vector length for EL */ +uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); + #endif /* CPU_SVE_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3edf8bb4ec..e9bfb6f575 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -223,7 +223,8 @@ typedef struct ARMPACKey { } ARMPACKey; #else static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } -#endif + +#endif /* TARGET_AARCH64 */ =20 /* See the commentary above the TBFLAG field definitions. */ typedef struct CPUARMTBFlags { @@ -1097,7 +1098,6 @@ void aarch64_sync_64_to_32(CPUARMState *env); =20 int fp_exception_el(CPUARMState *env, int cur_el); int sve_exception_el(CPUARMState *env, int cur_el); -uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); =20 /* you can call this signal handler from your SIGBUS and SIGSEGV signal handlers to inform the virtual CPU of exceptions. non zero diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 9cc75a6fda..9b2e76f5a7 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -24,6 +24,7 @@ #include "sysemu/dump.h" =20 #ifdef TARGET_AARCH64 +#include "cpu-sve.h" =20 /* struct user_pt_regs from arch/arm64/include/uapi/asm/ptrace.h */ struct aarch64_user_regs { diff --git a/target/arm/cpu-common.c b/target/arm/cpu-common.c index f4a3780e9e..b7a199a8d6 100644 --- a/target/arm/cpu-common.c +++ b/target/arm/cpu-common.c @@ -301,49 +301,6 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) return ret; } =20 -/* - * these are AARCH64-only, but due to the chain of dependencies, - * between HELPER prototypes, hflags, cpreg definitions and functions in - * tcg/ etc, it becomes incredibly messy to add what should be here: - * - * #ifdef TARGET_AARCH64 - */ - -static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) -{ - uint32_t end_len; - - end_len =3D start_len &=3D 0xf; - if (!test_bit(start_len, cpu->sve_vq_map)) { - end_len =3D find_last_bit(cpu->sve_vq_map, start_len); - assert(end_len < start_len); - } - return end_len; -} - -/* - * Given that SVE is enabled, return the vector length for EL. - */ -uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) -{ - ARMCPU *cpu =3D env_archcpu(env); - uint32_t zcr_len =3D cpu->sve_max_vq - 1; - - if (el <=3D 1) { - zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); - } - if (el <=3D 2 && arm_feature(env, ARM_FEATURE_EL2)) { - zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); - } - if (arm_feature(env, ARM_FEATURE_EL3)) { - zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); - } - - return sve_zcr_get_valid_len(cpu, zcr_len); -} - -/* #endif TARGET_AARCH64 , see matching comment above */ - uint64_t arm_sctlr(CPUARMState *env, int el) { /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ diff --git a/target/arm/cpu-sve.c b/target/arm/cpu-sve.c index 24bffbba8b..e8e817e110 100644 --- a/target/arm/cpu-sve.c +++ b/target/arm/cpu-sve.c @@ -288,3 +288,36 @@ void cpu_sve_add_props_max(Object *obj) { object_property_add(obj, "sve-max-vq", "uint32", get_prop_max_vq, set_= prop_max_vq, NULL, NULL); } + +static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) +{ + uint32_t end_len; + + end_len =3D start_len &=3D 0xf; + if (!test_bit(start_len, cpu->sve_vq_map)) { + end_len =3D find_last_bit(cpu->sve_vq_map, start_len); + assert(end_len < start_len); + } + return end_len; +} + +/* + * Given that SVE is enabled, return the vector length for EL. + */ +uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) +{ + ARMCPU *cpu =3D env_archcpu(env); + uint32_t zcr_len =3D cpu->sve_max_vq - 1; + + if (el <=3D 1) { + zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); + } + if (el <=3D 2 && arm_feature(env, ARM_FEATURE_EL2)) { + zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); + } + if (arm_feature(env, ARM_FEATURE_EL3)) { + zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); + } + + return sve_zcr_get_valid_len(cpu, zcr_len); +} diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b297d0e6aa..0e41854b92 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -23,7 +23,11 @@ #include "target/arm/idau.h" #include "qapi/error.h" #include "cpu.h" + +#ifdef TARGET_AARCH64 #include "cpu-sve.h" +#endif /* TARGET_AARCH64 */ + #include "cpregs.h" =20 #ifdef CONFIG_TCG diff --git a/target/arm/tcg/cpregs.c b/target/arm/tcg/cpregs.c index 9d4ac66281..c971dc6097 100644 --- a/target/arm/tcg/cpregs.c +++ b/target/arm/tcg/cpregs.c @@ -17,6 +17,7 @@ #include "cpregs.h" =20 #ifdef TARGET_AARCH64 +#include "cpu-sve.h" #include "tcg/tcg-sve.h" #endif /* TARGET_AARCH64 */ =20 diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index edc4b4cb4e..984dae7643 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -18,6 +18,10 @@ #include "cpregs.h" #include "tcg-cpu.h" =20 +#ifdef TARGET_AARCH64 +#include "cpu-sve.h" +#endif /* TARGET_AARCH64 */ + static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg) { ARMCPU *cpu =3D env_archcpu(env); --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622826495; cv=none; d=zohomail.com; s=zohoarc; b=NwO/8xCDE5wk/v5yNkkytC2HSKQ5VryE80bm78WvFX+L9hskzhFJ3eMBnnBRWJA293peB+9PqYD4zijTl6hg1hGbYL2OGmI47YcYzkblUh61uOge36QZseXc8/px6z/n4dEAJnqO37tVc5vLas0bMmTKmsTHSzwh2ZmH/6vaRTY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622826495; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jq4lq9iuiQPC9xlaM7lJ7USLdiB1vnToi4qLCV27AdQ=; b=kGhXXiDYvcuMA35uuf/BsnVJwsXIHJ4CDxwiTxLgZh53v/POGWPtgdgXCoRyiLcWsxWPAOu+CXP/6bLtYZjMtFXs44yr6lGjkRFZ4MMiD3Q14xG8L9xfRDmlT6DbnJ78hUyBFMiJ6CFZovnGL0nyRqMtvOWKfyg15Ul24ifg1FQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622826495480164.03191173935204; Fri, 4 Jun 2021 10:08:15 -0700 (PDT) Received: from localhost ([::1]:37154 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDIr-0005Xv-R6 for importer@patchew.org; Fri, 04 Jun 2021 13:08:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51908) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCRL-00033I-O0 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:56 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:42645) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCRE-0003q3-SP for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:55 -0400 Received: by mail-wr1-x432.google.com with SMTP id c5so9823048wrq.9 for ; Fri, 04 Jun 2021 09:12:48 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id g17sm2392705wrp.61.2021.06.04.09.12.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:12:43 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 036231FFF7; Fri, 4 Jun 2021 16:53:23 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jq4lq9iuiQPC9xlaM7lJ7USLdiB1vnToi4qLCV27AdQ=; b=CCxB3m4/qWB+FBCB5RYuIyfdzCHrqKav2Y/P3/CKCBiNLyAcmaFVd+pLOAdDnOavjH Nd74xIo731m5pKaJptlAGHYP/eNNXdnVF+BuF7yszNPMjJUJvQVJ4lwIY6SD1nkId2jc U/ZjCte5ozm/kiuNCjIPLFmtJ7TSZgrC9SbTsHkpD5WozzLF71gjj2knuIo346/PpJDN GdBHMOuSWAH7ZwsDHjf4jXy3O58rQaUwnYl0bTM1reTs5LtALEcajQ07veI/UQpKDIp9 JlKn2UlOzRj0zLQYFQX2C0jR5fJ/aVK670W4Dx3w34QGptt0VEbvOJY1kw1QzII8M2js nV1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jq4lq9iuiQPC9xlaM7lJ7USLdiB1vnToi4qLCV27AdQ=; b=Csi79o9M2Q+gE+4TddAA1WuEBvcYS3cXxYRNTpxb9Tg1tcR15c+HLQSVH2cdf/ktdp co3scI04VJmkHPueClcDw2Djw4eowL22CN+Iq9BBh6UMv65r6wtq0lx2bAPqVmSgsGMk BKPwOivZg7xvgfNS5d+VOAggP30oGmAJbxtmdw8eIwvyKqHVM4ue7ssSFBeDuq1AKV7R 8Sin3ZbauZK6Z0KlzChJ4/bEVncd/KyUQIGe6BeGpMS5SFlJAdvkOzlDsblpZiAOIOC5 6/hRuhBSOz40M2Xfw2Rx9wBhQd98FKOsYfDRcxMLB0yvuauFNSe/OMEJyHoFuamYuFtj EXxg== X-Gm-Message-State: AOAM532OHz8qENW2GjhovPi6/BlF/Tftf/E2tPvXsHd5UqfH4mPbCFg0 ZI7sjoS/sODkhdcsXNN6naXWmg== X-Google-Smtp-Source: ABdhPJxkgEzcBc542kOogVH4Jt2jO79PP4zGIrFIxTANYxOJzTFWjCB2nPUPh7qZkQDhOH+D9llvPQ== X-Received: by 2002:a05:6000:2c1:: with SMTP id o1mr4718171wry.425.1622823167538; Fri, 04 Jun 2021 09:12:47 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 83/99] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el Date: Fri, 4 Jun 2021 16:52:56 +0100 Message-Id: <20210604155312.15902-84-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana use a canonical module prefix followed by the get_zcr_len_for_el() method name. Also rename the static internal auxiliary function, where the module prefix is not necessary. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-sve.h | 2 +- target/arm/arch_dump.c | 2 +- target/arm/cpu-sve.c | 6 +++--- target/arm/cpu64.c | 2 +- target/arm/tcg/cpregs.c | 4 ++-- target/arm/tcg/helper.c | 4 ++-- target/arm/tcg/tcg-sve.c | 4 ++-- 7 files changed, 12 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu-sve.h b/target/arm/cpu-sve.h index 1512c56a6b..c83508ea0a 100644 --- a/target/arm/cpu-sve.h +++ b/target/arm/cpu-sve.h @@ -35,6 +35,6 @@ void cpu_sve_add_props(Object *obj); void cpu_sve_add_props_max(Object *obj); =20 /* return the vector length for EL */ -uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); +uint32_t cpu_sve_get_zcr_len_for_el(CPUARMState *env, int el); =20 #endif /* CPU_SVE_H */ diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 9b2e76f5a7..f192c8df97 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -168,7 +168,7 @@ static off_t sve_fpcr_offset(uint32_t vq) =20 static uint32_t sve_current_vq(CPUARMState *env) { - return sve_zcr_len_for_el(env, arm_current_el(env)) + 1; + return cpu_sve_get_zcr_len_for_el(env, arm_current_el(env)) + 1; } =20 static size_t sve_size_vq(uint32_t vq) diff --git a/target/arm/cpu-sve.c b/target/arm/cpu-sve.c index e8e817e110..1bc8c0bdb0 100644 --- a/target/arm/cpu-sve.c +++ b/target/arm/cpu-sve.c @@ -289,7 +289,7 @@ void cpu_sve_add_props_max(Object *obj) object_property_add(obj, "sve-max-vq", "uint32", get_prop_max_vq, set_= prop_max_vq, NULL, NULL); } =20 -static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) +static uint32_t get_valid_len(ARMCPU *cpu, uint32_t start_len) { uint32_t end_len; =20 @@ -304,7 +304,7 @@ static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint= 32_t start_len) /* * Given that SVE is enabled, return the vector length for EL. */ -uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) +uint32_t cpu_sve_get_zcr_len_for_el(CPUARMState *env, int el) { ARMCPU *cpu =3D env_archcpu(env); uint32_t zcr_len =3D cpu->sve_max_vq - 1; @@ -319,5 +319,5 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); } =20 - return sve_zcr_get_valid_len(cpu, zcr_len); + return get_valid_len(cpu, zcr_len); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 03ed637bdb..67b35feb17 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -549,7 +549,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *= f, int flags) vfp_get_fpcr(env), vfp_get_fpsr(env)); =20 if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) =3D= =3D 0) { - int j, zcr_len =3D sve_zcr_len_for_el(env, el); + int j, zcr_len =3D cpu_sve_get_zcr_len_for_el(env, el); =20 for (i =3D 0; i <=3D FFR_PRED_NUM; i++) { bool eol; diff --git a/target/arm/tcg/cpregs.c b/target/arm/tcg/cpregs.c index c971dc6097..9118f4347c 100644 --- a/target/arm/tcg/cpregs.c +++ b/target/arm/tcg/cpregs.c @@ -5802,7 +5802,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) { int cur_el =3D arm_current_el(env); - int old_len =3D sve_zcr_len_for_el(env, cur_el); + int old_len =3D cpu_sve_get_zcr_len_for_el(env, cur_el); int new_len; =20 /* Bits other than [3:0] are RAZ/WI. */ @@ -5813,7 +5813,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, * Because we arrived here, we know both FP and SVE are enabled; * otherwise we would have trapped access to the ZCR_ELn register. */ - new_len =3D sve_zcr_len_for_el(env, cur_el); + new_len =3D cpu_sve_get_zcr_len_for_el(env, cur_el); if (new_len < old_len) { tcg_sve_narrow_vq(env, new_len + 1); } diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index 984dae7643..fff185f422 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -186,7 +186,7 @@ static int arm_gdb_get_svereg(CPUARMState *env, GByteAr= ray *buf, int reg) * We report in Vector Granules (VG) which is 64bit in a Z reg * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. */ - int vq =3D sve_zcr_len_for_el(env, arm_current_el(env)) + 1; + int vq =3D cpu_sve_get_zcr_len_for_el(env, arm_current_el(env)) + = 1; return gdb_get_reg64(buf, vq * 2); } default: @@ -1034,7 +1034,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *= env, int el, int fp_el, if (sve_el !=3D 0 && fp_el =3D=3D 0) { zcr_len =3D 0; } else { - zcr_len =3D sve_zcr_len_for_el(env, el); + zcr_len =3D cpu_sve_get_zcr_len_for_el(env, el); } DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); DP_TBFLAG_A64(flags, ZCR_LEN, zcr_len); diff --git a/target/arm/tcg/tcg-sve.c b/target/arm/tcg/tcg-sve.c index 25d5a5867c..80a37caf6e 100644 --- a/target/arm/tcg/tcg-sve.c +++ b/target/arm/tcg/tcg-sve.c @@ -155,10 +155,10 @@ void tcg_sve_change_el(CPUARMState *env, int old_el, */ old_a64 =3D old_el ? arm_el_is_aa64(env, old_el) : el0_a64; old_len =3D (old_a64 && !sve_exception_el(env, old_el) - ? sve_zcr_len_for_el(env, old_el) : 0); + ? cpu_sve_get_zcr_len_for_el(env, old_el) : 0); new_a64 =3D new_el ? arm_el_is_aa64(env, new_el) : el0_a64; new_len =3D (new_a64 && !sve_exception_el(env, new_el) - ? sve_zcr_len_for_el(env, new_el) : 0); + ? cpu_sve_get_zcr_len_for_el(env, new_el) : 0); =20 /* When changing vector length, clear inaccessible state. */ if (new_len < old_len) { --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622825976; cv=none; d=zohomail.com; s=zohoarc; b=EMa40UmhHlEGtHEbe0W14zyJWcotgqtQZh+kFF0zVvI4ZKOSSy9Jgf12ur8a/HvrDI9m26BDGPOCmo2BEEOLseW+7vD+KWzzrUB+pgzcuDWuiYkA4XQm0yqYEcR1PGo3nEUF/MMdmsjeNuHruNg1uU5hrQSKNvupo/9cpkKEZp8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622825976; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dQ5wxdfmiKKfim62JoM4B+biad6w8O8eV+yYLw/gu6A=; b=hWAmw49jkhQI3bswZG3ozmVhJXZ3BiyjOp3W9iH7k/y9yBttAsoYvSbpBFuzsNXzstWY7Y3ZLikdGH3UrkFk794bJUnfA58igABB3IbjhETSyLkWbqKDSzyWGFW5Ko50aftkOd4CSYEu0DdgTjeuo/4DKB9DfR9tYFFuJgkEO+8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622825976611938.1777548088724; Fri, 4 Jun 2021 09:59:36 -0700 (PDT) Received: from localhost ([::1]:36590 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDAV-0002T4-GG for importer@patchew.org; Fri, 04 Jun 2021 12:59:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51666) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCRC-0002g5-A8 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:46 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:45998) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCR7-0003nJ-Tc for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:46 -0400 Received: by mail-wr1-x42b.google.com with SMTP id z8so9831691wrp.12 for ; Fri, 04 Jun 2021 09:12:41 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id u7sm1508669wrt.18.2021.06.04.09.12.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:12:37 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 1A3B920002; Fri, 4 Jun 2021 16:53:23 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dQ5wxdfmiKKfim62JoM4B+biad6w8O8eV+yYLw/gu6A=; b=UJ5lzGopsP9AQtjSgFaH1tpTRzHkHZ/Vq1B2TWuYenV1Wu/faEwBOseEXSRS5oigbX +4CSqyhboHFqh5+npL7V6R6cxMq/jE8LvXbq5G/46qWnKOOyWbI+ifSQcOnDbwM3HC66 vyd7X1wxtPPCP3vmso89pBgQ1k3vEV6gfJu1QG4fNlKLqR5wMS6v0WgFSzTnSUItHsde su25ryqMMGLLXTyDYevVndq4Pw/RhI+O3PP/HXKibfnYP/bTS0a6zM7yWYA2VrCEqRGe FfRE277Derg5DcQy6/gWZR1luhFS9CN8dkuNrM8NNEOUj8p4Y3p39C5nWjEC2mdG0NsR g2XA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dQ5wxdfmiKKfim62JoM4B+biad6w8O8eV+yYLw/gu6A=; b=g36zxwWmLppCBeqtvOH96A6j7KmYKaWWutJ27BDylDo3fiQ48YLcuysAqB7t39BHFV Hd18q8BkrydbzG43cUzShV8WQZWDAJBv1RVnPBWFqd92zzGPt5RrjyH0Xd7e9ahfP4qd BdxnqXRjnGq3lNj3VFLuKgicIeqp28YGXEvDhTEWiadLlVr3JQWZGKBDhpW3ZOIKQJT0 UEHdkFE38gQRZ54C+W/dy7rYIehi9uDouNfrOd17wS/2cfGMFpd2APpSUbyB8M0eK3Ps 6RlT6bkqLFdgwqdlLvK1hNi4jlZoLSfvZpujCTmruAd7Qs1X31aRXvRDrodAaRVO537P MHyQ== X-Gm-Message-State: AOAM533zHZBeDuM+n993OwDFEp9l9vSHAnS8F3v+vz7suNy+enoH47yI JFL2d5zQ+FZb6Hk4iBlFoQ9LOA== X-Google-Smtp-Source: ABdhPJy0E5A78t5pbqJPgPl2OKCYyJ4M2NiHTQjl/OPl++T7//3MFdFkbe169O/lMiNl+dW7b4IwFw== X-Received: by 2002:a5d:4287:: with SMTP id k7mr4860461wrq.98.1622823160471; Fri, 04 Jun 2021 09:12:40 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 84/99] target/arm: cpu-common: wrap a64-only check with is_a64 Date: Fri, 4 Jun 2021 16:52:57 +0100 Message-Id: <20210604155312.15902-85-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana now that is_a64() is just always false when !TARGET_AARCH64, we can just use that instead of introducing a new ifdef. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-common.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu-common.c b/target/arm/cpu-common.c index b7a199a8d6..585223350f 100644 --- a/target/arm/cpu-common.c +++ b/target/arm/cpu-common.c @@ -305,9 +305,13 @@ uint64_t arm_sctlr(CPUARMState *env, int el) { /* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */ if (el =3D=3D 0) { - ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, 0); - el =3D (mmu_idx =3D=3D ARMMMUIdx_E20_0 || mmu_idx =3D=3D ARMMMUIdx= _SE20_0) - ? 2 : 1; + if (is_a64(env)) { + ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, 0); + el =3D (mmu_idx =3D=3D ARMMMUIdx_E20_0 || mmu_idx =3D=3D ARMMM= UIdx_SE20_0) + ? 2 : 1; + } else { + el =3D 1; + } } return env->cp15.sctlr_el[el]; } --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622825851; cv=none; d=zohomail.com; s=zohoarc; b=M0T0tuHyFSqnY3xi6LcHJSMrBSsgXSfm+E2UVjM9nSoSKQl0ReDEpImnfXtk7ySu1Pt0SO2x17MAuZ9UbSbkw4HVrgBgEL4An891JYOD/8MyazoNtka/DBornjU5/iWB+ygFpDFrkHSnFuaYQ0H1HnoGPs6JuSiT15LKNt0xy3E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622825851; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Wv3S6+DE4Tp2NGr/S13GqQas1/V9v12ce15H5pOTlFY=; b=Xj2plc+utvjrE11nb/sQtgS8fv6Rav9IlvsLZeQnZYPD98Pj9veNBtHXzpPao/mO6QFUF2snNAuiHrKwDymRpWuxNLeMteE5BPu5HYIbjif3RpymXYAwQRw9DY+Lw7djTCSlQ2kEX8TleJpsV5TQbaH+SU/OJWfOdljcZAUj77g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622825851039899.7502028105854; Fri, 4 Jun 2021 09:57:31 -0700 (PDT) Received: from localhost ([::1]:56260 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpD8T-00056w-Mz for importer@patchew.org; Fri, 04 Jun 2021 12:57:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51636) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCRA-0002aC-T8 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:44 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:44806) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCR6-0003mz-J5 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:44 -0400 Received: by mail-wm1-x331.google.com with SMTP id p13-20020a05600c358db029019f44afc845so5906107wmq.3 for ; Fri, 04 Jun 2021 09:12:40 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id l3sm6080884wmh.2.2021.06.04.09.12.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:12:37 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 3A81520005; Fri, 4 Jun 2021 16:53:23 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Wv3S6+DE4Tp2NGr/S13GqQas1/V9v12ce15H5pOTlFY=; b=B/hSGWi9lillA/dNDJyqNvauLgWPWxmFpDVfLdsD/YNrpDExP9k05FNJKcwJIqY3tX IlvHss/Ajn4aa8YHtpW46Upg3JElxoHulAaE6nKDRm5ECNQ0W4+vrsVt+bZHfFwbqCbI TBalPithNU9DZOJoCWBF3IyOXH4Uinrn6oNhmukyJ/vfLmjluDGX1yIxVrjqxiMOo8ib PC521YYCdMKNVeG6gRWGlNz178HAWEnOiu/SS547jC4QLd6cNm2mZZ9COmyuhrCU/PkY WZF8dwSu+Jb6n6/CE+I61oN6K9y0BYetVaRspFJJZbxeFfjU6nWjU+vMrMfEjamEVpfu rGzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Wv3S6+DE4Tp2NGr/S13GqQas1/V9v12ce15H5pOTlFY=; b=Kax4g7Pog4e+UHdoPXqy2wECTPTMnveL0KBf6nk7FvaQiBSYoVgFf2z+1s7KrpAvmw lwwn0kr+SCes/pt0wixs8IyDvuavK3fJd+Iczal1fCyR7QJylnZgyBQES/k1poW6Be/0 DtB2/qR6lDl+0RqiXnw8gmnnrL6Gr1VC4nS8/OHqYMCHCxlOjsaJiIiVz7DwzJ68wr6j au224V4wHX2WvpgvHIecyXEqSOWBSuK91btgDQ8ImOh4D5NUgjSFz6TWAEBx5l5QSfHe KuoVHKcWIpJnmvQnjVejkCHS4+gHk3dhjQuIC4Dk+7giaj7vjCgy6drFUhieDpo6gNl8 rbPg== X-Gm-Message-State: AOAM5336kP+4QsBsAf583JVB1Sec0fqxxsQY5L5g2RqSgJEDCGgrv8vZ ddaFRx3j72QWBo9yUj1SY5AS3Q== X-Google-Smtp-Source: ABdhPJwDO58kTmZYR3Cpugi9Y0f4U8aWtBCX8Bfmk9r82UEFR3O0lKG5DW+Wodf3jCCroxqiaolBAA== X-Received: by 2002:a1c:146:: with SMTP id 67mr4482278wmb.61.1622823158264; Fri, 04 Jun 2021 09:12:38 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 85/99] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication Date: Fri, 4 Jun 2021 16:52:58 +0100 Message-Id: <20210604155312.15902-86-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana Pointer Authentication is an AARCH64-only ARMv8.3 optional extension, whose cpu properties can be separated out in its own module. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 3 -- target/arm/tcg/cpu-pauth.h | 34 ++++++++++++++++++++ target/arm/cpu.c | 1 + target/arm/cpu64.c | 35 ++------------------- target/arm/tcg/cpu-pauth.c | 63 ++++++++++++++++++++++++++++++++++++++ target/arm/tcg/meson.build | 1 + 6 files changed, 101 insertions(+), 36 deletions(-) create mode 100644 target/arm/tcg/cpu-pauth.h create mode 100644 target/arm/tcg/cpu-pauth.c diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e9bfb6f575..02e0fe5dbd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -216,13 +216,10 @@ typedef struct ARMPredicateReg { uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); } ARMPredicateReg; =20 -void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); /* In AArch32 mode, PAC keys do not exist at all. */ typedef struct ARMPACKey { uint64_t lo, hi; } ARMPACKey; -#else -static inline void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { } =20 #endif /* TARGET_AARCH64 */ =20 diff --git a/target/arm/tcg/cpu-pauth.h b/target/arm/tcg/cpu-pauth.h new file mode 100644 index 0000000000..af127876fe --- /dev/null +++ b/target/arm/tcg/cpu-pauth.h @@ -0,0 +1,34 @@ +/* + * QEMU AArch64 Pointer Authentication Extensions + * + * Copyright (c) 2013 Linaro Ltd + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#ifndef CPU_PAUTH_H +#define CPU_PAUTH_H + +/* ARMv8.3 pauth is an AARCH64 option, only include this for TARGET_AARCH6= 4 */ + +#include "cpu.h" + +/* called by arm_cpu_finalize_features in realizefn */ +void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); + +/* add the CPU Pointer Authentication properties */ +void cpu_pauth_add_props(Object *obj); + +#endif /* CPU_PAUTH_H */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0e41854b92..5359331bff 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -33,6 +33,7 @@ #ifdef CONFIG_TCG #include "tcg/tcg-cpu.h" #endif /* CONFIG_TCG */ +#include "tcg/cpu-pauth.h" #include "cpu32.h" #include "exec/exec-all.h" #include "hw/qdev-properties.h" diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 67b35feb17..fefb6954fc 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -24,6 +24,7 @@ #include "cpu.h" #include "cpu32.h" #include "cpu-sve.h" +#include "tcg/cpu-pauth.h" #include "qemu/module.h" #include "sysemu/tcg.h" #include "sysemu/kvm.h" @@ -246,36 +247,6 @@ static void aarch64_a72_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } =20 -void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) -{ - int arch_val =3D 0, impdef_val =3D 0; - uint64_t t; - - /* TODO: Handle HaveEnhancedPAC, HaveEnhancedPAC2, HaveFPAC. */ - if (cpu->prop_pauth) { - if (cpu->prop_pauth_impdef) { - impdef_val =3D 1; - } else { - arch_val =3D 1; - } - } else if (cpu->prop_pauth_impdef) { - error_setg(errp, "cannot enable pauth-impdef without pauth"); - error_append_hint(errp, "Add pauth=3Don to the CPU property list.\= n"); - } - - t =3D cpu->isar.id_aa64isar1; - t =3D FIELD_DP64(t, ID_AA64ISAR1, APA, arch_val); - t =3D FIELD_DP64(t, ID_AA64ISAR1, GPA, arch_val); - t =3D FIELD_DP64(t, ID_AA64ISAR1, API, impdef_val); - t =3D FIELD_DP64(t, ID_AA64ISAR1, GPI, impdef_val); - cpu->isar.id_aa64isar1 =3D t; -} - -static Property arm_cpu_pauth_property =3D - DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true); -static Property arm_cpu_pauth_impdef_property =3D - DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); - /* -cpu max: if KVM is enabled, like -cpu host (best possible with this ho= st); * otherwise, a CPU with as many features enabled as our emulation support= s. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; @@ -447,9 +418,7 @@ static void aarch64_max_initfn(Object *obj) cpu->dcz_blocksize =3D 7; /* 512 bytes */ #endif =20 - /* Default to PAUTH on, with the architected algorithm. */ - qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); - qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_proper= ty); + cpu_pauth_add_props(obj); } =20 cpu_sve_add_props(obj); diff --git a/target/arm/tcg/cpu-pauth.c b/target/arm/tcg/cpu-pauth.c new file mode 100644 index 0000000000..f821087b14 --- /dev/null +++ b/target/arm/tcg/cpu-pauth.c @@ -0,0 +1,63 @@ +/* + * QEMU AArch64 Pointer Authentication Extensions + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "cpu.h" +#include "sysemu/tcg.h" +#include "tcg/cpu-pauth.h" +#include "hw/qdev-properties.h" + +void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) +{ + int arch_val =3D 0, impdef_val =3D 0; + uint64_t t; + + /* TODO: Handle HaveEnhancedPAC, HaveEnhancedPAC2, HaveFPAC. */ + if (cpu->prop_pauth) { + if (cpu->prop_pauth_impdef) { + impdef_val =3D 1; + } else { + arch_val =3D 1; + } + } else if (cpu->prop_pauth_impdef) { + error_setg(errp, "cannot enable pauth-impdef without pauth"); + error_append_hint(errp, "Add pauth=3Don to the CPU property list.\= n"); + } + + t =3D cpu->isar.id_aa64isar1; + t =3D FIELD_DP64(t, ID_AA64ISAR1, APA, arch_val); + t =3D FIELD_DP64(t, ID_AA64ISAR1, GPA, arch_val); + t =3D FIELD_DP64(t, ID_AA64ISAR1, API, impdef_val); + t =3D FIELD_DP64(t, ID_AA64ISAR1, GPI, impdef_val); + cpu->isar.id_aa64isar1 =3D t; +} + +static Property arm_cpu_pauth_property =3D + DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true); +static Property arm_cpu_pauth_impdef_property =3D + DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false); + +void cpu_pauth_add_props(Object *obj) +{ + /* Default to PAUTH on, with the architected algorithm. */ + qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property); + qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property); +} diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index c289771e97..646bb5eb25 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -39,6 +39,7 @@ arm_ss.add(when: 'CONFIG_TCG', if_true: files( )) =20 arm_ss.add(when: ['TARGET_AARCH64','CONFIG_TCG'], if_true: files( + 'cpu-pauth.c', 'translate-a64.c', 'translate-sve.c', 'helper-a64.c', --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622823525; cv=none; d=zohomail.com; s=zohoarc; b=ErGR2YAPxV641k11KhjTFfpxpoT133ifEywV27hjeehH9/XT8gQbINUIFd5QmgRq/phQ21CL+Gvzdby9gK/3DO/4nrJgmt1xAMvDKizkRutkRJbBJAU/syTjZeukXxQAf1q1nZxPdRCJOFAMcI0+MxIQJblRLsZE5e1O3335dc8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622823525; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OSMTOGHNpqVDrWKBS5w0Ojq5CsCdFRCX6CpyFDgYeFE=; b=IX3PqB5HhwGIgc6qxTAD45ha3Lvd5gUeSoE4gEnAHXRAab7d5vE2ehLuyMTRYmgjwXb05EEymQsMj9oSjadxPzABlcUNbghah+bLN/Ji2R7ywDzCGUitSqm+n4cAQ3sIHFo82eL9hXOBvvubo2fntPU9ZeRPTIRGjCxyfvfinyM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162282352591017.002949385193915; Fri, 4 Jun 2021 09:18:45 -0700 (PDT) Received: from localhost ([::1]:36222 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCWy-0006Xu-Qy for importer@patchew.org; Fri, 04 Jun 2021 12:18:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44772) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8i-0003N3-Cc for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:40 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:39548) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8f-0000CU-T8 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:40 -0400 Received: by mail-wr1-x430.google.com with SMTP id l2so9813729wrw.6 for ; Fri, 04 Jun 2021 08:53:37 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id x10sm7152427wrt.65.2021.06.04.08.53.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:31 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 5572F20006; Fri, 4 Jun 2021 16:53:23 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OSMTOGHNpqVDrWKBS5w0Ojq5CsCdFRCX6CpyFDgYeFE=; b=q96mASnmKRNkqqhVOYy6ncNg91A9TgllizfE3UQXVyrVQTEaj59noi+dbN5AEB+xiK /vLyjGF1Ca6+MWWN8Zw3rq2r6y2/DDgcmaJCyaJcHo6bDP9IRzP74GY883jjJMDsFkD6 lbrANKs83N+VL6uOjwRHtNmyH8+W65mYrC5/zsET5nqKm9Z6ue50xz8nMrvEe8kVr0R9 eSf7ib1cCBsHKLgH9aBt/TQq/byC9dZsXgs5KSnXaASbI2MAsq8w0PZAn3ejFOTwjIKT cW6laUC1Brf5x6i49QKPHs8Ld4NxngS1p+4L1MMhH78l0RSrORs1YeFksfmp35tUFGIW n1uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OSMTOGHNpqVDrWKBS5w0Ojq5CsCdFRCX6CpyFDgYeFE=; b=bVxSKEzkjxNPMVKYoLdolsrI0ouUWJZx4o/riAOtppvjPL7NowraaGGyEg5rDVFe9v gk/+LiwI4Y8DHJ9OatKB+X9OK3nuflv7K0MESBXbIMe+s91b2lpKGo+XbCGzzQpELDba vQICLxfFvl5spUq01qkE+xRLoi3ILRoVfBP1HVx1jrvXZj/RmjXiItVRy/PfTaM6OpKO FbogMKDIYOLgWazIx+CING9zLBV92wYjuKKgccgcW80gD4iuMy3tLXsOpb76tVkUW+S+ CXqWlAvw/GxE2fn4EC+OYjbE1JkcdxKt5GSdNy9DLAt0VE6z6cTo1Ru1xEY/2+MtZkuF 0zEQ== X-Gm-Message-State: AOAM5319Ok9EuqbjA4f3yhBBE05DDIZGAwbPbsTKGnZjYrUF34kBfbKO 2IziLB8GGwJiPE2P8Nl9WYp2ew== X-Google-Smtp-Source: ABdhPJwE1gdhJQDlppCfA0gwvjff3MrrRQaDYGxVmJShahLLeJIZdrZqNni2pljsw6NjIRIWrxbiLw== X-Received: by 2002:a5d:6546:: with SMTP id z6mr4683184wrv.100.1622822016391; Fri, 04 Jun 2021 08:53:36 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 86/99] target/arm: cpu-pauth: change arm_cpu_pauth_finalize name and sig Date: Fri, 4 Jun 2021 16:52:59 +0100 Message-Id: <20210604155312.15902-87-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana make arm_cpu_pauth_finalize return a bool, and make the name canonical for the module (cpu_pauth_finalize). Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/cpu-pauth.h | 2 +- target/arm/cpu.c | 3 +-- target/arm/tcg/cpu-pauth.c | 5 ++++- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/cpu-pauth.h b/target/arm/tcg/cpu-pauth.h index af127876fe..a0ef74dc77 100644 --- a/target/arm/tcg/cpu-pauth.h +++ b/target/arm/tcg/cpu-pauth.h @@ -26,7 +26,7 @@ #include "cpu.h" =20 /* called by arm_cpu_finalize_features in realizefn */ -void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp); +bool cpu_pauth_finalize(ARMCPU *cpu, Error **errp); =20 /* add the CPU Pointer Authentication properties */ void cpu_pauth_add_props(Object *obj); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5359331bff..8709c11784 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -837,8 +837,7 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **err= p) * is in use, so the user will not be able to set them. */ if (tcg_enabled()) { - arm_cpu_pauth_finalize(cpu, &local_err); - if (local_err !=3D NULL) { + if (!cpu_pauth_finalize(cpu, &local_err)) { error_propagate(errp, local_err); return; } diff --git a/target/arm/tcg/cpu-pauth.c b/target/arm/tcg/cpu-pauth.c index f821087b14..4f087923ac 100644 --- a/target/arm/tcg/cpu-pauth.c +++ b/target/arm/tcg/cpu-pauth.c @@ -25,8 +25,9 @@ #include "tcg/cpu-pauth.h" #include "hw/qdev-properties.h" =20 -void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) +bool cpu_pauth_finalize(ARMCPU *cpu, Error **errp) { + bool result =3D true; int arch_val =3D 0, impdef_val =3D 0; uint64_t t; =20 @@ -40,6 +41,7 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) } else if (cpu->prop_pauth_impdef) { error_setg(errp, "cannot enable pauth-impdef without pauth"); error_append_hint(errp, "Add pauth=3Don to the CPU property list.\= n"); + result =3D false; } =20 t =3D cpu->isar.id_aa64isar1; @@ -48,6 +50,7 @@ void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp) t =3D FIELD_DP64(t, ID_AA64ISAR1, API, impdef_val); t =3D FIELD_DP64(t, ID_AA64ISAR1, GPI, impdef_val); cpu->isar.id_aa64isar1 =3D t; + return result; } =20 static Property arm_cpu_pauth_property =3D --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622822616; cv=none; d=zohomail.com; s=zohoarc; b=WB+qJYMUjKwtvI2Ns9rPmF7dUrAlD5m7w0BaKEF3A2JIVY2Hp9Pzx18nllTeZmp9TG25oWQmWAVMjIE/zILqUtpNzZ++0Ofs822/rd5MaTtpZftWduS3Z5obx5/xwVrnzLg0YD30nMcAXSMhu7J8GHIWOZfLKavK2F+6r4vpD8U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622822616; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kkP+MYbBmAzVDrfIZPpeRjBWZ6tsRXqrVrjsv5uYDeI=; b=EZDmvqjNwQsz8GY7lYOYLLDeLqun3QukHKeN11YUxjP9Q/c2Ayz5hZStR7WzM7CTB+ww04lSHYXS4o5Ztt1MQOo69Bz30LC4WxCFTRIG1W2OwtlKKd19NJDLIJcsRrOeLTWwITUHqj7kOtYhx/vbdOXusS641xsieuKhLwWHiVY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622822616365943.5305627396905; Fri, 4 Jun 2021 09:03:36 -0700 (PDT) Received: from localhost ([::1]:46440 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCIJ-0006w0-0I for importer@patchew.org; Fri, 04 Jun 2021 12:03:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44678) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8f-0003D3-Sh for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:37 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:37759) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8c-00009K-Vp for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:37 -0400 Received: by mail-wm1-x32d.google.com with SMTP id t16-20020a05600c1990b02901a0d45ff03aso4661238wmq.2 for ; Fri, 04 Jun 2021 08:53:34 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id o6sm8006091wre.73.2021.06.04.08.53.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:31 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 7163C20007; Fri, 4 Jun 2021 16:53:23 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kkP+MYbBmAzVDrfIZPpeRjBWZ6tsRXqrVrjsv5uYDeI=; b=iJNOkhUHHnJyguCif0Hbohyg8LrW1hxcTTqcCOYVAIh2SPCQ81ypnOkda20WuHQR1g Jwxh1g28Rju1oeE14+KBJM75CsPXJps+C+NWsvbQUlMj/MwWV+AnoJAAGOqRacFpVceG 1sYynQ4pqis/e+ruhvMDNGvGAtV13jDWPNo0WyWGQDk2QE04J6/BOW7jIHxAuGVF8/l2 OiNPCPYRRb7lzv31CA4GZbdH6DEvG9+0p2hbFd2g1lpdajOnZeAindapNLdi8+519EJW yTX3N3JtHBga90IjEHm41VKtGvO0w7XM/0Cbm2EUINX4bFEHJFlEl/acwbsQ0K75wW9K dC1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kkP+MYbBmAzVDrfIZPpeRjBWZ6tsRXqrVrjsv5uYDeI=; b=q73l3Ux+Bkzxi9J1xgtN0yV0d0CMNBugX+ModgzmY9ADMTKjQJUKUtcg5Ig+UFlwxs unK+7bCAlic4MFR2Bs50EbVUCWkAJkeEZYUQx9x5TJ+K5YR2U3yz0/G1f3cXzIhBJ+lt z9+Y1HrP8Ex5/K4/b6Hv7hYkSvMQTau3q5TF+ozKvtp9tbWcfhK1fGD6X0jSkmngAtnF XiKb0ZlUcTrr7kPHkCOtY+OcHF0EtHQ4nH6tymA9fRZJGZxuGMYcRZ0iFx6D78x1zLGH necDl0RIW/KimFzXb3SkTdc9AH8Qj8CENE11JAfbSfC/E2ZVWxvZE7T3mw0aS81mK7kq dChA== X-Gm-Message-State: AOAM530ByqM1FBjRJ8t1u/DnI5cMD2RVseIACXSnMZWVPXDSutZrDz62 YQWmFPX7/0dvTymbDSP772BEWnfStjOW+Q== X-Google-Smtp-Source: ABdhPJzrkVhvMvpuxMYki5YjoAI1fgbQOON/JX/4S5EsJp5bNZLSgMwpjpCmi3Khvd9+I4RaqmQdDA== X-Received: by 2002:a1c:98d0:: with SMTP id a199mr4387062wme.22.1622822013426; Fri, 04 Jun 2021 08:53:33 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 87/99] target/arm: move arm_cpu_finalize_features into cpu64 Date: Fri, 4 Jun 2021 16:53:00 +0100 Message-Id: <20210604155312.15902-88-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana all the features in arm_cpu_finalize_features are actually TARGET_AARCH64-only now, since KVM is now only supported on 64bit. Therefore move the function to cpu64. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu.c | 36 ++---------------------------------- target/arm/cpu64.c | 34 ++++++++++++++++++++++++++++++++++ target/arm/monitor.c | 4 ++++ 3 files changed, 40 insertions(+), 34 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8709c11784..0adbf36347 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -820,40 +820,6 @@ static void arm_cpu_finalizefn(Object *obj) #endif } =20 -void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) -{ - Error *local_err =3D NULL; - -#ifdef TARGET_AARCH64 - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - if (!cpu_sve_finalize_features(cpu, &local_err)) { - error_propagate(errp, local_err); - return; - } - - /* - * KVM does not support modifications to this feature. - * We have not registered the cpu properties when KVM - * is in use, so the user will not be able to set them. - */ - if (tcg_enabled()) { - if (!cpu_pauth_finalize(cpu, &local_err)) { - error_propagate(errp, local_err); - return; - } - } - } -#endif /* TARGET_AARCH64 */ - - if (kvm_enabled()) { - kvm_arm_steal_time_finalize(cpu, &local_err); - if (local_err !=3D NULL) { - error_propagate(errp, local_err); - return; - } - } -} - static void arm_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); @@ -876,6 +842,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error *= *errp) return; } =20 +#ifdef TARGET_AARCH64 arm_cpu_finalize_features(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); @@ -892,6 +859,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error *= *errp) "AArch64 CPUs must have both VFP and Neon or neither"); return; } +#endif /* TARGET_AARCH64 */ =20 if (!cpu->has_vfp) { uint64_t t; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index fefb6954fc..c762f3f07a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -469,6 +469,40 @@ static gchar *aarch64_gdb_arch_name(CPUState *cs) return g_strdup("aarch64"); } =20 +void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) +{ + Error *local_err =3D NULL; + +#ifdef TARGET_AARCH64 + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + if (!cpu_sve_finalize_features(cpu, &local_err)) { + error_propagate(errp, local_err); + return; + } + + /* + * KVM does not support modifications to this feature. + * We have not registered the cpu properties when KVM + * is in use, so the user will not be able to set them. + */ + if (tcg_enabled()) { + if (!cpu_pauth_finalize(cpu, &local_err)) { + error_propagate(errp, local_err); + return; + } + } + } +#endif /* TARGET_AARCH64 */ + + if (kvm_enabled()) { + kvm_arm_steal_time_finalize(cpu, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + } +} + static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) { ARMCPU *cpu =3D ARM_CPU(cs); diff --git a/target/arm/monitor.c b/target/arm/monitor.c index 0c72bf7c31..95c1e72cd1 100644 --- a/target/arm/monitor.c +++ b/target/arm/monitor.c @@ -184,9 +184,11 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(C= puModelExpansionType type, if (!err) { visit_check_struct(visitor, &err); } +#ifdef TARGET_AARCH64 if (!err) { arm_cpu_finalize_features(ARM_CPU(obj), &err); } +#endif /* TARGET_AARCH64 */ visit_end_struct(visitor, NULL); visit_free(visitor); if (err) { @@ -195,7 +197,9 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(Cp= uModelExpansionType type, return NULL; } } else { +#ifdef TARGET_AARCH64 arm_cpu_finalize_features(ARM_CPU(obj), &error_abort); +#endif /* TARGET_AARCH64 */ } =20 expansion_info =3D g_new0(CpuModelExpansionInfo, 1); --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622824377; cv=none; d=zohomail.com; s=zohoarc; b=DL7QkmImnpvCOPRO2XtaLYuKnSn4usYg4eX2b0mmO62bzvvWgZX7pOIwVoWFRTOSxGi6s3NxNshfFtso5G3PHPJNzExHxyZ8NEaLE+VESlcXrmvRUgyXg+MTwlIAdHRK3+KO710fnkSOwFPhSPDVMbY2EEUP+PAvmT0WxP+8bVg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622824377; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KFXdupVdeAnSfunCtZQNKO6+//sRzqaD3i4QyYWExWo=; b=iDbRcRVD66EoIrmxxdiFmLHbNiFrQdTqOfipZWzWkNFYclO80/t0NBGW5d3XgtY9YTV93kKPWmmEknFuJoNQadmkGYWsTzjAGZCREhwzI4KRujAoJhuT97Z0970ztEjCUSrjkSWNQItbKWbs3OfG564MpgyVxcOb3Bn6+YFfb3s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 162282437737561.79263381503381; Fri, 4 Jun 2021 09:32:57 -0700 (PDT) Received: from localhost ([::1]:57726 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCkg-0006qu-3L for importer@patchew.org; Fri, 04 Jun 2021 12:32:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48212) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCHb-0007iu-BJ for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:02:51 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:42551) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHS-0005iV-Ku for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:02:51 -0400 Received: by mail-wr1-x435.google.com with SMTP id c5so9793484wrq.9 for ; Fri, 04 Jun 2021 09:02:42 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id s1sm7503481wre.67.2021.06.04.09.02.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:37 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 9026A20008; Fri, 4 Jun 2021 16:53:23 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KFXdupVdeAnSfunCtZQNKO6+//sRzqaD3i4QyYWExWo=; b=EWIBS1imBQS8e8FjiILHdMdtM6O+ZJB0YUmjyTfJo0Hv8D+MCpAlQq2dEaAfVqm6Zk LFFXiMQl0sKZuuzDJuxbcdBgN855xptbvbSBkuZIL+Mrt9s9WxNOyW7zWeJhtaq3jNqm 740aueAjyc6X+YahPUCVSK+WZBUbhLKDIvZValekPtSj1Wysyk12EbqpTt82Q08bk0+Y 5iwczK7C8Vy6UunvvbFBSflAo8KdqKdljlIRhOFfsPCVypiQ5ZnLlqhGJUyvsty2rkmX LTv896m/KYscSfvpwWzEtVtSGecCqwJ3lBHMEg2mKOl+6LgGJWT/7s1EprlU/BFWbLNc ooPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KFXdupVdeAnSfunCtZQNKO6+//sRzqaD3i4QyYWExWo=; b=oqdBWEVQfmd62xA98lvsJFjmu2obB0pNAjE3JIY+EU5lLYxE08t0ZI6Sk+7BUJs9xo hJ8KdX0aWLuMJKTO850Eqd7sWmC7uX3Rf42bESTO1Rou4NwFDWaLcTh3JnvaE8rc28qN H/qhvg1ijCNt1jbR2AdFWmvqrudCCzFLxQFZtQXug6u9FjkW9sAJ3Ugx7XtE7aSY6Cn4 PvRlPLB4L/BiUXJFiavoZlvxF+7/SGELp7OaNCcLQffhbgbL2dIo/ZhxPewzu0oV2cNa kh1DkdbcUsm92Tpfu4k6MnLRRefgurkd++uQn+TmnEU35l7mZfQp1/KPuPXLbo9978ys kKhA== X-Gm-Message-State: AOAM533JYSn+d9tcdY2g6CZ3aIy9Fp0Jhrtvhfmj1vB+dO2aIP8Vmirj k8JDuAzsteeTe3nlcoY6yC1hEw== X-Google-Smtp-Source: ABdhPJwsNFfJo+dczdJRUqWFv0CIx/BojoQ9uI6GUTdVlEAcgoBH37j9y+y06x9NEMghHfPYjyjx2A== X-Received: by 2002:a5d:64a5:: with SMTP id m5mr4566198wrp.182.1622822561382; Fri, 04 Jun 2021 09:02:41 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 88/99] target/arm: cpu64: rename arm_cpu_finalize_features Date: Fri, 4 Jun 2021 16:53:01 +0100 Message-Id: <20210604155312.15902-89-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana also remove the now useless ifdef TARGET_AARCH64 from the function Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-sve.h | 2 +- target/arm/cpu.h | 2 +- target/arm/tcg/cpu-pauth.h | 2 +- target/arm/cpu.c | 2 +- target/arm/cpu64.c | 4 +--- target/arm/monitor.c | 4 ++-- 6 files changed, 7 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu-sve.h b/target/arm/cpu-sve.h index c83508ea0a..85078550bb 100644 --- a/target/arm/cpu-sve.h +++ b/target/arm/cpu-sve.h @@ -25,7 +25,7 @@ =20 #include "cpu.h" =20 -/* called by arm_cpu_finalize_features in realizefn */ +/* called by aarch64_cpu_finalize_features in realizefn */ bool cpu_sve_finalize_features(ARMCPU *cpu, Error **errp); =20 /* add the CPU SVE properties */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 02e0fe5dbd..847d3628e9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2127,7 +2127,7 @@ static inline int arm_feature(CPUARMState *env, int f= eature) return (env->features & (1ULL << feature)) !=3D 0; } =20 -void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp); +void aarch64_cpu_finalize_features(ARMCPU *cpu, Error **errp); =20 #if !defined(CONFIG_USER_ONLY) /* Return true if exception levels below EL3 are in secure state, diff --git a/target/arm/tcg/cpu-pauth.h b/target/arm/tcg/cpu-pauth.h index a0ef74dc77..b106b9cefc 100644 --- a/target/arm/tcg/cpu-pauth.h +++ b/target/arm/tcg/cpu-pauth.h @@ -25,7 +25,7 @@ =20 #include "cpu.h" =20 -/* called by arm_cpu_finalize_features in realizefn */ +/* called by aarch64_cpu_finalize_features in realizefn */ bool cpu_pauth_finalize(ARMCPU *cpu, Error **errp); =20 /* add the CPU Pointer Authentication properties */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0adbf36347..fb04d768b5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -843,7 +843,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error *= *errp) } =20 #ifdef TARGET_AARCH64 - arm_cpu_finalize_features(cpu, &local_err); + aarch64_cpu_finalize_features(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); return; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c762f3f07a..3058e2c273 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -469,11 +469,10 @@ static gchar *aarch64_gdb_arch_name(CPUState *cs) return g_strdup("aarch64"); } =20 -void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp) +void aarch64_cpu_finalize_features(ARMCPU *cpu, Error **errp) { Error *local_err =3D NULL; =20 -#ifdef TARGET_AARCH64 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { if (!cpu_sve_finalize_features(cpu, &local_err)) { error_propagate(errp, local_err); @@ -492,7 +491,6 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **err= p) } } } -#endif /* TARGET_AARCH64 */ =20 if (kvm_enabled()) { kvm_arm_steal_time_finalize(cpu, &local_err); diff --git a/target/arm/monitor.c b/target/arm/monitor.c index 95c1e72cd1..8a31c4dd04 100644 --- a/target/arm/monitor.c +++ b/target/arm/monitor.c @@ -186,7 +186,7 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(Cp= uModelExpansionType type, } #ifdef TARGET_AARCH64 if (!err) { - arm_cpu_finalize_features(ARM_CPU(obj), &err); + aarch64_cpu_finalize_features(ARM_CPU(obj), &err); } #endif /* TARGET_AARCH64 */ visit_end_struct(visitor, NULL); @@ -198,7 +198,7 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(Cp= uModelExpansionType type, } } else { #ifdef TARGET_AARCH64 - arm_cpu_finalize_features(ARM_CPU(obj), &error_abort); + aarch64_cpu_finalize_features(ARM_CPU(obj), &error_abort); #endif /* TARGET_AARCH64 */ } =20 --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622826816; cv=none; d=zohomail.com; s=zohoarc; b=RCAd1xxq26Fb0hePkM7vJ3WBHMPEt0nBfD5M8P6at0p+FcZqkdioq0TxrPGVxS+ztyyruxQ2z81UeZlxtvBULujudceMiM5Lgey9EXxpOxWd3V9OHHq924I6JILNGJfJm7GKum+xW0VSv7XMJzkiWN5KSO/G9nhX1THnUXyhh4o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622826816; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QruW2yuHWroD/WpqnI/5LDTpQWpXeY+42xPYVRJQ+80=; b=Y0uzTwUsyQkIrogSpwwQGYjJlD1tpMTYr7eBUqvBO9I5dLbTSPrgSwwV0BaASob3svG5rvZnje8+EGoH0bbe5HodN+bmD8xdS2Xp8EWaNNebqF5ADQekhzYd8f4EJn0hj3/A8sRWIyWeM1tAj+hDYpyyvrCdL9V1wq26Tt6Yzk8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622826816365586.1854241432414; Fri, 4 Jun 2021 10:13:36 -0700 (PDT) Received: from localhost ([::1]:53628 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDO2-0008MX-Vl for importer@patchew.org; Fri, 04 Jun 2021 13:13:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33624) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCkk-0008QU-8I for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:32:58 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:56029) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCkb-0002Ah-Gw for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:32:57 -0400 Received: by mail-wm1-x330.google.com with SMTP id g204so5720154wmf.5 for ; Fri, 04 Jun 2021 09:32:48 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id u14sm8911091wmc.41.2021.06.04.09.32.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:43 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A886D2000C; Fri, 4 Jun 2021 16:53:23 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QruW2yuHWroD/WpqnI/5LDTpQWpXeY+42xPYVRJQ+80=; b=vFqXM8X5vIPtKdmqPez8EQFPlIFyhbZeU71gi8KwCYJ0+yz7ha44qVqvSTjQLbN4zu mWgTia7lJReCWrKA5y49AcqoleL1c/BNLvFtkn3OUGlI6wWFqQJODMdWE+RatWzIzMMk CnjXllbRbQsrKZaBJet3ytN/2eMXXVD8u1tIZY9dArpq4BdywOIgASYFM9y4rLVMtHBk w3mfPZVknWqYBR05JnN+bMvT4xEeFK1rMqmF5/RSCz/wFmQ9RCQlDiFrQwCrKA5dP/2Z zIvR1LmIu29s5iRP6popwNplpL/Oc6f+JkOIhZR1FNbutFZsfFUZsmAWVPpEsRS+lb2A 0qww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QruW2yuHWroD/WpqnI/5LDTpQWpXeY+42xPYVRJQ+80=; b=OITNgVXwb8i6rD5X9AeThexlzKlkz/Lj/tZm0r9c2HYp0vT/nttR8dqbqdPO9/sS8c hY0r+Y4TLCAfVrWq56tFur1rUCPhJV8bBj6DdNsMv5vtuUv8gxllW0NBhWc2ow0Zeb4k x3X0PoYOResZhUNVS9mDkkX6ZgodO7V3fR3Mjs0DZRWGEDpkB5HFObqDahrsI0Brx6mg j9jeI0ztGc25nYqnKqIMAMEeAminZ93Wn5ZV3Nh5/JnNTmz/OTuzSQo4gaZ36jsRjs5F s5PPMtkEb0lrH7hqAdx4gQK4aKS6MaozctazybmtZfGhGnTq781FByzMvb1MBpQcXD60 9hZQ== X-Gm-Message-State: AOAM531BopWN9PTiNs3dFyVXOp83a2gACBADqEZSe3WRDTdOAa2ljwNr JJb3uCdJJX1jw8RqXxK/B/+KAg== X-Google-Smtp-Source: ABdhPJy12T0kC3vixKWYr/mUIN+evrh5xV5WaZUdZUG3S3u3GtOgATbqG3yicbqgnuzlUoUylGiDWA== X-Received: by 2002:a05:600c:47d7:: with SMTP id l23mr4611072wmo.49.1622824367987; Fri, 04 Jun 2021 09:32:47 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 89/99] target/arm: cpu64: some final cleanup on aarch64_cpu_finalize_features Date: Fri, 4 Jun 2021 16:53:02 +0100 Message-Id: <20210604155312.15902-90-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana bail out immediately if ARM_FEATURE_AARCH64 is not set, and add an else statement when checking for accelerators. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu64.c | 33 ++++++++++++++++----------------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3058e2c273..ecce8c4308 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -473,26 +473,25 @@ void aarch64_cpu_finalize_features(ARMCPU *cpu, Error= **errp) { Error *local_err =3D NULL; =20 - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - if (!cpu_sve_finalize_features(cpu, &local_err)) { + if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + return; + } + if (!cpu_sve_finalize_features(cpu, &local_err)) { + error_propagate(errp, local_err); + return; + } + + /* + * KVM does not support modifications to this feature. + * We have not registered the cpu properties when KVM + * is in use, so the user will not be able to set them. + */ + if (tcg_enabled()) { + if (!cpu_pauth_finalize(cpu, &local_err)) { error_propagate(errp, local_err); return; } - - /* - * KVM does not support modifications to this feature. - * We have not registered the cpu properties when KVM - * is in use, so the user will not be able to set them. - */ - if (tcg_enabled()) { - if (!cpu_pauth_finalize(cpu, &local_err)) { - error_propagate(errp, local_err); - return; - } - } - } - - if (kvm_enabled()) { + } else if (kvm_enabled()) { kvm_arm_steal_time_finalize(cpu, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622827419; cv=none; d=zohomail.com; s=zohoarc; b=gcOwWDwyGUgVWyLYZajks1VQFxhkjaWLoskBha5ZvTKLTcktcWR9L/TrXXIg8QH9fREy1uxabiTBB1mPPB5P0ouuk1oX0D/6+J++/wReunqyBX05fA/IJRu2FEM55A6eUsQa8G3O8FjzHGjpeQTlJKnY5CYDueamNzxRhu8u/BA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622827419; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DAHUANG/vqqFP+x4dLlbQOPag/TtMMrlsBRBzfaoKto=; b=J8hN41X+Ql2nN73+JFSCCD3zkQf7sh7wpTSF07RDglrOogRr05fPLF4S+JMFtwTPAV2OoIoyFyj1gXohxzd6kRvY9MTI2a4SJs/OMBaSvVsAXlOFzz3q/lNRi14ZC4IetIDtWy4juq5O10bZGtZ0V+qRaMGxJL8oiH/gWcK7Tz4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622827418953127.42773892015055; Fri, 4 Jun 2021 10:23:38 -0700 (PDT) Received: from localhost ([::1]:33848 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDXj-00012z-Qc for importer@patchew.org; Fri, 04 Jun 2021 13:23:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCkx-0000OL-0x for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:11 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:41719) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCkh-0002De-VW for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:10 -0400 Received: by mail-wr1-x431.google.com with SMTP id h8so9890415wrz.8 for ; Fri, 04 Jun 2021 09:32:55 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id r7sm4615381wmq.23.2021.06.04.09.32.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:51 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id CD5EF20013; Fri, 4 Jun 2021 16:53:23 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DAHUANG/vqqFP+x4dLlbQOPag/TtMMrlsBRBzfaoKto=; b=t3Bo5nS5YYhppyuoNE30Y56mzdpN+u8Zlwcal0nsKvWNE5o1bwSgMMB2LJPsDmm3Gq exVJ7Elt3n16uUm+T3hJlMbkYq9LLbboE56GXHC5cER+3pTO4Ye/58alchXm8kvfRUW+ exTQokNHAvAMOts3Pd3zNadmaQbNWqqF3mHhgfdXQmEZLGPZZx5Jt5NKs8JcYl4FBsxm 6k38NpH5eMO69jNhEinbwioep71YWxNVK0FKrKqwwQIGWuxhpIeaWF3+d2KpDGUAeXqj ydIgQ2cicPCVQgnI/f4g91O/H6TQo6itCpEEoUi77x5YiCGjlQbg3bkF1QMpajpjz29n 8mwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DAHUANG/vqqFP+x4dLlbQOPag/TtMMrlsBRBzfaoKto=; b=EpKVUsZ2Ea51QPctQQxHh5qUYNt+LYf2ptOnSYYVkCTyrO1UgjoElpgSskYwS3plzd aYtIFHN2A9uDNjnCS6wuQxDYnFtUk6w++kpVms5wHmXmm2zUGjR6e11R899UofIckqPl LIFUfauCPxd+qbf86EoBQCfdmqLwNm7avIq2hM7/TWrqXZkdA22igqjCcxl1iUCpf3zV KG3CcvQamDEKL0pV+beFXyaxzZ6Q5OcRxHfMwQ73O4DTLdK0rp5KyntKiZL39etZoPb0 yM35at0hoRe5WQz7gyRmglncTuZLl8fX3yxJDjGkjJltIwAvtEwdTB4xZ2IgO+9n6Qlo wBuQ== X-Gm-Message-State: AOAM530En+CbNZKaI4kQmI/wQI9Duo29zyy2IPU8qIweEcOjeuxT7LgS p0kw8h58Q/aOBODTBQwDPIg2mQ== X-Google-Smtp-Source: ABdhPJzHZUT9c11GW3nKUE/fm4sYIUBtDKCdCxqVJxyU34DdZ/Wm1EcDFGaQmr4yGv2mbMOSsNaRpA== X-Received: by 2002:a5d:414e:: with SMTP id c14mr4619104wrq.81.1622824374611; Fri, 04 Jun 2021 09:32:54 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 90/99] XXX target/arm: experiment refactoring cpu "max" Date: Fri, 4 Jun 2021 16:53:03 +0100 Message-Id: <20210604155312.15902-91-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana XXX Someone who really understands which properties should be added where should review this attentively. What goes into cpu leaf class initialization? What goes into arm_post_init / accel_cpu? What goes into arm_cpu_finalize_features / aarch64_cpu_finalize_features? Should there be shift of more code into finalize_features? Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 3 + target/arm/cpu64.c | 175 ++---------------------- target/arm/kvm/kvm-cpu.c | 4 +- target/arm/tcg/tcg-cpu-models.c | 63 +-------- target/arm/tcg/tcg-cpu.c | 228 +++++++++++++++++++++++++++++++- 5 files changed, 241 insertions(+), 232 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 847d3628e9..daa3e5f8d0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1015,6 +1015,9 @@ struct ARMCPU { =20 /* Generic timer counter frequency, in Hz */ uint64_t gt_cntfrq_hz; + + /* MAX features requested via cpu=3D"max" */ + bool max_features; }; =20 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index ecce8c4308..9595587ee0 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -247,10 +247,15 @@ static void aarch64_a72_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } =20 -/* -cpu max: if KVM is enabled, like -cpu host (best possible with this ho= st); - * otherwise, a CPU with as many features enabled as our emulation support= s. - * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; - * this only needs to handle 64 bits. +/* + * -cpu max: if KVM is enabled, like -cpu host (best possible with this ho= st), + * plus some "max"-only properties, see f.e. cpu_sve_add_props_m= ax(). + * + * if TCG is enabled, a CPU with as many features enabled as our + * emulation supports. + * + * The version of '-cpu max' for qemu-system-arm is defined in + * tcg/tcg-cpu-models.c, while this version only handles 64bit. */ static void aarch64_max_initfn(Object *obj) { @@ -259,170 +264,12 @@ static void aarch64_max_initfn(Object *obj) if (kvm_enabled()) { kvm_arm_set_cpu_features_from_host(cpu); } else if (tcg_enabled()) { - uint64_t t; - uint32_t u; aarch64_a57_initfn(obj); - - /* - * Reset MIDR so the guest doesn't mistake our 'max' CPU type for = a real - * one and try to apply errata workarounds or use impdef features = we - * don't provide. - * An IMPLEMENTER field of 0 means "reserved for software use"; - * ARCHITECTURE must be 0xf indicating "v7 or later, check ID regi= sters - * to see which features are present"; - * the VARIANT, PARTNUM and REVISION fields are all implementation - * defined and we choose to define PARTNUM just in case guest - * code needs to distinguish this QEMU CPU from other software - * implementations, though this shouldn't be needed. - */ - t =3D FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); - t =3D FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); - t =3D FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); - t =3D FIELD_DP64(t, MIDR_EL1, VARIANT, 0); - t =3D FIELD_DP64(t, MIDR_EL1, REVISION, 0); - cpu->midr =3D t; - - t =3D cpu->isar.id_aa64isar0; - t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); - t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); - cpu->isar.id_aa64isar0 =3D t; - - t =3D cpu->isar.id_aa64isar1; - t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); - t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); - cpu->isar.id_aa64isar1 =3D t; - - t =3D cpu->isar.id_aa64pfr0; - t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); - cpu->isar.id_aa64pfr0 =3D t; - - t =3D cpu->isar.id_aa64pfr1; - t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); - t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); - /* - * Begin with full support for MTE. This will be downgraded to MTE= =3D0 - * during realize if the board provides no tag memory, much like - * we do for EL2 with the virtualization=3Don property. - */ - t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 2); - cpu->isar.id_aa64pfr1 =3D t; - - t =3D cpu->isar.id_aa64mmfr0; - t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits= */ - cpu->isar.id_aa64mmfr0 =3D t; - - t =3D cpu->isar.id_aa64mmfr1; - t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ - cpu->isar.id_aa64mmfr1 =3D t; - - t =3D cpu->isar.id_aa64mmfr2; - t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ - cpu->isar.id_aa64mmfr2 =3D t; - - t =3D cpu->isar.id_aa64zfr0; - t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); - cpu->isar.id_aa64zfr0 =3D t; - - /* Replicate the same data to the 32-bit id registers. */ - u =3D cpu->isar.id_isar5; - u =3D FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ - u =3D FIELD_DP32(u, ID_ISAR5, SHA1, 1); - u =3D FIELD_DP32(u, ID_ISAR5, SHA2, 1); - u =3D FIELD_DP32(u, ID_ISAR5, CRC32, 1); - u =3D FIELD_DP32(u, ID_ISAR5, RDM, 1); - u =3D FIELD_DP32(u, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D u; - - u =3D cpu->isar.id_isar6; - u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 1); - u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); - u =3D FIELD_DP32(u, ID_ISAR6, FHM, 1); - u =3D FIELD_DP32(u, ID_ISAR6, SB, 1); - u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); - u =3D FIELD_DP32(u, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D u; - - u =3D cpu->isar.id_pfr0; - u =3D FIELD_DP32(u, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D u; - - u =3D cpu->isar.id_pfr2; - u =3D FIELD_DP32(u, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D u; - - u =3D cpu->isar.id_mmfr3; - u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D u; - - u =3D cpu->isar.id_mmfr4; - u =3D FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ - u =3D FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - u =3D FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ - u =3D FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D u; - - t =3D cpu->isar.id_aa64dfr0; - t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ - cpu->isar.id_aa64dfr0 =3D t; - - u =3D cpu->isar.id_dfr0; - u =3D FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ - cpu->isar.id_dfr0 =3D u; - - u =3D cpu->isar.mvfr1; - u =3D FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ - u =3D FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D u; - -#ifdef CONFIG_USER_ONLY - /* For usermode -cpu max we can use a larger and more efficient DCZ - * blocksize since we don't have to follow what the hardware does. - */ - cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT i= cache */ - cpu->dcz_blocksize =3D 7; /* 512 bytes */ -#endif - - cpu_pauth_add_props(obj); } - cpu_sve_add_props(obj); cpu_sve_add_props_max(obj); + + cpu->max_features =3D true; } =20 static const ARMCPUInfo aarch64_cpus[] =3D { diff --git a/target/arm/kvm/kvm-cpu.c b/target/arm/kvm/kvm-cpu.c index 09aede9319..1157888f85 100644 --- a/target/arm/kvm/kvm-cpu.c +++ b/target/arm/kvm/kvm-cpu.c @@ -88,9 +88,7 @@ static void host_cpu_instance_init(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); =20 kvm_arm_set_cpu_features_from_host(cpu); - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - cpu_sve_add_props(obj); - } + cpu_sve_add_props(obj); arm_cpu_post_init(obj); } =20 diff --git a/target/arm/tcg/tcg-cpu-models.c b/target/arm/tcg/tcg-cpu-model= s.c index 975869f276..1be953ad1a 100644 --- a/target/arm/tcg/tcg-cpu-models.c +++ b/target/arm/tcg/tcg-cpu-models.c @@ -872,68 +872,7 @@ static void arm_max_initfn(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); =20 cortex_a15_initfn(obj); - - /* old-style VFP short-vector support */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); - -#ifdef CONFIG_USER_ONLY - /* - * We don't set these in system emulation mode for the moment, - * since we don't correctly set (all of) the ID registers to - * advertise them. - */ - set_feature(&cpu->env, ARM_FEATURE_V8); - { - uint32_t t; - - t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D t; - - t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D t; - - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D t; - - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; - - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D t; - - t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D t; - - t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D t; - - t =3D cpu->isar.id_pfr2; - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D t; - } -#endif /* CONFIG_USER_ONLY */ + cpu->max_features =3D true; } #endif /* !TARGET_AARCH64 */ =20 diff --git a/target/arm/tcg/tcg-cpu.c b/target/arm/tcg/tcg-cpu.c index db677bc71c..675f36be27 100644 --- a/target/arm/tcg/tcg-cpu.c +++ b/target/arm/tcg/tcg-cpu.c @@ -26,6 +26,10 @@ #include "internals.h" #include "exec/exec-all.h" =20 +#ifdef TARGET_AARCH64 +#include "tcg/cpu-pauth.h" +#endif + void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { @@ -228,16 +232,234 @@ static struct TCGCPUOps arm_tcg_ops =3D { #endif /* !CONFIG_USER_ONLY */ }; =20 -static void tcg_cpu_instance_init(CPUState *cs) +#ifdef TARGET_AARCH64 +static void tcg_cpu_max_instance_init(CPUState *cs) { + uint64_t t; + uint32_t u; + Object *obj =3D OBJECT(cs); ARMCPU *cpu =3D ARM_CPU(cs); =20 /* - * this would be the place to move TCG-specific props - * in future refactoring of cpu properties. + * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a re= al + * one and try to apply errata workarounds or use impdef features we + * don't provide. + * An IMPLEMENTER field of 0 means "reserved for software use"; + * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers + * to see which features are present"; + * the VARIANT, PARTNUM and REVISION fields are all implementation + * defined and we choose to define PARTNUM just in case guest + * code needs to distinguish this QEMU CPU from other software + * implementations, though this shouldn't be needed. + */ + t =3D FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0); + t =3D FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf); + t =3D FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q'); + t =3D FIELD_DP64(t, MIDR_EL1, VARIANT, 0); + t =3D FIELD_DP64(t, MIDR_EL1, REVISION, 0); + cpu->midr =3D t; + + t =3D cpu->isar.id_aa64isar0; + t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); + t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); + cpu->isar.id_aa64isar0 =3D t; + + t =3D cpu->isar.id_aa64isar1; + t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); + t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ + cpu->isar.id_aa64isar1 =3D t; + + t =3D cpu->isar.id_aa64pfr0; + t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); + cpu->isar.id_aa64pfr0 =3D t; + + t =3D cpu->isar.id_aa64pfr1; + t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); + t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); + /* + * Begin with full support for MTE. This will be downgraded to MTE=3D0 + * during realize if the board provides no tag memory, much like + * we do for EL2 with the virtualization=3Don property. + */ + t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 2); + cpu->isar.id_aa64pfr1 =3D t; + + t =3D cpu->isar.id_aa64mmfr0; + t =3D FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */ + cpu->isar.id_aa64mmfr0 =3D t; + + t =3D cpu->isar.id_aa64mmfr1; + t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); + t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); + t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ + cpu->isar.id_aa64mmfr1 =3D t; + + t =3D cpu->isar.id_aa64mmfr2; + t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); + t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ + cpu->isar.id_aa64mmfr2 =3D t; + + /* Replicate the same data to the 32-bit id registers. */ + u =3D cpu->isar.id_isar5; + u =3D FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ + u =3D FIELD_DP32(u, ID_ISAR5, SHA1, 1); + u =3D FIELD_DP32(u, ID_ISAR5, SHA2, 1); + u =3D FIELD_DP32(u, ID_ISAR5, CRC32, 1); + u =3D FIELD_DP32(u, ID_ISAR5, RDM, 1); + u =3D FIELD_DP32(u, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 =3D u; + + u =3D cpu->isar.id_isar6; + u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 1); + u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); + u =3D FIELD_DP32(u, ID_ISAR6, FHM, 1); + u =3D FIELD_DP32(u, ID_ISAR6, SB, 1); + u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); + cpu->isar.id_isar6 =3D u; + + u =3D cpu->isar.id_pfr0; + u =3D FIELD_DP32(u, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D u; + + u =3D cpu->isar.id_pfr2; + u =3D FIELD_DP32(u, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 =3D u; + + u =3D cpu->isar.id_mmfr3; + u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 =3D u; + + u =3D cpu->isar.id_mmfr4; + u =3D FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ + u =3D FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + u =3D FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ + u =3D FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 =3D u; + + t =3D cpu->isar.id_aa64dfr0; + t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ + cpu->isar.id_aa64dfr0 =3D t; + + u =3D cpu->isar.id_dfr0; + u =3D FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 =3D u; + + u =3D cpu->isar.mvfr1; + u =3D FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ + u =3D FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D u; + +#ifdef CONFIG_USER_ONLY + /* + * For usermode -cpu max we can use a larger and more efficient DCZ + * blocksize since we don't have to follow what the hardware does. */ + cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT icach= e */ + cpu->dcz_blocksize =3D 7; /* 512 bytes */ +#endif + cpu_pauth_add_props(obj); +} + +#else /* !TARGET_AARCH64 */ +static void tcg_cpu_max_instance_init(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + + /* old-style VFP short-vector support */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + +#ifdef CONFIG_USER_ONLY + /* + * We don't set these in system emulation mode for the moment, + * since we don't correctly set (all of) the ID registers to + * advertise them. + */ + set_feature(&cpu->env, ARM_FEATURE_V8); + { + uint32_t t; + + t =3D cpu->isar.id_isar5; + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 =3D t; + + t =3D cpu->isar.id_isar6; + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + cpu->isar.id_isar6 =3D t; + + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D t; + + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; + + t =3D cpu->isar.id_mmfr3; + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 =3D t; + + t =3D cpu->isar.id_mmfr4; + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 =3D t; + + t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D t; + + t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 =3D t; + } +#endif /* CONFIG_USER_ONLY */ +} +#endif /* TARGET_AARCH64 */ + +static void tcg_cpu_instance_init(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); =20 cpu->psci_version =3D 2; /* TCG implements PSCI 0.2 */ + if (cpu->max_features) { + tcg_cpu_max_instance_init(cs); + } } =20 static void tcg_cpu_reset(CPUState *cs) --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622827649; cv=none; d=zohomail.com; s=zohoarc; b=EUW+Q2QXkSwrRkvws6ZWZAzbwsqNkL5+OdsH81i21xSrmk6Ult0JHe3ueQCtqC5CItijwhV4M9AaE++IlT4pAX1cucFSot8IdGduoYTYY1WO1Lnz1U65V0TlHaE3Slh5ua3kaKJOrvLcGcXSuih4a8hXNIuhO+SMCXp7VRm8siw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622827649; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xfsi0lTAgR9azxMfpWXQUQ//2Zf5ZUMfbhMWxCScq+0=; b=C3/4fYw3i8W27UjtZ7hyWkAoD0r89bd+ffm6rzy8jWy++kgpcjxH7FIjXGUvoYYgvV3K75Zhdrvvcly3XXoBPUg4DUISYcik3Gnp99ObpZVBgcPLgsoFDENcadJk7bxLammzaXoFXVo7GcWS9kgWGv9vNpbGi5fXLKnUwAAcGl8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622827649856600.155080820965; Fri, 4 Jun 2021 10:27:29 -0700 (PDT) Received: from localhost ([::1]:46410 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDbU-00018Z-OS for importer@patchew.org; Fri, 04 Jun 2021 13:27:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33922) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCl0-0000a9-7n for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:14 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:53779) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCkn-0002FF-55 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:14 -0400 Received: by mail-wm1-x333.google.com with SMTP id h3so5739709wmq.3 for ; Fri, 04 Jun 2021 09:32:59 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id c12sm8239845wrr.90.2021.06.04.09.32.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:57 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id E371E20014; Fri, 4 Jun 2021 16:53:23 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xfsi0lTAgR9azxMfpWXQUQ//2Zf5ZUMfbhMWxCScq+0=; b=zH2kST0KdUrWybiGIhRu12LOpnFkhLJqwAGTA774+26P8thcPUioyiwZsnewErKmUc edQKrlvM5deNcd8bM7BD/f+5P4Jojt4APhudjziIFl26rRjhWIFzuIcKJgHV55dNpoDI So+D9c7Ktk+cc2Fjv1vhd7Qk1lPZDhIQIq3UXEGoo4OeoAlLgCJan2GYzDIiTWo051jA m09I0ynBOHGrxTiOAY5QlN3HsdaTytQLf5rZFScrYAQjzwPyd0TV9naJpzLskYkK0mWe MMwP3UNjkwjCBsiBTv8Mnd8AW9qpBzyt9GVJzfhaKB2TGgls01/ASPaGDDIo9mW74Kw1 vHFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xfsi0lTAgR9azxMfpWXQUQ//2Zf5ZUMfbhMWxCScq+0=; b=pCLLkG8Zq9xzYS0x5lw7gxaDKCpoEdNzbuXCy/jeWeZXoj8lPPEg7mlopjLKkFWzNV uEC5IkfhwxgOcNkkj0bznUHuzdX77rLTRgkShmNqt8m4hi7S2m9OAjiDkPwdjNQHM0WQ ZqVrXfDvz+fWjl/jDaWfKOHNuFe5+CCaeH6siX5z57lB75JXBWAQZPL3J0OsZpNmxLcT TFZ9d1nHxopgvpEq2P3S0GTqv+9Or9AhPTxFiisxM2+kzDL+rXLtnp97/b8JsB6Djq7A HeAC2RztM2Kwpqa7v0Hg4q5Yjtm20SCgg6fLIOzpItkKuf5HLFXDlzrBfpb+DRgulQrV vqRQ== X-Gm-Message-State: AOAM530VkbVLvLBI3ULKiCnp2GL6Jhwp0PnFmQXcrBUyw6BW/r4KlKhu yhQcKVk475SVNLg7CguFHMU8Wq2w73iHKw== X-Google-Smtp-Source: ABdhPJwowIYcAHdAwWNVsZDsvOYvhSwnzPQL19QhWnGup5ZnB/m4KJEJsn3QlcEXTfogsL4zNTL9RA== X-Received: by 2002:a05:600c:358f:: with SMTP id p15mr4621878wmq.14.1622824378322; Fri, 04 Jun 2021 09:32:58 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 91/99] target/arm: tcg: remove superfluous CONFIG_TCG check Date: Fri, 4 Jun 2021 16:53:04 +0100 Message-Id: <20210604155312.15902-92-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Richard Henderson , Claudio Fontana , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana modules under tcg/ are only built for CONFIG_TCG anyway. Signed-off-by: Claudio Fontana Reviewed-by: Richard Henderson Signed-off-by: Alex Benn=C3=A9e --- target/arm/tcg/vfp_helper.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/target/arm/tcg/vfp_helper.c b/target/arm/tcg/vfp_helper.c index 521719f327..0cc6c85270 100644 --- a/target/arm/tcg/vfp_helper.c +++ b/target/arm/tcg/vfp_helper.c @@ -21,10 +21,8 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "internals.h" -#ifdef CONFIG_TCG #include "qemu/log.h" #include "fpu/softfloat.h" -#endif =20 /* VFP support. We follow the convention used for VFP instructions: Single precision routines have a "s" suffix, double precision a @@ -40,8 +38,6 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) vfp_set_fpscr(env, val); } =20 -#ifdef CONFIG_TCG - #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p)) =20 #define VFP_BINOP(name) \ @@ -1110,5 +1106,3 @@ void HELPER(check_hcr_el2_trap)(CPUARMState *env, uin= t32_t rt, uint32_t reg) =20 raise_exception(env, EXCP_HYP_TRAP, syndrome, 2); } - -#endif --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622825445; cv=none; d=zohomail.com; s=zohoarc; b=nLopWDuc1U7ePpv+7PdwLy/PBh9yxudT40uojj7147PvQKzoF7NZsO1XUsprv9ffupXfUn2VBwb0W5lWKp0PcrOaqR127Ba3IOq3JBOE+pKbemycHisPk9FD5bQtfxx4cELE1BMOAPneE/Nq9+LcYaSXp9ruMPZSWunZvlvoVpc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622825445; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=n32frv1K2Ssc6wYL5ATggtwpjBZGV8bN4E1z0WJz+l0=; b=GScjJ3M/QNn8ZzgM+LXHlEVs9m+ZIlzrqPJDyBP25v99fufQPm2UHPNepvPJGkhY6yAEcq+kW1m3kt6ZjlCoHKm1ZDRw2YTI2UjRA1npI5LLVJquKc8eVn3iravVf8HRp+iy9uBj5Te52N7G49CFXL+DxGYLbwFaSon9A+80I8A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622825445254867.9138127903918; Fri, 4 Jun 2021 09:50:45 -0700 (PDT) Received: from localhost ([::1]:57776 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpD1v-00040O-TB for importer@patchew.org; Fri, 04 Jun 2021 12:50:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51952) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCRN-00035I-Gm for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:58 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:37780) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCRH-0003qp-RQ for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:12:57 -0400 Received: by mail-wr1-x42b.google.com with SMTP id i94so4813657wri.4 for ; Fri, 04 Jun 2021 09:12:50 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id l9sm5987730wme.21.2021.06.04.09.12.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:12:43 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 0518A20015; Fri, 4 Jun 2021 16:53:24 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=n32frv1K2Ssc6wYL5ATggtwpjBZGV8bN4E1z0WJz+l0=; b=L2rxQn4zfSGnN9D4kyT975Q2rQwLdBLyQQXCnb64NqjZ79LhZpcgH9/SYKGuECmsYA S40RNff0PxqWAao8n/RYPVXUlM8dj8SqQg1xFlLMU3241xGmbkr0Wspa8F21RZfR2dVl xHYwfb6ZO75vAg9aNuoEspL3UGd5HXu2GhQCVrbJFfFJq4u+xl0rfT332c5jqLEK/hoD 6R28wc2w2pmvxbmLiok0/2gYaQ9jjmTnIXnfwRxXw5yBy9Pm0VxaaxkuVytSAzzOCV2f 55up5gOvM/k5FLzmclpHGproCaNwXzur+bCQZ3VlavT8CCDeV1ZvJDZ5TZ5L6LJcVA1e UzOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n32frv1K2Ssc6wYL5ATggtwpjBZGV8bN4E1z0WJz+l0=; b=ovqe97Rx9INN4v8E+7iY1Ri/T8q39c8LKQB/Nkn2Q2c5jK3zIhiyzOdpoEktmWiUiV 6xPRCZSfCNDvPbrbu9hzEKz5lJFW5WPU9TuEPZDL5rMauZQCZBY72tXUq2vITiD7Ztbz /Wsip6k3WRapLThFZfTkQf9DEvtlJbr6sBlsyKr6vSi4AyuFWZ/Z9EkNfnQHp6t/R3lg OPn2/S2N9fHFZF6v4g81ByUGcXD8oTpawNC89g3UH9pbnk9QZF7xdtN79/kVK16z0xV3 QegdZF+BPNJSdeuBOh8ghFK5MHZQeGoRGyQ9UtMqVYNOO19Nh+v/k/tzxfPk5L/x40oD ks4g== X-Gm-Message-State: AOAM533USqvJLZC/bG+s0HnaNDBN+oWIr7MgMQ3rs1rc+Nn1oHQWf1tV Ye2Z6uShUvvmzsMiOvXwAln2kQ== X-Google-Smtp-Source: ABdhPJzV0HzIDpKbGDmqtxQe7LhDLbS8SGeQuf1EQMt6sz97V3whIgLyjr8wu5fOvLeIFtQZKYUmXQ== X-Received: by 2002:a5d:4203:: with SMTP id n3mr4765868wrq.132.1622823170108; Fri, 04 Jun 2021 09:12:50 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 92/99] target/arm: remove v7m stub function for !CONFIG_TCG Date: Fri, 4 Jun 2021 16:53:05 +0100 Message-Id: <20210604155312.15902-93-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Claudio Fontana Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Claudio Fontana it is needed just once, so just move the CONFIG_TCG check in place. Signed-off-by: Claudio Fontana Signed-off-by: Alex Benn=C3=A9e --- target/arm/cpu-mmu.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu-mmu.c b/target/arm/cpu-mmu.c index c6ac90a61e..e1bebbf73e 100644 --- a/target/arm/cpu-mmu.c +++ b/target/arm/cpu-mmu.c @@ -19,6 +19,7 @@ */ =20 #include "qemu/osdep.h" +#include "sysemu/tcg.h" #include "cpu-mmu.h" =20 int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) @@ -155,20 +156,15 @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) } } =20 -#ifndef CONFIG_TCG -ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) -{ - g_assert_not_reached(); -} -#endif - ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el) { ARMMMUIdx idx; uint64_t hcr; =20 - if (arm_feature(env, ARM_FEATURE_M)) { - return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); + if (tcg_enabled()) { + if (arm_feature(env, ARM_FEATURE_M)) { + return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure); + } } =20 /* See ARM pseudo-function ELIsInHost. */ --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622824315; cv=none; d=zohomail.com; s=zohoarc; b=czBL+38nbonpOXE2r5dACUjOR0SaRuAGpI96bF4fNwqdUl1RNc/VuuMCB79uF3fkM0FknudXU8NoZ52GYaRPpiOVT32sSuLYasBOoPqXziH2p8U8XJSkGRBzAdjgsBMC1L1vkVYM18PZp+ALmjb037kpp+TFba+NPiEw7KBScpA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622824315; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QeEI4sc2dcuV1npg4L31+R2Mrp6pBAsdJJMzJp4sGcE=; b=UKEevoId4Bh5pPSDmGp1cTgvsSXVhEw6On9Q8MQtr2jWQOhW4dDmh6RpNanRK75wcrNdGRdCSxSx94F/xzw0RnkGL+M8AIK2gKZ21quV09Y/nnJ5rdkDGL+mgOeAMVg2OSl1mYLLz5J+5hSR3e/9O87EbI+W+K7zMbNGvTpVGT0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622824315371522.1568155068567; Fri, 4 Jun 2021 09:31:55 -0700 (PDT) Received: from localhost ([::1]:53648 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCji-00044m-84 for importer@patchew.org; Fri, 04 Jun 2021 12:31:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48326) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCHg-0007uC-JP for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:02:57 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:35700) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHX-0005mB-Nm for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:02:56 -0400 Received: by mail-wr1-x435.google.com with SMTP id m18so9836976wrv.2 for ; Fri, 04 Jun 2021 09:02:47 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id n9sm8226282wrt.81.2021.06.04.09.02.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:43 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 50DBB2001C; Fri, 4 Jun 2021 16:53:24 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QeEI4sc2dcuV1npg4L31+R2Mrp6pBAsdJJMzJp4sGcE=; b=eeamy+HhDQrUpgVH84rB+qmGjwMURu271d/xyE/eihURSMWrojHNhK9ic0YqaT6WQY zBL/B3Y84IsrP05IvsCzv2rRf82cKNtu5awnNsqzk1eotP/Wb1ejksc02qKa3WdOF8jl Cc+1z8LbaawVjITEG0E1B0sQzYDEeuNG8KA+yumxqJ19AdWBkPgzWWKNhi903mSWaXoD KWLNy8dYo33CppPeNArEWdmf+CfowWChZjeRt+daX+onP9koJe3r7qevC3x/8O65hUh8 qPRDcgF8RE6Aku8XrEuXQ8nmcXGFXTfpxCJmrDUORS/HPY+2pqgAjC6xHbBSEclRUyPB v11Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QeEI4sc2dcuV1npg4L31+R2Mrp6pBAsdJJMzJp4sGcE=; b=VD4ecCVByfXTxaVp3eDfj78+r9psVFfe2bmx4ZUexMa8Vj6P5dtViXSb+evtc8+kX0 EFR03Zn6Y44Fl7qHj8dvYc9A/YibCzge0jqgQFrTGqaGNi3OvZO9v781Jqh6ZGaZAhsE v+qKHM1UQrgiu7citvGIF7SgmpA/3201RnTMDhtlGf5kRJqcgAD/LsVBDABA0oSJqpdT GcUIv9BQB9MbJ8tSGdnhauCrOKUBMswW8NaI80t37adgRacHkBVOgsy4wi8OyhyXdn7V kTRLmPaC9ImBMMycfzjn1yhHZLCLpEctzoQ0lG55fps8SqMiko3WSolbWjzBf5DdwNBs ML1Q== X-Gm-Message-State: AOAM533BJxP9IMUVfmaXrN2YKlaqv38I9ha0zEQlciNvChgtBSsuLVW3 h0uJ1bBespW/BnN+cr/pg8SMdw== X-Google-Smtp-Source: ABdhPJy3IOkRSpbL8eFa3ZXtQjudbo1pdxVtFXKrGt0zwpoTWtwW417L8IQdlznYobp/Txu6JAiNIA== X-Received: by 2002:a5d:414e:: with SMTP id c14mr4484404wrq.81.1622822566165; Fri, 04 Jun 2021 09:02:46 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 93/99] meson: Introduce target-specific Kconfig Date: Fri, 4 Jun 2021 16:53:06 +0100 Message-Id: <20210604155312.15902-94-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Cornelia Huck , David Hildenbrand , Bin Meng , Mark Cave-Ayland , Thomas Huth , Laurent Vivier , Max Filippov , Alistair Francis , "Edgar E. Iglesias" , Marek Vasut , Yoshinori Sato , "open list:PowerPC TCG CPUs" , Artyom Tarasenko , Aleksandar Rikalo , Richard Henderson , Greg Kurz , "open list:S390 TCG CPUs" , qemu-arm@nongnu.org, Michael Rolnik , Stafford Horne , David Gibson , "open list:RISC-V TCG CPUs" , Bastian Koppelmann , Chris Wulff , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Philippe Mathieu-Daud=C3=A9 Add a target-specific Kconfig. Target foo now has CONFIG_FOO defined. Two architecture have a particularity, ARM and MIPS: their 64-bit version include the 32-bit subset. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20210131111316.232778-6-f4bug@amsat.org> --- meson.build | 3 ++- Kconfig | 1 + target/Kconfig | 23 +++++++++++++++++++++++ target/alpha/Kconfig | 2 ++ target/arm/Kconfig | 6 ++++++ target/avr/Kconfig | 2 ++ target/cris/Kconfig | 2 ++ target/hppa/Kconfig | 2 ++ target/i386/Kconfig | 5 +++++ target/lm32/Kconfig | 2 ++ target/m68k/Kconfig | 2 ++ target/microblaze/Kconfig | 2 ++ target/mips/Kconfig | 6 ++++++ target/moxie/Kconfig | 2 ++ target/nios2/Kconfig | 2 ++ target/openrisc/Kconfig | 2 ++ target/ppc/Kconfig | 5 +++++ target/riscv/Kconfig | 5 +++++ target/rx/Kconfig | 2 ++ target/s390x/Kconfig | 2 ++ target/sh4/Kconfig | 2 ++ target/sparc/Kconfig | 5 +++++ target/tilegx/Kconfig | 2 ++ target/tricore/Kconfig | 2 ++ target/unicore32/Kconfig | 2 ++ target/xtensa/Kconfig | 2 ++ 26 files changed, 92 insertions(+), 1 deletion(-) create mode 100644 target/Kconfig create mode 100644 target/alpha/Kconfig create mode 100644 target/arm/Kconfig create mode 100644 target/avr/Kconfig create mode 100644 target/cris/Kconfig create mode 100644 target/hppa/Kconfig create mode 100644 target/i386/Kconfig create mode 100644 target/lm32/Kconfig create mode 100644 target/m68k/Kconfig create mode 100644 target/microblaze/Kconfig create mode 100644 target/mips/Kconfig create mode 100644 target/moxie/Kconfig create mode 100644 target/nios2/Kconfig create mode 100644 target/openrisc/Kconfig create mode 100644 target/ppc/Kconfig create mode 100644 target/riscv/Kconfig create mode 100644 target/rx/Kconfig create mode 100644 target/s390x/Kconfig create mode 100644 target/sh4/Kconfig create mode 100644 target/sparc/Kconfig create mode 100644 target/tilegx/Kconfig create mode 100644 target/tricore/Kconfig create mode 100644 target/unicore32/Kconfig create mode 100644 target/xtensa/Kconfig diff --git a/meson.build b/meson.build index e2a22984b8..09c7809d6b 100644 --- a/meson.build +++ b/meson.build @@ -1359,7 +1359,8 @@ foreach target : target_dirs command: [minikconf, get_option('default_devices') ? '--defconfig' : '--allnoco= nfig', config_devices_mak, '@DEPFILE@', '@INPUT@', - host_kconfig, accel_kconfig]) + host_kconfig, accel_kconfig, + 'CONFIG_' + config_target['TARGET_ARCH'].to_upper() + '=3D= y']) =20 config_devices_data =3D configuration_data() config_devices =3D keyval.load(config_devices_mak) diff --git a/Kconfig b/Kconfig index d52ebd839b..fb6a24a2de 100644 --- a/Kconfig +++ b/Kconfig @@ -1,5 +1,6 @@ source Kconfig.host source backends/Kconfig source accel/Kconfig +source target/Kconfig source hw/Kconfig source semihosting/Kconfig diff --git a/target/Kconfig b/target/Kconfig new file mode 100644 index 0000000000..a6f719f223 --- /dev/null +++ b/target/Kconfig @@ -0,0 +1,23 @@ +source alpha/Kconfig +source arm/Kconfig +source avr/Kconfig +source cris/Kconfig +source hppa/Kconfig +source i386/Kconfig +source lm32/Kconfig +source m68k/Kconfig +source microblaze/Kconfig +source mips/Kconfig +source moxie/Kconfig +source nios2/Kconfig +source openrisc/Kconfig +source ppc/Kconfig +source riscv/Kconfig +source rx/Kconfig +source s390x/Kconfig +source sh4/Kconfig +source sparc/Kconfig +source tilegx/Kconfig +source tricore/Kconfig +source unicore32/Kconfig +source xtensa/Kconfig diff --git a/target/alpha/Kconfig b/target/alpha/Kconfig new file mode 100644 index 0000000000..267222c05b --- /dev/null +++ b/target/alpha/Kconfig @@ -0,0 +1,2 @@ +config ALPHA + bool diff --git a/target/arm/Kconfig b/target/arm/Kconfig new file mode 100644 index 0000000000..3f3394a22b --- /dev/null +++ b/target/arm/Kconfig @@ -0,0 +1,6 @@ +config ARM + bool + +config AARCH64 + bool + select ARM diff --git a/target/avr/Kconfig b/target/avr/Kconfig new file mode 100644 index 0000000000..155592d353 --- /dev/null +++ b/target/avr/Kconfig @@ -0,0 +1,2 @@ +config AVR + bool diff --git a/target/cris/Kconfig b/target/cris/Kconfig new file mode 100644 index 0000000000..3fdc309fbb --- /dev/null +++ b/target/cris/Kconfig @@ -0,0 +1,2 @@ +config CRIS + bool diff --git a/target/hppa/Kconfig b/target/hppa/Kconfig new file mode 100644 index 0000000000..395a35d799 --- /dev/null +++ b/target/hppa/Kconfig @@ -0,0 +1,2 @@ +config HPPA + bool diff --git a/target/i386/Kconfig b/target/i386/Kconfig new file mode 100644 index 0000000000..ce6968906e --- /dev/null +++ b/target/i386/Kconfig @@ -0,0 +1,5 @@ +config I386 + bool + +config X86_64 + bool diff --git a/target/lm32/Kconfig b/target/lm32/Kconfig new file mode 100644 index 0000000000..09de5b703a --- /dev/null +++ b/target/lm32/Kconfig @@ -0,0 +1,2 @@ +config LM32 + bool diff --git a/target/m68k/Kconfig b/target/m68k/Kconfig new file mode 100644 index 0000000000..23debad519 --- /dev/null +++ b/target/m68k/Kconfig @@ -0,0 +1,2 @@ +config M68K + bool diff --git a/target/microblaze/Kconfig b/target/microblaze/Kconfig new file mode 100644 index 0000000000..a5410d9218 --- /dev/null +++ b/target/microblaze/Kconfig @@ -0,0 +1,2 @@ +config MICROBLAZE + bool diff --git a/target/mips/Kconfig b/target/mips/Kconfig new file mode 100644 index 0000000000..6adf145354 --- /dev/null +++ b/target/mips/Kconfig @@ -0,0 +1,6 @@ +config MIPS + bool + +config MIPS64 + bool + select MIPS diff --git a/target/moxie/Kconfig b/target/moxie/Kconfig new file mode 100644 index 0000000000..52391bbd28 --- /dev/null +++ b/target/moxie/Kconfig @@ -0,0 +1,2 @@ +config MOXIE + bool diff --git a/target/nios2/Kconfig b/target/nios2/Kconfig new file mode 100644 index 0000000000..1529ab8950 --- /dev/null +++ b/target/nios2/Kconfig @@ -0,0 +1,2 @@ +config NIOS2 + bool diff --git a/target/openrisc/Kconfig b/target/openrisc/Kconfig new file mode 100644 index 0000000000..e0da4ac1df --- /dev/null +++ b/target/openrisc/Kconfig @@ -0,0 +1,2 @@ +config OPENRISC + bool diff --git a/target/ppc/Kconfig b/target/ppc/Kconfig new file mode 100644 index 0000000000..3ff152051a --- /dev/null +++ b/target/ppc/Kconfig @@ -0,0 +1,5 @@ +config PPC + bool + +config PPC64 + bool diff --git a/target/riscv/Kconfig b/target/riscv/Kconfig new file mode 100644 index 0000000000..b9e5932f13 --- /dev/null +++ b/target/riscv/Kconfig @@ -0,0 +1,5 @@ +config RISCV32 + bool + +config RISCV64 + bool diff --git a/target/rx/Kconfig b/target/rx/Kconfig new file mode 100644 index 0000000000..aceb5ed28f --- /dev/null +++ b/target/rx/Kconfig @@ -0,0 +1,2 @@ +config RX + bool diff --git a/target/s390x/Kconfig b/target/s390x/Kconfig new file mode 100644 index 0000000000..72da48136c --- /dev/null +++ b/target/s390x/Kconfig @@ -0,0 +1,2 @@ +config S390X + bool diff --git a/target/sh4/Kconfig b/target/sh4/Kconfig new file mode 100644 index 0000000000..2397c86028 --- /dev/null +++ b/target/sh4/Kconfig @@ -0,0 +1,2 @@ +config SH4 + bool diff --git a/target/sparc/Kconfig b/target/sparc/Kconfig new file mode 100644 index 0000000000..70cc0f3a21 --- /dev/null +++ b/target/sparc/Kconfig @@ -0,0 +1,5 @@ +config SPARC + bool + +config SPARC64 + bool diff --git a/target/tilegx/Kconfig b/target/tilegx/Kconfig new file mode 100644 index 0000000000..aad882826a --- /dev/null +++ b/target/tilegx/Kconfig @@ -0,0 +1,2 @@ +config TILEGX + bool diff --git a/target/tricore/Kconfig b/target/tricore/Kconfig new file mode 100644 index 0000000000..9313409309 --- /dev/null +++ b/target/tricore/Kconfig @@ -0,0 +1,2 @@ +config TRICORE + bool diff --git a/target/unicore32/Kconfig b/target/unicore32/Kconfig new file mode 100644 index 0000000000..62c9d10b38 --- /dev/null +++ b/target/unicore32/Kconfig @@ -0,0 +1,2 @@ +config UNICORE32 + bool diff --git a/target/xtensa/Kconfig b/target/xtensa/Kconfig new file mode 100644 index 0000000000..a3c8dc7f6d --- /dev/null +++ b/target/xtensa/Kconfig @@ -0,0 +1,2 @@ +config XTENSA + bool --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622823562; cv=none; d=zohomail.com; s=zohoarc; b=K+3qiV1iWXP1UF6xgdXMgUorOOkKcKSgx7MQJrTS90PW1FynW+nfREro9Mk692Hu4hhBHa+z6k84v22jMYvgyudp6NLXoUtXTjeF78oqZgedsJeyyGzvitbK7Iy96XZCYDr33co+d0952O4R19/3zkMxKGsIbxCRTKbaax8103I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622823562; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/YG66hyD1VOf/fOI4qw/ZTnuURBGgVxAEUhf5rfH4Y0=; b=J6umxOA3R5AYjA/r5j6JghKzIUbKCsdq8aCQu2srbZi8EnQyr0M7sBceUNl0vzB+a0CEC9U7Jw2cpkquVO9bKcbO6UJ5eaONWPfz518VxZYF5JvRSOlLNaK+nMfzsY4MQ86ojn0LAKK9T81M2egaPlJMMAyvYVqjVbil4qUBJb4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622823562456641.8518128064586; Fri, 4 Jun 2021 09:19:22 -0700 (PDT) Received: from localhost ([::1]:39080 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCXZ-00006Q-Bz for importer@patchew.org; Fri, 04 Jun 2021 12:19:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48594) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCI4-0008Ny-7X for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:20 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:43536) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCHd-0005qK-JY for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:03:19 -0400 Received: by mail-wr1-x436.google.com with SMTP id u7so4384708wrs.10 for ; Fri, 04 Jun 2021 09:02:53 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id l2sm6843694wrp.21.2021.06.04.09.02.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:02:43 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 6C56E20021; Fri, 4 Jun 2021 16:53:24 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/YG66hyD1VOf/fOI4qw/ZTnuURBGgVxAEUhf5rfH4Y0=; b=fC6Z4tu+Pi3NnHTTj1S95aaBJf3XfPsnkTphTm3RJjD9o+QNOsVgm5+CQjJfyd/Dg5 9OGU/p8Bks+cAY+zoQLH9We4C7sZ4Z0aGsBQ3/HuSvmqop3xpF5PJ4PaSxq7OA3b0zR7 qi3pjjl6cbWqRNsaBJZ3nc8Y7v4fq05u+nGUQUrI1/qHk1VJp1mJYv2u0Oa2MswHYHNH XHFwNy0XxbKpSK9lnXN9sJBLlyheeBYHkfNUh6Mfd7UBMVjuJCdimNpaKaMgudOU9W3B bDlb9dOz5UVokJn+7Qj6z+52HyHAsa0ObA3nDgEXyQevHJE0jGD/weNGp9eUlgM1zHkV xYQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/YG66hyD1VOf/fOI4qw/ZTnuURBGgVxAEUhf5rfH4Y0=; b=iYQ7S68iJbwXjm422NppglgOwbABL4rvo2MA8m8XukRkqTldtSF6pnFhR6Opl8mE5Y ncJNzFq2q6uGyL49JJKyLY82M8TY3WEMr5m26eGYHfYmD4CyCMS4M5HA79FoxDXQfi4i /fbwyXjl64dbasbbnp3fs76TPsjJ5TEefCwAtsLPsoPWN23pOl14XTcq8z5Mk8khI9MM G4Zb3tKzofGkucgV0rSzafRZaXtdnJaB3jV50i+5m5xgZHDAwEeSYgl1xKicTxbE6dMW hwex5cWFVnAfxOjThaRokZRnb36nTxX5mgC+bURxebxqaUecN9sAkIi9wWE/LrcVCPMK NSYQ== X-Gm-Message-State: AOAM532speN1Dqmx4QLpl/tUf3vb37yzmTsaGJZtFQqiZ+jOhvMNqOn2 WXW1Cm9Pe10Vdc2c+VnyuuZ8FA== X-Google-Smtp-Source: ABdhPJxoNh4ZssVD5lwFM3Dx5OLmXna9H8Fq7cYBY7tnC0SQE6H+rLqFNc9rVxR8bEvO5OPslTURRQ== X-Received: by 2002:adf:f98a:: with SMTP id f10mr4644621wrr.143.1622822572137; Fri, 04 Jun 2021 09:02:52 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 94/99] target/arm: move CONFIG_V7M out of default-devices Date: Fri, 4 Jun 2021 16:53:07 +0100 Message-Id: <20210604155312.15902-95-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) We currently select CONFIG_V7M for a bunch of our m-profile devices. The last sticking point is translate.c which cannot be compiled without expecting v7m support. Express this dependency in Kconfig rather than in default devices as a stepping stone to a fully configurable translate.c. While we are at it we also need to select ARM_COMPATIBLE_SEMIHOSTING as that is implied for M profile machines. Signed-off-by: Alex Benn=C3=A9e --- default-configs/devices/arm-softmmu.mak | 3 --- hw/arm/Kconfig | 3 +++ target/arm/tcg/sysemu/meson.build | 5 ++++- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/default-configs/devices/arm-softmmu.mak b/default-configs/devi= ces/arm-softmmu.mak index 0500156a0c..4114aa9e35 100644 --- a/default-configs/devices/arm-softmmu.mak +++ b/default-configs/devices/arm-softmmu.mak @@ -1,8 +1,5 @@ # Default configuration for arm-softmmu =20 -# TODO: ARM_V7M is currently always required - make this more flexible! -CONFIG_ARM_V7M=3Dy - # CONFIG_PCI_DEVICES=3Dn # CONFIG_TEST_DEVICES=3Dn =20 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 67723d9ea6..afaf807c92 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -296,7 +296,10 @@ config ZYNQ =20 config ARM_V7M bool + # currently v7M must be included in a TCG build due to translate.c + default y if TCG && (ARM || AARCH64) select PTIMER + select ARM_COMPATIBLE_SEMIHOSTING =20 config ALLWINNER_A10 bool diff --git a/target/arm/tcg/sysemu/meson.build b/target/arm/tcg/sysemu/meso= n.build index 56e4b5ccea..520f305deb 100644 --- a/target/arm/tcg/sysemu/meson.build +++ b/target/arm/tcg/sysemu/meson.build @@ -1,7 +1,10 @@ arm_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( 'debug_helper.c', - 'm_helper.c', 'mte_helper.c', 'tcg-cpu.c', 'tlb_helper.c', )) + +arm_softmmu_ss.add(when: 'CONFIG_ARM_V7M', if_true: files( + 'm_helper.c', +)) --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622828358; cv=none; d=zohomail.com; s=zohoarc; b=i3wKx5ZVetGCC9aqFjLbsyUAw1rAcGca1ncRYIDEeZk55D45db2Zj5XnRuxFUicmXVDLI706pcGbK8DhzC9ZFOMdLh1i6z+bX6rZYVl7snlXQQsbtenmLwKm1c+yfopI2zyCsitmmiNvj/0Sgb/F2EF3/kJZiipVYgdwihQb8vY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622828358; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YHX7W7pdovA8sEaHbdvBxPdYJmSQGO3xjxfiDb+VvUU=; b=YZ+aAjfYjRwAm5h3or08w0Ly+FjBrrRpiMS94kBqgLIzq5zEDNW69DnA8JO8MD4kmVpDn1M2je+awACfyoJX/MnBCfSnlRsRXT1JhaCvknsDjHwHSdD0rbu8wEP9JceW4g+0KBB79d9NlztdMrrEpKeuB1SDOrFxdqJxtBtt9/I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16228283580161005.0671764204094; Fri, 4 Jun 2021 10:39:18 -0700 (PDT) Received: from localhost ([::1]:55640 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDmu-0001J7-RB for importer@patchew.org; Fri, 04 Jun 2021 13:39:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48944) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpDNT-0000N6-Nq for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:59 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:33727) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpDNR-00028U-AH for qemu-devel@nongnu.org; Fri, 04 Jun 2021 13:12:59 -0400 Received: by mail-wr1-x431.google.com with SMTP id a20so10078149wrc.0 for ; Fri, 04 Jun 2021 10:12:56 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id m22sm1190276wmq.21.2021.06.04.10.12.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 10:12:46 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 8150B20023; Fri, 4 Jun 2021 16:53:24 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YHX7W7pdovA8sEaHbdvBxPdYJmSQGO3xjxfiDb+VvUU=; b=rs7ezZV7gCdf3aUQB0E6qL/jm7MgBEpBi7CEhaulBEMsi6cOzQyepxi4s2BukgV748 PwQ247qsBXs2KM6kwmf1JVDYtrRPHBiCn0kB+ZSCimu+BcswEbBXz6koH8Ux4OGTYbAx 7opJTl1qdFOOEVsbJCJOCM6h7644KP2CDomrX4c+9buz2TkgtnosELU4xFvtVZVNxC/V d7Lk9g//cn0MXAhRg+Ztd26YTaW6Quxzpe1JRH48b2Cte7SfnpXcZeyi8zZgXbALfl/b c50SPeqIXBhNBiQpazzZMJHVzu1cZ98DQT26qGNZVHTxPlsHxSOZDA3VI1Wflh19dTtF CcYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YHX7W7pdovA8sEaHbdvBxPdYJmSQGO3xjxfiDb+VvUU=; b=cua+OmrLg6ulPq10/wFun2Vc839AI8GfeS4f+MkbneT1WCJndJ3+O4RlqfDSTiq+Vw lW9IUdLYAtHQV4BG0ocDwwNI1G5ZLeJ4kvJbmubz8w0Ub6IwQ98n7JAZhWuV1TfjazoX xdPiB6bkUJa7tp04DwFVI+eLLoqhWfjBPQUTAjTt6jU8C6jAiyX//RUmQhleBmk8/wtT 5mH/1PIVzQeDNBpbssAZbZW/T9pPMA7a9hgpSeRIXZ0IfFTK03GXEgonAsiUt0GPE4wu yCZ6d3gZOTzkkZEkF394W2LAvV5bCqZs8kni/myqkfCqSIQyM2U+xGK0v4Rqh1g7c/HW zTXA== X-Gm-Message-State: AOAM533Z1pFcnehW/XMeSCN2fK56ERQO7yotQS6l55LHcpuvharNm4fK gz/47G0TxEtjcwOBTrFpZNUtZA== X-Google-Smtp-Source: ABdhPJw07QOmfs5qh+xdFRfGSeyaA6eg15d+GHM6EbygIUisvL1wp2iFrzMrnJvK6EVG7yAuM4LdwA== X-Received: by 2002:adf:df87:: with SMTP id z7mr5029279wrl.56.1622826775698; Fri, 04 Jun 2021 10:12:55 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 95/99] hw/arm: add dependency on OR_IRQ for XLNX_VERSAL Date: Fri, 4 Jun 2021 16:53:08 +0100 Message-Id: <20210604155312.15902-96-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) We need this functionality due to: /* XRAM IRQs get ORed into a single line. */ object_initialize_child(OBJECT(s), "xram-irq-orgate", &s->lpd.xram.irq_orgate, TYPE_OR_IRQ); Signed-off-by: Alex Benn=C3=A9e --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index afaf807c92..02962c0987 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -371,6 +371,7 @@ config XLNX_VERSAL select UNIMP select XLNX_ZDMA select XLNX_ZYNQMP + select OR_IRQ =20 config NPCM7XX bool --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622823694; cv=none; d=zohomail.com; s=zohoarc; b=Oe/prDjQh1BpeLIesw8uBz5iMpCALgc+myTpUxs4V+DQ4SkscCS8jte8EjU1vc149mbszy+T5Y+O2N/FOPP5e0AgmrWZtty9CRB1xgA/nOFf7C2FTTrBXbqZG3bpg6ZQ+ECXkCM0jFjXsOhR14V7LbURIptUeqa+wrLx/VIlUbU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622823694; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dsyKHQJNOhAXErDDhKEWsE1reIuTyEMwEV0R3vqvPqo=; b=lJHsTy0VtmGVUd4ubPennFRQCC0JozHOqYZHShvMWb2wmIKI+YHLTiZwN/UwSt07RuXKpEn1HLKua6K2g+qf2JXoQhW7zy2j3bsIrcuxkuWSEGyoKPA22+dZCT2ehORj0HjTYNRVzgChGx0V5zLEE+Ffqx/63xyv71/w6lF96nU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622823694106274.54673482307624; Fri, 4 Jun 2021 09:21:34 -0700 (PDT) Received: from localhost ([::1]:45652 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCZh-0004pe-2m for importer@patchew.org; Fri, 04 Jun 2021 12:21:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44846) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8m-0003Vk-CZ for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:44 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:38650) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8i-0000EG-8p for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:44 -0400 Received: by mail-wm1-x331.google.com with SMTP id t4-20020a1c77040000b029019d22d84ebdso8196543wmi.3 for ; Fri, 04 Jun 2021 08:53:39 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id c23sm9110099wme.37.2021.06.04.08.53.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:31 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 96AC31FF92; Fri, 4 Jun 2021 16:53:24 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dsyKHQJNOhAXErDDhKEWsE1reIuTyEMwEV0R3vqvPqo=; b=ylkJNz4GI+pdjTJ8e7ZpdDZFzkDAO/0NVJO2mS/6czgbyE6dMwlXVTNjBmjnDCJ8ib LmDB1Aqtb57TQEIhiutaZ/3S7KYR6grnTepTaLHA8faoCcmB3x0EgXex7SXoAyniTgW5 S4GemIN4svMgYyh/o63H7UXSy16BEZnxnYCFk8NxSfN3m3QN67FGLvzLT4/ZKeONndCF tc/wpq9AeQmfO0fYSptBj65S10PhJfIS4qRXu0ZQ1GII+8HbxzKc0+8ccDRLmfoYVLDA hmhDtF3YAh0mEd0xaBLnD/ZLghicvwnI35Krb42+buE9jYLn/lx3o2OVrm+IGdlwUIA7 SjNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dsyKHQJNOhAXErDDhKEWsE1reIuTyEMwEV0R3vqvPqo=; b=gnwC4d/K8AOc3+qsgPWRQJdWzK4HDy2BPUgHBSCXxZXfOLReHR2EVu5UtcpycrhBbU HUQ/z1McU5b9GM58mh5MFA2YcAn36X0DBJXbgJGFqRJPfgnPsYCYORLq53bmOmCiFkg+ yUu72DT8lUywJGS/v+jjq34D2dZECo9fVW25G8py7ezz3b0SIZOP5hjKpimiB3yPrbuJ T/dgh5ccgMxbnJmKe6S0GiQajE87H5l4vvVksJSq2Xtngdpj23l/innWSuSikrsHGP7y 8lk22NBKqzRSAGUGumIdgMIlWpDuTUMRAjavMAgm2Ac0TR4pIdBqv0qAvjey7fa6zIE6 lMIA== X-Gm-Message-State: AOAM530H2HS1ayJuvGlBalK11vEZJyF241F7mHgwnVeu+Dg01PtYPBWW F6my2t3zT0YydQRH/WtUT8+UjA== X-Google-Smtp-Source: ABdhPJz8C3AWDs1VwBlGFojha1Z5+/DCrGZ9Kapu/NrazzA8jjF5qNukKeJCJdI7Sqo2HS08z0V7nQ== X-Received: by 2002:a1c:8016:: with SMTP id b22mr4252034wmd.43.1622822018959; Fri, 04 Jun 2021 08:53:38 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 96/99] tests/qtest: split the cdrom-test into arm/aarch64 Date: Fri, 4 Jun 2021 16:53:09 +0100 Message-Id: <20210604155312.15902-97-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , "open list:IDE" , =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, Paolo Bonzini , John Snow Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The assumption that the qemu-system-aarch64 image can run all 32 bit machines is about to be broken and besides it's not likely this is improving out coverage by much. Test the "virt" machine for both arm and aarch64 as it can be used by either architecture. Signed-off-by: Alex Benn=C3=A9e --- tests/qtest/cdrom-test.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tests/qtest/cdrom-test.c b/tests/qtest/cdrom-test.c index 5af944a5fb..1e74354624 100644 --- a/tests/qtest/cdrom-test.c +++ b/tests/qtest/cdrom-test.c @@ -220,13 +220,16 @@ int main(int argc, char **argv) "magnum", "malta", "pica61", NULL }; add_cdrom_param_tests(mips64machines); - } else if (g_str_equal(arch, "arm") || g_str_equal(arch, "aarch64")) { + } else if (g_str_equal(arch, "arm")) { const char *armmachines[] =3D { "realview-eb", "realview-eb-mpcore", "realview-pb-a8", "realview-pbx-a9", "versatileab", "versatilepb", "vexpress-a15= ", "vexpress-a9", "virt", NULL }; add_cdrom_param_tests(armmachines); + } else if (g_str_equal(arch, "aarch64")) { + const char *aarch64machines[] =3D { "virt", NULL }; + add_cdrom_param_tests(aarch64machines); } else { const char *nonemachine[] =3D { "none", NULL }; add_cdrom_param_tests(nonemachine); --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622822938; cv=none; d=zohomail.com; s=zohoarc; b=Wisa1nYtH4jIuBtBiRdfFu7TNGT1IFQDmNATHlsyd9o1YQXFBfvdcvypbmcHOdXrsIfk1FgyhHfDAspivxMu+5VfqJfCb+LgT0VPwT77TzahYQM2+W5QbUsagpm8OvO1VwcINCVKF+/ThQjCrOZstlqTqRfXrFgxAMankfponJw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622822938; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HwjS13hI3FClI76JoclT19qTXBq1v/r670a52v458qs=; b=f+VLwhEfdmCJqPAD4LdeVPhWpbXt2LsBgmozcufrXmvUFI24Q/zdFSbIjXCRaeXSX2kG98/OtfhXEL7w0NekSFawdEpWqXGz5qENEJ7gPkNlVZTPMf0XFxVRCqYDz6+8F8COBYdX4ZdXijc3byOSyZuBbgOFXguc06nqeXWWN48= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622822938279409.6800436896033; Fri, 4 Jun 2021 09:08:58 -0700 (PDT) Received: from localhost ([::1]:33688 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCNV-00017v-1Z for importer@patchew.org; Fri, 04 Jun 2021 12:08:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44820) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpC8k-0003TB-Mm for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:42 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:34309) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpC8h-0000DH-In for qemu-devel@nongnu.org; Fri, 04 Jun 2021 11:53:42 -0400 Received: by mail-wr1-x429.google.com with SMTP id q5so9825067wrm.1 for ; Fri, 04 Jun 2021 08:53:39 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id x125sm2617808wmg.37.2021.06.04.08.53.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:53:32 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id AC58020024; Fri, 4 Jun 2021 16:53:24 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HwjS13hI3FClI76JoclT19qTXBq1v/r670a52v458qs=; b=wGtFvCu/mJEFs8jdHdb5UJW1O0+frpqTH0dgI5ZU2ZUrJdVQb36LLNss1hTciHhA63 GMvCx0iB64yVt/oXBPVS5khvecTWwC6wUKn62mjdnmnLSOc8v9bPwTtB87C3ES3YCUrx gVVNNehqrfMfSLc8qB5+GM+7hFfLISKeCWeuKOBRuyKIBJFWrGStyI+oL2C6syZNGELc AEcPf0goktZ0cActcS3jK1UMq4Ho68WUvApPNl+s16pwlDvDApt/thEqLKrxwCOFysQc Hy9kbyN7HowNcsu6Dwc5nwt22Lqzt63q/xFLQGs6nPZTMBv9cQ5SwUv9e22rfwwH1des oStA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HwjS13hI3FClI76JoclT19qTXBq1v/r670a52v458qs=; b=LJ7cNmChfzvedT9JfdnWx/LkJXMtakjUTo5ikrLWqlU8vKcYWBPCheXD3fL1e9SMf8 uYX9UKBYaFt0Q6WE3b+UiOXSxEH4UMA5ksFg4bPd1Xt5798UDWdyQCxp+v7Zpfws6ukW Ztc1f/AvsxjqnSizP6yjRd//pu+IS4/GzjCp4zwACnkissfITnyHnYMBqzvBcf749p/G nUJmBXGLCn8TSnlxZqScMaoIowaqjtqs5MHnLxZwUijBzF96jRNr5hMLAcHsQEUtGm4t 4e5R3q9vRK73IBlI1CLL4MqrURbZHIiGv1mS0JEAQ1TXkaAb7LeUoIQxQUqSl9pu3aCl 24hg== X-Gm-Message-State: AOAM530JEY5ZBqF3kLr9dg7OA1dZmzMeDe3pAvUyJAl2F2ki1AGkZIHJ Gy174Mjzrq4ER+yOaer4WjSGCw== X-Google-Smtp-Source: ABdhPJzjepIt/J7YHuqVe79mWTwXeFRfd8c8T7lujXxe5Q6sKu9p+ekkhDZna1cx7Uz4Ti2v362jTQ== X-Received: by 2002:adf:bc07:: with SMTP id s7mr4668803wrg.301.1622822018180; Fri, 04 Jun 2021 08:53:38 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 97/99] tests/qtest: make xlnx-can-test conditional on being configured Date: Fri, 4 Jun 2021 16:53:10 +0100 Message-Id: <20210604155312.15902-98-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Paolo Bonzini , Thomas Huth , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) It will soon be possible to build an qemu-system-aarch64 system that doesn't have this. Signed-off-by: Alex Benn=C3=A9e --- tests/qtest/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 2c7415d616..772e62920c 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -179,11 +179,11 @@ qtests_arm =3D \ qtests_aarch64 =3D \ (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-= test'] : []) + \ (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-= swtpm-test'] : []) + \ + (config_all_devices.has_key('CONFIG_XLNX_ZYNQMP_ARM') ? ['xlnx-can-test'= ] : []) + \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', 'bios-tables-test', - 'xlnx-can-test', 'migration-test'] =20 qtests_s390x =3D \ --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622827168; cv=none; d=zohomail.com; s=zohoarc; b=T7AnD0p7IPdPd2cVthpq0RE/PZXfwUOq0k9cJz0Qqk3BMnhIjUXnGKL+wgHwRlvA+iHx3Ig7fqpK/zYUn6Kb/HBkX+OzhojmUocyKJsKvbOKMCN8DJmnUDd04jdz0nrNz8a/UZUACe07Kgp8rPu7Df6oAa3LCX/RzsePTrgjDEM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622827168; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=79gl5zIRvGor1ajCQ3OtdQMP/o/iWQG5y8hlHOshVx0=; b=GGVkbOi4WQFCnJnVFG1HZzue3D9ab+7FPO24qVB7nq81meW8HPDld5RJNcYtJisJkNEH2jJJnJQkBO2cRvKk2+KbP824akRFtBtoUoBFVFE1S4g5AMATpDq3PJ69b8Ymw26eBHX3g6piKDtVV+p03lp4qlBQvxNok9/UqYGQbQ0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622827168656572.5456384984567; Fri, 4 Jun 2021 10:19:28 -0700 (PDT) Received: from localhost ([::1]:47280 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpDTi-0007Kp-Lj for importer@patchew.org; Fri, 04 Jun 2021 13:19:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33894) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCkz-0000XQ-E2 for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:13 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:41714) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCkl-0002EP-6G for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:33:13 -0400 Received: by mail-wr1-x42b.google.com with SMTP id h8so9890538wrz.8 for ; Fri, 04 Jun 2021 09:32:58 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id z188sm6319988wme.38.2021.06.04.09.32.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:32:51 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id C857720025; Fri, 4 Jun 2021 16:53:24 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=79gl5zIRvGor1ajCQ3OtdQMP/o/iWQG5y8hlHOshVx0=; b=cosZHVJqYiqSsO9gtZOu09LMFBHi+HLcGtBn5yfdWzeHis1OzWVeByF6tT5Y4BFCiN BwVTmlOfN/yXWllQXCtdz662amm44Eyhdc0BspAljUgGIP9ZqmGXsMS6GTzr7FZUzW94 97NbSlcZ8U9wkoELJK0DyqsXC3XaeRHJkgjMnvmGZ7mdpo2Miq4FaIUrz+YUv7DTDdC7 InMOdFXh53CB0snTkE/6CdNx2XPuiJn+C5wQj4CJVVBsrbz/K7L1i91SZT4V2LKDw3Jy 5+eTbY+XlXfHrxGJCQwa3hJWjc9f+DXzjPjy6HRkkEB6MkMnT5cL0YE8oVSzu3bUoG+Q FJtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=79gl5zIRvGor1ajCQ3OtdQMP/o/iWQG5y8hlHOshVx0=; b=ezVTEoy0ko8B/Pwzmi8cjOgV9CXDOsi9p5n++6RHAMcdAtO6T+wlUi6InD14mkbyuS 7iz9lrJKgRfbArAROZ6Ph7qOzaA2ueNbVIaP00jYRtK8XQwGtCjdX8zGuH8L1xAoN6/3 aKZWUBhuI+VcgidP91QbHyWd/PCW5tA8lu1f+GXzU2u+6TR3VvXcURaXVRIiG02hKEjb xEqJ/pgO9TWEH1Ndir185h5nhDjqX1zlcDooZReW66BZe6Kysu8XTPsIMm1q0mciHcvj UEJi39ivkVOai2Lz+8V8vZcxNyd0oIKulbiXmU9z6BCz23Cu5eFdfvrS5vrQVIW7R+HT A07w== X-Gm-Message-State: AOAM532iO9U2Th6cLp8DJvQni6eCIGvWY4kJv0bH2+wQOcTuzUt6hDBT ilotZkXc4aCeeEFZLmwiymWK1Q== X-Google-Smtp-Source: ABdhPJwaoKH+g3X9d/mVql5khmtAzEGja+y/sgp8ABUT3sxlOo8mIaYKx/i/GVsLHSjk2RiKoikJww== X-Received: by 2002:a05:6000:1b8f:: with SMTP id r15mr4696767wru.119.1622824377325; Fri, 04 Jun 2021 09:32:57 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 98/99] configure: allow the overriding of default-config in the build Date: Fri, 4 Jun 2021 16:53:11 +0100 Message-Id: <20210604155312.15902-99-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) While the default config works well enough it does end up enabling a lot of stuff. For more minimal builds we can pass a slimmed down list of devices and let Kconfig work out what we want. For example: ../../configure --without-default-features \ --target-list=3Darm-softmmu,aarch64-softmmu \ --with-devices-aarch64=3D(pwd)/../../configs/aarch64-softmmu/64bit-only= .mak will override the aarch64-softmmu default devices to one of our own choosing. Currently there are two configs provided: - 64bit-only, to build without any 32 bit boards at all - virt, even more minimal set for --disable-tcg builds Signed-off-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Cc: Paolo Bonzini Message-Id: <20210528163116.31902-1-alex.bennee@linaro.org> --- v2 - remove extraneous cc - dropped pathname from config - add virt.mak config - drop ZYNQMP from the 64bit only build - test -f the --with-devices-FOO file --- configure | 20 ++++++++++++++++++++ configs/aarch64-softmmu/64bit-only.mak | 10 ++++++++++ configs/aarch64-softmmu/virt-only.mak | 8 ++++++++ meson.build | 3 ++- 4 files changed, 40 insertions(+), 1 deletion(-) create mode 100644 configs/aarch64-softmmu/64bit-only.mak create mode 100644 configs/aarch64-softmmu/virt-only.mak diff --git a/configure b/configure index f0c8629dc6..5bf2f56ac6 100755 --- a/configure +++ b/configure @@ -920,6 +920,16 @@ for opt do ;; --without-default-devices) default_devices=3D"false" ;; + --with-devices-*[!a-zA-Z0-9_-]*=3D*) error_exit "Passed bad --with-devic= es-FOO option" + ;; + --with-devices-*) device_arch=3D${opt#--with-devices-}; device_arch=3D${= device_arch%%=3D*} + if test -f "$optarg"; then + device_archs=3D"$device_archs $device_arch" + eval "devices_${device_arch}=3D\$optarg" + else + error_exit "File $optarg does not exist" + fi + ;; --without-default-features) # processed above ;; --enable-gprof) gprof=3D"yes" @@ -1766,6 +1776,7 @@ Advanced options (experts only): --without-default-devices do not include any device that is not needed = to start the emulator (only use if you are includi= ng desired devices in default-configs/devices/) + --with-devices-ARCH=3DPATH override default-configs/devices with your ow= n file --enable-debug enable common debug build options --enable-sanitizers enable default sanitizers --enable-tsan enable thread sanitizer @@ -6343,6 +6354,15 @@ if test "$skip_meson" =3D no; then =20 echo "# Automatically generated by configure - do not modify" > $cross echo "[properties]" >> $cross + + # unroll any custom device configs + if test -n "$device_archs"; then + for a in $device_archs; do + eval "c=3D\$devices_${a}" + echo "${a}-softmmu =3D [ '$c' ]" >> $cross + done + fi + test -z "$cxx" && echo "link_language =3D 'c'" >> $cross echo "[built-in options]" >> $cross echo "c_args =3D [${CFLAGS:+$(meson_quote $CFLAGS)}]" >> $cross diff --git a/configs/aarch64-softmmu/64bit-only.mak b/configs/aarch64-softm= mu/64bit-only.mak new file mode 100644 index 0000000000..19638a56cf --- /dev/null +++ b/configs/aarch64-softmmu/64bit-only.mak @@ -0,0 +1,10 @@ +# +# A version of the config that only supports 64bits and their devices. +# This doesn't quite eliminate all 32 bit devices as some boards like +# "virt" support both. The CONFIG_XLNX_ZYNQMP_ARM isn't included as it +# also requires 32 bit support for the R5s +# + +CONFIG_ARM_VIRT=3Dy +CONFIG_XLNX_VERSAL=3Dy +CONFIG_SBSA_REF=3Dy diff --git a/configs/aarch64-softmmu/virt-only.mak b/configs/aarch64-softmm= u/virt-only.mak new file mode 100644 index 0000000000..cadacf3e89 --- /dev/null +++ b/configs/aarch64-softmmu/virt-only.mak @@ -0,0 +1,8 @@ +# +# A version of the config that only supports virtual machines. This is +# intended to be combined with options like --disable-tcg for a +# minimal build supporting only machines we can virtualise with a +# hypervisor. +# + +CONFIG_ARM_VIRT=3Dy diff --git a/meson.build b/meson.build index 09c7809d6b..9d25906219 100644 --- a/meson.build +++ b/meson.build @@ -1350,9 +1350,10 @@ foreach target : target_dirs configuration: config_targe= t_data)} =20 if target.endswith('-softmmu') + config_input =3D meson.get_external_property(target, 'default-configs/= devices' / target + '.mak') config_devices_mak =3D target + '-config-devices.mak' config_devices_mak =3D configure_file( - input: ['default-configs/devices' / target + '.mak', 'Kconfig'], + input: [config_input, 'Kconfig'], output: config_devices_mak, depfile: config_devices_mak + '.d', capture: true, --=20 2.20.1 From nobody Fri Apr 26 12:00:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1622824950; cv=none; d=zohomail.com; s=zohoarc; b=bY8mjaqVMkui/gjH408v/gPDaM2Yh4b8+tj3OFDX/bg98yNSCDWhn5bZ8iQgBAZ4zugFLNi7VUKDiRxDc+/c7XRAAImfYLZmBZYmX2hX6upuFgqVPlT7+5jSk3gl0qWBbqNI5ZBQhshOTQFsCSZz+l6GKNzQv73sKnQzG1vo60g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622824950; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oBDOyQH7E7gFoIfvmNRWV3L6dZVZeclFGF8pX/YLgLo=; b=M1mfgk/bPS+2VhyYbnTyrVgqCNM6rdUe6cUzkL+gI2hbV/bAHbENxHhgvY4DQQUSAVcyO7N1Na0+Vy1wLy5OpEmnDGptuhPAoHjdmG4xj6XV7UN+165LI7hz2UVTITLGxOgmj6i2VNs1T0NNi2pUKgeluIrMHvL/2NOhpOp4OZA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622824950072551.1810429073099; Fri, 4 Jun 2021 09:42:30 -0700 (PDT) Received: from localhost ([::1]:57974 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lpCtx-0001au-09 for importer@patchew.org; Fri, 04 Jun 2021 12:42:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52160) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lpCRa-0003U7-5R for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:13:10 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:43624) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lpCRP-0003t0-1v for qemu-devel@nongnu.org; Fri, 04 Jun 2021 12:13:09 -0400 Received: by mail-wr1-x431.google.com with SMTP id u7so4415019wrs.10 for ; Fri, 04 Jun 2021 09:12:57 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id g17sm2392881wrp.61.2021.06.04.09.12.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 09:12:53 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id DEA8720026; Fri, 4 Jun 2021 16:53:24 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oBDOyQH7E7gFoIfvmNRWV3L6dZVZeclFGF8pX/YLgLo=; b=VJPJiOBLcu5S27efU17cDZylFxY1kO5tqe1r4Uf8ak294k8DwnHJTNLOpktsYVTbHm VCypjXUwxAK6cl5SpUNtKab9Xigh5XP39gXP5l6dIQekKBmaOVe0GnluaqsKc7OsfK+9 Rp3ausL/J4WK3CsME5d7us7GZylLYVDVH7dWk9REhLRkmEZknUTWcfe84Q2FnEaQdfXL AHNW5eTV/3uwWsyxECVRMu+Rr6w5n00kV9b473SbJCBiX6O+SgmBegsvDNdZh7m/4etX GBOSj2dEAwNZbq1VwkR2bP+8y7lDwJAJkOiS+pdjL0rYM1q8+zB6aCwinUvuFy5ePyWq w+cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oBDOyQH7E7gFoIfvmNRWV3L6dZVZeclFGF8pX/YLgLo=; b=Okbt/zNTQ9WCvoWEth2ai2EBhK/C1ybZoSSKmXBeBzDZ+9Z1nuaSwcYKubHnePmE4j 5RE3A6uERfmBf0WeNpfSVBXMXWisJUjQnc8TVhVMZ5pDJQuYlMzy/Am/5R30yhQ49j4e Q5FNAGjzLHav/M3eLL2jWoNQxBPY6ET23qcFIkpALRbMQPkvDx5tPL00zbm1oI2MazJG UaqOXueRS3bx2S372xFYFs81iS6DxgXohAo/t2eMI4qfVcn0P+nq83ROsiQhvb4aOi4d duO83RAQXSD4NxnWlsMDUGMi+RxMadxu8NjbSXEVzmM8D0aMhXG1JqGfYOhT3RBJlVAd DNOA== X-Gm-Message-State: AOAM533LoBRxTassaKr8qiXA0Y+sBwQ/LE7Umt62aeE/W4Brq6Q1RoV4 D26+AocQOGDmC1Cl/mAuRRsWSA== X-Google-Smtp-Source: ABdhPJwcmnKIDEaOAX4pSQR4RVWxCHOcphV/hF/DJg7mGiwNqRBwfi2i8zyL68vFlLUf5as9d8YuNg== X-Received: by 2002:adf:ee50:: with SMTP id w16mr4658027wro.187.1622823177020; Fri, 04 Jun 2021 09:12:57 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Subject: [PATCH v16 99/99] gitlab: defend the new stripped down arm64 configs Date: Fri, 4 Jun 2021 16:53:12 +0100 Message-Id: <20210604155312.15902-100-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210604155312.15902-1-alex.bennee@linaro.org> References: <20210604155312.15902-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Wainer dos Santos Moschetta , Willian Rampazzo , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) We can now build a KVM only aarch64-softmmu image which we need to cross build. We can also build a version that only supports a limited set of 64 bit images. Signed-off-by: Alex Benn=C3=A9e --- .gitlab-ci.d/buildtest.yml | 10 ++++++++++ .gitlab-ci.d/crossbuilds.yml | 9 +++++++++ 2 files changed, 19 insertions(+) diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml index b72c57e4df..a48e723efe 100644 --- a/.gitlab-ci.d/buildtest.yml +++ b/.gitlab-ci.d/buildtest.yml @@ -645,6 +645,16 @@ build-without-default-features: --target-list-exclude=3Darm-softmmu,i386-softmmu,mipsel-softmmu,mi= ps64-softmmu,ppc-softmmu MAKE_CHECK_ARGS: check-unit =20 +build-64bit-only-aarch64-softmmu: + extends: .native_build_job_template + needs: + job: amd64-debian-container + variables: + IMAGE: debian-amd64 + TARGETS: aarch64-softmmu + CONFIGURE_ARGS: --with-devices-aarch64=3D../configs/aarch64-softmmu/64= bit-only.mak + MAKE_CHECK_ARGS: check + build-libvhost-user: stage: build image: $CI_REGISTRY_IMAGE/qemu/fedora:latest diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml index 6b3865c9e8..a118aa3052 100644 --- a/.gitlab-ci.d/crossbuilds.yml +++ b/.gitlab-ci.d/crossbuilds.yml @@ -36,6 +36,15 @@ cross-arm64-system: variables: IMAGE: debian-arm64-cross =20 +cross-arm64-kvm-only-system: + extends: .cross_accel_build_job + needs: + job: arm64-debian-cross-container + variables: + IMAGE: debian-arm64-cross + ACCEL: kvm + EXTRA_CONFIGURE_OPTS: --disable-tcg + cross-arm64-user: extends: .cross_user_build_job needs: --=20 2.20.1