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[83.57.168.235]) by smtp.gmail.com with ESMTPSA id r12sm1371078edv.82.2021.06.03.02.03.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 02:03:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O9+spEcANDKYx8HcPdHHRJ407zGYpuqHR7eNVlkhEK0=; b=P+GQzUDBJKchMe+VJFjm2byIVSgkNkT+dQHKhqtqG1WVw9NJCJ3jPz+OYPWU0QnrqJ 7lxK1rHTStON3JWralPF/3pDicxZRnORwl+Eg5Of8danL5m+QqQU50yVTjGxxXrK0WF+ MED/44icC6RiRI11Sl5mRoJYTuR4MOaEb4V+Uws5NZARR1yHcxlh194MlL4QDbR8Vz8L zKglPiY2c+zZ68u1DtYOqeOt67ff2uJA8DDaGiYn9mnsZDvE2Ece+H50MBsBgn3MEa+Q zLdTUcGOcfZK6HVC0WPfdbFXC+h91dzIUqBWehy1Sh465R1dJrgpmWIrA4I8/d6DbXfA o4Ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=O9+spEcANDKYx8HcPdHHRJ407zGYpuqHR7eNVlkhEK0=; b=Mt7Mn1+FYkqOvlXdaEHsWMliPaf8/okVcBfVwgZh3fdeBknB/wixerGz/f1SDsmzpC o5Ao+q0CnUuuaoaxZ0SUERHjOo/nvMU8Dovk63EaBIfvH8BDHweG4wunubwnV7ORRz4i ndZExbcL7qepFPmZIiDTIsaJLY5PYHJnfqVw0GQK4gUv0gQe3SGud75oGMXDwyHDudvU BLA5/qjUsa0qg9Xwygf+MqoZsIg+L4EFXQ396l+fiWVjfDm223f8YIiQwGeEo3tuvNcX wDnc1VkquASljByqgp7uIXjacfIfwI8+mh0wA4x+oF4GM0w1RL/kTsPg8kioRmRVROUC 61Eg== X-Gm-Message-State: AOAM531rf5wU+VxXDkLWLRpnBbvAMA2AGFKDgE5IbfzDPeyZOi4sJb7P IxcwA2s+pZcB7c+Fk0fMfB0= X-Google-Smtp-Source: ABdhPJwEhVO/WNqBx4Wb2gI5thEygerLdYOLoPG9K7p1SprDxZcbEbt+HkrK3HYqgMpZn1dQ1QNJqg== X-Received: by 2002:a17:906:22c6:: with SMTP id q6mr38534524eja.275.1622711022264; Thu, 03 Jun 2021 02:03:42 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , "Edgar E. Iglesias" , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 6/6] target/microblaze: Set OPB bits in tlb_fill, not in transaction_failed Date: Thu, 3 Jun 2021 11:03:10 +0200 Message-Id: <20210603090310.2749892-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210603090310.2749892-1-f4bug@amsat.org> References: <20210603090310.2749892-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Per the 'MicroBlaze Processor Reference Guide' UG081 (v9.0), "Hardware Exceptions" chapter: Exception Causes: * Instruction Bus Exception The instruction On-chip Peripheral Bus exception is caused by an active error signal from the slave (IOPB_errAck) or timeout signal from the arbiter (IOPB_timeout). * Data Bus Exception The data On-chip Peripheral Bus exception is caused by an active error signal from the slave (DOPB_errAck) or timeout signal from the arbiter (DOPB_timeout). the table 1-24 (Processor Version Register 2): * IOPBEXC: Generate exception for IOPB error * DOPBEXC: Generate exception for DOPB error and the table 2-12 (MPD Parameters): * C_IOPB_BUS_EXCEPTION Enable exception handling for IOPB bus error * C_DOPB_BUS_EXCEPTION Enable exception handling for DOPB bus error So if PVR2.[ID]OPBEXC feature is disabled, no exception will be generated. Thus we can not get to the transaction_failed() handler. The ESR bits have to be set in tlb_fill(). However we never implemented the MMU check whether the address belong to the On-chip Peripheral Bus interface, so simply add a stub for it, warning the feature is not implemented. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/microblaze/helper.c | 19 +++++++++++++++++++ target/microblaze/op_helper.c | 13 ------------- 2 files changed, 19 insertions(+), 13 deletions(-) diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index d537f300ca6..60e62bc0710 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -56,6 +56,18 @@ static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu, } } =20 +/* On-chip Peripheral Bus (OPB) interface */ +static bool mb_cpu_address_is_opb(MicroBlazeCPU *cpu, + vaddr address, unsigned size) +{ + if (cpu->cfg.iopb_bus_exception || cpu->cfg.dopb_bus_exception) { + /* TODO */ + warn_report_once("On-chip Peripheral Bus (OPB) interface " + "feature not implemented."); + } + return false; +} + bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -119,6 +131,13 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, default: abort(); } + if (mb_cpu_address_is_opb(cpu, address, size)) { + if (access_type =3D=3D MMU_INST_FETCH) { + env->esr =3D ESR_EC_INSN_BUS; + } else { + env->esr =3D ESR_EC_DATA_BUS; + } + } =20 if (cs->exception_index =3D=3D EXCP_MMU) { cpu_abort(cs, "recursive faults\n"); diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 1048e656e27..171c4cf99a0 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -123,19 +123,6 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr ph= ysaddr, vaddr addr, (access_type =3D=3D MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_= STORE")); =20 assert(env->msr & MSR_EE); - - if (access_type =3D=3D MMU_INST_FETCH) { - if (!cpu->cfg.iopb_bus_exception) { - return; - } - env->esr =3D ESR_EC_INSN_BUS; - } else { - if (!cpu->cfg.dopb_bus_exception) { - return; - } - env->esr =3D ESR_EC_DATA_BUS; - } - env->ear =3D addr; cs->exception_index =3D EXCP_HW_EXCP; cpu_loop_exit_restore(cs, retaddr); --=20 2.26.3