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[83.57.168.235]) by smtp.gmail.com with ESMTPSA id t14sm1419253edv.27.2021.06.03.02.03.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 02:03:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=o0IJ99GBNBgLTCqp2mtuSzLlVDmKBunZStjd7bCnLMU=; b=Umd0SHxEJxu7y1eAGW3T4MiU1jZcRufZwB/BjqG27nmQ0gQPmABCWmC5TPyUFyrHAt vcnZrhAdDcWOTby+el7frCZ7PwJrxh0Uc2tJfqCvF0RLAClKqj8bn5igqdAq5MXXrTJq IalDI8XH4VI6rlU1Up8MrDSthXhpl5bfy2xZRW/qbcbxcPwNeDrwxWaoGKNbqdOZtQVL GZbp9sSENbEitExy4qYcUuL6+wDLWLgufNXX1JbP+GbDDJFKAm8KIZE8r2nnh6+oj1i3 YHdq8XxMTq7zzmPyg37OU8KTd2tamtWYu/xoKEMYnnuyJbJtexHAitdOfC6kMlGxwvu5 h/Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=o0IJ99GBNBgLTCqp2mtuSzLlVDmKBunZStjd7bCnLMU=; b=GaPEHsrAftpxJar3fJeX2/57ChddD6748nBgfioyc3J8VZpqOKpsFe0G4NVHJtywOi IoMSgv5HtQOPkj/OeT3yFdPkzarg7bqkxZrKKmxLaEhWEp9ooPkpS+tnSSQGH4zrabeD SA8vF4EH9pjwDxjGM6o74bgVSNwgwS4AyLTl8xfkGljtcbvYmT94TZ+cZGjzfhb/SSzt DhO62bc2beTAVEyWPLKqdgAaZd1QWjgs/9UR7zTPIPgqP5V8PBU2IJGyxt3uprtukwl1 rotwzof11hHkA5Yp6f1A9Cp9FI9RKxQJ6tMxfAFKOUqLd47dB8Tvu1beTY9Rn/ifpjas lzeg== X-Gm-Message-State: AOAM531gn8h3Ba5Ca0IPsC2UVPtkD1KQXqX6ABb/66pz6dlAXU4aTh7E kZT5WrM6aJs1rvT2ybKsjgc= X-Google-Smtp-Source: ABdhPJxK2MFlFXwzQspEnvi25vfQrcPApLMakZQZRv5Bj022TCXEPYReDUW65GKIGUkCmLTPfs6OQQ== X-Received: by 2002:a05:6402:548:: with SMTP id i8mr6356535edx.344.1622711002636; Thu, 03 Jun 2021 02:03:22 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , "Edgar E. Iglesias" , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/6] target/microblaze: Extract FPU helpers to fpu_helper.c Date: Thu, 3 Jun 2021 11:03:06 +0200 Message-Id: <20210603090310.2749892-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210603090310.2749892-1-f4bug@amsat.org> References: <20210603090310.2749892-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Extract FPU helpers to their own file: fpu_helper.c, so it is easier to focus on the generic helpers in op_helper.c. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- target/microblaze/fpu_helper.c | 308 +++++++++++++++++++++++++++++++++ target/microblaze/op_helper.c | 287 +----------------------------- target/microblaze/meson.build | 1 + 3 files changed, 310 insertions(+), 286 deletions(-) create mode 100644 target/microblaze/fpu_helper.c diff --git a/target/microblaze/fpu_helper.c b/target/microblaze/fpu_helper.c new file mode 100644 index 00000000000..ce729947079 --- /dev/null +++ b/target/microblaze/fpu_helper.c @@ -0,0 +1,308 @@ +/* + * Microblaze FPU helper routines. + * + * Copyright (c) 2009 Edgar E. Iglesias . + * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" +#include "fpu/softfloat.h" + +static bool check_divz(CPUMBState *env, uint32_t a, uint32_t b, uintptr_t = ra) +{ + if (unlikely(b =3D=3D 0)) { + env->msr |=3D MSR_DZ; + + if ((env->msr & MSR_EE) && + env_archcpu(env)->cfg.div_zero_exception) { + CPUState *cs =3D env_cpu(env); + + env->esr =3D ESR_EC_DIVZERO; + cs->exception_index =3D EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, ra); + } + return false; + } + return true; +} + +uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b) +{ + if (!check_divz(env, a, b, GETPC())) { + return 0; + } + return (int32_t)a / (int32_t)b; +} + +uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b) +{ + if (!check_divz(env, a, b, GETPC())) { + return 0; + } + return a / b; +} + +/* raise FPU exception. */ +static void raise_fpu_exception(CPUMBState *env, uintptr_t ra) +{ + CPUState *cs =3D env_cpu(env); + + env->esr =3D ESR_EC_FPU; + cs->exception_index =3D EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, ra); +} + +static void update_fpu_flags(CPUMBState *env, int flags, uintptr_t ra) +{ + int raise =3D 0; + + if (flags & float_flag_invalid) { + env->fsr |=3D FSR_IO; + raise =3D 1; + } + if (flags & float_flag_divbyzero) { + env->fsr |=3D FSR_DZ; + raise =3D 1; + } + if (flags & float_flag_overflow) { + env->fsr |=3D FSR_OF; + raise =3D 1; + } + if (flags & float_flag_underflow) { + env->fsr |=3D FSR_UF; + raise =3D 1; + } + if (raise + && (env_archcpu(env)->cfg.pvr_regs[2] & PVR2_FPU_EXC_MASK) + && (env->msr & MSR_EE)) { + raise_fpu_exception(env, ra); + } +} + +uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fd, fa, fb; + int flags; + + set_float_exception_flags(0, &env->fp_status); + fa.l =3D a; + fb.l =3D b; + fd.f =3D float32_add(fa.f, fb.f, &env->fp_status); + + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags, GETPC()); + return fd.l; +} + +uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fd, fa, fb; + int flags; + + set_float_exception_flags(0, &env->fp_status); + fa.l =3D a; + fb.l =3D b; + fd.f =3D float32_sub(fb.f, fa.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags, GETPC()); + return fd.l; +} + +uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fd, fa, fb; + int flags; + + set_float_exception_flags(0, &env->fp_status); + fa.l =3D a; + fb.l =3D b; + fd.f =3D float32_mul(fa.f, fb.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags, GETPC()); + + return fd.l; +} + +uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fd, fa, fb; + int flags; + + set_float_exception_flags(0, &env->fp_status); + fa.l =3D a; + fb.l =3D b; + fd.f =3D float32_div(fb.f, fa.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags, GETPC()); + + return fd.l; +} + +uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fa, fb; + uint32_t r =3D 0; + + fa.l =3D a; + fb.l =3D b; + + if (float32_is_signaling_nan(fa.f, &env->fp_status) || + float32_is_signaling_nan(fb.f, &env->fp_status)) { + update_fpu_flags(env, float_flag_invalid, GETPC()); + r =3D 1; + } + + if (float32_is_quiet_nan(fa.f, &env->fp_status) || + float32_is_quiet_nan(fb.f, &env->fp_status)) { + r =3D 1; + } + + return r; +} + +uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fa, fb; + int r; + int flags; + + set_float_exception_flags(0, &env->fp_status); + fa.l =3D a; + fb.l =3D b; + r =3D float32_lt(fb.f, fa.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); + + return r; +} + +uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fa, fb; + int flags; + int r; + + set_float_exception_flags(0, &env->fp_status); + fa.l =3D a; + fb.l =3D b; + r =3D float32_eq_quiet(fa.f, fb.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); + + return r; +} + +uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fa, fb; + int flags; + int r; + + fa.l =3D a; + fb.l =3D b; + set_float_exception_flags(0, &env->fp_status); + r =3D float32_le(fa.f, fb.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); + + + return r; +} + +uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fa, fb; + int flags, r; + + fa.l =3D a; + fb.l =3D b; + set_float_exception_flags(0, &env->fp_status); + r =3D float32_lt(fa.f, fb.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); + return r; +} + +uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fa, fb; + int flags, r; + + fa.l =3D a; + fb.l =3D b; + set_float_exception_flags(0, &env->fp_status); + r =3D !float32_eq_quiet(fa.f, fb.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); + + return r; +} + +uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fa, fb; + int flags, r; + + fa.l =3D a; + fb.l =3D b; + set_float_exception_flags(0, &env->fp_status); + r =3D !float32_lt(fa.f, fb.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); + + return r; +} + +uint32_t helper_flt(CPUMBState *env, uint32_t a) +{ + CPU_FloatU fd, fa; + + fa.l =3D a; + fd.f =3D int32_to_float32(fa.l, &env->fp_status); + return fd.l; +} + +uint32_t helper_fint(CPUMBState *env, uint32_t a) +{ + CPU_FloatU fa; + uint32_t r; + int flags; + + set_float_exception_flags(0, &env->fp_status); + fa.l =3D a; + r =3D float32_to_int32(fa.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags, GETPC()); + + return r; +} + +uint32_t helper_fsqrt(CPUMBState *env, uint32_t a) +{ + CPU_FloatU fd, fa; + int flags; + + set_float_exception_flags(0, &env->fp_status); + fa.l =3D a; + fd.l =3D float32_sqrt(fa.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags, GETPC()); + + return fd.l; +} diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 58d633584d3..8d20522ee88 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -21,10 +21,8 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "qemu/host-utils.h" +#include "qemu/log.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" -#include "fpu/softfloat.h" =20 void helper_put(uint32_t id, uint32_t ctrl, uint32_t data) { @@ -69,289 +67,6 @@ void helper_raise_exception(CPUMBState *env, uint32_t i= ndex) cpu_loop_exit(cs); } =20 -static bool check_divz(CPUMBState *env, uint32_t a, uint32_t b, uintptr_t = ra) -{ - if (unlikely(b =3D=3D 0)) { - env->msr |=3D MSR_DZ; - - if ((env->msr & MSR_EE) && - env_archcpu(env)->cfg.div_zero_exception) { - CPUState *cs =3D env_cpu(env); - - env->esr =3D ESR_EC_DIVZERO; - cs->exception_index =3D EXCP_HW_EXCP; - cpu_loop_exit_restore(cs, ra); - } - return false; - } - return true; -} - -uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b) -{ - if (!check_divz(env, a, b, GETPC())) { - return 0; - } - return (int32_t)a / (int32_t)b; -} - -uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b) -{ - if (!check_divz(env, a, b, GETPC())) { - return 0; - } - return a / b; -} - -/* raise FPU exception. */ -static void raise_fpu_exception(CPUMBState *env, uintptr_t ra) -{ - CPUState *cs =3D env_cpu(env); - - env->esr =3D ESR_EC_FPU; - cs->exception_index =3D EXCP_HW_EXCP; - cpu_loop_exit_restore(cs, ra); -} - -static void update_fpu_flags(CPUMBState *env, int flags, uintptr_t ra) -{ - int raise =3D 0; - - if (flags & float_flag_invalid) { - env->fsr |=3D FSR_IO; - raise =3D 1; - } - if (flags & float_flag_divbyzero) { - env->fsr |=3D FSR_DZ; - raise =3D 1; - } - if (flags & float_flag_overflow) { - env->fsr |=3D FSR_OF; - raise =3D 1; - } - if (flags & float_flag_underflow) { - env->fsr |=3D FSR_UF; - raise =3D 1; - } - if (raise - && (env_archcpu(env)->cfg.pvr_regs[2] & PVR2_FPU_EXC_MASK) - && (env->msr & MSR_EE)) { - raise_fpu_exception(env, ra); - } -} - -uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fd, fa, fb; - int flags; - - set_float_exception_flags(0, &env->fp_status); - fa.l =3D a; - fb.l =3D b; - fd.f =3D float32_add(fa.f, fb.f, &env->fp_status); - - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags, GETPC()); - return fd.l; -} - -uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fd, fa, fb; - int flags; - - set_float_exception_flags(0, &env->fp_status); - fa.l =3D a; - fb.l =3D b; - fd.f =3D float32_sub(fb.f, fa.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags, GETPC()); - return fd.l; -} - -uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fd, fa, fb; - int flags; - - set_float_exception_flags(0, &env->fp_status); - fa.l =3D a; - fb.l =3D b; - fd.f =3D float32_mul(fa.f, fb.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags, GETPC()); - - return fd.l; -} - -uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fd, fa, fb; - int flags; - - set_float_exception_flags(0, &env->fp_status); - fa.l =3D a; - fb.l =3D b; - fd.f =3D float32_div(fb.f, fa.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags, GETPC()); - - return fd.l; -} - -uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fa, fb; - uint32_t r =3D 0; - - fa.l =3D a; - fb.l =3D b; - - if (float32_is_signaling_nan(fa.f, &env->fp_status) || - float32_is_signaling_nan(fb.f, &env->fp_status)) { - update_fpu_flags(env, float_flag_invalid, GETPC()); - r =3D 1; - } - - if (float32_is_quiet_nan(fa.f, &env->fp_status) || - float32_is_quiet_nan(fb.f, &env->fp_status)) { - r =3D 1; - } - - return r; -} - -uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fa, fb; - int r; - int flags; - - set_float_exception_flags(0, &env->fp_status); - fa.l =3D a; - fb.l =3D b; - r =3D float32_lt(fb.f, fa.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid, GETPC()); - - return r; -} - -uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fa, fb; - int flags; - int r; - - set_float_exception_flags(0, &env->fp_status); - fa.l =3D a; - fb.l =3D b; - r =3D float32_eq_quiet(fa.f, fb.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid, GETPC()); - - return r; -} - -uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fa, fb; - int flags; - int r; - - fa.l =3D a; - fb.l =3D b; - set_float_exception_flags(0, &env->fp_status); - r =3D float32_le(fa.f, fb.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid, GETPC()); - - - return r; -} - -uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fa, fb; - int flags, r; - - fa.l =3D a; - fb.l =3D b; - set_float_exception_flags(0, &env->fp_status); - r =3D float32_lt(fa.f, fb.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid, GETPC()); - return r; -} - -uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fa, fb; - int flags, r; - - fa.l =3D a; - fb.l =3D b; - set_float_exception_flags(0, &env->fp_status); - r =3D !float32_eq_quiet(fa.f, fb.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid, GETPC()); - - return r; -} - -uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fa, fb; - int flags, r; - - fa.l =3D a; - fb.l =3D b; - set_float_exception_flags(0, &env->fp_status); - r =3D !float32_lt(fa.f, fb.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid, GETPC()); - - return r; -} - -uint32_t helper_flt(CPUMBState *env, uint32_t a) -{ - CPU_FloatU fd, fa; - - fa.l =3D a; - fd.f =3D int32_to_float32(fa.l, &env->fp_status); - return fd.l; -} - -uint32_t helper_fint(CPUMBState *env, uint32_t a) -{ - CPU_FloatU fa; - uint32_t r; - int flags; - - set_float_exception_flags(0, &env->fp_status); - fa.l =3D a; - r =3D float32_to_int32(fa.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags, GETPC()); - - return r; -} - -uint32_t helper_fsqrt(CPUMBState *env, uint32_t a) -{ - CPU_FloatU fd, fa; - int flags; - - set_float_exception_flags(0, &env->fp_status); - fa.l =3D a; - fd.l =3D float32_sqrt(fa.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags, GETPC()); - - return fd.l; -} - uint32_t helper_pcmpbf(uint32_t a, uint32_t b) { unsigned int i; diff --git a/target/microblaze/meson.build b/target/microblaze/meson.build index 05ee0ec1635..0a5e46027af 100644 --- a/target/microblaze/meson.build +++ b/target/microblaze/meson.build @@ -4,6 +4,7 @@ microblaze_ss.add(gen) microblaze_ss.add(files( 'cpu.c', + 'fpu_helper.c', 'gdbstub.c', 'helper.c', 'op_helper.c', --=20 2.26.3