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[83.57.168.235]) by smtp.gmail.com with ESMTPSA id z19sm491776edr.77.2021.06.03.02.03.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 02:03:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ycDqdBNMfE6sy0aNiEZr8G7a3sAQ4DzhtUJazHFG448=; b=Gb1x1GerQQu/ps4AXoeAG0KMSGDYzaSDzSNDL7UCCzwonF03v50XjR3qAczlHcK5/B GNaXbKvfKw3CXgKa6CSouH/FSFQclrEH50LobGdXLNOeKxE/xV1TSHWoCcQqwQ1nzNOe ZCYqdNhI7jmt7zLxF6tc9VS6/A6pujkOU75JzPxLhYb9hNoh6rqG+Zj1TmI80DnVsy9/ qKsrLtSzyLykBfI10cw2pQWoqMKHRm0DSzoCqFyIcTxa0/oHROkPs5TIqsh54B7Q/tMd vO29QNkdFNgVFS+v59SbS3UYSTKdyijdarIK8ZNbipsuIjpyRXkcbIlamvXibtvW4Mws qPdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ycDqdBNMfE6sy0aNiEZr8G7a3sAQ4DzhtUJazHFG448=; b=LP4Y55A0iz9HG4LILS4oZoZdeeSCOBtvjIy8CJ7/E76qbjVRPdvF5NO0ZXj0ipp+ql N4NLeBZzM6RHKdksfKQPDtX9n+iO+F59Cxx3WTnXW7p3F3G9PI87gSnF6k8PIInepnjs 4XPJCaswSBykklxujynKJ4HboaklkXuUK2rcAVGxt/PuIuLPmksyhdBpFcSKFIX7xg9f xJ85H0Cz0s92AhUfdVSMKifgvhycwdK9S7BICW6ZjfgknQykX72BH1ApCVayjbUr+YvM l3xFIGXYBXr7dIA9SV44l7N7L8Pc5j7hn+0w7QC8Ckh5WG+wvU+OVZSJUDL4+kN9YZ66 ni6g== X-Gm-Message-State: AOAM533FlJWcirdcg7h/hHPmKA21CqEvzcnH6UNnLrjGwOLykvqqwRu6 jzogXquDqNakW2GLA7wl1AnxK1v8JqS0Sg== X-Google-Smtp-Source: ABdhPJwso4LzkdxtufJAanXZwFgGzbjUIjTPycJPJsabexUSQrZuEUzbFauLC0IUYu3bjJdsvtfSSg== X-Received: by 2002:a17:906:180a:: with SMTP id v10mr5955483eje.22.1622710997629; Thu, 03 Jun 2021 02:03:17 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , "Edgar E. Iglesias" , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 1/6] target/microblaze: Use the IEC binary prefix definitions Date: Thu, 3 Jun 2021 11:03:05 +0200 Message-Id: <20210603090310.2749892-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210603090310.2749892-1-f4bug@amsat.org> References: <20210603090310.2749892-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) IEC binary prefixes ease code review: the unit is explicit. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson --- target/microblaze/mmu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c index cc40f275eaf..1481e2769f1 100644 --- a/target/microblaze/mmu.c +++ b/target/microblaze/mmu.c @@ -19,14 +19,15 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/units.h" #include "cpu.h" #include "exec/exec-all.h" =20 static unsigned int tlb_decode_size(unsigned int f) { static const unsigned int sizes[] =3D { - 1 * 1024, 4 * 1024, 16 * 1024, 64 * 1024, 256 * 1024, - 1 * 1024 * 1024, 4 * 1024 * 1024, 16 * 1024 * 1024 + 1 * KiB, 4 * KiB, 16 * KiB, 64 * KiB, 256 * KiB, + 1 * MiB, 4 * MiB, 16 * MiB }; assert(f < ARRAY_SIZE(sizes)); return sizes[f]; --=20 2.26.3 From nobody Mon Feb 9 07:11:23 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.45 as permitted sender) client-ip=209.85.208.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1622711004; cv=none; d=zohomail.com; s=zohoarc; b=XP1u2NwFscrqcHkDDMjwxBKSVkzyNkevf0vvuYMcq0FboMH5BzmdxYtoajqloooBBFt1YYyMZB2q4G3zp4cPsxUDetofRznq8QpCq0P96NvBDBAoCmRmcUAsglzYkteenbScRw8XeXDLtjyIB4qVZmZy348Gqt747gEJA3j/YYo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622711004; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=o0IJ99GBNBgLTCqp2mtuSzLlVDmKBunZStjd7bCnLMU=; b=ZP7ENea6f0hvPMTrtqFHEf2+7dRQByiWs3Tp2+WJErIjsro+8gnbYHGHCxXrZwVY1GWvaxECE6KOTI0uLdTk21zejuQAwaf0EEPIjYcsFVQj73/Jv+f7bNwfzyi6PxkrZMfz8UNsGZcPjNtbti9LXlGzYZMv7lYqtQNgPhUK/Ic= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) by mx.zohomail.com with SMTPS id 162271100449463.544204668869725; Thu, 3 Jun 2021 02:03:24 -0700 (PDT) Received: by mail-ed1-f45.google.com with SMTP id o5so6238683edc.5 for ; Thu, 03 Jun 2021 02:03:23 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (235.red-83-57-168.dynamicip.rima-tde.net. [83.57.168.235]) by smtp.gmail.com with ESMTPSA id t14sm1419253edv.27.2021.06.03.02.03.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 02:03:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=o0IJ99GBNBgLTCqp2mtuSzLlVDmKBunZStjd7bCnLMU=; b=Umd0SHxEJxu7y1eAGW3T4MiU1jZcRufZwB/BjqG27nmQ0gQPmABCWmC5TPyUFyrHAt vcnZrhAdDcWOTby+el7frCZ7PwJrxh0Uc2tJfqCvF0RLAClKqj8bn5igqdAq5MXXrTJq IalDI8XH4VI6rlU1Up8MrDSthXhpl5bfy2xZRW/qbcbxcPwNeDrwxWaoGKNbqdOZtQVL GZbp9sSENbEitExy4qYcUuL6+wDLWLgufNXX1JbP+GbDDJFKAm8KIZE8r2nnh6+oj1i3 YHdq8XxMTq7zzmPyg37OU8KTd2tamtWYu/xoKEMYnnuyJbJtexHAitdOfC6kMlGxwvu5 h/Dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=o0IJ99GBNBgLTCqp2mtuSzLlVDmKBunZStjd7bCnLMU=; b=GaPEHsrAftpxJar3fJeX2/57ChddD6748nBgfioyc3J8VZpqOKpsFe0G4NVHJtywOi IoMSgv5HtQOPkj/OeT3yFdPkzarg7bqkxZrKKmxLaEhWEp9ooPkpS+tnSSQGH4zrabeD SA8vF4EH9pjwDxjGM6o74bgVSNwgwS4AyLTl8xfkGljtcbvYmT94TZ+cZGjzfhb/SSzt DhO62bc2beTAVEyWPLKqdgAaZd1QWjgs/9UR7zTPIPgqP5V8PBU2IJGyxt3uprtukwl1 rotwzof11hHkA5Yp6f1A9Cp9FI9RKxQJ6tMxfAFKOUqLd47dB8Tvu1beTY9Rn/ifpjas lzeg== X-Gm-Message-State: AOAM531gn8h3Ba5Ca0IPsC2UVPtkD1KQXqX6ABb/66pz6dlAXU4aTh7E kZT5WrM6aJs1rvT2ybKsjgc= X-Google-Smtp-Source: ABdhPJxK2MFlFXwzQspEnvi25vfQrcPApLMakZQZRv5Bj022TCXEPYReDUW65GKIGUkCmLTPfs6OQQ== X-Received: by 2002:a05:6402:548:: with SMTP id i8mr6356535edx.344.1622711002636; Thu, 03 Jun 2021 02:03:22 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , "Edgar E. Iglesias" , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/6] target/microblaze: Extract FPU helpers to fpu_helper.c Date: Thu, 3 Jun 2021 11:03:06 +0200 Message-Id: <20210603090310.2749892-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210603090310.2749892-1-f4bug@amsat.org> References: <20210603090310.2749892-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Extract FPU helpers to their own file: fpu_helper.c, so it is easier to focus on the generic helpers in op_helper.c. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- target/microblaze/fpu_helper.c | 308 +++++++++++++++++++++++++++++++++ target/microblaze/op_helper.c | 287 +----------------------------- target/microblaze/meson.build | 1 + 3 files changed, 310 insertions(+), 286 deletions(-) create mode 100644 target/microblaze/fpu_helper.c diff --git a/target/microblaze/fpu_helper.c b/target/microblaze/fpu_helper.c new file mode 100644 index 00000000000..ce729947079 --- /dev/null +++ b/target/microblaze/fpu_helper.c @@ -0,0 +1,308 @@ +/* + * Microblaze FPU helper routines. + * + * Copyright (c) 2009 Edgar E. Iglesias . + * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" +#include "fpu/softfloat.h" + +static bool check_divz(CPUMBState *env, uint32_t a, uint32_t b, uintptr_t = ra) +{ + if (unlikely(b =3D=3D 0)) { + env->msr |=3D MSR_DZ; + + if ((env->msr & MSR_EE) && + env_archcpu(env)->cfg.div_zero_exception) { + CPUState *cs =3D env_cpu(env); + + env->esr =3D ESR_EC_DIVZERO; + cs->exception_index =3D EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, ra); + } + return false; + } + return true; +} + +uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b) +{ + if (!check_divz(env, a, b, GETPC())) { + return 0; + } + return (int32_t)a / (int32_t)b; +} + +uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b) +{ + if (!check_divz(env, a, b, GETPC())) { + return 0; + } + return a / b; +} + +/* raise FPU exception. */ +static void raise_fpu_exception(CPUMBState *env, uintptr_t ra) +{ + CPUState *cs =3D env_cpu(env); + + env->esr =3D ESR_EC_FPU; + cs->exception_index =3D EXCP_HW_EXCP; + cpu_loop_exit_restore(cs, ra); +} + +static void update_fpu_flags(CPUMBState *env, int flags, uintptr_t ra) +{ + int raise =3D 0; + + if (flags & float_flag_invalid) { + env->fsr |=3D FSR_IO; + raise =3D 1; + } + if (flags & float_flag_divbyzero) { + env->fsr |=3D FSR_DZ; + raise =3D 1; + } + if (flags & float_flag_overflow) { + env->fsr |=3D FSR_OF; + raise =3D 1; + } + if (flags & float_flag_underflow) { + env->fsr |=3D FSR_UF; + raise =3D 1; + } + if (raise + && (env_archcpu(env)->cfg.pvr_regs[2] & PVR2_FPU_EXC_MASK) + && (env->msr & MSR_EE)) { + raise_fpu_exception(env, ra); + } +} + +uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fd, fa, fb; + int flags; + + set_float_exception_flags(0, &env->fp_status); + fa.l =3D a; + fb.l =3D b; + fd.f =3D float32_add(fa.f, fb.f, &env->fp_status); + + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags, GETPC()); + return fd.l; +} + +uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fd, fa, fb; + int flags; + + set_float_exception_flags(0, &env->fp_status); + fa.l =3D a; + fb.l =3D b; + fd.f =3D float32_sub(fb.f, fa.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags, GETPC()); + return fd.l; +} + +uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fd, fa, fb; + int flags; + + set_float_exception_flags(0, &env->fp_status); + fa.l =3D a; + fb.l =3D b; + fd.f =3D float32_mul(fa.f, fb.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags, GETPC()); + + return fd.l; +} + +uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fd, fa, fb; + int flags; + + set_float_exception_flags(0, &env->fp_status); + fa.l =3D a; + fb.l =3D b; + fd.f =3D float32_div(fb.f, fa.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags, GETPC()); + + return fd.l; +} + +uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fa, fb; + uint32_t r =3D 0; + + fa.l =3D a; + fb.l =3D b; + + if (float32_is_signaling_nan(fa.f, &env->fp_status) || + float32_is_signaling_nan(fb.f, &env->fp_status)) { + update_fpu_flags(env, float_flag_invalid, GETPC()); + r =3D 1; + } + + if (float32_is_quiet_nan(fa.f, &env->fp_status) || + float32_is_quiet_nan(fb.f, &env->fp_status)) { + r =3D 1; + } + + return r; +} + +uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fa, fb; + int r; + int flags; + + set_float_exception_flags(0, &env->fp_status); + fa.l =3D a; + fb.l =3D b; + r =3D float32_lt(fb.f, fa.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); + + return r; +} + +uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fa, fb; + int flags; + int r; + + set_float_exception_flags(0, &env->fp_status); + fa.l =3D a; + fb.l =3D b; + r =3D float32_eq_quiet(fa.f, fb.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); + + return r; +} + +uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fa, fb; + int flags; + int r; + + fa.l =3D a; + fb.l =3D b; + set_float_exception_flags(0, &env->fp_status); + r =3D float32_le(fa.f, fb.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); + + + return r; +} + +uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fa, fb; + int flags, r; + + fa.l =3D a; + fb.l =3D b; + set_float_exception_flags(0, &env->fp_status); + r =3D float32_lt(fa.f, fb.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); + return r; +} + +uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fa, fb; + int flags, r; + + fa.l =3D a; + fb.l =3D b; + set_float_exception_flags(0, &env->fp_status); + r =3D !float32_eq_quiet(fa.f, fb.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); + + return r; +} + +uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b) +{ + CPU_FloatU fa, fb; + int flags, r; + + fa.l =3D a; + fb.l =3D b; + set_float_exception_flags(0, &env->fp_status); + r =3D !float32_lt(fa.f, fb.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags & float_flag_invalid, GETPC()); + + return r; +} + +uint32_t helper_flt(CPUMBState *env, uint32_t a) +{ + CPU_FloatU fd, fa; + + fa.l =3D a; + fd.f =3D int32_to_float32(fa.l, &env->fp_status); + return fd.l; +} + +uint32_t helper_fint(CPUMBState *env, uint32_t a) +{ + CPU_FloatU fa; + uint32_t r; + int flags; + + set_float_exception_flags(0, &env->fp_status); + fa.l =3D a; + r =3D float32_to_int32(fa.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags, GETPC()); + + return r; +} + +uint32_t helper_fsqrt(CPUMBState *env, uint32_t a) +{ + CPU_FloatU fd, fa; + int flags; + + set_float_exception_flags(0, &env->fp_status); + fa.l =3D a; + fd.l =3D float32_sqrt(fa.f, &env->fp_status); + flags =3D get_float_exception_flags(&env->fp_status); + update_fpu_flags(env, flags, GETPC()); + + return fd.l; +} diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 58d633584d3..8d20522ee88 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -21,10 +21,8 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "qemu/host-utils.h" +#include "qemu/log.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" -#include "fpu/softfloat.h" =20 void helper_put(uint32_t id, uint32_t ctrl, uint32_t data) { @@ -69,289 +67,6 @@ void helper_raise_exception(CPUMBState *env, uint32_t i= ndex) cpu_loop_exit(cs); } =20 -static bool check_divz(CPUMBState *env, uint32_t a, uint32_t b, uintptr_t = ra) -{ - if (unlikely(b =3D=3D 0)) { - env->msr |=3D MSR_DZ; - - if ((env->msr & MSR_EE) && - env_archcpu(env)->cfg.div_zero_exception) { - CPUState *cs =3D env_cpu(env); - - env->esr =3D ESR_EC_DIVZERO; - cs->exception_index =3D EXCP_HW_EXCP; - cpu_loop_exit_restore(cs, ra); - } - return false; - } - return true; -} - -uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b) -{ - if (!check_divz(env, a, b, GETPC())) { - return 0; - } - return (int32_t)a / (int32_t)b; -} - -uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b) -{ - if (!check_divz(env, a, b, GETPC())) { - return 0; - } - return a / b; -} - -/* raise FPU exception. */ -static void raise_fpu_exception(CPUMBState *env, uintptr_t ra) -{ - CPUState *cs =3D env_cpu(env); - - env->esr =3D ESR_EC_FPU; - cs->exception_index =3D EXCP_HW_EXCP; - cpu_loop_exit_restore(cs, ra); -} - -static void update_fpu_flags(CPUMBState *env, int flags, uintptr_t ra) -{ - int raise =3D 0; - - if (flags & float_flag_invalid) { - env->fsr |=3D FSR_IO; - raise =3D 1; - } - if (flags & float_flag_divbyzero) { - env->fsr |=3D FSR_DZ; - raise =3D 1; - } - if (flags & float_flag_overflow) { - env->fsr |=3D FSR_OF; - raise =3D 1; - } - if (flags & float_flag_underflow) { - env->fsr |=3D FSR_UF; - raise =3D 1; - } - if (raise - && (env_archcpu(env)->cfg.pvr_regs[2] & PVR2_FPU_EXC_MASK) - && (env->msr & MSR_EE)) { - raise_fpu_exception(env, ra); - } -} - -uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fd, fa, fb; - int flags; - - set_float_exception_flags(0, &env->fp_status); - fa.l =3D a; - fb.l =3D b; - fd.f =3D float32_add(fa.f, fb.f, &env->fp_status); - - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags, GETPC()); - return fd.l; -} - -uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fd, fa, fb; - int flags; - - set_float_exception_flags(0, &env->fp_status); - fa.l =3D a; - fb.l =3D b; - fd.f =3D float32_sub(fb.f, fa.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags, GETPC()); - return fd.l; -} - -uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fd, fa, fb; - int flags; - - set_float_exception_flags(0, &env->fp_status); - fa.l =3D a; - fb.l =3D b; - fd.f =3D float32_mul(fa.f, fb.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags, GETPC()); - - return fd.l; -} - -uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fd, fa, fb; - int flags; - - set_float_exception_flags(0, &env->fp_status); - fa.l =3D a; - fb.l =3D b; - fd.f =3D float32_div(fb.f, fa.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags, GETPC()); - - return fd.l; -} - -uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fa, fb; - uint32_t r =3D 0; - - fa.l =3D a; - fb.l =3D b; - - if (float32_is_signaling_nan(fa.f, &env->fp_status) || - float32_is_signaling_nan(fb.f, &env->fp_status)) { - update_fpu_flags(env, float_flag_invalid, GETPC()); - r =3D 1; - } - - if (float32_is_quiet_nan(fa.f, &env->fp_status) || - float32_is_quiet_nan(fb.f, &env->fp_status)) { - r =3D 1; - } - - return r; -} - -uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fa, fb; - int r; - int flags; - - set_float_exception_flags(0, &env->fp_status); - fa.l =3D a; - fb.l =3D b; - r =3D float32_lt(fb.f, fa.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid, GETPC()); - - return r; -} - -uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fa, fb; - int flags; - int r; - - set_float_exception_flags(0, &env->fp_status); - fa.l =3D a; - fb.l =3D b; - r =3D float32_eq_quiet(fa.f, fb.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid, GETPC()); - - return r; -} - -uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fa, fb; - int flags; - int r; - - fa.l =3D a; - fb.l =3D b; - set_float_exception_flags(0, &env->fp_status); - r =3D float32_le(fa.f, fb.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid, GETPC()); - - - return r; -} - -uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fa, fb; - int flags, r; - - fa.l =3D a; - fb.l =3D b; - set_float_exception_flags(0, &env->fp_status); - r =3D float32_lt(fa.f, fb.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid, GETPC()); - return r; -} - -uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fa, fb; - int flags, r; - - fa.l =3D a; - fb.l =3D b; - set_float_exception_flags(0, &env->fp_status); - r =3D !float32_eq_quiet(fa.f, fb.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid, GETPC()); - - return r; -} - -uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b) -{ - CPU_FloatU fa, fb; - int flags, r; - - fa.l =3D a; - fb.l =3D b; - set_float_exception_flags(0, &env->fp_status); - r =3D !float32_lt(fa.f, fb.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags & float_flag_invalid, GETPC()); - - return r; -} - -uint32_t helper_flt(CPUMBState *env, uint32_t a) -{ - CPU_FloatU fd, fa; - - fa.l =3D a; - fd.f =3D int32_to_float32(fa.l, &env->fp_status); - return fd.l; -} - -uint32_t helper_fint(CPUMBState *env, uint32_t a) -{ - CPU_FloatU fa; - uint32_t r; - int flags; - - set_float_exception_flags(0, &env->fp_status); - fa.l =3D a; - r =3D float32_to_int32(fa.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags, GETPC()); - - return r; -} - -uint32_t helper_fsqrt(CPUMBState *env, uint32_t a) -{ - CPU_FloatU fd, fa; - int flags; - - set_float_exception_flags(0, &env->fp_status); - fa.l =3D a; - fd.l =3D float32_sqrt(fa.f, &env->fp_status); - flags =3D get_float_exception_flags(&env->fp_status); - update_fpu_flags(env, flags, GETPC()); - - return fd.l; -} - uint32_t helper_pcmpbf(uint32_t a, uint32_t b) { unsigned int i; diff --git a/target/microblaze/meson.build b/target/microblaze/meson.build index 05ee0ec1635..0a5e46027af 100644 --- a/target/microblaze/meson.build +++ b/target/microblaze/meson.build @@ -4,6 +4,7 @@ microblaze_ss.add(gen) microblaze_ss.add(files( 'cpu.c', + 'fpu_helper.c', 'gdbstub.c', 'helper.c', 'op_helper.c', --=20 2.26.3 From nobody Mon Feb 9 07:11:23 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.51 as permitted sender) client-ip=209.85.208.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f51.google.com; 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[83.57.168.235]) by smtp.gmail.com with ESMTPSA id i12sm1412143edx.13.2021.06.03.02.03.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 02:03:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5sevVFrnb8PFEJqb8tjfwJ5PpGOfYaPfNnd2GAELM28=; b=spT1DOgqGrG7fS96sbEzZX1jWqOkX2yKvAoAzo/hvMRUZkMejLSHUVomZU9dmDXk83 ySsS+9wV1BZrS3dtOPrronExChdfjh70HI8N8pkeXHduZP4CLl07xVYoWNnf0c5gOTst jL9pu2WCTaFKrdqRmVhKB8Sy302lGnnI1uobLGH9RaDhdcZ2S6S4neMBVRa/8uy8uCls jt7Ajotnu++pIHuK9VGw3lldH5ebGy5Ph3ZA/umO+yhMIQLXbL1CpaRMei4E9LvNJ4AH LtO91kbKzV4qvV252XgDgKiI9GrGqVkE3R7Bkc0kavQKepjcQy00NquCvU9P1t8ADyFU xKyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=5sevVFrnb8PFEJqb8tjfwJ5PpGOfYaPfNnd2GAELM28=; b=U16urkm5lfhaezUk+fdKGOr/iQfUZY7R7O+g+/68q+ZPwASy9lhYhS4UMfvLVtZPR8 t01OVGuv6+SbzvnTnmTPUnU/bj8vCfYy7Y/yEFKQrA0RNEqgrMAeyXjKOF3SgW/ZI4aY AIvD5u4WXANNJ70rfaZXBXH3vZ3sHZl6LPIzZ1RKGbVjlQHFE4m2MvOdwafO6lutkjB4 V8EQHm6J7oKHWVG4jnyRP3/dbf2ZOcXu4jQETZMwwWsvVggH1eGhbfucum8dOlgh6wpY HBWFi9CaNCuNdJG5zoHhu9AGueAOAw5LxZ8NMdnT31r4kmxNx+T5o8XiGmKlWeq9kjwX SUag== X-Gm-Message-State: AOAM533JxbkA0xY5fqp6jin5/zXO8FqulU3qD9lgQUUtk4lUGepNglWZ pgtNcj9CzEXgsf79HovHzvs= X-Google-Smtp-Source: ABdhPJw0l2ndqqHOCmeS+6Z9vZBweHDQFaWjuseXXATWzkfB7GmQ5MF7ZBMv8gmWSBMlKW2L9/tk2g== X-Received: by 2002:aa7:ca50:: with SMTP id j16mr11466174edt.158.1622711007594; Thu, 03 Jun 2021 02:03:27 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , "Edgar E. Iglesias" , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 3/6] target/microblaze: Assert transaction failures have exception enabled Date: Thu, 3 Jun 2021 11:03:07 +0200 Message-Id: <20210603090310.2749892-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210603090310.2749892-1-f4bug@amsat.org> References: <20210603090310.2749892-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) If exceptions are disabled, we must not get a transaction failure. Assert they are enabled passed that point. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/microblaze/op_helper.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 8d20522ee88..1048e656e27 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -122,9 +122,7 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr phy= saddr, vaddr addr, access_type =3D=3D MMU_INST_FETCH ? "INST_FETCH" : (access_type =3D=3D MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_= STORE")); =20 - if (!(env->msr & MSR_EE)) { - return; - } + assert(env->msr & MSR_EE); =20 if (access_type =3D=3D MMU_INST_FETCH) { if (!cpu->cfg.iopb_bus_exception) { --=20 2.26.3 From nobody Mon Feb 9 07:11:23 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.54 as permitted sender) client-ip=209.85.208.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1622711014; cv=none; d=zohomail.com; s=zohoarc; b=MZg55FOj9JehCARsdMpc89d0mKvSB7kFSVknr5wHnO3vPUYA6RHkCbGAo9b7ZB4mHQu5fXLT/O/CcTEjhAQqheM0vrehj9EcRx7PubJohePLwMfcqdxSsqUbMifeTYSbxRuPPwrk9eFgc32cgRnrpQDShHByWnae4+omqphqf8g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622711014; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aPYdoGgpX0ZUspn+3dr8FCwIyeB5KG9UkLhwzhTVuOg=; b=fEP/yNvWzyecY7wmrHeu8bnOMK5KEvG4OPTGXBMIkV5PErBvq6iUQq08bxbi8AH8FzoweW4gbtmTY9QR6Oj7DNWwOLDZ6QM7FYnP7MUyIlDKP0/KBx6Xt1psQGCo1vkSSMnPnpmhYrM+jmqAVdh/978yMF/9H7WLD4S5rVqwvPc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) by mx.zohomail.com with SMTPS id 1622711014133905.09336803164; Thu, 3 Jun 2021 02:03:34 -0700 (PDT) Received: by mail-ed1-f54.google.com with SMTP id u24so6187044edy.11 for ; Thu, 03 Jun 2021 02:03:33 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (235.red-83-57-168.dynamicip.rima-tde.net. [83.57.168.235]) by smtp.gmail.com with ESMTPSA id f26sm1420082edu.31.2021.06.03.02.03.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 02:03:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aPYdoGgpX0ZUspn+3dr8FCwIyeB5KG9UkLhwzhTVuOg=; b=Eq+Fk8yQD30VFL6oOz6NItDgBROJ1Qec+eLXguO1ZdLG8IYAVemLbbY7KePaXUz3D6 DYffV6lnBh+nvNcvwUrDSY3J1vU2v78nxN3l3zGYARTfMRp1pBYpjBmlFnUJsqzOCd+a wxRtYKnVu4xYFx56rp0Fv2EsCLOReU4uvjrmVTAkrEkt114sqoXTovIxqHU42ykcHJaf 5uMxI5TF3oek6Wj2GuGD/rrAtjuu/2Qp1ZAYQDqhiHzplOoVECq30UpcpHU0cFN0QeRJ E15CzZE0BGCDrSy4jvf6Qi/1W4MEVl/UONaMvtl/42KfwbGZwgtCdOc2X0RCnNEPs7h8 2BHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=aPYdoGgpX0ZUspn+3dr8FCwIyeB5KG9UkLhwzhTVuOg=; b=BH/0MmjN3s6dqFK9p29TuakWEOHoz2otdSCPBHgeo6wg1Xbi27CNVT5DFE9IrbH4eJ XZK3jnt3W7KEeIK7sN0S3Js5YjUm+5gYfiGJRyG8LXaB2vZw00opbsSqVFXE/FGXTkuv ru4a4wYAyZt+UxPjpWzjXZpB0T8bKBO8s+D6O+m9vLiGgrZiDq4UaGn39oAG3xRFBOqR 2sZLhs+hC149Ko/JgKrSqYDZU+7SklHwjUl7z9TXVlCyLfjv39Q4UGABlEDzvUYbldpT JBgRmYEgk+Nwjw7vkHwfaXO1H+NOA4M9sLgjkUvLgLPrcnGmc41V+7mjG5fcKOvVtDMl sY1Q== X-Gm-Message-State: AOAM530Sw1qvX4pl4ReC2W8BDAwtPzFkX+nhXjV5hCkU+Y9xNq4upgU4 Hf1M1RXZmKQomrFXLvh+GV4= X-Google-Smtp-Source: ABdhPJyQ2hSmNBO3nLzxUeH0kAaoNbgrHsqjdXf7LNBgWW93RAUmxRyOG2Z+7aPismMUQRhGmaS/zw== X-Received: by 2002:a05:6402:44:: with SMTP id f4mr43212973edu.364.1622711012437; Thu, 03 Jun 2021 02:03:32 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , "Edgar E. Iglesias" , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 4/6] target/microblaze: Fix Exception Status Register 'Cause' definitions Date: Thu, 3 Jun 2021 11:03:08 +0200 Message-Id: <20210603090310.2749892-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210603090310.2749892-1-f4bug@amsat.org> References: <20210603090310.2749892-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) See 'MicroBlaze Processor Reference Guide' UG081 (v9.0), Table 1-11: "Exception Status Register (ESR)". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Edgar E. Iglesias --- target/microblaze/cpu.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e4bba8a7551..42b9ad8d313 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -95,10 +95,10 @@ typedef struct CPUMBState CPUMBState; #define ESR_EC_FPU 6 #define ESR_EC_PRIVINSN 7 #define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */ -#define ESR_EC_DATA_STORAGE 8 -#define ESR_EC_INSN_STORAGE 9 -#define ESR_EC_DATA_TLB 10 -#define ESR_EC_INSN_TLB 11 +#define ESR_EC_DATA_STORAGE 16 +#define ESR_EC_INSN_STORAGE 17 +#define ESR_EC_DATA_TLB 18 +#define ESR_EC_INSN_TLB 19 #define ESR_EC_MASK 31 =20 /* Floating Point Status Register (FSR) Bits */ --=20 2.26.3 From nobody Mon Feb 9 07:11:23 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.208.48 as permitted sender) client-ip=209.85.208.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1622711019; cv=none; d=zohomail.com; s=zohoarc; b=U5sFQf3ykZLRWHatYbbqkexlYmqfDUKOQU3nMn7e9vO0zNBrelJAKLBkKhO3ZFI+kJ4BB8kBr3OazxTTkWSNeueLUb6/RbEyRWUTryY98pcRFcM1+eAno+sIKPQTCKl9XH1UbW7cb25kHHKDs1wbqo5c8YJGULmleGstbicvBJE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622711019; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+aq3bYmzCfrRF1OZBJAm7L1BFoguyeY0vM7CmI9EICc=; b=kfowXO4bsphrMOjhLOyeg3vzBfTc2k6g3ZYdlA7KgtyTHL0LLWkyDPC/O8uwmejjOiWbv964xBdoQw1SgKsO1Mhpe2BorT2Fj1C7GWw/e/eZk8ed/TTmbllaJhbCGffQrAZZrGWml7CCgqRT78dmqi9BUnnOGFjKE0giNyHPEjo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.208.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) by mx.zohomail.com with SMTPS id 1622711019240748.660277892872; Thu, 3 Jun 2021 02:03:39 -0700 (PDT) Received: by mail-ed1-f48.google.com with SMTP id g18so4223827edq.8 for ; Thu, 03 Jun 2021 02:03:38 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (235.red-83-57-168.dynamicip.rima-tde.net. [83.57.168.235]) by smtp.gmail.com with ESMTPSA id u1sm1380327edv.91.2021.06.03.02.03.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 02:03:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+aq3bYmzCfrRF1OZBJAm7L1BFoguyeY0vM7CmI9EICc=; b=iX1YCkrvg1cnb1i+Uo83gLbx0VLvoOJCo/g20HG7dJvzW9opJ1yXwPSR4f6UwzUZGO oWTtwoSIZiGGoulDKhwlG6xXOdTL8ptcqvxnwNWcjX9zzuLdQci23RuNudm4QJ2hxuSY zK33wfbIujZx1hHfXR1/S2F4LcPjbV7cM3zxLVnUBF7RkSAcdVc8c3JQ3uxzHOZ2nNFk /C2eQ8fF+7IBK4gXZfDFR/fPIPwNO10JNWXq9DFpe7qxjNOjdP9Kk2h/RIiKUZ7ToKm+ b4aR0OVamSEeIOGYKOFx+UcyM1cYibuf8/1Ty4P9lPy8AED//B0xtwzBLhfC08HzyW1D QmbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=+aq3bYmzCfrRF1OZBJAm7L1BFoguyeY0vM7CmI9EICc=; b=n5Pn/4RQQExhptqYZL/PvHTUg5rvoUpdcf51JaZh2e/5OgqUUmJYfc8aHPWEa90F3P ckAo5bc8xiuwhsVccO+CnVwDsAunE30sGIarQZfnwBY9CYAtNZ80vkXNiuspBMgN74g7 qYCbtproWPpv1DpXkUeGoP4lL6j5PhUYrH+M4KXvFXej3g1FFMQ6g2a+jLTFNe2T1zS7 /MQivkznNSet52907TqTVn70RVRiheaOmpAxYLBBHAOMy74l+kNHnNp09VWYXfA1lKas kpv1NAFx06O+28e0+oWvunred7FEHvCN2m1sCSliIVrFZvNrkNXYYbQTRNZWgAebDurF B+JA== X-Gm-Message-State: AOAM531Ec+rpPPwuvSSpAtWDbtcmPayyiNwrjs9yyKcGgNdmz1MxzH5d vRuX8QaqWkSXeSTX1U9l9lw= X-Google-Smtp-Source: ABdhPJz2l6GaL/M2V3y+cmBe/2MU0BPXO5o9vnFtKXR6Sr4RzOzk0m1areBGPbjYt8H6T1rbYNm5AQ== X-Received: by 2002:a05:6402:368:: with SMTP id s8mr27852654edw.129.1622711017284; Thu, 03 Jun 2021 02:03:37 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , "Edgar E. Iglesias" , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 5/6] target/microblaze: Replace magic values by proper definitions Date: Thu, 3 Jun 2021 11:03:09 +0200 Message-Id: <20210603090310.2749892-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210603090310.2749892-1-f4bug@amsat.org> References: <20210603090310.2749892-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Use the Exception Status Register definitions from "cpu.h". Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Edgar E. Iglesias --- target/microblaze/helper.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 20dbd673136..d537f300ca6 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -99,14 +99,22 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, mmu_idx, address); =20 env->ear =3D address; + + env->esr =3D (access_type =3D=3D MMU_DATA_STORE) ? ESR_S : 0; switch (lu.err) { case ERR_PROT: - env->esr =3D access_type =3D=3D MMU_INST_FETCH ? 17 : 16; - env->esr |=3D (access_type =3D=3D MMU_DATA_STORE) << 10; + if (access_type =3D=3D MMU_INST_FETCH) { + env->esr |=3D ESR_EC_INSN_STORAGE; + } else { + env->esr |=3D ESR_EC_DATA_STORAGE; + } break; case ERR_MISS: - env->esr =3D access_type =3D=3D MMU_INST_FETCH ? 19 : 18; - env->esr |=3D (access_type =3D=3D MMU_DATA_STORE) << 10; + if (access_type =3D=3D MMU_INST_FETCH) { + env->esr |=3D ESR_EC_INSN_TLB; + } else { + env->esr |=3D ESR_EC_DATA_TLB; + } break; default: abort(); --=20 2.26.3 From nobody Mon Feb 9 07:11:23 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.218.47 as permitted sender) client-ip=209.85.218.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1622711024; cv=none; d=zohomail.com; s=zohoarc; b=SDIecfX3hB1z0+WpJR8NLxXTFWq/7f1kmMRj55AyMeG2eROt1NOWS0mCbX0GrfyrMIau40tvggfGE8QPvsCPZWyNjkqEVh4sovK0vdRdUCaSi5eGSMKnjbaGWjkZhThg7/1Ibn6c1JVeJvw56Yc1w8FdQrcJrG2awczB/ydyDoI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622711024; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=O9+spEcANDKYx8HcPdHHRJ407zGYpuqHR7eNVlkhEK0=; b=EN8kzSmK/lytxlMcaDMnksE8aChdgLmYyDrORbo8JJbyqvXkUd6oyLe8l5or4B+hFtz4bziMS/GKeXgSp8pkt5BNbOgj2FbL4Rw/13t26gk2UvTl2GK+v7SmMBBrFb9VjXGbhxRA3pLlBCeeyXmV2/9/f11y4/Y+cSHMOWtpPgo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.218.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) by mx.zohomail.com with SMTPS id 1622711024052255.36982388053104; Thu, 3 Jun 2021 02:03:44 -0700 (PDT) Received: by mail-ej1-f47.google.com with SMTP id g20so8209658ejt.0 for ; Thu, 03 Jun 2021 02:03:43 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (235.red-83-57-168.dynamicip.rima-tde.net. [83.57.168.235]) by smtp.gmail.com with ESMTPSA id r12sm1371078edv.82.2021.06.03.02.03.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 02:03:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O9+spEcANDKYx8HcPdHHRJ407zGYpuqHR7eNVlkhEK0=; b=P+GQzUDBJKchMe+VJFjm2byIVSgkNkT+dQHKhqtqG1WVw9NJCJ3jPz+OYPWU0QnrqJ 7lxK1rHTStON3JWralPF/3pDicxZRnORwl+Eg5Of8danL5m+QqQU50yVTjGxxXrK0WF+ MED/44icC6RiRI11Sl5mRoJYTuR4MOaEb4V+Uws5NZARR1yHcxlh194MlL4QDbR8Vz8L zKglPiY2c+zZ68u1DtYOqeOt67ff2uJA8DDaGiYn9mnsZDvE2Ece+H50MBsBgn3MEa+Q zLdTUcGOcfZK6HVC0WPfdbFXC+h91dzIUqBWehy1Sh465R1dJrgpmWIrA4I8/d6DbXfA o4Ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=O9+spEcANDKYx8HcPdHHRJ407zGYpuqHR7eNVlkhEK0=; b=Mt7Mn1+FYkqOvlXdaEHsWMliPaf8/okVcBfVwgZh3fdeBknB/wixerGz/f1SDsmzpC o5Ao+q0CnUuuaoaxZ0SUERHjOo/nvMU8Dovk63EaBIfvH8BDHweG4wunubwnV7ORRz4i ndZExbcL7qepFPmZIiDTIsaJLY5PYHJnfqVw0GQK4gUv0gQe3SGud75oGMXDwyHDudvU BLA5/qjUsa0qg9Xwygf+MqoZsIg+L4EFXQ396l+fiWVjfDm223f8YIiQwGeEo3tuvNcX wDnc1VkquASljByqgp7uIXjacfIfwI8+mh0wA4x+oF4GM0w1RL/kTsPg8kioRmRVROUC 61Eg== X-Gm-Message-State: AOAM531rf5wU+VxXDkLWLRpnBbvAMA2AGFKDgE5IbfzDPeyZOi4sJb7P IxcwA2s+pZcB7c+Fk0fMfB0= X-Google-Smtp-Source: ABdhPJwEhVO/WNqBx4Wb2gI5thEygerLdYOLoPG9K7p1SprDxZcbEbt+HkrK3HYqgMpZn1dQ1QNJqg== X-Received: by 2002:a17:906:22c6:: with SMTP id q6mr38534524eja.275.1622711022264; Thu, 03 Jun 2021 02:03:42 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Alistair Francis , "Edgar E. Iglesias" , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 6/6] target/microblaze: Set OPB bits in tlb_fill, not in transaction_failed Date: Thu, 3 Jun 2021 11:03:10 +0200 Message-Id: <20210603090310.2749892-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210603090310.2749892-1-f4bug@amsat.org> References: <20210603090310.2749892-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Per the 'MicroBlaze Processor Reference Guide' UG081 (v9.0), "Hardware Exceptions" chapter: Exception Causes: * Instruction Bus Exception The instruction On-chip Peripheral Bus exception is caused by an active error signal from the slave (IOPB_errAck) or timeout signal from the arbiter (IOPB_timeout). * Data Bus Exception The data On-chip Peripheral Bus exception is caused by an active error signal from the slave (DOPB_errAck) or timeout signal from the arbiter (DOPB_timeout). the table 1-24 (Processor Version Register 2): * IOPBEXC: Generate exception for IOPB error * DOPBEXC: Generate exception for DOPB error and the table 2-12 (MPD Parameters): * C_IOPB_BUS_EXCEPTION Enable exception handling for IOPB bus error * C_DOPB_BUS_EXCEPTION Enable exception handling for DOPB bus error So if PVR2.[ID]OPBEXC feature is disabled, no exception will be generated. Thus we can not get to the transaction_failed() handler. The ESR bits have to be set in tlb_fill(). However we never implemented the MMU check whether the address belong to the On-chip Peripheral Bus interface, so simply add a stub for it, warning the feature is not implemented. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/microblaze/helper.c | 19 +++++++++++++++++++ target/microblaze/op_helper.c | 13 ------------- 2 files changed, 19 insertions(+), 13 deletions(-) diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index d537f300ca6..60e62bc0710 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -56,6 +56,18 @@ static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu, } } =20 +/* On-chip Peripheral Bus (OPB) interface */ +static bool mb_cpu_address_is_opb(MicroBlazeCPU *cpu, + vaddr address, unsigned size) +{ + if (cpu->cfg.iopb_bus_exception || cpu->cfg.dopb_bus_exception) { + /* TODO */ + warn_report_once("On-chip Peripheral Bus (OPB) interface " + "feature not implemented."); + } + return false; +} + bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -119,6 +131,13 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, default: abort(); } + if (mb_cpu_address_is_opb(cpu, address, size)) { + if (access_type =3D=3D MMU_INST_FETCH) { + env->esr =3D ESR_EC_INSN_BUS; + } else { + env->esr =3D ESR_EC_DATA_BUS; + } + } =20 if (cs->exception_index =3D=3D EXCP_MMU) { cpu_abort(cs, "recursive faults\n"); diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 1048e656e27..171c4cf99a0 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -123,19 +123,6 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr ph= ysaddr, vaddr addr, (access_type =3D=3D MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_= STORE")); =20 assert(env->msr & MSR_EE); - - if (access_type =3D=3D MMU_INST_FETCH) { - if (!cpu->cfg.iopb_bus_exception) { - return; - } - env->esr =3D ESR_EC_INSN_BUS; - } else { - if (!cpu->cfg.dopb_bus_exception) { - return; - } - env->esr =3D ESR_EC_DATA_BUS; - } - env->ear =3D addr; cs->exception_index =3D EXCP_HW_EXCP; cpu_loop_exit_restore(cs, retaddr); --=20 2.26.3