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Thu, 3 Jun 2021 18:22:40 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1622708561; bh=W0eEheTbDJ3WJbjQVn97v55ot8/Dy8ULgRERo6bK4C4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=h7i6t6qmFSc1XYLAQZxZW9b/CGoL8tGfUtMgqnlfI5FZBheg7KhKj1sbiT1BuGTuk 9/AcwsxA1nR21mGrCUEpvg93tBbSkXMAkbeWAY9gEQN5f7fw1O5XT1HKBUke0fPweC eNYUp/rggVPDGHyBjnUcd/XHe/MxddlbVjOB2/0I= From: David Gibson To: peter.maydell@linaro.org, groug@kaod.org Subject: [PULL 38/42] target/ppc: Implement cfuged instruction Date: Thu, 3 Jun 2021 18:22:27 +1000 Message-Id: <20210603082231.601214-39-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210603082231.601214-1-david@gibson.dropbear.id.au> References: <20210603082231.601214-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=203.11.71.1; envelope-from=dgibson@ozlabs.org; helo=ozlabs.org X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matheus Ferst , Richard Henderson , qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Matheus Ferst Signed-off-by: Matheus Ferst Message-Id: <20210601193528.2533031-12-matheus.ferst@eldorado.org.br> Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/helper.h | 1 + target/ppc/insn32.decode | 4 ++ target/ppc/int_helper.c | 62 ++++++++++++++++++++++ target/ppc/translate/fixedpoint-impl.c.inc | 12 +++++ 4 files changed, 79 insertions(+) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index ea9f2a236c..c517b9f025 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -46,6 +46,7 @@ DEF_HELPER_4(divwe, tl, env, tl, tl, i32) DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_3(sraw, tl, env, tl, tl) +DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64) #if defined(TARGET_PPC64) DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl) DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index bc69c70493..d4044d9069 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -87,6 +87,10 @@ STDUX 011111 ..... ..... ..... 0010110101 - = @X ADDI 001110 ..... ..... ................ @D ADDIS 001111 ..... ..... ................ @D =20 +## Fixed-Point Logical Instructions + +CFUGED 011111 ..... ..... ..... 0011011100 - @X + ### Move To/From System Register Instructions =20 SETBC 011111 ..... ..... ----- 0110000000 - @X_bi diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 41f8477d4b..efa833ef64 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -320,6 +320,68 @@ target_ulong helper_popcntb(target_ulong val) } #endif =20 +uint64_t helper_cfuged(uint64_t src, uint64_t mask) +{ + /* + * Instead of processing the mask bit-by-bit from the most significant= to + * the least significant bit, as described in PowerISA, we'll handle i= t in + * blocks of 'n' zeros/ones from LSB to MSB. To avoid the decision to = use + * ctz or cto, we negate the mask at the end of the loop. + */ + target_ulong m, left =3D 0, right =3D 0; + unsigned int n, i =3D 64; + bool bit =3D false; /* tracks if we are processing zeros or ones */ + + if (mask =3D=3D 0 || mask =3D=3D -1) { + return src; + } + + /* Processes the mask in blocks, from LSB to MSB */ + while (i) { + /* Find how many bits we should take */ + n =3D ctz64(mask); + if (n > i) { + n =3D i; + } + + /* + * Extracts 'n' trailing bits of src and put them on the leading '= n' + * bits of 'right' or 'left', pushing down the previously extracted + * values. + */ + m =3D (1ll << n) - 1; + if (bit) { + right =3D ror64(right | (src & m), n); + } else { + left =3D ror64(left | (src & m), n); + } + + /* + * Discards the processed bits from 'src' and 'mask'. Note that we= are + * removing 'n' trailing zeros from 'mask', but the logical shift = will + * add 'n' leading zeros back, so the population count of 'mask' i= s kept + * the same. + */ + src >>=3D n; + mask >>=3D n; + i -=3D n; + bit =3D !bit; + mask =3D ~mask; + } + + /* + * At the end, right was ror'ed ctpop(mask) times. To put it back in p= lace, + * we'll shift it more 64-ctpop(mask) times. + */ + if (bit) { + n =3D ctpop64(mask); + } else { + n =3D 64 - ctpop64(mask); + } + + return left | (right >> n); +} + /*************************************************************************= ****/ /* PowerPC 601 specific instructions (POWER bridge) */ target_ulong helper_div(CPUPPCState *env, target_ulong arg1, target_ulong = arg2) diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/transl= ate/fixedpoint-impl.c.inc index 5f9845fa40..50933a3b9d 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -227,3 +227,15 @@ TRANS(SETBC, do_set_bool_cond, false, false) TRANS(SETBCR, do_set_bool_cond, false, true) TRANS(SETNBC, do_set_bool_cond, true, false) TRANS(SETNBCR, do_set_bool_cond, true, true) + +static bool trans_CFUGED(DisasContext *ctx, arg_X *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_INSNS_FLAGS2(ctx, ISA310); +#if defined(TARGET_PPC64) + gen_helper_cfuged(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]); +#else + qemu_build_not_reached(); +#endif + return true; +} --=20 2.31.1