From nobody Tue Feb 10 11:14:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1622662505; cv=none; d=zohomail.com; s=zohoarc; b=YiIfHcM+2Phg2VfrT11SeknRxm7fklK+o7jJfDH9m+/pntsZHFWPYvfOtgn0daVdQYqlNv5JNkW664s3hx0zsWx5xPlQLghgx+Vqwn3L+nhli/XSmhmnwdEmyxFikfr3JN5G5jrQSpdndgOM23y0x4txILj7aPc5OGkPJnxNsfo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1622662505; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=lzCEKfQMnQvbp2Jj4Xz6RguyjH0vlyTqCp/JSR12NMM=; b=Q2YNo/U9ZbvscsAsmJwvKbwkAqM4/anqLBsONQw4XHZNHvjI2BnYM9aIJOyTsG5wWok+KffnZ0J4ADBlffCJXdXXxzgAOXo2jAzg1iOnbJ8kYw/G/A0+LWjIRMCN+/BA7swVtM3Wc9FUp0atDIcL8R6Xpfz2DpZndvZJwXuGFpM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1622662505851315.96655387056535; Wed, 2 Jun 2021 12:35:05 -0700 (PDT) Received: from localhost ([::1]:43174 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loWds-0006y5-Ki for importer@patchew.org; Wed, 02 Jun 2021 15:35:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38244) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1loWWL-00055i-NS; Wed, 02 Jun 2021 15:27:17 -0400 Received: from [201.28.113.2] (port=39068 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1loWWJ-0002aI-Eo; Wed, 02 Jun 2021 15:27:17 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Wed, 2 Jun 2021 16:26:29 -0300 Received: from eldorado.org.br (unknown [10.10.71.235]) by power9a (Postfix) with ESMTP id ABA1A80148C; Wed, 2 Jun 2021 16:26:29 -0300 (-03) From: "Lucas Mateus Castro (alqotel)" To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [RFC PATCH 4/4] target/ppc: Moved helpers to mmu_helper.c Date: Wed, 2 Jun 2021 16:26:04 -0300 Message-Id: <20210602192604.90846-5-lucas.araujo@eldorado.org.br> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210602192604.90846-1-lucas.araujo@eldorado.org.br> References: <20210602192604.90846-1-lucas.araujo@eldorado.org.br> X-OriginalArrivalTime: 02 Jun 2021 19:26:29.0835 (UTC) FILETIME=[3030C9B0:01D757E5] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=201.28.113.2; envelope-from=lucas.araujo@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Lucas Mateus Castro \(alqotel\)" , luis.pires@eldorado.org.br, fernando.valle@eldorado.org.br, matheus.ferst@eldorado.org.br, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Moved helpers from target/ppc/mmu-hash64.c to target/ppc/mmu_helpers.c and removed #ifdef CONFIG_TCG and #include exec/helper-proto.h from mmu-hash64.c Signed-off-by: Lucas Mateus Castro (alqotel) --- I had to turn slb_lookup in a non static function as it had calls from the code that was moved to mmu_helper.c and from the code that wasn't moved. Also perhaps it would be best to create a new file to move the mmu-hash functions that are not compiled in !TCG, personally I thought that moving the helpers in mmu-hash64 to mmu_helpers the better choice. --- target/ppc/mmu-hash64.c | 219 +--------------------------------------- target/ppc/mmu-hash64.h | 1 + target/ppc/mmu_helper.c | 209 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 211 insertions(+), 218 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 708dffc31b..d2ded71107 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -32,10 +32,6 @@ #include "mmu-book3s-v3.h" #include "helper_regs.h" =20 -#ifdef CONFIG_TCG -#include "exec/helper-proto.h" -#endif - /* #define DEBUG_SLB */ =20 #ifdef DEBUG_SLB @@ -48,7 +44,7 @@ * SLB handling */ =20 -static ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr) +ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr) { CPUPPCState *env =3D &cpu->env; uint64_t esid_256M, esid_1T; @@ -100,114 +96,6 @@ void dump_slb(PowerPCCPU *cpu) } } =20 -#ifdef CONFIG_TCG -void helper_slbia(CPUPPCState *env, uint32_t ih) -{ - PowerPCCPU *cpu =3D env_archcpu(env); - int starting_entry; - int n; - - /* - * slbia must always flush all TLB (which is equivalent to ERAT in ppc - * architecture). Matching on SLB_ESID_V is not good enough, because s= lbmte - * can overwrite a valid SLB without flushing its lookaside informatio= n. - * - * It would be possible to keep the TLB in synch with the SLB by flush= ing - * when a valid entry is overwritten by slbmte, and therefore slbia wo= uld - * not have to flush unless it evicts a valid SLB entry. However it is - * expected that slbmte is more common than slbia, and slbia is usually - * going to evict valid SLB entries, so that tradeoff is unlikely to b= e a - * good one. - * - * ISA v2.05 introduced IH field with values 0,1,2,6. These all invali= date - * the same SLB entries (everything but entry 0), but differ in what - * "lookaside information" is invalidated. TCG can ignore this and flu= sh - * everything. - * - * ISA v3.0 introduced additional values 3,4,7, which change what SLBs= are - * invalidated. - */ - - env->tlb_need_flush |=3D TLB_NEED_LOCAL_FLUSH; - - starting_entry =3D 1; /* default for IH=3D0,1,2,6 */ - - if (env->mmu_model =3D=3D POWERPC_MMU_3_00) { - switch (ih) { - case 0x7: - /* invalidate no SLBs, but all lookaside information */ - return; - - case 0x3: - case 0x4: - /* also considers SLB entry 0 */ - starting_entry =3D 0; - break; - - case 0x5: - /* treat undefined values as ih=3D=3D0, and warn */ - qemu_log_mask(LOG_GUEST_ERROR, - "slbia undefined IH field %u.\n", ih); - break; - - default: - /* 0,1,2,6 */ - break; - } - } - - for (n =3D starting_entry; n < cpu->hash64_opts->slb_size; n++) { - ppc_slb_t *slb =3D &env->slb[n]; - - if (!(slb->esid & SLB_ESID_V)) { - continue; - } - if (env->mmu_model =3D=3D POWERPC_MMU_3_00) { - if (ih =3D=3D 0x3 && (slb->vsid & SLB_VSID_C) =3D=3D 0) { - /* preserves entries with a class value of 0 */ - continue; - } - } - - slb->esid &=3D ~SLB_ESID_V; - } -} - -static void __helper_slbie(CPUPPCState *env, target_ulong addr, - target_ulong global) -{ - PowerPCCPU *cpu =3D env_archcpu(env); - ppc_slb_t *slb; - - slb =3D slb_lookup(cpu, addr); - if (!slb) { - return; - } - - if (slb->esid & SLB_ESID_V) { - slb->esid &=3D ~SLB_ESID_V; - - /* - * XXX: given the fact that segment size is 256 MB or 1TB, - * and we still don't have a tlb_flush_mask(env, n, mask) - * in QEMU, we just invalidate all TLBs - */ - env->tlb_need_flush |=3D - (global =3D=3D false ? TLB_NEED_LOCAL_FLUSH : TLB_NEED_GLOBAL_= FLUSH); - } -} - -void helper_slbie(CPUPPCState *env, target_ulong addr) -{ - __helper_slbie(env, addr, false); -} - -void helper_slbieg(CPUPPCState *env, target_ulong addr) -{ - __helper_slbie(env, addr, true); -} -#endif - int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, target_ulong esid, target_ulong vsid) { @@ -260,102 +148,6 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, return 0; } =20 -#ifdef CONFIG_TCG -static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb, - target_ulong *rt) -{ - CPUPPCState *env =3D &cpu->env; - int slot =3D rb & 0xfff; - ppc_slb_t *slb =3D &env->slb[slot]; - - if (slot >=3D cpu->hash64_opts->slb_size) { - return -1; - } - - *rt =3D slb->esid; - return 0; -} - -static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb, - target_ulong *rt) -{ - CPUPPCState *env =3D &cpu->env; - int slot =3D rb & 0xfff; - ppc_slb_t *slb =3D &env->slb[slot]; - - if (slot >=3D cpu->hash64_opts->slb_size) { - return -1; - } - - *rt =3D slb->vsid; - return 0; -} - -static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb, - target_ulong *rt) -{ - CPUPPCState *env =3D &cpu->env; - ppc_slb_t *slb; - - if (!msr_is_64bit(env, env->msr)) { - rb &=3D 0xffffffff; - } - slb =3D slb_lookup(cpu, rb); - if (slb =3D=3D NULL) { - *rt =3D (target_ulong)-1ul; - } else { - *rt =3D slb->vsid; - } - return 0; -} - -void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs) -{ - PowerPCCPU *cpu =3D env_archcpu(env); - - if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) { - raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, - POWERPC_EXCP_INVAL, GETPC()); - } -} - -target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb) -{ - PowerPCCPU *cpu =3D env_archcpu(env); - target_ulong rt =3D 0; - - if (ppc_load_slb_esid(cpu, rb, &rt) < 0) { - raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, - POWERPC_EXCP_INVAL, GETPC()); - } - return rt; -} - -target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb) -{ - PowerPCCPU *cpu =3D env_archcpu(env); - target_ulong rt =3D 0; - - if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) { - raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, - POWERPC_EXCP_INVAL, GETPC()); - } - return rt; -} - -target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb) -{ - PowerPCCPU *cpu =3D env_archcpu(env); - target_ulong rt =3D 0; - - if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) { - raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, - POWERPC_EXCP_INVAL, GETPC()); - } - return rt; -} -#endif - /* Check No-Execute or Guarded Storage */ static inline int ppc_hash64_pte_noexec_guard(PowerPCCPU *cpu, ppc_hash_pte64_t pte) @@ -1146,15 +938,6 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, targe= t_ulong ptex, cpu->env.tlb_need_flush =3D TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLU= SH; } =20 -#ifdef CONFIG_TCG -void helper_store_lpcr(CPUPPCState *env, target_ulong val) -{ - PowerPCCPU *cpu =3D env_archcpu(env); - - ppc_store_lpcr(cpu, val); -} -#endif - void ppc_hash64_init(PowerPCCPU *cpu) { CPUPPCState *env =3D &cpu->env; diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index 4b8b8e7950..44fd7c9d35 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -7,6 +7,7 @@ void dump_slb(PowerPCCPU *cpu); int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, target_ulong esid, target_ulong vsid); +ppc_slb_t *slb_lookup(PowerPCCPU *cpu, target_ulong eaddr); hwaddr ppc_hash64_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr); int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw, int mmu_idx); diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index dbf7b398cd..6db2678a89 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1361,3 +1361,211 @@ void helper_check_tlb_flush_global(CPUPPCState *env) =20 /*************************************************************************= ****/ =20 +#if defined(TARGET_PPC64) +void helper_slbia(CPUPPCState *env, uint32_t ih) +{ + PowerPCCPU *cpu =3D env_archcpu(env); + int starting_entry; + int n; + + /* + * slbia must always flush all TLB (which is equivalent to ERAT in ppc + * architecture). Matching on SLB_ESID_V is not good enough, because s= lbmte + * can overwrite a valid SLB without flushing its lookaside informatio= n. + * + * It would be possible to keep the TLB in synch with the SLB by flush= ing + * when a valid entry is overwritten by slbmte, and therefore slbia wo= uld + * not have to flush unless it evicts a valid SLB entry. However it is + * expected that slbmte is more common than slbia, and slbia is usually + * going to evict valid SLB entries, so that tradeoff is unlikely to b= e a + * good one. + * + * ISA v2.05 introduced IH field with values 0,1,2,6. These all invali= date + * the same SLB entries (everything but entry 0), but differ in what + * "lookaside information" is invalidated. TCG can ignore this and flu= sh + * everything. + * + * ISA v3.0 introduced additional values 3,4,7, which change what SLBs= are + * invalidated. + */ + + env->tlb_need_flush |=3D TLB_NEED_LOCAL_FLUSH; + + starting_entry =3D 1; /* default for IH=3D0,1,2,6 */ + + if (env->mmu_model =3D=3D POWERPC_MMU_3_00) { + switch (ih) { + case 0x7: + /* invalidate no SLBs, but all lookaside information */ + return; + + case 0x3: + case 0x4: + /* also considers SLB entry 0 */ + starting_entry =3D 0; + break; + + case 0x5: + /* treat undefined values as ih=3D=3D0, and warn */ + qemu_log_mask(LOG_GUEST_ERROR, + "slbia undefined IH field %u.\n", ih); + break; + + default: + /* 0,1,2,6 */ + break; + } + } + + for (n =3D starting_entry; n < cpu->hash64_opts->slb_size; n++) { + ppc_slb_t *slb =3D &env->slb[n]; + + if (!(slb->esid & SLB_ESID_V)) { + continue; + } + if (env->mmu_model =3D=3D POWERPC_MMU_3_00) { + if (ih =3D=3D 0x3 && (slb->vsid & SLB_VSID_C) =3D=3D 0) { + /* preserves entries with a class value of 0 */ + continue; + } + } + + slb->esid &=3D ~SLB_ESID_V; + } +} + +static void __helper_slbie(CPUPPCState *env, target_ulong addr, + target_ulong global) +{ + PowerPCCPU *cpu =3D env_archcpu(env); + ppc_slb_t *slb; + + slb =3D slb_lookup(cpu, addr); + if (!slb) { + return; + } + + if (slb->esid & SLB_ESID_V) { + slb->esid &=3D ~SLB_ESID_V; + + /* + * XXX: given the fact that segment size is 256 MB or 1TB, + * and we still don't have a tlb_flush_mask(env, n, mask) + * in QEMU, we just invalidate all TLBs + */ + env->tlb_need_flush |=3D + (global =3D=3D false ? TLB_NEED_LOCAL_FLUSH : TLB_NEED_GLOBAL_= FLUSH); + } +} + +void helper_slbie(CPUPPCState *env, target_ulong addr) +{ + __helper_slbie(env, addr, false); +} + +void helper_slbieg(CPUPPCState *env, target_ulong addr) +{ + __helper_slbie(env, addr, true); +} + +static int ppc_load_slb_esid(PowerPCCPU *cpu, target_ulong rb, + target_ulong *rt) +{ + CPUPPCState *env =3D &cpu->env; + int slot =3D rb & 0xfff; + ppc_slb_t *slb =3D &env->slb[slot]; + + if (slot >=3D cpu->hash64_opts->slb_size) { + return -1; + } + + *rt =3D slb->esid; + return 0; +} + +static int ppc_load_slb_vsid(PowerPCCPU *cpu, target_ulong rb, + target_ulong *rt) +{ + CPUPPCState *env =3D &cpu->env; + int slot =3D rb & 0xfff; + ppc_slb_t *slb =3D &env->slb[slot]; + + if (slot >=3D cpu->hash64_opts->slb_size) { + return -1; + } + + *rt =3D slb->vsid; + return 0; +} + +static int ppc_find_slb_vsid(PowerPCCPU *cpu, target_ulong rb, + target_ulong *rt) +{ + CPUPPCState *env =3D &cpu->env; + ppc_slb_t *slb; + + if (!msr_is_64bit(env, env->msr)) { + rb &=3D 0xffffffff; + } + slb =3D slb_lookup(cpu, rb); + if (slb =3D=3D NULL) { + *rt =3D (target_ulong)-1ul; + } else { + *rt =3D slb->vsid; + } + return 0; +} + +void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs) +{ + PowerPCCPU *cpu =3D env_archcpu(env); + + if (ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs) < 0) { + raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_INVAL, GETPC()); + } +} + +target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb) +{ + PowerPCCPU *cpu =3D env_archcpu(env); + target_ulong rt =3D 0; + + if (ppc_load_slb_esid(cpu, rb, &rt) < 0) { + raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_INVAL, GETPC()); + } + return rt; +} + +target_ulong helper_find_slb_vsid(CPUPPCState *env, target_ulong rb) +{ + PowerPCCPU *cpu =3D env_archcpu(env); + target_ulong rt =3D 0; + + if (ppc_find_slb_vsid(cpu, rb, &rt) < 0) { + raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_INVAL, GETPC()); + } + return rt; +} + +target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb) +{ + PowerPCCPU *cpu =3D env_archcpu(env); + target_ulong rt =3D 0; + + if (ppc_load_slb_vsid(cpu, rb, &rt) < 0) { + raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_INVAL, GETPC()); + } + return rt; +} + +void helper_store_lpcr(CPUPPCState *env, target_ulong val) +{ + PowerPCCPU *cpu =3D env_archcpu(env); + + ppc_store_lpcr(cpu, val); +} +#endif --=20 2.17.1