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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id g13sm285355pfi.18.2021.05.26.16.47.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 May 2021 16:47:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KggNdH/EFsJ3T1kmCx5Td3eZBoTdhzd36Y4s4qQekSU=; b=arbrUCu7Zshk+oAH4EDP9DYGwWaQV9VYDzeVS/oA3sK9I35yEhihDSJ66nG8KRDPyf 9UMICYeDBLbckwpHxFdtOLX2foVeAy60VrM5YGvNc/iVsIv1wqlhWd03OnPDceU/RgS9 r0EcGE5oLVGQLtq2Ud7Z/oKFkqqV6A6PgOAcitt4VSGkxZFYj2agDYk2XCUiAy2N7klj c4EcEBkzAVPdLLntTDn+s7QX2F4Aql/70IPJzi3cJv1FRaM9cVcHjIaEjvxO2/c/2HNQ r9jB2sfLfeEFYnFDpcpSwOsULsuxbgvzxgYGtT8RkDr9PR7mJjWTlwTFgVkrZUAYDitu jbng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KggNdH/EFsJ3T1kmCx5Td3eZBoTdhzd36Y4s4qQekSU=; b=IDu0HBCMnLfjxvvlBq9IF0CYGkvGoK1xV3MgcGCR0BuFe59zGAicms4MYUEz8QI1Vp UDP4JBPFYrzF2O0qU4pRkvCea5vSRJ6barJffhY8a92F4ymo17eiM1wLjwA+QE/mCqIS YsenTnTQYtB1je1XDt2hWLS4SgeJw1U+ppsRYnKbZLuOAxTmnm1q9mlCV7cv8ifdSLIP UHesObKMN12dXt/C0ce1O5aXgi4QAW9B4Y/g8rkPNy9f73kIkW5F/nOyaNFERqbViTzJ LziFycYzAJJLVpZd+TBBeKnUSrVLymmYIE+96W4/CZ9z4Q4Q9+Goo2QpkbqH3w/efk5H LqbA== X-Gm-Message-State: AOAM533LQOt2HoJ26jopHAifnLNHJVNDmU8h4kIOs2BDmbXYlCfPMDCr eoeT7os30VVyoaXniSOKE+G4U5GaJoHkzw== X-Google-Smtp-Source: ABdhPJwbwiuzl7D4AKAOPf94JPcuC4GUOWGVqyJYs9M1xOlHGAAoQG34D5QA2ZC4Enou4PeU1tt9kQ== X-Received: by 2002:aa7:9a8e:0:b029:2e7:e3fd:4fa4 with SMTP id w14-20020aa79a8e0000b02902e7e3fd4fa4mr923249pfi.63.1622072856793; Wed, 26 May 2021 16:47:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL 30/31] target/mips: Fold jazz behaviour into mips_cpu_do_transaction_failed Date: Wed, 26 May 2021 16:47:09 -0700 Message-Id: <20210526234710.125396-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210526234710.125396-1-richard.henderson@linaro.org> References: <20210526234710.125396-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Add a flag to MIPSCPUClass in order to avoid needing to replace mips_tcg_ops.do_transaction_failed. Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-ID: <20210227232519.222663-2-richard.henderson@linaro.org> --- target/mips/cpu-qom.h | 3 +++ hw/mips/jazz.c | 35 +++-------------------------------- target/mips/tcg/op_helper.c | 3 ++- 3 files changed, 8 insertions(+), 33 deletions(-) diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index 826ab13019..dda0c911fa 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -47,6 +47,9 @@ struct MIPSCPUClass { DeviceRealize parent_realize; DeviceReset parent_reset; const struct mips_def_t *cpu_def; + + /* Used for the jazz board to modify mips_cpu_do_transaction_failed. */ + bool no_data_aborts; }; =20 =20 diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index dba2088ed1..1e1cf8154e 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -119,30 +119,6 @@ static const MemoryRegionOps dma_dummy_ops =3D { #define MAGNUM_BIOS_SIZE = \ (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_M= AX) =20 -#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) -static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, - uintptr_t retaddr); - -static void mips_jazz_do_transaction_failed(CPUState *cs, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, - uintptr_t retaddr) -{ - if (access_type !=3D MMU_INST_FETCH) { - /* ignore invalid access (ie do not raise exception) */ - return; - } - (*real_do_transaction_failed)(cs, physaddr, addr, size, access_type, - mmu_idx, attrs, response, retaddr); -} -#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ - static void mips_jazz_init(MachineState *machine, enum jazz_model_e jazz_model) { @@ -151,7 +127,7 @@ static void mips_jazz_init(MachineState *machine, int bios_size, n; Clock *cpuclk; MIPSCPU *cpu; - CPUClass *cc; + MIPSCPUClass *mcc; CPUMIPSState *env; qemu_irq *i8259; rc4030_dma *dmas; @@ -198,8 +174,6 @@ static void mips_jazz_init(MachineState *machine, * However, we can't simply add a global memory region to catch * everything, as this would make all accesses including instruction * accesses be ignored and not raise exceptions. - * So instead we hijack the do_transaction_failed method on the CPU, a= nd - * do not raise exceptions for data access. * * NOTE: this behaviour of raising exceptions for bad instruction * fetches but not bad data accesses was added in commit 54e755588cf1e9 @@ -209,11 +183,8 @@ static void mips_jazz_init(MachineState *machine, * we could replace this hijacking of CPU methods with a simple global * memory region that catches all memory accesses, as we do on Malta. */ - cc =3D CPU_GET_CLASS(cpu); -#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) - real_do_transaction_failed =3D cc->tcg_ops->do_transaction_failed; - cc->tcg_ops->do_transaction_failed =3D mips_jazz_do_transaction_failed; -#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ + mcc =3D MIPS_CPU_GET_CLASS(cpu); + mcc->no_data_aborts =3D true; =20 /* allocate RAM */ memory_region_add_subregion(address_space, 0, machine->ram); diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c index ce1549c985..fafbf1faca 100644 --- a/target/mips/tcg/op_helper.c +++ b/target/mips/tcg/op_helper.c @@ -409,11 +409,12 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwa= ddr physaddr, MemTxResult response, uintptr_t retadd= r) { MIPSCPU *cpu =3D MIPS_CPU(cs); + MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(cpu); CPUMIPSState *env =3D &cpu->env; =20 if (access_type =3D=3D MMU_INST_FETCH) { do_raise_exception(env, EXCP_IBE, retaddr); - } else { + } else if (!mcc->no_data_aborts) { do_raise_exception(env, EXCP_DBE, retaddr); } } --=20 2.25.1