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bh=m/UXV+faOWq2I0Hna/niiE/7W+a67yHBEdZ7BzU4daM=; b=E6Dv2CnudqhsGwvaJGfmltdrDx1F1Uq2Y5v8QrtT5PehemD6XcC6Fipbh7mNy6/74U98AA KIfU7kYf7yCGX0AAN9R4x0xJJYU8nDXsAY1Ew1952tJjUvrVc4EIrdZLrAATXQQB3w/7Se 8SpS67kMUSdscDJYN4UzKeWU+35MbVA= X-MC-Unique: CcdjnJjqOFq57e0YX7OscA-1 From: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 1/4] docs: add a table showing x86-64 ABI compatibility levels Date: Wed, 26 May 2021 15:40:35 +0100 Message-Id: <20210526144038.278899-2-berrange@redhat.com> In-Reply-To: <20210526144038.278899-1-berrange@redhat.com> References: <20210526144038.278899-1-berrange@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=berrange@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.205.24.124; envelope-from=berrange@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.371, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Cleber Rosa , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) It is useful to know which CPUs satisfy each x86-64 ABI compatibility level, when dealing with guest OS that require something newer than the baseline ABI. These ABI levels are defined in: https://gitlab.com/x86-psABIs/x86-64-ABI/ and supported by GCC, Clang, glibc and more. Signed-off-by: Daniel P. Berrang=C3=A9 --- MAINTAINERS | 2 +- docs/system/cpu-models-x86-abi.csv | 67 ++++++++++++++++++++++++++++++ docs/system/cpu-models-x86.rst.inc | 22 ++++++++++ 3 files changed, 90 insertions(+), 1 deletion(-) create mode 100644 docs/system/cpu-models-x86-abi.csv diff --git a/MAINTAINERS b/MAINTAINERS index 75e0f2d750..ed9c361ec1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -329,7 +329,7 @@ F: tests/tcg/i386/ F: tests/tcg/x86_64/ F: hw/i386/ F: disas/i386.c -F: docs/system/cpu-models-x86.rst.inc +F: docs/system/cpu-models-x86* T: git https://gitlab.com/ehabkost/qemu.git x86-next =20 Xtensa TCG CPUs diff --git a/docs/system/cpu-models-x86-abi.csv b/docs/system/cpu-models-x8= 6-abi.csv new file mode 100644 index 0000000000..f3f3b60be1 --- /dev/null +++ b/docs/system/cpu-models-x86-abi.csv @@ -0,0 +1,67 @@ +Model,baseline,v2,v3,v4 +486-v1,,,, +Broadwell-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Broadwell-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Broadwell-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Broadwell-v4,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Cascadelake-Server-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Cascadelake-Server-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Cascadelake-Server-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Cascadelake-Server-v4,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Conroe-v1,=E2=9C=85,,, +Cooperlake-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Denverton-v1,=E2=9C=85,=E2=9C=85,, +Denverton-v2,=E2=9C=85,=E2=9C=85,, +Dhyana-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, +EPYC-Milan-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, +EPYC-Rome-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, +EPYC-Rome-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85, +EPYC-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, +EPYC-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85, +EPYC-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Haswell-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Haswell-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Haswell-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Haswell-v4,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Icelake-Client-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Icelake-Client-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Icelake-Server-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Icelake-Server-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Icelake-Server-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Icelake-Server-v4,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +IvyBridge-v1,=E2=9C=85,=E2=9C=85,, +IvyBridge-v2,=E2=9C=85,=E2=9C=85,, +KnightsMill-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Nehalem-v1,=E2=9C=85,=E2=9C=85,, +Nehalem-v2,=E2=9C=85,=E2=9C=85,, +Opteron_G1-v1,=E2=9C=85,,, +Opteron_G2-v1,=E2=9C=85,,, +Opteron_G3-v1,=E2=9C=85,,, +Opteron_G4-v1,=E2=9C=85,=E2=9C=85,, +Opteron_G5-v1,=E2=9C=85,=E2=9C=85,, +Penryn-v1,=E2=9C=85,,, +SandyBridge-v1,=E2=9C=85,=E2=9C=85,, +SandyBridge-v2,=E2=9C=85,=E2=9C=85,, +Skylake-Client-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Skylake-Client-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Skylake-Client-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85, +Skylake-Server-v1,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Skylake-Server-v2,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Skylake-Server-v3,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Skylake-Server-v4,=E2=9C=85,=E2=9C=85,=E2=9C=85,=E2=9C=85 +Snowridge-v1,=E2=9C=85,=E2=9C=85,, +Snowridge-v2,=E2=9C=85,=E2=9C=85,, +Westmere-v1,=E2=9C=85,=E2=9C=85,, +Westmere-v2,=E2=9C=85,=E2=9C=85,, +athlon-v1,,,, +core2duo-v1,=E2=9C=85,,, +coreduo-v1,,,, +kvm32-v1,,,, +kvm64-v1,=E2=9C=85,,, +n270-v1,,,, +pentium-v1,,,, +pentium2-v1,,,, +pentium3-v1,,,, +phenom-v1,=E2=9C=85,,, +qemu32-v1,,,, +qemu64-v1,=E2=9C=85,,, diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-x8= 6.rst.inc index 867c8216b5..f40ee03ecc 100644 --- a/docs/system/cpu-models-x86.rst.inc +++ b/docs/system/cpu-models-x86.rst.inc @@ -39,6 +39,28 @@ CPU, as they would with "Host passthrough", but gives mu= ch of the benefit of passthrough, while making live migration safe. =20 =20 +ABI compatibility levels for CPU models +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The x86_64 architecture has a number of `ABI compatibility levels`_ +defined. Traditionally most operating systems and toolchains would +only target the original baseline ABI. It is expected that in +future OS and toolchains are likely to target newer ABIs. The +table that follows illustrates which ABI compatibility levels +can be satisfied by the QEMU CPU models. Note that the table only +lists the long term stable CPU model versions (eg Haswell-v4). +In addition to whats listed, there are also many CPU model +aliases which resolve to a different CPU model version, +depending on the machine type is in use. + +.. _ABI compatibility levels: https://gitlab.com/x86-psABIs/x86-64-ABI/ + +.. csv-table:: x86-64 ABI compatibility levels + :file: cpu-models-x86-abi.csv + :widths: 40,15,15,15,15 + :header-rows: 2 + + Preferred CPU models for Intel x86 hosts ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ =20 --=20 2.31.1