From nobody Thu Dec 18 17:56:30 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1621955596; cv=none; d=zohomail.com; s=zohoarc; b=j586yQ2GDzkpGCd9xul6t3/mdAquJTWBxOZJkSBCuh2y86N59k3sGH8eC4ALjXcvLtzuw6SZdxODeocxY8uYvVJ0zTNm3pjMHmqBtcOMl4Zb5B2SVNLo7aMd/jK7wuRZdi/ZDElamXv+7UA5VFulqILHNjkpG+7jj8tkTuXKXm4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621955596; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Wp1Tfw/cNQ1FJuNdktBt5w18+3l6z2igOWDQmJdVNNA=; b=Mp43p7/kN5npkdDzygP5TvjOrWUKcP78W7ke0X7gOhsemx9zf41hFAXO5+QvX7Wbhx4OxHStQyWhEJr2Y6wt9tRYswYYyYKru4M3nE5O2v1BaSl0QgcZnA+aBkgNhMzLoPLji+Iq3lxjXCHFm6f+FKcL58u1fSEdeEYWC5YGanA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1621955596466337.3679050458434; Tue, 25 May 2021 08:13:16 -0700 (PDT) Received: from localhost ([::1]:55306 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1llYk7-0007pN-EM for importer@patchew.org; Tue, 25 May 2021 11:13:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58342) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1llYay-0002B3-KC for qemu-devel@nongnu.org; Tue, 25 May 2021 11:03:48 -0400 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:42616) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1llYau-0004Bh-PT for qemu-devel@nongnu.org; Tue, 25 May 2021 11:03:48 -0400 Received: by mail-wr1-x42e.google.com with SMTP id x8so32601248wrq.9 for ; Tue, 25 May 2021 08:03:44 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q62sm11710284wma.42.2021.05.25.08.03.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 May 2021 08:03:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Wp1Tfw/cNQ1FJuNdktBt5w18+3l6z2igOWDQmJdVNNA=; b=fTRwj307kltm12XTck1BoDVv63kLjW39k86luyYiOM2soNOgRCoOkErjXXsjjATRbA KBvbFHi+TfOfzO0w3dkmijIFkNilR043UCgwGcTb/xD+JOvOILeTiGCWA6WB47ABSvwt ZMq/mHr7qc8P9bjylApv6xMQbTynHmplHpU2cw56VDDwLUefNjT07faNx/9V5WmR0eBh DcMcKKi6cOqO37qAJjqzrDbuoNN1WP1XPD0f21Z9uwvJMoHdGc3oVl6YS1XUH9Tlatn6 /qcMFJLSKvogHPmpB9e4sE0We7csWNZsDINPh7R3rlp6jBAxT/vFimjoR8X7YLsx5gQt AwPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Wp1Tfw/cNQ1FJuNdktBt5w18+3l6z2igOWDQmJdVNNA=; b=Chu+Kv78EH2HyG3LRYcLpY/6kz74CDSv5rCmgROYskiItJZ2I5N0I4Qb81W20Hkydq c5prqGauSDdQo2jUcK7YLU4Eq0ilwgekZOwrs9YK8Sw86VGQkFY2Abja+NWCIiEEHQwB 74bWN2wdZPu/Eo+ZXmjlYdWwG/bciCh4ckgXm87MIkjzt5SK1R5ytvEAa3wauze6F80E oj/UCGAJqxhKDhYoWcLgDDnbmg1myLT2AnRUzfpiJ7e8q8vacFsTn8fX/9yESj06uWW4 6wyXGGrM0MWkoDgJUTTCrWBram6YkFNXA1bwtWUdp96toQskcSOCCFT0iB+jZnLiwGWJ xFSw== X-Gm-Message-State: AOAM531H0fuGQBbapuErH/1HP9EM9kBUJHLyhvSJKGrMOhKWrzHBPjBY EfGzH/SmlqgMCuVAW1uWy5r60gGfUWrnKfdl X-Google-Smtp-Source: ABdhPJyM9Kph2WjXfB5SaFTRjQEikSbAqfVpu5fnsgSluXG6EI7vn7oxEzfddqdGiRmYBiUtFH3sNw== X-Received: by 2002:adf:d231:: with SMTP id k17mr27023654wrh.78.1621955023404; Tue, 25 May 2021 08:03:43 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 016/114] accel/tlb: Add tlb_flush_range_by_mmuidx_all_cpus_synced() Date: Tue, 25 May 2021 16:01:46 +0100 Message-Id: <20210525150324.32370-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210525150324.32370-1-peter.maydell@linaro.org> References: <20210525150324.32370-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson Forward tlb_flush_page_bits_by_mmuidx_all_cpus_synced to tlb_flush_range_by_mmuidx_all_cpus_synced passing TARGET_PAGE_SIZE. Signed-off-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210509151618.2331764-7-f4bug@amsat.org Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org> [PMD: Split from bigger patch] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/exec/exec-all.h | 12 ++++++++++++ accel/tcg/cputlb.c | 27 ++++++++++++++++++++------- 2 files changed, 32 insertions(+), 7 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 9a3dbb7ec08..8021adf38f4 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -281,6 +281,11 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, target_u= long addr, void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr, target_ulong len, uint16_t idxmap, unsigned bits); +void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, + target_ulong addr, + target_ulong len, + uint16_t idxmap, + unsigned bits); =20 /** * tlb_set_page_with_attrs: @@ -397,6 +402,13 @@ static inline void tlb_flush_range_by_mmuidx_all_cpus(= CPUState *cpu, unsigned bits) { } +static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, + target_ulong = addr, + target_long l= en, + uint16_t idxm= ap, + unsigned bits) +{ +} #endif /** * probe_access: diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a63cf187a4f..4b3ac7093cb 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -887,16 +887,20 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState = *src_cpu, idxmap, bits); } =20 -void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, - target_ulong addr, - uint16_t idxmap, - unsigned bits) +void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu, + target_ulong addr, + target_ulong len, + uint16_t idxmap, + unsigned bits) { TLBFlushRangeData d, *p; CPUState *dst_cpu; =20 - /* If all bits are significant, this devolves to tlb_flush_page. */ - if (bits >=3D TARGET_LONG_BITS) { + /* + * If all bits are significant, and len is small, + * this devolves to tlb_flush_page. + */ + if (bits >=3D TARGET_LONG_BITS && len <=3D TARGET_PAGE_SIZE) { tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu, addr, idxmap); return; } @@ -908,7 +912,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUS= tate *src_cpu, =20 /* This should already be page aligned */ d.addr =3D addr & TARGET_PAGE_MASK; - d.len =3D TARGET_PAGE_SIZE; + d.len =3D len; d.idxmap =3D idxmap; d.bits =3D bits; =20 @@ -926,6 +930,15 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPU= State *src_cpu, RUN_ON_CPU_HOST_PTR(p)); } =20 +void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, + target_ulong addr, + uint16_t idxmap, + unsigned bits) +{ + tlb_flush_range_by_mmuidx_all_cpus_synced(src_cpu, addr, TARGET_PAGE_S= IZE, + idxmap, bits); +} + /* update the TLBs so that writes to code in the virtual page 'addr' can be detected */ void tlb_protect_code(ram_addr_t ram_addr) --=20 2.20.1