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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q62sm11710284wma.42.2021.05.25.08.03.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 May 2021 08:03:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=aYnbRqEtX/G/24dkOfBXmmy8TqbaOH7Q6ZCKhOBKqLg=; b=fW+62xQYz6gvP7IDoN0YagTPJOaVrDSqkD1QM5K89ZFqVBVodlZUAUqZF+pP5UMCeO h/BvfRgz73OJy5liECWocy7JuffaoWV6gxLSYi+WEBzgdjlLRfD13gFl2IxUXx2xujeO DGrvBbfyzL96Rt5toI+NV3VIQ/v9/pTv1XTrdu08Mjbyem/7E94pH8cC3CM2bBm7dBg9 TeuBWBeny7vK8JcV+bFbK1/yzpCSyptL6SDupW/ilR3B8HzSuhMaNaZATdS9OhIOLomj yNvjR/TtFy1saKK8rorOMuD6gL0dsRW75Q5yIFWSLxHylN2Sp/Ie3dUTKN2wrXkaNqYE Tc3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aYnbRqEtX/G/24dkOfBXmmy8TqbaOH7Q6ZCKhOBKqLg=; b=sCl1u2SGl0xfWOhBObJxpI1mqf2E/OZUGLpjhEAKjjO3qsVjkhVgUnH6onxv4LXkAT Jt1iKVzNEniUhgIa9FEPqlqB/fUVEOKcjjsN9QSFWD9rhnbI8vsJbQPJQGzAWAfdZPeV ReMVWF2bDjgUk6Jyi+xvtWH+RKuLhc7svospigaOl+dtr9g4IK0E3gQJFpJDSIQX5u51 xBV7Ztx2pMcwE8Zz4VAL/bUJRLRhyN/3tBIDeFjnmqmPkBpLMhCzecxuMBOrUGyL3hFJ piTGAHpDbCbac3WA7eoFshLDuTfitkNoUoXDXXzZw7CTZpMy08pVIZgTd2A35rZSbNtP nhnA== X-Gm-Message-State: AOAM530Re5jXaFqq8CQ4oA9+LngCIzFCtRV5vATsPlcOR4EtWU+BFzgD fl2ymxLnUVWQbp7fpHmhC7z6KGxF1H2cLIDn X-Google-Smtp-Source: ABdhPJwyoBl9NbM6LywZZ5Q4rJWjBin84ab/d7Ocib2A1y5xFnoOA80wtuDuApOJI2XPB6U8nczfsw== X-Received: by 2002:adf:f341:: with SMTP id e1mr26678564wrp.352.1621955019985; Tue, 25 May 2021 08:03:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 012/114] accel/tlb: Rename TLBFlushPageBitsByMMUIdxData -> TLBFlushRangeData Date: Tue, 25 May 2021 16:01:42 +0100 Message-Id: <20210525150324.32370-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210525150324.32370-1-peter.maydell@linaro.org> References: <20210525150324.32370-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson Rename the structure to match the rename of tlb_flush_range_locked. Signed-off-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20210509151618.2331764-4-f4bug@amsat.org Message-Id: <20210508201640.1045808-1-richard.henderson@linaro.org> [PMD: Split from bigger patch] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- accel/tcg/cputlb.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index df5d5dbf879..36e7831ef70 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -762,11 +762,11 @@ typedef struct { target_ulong len; uint16_t idxmap; uint16_t bits; -} TLBFlushPageBitsByMMUIdxData; +} TLBFlushRangeData; =20 static void tlb_flush_page_bits_by_mmuidx_async_0(CPUState *cpu, - TLBFlushPageBitsByMMUIdxData d) + TLBFlushRangeData d) { CPUArchState *env =3D cpu->env_ptr; int mmu_idx; @@ -790,7 +790,7 @@ tlb_flush_page_bits_by_mmuidx_async_0(CPUState *cpu, } =20 static bool encode_pbm_to_runon(run_on_cpu_data *out, - TLBFlushPageBitsByMMUIdxData d) + TLBFlushRangeData d) { /* We need 6 bits to hold to hold @bits up to 63. */ if (d.idxmap <=3D MAKE_64BIT_MASK(0, TARGET_PAGE_BITS - 6)) { @@ -800,11 +800,11 @@ static bool encode_pbm_to_runon(run_on_cpu_data *out, return false; } =20 -static TLBFlushPageBitsByMMUIdxData +static TLBFlushRangeData decode_runon_to_pbm(run_on_cpu_data data) { target_ulong addr_map_bits =3D (target_ulong) data.target_ptr; - return (TLBFlushPageBitsByMMUIdxData){ + return (TLBFlushRangeData){ .addr =3D addr_map_bits & TARGET_PAGE_MASK, .idxmap =3D (addr_map_bits & ~TARGET_PAGE_MASK) >> 6, .bits =3D addr_map_bits & 0x3f @@ -820,7 +820,7 @@ static void tlb_flush_page_bits_by_mmuidx_async_1(CPUSt= ate *cpu, static void tlb_flush_page_bits_by_mmuidx_async_2(CPUState *cpu, run_on_cpu_data data) { - TLBFlushPageBitsByMMUIdxData *d =3D data.host_ptr; + TLBFlushRangeData *d =3D data.host_ptr; tlb_flush_page_bits_by_mmuidx_async_0(cpu, *d); g_free(d); } @@ -828,7 +828,7 @@ static void tlb_flush_page_bits_by_mmuidx_async_2(CPUSt= ate *cpu, void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr, uint16_t idxmap, unsigned bits) { - TLBFlushPageBitsByMMUIdxData d; + TLBFlushRangeData d; run_on_cpu_data runon; =20 /* If all bits are significant, this devolves to tlb_flush_page. */ @@ -854,7 +854,7 @@ void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, targe= t_ulong addr, async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_1, runon= ); } else { /* Otherwise allocate a structure, freed by the worker. */ - TLBFlushPageBitsByMMUIdxData *p =3D g_memdup(&d, sizeof(d)); + TLBFlushRangeData *p =3D g_memdup(&d, sizeof(d)); async_run_on_cpu(cpu, tlb_flush_page_bits_by_mmuidx_async_2, RUN_ON_CPU_HOST_PTR(p)); } @@ -865,7 +865,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *s= rc_cpu, uint16_t idxmap, unsigned bits) { - TLBFlushPageBitsByMMUIdxData d; + TLBFlushRangeData d; run_on_cpu_data runon; =20 /* If all bits are significant, this devolves to tlb_flush_page. */ @@ -893,7 +893,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *s= rc_cpu, /* Allocate a separate data block for each destination cpu. */ CPU_FOREACH(dst_cpu) { if (dst_cpu !=3D src_cpu) { - TLBFlushPageBitsByMMUIdxData *p =3D g_memdup(&d, sizeof(d)= ); + TLBFlushRangeData *p =3D g_memdup(&d, sizeof(d)); async_run_on_cpu(dst_cpu, tlb_flush_page_bits_by_mmuidx_async_2, RUN_ON_CPU_HOST_PTR(p)); @@ -909,7 +909,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUS= tate *src_cpu, uint16_t idxmap, unsigned bits) { - TLBFlushPageBitsByMMUIdxData d; + TLBFlushRangeData d; run_on_cpu_data runon; =20 /* If all bits are significant, this devolves to tlb_flush_page. */ @@ -935,7 +935,7 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUS= tate *src_cpu, runon); } else { CPUState *dst_cpu; - TLBFlushPageBitsByMMUIdxData *p; + TLBFlushRangeData *p; =20 /* Allocate a separate data block for each destination cpu. */ CPU_FOREACH(dst_cpu) { --=20 2.20.1