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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, Stephen Long Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Stephen Long Reviewed-by: Peter Maydell Signed-off-by: Stephen Long Message-Id: <20200422165503.13511-1-steplong@quicinc.com> [rth: Fix indexing in helpers, expand macro to straight functions.] Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++++++ target/arm/helper-sve.h | 3 ++ target/arm/sve.decode | 4 +++ target/arm/sve_helper.c | 74 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 34 ++++++++++++++++++ 5 files changed, 125 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ae787fac8a..595bc6349d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4246,6 +4246,16 @@ static inline bool isar_feature_aa64_sve2_bitperm(co= nst ARMISARegisters *id) return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, BITPERM) !=3D 0; } =20 +static inline bool isar_feature_aa64_sve_f32mm(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F32MM) !=3D 0; +} + +static inline bool isar_feature_aa64_sve_f64mm(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) !=3D 0; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 28b8f00201..7e99dcd119 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -2662,3 +2662,6 @@ DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_zzzz_s, TCG_CALL_NO= _RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve2_sqrdcmlah_zzzz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_6(fmmla_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr= , i32) +DEF_HELPER_FLAGS_6(fmmla_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr= , i32) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index c3958bed6a..cb2ee86228 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -1389,6 +1389,10 @@ UMLSLT_zzzw 01000100 .. 0 ..... 010 111 ..... ..= ... @rda_rn_rm CMLA_zzzz 01000100 esz:2 0 rm:5 0010 rot:2 rn:5 rd:5 ra=3D%reg_movp= rfx SQRDCMLAH_zzzz 01000100 esz:2 0 rm:5 0011 rot:2 rn:5 rd:5 ra=3D%reg_movp= rfx =20 +### SVE2 floating point matrix multiply accumulate + +FMMLA 01100100 .. 1 ..... 111001 ..... ..... @rda_rn_rm + ### SVE2 Memory Gather Load Group =20 # SVE2 64-bit gather non-temporal load diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 5b6292929e..fa96e28639 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -7241,3 +7241,77 @@ void HELPER(sve2_xar_s)(void *vd, void *vn, void *vm= , uint32_t desc) d[i] =3D ror32(n[i] ^ m[i], shr); } } + +void HELPER(fmmla_s)(void *vd, void *vn, void *vm, void *va, + void *status, uint32_t desc) +{ + intptr_t s, opr_sz =3D simd_oprsz(desc) / (sizeof(float32) * 4); + + for (s =3D 0; s < opr_sz; ++s) { + float32 *n =3D vn + s * sizeof(float32) * 4; + float32 *m =3D vm + s * sizeof(float32) * 4; + float32 *a =3D va + s * sizeof(float32) * 4; + float32 *d =3D vd + s * sizeof(float32) * 4; + float32 n00 =3D n[H4(0)], n01 =3D n[H4(1)]; + float32 n10 =3D n[H4(2)], n11 =3D n[H4(3)]; + float32 m00 =3D m[H4(0)], m01 =3D m[H4(1)]; + float32 m10 =3D m[H4(2)], m11 =3D m[H4(3)]; + float32 p0, p1; + + /* i =3D 0, j =3D 0 */ + p0 =3D float32_mul(n00, m00, status); + p1 =3D float32_mul(n01, m01, status); + d[H4(0)] =3D float32_add(a[H4(0)], float32_add(p0, p1, status), st= atus); + + /* i =3D 0, j =3D 1 */ + p0 =3D float32_mul(n00, m10, status); + p1 =3D float32_mul(n01, m11, status); + d[H4(1)] =3D float32_add(a[H4(1)], float32_add(p0, p1, status), st= atus); + + /* i =3D 1, j =3D 0 */ + p0 =3D float32_mul(n10, m00, status); + p1 =3D float32_mul(n11, m01, status); + d[H4(2)] =3D float32_add(a[H4(2)], float32_add(p0, p1, status), st= atus); + + /* i =3D 1, j =3D 1 */ + p0 =3D float32_mul(n10, m10, status); + p1 =3D float32_mul(n11, m11, status); + d[H4(3)] =3D float32_add(a[H4(3)], float32_add(p0, p1, status), st= atus); + } +} + +void HELPER(fmmla_d)(void *vd, void *vn, void *vm, void *va, + void *status, uint32_t desc) +{ + intptr_t s, opr_sz =3D simd_oprsz(desc) / (sizeof(float64) * 4); + + for (s =3D 0; s < opr_sz; ++s) { + float64 *n =3D vn + s * sizeof(float64) * 4; + float64 *m =3D vm + s * sizeof(float64) * 4; + float64 *a =3D va + s * sizeof(float64) * 4; + float64 *d =3D vd + s * sizeof(float64) * 4; + float64 n00 =3D n[0], n01 =3D n[1], n10 =3D n[2], n11 =3D n[3]; + float64 m00 =3D m[0], m01 =3D m[1], m10 =3D m[2], m11 =3D m[3]; + float64 p0, p1; + + /* i =3D 0, j =3D 0 */ + p0 =3D float64_mul(n00, m00, status); + p1 =3D float64_mul(n01, m01, status); + d[0] =3D float64_add(a[0], float64_add(p0, p1, status), status); + + /* i =3D 0, j =3D 1 */ + p0 =3D float64_mul(n00, m10, status); + p1 =3D float64_mul(n01, m11, status); + d[1] =3D float64_add(a[1], float64_add(p0, p1, status), status); + + /* i =3D 1, j =3D 0 */ + p0 =3D float64_mul(n10, m00, status); + p1 =3D float64_mul(n11, m01, status); + d[2] =3D float64_add(a[2], float64_add(p0, p1, status), status); + + /* i =3D 1, j =3D 1 */ + p0 =3D float64_mul(n10, m10, status); + p1 =3D float64_mul(n11, m11, status); + d[3] =3D float64_add(a[3], float64_add(p0, p1, status), status); + } +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index a64ad04c50..a94b399f67 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -7672,6 +7672,40 @@ DO_SVE2_ZPZZ_FP(FMINP, fminp) * SVE Integer Multiply-Add (unpredicated) */ =20 +static bool trans_FMMLA(DisasContext *s, arg_rrrr_esz *a) +{ + gen_helper_gvec_4_ptr *fn; + + switch (a->esz) { + case MO_32: + if (!dc_isar_feature(aa64_sve_f32mm, s)) { + return false; + } + fn =3D gen_helper_fmmla_s; + break; + case MO_64: + if (!dc_isar_feature(aa64_sve_f64mm, s)) { + return false; + } + fn =3D gen_helper_fmmla_d; + break; + default: + return false; + } + + if (sve_access_check(s)) { + unsigned vsz =3D vec_full_reg_size(s); + TCGv_ptr status =3D fpstatus_ptr(FPST_FPCR); + tcg_gen_gvec_4_ptr(vec_full_reg_offset(s, a->rd), + vec_full_reg_offset(s, a->rn), + vec_full_reg_offset(s, a->rm), + vec_full_reg_offset(s, a->ra), + status, vsz, vsz, 0, fn); + tcg_temp_free_ptr(status); + } + return true; +} + static bool do_sqdmlal_zzzw(DisasContext *s, arg_rrrr_esz *a, bool sel1, bool sel2) { --=20 2.25.1