From nobody Sat Nov 16 01:32:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1621456440; cv=none; d=zohomail.com; s=zohoarc; b=X+Ar5qOLaU3b/MOmP6ZeWPqVdAsjoTCf4o2+p/iGGrDmu/EPi7Za7FKvNgjOFdwhfwVxUaxhJiVkRney/4gHAvOrnMvokZg1eJYaQwHssQcHApeljOckTK6r7MUcHD2z8zINZhS90WvELAtyiM8foFvOCvFMt5NCzOaqlRiPr0w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621456440; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HbV9HVtxAlWXcBX0c9TmFfWAXsVc69rLNGxXdzxuRVE=; b=R9bMHSD4dtbYXef7+jq/HMYs1X2SbWpHh6NgBXeozx6H3aUzlLB5D4vAb6BNpaNsYbEFG83CKMUFmDt+C23iL70s/ryR1sYoXjYy4tvc2tmMnnGayynRZAwwY+fQwZP04pAzqpgmfABw94QgRoHA21PXBGwWuOCkF46sDDcWXv8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1621456440443985.5767007572998; Wed, 19 May 2021 13:34:00 -0700 (PDT) Received: from localhost ([::1]:54880 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljStD-00028P-CJ for importer@patchew.org; Wed, 19 May 2021 16:33:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53546) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljSjO-0005W4-O9; Wed, 19 May 2021 16:23:51 -0400 Received: from mail.csgraf.de ([85.25.223.15]:48270 helo=zulu616.server4you.de) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljSjL-0003IC-Cn; Wed, 19 May 2021 16:23:50 -0400 Received: from localhost.localdomain (dynamic-095-114-039-201.95.114.pool.telefonica.de [95.114.39.201]) by csgraf.de (Postfix) with ESMTPSA id CD93B6080727; Wed, 19 May 2021 22:23:04 +0200 (CEST) From: Alexander Graf To: QEMU Developers Subject: [PATCH v8 15/19] hvf: arm: Implement -cpu host Date: Wed, 19 May 2021 22:22:49 +0200 Message-Id: <20210519202253.76782-16-agraf@csgraf.de> X-Mailer: git-send-email 2.30.1 (Apple Git-130) In-Reply-To: <20210519202253.76782-1-agraf@csgraf.de> References: <20210519202253.76782-1-agraf@csgraf.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=85.25.223.15; envelope-from=agraf@csgraf.de; helo=zulu616.server4you.de X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Eduardo Habkost , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Cameron Esfahani , Roman Bolshakov , qemu-arm , Frank Yang , Paolo Bonzini , Peter Collingbourne Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Now that we have working system register sync, we push more target CPU properties into the virtual machine. That might be useful in some situations, but is not the typical case that users want. So let's add a -cpu host option that allows them to explicitly pass all CPU capabilities of their host CPU into the guest. Signed-off-by: Alexander Graf Acked-by: Roman Bolshakov Reviewed-by: Sergio Lopez Tested-by: Sergio Lopez --- v6 -> v7: - Move function define to own header - Do not propagate SVE features for HVF - Remove stray whitespace change - Verify that EL0 and EL1 do not allow AArch32 mode - Only probe host CPU features once --- target/arm/cpu.c | 9 ++++-- target/arm/cpu.h | 2 ++ target/arm/hvf/hvf.c | 72 ++++++++++++++++++++++++++++++++++++++++++++ target/arm/hvf_arm.h | 19 ++++++++++++ target/arm/kvm_arm.h | 2 -- 5 files changed, 100 insertions(+), 4 deletions(-) create mode 100644 target/arm/hvf_arm.h diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4eb0d2f85c..762d8a6d26 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -39,6 +39,7 @@ #include "sysemu/tcg.h" #include "sysemu/hw_accel.h" #include "kvm_arm.h" +#include "hvf_arm.h" #include "disas/capstone.h" #include "fpu/softfloat.h" =20 @@ -1998,15 +1999,19 @@ static void arm_cpu_class_init(ObjectClass *oc, voi= d *data) #endif /* CONFIG_TCG */ } =20 -#ifdef CONFIG_KVM +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) static void arm_host_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); =20 +#ifdef CONFIG_KVM kvm_arm_set_cpu_features_from_host(cpu); if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { aarch64_add_sve_properties(obj); } +#else + hvf_arm_set_cpu_features_from_host(cpu); +#endif arm_cpu_post_init(obj); } =20 @@ -2066,7 +2071,7 @@ static void arm_cpu_register_types(void) { type_register_static(&arm_cpu_type_info); =20 -#ifdef CONFIG_KVM +#if defined(CONFIG_KVM) || defined(CONFIG_HVF) type_register_static(&host_arm_cpu_type_info); #endif } diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 616b393253..4360e77183 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2977,6 +2977,8 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_syn= c); #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_ARM_CPU =20 +#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU + #define cpu_signal_handler cpu_arm_signal_handler #define cpu_list arm_cpu_list =20 diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 67002efd36..bce46f3ed8 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -17,6 +17,7 @@ #include "sysemu/hvf.h" #include "sysemu/hvf_int.h" #include "sysemu/hw_accel.h" +#include "hvf_arm.h" =20 #include =20 @@ -44,6 +45,16 @@ #define TMR_CTL_IMASK (1 << 1) #define TMR_CTL_ISTATUS (1 << 2) =20 +typedef struct ARMHostCPUFeatures { + ARMISARegisters isar; + uint64_t features; + uint64_t midr; + uint32_t reset_sctlr; + const char *dtb_compatible; +} ARMHostCPUFeatures; + +static ARMHostCPUFeatures arm_host_cpu_features; + struct hvf_reg_match { int reg; uint64_t offset; @@ -390,6 +401,67 @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt) return val; } =20 +static void hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) +{ + ARMISARegisters host_isar; + const struct isar_regs { + int reg; + uint64_t *val; + } regs[] =3D { + { HV_SYS_REG_ID_AA64PFR0_EL1, &host_isar.id_aa64pfr0 }, + { HV_SYS_REG_ID_AA64PFR1_EL1, &host_isar.id_aa64pfr1 }, + { HV_SYS_REG_ID_AA64DFR0_EL1, &host_isar.id_aa64dfr0 }, + { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 }, + { HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 }, + { HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 }, + { HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 }, + { HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 }, + { HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 }, + }; + hv_vcpu_t fd; + hv_vcpu_exit_t *exit; + int i; + + ahcf->dtb_compatible =3D "arm,arm-v8"; + ahcf->features =3D (1ULL << ARM_FEATURE_V8) | + (1ULL << ARM_FEATURE_NEON) | + (1ULL << ARM_FEATURE_AARCH64) | + (1ULL << ARM_FEATURE_PMU) | + (1ULL << ARM_FEATURE_GENERIC_TIMER); + + /* We set up a small vcpu to extract host registers */ + + assert_hvf_ok(hv_vcpu_create(&fd, &exit, NULL)); + for (i =3D 0; i < ARRAY_SIZE(regs); i++) { + assert_hvf_ok(hv_vcpu_get_sys_reg(fd, regs[i].reg, regs[i].val)); + } + assert_hvf_ok(hv_vcpu_get_sys_reg(fd, HV_SYS_REG_MIDR_EL1, &ahcf->midr= )); + assert_hvf_ok(hv_vcpu_destroy(fd)); + + ahcf->isar =3D host_isar; + ahcf->reset_sctlr =3D 0x00c50078; + + /* Make sure we don't advertise AArch32 support for EL0/EL1 */ + g_assert((host_isar.id_aa64pfr0 & 0xff) =3D=3D 0x11); +} + +void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) +{ + if (!arm_host_cpu_features.dtb_compatible) { + if (!hvf_enabled()) { + cpu->host_cpu_probe_failed =3D true; + return; + } + hvf_arm_get_host_cpu_features(&arm_host_cpu_features); + } + + cpu->dtb_compatible =3D arm_host_cpu_features.dtb_compatible; + cpu->isar =3D arm_host_cpu_features.isar; + cpu->env.features =3D arm_host_cpu_features.features; + cpu->midr =3D arm_host_cpu_features.midr; + cpu->reset_sctlr =3D arm_host_cpu_features.reset_sctlr; +} + void hvf_arch_vcpu_destroy(CPUState *cpu) { } diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h new file mode 100644 index 0000000000..603074a331 --- /dev/null +++ b/target/arm/hvf_arm.h @@ -0,0 +1,19 @@ +/* + * QEMU Hypervisor.framework (HVF) support -- ARM specifics + * + * Copyright (c) 2021 Alexander Graf + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + * + */ + +#ifndef QEMU_HVF_ARM_H +#define QEMU_HVF_ARM_H + +#include "qemu/accel.h" +#include "cpu.h" + +void hvf_arm_set_cpu_features_from_host(struct ARMCPU *cpu); + +#endif diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index 34f8daa377..828dca4a4a 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -214,8 +214,6 @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *c= pus_to_try, */ void kvm_arm_destroy_scratch_host_vcpu(int *fdarray); =20 -#define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU - /** * ARMHostCPUFeatures: information about the host CPU (identified * by asking the host kernel) --=20 2.30.1 (Apple Git-130)