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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" For x86_64 user-only, there is no way to leave 64-bit mode. Without x86_64, there is no way to enter 64-bit mode. There is an existing macro to aid with that; simply place it in the right place in the ifdef chain. Since we're adding an accessor macro, pull the value directly out of flags when we're not assuming a constant. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini Message-Id: <20210514151342.384376-13-richard.henderson@linaro.org> --- target/i386/tcg/translate.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 7b5031f647..e3907f9066 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -41,11 +41,9 @@ #define PREFIX_VEX 0x20 =20 #ifdef TARGET_X86_64 -#define CODE64(s) ((s)->code64) #define REX_X(s) ((s)->rex_x) #define REX_B(s) ((s)->rex_b) #else -#define CODE64(s) 0 #define REX_X(s) 0 #define REX_B(s) 0 #endif @@ -102,7 +100,6 @@ typedef struct DisasContext { =20 #ifdef TARGET_X86_64 int lma; /* long mode active */ - int code64; /* 64 bit code segment */ int rex_x, rex_b; #endif int vex_l; /* vex vector length */ @@ -165,6 +162,13 @@ typedef struct DisasContext { #define CODE32(S) (((S)->flags & HF_CS32_MASK) !=3D 0) #define SS32(S) (((S)->flags & HF_SS32_MASK) !=3D 0) #endif +#if !defined(TARGET_X86_64) +#define CODE64(S) false +#elif defined(CONFIG_USER_ONLY) +#define CODE64(S) true +#else +#define CODE64(S) (((S)->flags & HF_CS64_MASK) !=3D 0) +#endif =20 static void gen_eob(DisasContext *s); static void gen_jr(DisasContext *s, TCGv dest); @@ -8497,6 +8501,7 @@ static void i386_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cpu) g_assert(IOPL(dc) =3D=3D iopl); g_assert(VM86(dc) =3D=3D ((flags & HF_VM_MASK) !=3D 0)); g_assert(CODE32(dc) =3D=3D ((flags & HF_CS32_MASK) !=3D 0)); + g_assert(CODE64(dc) =3D=3D ((flags & HF_CS64_MASK) !=3D 0)); g_assert(SS32(dc) =3D=3D ((flags & HF_SS32_MASK) !=3D 0)); =20 dc->addseg =3D (flags >> HF_ADDSEG_SHIFT) & 1; @@ -8518,7 +8523,6 @@ static void i386_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cpu) dc->cpuid_xsave_features =3D env->features[FEAT_XSAVE]; #ifdef TARGET_X86_64 dc->lma =3D (flags >> HF_LMA_SHIFT) & 1; - dc->code64 =3D (flags >> HF_CS64_SHIFT) & 1; #endif dc->jmp_opt =3D !(dc->tf || dc->base.singlestep_enabled || (flags & HF_INHIBIT_IRQ_MASK)); --=20 2.25.1