From nobody Wed Feb 11 02:13:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1621435006; cv=none; d=zohomail.com; s=zohoarc; b=TTIK3Lf7rfvp7i6PwBOvrxNWw9lGV4WuESf1KA4Sn3PfTEReyc3nRy/wZUBKAefK6vwSreeD5b0hT4gYQ3wS2l6B94nNlp9Out2i9BrISKp7/fbxu7x739W9++pohMqdNKSnoA8BnCrT2lHTUWdkzWijfMt7LwITwo48gAyAbs8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621435006; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+VY3RuILHc2dnKazbadIaeDmctRG0DAo891J8OenakI=; b=WUpDXPXQWm/jM7WqjEs49Fj9IL92nI6s5gEtS7qQcqKRqXCxZJ2cpB5syR9TdfnPjj5ZuDAEvxU3T373V2DjcgpobqcJQFe0hSsdWw6pY5rwlTxa4Aa4tjj3l7mZWztS4Zl7zoj0+crzgSSOr0IpGEh9rS6s6K25jBmg9hzhUHs= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1621435006032467.69809945553015; Wed, 19 May 2021 07:36:46 -0700 (PDT) Received: from localhost ([::1]:58242 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljNJV-0003vK-Cb for importer@patchew.org; Wed, 19 May 2021 10:36:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57436) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljNCe-0000j4-LP for qemu-devel@nongnu.org; Wed, 19 May 2021 10:29:40 -0400 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]:37868 helo=mail.default.ilande.bv.iomart.io) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljNCY-0008Jz-SZ for qemu-devel@nongnu.org; Wed, 19 May 2021 10:29:40 -0400 Received: from host217-39-58-213.range217-39.btcentralplus.com ([217.39.58.213] helo=kentang.home) by mail.default.ilande.bv.iomart.io with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1ljNCW-0003Tz-Kz; Wed, 19 May 2021 15:29:32 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, laurent@vivier.eu Date: Wed, 19 May 2021 15:29:17 +0100 Message-Id: <20210519142917.16693-5-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210519142917.16693-1-mark.cave-ayland@ilande.co.uk> References: <20210519142917.16693-1-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 217.39.58.213 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: [PATCH 4/4] target/m68k: implement m68k "any instruction" trace mode X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.default.ilande.bv.iomart.io) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.default.ilande.bv.iomart.io X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The m68k trace mode is controlled by the top 2 bits in the SR register. Imp= lement the m68k "any instruction" trace mode where bit T1=3D1 and bit T0=3D0 in wh= ich the CPU generates an EXCP_TRACE exception (vector 9 or offset 0x24) after executing= each instruction. This functionality is used by the NetBSD kernel debugger to allow single-st= epping on m68k architectures. Signed-off-by: Mark Cave-Ayland Reviewed-by: Richard Henderson --- target/m68k/cpu.h | 8 ++++++++ target/m68k/translate.c | 27 ++++++++++++++++++++------- 2 files changed, 28 insertions(+), 7 deletions(-) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 402c86c876..997d588911 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -230,6 +230,9 @@ typedef enum { #define SR_T_SHIFT 14 #define SR_T 0xc000 =20 +#define M68K_SR_TRACE(sr) ((sr & SR_T) >> SR_T_SHIFT) +#define M68K_SR_TRACE_ANY_INS 0x2 + #define M68K_SSP 0 #define M68K_USP 1 #define M68K_ISP 2 @@ -590,6 +593,8 @@ typedef M68kCPU ArchCPU; #define TB_FLAGS_SFC_S (1 << TB_FLAGS_SFC_S_BIT) #define TB_FLAGS_DFC_S_BIT 15 #define TB_FLAGS_DFC_S (1 << TB_FLAGS_DFC_S_BIT) +#define TB_FLAGS_TRACE 16 +#define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE) =20 static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *p= c, target_ulong *cs_base, uint32_t *f= lags) @@ -602,6 +607,9 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *e= nv, target_ulong *pc, *flags |=3D (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_= S; *flags |=3D (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_= S; } + if (M68K_SR_TRACE(env->sr) =3D=3D M68K_SR_TRACE_ANY_INS) { + *flags |=3D TB_FLAGS_TRACE; + } } =20 void dump_mmu(CPUM68KState *env); diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 10e8aba42e..f0c5bf9154 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -124,6 +124,7 @@ typedef struct DisasContext { #define MAX_TO_RELEASE 8 int release_count; TCGv release[MAX_TO_RELEASE]; + bool ss_active; } DisasContext; =20 static void init_release_array(DisasContext *s) @@ -197,12 +198,13 @@ static void do_writebacks(DisasContext *s) static bool is_singlestepping(DisasContext *s) { /* - * Return true if we are singlestepping either because of QEMU gdbstub - * singlestep. This does not include the command line '-singlestep' mo= de - * which is rather misnamed as it only means "one instruction per TB" = and - * doesn't affect the code we generate. + * Return true if we are singlestepping either because of + * architectural singlestep or QEMU gdbstub singlestep. This does + * not include the command line '-singlestep' mode which is rather + * misnamed as it only means "one instruction per TB" and doesn't + * affect the code we generate. */ - return s->base.singlestep_enabled; + return s->base.singlestep_enabled || s->ss_active; } =20 /* is_jmp field values */ @@ -323,9 +325,14 @@ static void gen_singlestep_exception(DisasContext *s) { /* * Generate the right kind of exception for singlestep, which is - * EXCP_DEBUG for QEMU's gdb singlestepping. + * either the architectural singlestep or EXCP_DEBUG for QEMU's + * gdb singlestepping. */ - gen_raise_exception(EXCP_DEBUG); + if (s->ss_active) { + gen_raise_exception(EXCP_TRACE); + } else { + gen_raise_exception(EXCP_DEBUG); + } } =20 static inline void gen_addr_fault(DisasContext *s) @@ -6194,6 +6201,12 @@ static void m68k_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cpu) dc->done_mac =3D 0; dc->writeback_mask =3D 0; init_release_array(dc); + + dc->ss_active =3D (M68K_SR_TRACE(env->sr) =3D=3D M68K_SR_TRACE_ANY_INS= ); + /* If architectural single step active, limit to 1 */ + if (is_singlestepping(dc)) { + dc->base.max_insns =3D 1; + } } =20 static void m68k_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) --=20 2.20.1