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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: bruno.larsen@eldorado.org.br, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" We must leave the 'int rwx' parameter to ppc_radix64_handle_mmu_fault for now, but will clean that up later. Signed-off-by: Richard Henderson --- target/ppc/mmu-radix64.c | 119 ++++++++++++++++++++++++--------------- 1 file changed, 74 insertions(+), 45 deletions(-) diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 646b9afb7b..7972153f23 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -75,71 +75,94 @@ static bool ppc_radix64_get_fully_qualified_addr(const = CPUPPCState *env, return true; } =20 -static void ppc_radix64_raise_segi(PowerPCCPU *cpu, int rwx, vaddr eaddr) +static void ppc_radix64_raise_segi(PowerPCCPU *cpu, MMUAccessType access_t= ype, + vaddr eaddr) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; =20 - if (rwx =3D=3D 2) { /* Instruction Segment Interrupt */ + switch (access_type) { + case MMU_INST_FETCH: + /* Instruction Segment Interrupt */ cs->exception_index =3D POWERPC_EXCP_ISEG; - } else { /* Data Segment Interrupt */ + break; + case MMU_DATA_STORE: + case MMU_DATA_LOAD: + /* Data Segment Interrupt */ cs->exception_index =3D POWERPC_EXCP_DSEG; env->spr[SPR_DAR] =3D eaddr; + break; + default: + g_assert_not_reached(); } env->error_code =3D 0; } =20 -static void ppc_radix64_raise_si(PowerPCCPU *cpu, int rwx, vaddr eaddr, - uint32_t cause) +static void ppc_radix64_raise_si(PowerPCCPU *cpu, MMUAccessType access_typ= e, + vaddr eaddr, uint32_t cause) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; =20 - if (rwx =3D=3D 2) { /* Instruction Storage Interrupt */ + switch (access_type) { + case MMU_INST_FETCH: + /* Instruction Storage Interrupt */ cs->exception_index =3D POWERPC_EXCP_ISI; env->error_code =3D cause; - } else { /* Data Storage Interrupt */ + break; + case MMU_DATA_STORE: + cause |=3D DSISR_ISSTORE; + /* fall through */ + case MMU_DATA_LOAD: + /* Data Storage Interrupt */ cs->exception_index =3D POWERPC_EXCP_DSI; - if (rwx =3D=3D 1) { /* Write -> Store */ - cause |=3D DSISR_ISSTORE; - } env->spr[SPR_DSISR] =3D cause; env->spr[SPR_DAR] =3D eaddr; env->error_code =3D 0; + break; + default: + g_assert_not_reached(); } } =20 -static void ppc_radix64_raise_hsi(PowerPCCPU *cpu, int rwx, vaddr eaddr, - hwaddr g_raddr, uint32_t cause) +static void ppc_radix64_raise_hsi(PowerPCCPU *cpu, MMUAccessType access_ty= pe, + vaddr eaddr, hwaddr g_raddr, uint32_t ca= use) { CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; =20 - if (rwx =3D=3D 2) { /* H Instruction Storage Interrupt */ + switch (access_type) { + case MMU_INST_FETCH: + /* H Instruction Storage Interrupt */ cs->exception_index =3D POWERPC_EXCP_HISI; env->spr[SPR_ASDR] =3D g_raddr; env->error_code =3D cause; - } else { /* H Data Storage Interrupt */ + break; + case MMU_DATA_STORE: + cause |=3D DSISR_ISSTORE; + /* fall through */ + case MMU_DATA_LOAD: + /* H Data Storage Interrupt */ cs->exception_index =3D POWERPC_EXCP_HDSI; - if (rwx =3D=3D 1) { /* Write -> Store */ - cause |=3D DSISR_ISSTORE; - } env->spr[SPR_HDSISR] =3D cause; env->spr[SPR_HDAR] =3D eaddr; env->spr[SPR_ASDR] =3D g_raddr; env->error_code =3D 0; + break; + default: + g_assert_not_reached(); } } =20 -static bool ppc_radix64_check_prot(PowerPCCPU *cpu, int rwx, uint64_t pte, - int *fault_cause, int *prot, +static bool ppc_radix64_check_prot(PowerPCCPU *cpu, MMUAccessType access_t= ype, + uint64_t pte, int *fault_cause, int *pr= ot, bool partition_scoped) { CPUPPCState *env =3D &cpu->env; int need_prot; =20 /* Check Page Attributes (pte58:59) */ - if (((pte & R_PTE_ATT) =3D=3D R_PTE_ATT_NI_IO) && (rwx =3D=3D 2)) { + if ((pte & R_PTE_ATT) =3D=3D R_PTE_ATT_NI_IO && access_type =3D=3D MMU= _INST_FETCH) { /* * Radix PTE entries with the non-idempotent I/O attribute are tre= ated * as guarded storage @@ -159,7 +182,7 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, int= rwx, uint64_t pte, } =20 /* Check if requested access type is allowed */ - need_prot =3D prot_for_access_type(rwx); + need_prot =3D prot_for_access_type(access_type); if (need_prot & ~*prot) { /* Page Protected for that Access */ *fault_cause |=3D DSISR_PROTFAULT; return true; @@ -168,15 +191,15 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, i= nt rwx, uint64_t pte, return false; } =20 -static void ppc_radix64_set_rc(PowerPCCPU *cpu, int rwx, uint64_t pte, - hwaddr pte_addr, int *prot) +static void ppc_radix64_set_rc(PowerPCCPU *cpu, MMUAccessType access_type, + uint64_t pte, hwaddr pte_addr, int *prot) { CPUState *cs =3D CPU(cpu); uint64_t npte; =20 npte =3D pte | R_PTE_R; /* Always set reference bit */ =20 - if (rwx =3D=3D 1) { /* Store/Write */ + if (access_type =3D=3D MMU_DATA_STORE) { /* Store/Write */ npte |=3D R_PTE_C; /* Set change bit */ } else { /* @@ -271,7 +294,8 @@ static bool validate_pate(PowerPCCPU *cpu, uint64_t lpi= d, ppc_v3_pate_t *pate) return true; } =20 -static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu, int rwx, +static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu, + MMUAccessType access_type, vaddr eaddr, hwaddr g_raddr, ppc_v3_pate_t pate, hwaddr *h_raddr, int *h_prot, @@ -287,24 +311,25 @@ static int ppc_radix64_partition_scoped_xlate(PowerPC= CPU *cpu, int rwx, if (ppc_radix64_walk_tree(CPU(cpu)->as, g_raddr, pate.dw0 & PRTBE_R_RP= DB, pate.dw0 & PRTBE_R_RPDS, h_raddr, h_page_siz= e, &pte, &fault_cause, &pte_addr) || - ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, h_prot, true))= { + ppc_radix64_check_prot(cpu, access_type, pte, &fault_cause, h_prot= , true)) { if (pde_addr) { /* address being translated was that of a guest pd= e */ fault_cause |=3D DSISR_PRTABLE_FAULT; } if (guest_visible) { - ppc_radix64_raise_hsi(cpu, rwx, eaddr, g_raddr, fault_cause); + ppc_radix64_raise_hsi(cpu, access_type, eaddr, g_raddr, fault_= cause); } return 1; } =20 if (guest_visible) { - ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, h_prot); + ppc_radix64_set_rc(cpu, access_type, pte, pte_addr, h_prot); } =20 return 0; } =20 -static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, int rwx, +static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, + MMUAccessType access_type, vaddr eaddr, uint64_t pid, ppc_v3_pate_t pate, hwaddr *g_= raddr, int *g_prot, int *g_page_size, @@ -323,7 +348,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU = *cpu, int rwx, if (offset >=3D size) { /* offset exceeds size of the process table */ if (guest_visible) { - ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE); + ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_NOPTE); } return 1; } @@ -364,7 +389,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU = *cpu, int rwx, if (ret) { /* No valid PTE */ if (guest_visible) { - ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause); + ppc_radix64_raise_si(cpu, access_type, eaddr, fault_cause); } return ret; } @@ -393,7 +418,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU = *cpu, int rwx, if (ret) { /* No valid pte */ if (guest_visible) { - ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause); + ppc_radix64_raise_si(cpu, access_type, eaddr, fault_ca= use); } return ret; } @@ -407,16 +432,16 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCP= U *cpu, int rwx, *g_raddr =3D (rpn & ~mask) | (eaddr & mask); } =20 - if (ppc_radix64_check_prot(cpu, rwx, pte, &fault_cause, g_prot, false)= ) { + if (ppc_radix64_check_prot(cpu, access_type, pte, &fault_cause, g_prot= , false)) { /* Access denied due to protection */ if (guest_visible) { - ppc_radix64_raise_si(cpu, rwx, eaddr, fault_cause); + ppc_radix64_raise_si(cpu, access_type, eaddr, fault_cause); } return 1; } =20 if (guest_visible) { - ppc_radix64_set_rc(cpu, rwx, pte, pte_addr, g_prot); + ppc_radix64_set_rc(cpu, access_type, pte, pte_addr, g_prot); } =20 return 0; @@ -439,7 +464,8 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU = *cpu, int rwx, * | =3D On | Process Scoped | Scoped | * +-------------+----------------+---------------+ */ -static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, int rwx, +static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr eaddr, + MMUAccessType access_type, bool relocation, hwaddr *raddr, int *psizep, int *protp, bool guest_visible) @@ -453,7 +479,7 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr ead= dr, int rwx, /* Virtual Mode Access - get the fully qualified address */ if (!ppc_radix64_get_fully_qualified_addr(&cpu->env, eaddr, &lpid, &pi= d)) { if (guest_visible) { - ppc_radix64_raise_segi(cpu, rwx, eaddr); + ppc_radix64_raise_segi(cpu, access_type, eaddr); } return 1; } @@ -466,13 +492,13 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr e= addr, int rwx, } else { if (!ppc64_v3_get_pate(cpu, lpid, &pate)) { if (guest_visible) { - ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_NOPTE); + ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_NOPTE); } return 1; } if (!validate_pate(cpu, lpid, &pate)) { if (guest_visible) { - ppc_radix64_raise_si(cpu, rwx, eaddr, DSISR_R_BADCONFIG); + ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_R_BADC= ONFIG); } return 1; } @@ -490,7 +516,7 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr ead= dr, int rwx, * - Translates an effective address to a guest real address. */ if (relocation) { - int ret =3D ppc_radix64_process_scoped_xlate(cpu, rwx, eaddr, pid, + int ret =3D ppc_radix64_process_scoped_xlate(cpu, access_type, ead= dr, pid, pate, &g_raddr, &prot, &psize, guest_visible); if (ret) { @@ -513,9 +539,10 @@ static int ppc_radix64_xlate(PowerPCCPU *cpu, vaddr ea= ddr, int rwx, if (lpid || !msr_hv) { int ret; =20 - ret =3D ppc_radix64_partition_scoped_xlate(cpu, rwx, eaddr, g_= raddr, - pate, raddr, &prot, &= psize, - false, guest_visible); + ret =3D ppc_radix64_partition_scoped_xlate(cpu, access_type, e= addr, + g_raddr, pate, raddr, + &prot, &psize, false, + guest_visible); if (ret) { return ret; } @@ -536,12 +563,14 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vad= dr eaddr, int rwx, CPUPPCState *env =3D &cpu->env; int page_size, prot; bool relocation; + MMUAccessType access_type; hwaddr raddr; =20 assert(!(msr_hv && cpu->vhyp)); assert((rwx =3D=3D 0) || (rwx =3D=3D 1) || (rwx =3D=3D 2)); + access_type =3D rwx; =20 - relocation =3D ((rwx =3D=3D 2) && (msr_ir =3D=3D 1)) || ((rwx !=3D 2) = && (msr_dr =3D=3D 1)); + relocation =3D (access_type =3D=3D MMU_INST_FETCH ? msr_ir : msr_dr); /* HV or virtual hypervisor Real Mode Access */ if (!relocation && (msr_hv || cpu->vhyp)) { /* In real mode top 4 effective addr bits (mostly) ignored */ @@ -570,7 +599,7 @@ int ppc_radix64_handle_mmu_fault(PowerPCCPU *cpu, vaddr= eaddr, int rwx, } =20 /* Translate eaddr to raddr (where raddr is addr qemu needs for access= ) */ - if (ppc_radix64_xlate(cpu, eaddr, rwx, relocation, &raddr, + if (ppc_radix64_xlate(cpu, eaddr, access_type, relocation, &raddr, &page_size, &prot, true)) { return 1; } --=20 2.25.1