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[83.51.215.31]) by smtp.gmail.com with ESMTPSA id j14sm16735759wmj.19.2021.05.17.03.52.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:52:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GlSXe+rLjO5Sm+DFhb+DRpEt2vwp+8OnODDN1P00uBk=; b=W8v5ewV3Bdno7Txtdy4oFcQuokxSg6tEF86HSbkhdjYzIAl+L4ppgjqT6HW4GaveBo LtLgJHswCMjWD9Twdavox3X2krKFuH89MMyrP7Si4Tr84fr0QrLBBDqhy4TYOqsz7Eq/ toyB41+6p2ON3BG3X9c4HUwowH7PDQwUHzQqj7i/AH2qMyMyXrtZNYfBdpxvxlfDj3D2 bwyBeSJjEDQmdYI/69EV999JA2+Y/ynDsoU+7OuYUUn5o8nD6mcy97ZE/3HVn/FOG1Sh EE1bHaJlAZRXKrDEMSn25yLOs8tqDKdzmiSum80bZj4ONrhN9b70A/CAvN6V0Y+bhjML NHPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=GlSXe+rLjO5Sm+DFhb+DRpEt2vwp+8OnODDN1P00uBk=; b=nW9GJrfls+c5WMDFhrLwX1ylI3C74iJembIsi047IKVGVfQMhNgpFvIDU3T9qLF+dL jWLaxE6IraJ1F+938xOzm0vPrO4zkf76w3G3D/zs/r4tJ75MPoxAoZ0Sw4wcpKh6wM/s TxjaMsYgR53dmGhu3Bf4z13uYKZ9tFRsuRvZpaKtnIcoKnyHDhm0WDNoSe6DeVFMy0sA CefwvYq8BtGyTDMdysx8S0kd6j5dejZ9SvlQIIz56BwvR5tEEz9mfLnSofOuGBqREykN 9eyC9P2C6cEHvjn2Pxje/WsC/SZp7kinT9XsMazZr1G4VMd3vs3f9Et+2DW3QZgsLmiR 0X9A== X-Gm-Message-State: AOAM533mv/k5qvdx1K2MDb/hTeGFFv8ddiUknxdE/rV7OYNuL5C5+sfe T2EBAoYiHu6jChgr2SkuIkYrEDX2pqOM4A== X-Google-Smtp-Source: ABdhPJw1sNKQoNDS2hyfIPpw5MArCNHnqmjL26abifhPojGm7NExft4qIayqq4ekMm4w0AunGOr/5A== X-Received: by 2002:a5d:4e91:: with SMTP id e17mr11136051wru.396.1621248731341; Mon, 17 May 2021 03:52:11 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 06/23] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs Date: Mon, 17 May 2021 12:51:23 +0200 Message-Id: <20210517105140.1062037-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To be able to later extract the cpu_get_phys_page_debug() and cpu_asidx_from_attrs() handlers from CPUClass, un-inline them from "hw/core/cpu.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 33 ++++----------------------------- hw/core/cpu-sysemu.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 29 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index d45f78290e0..df495287850 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -586,18 +586,8 @@ void cpu_dump_statistics(CPUState *cpu, int flags); * * Returns: Corresponding physical page address or -1 if no page found. */ -static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr ad= dr, - MemTxAttrs *attrs) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - if (cc->get_phys_page_attrs_debug) { - return cc->get_phys_page_attrs_debug(cpu, addr, attrs); - } - /* Fallback for CPUs which don't implement the _attrs_ hook */ - *attrs =3D MEMTXATTRS_UNSPECIFIED; - return cc->get_phys_page_debug(cpu, addr); -} +hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); =20 /** * cpu_get_phys_page_debug: @@ -609,12 +599,7 @@ static inline hwaddr cpu_get_phys_page_attrs_debug(CPU= State *cpu, vaddr addr, * * Returns: Corresponding physical page address or -1 if no page found. */ -static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) -{ - MemTxAttrs attrs =3D {}; - - return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); -} +hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 /** cpu_asidx_from_attrs: * @cpu: CPU @@ -623,17 +608,7 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState = *cpu, vaddr addr) * Returns the address space index specifying the CPU AddressSpace * to use for a memory access with the given transaction attributes. */ -static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - int ret =3D 0; - - if (cc->asidx_from_attrs) { - ret =3D cc->asidx_from_attrs(cpu, attrs); - assert(ret < cpu->num_ases && ret >=3D 0); - } - return ret; -} +int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); =20 #endif /* CONFIG_USER_ONLY */ =20 diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index f517ef5d460..fe90dde8681 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -22,6 +22,38 @@ #include "qapi/error.h" #include "hw/core/cpu.h" =20 +hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->get_phys_page_attrs_debug) { + return cc->get_phys_page_attrs_debug(cpu, addr, attrs); + } + /* Fallback for CPUs which don't implement the _attrs_ hook */ + *attrs =3D MEMTXATTRS_UNSPECIFIED; + return cc->get_phys_page_debug(cpu, addr); +} + +hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) +{ + MemTxAttrs attrs =3D {}; + + return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); +} + +int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + int ret =3D 0; + + if (cc->asidx_from_attrs) { + ret =3D cc->asidx_from_attrs(cpu, attrs); + assert(ret < cpu->num_ases && ret >=3D 0); + } + return ret; +} + GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); --=20 2.26.3