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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 8 -------- include/hw/core/sysemu-cpu-ops.h | 13 +++++++++++++ target/alpha/cpu.h | 2 +- target/arm/cpu.h | 6 +++--- target/cris/cpu.h | 4 ++-- target/hppa/cpu.h | 2 +- target/i386/cpu.h | 6 +++--- target/m68k/cpu.h | 5 ++++- target/microblaze/cpu.h | 5 ++--- target/nios2/cpu.h | 2 +- target/openrisc/cpu.h | 3 ++- target/ppc/cpu.h | 2 +- target/riscv/cpu.h | 2 +- target/rx/cpu.h | 2 ++ target/sh4/cpu.h | 2 +- target/sparc/cpu.h | 2 +- target/tricore/cpu.h | 2 ++ target/xtensa/cpu.h | 2 +- hw/core/cpu-sysemu.c | 6 +++--- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 38 files changed, 63 insertions(+), 51 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index cbc43f11376..b4d3a21bbf0 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -103,11 +103,6 @@ struct AccelCPUClass; * If the target behaviour here is anything other than "set * the PC register to the value passed in" then the target must * also implement the synchronize_from_tb hook. - * @get_phys_page_debug: Callback for obtaining a physical address. - * @get_phys_page_attrs_debug: Callback for obtaining a physical address a= nd the - * associated memory transaction attributes to use for the access. - * CPUs which use memory transaction attributes should implement this - * instead of get_phys_page_debug. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -146,9 +141,6 @@ struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); - hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 894bb95e4fa..7f8ff641854 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,19 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_phys_page_debug: Callback for obtaining a physical address. + */ + hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); + /** + * @get_phys_page_attrs_debug: Callback for obtaining a physical addre= ss + * and the associated memory transaction attributes to use for t= he + * access. + * CPUs which use memory transaction attributes should implement this + * instead of get_phys_page_debug. + */ + hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); /** * @asidx_from_attrs: Callback to return the CPU AddressSpace to use f= or * a memory access with the specified memory transaction attribu= tes. diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 6541675d9d6..cb3021c1afa 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -275,6 +275,7 @@ struct AlphaCPU { #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_alpha_cpu; =20 +hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); @@ -283,7 +284,6 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr= addr, void alpha_cpu_do_interrupt(CPUState *cpu); bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req); void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags); -hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 616b3932534..1129b5ec0cc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1026,15 +1026,15 @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clust= ersz); =20 #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_arm_cpu; + +hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); #endif =20 void arm_cpu_do_interrupt(CPUState *cpu); void arm_v7m_cpu_do_interrupt(CPUState *cpu); bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); =20 -hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); - int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/target/cris/cpu.h b/target/cris/cpu.h index d3b64929096..aac921e221a 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -185,6 +185,8 @@ struct CRISCPU { =20 #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_cris_cpu; + +hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); #endif =20 void cris_cpu_do_interrupt(CPUState *cpu); @@ -193,8 +195,6 @@ bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req= ); =20 void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags); =20 -hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); - int crisv10_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 748270bfa31..d125aeac1d3 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -322,7 +322,6 @@ void cpu_hppa_change_prot_id(CPUHPPAState *env); #define cpu_signal_handler cpu_hppa_signal_handler =20 int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); -hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_do_interrupt(CPUState *cpu); @@ -332,6 +331,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); #ifndef CONFIG_USER_ONLY +hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, int type, hwaddr *pphys, int *pprot); extern const MemoryRegionOps hppa_io_eir_ops; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 324ef92beb7..27a7214debe 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1800,6 +1800,9 @@ struct X86CPU { =20 #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_x86_cpu; + +hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); #endif =20 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); @@ -1818,9 +1821,6 @@ void x86_cpu_get_memory_mapping(CPUState *cpu, Memory= MappingList *list, =20 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); =20 -hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); - int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index cf58fee9ada..7b17f59d40f 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -169,10 +169,13 @@ struct M68kCPU { void m68k_cpu_do_interrupt(CPUState *cpu); bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 +#if !defined(CONFIG_USER_ONLY) +hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +#endif + void m68k_tcg_init(void); void m68k_cpu_init_gdb(M68kCPU *cpu); /* diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 348540c7640..444dc487456 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -358,8 +358,6 @@ struct MicroBlazeCPU { void mb_cpu_do_interrupt(CPUState *cs); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 @@ -417,7 +415,8 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env= , target_ulong *pc, } =20 #if !defined(CONFIG_USER_ONLY) - +hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index aa7b5cc9e16..75b0c9924bb 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -196,8 +196,8 @@ void nios2_cpu_do_interrupt(CPUState *cs); int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc); void dump_mmu(CPUNios2State *env); void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); #ifndef CONFIG_USER_ONLY +hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 82cbaeb4f84..33ab91719c2 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -315,7 +315,6 @@ void cpu_openrisc_list(void); void openrisc_cpu_do_interrupt(CPUState *cpu); bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg= ); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); @@ -331,6 +330,8 @@ int print_insn_or1k(bfd_vma addr, disassemble_info *inf= o); #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_openrisc_cpu; =20 +hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); + /* hw/openrisc_pic.c */ void cpu_openrisc_pic_init(OpenRISCCPU *cpu); =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 733a2168c48..69978fe0d9b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1261,7 +1261,6 @@ void ppc_cpu_do_interrupt(CPUState *cpu); bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req); void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); void ppc_cpu_dump_statistics(CPUState *cpu, int flags); -hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int re= g); int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); @@ -1275,6 +1274,7 @@ int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction = f, CPUState *cs, int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, void *opaque); #ifndef CONFIG_USER_ONLY +hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void ppc_cpu_do_system_reset(CPUState *cs); void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector); extern const VMStateDescription vmstate_ppc_cpu; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2dd66401127..6713bf6fb44 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -339,7 +339,6 @@ bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *en= v); void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); -hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); @@ -351,6 +350,7 @@ void riscv_cpu_list(void); #define cpu_mmu_index riscv_cpu_mmu_index =20 #ifndef CONFIG_USER_ONLY +hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 0b4b998c7be..2b7595ff372 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -129,7 +129,9 @@ bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req); void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +#ifndef CONFIG_USER_ONLY hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +#endif =20 void rx_translate_init(void); int cpu_rx_signal_handler(int host_signum, void *pinfo, diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index e41337a101d..64870023e31 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -207,7 +207,6 @@ struct SuperHCPU { void superh_cpu_do_interrupt(CPUState *cpu); bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 @@ -237,6 +236,7 @@ uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s, hwaddr addr); void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr, uint32_t mem_value); +hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 60ff6306980..79e28eb2182 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -569,6 +569,7 @@ struct SPARCCPU { #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_sparc_cpu; =20 +hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, @@ -577,7 +578,6 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUSta= te *cpu, vaddr addr, =20 void sparc_cpu_do_interrupt(CPUState *cpu); void sparc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN; diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 4b61a2c03f8..0892ae647dc 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -207,7 +207,9 @@ struct TriCoreCPU { }; =20 =20 +#ifndef CONFIG_USER_ONLY hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +#endif void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags); =20 =20 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index d08e60c673e..d40d8b7d863 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -570,7 +570,6 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void xtensa_count_regs(const XtensaConfig *config, unsigned *n_regs, unsigned *n_core_regs); int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); @@ -668,6 +667,7 @@ static inline int xtensa_get_cring(const CPUXtensaState= *env) } =20 #ifndef CONFIG_USER_ONLY +hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index ba53c2eaa85..b31c33ad2b5 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -52,12 +52,12 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vad= dr addr, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_phys_page_attrs_debug) { - return cc->get_phys_page_attrs_debug(cpu, addr, attrs); + if (cc->sysemu_ops->get_phys_page_attrs_debug) { + return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs); } /* Fallback for CPUs which don't implement the _attrs_ hook */ *attrs =3D MEMTXATTRS_UNSPECIFIED; - return cc->get_phys_page_debug(cpu, addr); + return cc->sysemu_ops->get_phys_page_debug(cpu, addr); } =20 hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index cd01d34d92f..979a4c0be1e 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps alpha_sysemu_ops =3D { + .get_phys_page_debug =3D alpha_cpu_get_phys_page_debug, }; #endif =20 @@ -241,7 +242,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D alpha_cpu_gdb_read_register; cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_alpha_cpu; cc->sysemu_ops =3D &alpha_sysemu_ops; #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f8fc0d01956..f29649ecba7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1944,6 +1944,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, .write_elf64_note =3D arm_cpu_write_elf64_note, @@ -1989,7 +1990,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 5c8bb9b3fec..a357ff0bffb 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) } =20 static const struct SysemuCPUOps avr_sysemu_ops =3D { + .get_phys_page_debug =3D avr_cpu_get_phys_page_debug, }; =20 #include "hw/core/tcg-cpu-ops.h" @@ -215,7 +216,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; - cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; dc->vmsd =3D &vms_avr_cpu; cc->sysemu_ops =3D &avr_sysemu_ops; cc->disas_set_info =3D avr_cpu_disas_set_info; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 394df655c9f..58193c02cbf 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps cris_sysemu_ops =3D { + .get_phys_page_debug =3D cris_cpu_get_phys_page_debug, }; #endif =20 @@ -297,7 +298,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D cris_cpu_gdb_read_register; cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_cris_cpu; cc->sysemu_ops =3D &cris_sysemu_ops; #endif diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 6605c42e509..0d755b8a880 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps hppa_sysemu_ops =3D { + .get_phys_page_debug =3D hppa_cpu_get_phys_page_debug, }; #endif =20 @@ -166,7 +167,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_hppa_cpu; cc->sysemu_ops =3D &hppa_sysemu_ops; #endif diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d050245b502..1092305cb43 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6716,6 +6716,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, .write_elf32_note =3D x86_cpu_write_elf32_note, @@ -6754,7 +6755,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) =20 #ifndef CONFIG_USER_ONLY cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; - cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 600812d682b..f743a86c7d5 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -505,6 +505,7 @@ static const VMStateDescription vmstate_m68k_cpu =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps m68k_sysemu_ops =3D { + .get_phys_page_debug =3D m68k_cpu_get_phys_page_debug, }; #endif =20 @@ -538,7 +539,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D m68k_cpu_gdb_read_register; cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) - cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_m68k_cpu; cc->sysemu_ops =3D &m68k_sysemu_ops; #endif diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index c6a10b1a52b..8ccac373631 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cp= u_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps mb_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug, }; #endif =20 @@ -391,7 +392,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->gdb_write_register =3D mb_cpu_gdb_write_register; =20 #ifndef CONFIG_USER_ONLY - cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; dc->vmsd =3D &vmstate_mb_cpu; cc->sysemu_ops =3D &mb_sysemu_ops; #endif diff --git a/target/mips/cpu.c b/target/mips/cpu.c index a74b7fab318..c65fb4607f6 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -523,6 +523,7 @@ static Property mips_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps mips_sysemu_ops =3D { + .get_phys_page_debug =3D mips_cpu_get_phys_page_debug, .legacy_vmsd =3D &vmstate_mips_cpu, }; #endif @@ -566,7 +567,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->sysemu_ops =3D &mips_sysemu_ops; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 296ccc0ed3c..f3b51732c29 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -209,6 +209,7 @@ static Property nios2_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps nios2_sysemu_ops =3D { + .get_phys_page_debug =3D nios2_cpu_get_phys_page_debug, }; #endif =20 @@ -242,7 +243,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D nios2_cpu_set_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; cc->sysemu_ops =3D &nios2_sysemu_ops; #endif cc->gdb_read_register =3D nios2_cpu_gdb_read_register; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index cd8e3ae6754..babe637cda6 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps openrisc_sysemu_ops =3D { + .get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug, }; #endif =20 @@ -208,7 +209,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_openrisc_cpu; cc->sysemu_ops =3D &openrisc_sysemu_ops; #endif diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d86e44ca07d..29b829e9484 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -598,6 +598,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *= cs, const char *xmlname) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps riscv_sysemu_ops =3D { + .get_phys_page_debug =3D riscv_cpu_get_phys_page_debug, .write_elf64_note =3D riscv_cpu_write_elf64_note, .write_elf32_note =3D riscv_cpu_write_elf32_note, .legacy_vmsd =3D &vmstate_riscv_cpu, @@ -645,7 +646,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; cc->sysemu_ops =3D &riscv_sysemu_ops; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index bbee1cb913f..e76b7708b89 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -175,6 +175,7 @@ static void rx_cpu_init(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps rx_sysemu_ops =3D { + .get_phys_page_debug =3D rx_cpu_get_phys_page_debug, }; #endif =20 @@ -212,7 +213,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) #endif cc->gdb_read_register =3D rx_cpu_gdb_read_register; cc->gdb_write_register =3D rx_cpu_gdb_write_register; - cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; cc->disas_set_info =3D rx_cpu_disas_set_info; =20 cc->gdb_num_core_regs =3D 26; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 058ffcef15f..e32265a61eb 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -478,6 +478,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps s390_sysemu_ops =3D { + .get_phys_page_debug =3D s390_cpu_get_phys_page_debug, .get_crash_info =3D s390_cpu_get_crash_info, .write_elf64_note =3D s390_cpu_write_elf64_note, .legacy_vmsd =3D &vmstate_s390_cpu, @@ -523,7 +524,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D s390_cpu_gdb_read_register; cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; cc->sysemu_ops =3D &s390_sysemu_ops; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 85e15ec9954..09de295cf91 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -225,6 +225,7 @@ static const VMStateDescription vmstate_sh_cpu =3D { }; =20 static const struct SysemuCPUOps sh4_sysemu_ops =3D { + .get_phys_page_debug =3D superh_cpu_get_phys_page_debug, }; #endif =20 @@ -261,7 +262,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; cc->sysemu_ops =3D &sh4_sysemu_ops; dc->vmsd =3D &vmstate_sh_cpu; #endif diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 543853c24dc..90658ba8e61 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps sparc_sysemu_ops =3D { + .get_phys_page_debug =3D sparc_cpu_get_phys_page_debug, .legacy_vmsd =3D &vmstate_sparc_cpu, }; #endif @@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &sparc_sysemu_ops; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 8865fa18fce..4572dde1486 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -143,6 +143,7 @@ static void tc27x_initfn(Object *obj) } =20 static const struct SysemuCPUOps tricore_sysemu_ops =3D { + .get_phys_page_debug =3D tricore_cpu_get_phys_page_debug, }; =20 #include "hw/core/tcg-cpu-ops.h" @@ -173,7 +174,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) =20 cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; - cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; cc->sysemu_ops =3D &tricore_sysemu_ops; cc->tcg_ops =3D &tricore_tcg_ops; } diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index d0bf06696e4..eb61ee55be4 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -183,6 +183,7 @@ static const VMStateDescription vmstate_xtensa_cpu =3D { }; =20 static const struct SysemuCPUOps xtensa_sysemu_ops =3D { + .get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug, }; #endif =20 @@ -221,7 +222,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_stop_before_watchpoint =3D true; #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &xtensa_sysemu_ops; - cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_xtensa_cpu; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 86b11e1356a..fd252ba72c9 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10239,6 +10239,7 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps ppc_sysemu_ops =3D { + .get_phys_page_debug =3D ppc_cpu_get_phys_page_debug, .write_elf32_note =3D ppc32_cpu_write_elf32_note, .write_elf64_note =3D ppc64_cpu_write_elf64_note, .virtio_is_big_endian =3D ppc_cpu_is_big_endian, @@ -10287,7 +10288,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_read_register =3D ppc_cpu_gdb_read_register; cc->gdb_write_register =3D ppc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &ppc_sysemu_ops; #endif =20 --=20 2.26.3