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[83.51.215.31]) by smtp.gmail.com with ESMTPSA id a16sm5196820wrw.62.2021.05.17.03.51.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:51:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QZd/87Z8RVp2dDQlE17s2j2kfbwKqcNh9feGLDEoUT0=; b=GSJGoC87NqEgxIwzRO1/6LBWqPZpuXPMZ0uXbz4T/sNWuMmbCnnuvO7vO19vrn5mNF sldOSfayHYF1gvCoJwMKAuj+1QCwKii25COszYAQyXKK8eumUNbi4P2D57Su8hFGp38L UzO5eLOhyMbUNxc+xkdcMlyo5We4ZxKSOaZlxAB4+UusHK6++x+vTdzaTMtFs7qXNgyr TLlH4pL+xNorKOAz4mzmTj+Z5YkNYRdaN5upqg1IfxNSz0ETlQL/XSupu21ISEw5WrN7 WzE1u9OxS7aigVnYQfwLOckiW1U+1/itET15BsDkLkUPkWz/ee7jiSfEQhcTkLKUadYJ fTtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=QZd/87Z8RVp2dDQlE17s2j2kfbwKqcNh9feGLDEoUT0=; b=hFhPmi3qOqkQ6wlBzdU94kD7KIR1lpCSQC1I4i/09upmpo5JzI3Sl08RwVPMiI+rBF 4x35iGrF1j48mg0uoUzN8euqGdIZ8g9/QcOkjLHM+IymFJoRBGiY/WfU4obliIxPdBq2 /T5jDzkXK2AW5wqyIRArX+A80UMR33NVH1eRvBzidncSRPaJAg18twNjvrGiGCNCBViu hpbzCn2mSQboCdFIeDOhbhkNWFeJkOgCQyUnzotaTVhYyCaqneoQJ1UUpLv+ujA5oh45 Nyz9Ou0P5Y/rCYaNZb7mmn00DqPrYclZGfizbdO+aFUn5SV6sDekRelbgnZd9ak0+2+d MIIw== X-Gm-Message-State: AOAM5331v4APwzXVBDqAiWt1bmxCCzNiQjO3xa+VchyINNP7S3/pTgI4 TMSDgQd/p7TiGGPIwzGHvmE= X-Google-Smtp-Source: ABdhPJzhNebuAkLW9FHYgk5dryRkSRcYzk4irc187D11kKRvi8sz5wu5anMgKLHUbWLPWuM4n77riw== X-Received: by 2002:a1c:7501:: with SMTP id o1mr64620985wmc.65.1621248707826; Mon, 17 May 2021 03:51:47 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 01/23] NOTFORMERGE target/arm: Restrict MTE code to softmmu Date: Mon, 17 May 2021 12:51:18 +0200 Message-Id: <20210517105140.1062037-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The following patches require the "arm cleanup experiment for kvm-only build" [*] series with split various user/sysemu and tcg/kvm code from the target/arm/ directory. To be able to build the following patches waiting the series get merged, simply restrict the MTE code to the softmmu source set. [*] https://lists.gnu.org/archive/html/qemu-devel/2021-04/msg02908.html Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/meson.build | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/arm/meson.build b/target/arm/meson.build index 5bfaf43b500..09802ba1a17 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -41,7 +41,6 @@ 'cpu64.c', 'gdbstub64.c', 'helper-a64.c', - 'mte_helper.c', 'pauth_helper.c', 'sve_helper.c', 'translate-a64.c', @@ -49,6 +48,11 @@ )) =20 arm_softmmu_ss =3D ss.source_set() + +arm_softmmu_ss.add(when: 'TARGET_AARCH64', if_true: files( + 'mte_helper.c', +)) + arm_softmmu_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) client-ip=209.85.221.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1621248714; cv=none; d=zohomail.com; s=zohoarc; b=eXFgd7J+Kj8cajzFnTBfan4uM7Y3TCbc+xUtA4uWFsP9fSqZAKVSVsB95CyvWFNM+6dRItTEU3rWY+xwW5XWktg67BrSzF3prz/EXzr2HPDQ4ZO1xWlBiFsHxbjvpgG/J9lFs+8MEhzBrL8oi2fHBQacLy2pG7ir4EzoWFOtpII= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621248714; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=J++NDLnF3ZLjQJuDikbfz+qqlVxXQCnKQi7mCfFvCw8=; b=iMWWSpTXm+cU+69F0sI0ha/YeT6iOHVrcxk/EYJ/SLILyPzpCU4BBwrgNZHil6BZghDVEla2erEdf7x/B+E+Fvt54lrLefrv6qXoFyjs2uCSpqZ5IvTqfi0Rc0S0aG8K0zDtNITdSBbCbIHlWGlkM+UC0Miof54zsRSXiwpSmiw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) by mx.zohomail.com with SMTPS id 16212487144488.162102520875692; Mon, 17 May 2021 03:51:54 -0700 (PDT) Received: by mail-wr1-f47.google.com with SMTP id d11so5865837wrw.8 for ; Mon, 17 May 2021 03:51:53 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (31.red-83-51-215.dynamicip.rima-tde.net. [83.51.215.31]) by smtp.gmail.com with ESMTPSA id t13sm349995wmi.2.2021.05.17.03.51.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:51:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J++NDLnF3ZLjQJuDikbfz+qqlVxXQCnKQi7mCfFvCw8=; b=mZTsOjj3LWDbZgvFyA7NV3RaiQb1WFhBGbE1A1hLQLSWZ6lbo9cF/JTYOaDceQ+ZR4 ZnUESu8TKoJuRoL2A/ujqULQjEg2laKgYu8Z+UwG/dziXYracDTo6VJw26wq5LMW/VU0 vObsTR2/yjxbdBvJHwDtPNC5r9XPXnd03o5/fKog96aqtxbv4fjVMr8fwlDrujWrBkTG gtqqkLDwXEZhZdPJDpcsN8XZrETQCfLhDNC5Y/zUFsARR1yN0UcX352zl9homP9Qy/pm 4myGEfTSWFr5c9l6tktkzx8odsuSEykaxWDPbax4WEYcSXucDgct69PGNnnHEAIorZ3J ih5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=J++NDLnF3ZLjQJuDikbfz+qqlVxXQCnKQi7mCfFvCw8=; b=STi6He1MCNZ+qOkX7/E5iohjdKWirFPoXp0yXYk+S6FnEyZWUrpEYimZaL6JmczVeY O40eL66t5v1VMKCy65fWUbLZA1clKmQ20z8KeiALgF3jo6L3lL2xAqU+MeBlMachUjlG 1OjZnPp5hlqIsGE+yEVzXCcqKakKhTZvQ1N8BJp2fYafaMzBV5QE2M5QzPQtaswhTtPM jgPyfUpY7KTfNqNJqqGfXBK8RkpfvweNpuJqg18GyTFWN6ruT2/f8Tz6fgsfLrurUcMR shMO2vQwWfCA9blylS/EmOaKz7BtmEAej8xlByrbX17WiBaBt/p4/HBxFx7EtsqjL3P1 TFpQ== X-Gm-Message-State: AOAM531CFAir4xodzp2pjTL56Nvgr0maSvpSUmkSt4JJAYPDnlFlJkya TEWeQ6m7G7vjPo1pcAYnphE= X-Google-Smtp-Source: ABdhPJzv3VIwKFhk6zkwm9PrX+5xBZFFYOPB7ZnN/gWssFbJ0ycPkS71ak1ykFXNEIMtnjcn8jX/PA== X-Received: by 2002:a5d:4c48:: with SMTP id n8mr17063451wrt.422.1621248712701; Mon, 17 May 2021 03:51:52 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 02/23] cpu: Restrict target cpu_do_transaction_failed() handlers to sysemu Date: Mon, 17 May 2021 12:51:19 +0200 Message-Id: <20210517105140.1062037-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) In commit cbc183d2d9f ("cpu: move cc->transaction_failed to tcg_ops") we restricted the do_transaction_failed() handler to the sysemu part of TCGCPUOps, but forgot to restrict the target specific declarations. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/internals.h | 2 ++ target/m68k/cpu.h | 2 ++ target/riscv/cpu.h | 10 +++++----- target/xtensa/cpu.h | 8 ++++---- 4 files changed, 13 insertions(+), 9 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 886db56b580..3614f6dd988 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -583,6 +583,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr va= ddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); =20 +#if !defined(CONFIG_USER_ONLY) /* arm_cpu_do_transaction_failed: handle a memory system error response * (eg "no device/memory present at address") by raising an external abort * exception @@ -592,6 +593,7 @@ void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr= physaddr, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr= ); +#endif =20 /* Call any registered EL change hooks */ static inline void arm_call_pre_el_change_hook(ARMCPU *cpu) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 402c86c8769..cf58fee9ada 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -572,10 +572,12 @@ static inline int cpu_mmu_index (CPUM68KState *env, b= ool ifetch) bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#if !defined(CONFIG_USER_ONLY) void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); +#endif =20 typedef CPUM68KState CPUArchState; typedef M68kCPU ArchCPU; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0619b491a42..aa19d8f304e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -346,11 +346,6 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t retad= dr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); =20 @@ -359,6 +354,11 @@ void riscv_cpu_list(void); #define cpu_mmu_index riscv_cpu_mmu_index =20 #ifndef CONFIG_USER_ONLY +void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retad= dr); void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value= ); diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 3bd4f691c1a..cbe9e5ff230 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -569,10 +569,6 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, bool probe, uintptr_t retaddr); void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); -void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, - unsigned size, MMUAccessType access_= type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t reta= ddr); void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void xtensa_count_regs(const XtensaConfig *config, @@ -675,6 +671,10 @@ static inline int xtensa_get_cring(const CPUXtensaStat= e *env) } =20 #ifndef CONFIG_USER_ONLY +void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, + unsigned size, MMUAccessType access_= type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t reta= ddr); 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[83.51.215.31]) by smtp.gmail.com with ESMTPSA id v10sm19368812wrq.0.2021.05.17.03.51.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:51:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4y6dJ5W0jRFDoCjc5ce7xU1qdLgWVyXVf+o6CYpimiI=; b=aw+C6wdMWzjcpiu4fDUBOAlZauufWX6TuW/sg846ikpCQUJGPOKW1YZZs1/MlgcScV 4ZtXduOr50cxLAfOgfFHne/MvW05sEhbvuZRgmlQvbddj7FwXQPWqQsTqtI/M4EdUnm2 snC1E6VAMz8q2LlGlrIJB7fiwihs0eXYloynKjktAGhKAHVIQRBlC+3/F/ruTJbQg5OG Xk2XHlf+M+POoM1o3PmMo+Ti+jhlf3xJ9Zy/PIeDx/xFmYMPIR7ok1cx5Xa5p4BAj93O fDgnqKmL4k0Wz/ylpr8BJApCS8u0Gh6zoigX2Jwa4sAYmguH+MO5vG+pL25nT2WDDic6 3UMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=4y6dJ5W0jRFDoCjc5ce7xU1qdLgWVyXVf+o6CYpimiI=; b=bQlC/VudUPNPyJhk+ReIGLvqHG2zhhX64BdhkiZgGK2+bcjOwXZO31bZZtl2EyckJr sHNiqAGvbcoI+Ia1VqoGCJWknTuU8Dsw3SacBLxo/4xkLQgmH3thDw36iQcCpVeyuWCw NetFB9mKycPYkiEgJnX1gCjX2PmMnefL+Kp/f19e2crNBkzgI0Vj2WXAEjeKGuqvPQEh Ef9lOyJTFyUlhfWBrebpGRpo3xf9WL/dQqFWZPEtPI7sa5BnS8HKniA/2y+vT32Y6h0H sUnNJp02tXalYwwzWqYPciJMTT5I8y3xn4yzyJ/LNOSwItCLpXLjUOG2twNd3JIs7uA4 0USg== X-Gm-Message-State: AOAM533p8zKKql8g+ZJw3w37aTUyqTuZqRGWMLUqdjOmxqrXoMTOEaN1 T0m25gau3J/aA2yuJPlfImg= X-Google-Smtp-Source: ABdhPJy2HLFQ9itghdh5t5I8R9nM1Cq5j9WeAFNyq65dzmeZevg1VDJLJ1g5gDIz+E5gf654Ff0+og== X-Received: by 2002:adf:d081:: with SMTP id y1mr17663319wrh.179.1621248717377; Mon, 17 May 2021 03:51:57 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 03/23] cpu: Restrict target cpu_do_unaligned_access() handlers to sysemu Date: Mon, 17 May 2021 12:51:20 +0200 Message-Id: <20210517105140.1062037-4-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Commit 8535dd702dd ("cpu: move do_unaligned_access to tcg_ops") restricted the do_unaligned_access() handler to the sysemu part of TCGCPUOps, but only restricted the HPPA declaration. Restrict the other targets. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/alpha/cpu.h | 7 ++++--- target/arm/internals.h | 2 +- target/microblaze/cpu.h | 7 ++++--- target/mips/tcg/tcg-internal.h | 6 +++--- target/nios2/cpu.h | 3 ++- target/ppc/internal.h | 2 ++ target/riscv/cpu.h | 6 +++--- target/s390x/internal.h | 2 ++ target/sh4/cpu.h | 6 +++--- target/sparc/cpu.h | 9 +++++---- target/xtensa/cpu.h | 6 +++--- target/arm/tlb_helper.c | 4 ++-- target/microblaze/helper.c | 35 +++++++++++++++++----------------- target/ppc/excp_helper.c | 3 ++- target/sparc/ldst_helper.c | 5 ++--- 15 files changed, 56 insertions(+), 47 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 82df108967b..6541675d9d6 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -274,6 +274,10 @@ struct AlphaCPU { =20 #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_alpha_cpu; + +void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); #endif =20 void alpha_cpu_do_interrupt(CPUState *cpu); @@ -282,9 +286,6 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags); hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); =20 #define cpu_list alpha_cpu_list #define cpu_signal_handler cpu_alpha_signal_handler diff --git a/target/arm/internals.h b/target/arm/internals.h index 3614f6dd988..a31e56602f5 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -578,12 +578,12 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *e= nv, bool secstate); * tables */ bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx); =20 +#if !defined(CONFIG_USER_ONLY) /* Raise a data fault alignment exception for the specified virtual addres= s */ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); =20 -#if !defined(CONFIG_USER_ONLY) /* arm_cpu_do_transaction_failed: handle a memory system error response * (eg "no device/memory present at address") by raising an external abort * exception diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e4bba8a7551..348540c7640 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -357,9 +357,6 @@ struct MicroBlazeCPU { =20 void mb_cpu_do_interrupt(CPUState *cs); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); -void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); @@ -420,6 +417,10 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *en= v, target_ulong *pc, } =20 #if !defined(CONFIG_USER_ONLY) + +void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h index 81b14eb219e..11d98a717f2 100644 --- a/target/mips/tcg/tcg-internal.h +++ b/target/mips/tcg/tcg-internal.h @@ -23,9 +23,6 @@ bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); =20 const char *mips_exception_name(int32_t exception); =20 @@ -57,6 +54,9 @@ void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr = physaddr, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retadd= r); +void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); void cpu_mips_tlb_flush(CPUMIPSState *env); =20 #endif /* !CONFIG_USER_ONLY */ diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 2ab82fdc713..aa7b5cc9e16 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -197,10 +197,11 @@ int cpu_nios2_signal_handler(int host_signum, void *p= info, void *puc); void dump_mmu(CPUNios2State *env); void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags); hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +#ifndef CONFIG_USER_ONLY void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); - +#endif void do_nios2_semihosting(CPUNios2State *env); =20 #define CPU_RESOLVING_TYPE TYPE_NIOS2_CPU diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 184ba6d6b3b..40b29bda75f 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -211,10 +211,12 @@ void helper_compute_fprf_float16(CPUPPCState *env, fl= oat16 arg); void helper_compute_fprf_float32(CPUPPCState *env, float32 arg); void helper_compute_fprf_float128(CPUPPCState *env, float128 arg); =20 +#if !defined(CONFIG_USER_ONLY) /* Raise a data fault alignment exception for the specified virtual addres= s */ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); +#endif =20 /* translate.c */ =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index aa19d8f304e..2dd66401127 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -340,9 +340,6 @@ void riscv_cpu_set_force_hs_excep(CPURISCVState *env, b= ool enable); bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr); bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); @@ -354,6 +351,9 @@ void riscv_cpu_list(void); #define cpu_mmu_index riscv_cpu_mmu_index =20 #ifndef CONFIG_USER_ONLY +void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr); void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, diff --git a/target/s390x/internal.h b/target/s390x/internal.h index 11515bb6173..b65b2a402c3 100644 --- a/target/s390x/internal.h +++ b/target/s390x/internal.h @@ -269,9 +269,11 @@ bool s390_cpu_exec_interrupt(CPUState *cpu, int int_re= q); bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); +#if !defined(CONFIG_USER_ONLY) void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); +#endif =20 =20 /* fpu_helper.c */ diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 01c43440822..e41337a101d 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -210,9 +210,6 @@ void superh_cpu_dump_state(CPUState *cpu, FILE *f, int = flags); hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); =20 void sh4_translate_init(void); int cpu_sh4_signal_handler(int host_signum, void *pinfo, @@ -240,6 +237,9 @@ uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s, hwaddr addr); void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr, uint32_t mem_value); +void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); #endif =20 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr); diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index ff8ae73002a..60ff6306980 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -568,6 +568,11 @@ struct SPARCCPU { =20 #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_sparc_cpu; + +void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, + uintptr_t retaddr); #endif =20 void sparc_cpu_do_interrupt(CPUState *cpu); @@ -575,10 +580,6 @@ void sparc_cpu_dump_state(CPUState *cpu, FILE *f, int = flags); hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, - uintptr_t retaddr); void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN; =20 #ifndef NO_CPU_IO_DEFS diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index cbe9e5ff230..d08e60c673e 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -575,9 +575,6 @@ void xtensa_count_regs(const XtensaConfig *config, unsigned *n_regs, unsigned *n_core_regs); int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); =20 #define cpu_signal_handler cpu_xtensa_signal_handler #define cpu_list xtensa_cpu_list @@ -671,6 +668,9 @@ static inline int xtensa_get_cring(const CPUXtensaState= *env) } =20 #ifndef CONFIG_USER_ONLY +void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr= addr, unsigned size, MMUAccessType access_= type, int mmu_idx, MemTxAttrs attrs, diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 3107f9823ef..9cd3cbeed51 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -108,6 +108,8 @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cpu= , vaddr addr, raise_exception(env, exc, syn, target_el); } =20 +#if !defined(CONFIG_USER_ONLY) + /* Raise a data fault alignment exception for the specified virtual addres= s */ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, @@ -123,8 +125,6 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr va= ddr, arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); } =20 -#if !defined(CONFIG_USER_ONLY) - /* * arm_cpu_do_transaction_failed: handle a memory system error response * (eg "no device/memory present at address") by raising an external abort diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index 20dbd673136..ae9c8e87a5a 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -271,23 +271,6 @@ hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, = vaddr addr, =20 return paddr; } -#endif - -bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); - CPUMBState *env =3D &cpu->env; - - if ((interrupt_request & CPU_INTERRUPT_HARD) - && (env->msr & MSR_IE) - && !(env->msr & (MSR_EIP | MSR_BIP)) - && !(env->iflags & (D_FLAG | IMM_FLAG))) { - cs->exception_index =3D EXCP_IRQ; - mb_cpu_do_interrupt(cs); - return true; - } - return false; -} =20 void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, @@ -316,3 +299,21 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr ad= dr, cs->exception_index =3D EXCP_HW_EXCP; cpu_loop_exit(cs); } + +#endif + +bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); + CPUMBState *env =3D &cpu->env; + + if ((interrupt_request & CPU_INTERRUPT_HARD) + && (env->msr & MSR_IE) + && !(env->msr & (MSR_EIP | MSR_BIP)) + && !(env->iflags & (D_FLAG | IMM_FLAG))) { + cs->exception_index =3D EXCP_IRQ; + mb_cpu_do_interrupt(cs); + return true; + } + return false; +} diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index f4f15279ebe..013728e0721 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1523,7 +1523,6 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_u= long rb) book3s_msgsnd_common(pir, PPC_INTERRUPT_DOORBELL); } #endif -#endif =20 void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, @@ -1540,3 +1539,5 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr = vaddr, env->error_code =3D insn & 0x03FF0000; cpu_loop_exit(cs); } + +#endif /* !CONFIG_USER_ONLY */ diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 22327d7d725..5097c535797 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1957,9 +1957,7 @@ void sparc_cpu_do_transaction_failed(CPUState *cs, hw= addr physaddr, sparc_raise_mmu_fault(cs, physaddr, is_write, is_exec, is_asi, size, retaddr); } -#endif =20 -#if !defined(CONFIG_USER_ONLY) void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, @@ -1974,4 +1972,5 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUS= tate *cs, vaddr addr, #endif cpu_raise_exception_ra(env, TT_UNALIGNED, retaddr); } -#endif + +#endif /* !CONFIG_USER_ONLY */ --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; 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[83.51.215.31]) by smtp.gmail.com with ESMTPSA id q12sm17140168wrx.17.2021.05.17.03.52.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:52:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LYuLraEC+Lf0AE7X9E3rg+Tkdhm34seQsrx2hTp2lLg=; b=abvQwnd6/GTVfLWXd7yFPB0AsNvvX/bLI/kGd6bPv0P1pROZY9z8A/Ug/GMI4fzO9H DJ7vacfTrWjQ76CrTBZPJxyxEVycIQQKhszMXrItnvA7W0NO287Y292j+o8gjIkzYvLN KUJnz51s0xSM22hP8OFCxTXX0JzndU9/JpODtYwvSixHNAXVOtFQBvBmPZMkBszAlp/Z P01ZhIBUbXAAgV+/w/uX1fa6Q6y/M+YdWCjGTJU3BX0jTGMq49f9T5bLKdsrJE+C2YgB QxlRArNZpfpV9dZTkVRFK4slM4bi5nOnXn4TrwZOzvaXJGoMuPh2KQhWuHK0MkiAACQO SGMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=LYuLraEC+Lf0AE7X9E3rg+Tkdhm34seQsrx2hTp2lLg=; b=V3YViSglYI7EkiI2Kf+TI1EmuOABB07MYU2rs5Ve83rjkwKyYA7ZxUkZ+k32Li/fDb sBYfZxMEsXE6b8GgwVj7ssZEFnwXdMzLjbppjtufoyoMgnhk4TCjDvLpf3dPqyV7nJE5 k+aHizXxrwM2vMrTOuKd+rOw1Abf3/86CS35CGVFeo17kxPoIfh3BdVJSomj0MMC2kUB MrCxGwuJX014vQmKYKJrBwOWYJ7NI1HOHQYGpeav1cD5yUju98AOs7TD6JNlogJlUGiu iNqacyzQ6zCZ22jo+fgvTyDmoW5kDy8SDE8c7oaZL5529kizNTbpey2nteAdCC8IXgiL UDmA== X-Gm-Message-State: AOAM532yXJdGPdJZ8otanrP5tKYkJvT2vaHxuiW68LM11MMyCuThnZwO ih8shqIOG7TAnFFtmjK6Mu0= X-Google-Smtp-Source: ABdhPJyvq4/NVQXgHcT6ZKk04BBuHd5GFvA4zQYxMlrCO4h9Q3VIxtGwTIKghiVya9UkC6ErFPdVKg== X-Received: by 2002:adf:8b4a:: with SMTP id v10mr14829620wra.274.1621248722001; Mon, 17 May 2021 03:52:02 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 04/23] cpu: Remove duplicated 'sysemu/hw_accel.h' header Date: Mon, 17 May 2021 12:51:21 +0200 Message-Id: <20210517105140.1062037-5-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/core/cpu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/core/cpu.c b/hw/core/cpu.c index 00330ba07de..919dc3435a3 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu.c @@ -34,7 +34,6 @@ #include "hw/qdev-properties.h" #include "trace/trace-root.h" #include "qemu/plugin.h" -#include "sysemu/hw_accel.h" =20 CPUState *cpu_by_arch_id(int64_t id) { --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) client-ip=209.85.128.48; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f48.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1621248728; cv=none; d=zohomail.com; s=zohoarc; b=QhR5HDovVoSonimNrf4pJnqJT4tCdB4+x5ju2xuGBOXvq76FnawSC9CerU1RqCrzOHvqGGZilH3BgAY7CxGFVrydD1yQvUv+zxbT3cLcgW23GeAs+tQe4X49hpVaa2+TyBcBcW7KzpLaqzI6VnGd+qM1G7qJIQHjsfbnHXkeMKk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621248728; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QHwci2qixAR5d1Isgklmt+j6/VrQrgpHFVrFxfi8kA4=; b=D9s00guzkNorNQKSnbfapjeGsy/Fqkx3j29cvGEtT1DYmAKbmft30f4EytOOv+dUycItLMb7z6xHr+SJm0bjGPNEMDy1/iQOMDH7NjFq6ta+Iu7XVZHY0oy3/VB0wtoiSE8CTq/dDLP7EP5BQfkIjGVOVCC+MXS8IfgU/LcotUY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) by mx.zohomail.com with SMTPS id 1621248728341465.37422655458556; Mon, 17 May 2021 03:52:08 -0700 (PDT) Received: by mail-wm1-f48.google.com with SMTP id f75-20020a1c1f4e0000b0290171001e7329so3316797wmf.1 for ; Mon, 17 May 2021 03:52:07 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (31.red-83-51-215.dynamicip.rima-tde.net. [83.51.215.31]) by smtp.gmail.com with ESMTPSA id r11sm10990297wrp.46.2021.05.17.03.52.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:52:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QHwci2qixAR5d1Isgklmt+j6/VrQrgpHFVrFxfi8kA4=; b=hIjZiZywwjEOcyj3lWCEIVxY2rgQexMxS5BUVk0N/okR18/OkYkOV+OzpxtT4UL1/D sKt/sCKaBcz0A/VTzwVVXEkLweJUbuzTNHAqRoSdzkZ9rArDRn7TDnvwU2BmCB7uhHWA +7YxE09SyPop1dSoLWvjKvXpNOYhxWfHsD+uFqbe2PfmzEz/MEcl/cakjDoD9Rqz1gh1 NI1Ljx1+skuBFZJcvBRZFb4ynOaobAXiQrRsmOC2qmpJ2TsD2ji5Xp49qW3W13HTSEIy 1Kz88IE+bzDgEVSYsJJwm90C0E6tBsPaIiPWc/S3yU3ubITIsy0ApFBCyNbxIrGU2lJn lDYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=QHwci2qixAR5d1Isgklmt+j6/VrQrgpHFVrFxfi8kA4=; b=Mcd6Jbn+OyPHSaDUqRJjmrYZLQUtmSN2SKNhRI5q1aA9VQrCzaTG2esTI+ipS2yyK0 PeQ4bwgBI3bFCJah9gLyC0WlNq2rP81tSwtXvRDyCkvItb6k52PGfeFtGXmKT5GPvYrF zHiMdlQVIGsnH6UaA91kn5w6RORtvcYKmDhyp+IqaAx7n21xxH+8WYB/OfGdA/xMDRho yyhlqKZ63M6O8UAv4mPz8zlX3LRv3ymu3KpHdVqzO2Ub4ZQY6boUgaeTBYddlptF9f8F AhlrsCW9YPclS7gj9r5+R4zdUJY+wJA6LzCkQipQhnMXpCiJmH3LAf8undwQcfFi+p1K zHrg== X-Gm-Message-State: AOAM532RNi0x5UTKgJH2EQyTteiFb7+5unbP3vJSEmqOdAZZ+iSq1qi4 lFfPMieXtsoRd+KIf3m91so= X-Google-Smtp-Source: ABdhPJzRoEu3JEhowL2N3n+rfMlRNV1PdYfrNH7GONxkoN3BUs+C4cakf4LjaYQUnaQIVHxL3I8iaQ== X-Received: by 2002:a7b:c182:: with SMTP id y2mr9174015wmi.125.1621248726537; Mon, 17 May 2021 03:52:06 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 05/23] cpu: Split as cpu-common / cpu-sysemu Date: Mon, 17 May 2021 12:51:22 +0200 Message-Id: <20210517105140.1062037-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The current cpu.c contains sysemu-specific methods. To avoid building them in user-mode builds, split the current cpu.c as cpu-common.c / cpu-sysemu.c. Start by moving cpu_get_crash_info(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- hw/core/{cpu.c =3D> cpu-common.c} | 17 ----------------- hw/core/cpu-sysemu.c | 34 +++++++++++++++++++++++++++++++++ hw/core/meson.build | 3 ++- 3 files changed, 36 insertions(+), 18 deletions(-) rename hw/core/{cpu.c =3D> cpu-common.c} (96%) create mode 100644 hw/core/cpu-sysemu.c diff --git a/hw/core/cpu.c b/hw/core/cpu-common.c similarity index 96% rename from hw/core/cpu.c rename to hw/core/cpu-common.c index 919dc3435a3..ddddf4b10eb 100644 --- a/hw/core/cpu.c +++ b/hw/core/cpu-common.c @@ -190,23 +190,6 @@ static bool cpu_common_virtio_is_big_endian(CPUState *= cpu) return target_words_bigendian(); } =20 -/* - * XXX the following #if is always true because this is a common_ss - * module, so target CONFIG_* is never defined. - */ -#if !defined(CONFIG_USER_ONLY) -GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - GuestPanicInformation *res =3D NULL; - - if (cc->get_crash_info) { - res =3D cc->get_crash_info(cpu); - } - return res; -} -#endif - void cpu_dump_state(CPUState *cpu, FILE *f, int flags) { CPUClass *cc =3D CPU_GET_CLASS(cpu); diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c new file mode 100644 index 00000000000..f517ef5d460 --- /dev/null +++ b/hw/core/cpu-sysemu.c @@ -0,0 +1,34 @@ +/* + * QEMU CPU model (system emulation specific) + * + * Copyright (c) 2012-2014 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/core/cpu.h" + +GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + GuestPanicInformation *res =3D NULL; + + if (cc->get_crash_info) { + res =3D cc->get_crash_info(cpu); + } + return res; +} diff --git a/hw/core/meson.build b/hw/core/meson.build index 59f1605bb07..18f44fb7c24 100644 --- a/hw/core/meson.build +++ b/hw/core/meson.build @@ -13,7 +13,7 @@ 'qdev-clock.c', ) =20 -common_ss.add(files('cpu.c')) +common_ss.add(files('cpu-common.c')) common_ss.add(when: 'CONFIG_FITLOADER', if_true: files('loader-fit.c')) common_ss.add(when: 'CONFIG_GENERIC_LOADER', if_true: files('generic-loade= r.c')) common_ss.add(when: ['CONFIG_GUEST_LOADER', fdt], if_true: files('guest-lo= ader.c')) @@ -25,6 +25,7 @@ common_ss.add(when: 'CONFIG_XILINX_AXI', if_true: files('stream.c')) =20 softmmu_ss.add(files( + 'cpu-sysemu.c', 'fw-path-provider.c', 'loader.c', 'machine-hmp-cmds.c', --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) client-ip=209.85.221.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1621248733; cv=none; d=zohomail.com; s=zohoarc; b=PFFpCEnOnmSy7XJay/Bz9QXAdFGBs/feHQ7byvW5A3zg7iU1HkTngWwq7PmZ8KrqIu8YNbAKvRZOVFa0z6NzW/t+Tzg6LYFO1sXNpPsyfU2pKjw5o9bdbE3h8Pc34tfLR5PkPMG8uo+DdZ4B2HFAfV/kU+nvZ9oSYtxvENuAG/A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621248733; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GlSXe+rLjO5Sm+DFhb+DRpEt2vwp+8OnODDN1P00uBk=; b=IchY8n/lDUZEUVlW9iWP1G/5dMXdYJzWj345fT8egU/OwnGUUGETFPPq1mYS9jeFkxNBvPgcLf3ScXVB8Q4b+qjKePQoHkUACg6lX9eouwQREzR1w4HL1zEa22CcHhoiqorUMZy8t30y2gx47fw5dvbH+EMPaqUetk72tDIh6J8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) by mx.zohomail.com with SMTPS id 1621248733096167.5456626476797; Mon, 17 May 2021 03:52:13 -0700 (PDT) Received: by mail-wr1-f43.google.com with SMTP id y14so3785485wrm.13 for ; Mon, 17 May 2021 03:52:12 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (31.red-83-51-215.dynamicip.rima-tde.net. [83.51.215.31]) by smtp.gmail.com with ESMTPSA id j14sm16735759wmj.19.2021.05.17.03.52.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:52:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GlSXe+rLjO5Sm+DFhb+DRpEt2vwp+8OnODDN1P00uBk=; b=W8v5ewV3Bdno7Txtdy4oFcQuokxSg6tEF86HSbkhdjYzIAl+L4ppgjqT6HW4GaveBo LtLgJHswCMjWD9Twdavox3X2krKFuH89MMyrP7Si4Tr84fr0QrLBBDqhy4TYOqsz7Eq/ toyB41+6p2ON3BG3X9c4HUwowH7PDQwUHzQqj7i/AH2qMyMyXrtZNYfBdpxvxlfDj3D2 bwyBeSJjEDQmdYI/69EV999JA2+Y/ynDsoU+7OuYUUn5o8nD6mcy97ZE/3HVn/FOG1Sh EE1bHaJlAZRXKrDEMSn25yLOs8tqDKdzmiSum80bZj4ONrhN9b70A/CAvN6V0Y+bhjML NHPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=GlSXe+rLjO5Sm+DFhb+DRpEt2vwp+8OnODDN1P00uBk=; b=nW9GJrfls+c5WMDFhrLwX1ylI3C74iJembIsi047IKVGVfQMhNgpFvIDU3T9qLF+dL jWLaxE6IraJ1F+938xOzm0vPrO4zkf76w3G3D/zs/r4tJ75MPoxAoZ0Sw4wcpKh6wM/s TxjaMsYgR53dmGhu3Bf4z13uYKZ9tFRsuRvZpaKtnIcoKnyHDhm0WDNoSe6DeVFMy0sA CefwvYq8BtGyTDMdysx8S0kd6j5dejZ9SvlQIIz56BwvR5tEEz9mfLnSofOuGBqREykN 9eyC9P2C6cEHvjn2Pxje/WsC/SZp7kinT9XsMazZr1G4VMd3vs3f9Et+2DW3QZgsLmiR 0X9A== X-Gm-Message-State: AOAM533mv/k5qvdx1K2MDb/hTeGFFv8ddiUknxdE/rV7OYNuL5C5+sfe T2EBAoYiHu6jChgr2SkuIkYrEDX2pqOM4A== X-Google-Smtp-Source: ABdhPJw1sNKQoNDS2hyfIPpw5MArCNHnqmjL26abifhPojGm7NExft4qIayqq4ekMm4w0AunGOr/5A== X-Received: by 2002:a5d:4e91:: with SMTP id e17mr11136051wru.396.1621248731341; Mon, 17 May 2021 03:52:11 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 06/23] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs Date: Mon, 17 May 2021 12:51:23 +0200 Message-Id: <20210517105140.1062037-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) To be able to later extract the cpu_get_phys_page_debug() and cpu_asidx_from_attrs() handlers from CPUClass, un-inline them from "hw/core/cpu.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 33 ++++----------------------------- hw/core/cpu-sysemu.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 29 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index d45f78290e0..df495287850 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -586,18 +586,8 @@ void cpu_dump_statistics(CPUState *cpu, int flags); * * Returns: Corresponding physical page address or -1 if no page found. */ -static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr ad= dr, - MemTxAttrs *attrs) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - if (cc->get_phys_page_attrs_debug) { - return cc->get_phys_page_attrs_debug(cpu, addr, attrs); - } - /* Fallback for CPUs which don't implement the _attrs_ hook */ - *attrs =3D MEMTXATTRS_UNSPECIFIED; - return cc->get_phys_page_debug(cpu, addr); -} +hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); =20 /** * cpu_get_phys_page_debug: @@ -609,12 +599,7 @@ static inline hwaddr cpu_get_phys_page_attrs_debug(CPU= State *cpu, vaddr addr, * * Returns: Corresponding physical page address or -1 if no page found. */ -static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) -{ - MemTxAttrs attrs =3D {}; - - return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); -} +hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); =20 /** cpu_asidx_from_attrs: * @cpu: CPU @@ -623,17 +608,7 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState = *cpu, vaddr addr) * Returns the address space index specifying the CPU AddressSpace * to use for a memory access with the given transaction attributes. */ -static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - int ret =3D 0; - - if (cc->asidx_from_attrs) { - ret =3D cc->asidx_from_attrs(cpu, attrs); - assert(ret < cpu->num_ases && ret >=3D 0); - } - return ret; -} +int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); =20 #endif /* CONFIG_USER_ONLY */ =20 diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index f517ef5d460..fe90dde8681 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -22,6 +22,38 @@ #include "qapi/error.h" #include "hw/core/cpu.h" =20 +hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->get_phys_page_attrs_debug) { + return cc->get_phys_page_attrs_debug(cpu, addr, attrs); + } + /* Fallback for CPUs which don't implement the _attrs_ hook */ + *attrs =3D MEMTXATTRS_UNSPECIFIED; + return cc->get_phys_page_debug(cpu, addr); +} + +hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) +{ + MemTxAttrs attrs =3D {}; + + return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); +} + +int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + int ret =3D 0; + + if (cc->asidx_from_attrs) { + ret =3D cc->asidx_from_attrs(cpu, attrs); + assert(ret < cpu->num_ases && ret >=3D 0); + } + return ret; +} + GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1621248737; cv=none; d=zohomail.com; s=zohoarc; b=WMoDRH1EPvHfSQkRu/B19Temfa+hwcaYPoB/nHqOEpq0SczjLVzSF66o2dIhy0S7DShA+966dOIYrtsqdJOHQlIJ9jL9Wxu2+aCGALlFr7s7X1noofSztYPSxCLax5oOv7P0gyuVXu87jL02TqiJdWg/N4CjhLIrSgpA+/ps6hg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621248737; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; 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[83.51.215.31]) by smtp.gmail.com with ESMTPSA id r11sm10990805wrp.46.2021.05.17.03.52.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:52:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l59dJwJTD3X/0a1ZARal5paaLkpJSadoVLKuikWa47k=; b=BmVPx1KPaifiuvOXGa4COEASn+9rXlOdAopBowSdJtwknRgiQcWsRx6iGLN9mYPPQT uHS7d7vc9mruNJLK5ObIkZXcvrZXhueYfOSAe4f4BiiQtsCBMXGpsK015mPzxhcGyTsB mEUr9BgajFYNSrUkSX0MfZYl1lwq/EMBZ1Ahp8J4Cgo+U4lLJ32s4doQPK0NEBOMk6zo wujAu1VdHqoYqnCNkbvLKLolfr1A74LBq7rrn2xQFq9yKFC64ioKlVwB95qMEPnFMzTO m4O9Io5oYp1MpkdVLZFfuMy5GlyxNilF2d6uWcJHRuDoOjpCoOWqMBYggSz4R02rOoAY UcqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=l59dJwJTD3X/0a1ZARal5paaLkpJSadoVLKuikWa47k=; b=lEPEPctY0IWgGLLcIa7O1Ia+5DL1fkoH6v2vq/cDOs1U8QwS+zWhk3904jFp2x4PdI xY9ja19xyI+hiyEkrHhlxiEcuhf8gjBNfqdCt4xVg6luQ+ZRB5LbhgJoI36HimnjpphB 9lKEnVgY/KjKdQH6wDNfSJVbwL55GcT4ttdz2XcleF2oO24Hmf2/7smh1DaG9SzkTJs0 tOTuFhefcSzX7U5bAC397QBFEW4WQc2R7PmG6SjzxP13HDqD8CGGnT62+w1Gxn+6gQTK oH/ncYNFsZp83C1eVsMHGvCihsD/0BmKVETuQ4Gv1SRYVliRCryj+P4BagUAJZMFQi8N Fu7Q== X-Gm-Message-State: AOAM533k5kYngtBvfj2UWDXdVAJ00C3/LxhIUwYqY6hiWGp68yag9F9Y TFDi06tJgTz6S/b+GV8liFQ= X-Google-Smtp-Source: ABdhPJxARe1TggM0cO94HPndcxDkxQrW2nLYeEPPxM1+Jit3Tveb4lDVmNgSWlGwaVS9wOSzAhOy2g== X-Received: by 2002:adf:e944:: with SMTP id m4mr31326484wrn.10.1621248736089; Mon, 17 May 2021 03:52:16 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 07/23] cpu: Introduce cpu_virtio_is_big_endian() Date: Mon, 17 May 2021 12:51:24 +0200 Message-Id: <20210517105140.1062037-8-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce the cpu_virtio_is_big_endian() generic helper to avoid calling CPUClass internal virtio_is_big_endian() one. Similarly to commit bf7663c4bd8 ("cpu: introduce CPUClass::virtio_is_big_endian()"), we keep 'virtio' in the method name to hint this handler shouldn't be called anywhere but from the virtio code. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 9 +++++++++ hw/core/cpu-common.c | 6 ------ hw/core/cpu-sysemu.c | 10 ++++++++++ hw/virtio/virtio.c | 4 +--- 4 files changed, 20 insertions(+), 9 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index df495287850..d96ff4dace0 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -610,6 +610,15 @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr ad= dr); */ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); =20 +/** + * cpu_virtio_is_big_endian: + * @cpu: CPU + + * Returns %true if a CPU which supports runtime configurable endianness + * is currently big-endian. + */ +bool cpu_virtio_is_big_endian(CPUState *cpu); + #endif /* CONFIG_USER_ONLY */ =20 /** diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index ddddf4b10eb..9d73c9a28ca 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -185,11 +185,6 @@ static int cpu_common_gdb_write_register(CPUState *cpu= , uint8_t *buf, int reg) return 0; } =20 -static bool cpu_common_virtio_is_big_endian(CPUState *cpu) -{ - return target_words_bigendian(); -} - void cpu_dump_state(CPUState *cpu, FILE *f, int flags) { CPUClass *cc =3D CPU_GET_CLASS(cpu); @@ -388,7 +383,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->write_elf64_note =3D cpu_common_write_elf64_note; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; - k->virtio_is_big_endian =3D cpu_common_virtio_is_big_endian; set_bit(DEVICE_CATEGORY_CPU, dc->categories); dc->realize =3D cpu_common_realizefn; dc->unrealize =3D cpu_common_unrealizefn; diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index fe90dde8681..078e1a84a58 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -54,6 +54,16 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) return ret; } =20 +bool cpu_virtio_is_big_endian(CPUState *cpu) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->virtio_is_big_endian) { + return cc->virtio_is_big_endian(cpu); + } + return target_words_bigendian(); +} + GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index e02544b2df7..ab516ac6144 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -1972,9 +1972,7 @@ static enum virtio_device_endian virtio_default_endia= n(void) =20 static enum virtio_device_endian virtio_current_cpu_endian(void) { - CPUClass *cc =3D CPU_GET_CLASS(current_cpu); - - if (cc->virtio_is_big_endian(current_cpu)) { + if (cpu_virtio_is_big_endian(current_cpu)) { return VIRTIO_DEVICE_ENDIAN_BIG; } else { return VIRTIO_DEVICE_ENDIAN_LITTLE; --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) client-ip=209.85.221.47; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f47.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1621248743; cv=none; d=zohomail.com; s=zohoarc; b=dpEbrwE6QAUDoFLcEprSoKDOrvRbmIgws7DFiDE5aQnYUPmzmJ3Fd/vFlKStl0ZvkjJzSOikGTEYXyDBRVqnajbgPfVD7UoBt/zdbwMBhD3O3TTQV5opqpNgYc93WEyPxqn3GJATyled1n4G3jx0S8t9OVocm2gf/xoMYiSqIGU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621248743; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jVPo/7wf7/2upfXpPnfl/YhREfWQHr+znlMSFXjo7H8=; b=nqdg10dOXQ3li5YPG0Edq8xn9gBGgUyzZ/R34nREW36/PmZYeCkpE+4qQFL7jdtpoDwKk6Uyvnj0LGb0Sy7997EPgBMSkgb3y9FUlNvhYPUccz7aUZ5Hkg2m50icrmn1j4wZ1qfCahoL932beSCCzc/ZRJXGA9X/q+yfMltLIjs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) by mx.zohomail.com with SMTPS id 1621248743291604.4200874656384; Mon, 17 May 2021 03:52:23 -0700 (PDT) Received: by mail-wr1-f47.google.com with SMTP id j14so4141106wrq.5 for ; Mon, 17 May 2021 03:52:22 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (31.red-83-51-215.dynamicip.rima-tde.net. [83.51.215.31]) by smtp.gmail.com with ESMTPSA id t17sm9915320wrp.89.2021.05.17.03.52.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:52:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jVPo/7wf7/2upfXpPnfl/YhREfWQHr+znlMSFXjo7H8=; b=ZXTAgZZDKYpbtRhiI+SV5EmMZJIobSIdnY7T9MyuO6DHeGB0w4oeWqveDrWJtK18/f sNMx+IR9GCXtwKMSCof1vx9Mg+q3fwgplcNAKPN3gVcWZjrM79q+T1wEV0Gfp05LAlUG AF5z5b7zngh1TfDmXCmRiH1wLLvIhAGlTUcpDQK24YOD2EAwo6oxYxzXC3dYdVqeVVuN 7r8E0Y1G6RIWIabLmkMZaWTYa4TtCldxOgRVDkHWPVN+rdU7hCxtoHiAZfTU9fz6kMKp OpOqxzsQJQxWrKuoIVVthEwLeLrcUasvkB6fvreKAWw8r9YhHXRnC9OcthoJwGiQxFgb PXrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=jVPo/7wf7/2upfXpPnfl/YhREfWQHr+znlMSFXjo7H8=; b=cQJWztukijAGsgNraQO3xNpN3+KfKJPyPbs5EYzU9P/6nz+AUrg8v9lyxrdpPO1pod ExH1SRWmCHyH7ys/GA2Q4ANHG14iWhnzQ+IpuHG2qv9XB+Ess6CL1sZtTBQ4jKQxz+y8 sfvExgsc270AbMuZ4CrBorUMwrHHidSHAGpj3I3X7OMPDeadesLu2ahFcHZmUigTW7Xo YTsby2Ogkg/+eQeYhDBYyJSrq3j0YHUTt8LZyenSSiMXKD41Y7hokbeQncMXEmc8jQuc 3cPW/eHA2H5J0PhJa2cK3dToL57DOtEzgRPPrnpWH72QzMGvC+wYiDxMsINIO5UPovzT 5DBQ== X-Gm-Message-State: AOAM530xEKCJEEYLNu2U9OxRuAg5GOI/VtRrJBH07VBtk5g1Wv+9txYU X4IcqpZ6vUlhL53TULAzQaQ= X-Google-Smtp-Source: ABdhPJxyXKwMak/9GBBedkKddkFPyp8nG47SyUhtPKruox03dhvwOGfC1JDWJHrG9a+y0nw75TB4WQ== X-Received: by 2002:a5d:4ec8:: with SMTP id s8mr4559165wrv.181.1621248741521; Mon, 17 May 2021 03:52:21 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 08/23] cpu: Directly use cpu_write_elf*() fallback handlers in place Date: Mon, 17 May 2021 12:51:25 +0200 Message-Id: <20210517105140.1062037-9-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No code directly accesses CPUClass::write_elf*() handlers out of hw/core/cpu.c (the rest are assignation in target/ code): $ git grep -F -- '->write_elf' hw/core/cpu.c:157: return (*cc->write_elf32_qemunote)(f, cpu, opaque); hw/core/cpu.c:171: return (*cc->write_elf32_note)(f, cpu, cpuid, opaqu= e); hw/core/cpu.c:186: return (*cc->write_elf64_qemunote)(f, cpu, opaque); hw/core/cpu.c:200: return (*cc->write_elf64_note)(f, cpu, cpuid, opaqu= e); hw/core/cpu.c:440: k->write_elf32_qemunote =3D cpu_common_write_elf32_= qemunote; hw/core/cpu.c:441: k->write_elf32_note =3D cpu_common_write_elf32_note; hw/core/cpu.c:442: k->write_elf64_qemunote =3D cpu_common_write_elf64_= qemunote; hw/core/cpu.c:443: k->write_elf64_note =3D cpu_common_write_elf64_note; target/arm/cpu.c:2304: cc->write_elf64_note =3D arm_cpu_write_elf64_no= te; target/arm/cpu.c:2305: cc->write_elf32_note =3D arm_cpu_write_elf32_no= te; target/i386/cpu.c:7425: cc->write_elf64_note =3D x86_cpu_write_elf64_n= ote; target/i386/cpu.c:7426: cc->write_elf64_qemunote =3D x86_cpu_write_elf= 64_qemunote; target/i386/cpu.c:7427: cc->write_elf32_note =3D x86_cpu_write_elf32_n= ote; target/i386/cpu.c:7428: cc->write_elf32_qemunote =3D x86_cpu_write_elf= 32_qemunote; target/ppc/translate_init.c.inc:10891: cc->write_elf64_note =3D ppc64_= cpu_write_elf64_note; target/ppc/translate_init.c.inc:10892: cc->write_elf32_note =3D ppc32_= cpu_write_elf32_note; target/s390x/cpu.c:522: cc->write_elf64_note =3D s390_cpu_write_elf64_= note; Check the handler presence in place and remove the common fallback code. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu-common.c | 63 -------------------------------------------- hw/core/cpu-sysemu.c | 44 +++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+), 63 deletions(-) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 9d73c9a28ca..5913ffe22be 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -116,65 +116,6 @@ void cpu_exit(CPUState *cpu) qatomic_set(&cpu->icount_decr_ptr->u16.high, -1); } =20 -int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - return (*cc->write_elf32_qemunote)(f, cpu, opaque); -} - -static int cpu_common_write_elf32_qemunote(WriteCoreDumpFunction f, - CPUState *cpu, void *opaque) -{ - return 0; -} - -int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - return (*cc->write_elf32_note)(f, cpu, cpuid, opaque); -} - -static int cpu_common_write_elf32_note(WriteCoreDumpFunction f, - CPUState *cpu, int cpuid, - void *opaque) -{ - return -1; -} - -int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - return (*cc->write_elf64_qemunote)(f, cpu, opaque); -} - -static int cpu_common_write_elf64_qemunote(WriteCoreDumpFunction f, - CPUState *cpu, void *opaque) -{ - return 0; -} - -int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - return (*cc->write_elf64_note)(f, cpu, cpuid, opaque); -} - -static int cpu_common_write_elf64_note(WriteCoreDumpFunction f, - CPUState *cpu, int cpuid, - void *opaque) -{ - return -1; -} - - static int cpu_common_gdb_read_register(CPUState *cpu, GByteArray *buf, in= t reg) { return 0; @@ -377,10 +318,6 @@ static void cpu_class_init(ObjectClass *klass, void *d= ata) k->has_work =3D cpu_common_has_work; k->get_paging_enabled =3D cpu_common_get_paging_enabled; k->get_memory_mapping =3D cpu_common_get_memory_mapping; - k->write_elf32_qemunote =3D cpu_common_write_elf32_qemunote; - k->write_elf32_note =3D cpu_common_write_elf32_note; - k->write_elf64_qemunote =3D cpu_common_write_elf64_qemunote; - k->write_elf64_note =3D cpu_common_write_elf64_note; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; set_bit(DEVICE_CATEGORY_CPU, dc->categories); diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index 078e1a84a58..7f3a3574943 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -54,6 +54,50 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) return ret; } =20 +int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (!cc->write_elf32_qemunote) { + return 0; + } + return (*cc->write_elf32_qemunote)(f, cpu, opaque); +} + +int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (!cc->write_elf32_note) { + return -1; + } + return (*cc->write_elf32_note)(f, cpu, cpuid, opaque); +} + +int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (!cc->write_elf64_qemunote) { + return 0; + } + return (*cc->write_elf64_qemunote)(f, cpu, opaque); +} + +int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (!cc->write_elf64_note) { + return -1; + } + return (*cc->write_elf64_note)(f, cpu, cpuid, opaque); +} + bool cpu_virtio_is_big_endian(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) client-ip=209.85.128.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f52.google.com; Authentication-Results: mx.zohomail.com; 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[83.51.215.31]) by smtp.gmail.com with ESMTPSA id c15sm17019645wrd.49.2021.05.17.03.52.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:52:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=numJYWQfN9cjP4y3FBe1McH7f7YrqdT6BscR7duwZVs=; b=PjPIsEmrl335FJg+p+NxwQla9zW8A5KcKXnlX0P1PCNzYPtTQOTNAltDsuUQ+UATZ6 GWNhnGQY3iCRH0E3fSh5VcxfGfdikuMZfyoovt7O2NODXr5ZzV2/UfQVLeEehANfLgGo yN5EceicQeG3ghsmcB/fwMLa/4zSmvFAsu4u64/mS3a0uzwAmCTtuxoCOU1egTRdv9aP QQAs4Jw7OkwmbxSL4UZV8zFgKaBD4J26div+p/ddz8P68LVFttmIHcl7LL6eVCH94KkN Y3sGMJB6NxxW6Lv75q6F/+5+W57Wt1fPGTBOMWFORxLgg/JZifflZHvZ6WlgxOu5A3/D qWLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=numJYWQfN9cjP4y3FBe1McH7f7YrqdT6BscR7duwZVs=; b=LuZVZ9l0MDSNk8Y+HG5KwaCLeIDjVAj/HpR465ZDUYK17Wr5FoaAGSj/I5+15doEtx UHQEYNl6TidEa4GOdUYyiKq//06Vz79DGxEp6J4OaOqMXsV/5GhY+cEIuhz0DahduXG+ UTDR1Jytvkm7l4qf8KjWOdSl/nuKV415WIfjESji62hbrgMUsKjCCjpDirLL1W3p4WU+ ENrRsXgX1sUjJbX48Xy225pOS0O1cyoSpQzbYe1DQC3RU/9RqVYVwMp/EgP1T7rCF6Ll fobGVt95N3QiTTF0XhWh2tn2vdB4ncU82KKe/xI1gLB+JXfGcNff8FHsrzOOFa7vZRkE I/rQ== X-Gm-Message-State: AOAM533xi6wRYGU8Rud08iDxvgejwQ8AdUACeef5FFFpHhBHi89oMqU5 jLGStFRNVXTXe+uUHky1Cls= X-Google-Smtp-Source: ABdhPJy3zXW8JzQyPPM0JT0plWT+oXbAu0+OlSmfl+DZ6r9raOTZPH9wTTipZrhs42HF9vg4dfzVDA== X-Received: by 2002:a1c:a7c2:: with SMTP id q185mr32839778wme.112.1621248746260; Mon, 17 May 2021 03:52:26 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 09/23] cpu: Directly use get_paging_enabled() fallback handlers in place Date: Mon, 17 May 2021 12:51:26 +0200 Message-Id: <20210517105140.1062037-10-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No code uses CPUClass::get_paging_enabled() outside of hw/core/cpu.c: $ git grep -F -- '->get_paging_enabled' hw/core/cpu.c:74: return cc->get_paging_enabled(cpu); hw/core/cpu.c:438: k->get_paging_enabled =3D cpu_common_get_paging_ena= bled; target/i386/cpu.c:7418: cc->get_paging_enabled =3D x86_cpu_get_paging_= enabled; Check the handler presence in place and remove the common fallback code. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu-common.c | 13 ------------- hw/core/cpu-sysemu.c | 11 +++++++++++ 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 5913ffe22be..2aa6b8cffca 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -66,18 +66,6 @@ CPUState *cpu_create(const char *typename) return cpu; } =20 -bool cpu_paging_enabled(const CPUState *cpu) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - return cc->get_paging_enabled(cpu); -} - -static bool cpu_common_get_paging_enabled(const CPUState *cpu) -{ - return false; -} - void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, Error **errp) { @@ -316,7 +304,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->parse_features =3D cpu_common_parse_features; k->get_arch_id =3D cpu_common_get_arch_id; k->has_work =3D cpu_common_has_work; - k->get_paging_enabled =3D cpu_common_get_paging_enabled; k->get_memory_mapping =3D cpu_common_get_memory_mapping; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index 7f3a3574943..931ba46354d 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -22,6 +22,17 @@ #include "qapi/error.h" #include "hw/core/cpu.h" =20 +bool cpu_paging_enabled(const CPUState *cpu) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->get_paging_enabled) { + return cc->get_paging_enabled(cpu); + } + + return false; +} + hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs) { --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.45 as permitted sender) client-ip=209.85.128.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1621248752; cv=none; d=zohomail.com; s=zohoarc; b=T92x+pEnQV03O6uZs11aAStdCGkwP6yTafwc5ZBIIwrxRdtLRbW7/lXTAb+SXkA65w4A7x+lUYMsxKR8+icOMsIZuhn8r5vC0cZWN0X4E1B2wKzgwSXNUTeEXX/n8Z6W2vkgr2+jTAviPCJHnfziLFMBBZStZlxBJPtAtn401bQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621248752; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XUBQ2jpiST+SjMtXV19Tr50fj7IFpfqAc4jPduflUQA=; b=IfD3mLp7FBeUdnHUPzg+P1CN7J+5Tg9C1x8mPNZao8yWuvd05g8j4o2Dy9LPneuwJFhCdg8wJAJSFG5iygDO4bpZP9v7Ek1vcjvLdpGLoN4HgT/kuoFD/d672MlkljUgc0szJFZsQZbWSLlftPnxpwRx94QylPCpxR9ZJgzC7Rs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) by mx.zohomail.com with SMTPS id 1621248752773552.2861194711008; Mon, 17 May 2021 03:52:32 -0700 (PDT) Received: by mail-wm1-f45.google.com with SMTP id z19-20020a7bc7d30000b029017521c1fb75so2713817wmk.0 for ; Mon, 17 May 2021 03:52:32 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (31.red-83-51-215.dynamicip.rima-tde.net. [83.51.215.31]) by smtp.gmail.com with ESMTPSA id s18sm6373966wra.80.2021.05.17.03.52.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:52:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XUBQ2jpiST+SjMtXV19Tr50fj7IFpfqAc4jPduflUQA=; b=nWQ7/CEDtfWl1LXldVPc9K5bALGvFIUBV6ph6/N8+ChrQW23KFZp5MpgMQLYwj5Tgz xisu6owmQlGD3f5LKGqNpPUpQCH0/UcmkyriF/I9yAMLgOKbhJxeGz5AXUzZn2c+YyTO uzJFIVk+EkNUdQB6T7YsRZjrs4VhABYwv89ZQlrocLX2R4IXRBUv0YwpXMgmNnYAHJ59 n5Oa4ACmY7PG9NPs+r34M3lPgUXekl14gSB2IyaeYkmw7Iq0gFYZW0ZKEHEPfO+liGjz BTpNraEeGM7OwJJn9OxNOncY9tQjHORKWtPn+8vKmcIviFICatTMUoMvoDB0/0Jr/hpD 8G2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=XUBQ2jpiST+SjMtXV19Tr50fj7IFpfqAc4jPduflUQA=; b=JCLmCmULpb5UyofQzaSkmksBupSpvNd6j15y3YS8EnG76q2bSBedPUuI2cqyU1/mBA 9D6T5yJ6TI5vKwaAiqx0gMIrnVq0aevpJXZcddjAI3yX6Zfnn+rQ6wSN4ifLxFuGdPQG txXXXikOHLFZ81Oqc7EiIocrzuKFshmnO7ugX08jKGAsUqnPFp2wue05jV/VHPd1A593 T2n5uhW4YCCaWFLyt+KLQZW7KNL7ntjzt3ECB8nGu4nonMc2QFl+58cHsMD/Izl6pVjS iz3tO55HaVW0RIKX948mC6jJYQLryRqJV9mZ2nB3mzfDyq2gr+5thU+bDvYJlp3WQnT3 /Fjg== X-Gm-Message-State: AOAM5311zc3ozAQIdeSTzZGQk1Pc708OAalzUC1mddX14XUlnaIs5I3W aycVdU9eOx5aHOQw2wKV0EM= X-Google-Smtp-Source: ABdhPJzIkw5diq4X5Z2elTFmNxSCJz+e8KNJZlWO7KlXhKmhaz5YLGhd1xq1Ffj6YkNca7lf/DxgQQ== X-Received: by 2002:a1c:4043:: with SMTP id n64mr19203312wma.9.1621248751005; Mon, 17 May 2021 03:52:31 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 10/23] cpu: Directly use get_memory_mapping() fallback handlers in place Date: Mon, 17 May 2021 12:51:27 +0200 Message-Id: <20210517105140.1062037-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) No code uses CPUClass::get_memory_mapping() outside of hw/core/cpu.c: $ git grep -F -- '->get_memory_mapping' hw/core/cpu.c:87: cc->get_memory_mapping(cpu, list, errp); hw/core/cpu.c:439: k->get_memory_mapping =3D cpu_common_get_memory_map= ping; target/i386/cpu.c:7422: cc->get_memory_mapping =3D x86_cpu_get_memory_= mapping; Check the handler presence in place and remove the common fallback code. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/cpu-common.c | 16 ---------------- hw/core/cpu-sysemu.c | 13 +++++++++++++ 2 files changed, 13 insertions(+), 16 deletions(-) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 2aa6b8cffca..9530e266ecb 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -66,21 +66,6 @@ CPUState *cpu_create(const char *typename) return cpu; } =20 -void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, - Error **errp) -{ - CPUClass *cc =3D CPU_GET_CLASS(cpu); - - cc->get_memory_mapping(cpu, list, errp); -} - -static void cpu_common_get_memory_mapping(CPUState *cpu, - MemoryMappingList *list, - Error **errp) -{ - error_setg(errp, "Obtaining memory mappings is unsupported on this CPU= ."); -} - /* Resetting the IRQ comes from across the code base so we take the * BQL here if we need to. cpu_interrupt assumes it is held.*/ void cpu_reset_interrupt(CPUState *cpu, int mask) @@ -304,7 +289,6 @@ static void cpu_class_init(ObjectClass *klass, void *da= ta) k->parse_features =3D cpu_common_parse_features; k->get_arch_id =3D cpu_common_get_arch_id; k->has_work =3D cpu_common_has_work; - k->get_memory_mapping =3D cpu_common_get_memory_mapping; k->gdb_read_register =3D cpu_common_gdb_read_register; k->gdb_write_register =3D cpu_common_gdb_write_register; set_bit(DEVICE_CATEGORY_CPU, dc->categories); diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index 931ba46354d..aa68ca281e8 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -33,6 +33,19 @@ bool cpu_paging_enabled(const CPUState *cpu) return false; } =20 +void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, + Error **errp) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->get_memory_mapping) { + cc->get_memory_mapping(cpu, list, errp); + return; + } + + error_setg(errp, "Obtaining memory mappings is unsupported on this CPU= ."); +} + hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs) { --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) client-ip=209.85.221.43; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f43.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1621248757; cv=none; d=zohomail.com; s=zohoarc; b=nmi8ZV/dtwCGIINSMsfj6MG7K62F5blq7px0d1fcCpA6gttea5Fj1evZ7AtEeeZ7868ejHHoVJ68AzoZBz+pSEJi8hxDpEwc5ZNpSKvE40KsP5xZOF3kg6LJn89mqM+Evz+rq9GH+MOAFc3820Tn2/9RGRt/MzPhunyTFbaKxG0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621248757; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=62bRjuN6Hv82DBcOqLhZSxPlLlMeXZkMX2kFXTADKa8=; b=DMaRNRBf/wL4+YtwU3FeWeKuY6mYC3Q3JdTe/x0LjY7CRvNBN5PU0s7Cqzbr5g02vWGQ9hj9pGeegcMHUZNch9zeKbz36DNzRCRnDVgEw0XVCk8nbfBn8TSagS79OteTkh/TKB2caWroP/TQ1Y83aDPN1WSaDUbmRjMEF0PZ4NI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) by mx.zohomail.com with SMTPS id 1621248757816886.8305770879027; Mon, 17 May 2021 03:52:37 -0700 (PDT) Received: by mail-wr1-f43.google.com with SMTP id x8so5864701wrq.9 for ; Mon, 17 May 2021 03:52:37 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (31.red-83-51-215.dynamicip.rima-tde.net. [83.51.215.31]) by smtp.gmail.com with ESMTPSA id n7sm16178413wri.14.2021.05.17.03.52.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:52:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=62bRjuN6Hv82DBcOqLhZSxPlLlMeXZkMX2kFXTADKa8=; b=WRR9/ZTGXumMwQZEBcx5Hs6N/5Olc0JagEXe+Tmnno2wD6IAr3o7LfKMfRoqj4pqSe yiYcxf6JAJYranESSCijaJ+stNpiHhYTIMTWKPa1DqEHM+0e9lzTPw0bUv/42NB8g2la DW7YEx32YzsytDjFXT0EyWGnXPz2+wQhlfKeujlrH0Ciqu03oo7d9eAhXaF8xKa4aCoT +kP6v92Sd4auYTQraXwNYBW3jwnIWsgfhxL3Vzz8T8mbu1XuER/Qxdrb626CH15f9DLk Edd73Er13ctIL3c7dY9ogD/Sk84sJn0mJMk1mx6jvbk4z5yS6UIDnrkx/RIcxU4+U53Y KZEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=62bRjuN6Hv82DBcOqLhZSxPlLlMeXZkMX2kFXTADKa8=; b=MPpp4L73MrTfa9dHSHe9vzt2qHsZBtcbyzLSAqZKqXvYm4a/VcgCSoTSeW0FkVb79c i6fXixFYSmoxFg/O2ZyuZssJ3CMbdXNd4wB0JPiAL4XFXjBbdJAcPrdfhpl7MAIFJnvC iZC7eTo+JVyFPiwgk1CPPA4P4qXVU7uigCavihGgN97Q3tGjAoOU5HPa+/Y5pani6ODx P3K8O3QUY6W2nR+vkOyuNLGzvf3yDt50S0/IuZmW/a7kQGwt8dXL4cYzajibsKpKBvBn 6fRYE/jUxBAAdvJmm65xXhYwcLUvUEoSTSntA5w6Oy7ANrMPIiyDSU7Z8WarcWObML+G ws6g== X-Gm-Message-State: AOAM530pHLRelR6rh8aslS0eHf0MHessdSpWkr4S6mk0uN46sBGSReis lZfHsLaTmLt1ER6RNwvkLOs= X-Google-Smtp-Source: ABdhPJxuGh9k7KDPLVkU7UAl8Q8bHZEURJ6FKu4cwawa4wjyB94cF4Ev29l3JvoZfhva4rx3vPJsrw== X-Received: by 2002:adf:f14d:: with SMTP id y13mr2556205wro.261.1621248755997; Mon, 17 May 2021 03:52:35 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 11/23] cpu: Assert DeviceClass::vmsd is NULL on user emulation Date: Mon, 17 May 2021 12:51:28 +0200 Message-Id: <20210517105140.1062037-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Migration is specific to system emulation. Restrict current DeviceClass::vmsd to sysemu using #ifdef'ry, and assert in cpu_exec_realizefn() that dc->vmsd not set under user emulation. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- v7: Check vmsd->unmigratable (David) --- cpu.c | 2 ++ target/sh4/cpu.c | 5 +++-- target/xtensa/cpu.c | 4 +++- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/cpu.c b/cpu.c index 34a0484bf41..6fe4af27975 100644 --- a/cpu.c +++ b/cpu.c @@ -141,6 +141,8 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) #endif /* CONFIG_TCG */ =20 #ifdef CONFIG_USER_ONLY + assert(qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL || + qdev_get_vmsd(DEVICE(cpu))->unmigratable); assert(cc->vmsd =3D=3D NULL); #else if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index ac65c88f1f8..35d4251aaf3 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -218,10 +218,12 @@ static void superh_cpu_initfn(Object *obj) env->movcal_backup_tail =3D &(env->movcal_backup); } =20 +#ifndef CONFIG_USER_ONLY static const VMStateDescription vmstate_sh_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, }; +#endif =20 #include "hw/core/tcg-cpu-ops.h" =20 @@ -257,12 +259,11 @@ static void superh_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_write_register =3D superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; + dc->vmsd =3D &vmstate_sh_cpu; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; =20 cc->gdb_num_core_regs =3D 59; - - dc->vmsd =3D &vmstate_sh_cpu; cc->tcg_ops =3D &superh_tcg_ops; } =20 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index e2b2c7a71c1..a66527e2d45 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -176,10 +176,12 @@ static void xtensa_cpu_initfn(Object *obj) #endif } =20 +#ifndef CONFIG_USER_ONLY static const VMStateDescription vmstate_xtensa_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, }; +#endif =20 #include "hw/core/tcg-cpu-ops.h" =20 @@ -216,9 +218,9 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_stop_before_watchpoint =3D true; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; + dc->vmsd =3D &vmstate_xtensa_cpu; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; - dc->vmsd =3D &vmstate_xtensa_cpu; cc->tcg_ops =3D &xtensa_tcg_ops; } =20 --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) client-ip=209.85.221.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1621248762; cv=none; d=zohomail.com; s=zohoarc; b=Kz67Zw940xGXQ1G7m9/u0/hHDSZgYxRe3uZpJ82fiENnGCdE+nbJduVKAA2/0gTgYi52jH762hLvxfGKufKhSjXR/fUmpgBeMgxH5I73bLNhRBELm+06RIVf+pc23znJcTT2B3XjIR9rK4xixWuabXEI7FYW7WBzwn/AVjK/w3M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621248762; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5+gvNlAktZ3R/5laA6wCqdudeSBg0Z7c6s+SBPqNIIY=; b=iEi1OK1N5ioRjqAXa3Fc9i1FTqDJz29Amb/Ze/vsYSElb36i3tCMz6srooAhOAt2hAE+7xcvpY4KErbs8RYydidU2ZDtCUrJUa4tsZGbg4ywvyp3GYVhp/wujMEDHjlyE/hIxEMart5kghydsdF/HOA2vyiMDfgzU97ALvflKZk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) by mx.zohomail.com with SMTPS id 162124876283254.44987292615576; Mon, 17 May 2021 03:52:42 -0700 (PDT) Received: by mail-wr1-f54.google.com with SMTP id a4so5904887wrr.2 for ; Mon, 17 May 2021 03:52:42 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (31.red-83-51-215.dynamicip.rima-tde.net. [83.51.215.31]) by smtp.gmail.com with ESMTPSA id m9sm9985812wrs.36.2021.05.17.03.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:52:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5+gvNlAktZ3R/5laA6wCqdudeSBg0Z7c6s+SBPqNIIY=; b=bR892HYfwwHBg/vgifAlkOOxTfAFp4pHdOKV5RWbZij8oCOytRLrmAfZ8TIGJxQCYw W8wslVt8DKGT1KMOLiAfEjXxX3Bfqc60m+81DvHK3H6km4IS1UtOeEQseAegw6+CkGgd OlKokQ3UZ41iDLLWmjZ/QE2HvaV1hWUxcuaVVwg4oCjG0hHsK9WcVIsilnxso7WAuoFG O68Ohzc4ncHmAIfUhn4DNMvxWYEDyRuo/VUSZfzmL7NiioA5BbsKBtMxoqEpw2hYHQVH WSxB87KaZolBEEx8uA4+CFZcNmv5qD2u7mUCYY0QAsNuyUxuOvT7XZkrSjE7Q76oYNa8 qblQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=5+gvNlAktZ3R/5laA6wCqdudeSBg0Z7c6s+SBPqNIIY=; b=lGZwJ8KSpzlNa5ij4Vj8T64bRdmTVN43R6ak0bnCnWtfXYqBClHanvfz+FnSChdsdN Gild3M5nk6a+fG6n5N+V7SBHo8yUtdk5pKHpByj/bm/i9e+33os2WuWJivmwA97RUJrR i/K0lXPlKO6LyX2aqop5rrBhV104RiFqncDbKihc8V7auzdN6QMmvs1X7LJo85dmxqhk h9hbLwJ+uzlvXUUKsIhIO5u2pIESLImtYbc5ZkYNocNOSrSFdZhuz1RZ0isNLPdp8DoE n0acFsA5wHd5G7wISAiQuLYDSbyt0c9li09m0NffMYTi5vsRd9fLR/VW0L01SLc6z33h EJLg== X-Gm-Message-State: AOAM530P2bpSJR/8/QAqzEL1ypG72WTH/kY9BbQh46aMrA8/8lejPPJR SrMPCNXIgobwBvdSeADJeGE= X-Google-Smtp-Source: ABdhPJwUVb/K957DjQSpTi+XYOVrdkz5o/cJDNZJgaxcUKqADJREYW2UlikacX40ZzT0QMMd7Pwo6A== X-Received: by 2002:a5d:5409:: with SMTP id g9mr3148894wrv.321.1621248760948; Mon, 17 May 2021 03:52:40 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH v7 12/23] cpu: Rename CPUClass vmsd -> legacy_vmsd Date: Mon, 17 May 2021 12:51:29 +0200 Message-Id: <20210517105140.1062037-13-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Quoting Peter Maydell [*]: There are two ways to handle migration for a CPU object: (1) like any other device, so it has a dc->vmsd that covers migration for the whole object. As usual for objects that are a subclass of a parent that has state, the first entry in the VMStateDescription field list is VMSTATE_CPU(), which migrates the cpu_common fields, followed by whatever the CPU's own migration fields are. (2) a backwards-compatible mechanism for CPUs that were originally migrated using manual "write fields to the migration stream structures". The on-the-wire migration format for those is based on the 'env' pointer (which isn't a QOM object), and the cpu_common part of the migration data is elsewhere. cpu_exec_realizefn() handles both possibilities: * for type 1, dc->vmsd is set and cc->vmsd is not, so cpu_exec_realizefn() does nothing, and the standard "register dc->vmsd for a device" code does everything needed * for type 2, dc->vmsd is NULL and so we register the vmstate_cpu_common directly to handle the cpu-common fields, and the cc->vmsd to handle the per-CPU stuff You can't change a CPU from one type to the other without breaking migration compatibility, which is why some guest architectures are stuck on the cc->vmsd form. New targets should use dc->vmsd. To avoid new targets to start using type (2), rename cc->vmsd as cc->legacy_vmsd. The correct field to implement is dc->vmsd (the DeviceClass one). See also commit b170fce3dd0 ("cpu: Register VMStateDescription through CPUState") for historic background. [*] https://www.mail-archive.com/qemu-devel@nongnu.org/msg800849.html Cc: Peter Maydell Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 5 +++-- cpu.c | 12 ++++++------ target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 10 files changed, 17 insertions(+), 16 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index d96ff4dace0..1dfb788415b 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -122,7 +122,8 @@ struct AccelCPUClass; * 32-bit VM coredump. * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF * note to a 32-bit VM coredump. - * @vmsd: State description for migration. + * @legacy_vmsd: Legacy state description for migration. + * Do not use in new targets, use #DeviceClass::vmsd instead. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to s= top @@ -177,7 +178,7 @@ struct CPUClass { int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, void *opaque); =20 - const VMStateDescription *vmsd; + const VMStateDescription *legacy_vmsd; const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); diff --git a/cpu.c b/cpu.c index 6fe4af27975..c57f4c302bc 100644 --- a/cpu.c +++ b/cpu.c @@ -143,13 +143,13 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) #ifdef CONFIG_USER_ONLY assert(qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL || qdev_get_vmsd(DEVICE(cpu))->unmigratable); - assert(cc->vmsd =3D=3D NULL); + assert(cc->legacy_vmsd =3D=3D NULL); #else if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); } - if (cc->vmsd !=3D NULL) { - vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); + if (cc->legacy_vmsd !=3D NULL) { + vmstate_register(NULL, cpu->cpu_index, cc->legacy_vmsd, cpu); } #endif /* CONFIG_USER_ONLY */ } @@ -159,10 +159,10 @@ void cpu_exec_unrealizefn(CPUState *cpu) CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 #ifdef CONFIG_USER_ONLY - assert(cc->vmsd =3D=3D NULL); + assert(cc->legacy_vmsd =3D=3D NULL); #else - if (cc->vmsd !=3D NULL) { - vmstate_unregister(NULL, cc->vmsd, cpu); + if (cc->legacy_vmsd !=3D NULL) { + vmstate_unregister(NULL, cc->legacy_vmsd, cpu); } if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_unregister(NULL, &vmstate_cpu_common, cpu); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4eb0d2f85c4..e9ad85dd706 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1981,7 +1981,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; - cc->vmsd =3D &vmstate_arm_cpu; + cc->legacy_vmsd =3D &vmstate_arm_cpu; cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 0f4596932ba..37a8ebcc86f 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -213,7 +213,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; - cc->vmsd =3D &vms_avr_cpu; + cc->legacy_vmsd =3D &vms_avr_cpu; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c496bfa1c23..5a1c8ead8ed 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6749,7 +6749,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; cc->write_elf32_note =3D x86_cpu_write_elf32_note; cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; - cc->vmsd =3D &vmstate_x86_cpu; + cc->legacy_vmsd =3D &vmstate_x86_cpu; #endif /* !CONFIG_USER_ONLY */ =20 cc->gdb_arch_name =3D x86_gdb_arch_name; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 1ad2fe4aa33..eba56ac8996 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -561,7 +561,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_mips_cpu; + cc->legacy_vmsd =3D &vmstate_mips_cpu; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; cc->gdb_num_core_regs =3D 73; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d459e8427e2..16510da2597 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -638,7 +638,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_riscv_cpu; + cc->legacy_vmsd =3D &vmstate_riscv_cpu; cc->write_elf64_note =3D riscv_cpu_write_elf64_note; cc->write_elf32_note =3D riscv_cpu_write_elf32_note; #endif diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 64455cf309a..7ce425f6111 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -516,7 +516,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_s390_cpu; + cc->legacy_vmsd =3D &vmstate_s390_cpu; cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; #endif diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index aece2c7dc83..ba497561bfa 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -889,7 +889,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; - cc->vmsd =3D &vmstate_sparc_cpu; + cc->legacy_vmsd =3D &vmstate_sparc_cpu; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; =20 diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 66e6a4a746f..f0f198e717f 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10279,7 +10279,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_write_register =3D ppc_cpu_gdb_write_register; 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[83.51.215.31]) by smtp.gmail.com with ESMTPSA id c14sm16873962wrt.77.2021.05.17.03.52.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:52:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=73qeszPShsMKmwQ6XsHjcTezehy+lvr/7Xa8ct6h49I=; b=KZdPVqTiITvdCNz5rGciJOBS/6F3QG7VJJfwgQItf76O4Kp4R0JPne0N/R+5FiLOsP o14Qz+IyZL40FAq0FLIoCjMmXMBuppqqG1Trct8uIJ7vusSKmuTKnuogCq20V+U9EIIZ 68s2gh56Hum75RkTg74qB2DaE7mhvMRv3xzrt1vAYX8xGZiMl5Cf1ieolSqXMl6mLTq4 oV3hvD+VZet7J277cUTnQ8Myj0OWbdc+7xzDorEyXjH1F12h9cscocFlYoa4bT5PEcJx EQPzIWqWa4fW2cRwvD1U/wKHmuXSs6oJvGKI7L5jzJ0ae0OXhB4u5Nb4WobZobYxWyky aTNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=73qeszPShsMKmwQ6XsHjcTezehy+lvr/7Xa8ct6h49I=; b=LrwQlHxIYzK9WGzG7FB8NyYXS1JbsfaBE2pMfjV/DYKoReD4eZ1fSqJuSIqOZRdNa5 8UI3oXVQaj90VXV6j+F6EHOn6zabD7MtfA62IDb1Qp22ZNAB9Qeg0YEpPnQ2w8S33uVU N0LrtRE2udy4Erb6OgMpbS+3hzowTnypuZ2LMgk4LkClNENDnYxhXokB/omdgdWgd3la Oj5Gg0e9oo0relVWjgj30FqkoofbGQAZGDaA2peyZB+v83vIHkQ9obOR6jgUcD/XGn7f eKud8UV9PcvAD5l8WocYjlZX4tyqkTgD0MoZrchLsdifmLcN5sKhabtivB4MEJi8D9Tb iCPQ== X-Gm-Message-State: AOAM532bvRTd7iHR5I5ag0BhfZXzMmL+pAhahmlvqQyWMPDBOZlYAXDL AnTUY2bzOqZyY8crAES8I2A= X-Google-Smtp-Source: ABdhPJx74qhFgmRDEijCQeQSdLdNbgNDud+KrdpZkAtqowjjW4GBXwrKfr/LUEYasa7AC8Q+p40MGw== X-Received: by 2002:a1c:a9ca:: with SMTP id s193mr33217198wme.132.1621248765787; Mon, 17 May 2021 03:52:45 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 13/23] cpu: Move AVR target vmsd field from CPUClass to DeviceClass Date: Mon, 17 May 2021 12:51:30 +0200 Message-Id: <20210517105140.1062037-14-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) See rationale in previous commit. Targets should use the vmsd field of DeviceClass, not CPUClass. As migration is not important on the AVR target, break the migration compatibility and set the DeviceClass vmsd field. To feel safer, increment the vmstate version. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- v7: Increment vmstate version (Richard) --- target/avr/cpu.c | 2 +- target/avr/machine.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 37a8ebcc86f..3353bcb9fc7 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -213,7 +213,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; - cc->legacy_vmsd =3D &vms_avr_cpu; + dc->vmsd =3D &vms_avr_cpu; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; diff --git a/target/avr/machine.c b/target/avr/machine.c index de264f57c33..16f7a3e031d 100644 --- a/target/avr/machine.c +++ b/target/avr/machine.c @@ -98,8 +98,8 @@ static const VMStateInfo vms_eind =3D { =20 const VMStateDescription vms_avr_cpu =3D { .name =3D "cpu", - .version_id =3D 0, - .minimum_version_id =3D 0, + .version_id =3D 1, + .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { VMSTATE_UINT32(env.pc_w, AVRCPU), VMSTATE_UINT32(env.sp, AVRCPU), --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f49.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1621248772; cv=none; d=zohomail.com; s=zohoarc; b=TYL6GGpiAAK3UDYo/GEIrIRpI49v0vM0fBvQg9CYvDlqs+Rst7fmmEXD45+/5MkeWU3FcTt+rnNSnoTI/JsVnbwq4W2xzUjs2LKRXrnn/FQguxtS8mWA2c+RrYAdlA4LzXnqIEHAQHXqIWgt3YLE7j5JV2Mnaot+OX+ZIVzXOJs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621248772; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hS+kp/ZLgiNhRKTh0kiH30GlqhW5SMy4RjCakAcczzY=; b=RZ8K2jdZtiAb9HYZkT96tLiF7GVpkomS2zxtQByA+5vJ/XSgR9jGJTpXQytvsCkykPp0BZ2MZExYp6C9RxYtr3dUh7shK+KPfLUP7YeKEuf/AWsuNbu3AEKRl1Sv/HMdD/b3zxr9RGNJwucu7wNPeQZXPNTm3ZycA1w54VjHjqk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) by mx.zohomail.com with SMTPS id 1621248772332839.2710014036073; Mon, 17 May 2021 03:52:52 -0700 (PDT) Received: by mail-wr1-f49.google.com with SMTP id j14so4142492wrq.5 for ; Mon, 17 May 2021 03:52:51 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (31.red-83-51-215.dynamicip.rima-tde.net. [83.51.215.31]) by smtp.gmail.com with ESMTPSA id c194sm18455523wme.46.2021.05.17.03.52.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:52:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hS+kp/ZLgiNhRKTh0kiH30GlqhW5SMy4RjCakAcczzY=; b=ZE+dNgyS5OT0YVdmpOKBLGJmDi4MZBhmlH96Dv8clsUGdyhj1OOcDEPKyBvBDSXmvD oPGRYtl6DPps6tiTCRwQyKsE0YMAmMGnozVJ6CtzucCDUBuIl3rF5U6sN6/l/ZM93OTq Bw+nzXacWL/gqljr3zCNr9JG4sA9DO4+L/69MDP0bxntQg9A1YtKezJ0KVjhTHNz65Il 8DQ/vxcT96AYOqOmvttWdiRt+vyBlYi77Fj4JUv1tpTkAcQINXYzQJEzK+3T8j6+c4Xc NBPXg0qMCaF8xW1lIgVFGT7X1d4XCNtGhj/ZvRioSuXL01TYh3LueQpWkzhyqeIdlTgX rpwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=hS+kp/ZLgiNhRKTh0kiH30GlqhW5SMy4RjCakAcczzY=; b=a64ru1FTGFCx2OnxOGFI9TiF6lEoXrCLQYux3HhourW8zm0djjCp51pRuq4jJu5sa5 YoB+Wvhq4jKbfr8AAPm1bhGD0zbcJv/cWpsBNmRObIvudW6YdlAB1dYIX+y2Ku+P3EKw 7CQO5DB2f7kWhKYhTd4C39qsSewBg1nHlaYI/NU2DEHdwjFcBsQE6O05NPNLP1AfDBbU By1FUZAQ3+KqeWJsR4ESL1h+AmMDT5gpvQAs7suBYXUq2SBt+m3HP3+K/yXNUv8LeDwt Wv9vsoGoAmH7fNIUO4uEgGGTqP4ULOvmoDYt6WMRSelqKLvt8pQLiL4uNPWQaFNsHDQV nk3w== X-Gm-Message-State: AOAM531Tq/ysvbDm3HsxfM3mxVZJ1iYtRc43mjqMnupPvKwokCmMnvdz An0wMXbLxvI3nMzgwjcPu5s= X-Google-Smtp-Source: ABdhPJyj2RP+uVb922paHwU9oi0XY5rELSgVz8zfAxgDusUshb6jckqWQM3X+Aza2+R76T+izWlUNw== X-Received: by 2002:a5d:64cf:: with SMTP id f15mr71573228wri.327.1621248770541; Mon, 17 May 2021 03:52:50 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 14/23] cpu: Introduce SysemuCPUOps structure Date: Mon, 17 May 2021 12:51:31 +0200 Message-Id: <20210517105140.1062037-15-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Introduce a structure to hold handler specific to sysemu. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 5 +++++ include/hw/core/sysemu-cpu-ops.h | 21 +++++++++++++++++++++ target/alpha/cpu.c | 6 ++++++ target/arm/cpu.c | 6 ++++++ target/avr/cpu.c | 4 ++++ target/cris/cpu.c | 6 ++++++ target/hppa/cpu.c | 6 ++++++ target/i386/cpu.c | 6 ++++++ target/m68k/cpu.c | 6 ++++++ target/microblaze/cpu.c | 6 ++++++ target/mips/cpu.c | 6 ++++++ target/nios2/cpu.c | 6 ++++++ target/openrisc/cpu.c | 6 ++++++ target/riscv/cpu.c | 6 ++++++ target/rx/cpu.c | 8 ++++++++ target/s390x/cpu.c | 6 ++++++ target/sh4/cpu.c | 4 ++++ target/sparc/cpu.c | 6 ++++++ target/tricore/cpu.c | 4 ++++ target/xtensa/cpu.c | 4 ++++ target/ppc/translate_init.c.inc | 6 ++++++ 21 files changed, 134 insertions(+) create mode 100644 include/hw/core/sysemu-cpu-ops.h diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 1dfb788415b..da55d310d4b 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -80,6 +80,8 @@ struct TCGCPUOps; /* see accel-cpu.h */ struct AccelCPUClass; =20 +#include "hw/core/sysemu-cpu-ops.h" + /** * CPUClass: * @class_by_name: Callback to map -cpu command line model name to an @@ -191,6 +193,9 @@ struct CPUClass { bool gdb_stop_before_watchpoint; struct AccelCPUClass *accel_cpu; =20 + /* when system emulation is not available, this pointer is NULL */ + const struct SysemuCPUOps *sysemu_ops; + /* when TCG is not available, this pointer is NULL */ struct TCGCPUOps *tcg_ops; =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h new file mode 100644 index 00000000000..e54a08ea25e --- /dev/null +++ b/include/hw/core/sysemu-cpu-ops.h @@ -0,0 +1,21 @@ +/* + * CPU operations specific to system emulation + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef SYSEMU_CPU_OPS_H +#define SYSEMU_CPU_OPS_H + +#include "hw/core/cpu.h" + +/* + * struct SysemuCPUOps: System operations specific to a CPU class + */ +typedef struct SysemuCPUOps { +} SysemuCPUOps; + +#endif /* SYSEMU_CPU_OPS_H */ diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index 27192b62e22..cd01d34d92f 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -206,6 +206,11 @@ static void alpha_cpu_initfn(Object *obj) #endif } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps alpha_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps alpha_tcg_ops =3D { @@ -238,6 +243,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_alpha_cpu; + cc->sysemu_ops =3D &alpha_sysemu_ops; #endif cc->disas_set_info =3D alpha_cpu_disas_set_info; =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e9ad85dd706..a9c9389859b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1942,6 +1942,11 @@ static gchar *arm_gdb_arch_name(CPUState *cs) return g_strdup("arm"); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps arm_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG static struct TCGCPUOps arm_tcg_ops =3D { .initialize =3D arm_translate_init, @@ -1985,6 +1990,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; + cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; cc->gdb_core_xml_file =3D "arm-core.xml"; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 3353bcb9fc7..5c8bb9b3fec 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -184,6 +184,9 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) qemu_fprintf(f, "\n"); } =20 +static const struct SysemuCPUOps avr_sysemu_ops =3D { +}; + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps avr_tcg_ops =3D { @@ -214,6 +217,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; dc->vmsd =3D &vms_avr_cpu; + cc->sysemu_ops =3D &avr_sysemu_ops; cc->disas_set_info =3D avr_cpu_disas_set_info; cc->gdb_read_register =3D avr_cpu_gdb_read_register; cc->gdb_write_register =3D avr_cpu_gdb_write_register; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index ed983380fca..394df655c9f 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -193,6 +193,11 @@ static void cris_cpu_initfn(Object *obj) #endif } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps cris_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps crisv10_tcg_ops =3D { @@ -294,6 +299,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_cris_cpu; + cc->sysemu_ops =3D &cris_sysemu_ops; #endif =20 cc->gdb_num_core_regs =3D 49; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index d8fad52d1fe..6605c42e509 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -131,6 +131,11 @@ static ObjectClass *hppa_cpu_class_by_name(const char = *cpu_model) return object_class_by_name(TYPE_HPPA_CPU); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps hppa_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps hppa_tcg_ops =3D { @@ -163,6 +168,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_hppa_cpu; + cc->sysemu_ops =3D &hppa_sysemu_ops; #endif cc->disas_set_info =3D hppa_cpu_disas_set_info; cc->gdb_num_core_regs =3D 128; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5a1c8ead8ed..35ef2eb1a41 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6714,6 +6714,11 @@ static Property x86_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps i386_sysemu_ops =3D { +}; +#endif + static void x86_cpu_common_class_init(ObjectClass *oc, void *data) { X86CPUClass *xcc =3D X86_CPU_CLASS(oc); @@ -6750,6 +6755,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->write_elf32_note =3D x86_cpu_write_elf32_note; cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; cc->legacy_vmsd =3D &vmstate_x86_cpu; + cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 cc->gdb_arch_name =3D x86_gdb_arch_name; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index a14874b4da2..600812d682b 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -503,6 +503,11 @@ static const VMStateDescription vmstate_m68k_cpu =3D { }; #endif =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps m68k_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps m68k_tcg_ops =3D { @@ -535,6 +540,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) #if defined(CONFIG_SOFTMMU) cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_m68k_cpu; + cc->sysemu_ops =3D &m68k_sysemu_ops; #endif cc->disas_set_info =3D m68k_cpu_disas_set_info; =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 433ba202037..c6a10b1a52b 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -352,6 +352,11 @@ static ObjectClass *mb_cpu_class_by_name(const char *c= pu_model) return object_class_by_name(TYPE_MICROBLAZE_CPU); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps mb_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps mb_tcg_ops =3D { @@ -388,6 +393,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; dc->vmsd =3D &vmstate_mb_cpu; + cc->sysemu_ops =3D &mb_sysemu_ops; #endif device_class_set_props(dc, mb_properties); cc->gdb_num_core_regs =3D 32 + 27; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index eba56ac8996..e61677fab74 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -521,6 +521,11 @@ static Property mips_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps mips_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" /* @@ -562,6 +567,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->legacy_vmsd =3D &vmstate_mips_cpu; + cc->sysemu_ops =3D &mips_sysemu_ops; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; cc->gdb_num_core_regs =3D 73; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index e9c9fc3a389..296ccc0ed3c 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -207,6 +207,11 @@ static Property nios2_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps nios2_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps nios2_tcg_ops =3D { @@ -238,6 +243,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->disas_set_info =3D nios2_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; + cc->sysemu_ops =3D &nios2_sysemu_ops; #endif cc->gdb_read_register =3D nios2_cpu_gdb_read_register; cc->gdb_write_register =3D nios2_cpu_gdb_write_register; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 2c64842f46b..cd8e3ae6754 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -174,6 +174,11 @@ static void openrisc_any_initfn(Object *obj) | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps openrisc_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps openrisc_tcg_ops =3D { @@ -205,6 +210,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_openrisc_cpu; + cc->sysemu_ops =3D &openrisc_sysemu_ops; #endif cc->gdb_num_core_regs =3D 32 + 3; cc->disas_set_info =3D openrisc_disas_set_info; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 16510da2597..f23eb63d186 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -596,6 +596,11 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState = *cs, const char *xmlname) return NULL; } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps riscv_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps riscv_tcg_ops =3D { @@ -639,6 +644,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; cc->legacy_vmsd =3D &vmstate_riscv_cpu; + cc->sysemu_ops =3D &riscv_sysemu_ops; cc->write_elf64_note =3D riscv_cpu_write_elf64_note; cc->write_elf32_note =3D riscv_cpu_write_elf32_note; #endif diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 7ac6618b26b..bbee1cb913f 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -173,6 +173,11 @@ static void rx_cpu_init(Object *obj) qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps rx_sysemu_ops =3D { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps rx_tcg_ops =3D { @@ -202,6 +207,9 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) cc->dump_state =3D rx_cpu_dump_state; cc->set_pc =3D rx_cpu_set_pc; =20 +#ifndef CONFIG_USER_ONLY + cc->sysemu_ops =3D &rx_sysemu_ops; +#endif cc->gdb_read_register =3D rx_cpu_gdb_read_register; cc->gdb_write_register =3D rx_cpu_gdb_write_register; cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 7ce425f6111..1fb4af4f2ca 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -476,6 +476,11 @@ static void s390_cpu_reset_full(DeviceState *dev) return s390_cpu_reset(s, S390_CPU_RESET_CLEAR); } =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps s390_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 @@ -519,6 +524,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->legacy_vmsd =3D &vmstate_s390_cpu; cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; + cc->sysemu_ops =3D &s390_sysemu_ops; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; cc->gdb_num_core_regs =3D S390_NUM_CORE_REGS; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 35d4251aaf3..85e15ec9954 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -223,6 +223,9 @@ static const VMStateDescription vmstate_sh_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, }; + +static const struct SysemuCPUOps sh4_sysemu_ops =3D { +}; #endif =20 #include "hw/core/tcg-cpu-ops.h" @@ -259,6 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_write_register =3D superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; + cc->sysemu_ops =3D &sh4_sysemu_ops; dc->vmsd =3D &vmstate_sh_cpu; #endif cc->disas_set_info =3D superh_cpu_disas_set_info; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index ba497561bfa..743a7287a4f 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -848,6 +848,11 @@ static Property sparc_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST() }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps sparc_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 @@ -890,6 +895,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->legacy_vmsd =3D &vmstate_sparc_cpu; + cc->sysemu_ops =3D &sparc_sysemu_ops; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; =20 diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 0b1e139bcba..8865fa18fce 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -142,6 +142,9 @@ static void tc27x_initfn(Object *obj) set_feature(&cpu->env, TRICORE_FEATURE_161); } =20 +static const struct SysemuCPUOps tricore_sysemu_ops =3D { +}; + #include "hw/core/tcg-cpu-ops.h" =20 static struct TCGCPUOps tricore_tcg_ops =3D { @@ -171,6 +174,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; + cc->sysemu_ops =3D &tricore_sysemu_ops; cc->tcg_ops =3D &tricore_tcg_ops; } =20 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index a66527e2d45..d0bf06696e4 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -181,6 +181,9 @@ static const VMStateDescription vmstate_xtensa_cpu =3D { .name =3D "cpu", .unmigratable =3D 1, }; + +static const struct SysemuCPUOps xtensa_sysemu_ops =3D { +}; #endif =20 #include "hw/core/tcg-cpu-ops.h" @@ -217,6 +220,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_write_register =3D xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint =3D true; #ifndef CONFIG_USER_ONLY + cc->sysemu_ops =3D &xtensa_sysemu_ops; cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_xtensa_cpu; #endif diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index f0f198e717f..9e828402a35 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10237,6 +10237,11 @@ static Property ppc_cpu_properties[] =3D { DEFINE_PROP_END_OF_LIST(), }; =20 +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps ppc_sysemu_ops =3D { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" =20 @@ -10280,6 +10285,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->legacy_vmsd =3D &vmstate_ppc_cpu; + cc->sysemu_ops =3D &ppc_sysemu_ops; #endif #if defined(CONFIG_SOFTMMU) cc->write_elf64_note =3D ppc64_cpu_write_elf64_note; --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) client-ip=209.85.128.47; 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[83.51.215.31]) by smtp.gmail.com with ESMTPSA id v12sm18894444wrv.76.2021.05.17.03.52.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:52:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J3KkyeAHowjlEzex1WLthgPCVr0R+I2QlAwoz2UGp0U=; b=k72uOhN3De4XB0RFeJSsYEv20VpS2bwY/EgWxdrqyk0hFb/o6y5KKN2WjLmgI6hRqQ 1SXixgRr2my9rAsxUftcur++udG4Yd3EHw5J7PWb8r/NJv4JMPRhNnW3bYj0/U6lWHM3 As//QVnAeNyn8JBhSB+PRbQCIwzb/NeS7kQ0R9rwh6DPdWWk3Ly0stfYCL1mpU8h1hzj t8djT6xKzNtzcr2N/Ij01FpfC8sbgMA6CrsqImVTroK9ZLihY3iggqNym9p8ZfARswsJ MPt/NzvMRtU9PZb3YZaUhMcfdWiKI1lNx7vZyBALrjDrEENXpDxSLZOI2evxFz4uWGyE 7vcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=J3KkyeAHowjlEzex1WLthgPCVr0R+I2QlAwoz2UGp0U=; b=ZyEl/L2sryjHts+/lxdVsG9MlPK//LOGL8bFjzb3SnBc2TRCer0nglV+J9rS1+Fng5 o3jSxNVXwcZ+433yyKYvQhyYqlO0ro2S9qTS3v/88InnxY4rCzk9+RMvF5YcCl4MzgxI QBveWk/wnlQEQE7wLxRupePDfpwWx0ItQ0EHQHJYAG1pinUC9u1Rw54x2LWnISn/RQLZ sHjRTQAXHeCtuJ446K+TsvB1ofTXCPxRBfGyNLd7ZCykF7JQz8QMjrWpqmu2rn6m6fi8 4aCbjAoi5ZmA4UQFXYqcuqEhqCt2nAvTAQ3oavsVdCj9GG1tBeB4RXFthPl18ue7LEoR +ysw== X-Gm-Message-State: AOAM530WeYIWGeJbbt/vBLy1tFp1DE8rdfIfCVntU2adMoCWZ76IhVGG 4jCFIqSXYB+18csibgpIdfc= X-Google-Smtp-Source: ABdhPJzbve7Elmdz0zpUPEI3D7THwAgrpv6jYPvYg1YlosjUEqQwkDmR0R2QN4VmFej+fbuI4vMhFQ== X-Received: by 2002:a7b:c206:: with SMTP id x6mr22680958wmi.72.1621248775774; Mon, 17 May 2021 03:52:55 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 15/23] cpu: Move CPUClass::vmsd to SysemuCPUOps Date: Mon, 17 May 2021 12:51:32 +0200 Message-Id: <20210517105140.1062037-16-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Migration is specific to system emulation. - Move the CPUClass::vmsd field to SysemuCPUOps, - restrict VMSTATE_CPU() macro to sysemu, - vmstate_dummy is now unused, remove it. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 8 ++------ include/hw/core/sysemu-cpu-ops.h | 6 ++++++ include/migration/vmstate.h | 2 -- cpu.c | 15 +++++++-------- stubs/vmstate.c | 2 -- target/arm/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 12 files changed, 22 insertions(+), 25 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index da55d310d4b..8e4f0662eb5 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -124,8 +124,6 @@ struct AccelCPUClass; * 32-bit VM coredump. * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF * note to a 32-bit VM coredump. - * @legacy_vmsd: Legacy state description for migration. - * Do not use in new targets, use #DeviceClass::vmsd instead. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to s= top @@ -180,7 +178,6 @@ struct CPUClass { int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, void *opaque); =20 - const VMStateDescription *legacy_vmsd; const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); @@ -1064,10 +1061,8 @@ bool target_words_bigendian(void); #ifdef NEED_CPU_H =20 #ifdef CONFIG_SOFTMMU + extern const VMStateDescription vmstate_cpu_common; -#else -#define vmstate_cpu_common vmstate_dummy -#endif =20 #define VMSTATE_CPU() { = \ .name =3D "parent_obj", = \ @@ -1076,6 +1071,7 @@ extern const VMStateDescription vmstate_cpu_common; .flags =3D VMS_STRUCT, = \ .offset =3D 0, = \ } +#endif /* CONFIG_SOFTMMU */ =20 #endif /* NEED_CPU_H */ =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index e54a08ea25e..0370ac15196 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,12 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @legacy_vmsd: Legacy state for migration. + * Do not use in new targets, use #DeviceClass::vmsd ins= tead. + */ + const VMStateDescription *legacy_vmsd; + } SysemuCPUOps; =20 #endif /* SYSEMU_CPU_OPS_H */ diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index 075ee800960..8df7b69f389 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -194,8 +194,6 @@ struct VMStateDescription { const VMStateDescription **subsections; }; =20 -extern const VMStateDescription vmstate_dummy; - extern const VMStateInfo vmstate_info_bool; =20 extern const VMStateInfo vmstate_info_int8; diff --git a/cpu.c b/cpu.c index c57f4c302bc..76047fcd4d6 100644 --- a/cpu.c +++ b/cpu.c @@ -127,7 +127,9 @@ const VMStateDescription vmstate_cpu_common =3D { =20 void cpu_exec_realizefn(CPUState *cpu, Error **errp) { +#ifndef CONFIG_USER_ONLY CPUClass *cc =3D CPU_GET_CLASS(cpu); +#endif =20 cpu_list_add(cpu); if (!accel_cpu_realizefn(cpu, errp)) { @@ -143,26 +145,23 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) #ifdef CONFIG_USER_ONLY assert(qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL || qdev_get_vmsd(DEVICE(cpu))->unmigratable); - assert(cc->legacy_vmsd =3D=3D NULL); #else if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); } - if (cc->legacy_vmsd !=3D NULL) { - vmstate_register(NULL, cpu->cpu_index, cc->legacy_vmsd, cpu); + if (cc->sysemu_ops->legacy_vmsd !=3D NULL) { + vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd= , cpu); } #endif /* CONFIG_USER_ONLY */ } =20 void cpu_exec_unrealizefn(CPUState *cpu) { +#ifndef CONFIG_USER_ONLY CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 -#ifdef CONFIG_USER_ONLY - assert(cc->legacy_vmsd =3D=3D NULL); -#else - if (cc->legacy_vmsd !=3D NULL) { - vmstate_unregister(NULL, cc->legacy_vmsd, cpu); + if (cc->sysemu_ops->legacy_vmsd !=3D NULL) { + vmstate_unregister(NULL, cc->sysemu_ops->legacy_vmsd, cpu); } if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { vmstate_unregister(NULL, &vmstate_cpu_common, cpu); diff --git a/stubs/vmstate.c b/stubs/vmstate.c index cc4fe41dfc2..8513d9204e4 100644 --- a/stubs/vmstate.c +++ b/stubs/vmstate.c @@ -1,8 +1,6 @@ #include "qemu/osdep.h" #include "migration/vmstate.h" =20 -const VMStateDescription vmstate_dummy =3D {}; - int vmstate_register_with_alias_id(VMStateIf *obj, uint32_t instance_id, const VMStateDescription *vmsd, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a9c9389859b..0a104cec633 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1944,6 +1944,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .legacy_vmsd =3D &vmstate_arm_cpu, }; #endif =20 @@ -1986,7 +1987,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; - cc->legacy_vmsd =3D &vmstate_arm_cpu; cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 35ef2eb1a41..f8750f6400f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6716,6 +6716,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .legacy_vmsd =3D &vmstate_x86_cpu, }; #endif =20 @@ -6754,7 +6755,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; cc->write_elf32_note =3D x86_cpu_write_elf32_note; cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; - cc->legacy_vmsd =3D &vmstate_x86_cpu; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index e61677fab74..a74b7fab318 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -523,6 +523,7 @@ static Property mips_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps mips_sysemu_ops =3D { + .legacy_vmsd =3D &vmstate_mips_cpu, }; #endif =20 @@ -566,7 +567,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; - cc->legacy_vmsd =3D &vmstate_mips_cpu; cc->sysemu_ops =3D &mips_sysemu_ops; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f23eb63d186..e724c10a2ed 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -598,6 +598,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *= cs, const char *xmlname) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps riscv_sysemu_ops =3D { + .legacy_vmsd =3D &vmstate_riscv_cpu, }; #endif =20 @@ -643,7 +644,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; - cc->legacy_vmsd =3D &vmstate_riscv_cpu; cc->sysemu_ops =3D &riscv_sysemu_ops; cc->write_elf64_note =3D riscv_cpu_write_elf64_note; cc->write_elf32_note =3D riscv_cpu_write_elf32_note; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 1fb4af4f2ca..aafe5fa2ef5 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -478,6 +478,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps s390_sysemu_ops =3D { + .legacy_vmsd =3D &vmstate_s390_cpu, }; #endif =20 @@ -521,7 +522,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; - cc->legacy_vmsd =3D &vmstate_s390_cpu; cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; cc->sysemu_ops =3D &s390_sysemu_ops; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 743a7287a4f..543853c24dc 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps sparc_sysemu_ops =3D { + .legacy_vmsd =3D &vmstate_sparc_cpu, }; #endif =20 @@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; - cc->legacy_vmsd =3D &vmstate_sparc_cpu; cc->sysemu_ops =3D &sparc_sysemu_ops; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 9e828402a35..9f20cdb569b 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10239,6 +10239,7 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps ppc_sysemu_ops =3D { + .legacy_vmsd =3D &vmstate_ppc_cpu, }; #endif =20 @@ -10284,7 +10285,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_write_register =3D ppc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; - cc->legacy_vmsd =3D &vmstate_ppc_cpu; cc->sysemu_ops =3D &ppc_sysemu_ops; #endif #if defined(CONFIG_SOFTMMU) --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; 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[83.51.215.31]) by smtp.gmail.com with ESMTPSA id f4sm17426570wrz.33.2021.05.17.03.52.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:53:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=63onU3fEYl+uRL/ePx949VTfyQdXHEiC6uRm6+a0hK8=; b=KaoKdbeif/Ibc1q3jebyXE+kfjBYxefCHMKFCfVGN7ZWvalO9bzRVDCahiWZlgIOlY jp86O9+9tTtKOb8jAsNJuOhuqVI2IZB66vA0KIAizRxF3puxmXlzkdjbCEt5KwT3inG3 KSaayB1T/OhtY04TY7HhUrPr7Tud4N1dSqIueRUnz4CCCTfJpTHea75DoIv/KeXNNBft /dE7HBHuLc3iTKJlnWPk0zNDfcV+XBwafO57ai1rCMvAYXUepVEwJXhLuNB6fffhVAwn h2D7E2mh6RJs/XEMpHNPQGYp5bUqZNg3V+awER0EsvBfm7NROsRvwfBlUY3Y/E/irf7h 2KrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=63onU3fEYl+uRL/ePx949VTfyQdXHEiC6uRm6+a0hK8=; b=VtMKw1gqWTK87vR2mwhQtBa1YevVn8+T8HlcQeuPL3+jFqqlAFUqRxUprJPOz488tV aoSsb98snxi3KehqAk5TZDOeL/KBlm3lUNQhnVT88BTYQhyK0CD98sbgisR3AcGMz6Ni PQdFhwfdIgAChWliquICogZcXNo7y567R8TFlYYBJr6XA6PJCHtSWn4HcrId7iSBPrZj 0VXcZ3IUSt3tGi5u2H1EppFJi/xieX2bMf3M83BwKGyg8h0tJ7lgRKYK6KSrDhNzLUKV R5P7lapP7No9S5PBh7eaM311FF9e6SJyzWQgwgzjNY3XySRJjo85IQ0dpn03Z232LcBY 2CNA== X-Gm-Message-State: AOAM533h4cW+RkGiQjbnruAyH/CjP0Nd4fnRywV75xlQ9RuipC66sRYP DmW2S4iSFcWoLZBLg5TIleE= X-Google-Smtp-Source: ABdhPJwxzxTtvDIXAOW55WeFxDVgptFoXz1U/8jWr+4SXApU3E7rkOkXDelW/laOysP7uSBEUhFGwg== X-Received: by 2002:adf:fb87:: with SMTP id a7mr74184247wrr.58.1621248780538; Mon, 17 May 2021 03:53:00 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 16/23] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps Date: Mon, 17 May 2021 12:51:33 +0200 Message-Id: <20210517105140.1062037-17-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) VirtIO devices are only meaningful with system emulation. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 5 ----- include/hw/core/sysemu-cpu-ops.h | 9 +++++++++ hw/core/cpu-sysemu.c | 5 +++-- target/arm/cpu.c | 2 +- target/ppc/translate_init.c.inc | 4 +--- 5 files changed, 14 insertions(+), 11 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 8e4f0662eb5..1b7e815c871 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -89,10 +89,6 @@ struct AccelCPUClass; * @parse_features: Callback to parse command line arguments. * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @has_work: Callback for checking if there is work to do. - * @virtio_is_big_endian: Callback to return %true if a CPU which supports - * runtime configurable endianness is currently big-endian. Non-configurab= le - * CPUs can use the default implementation of this method. This method sho= uld - * not be used by any callers other than the pre-1.0 virtio devices. * @memory_rw_debug: Callback for GDB memory access. * @dump_state: Callback for dumping state. * @dump_statistics: Callback for dumping statistics. @@ -151,7 +147,6 @@ struct CPUClass { =20 int reset_dump_flags; bool (*has_work)(CPUState *cpu); - bool (*virtio_is_big_endian)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 0370ac15196..ed212085f89 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,15 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @virtio_is_big_endian: Callback to return %true if a CPU which supp= orts + * runtime configurable endianness is currently big-endian. + * Non-configurable CPUs can use the default implementation of this me= thod. + * This method should not be used by any callers other than the pre-1.0 + * virtio devices. + */ + bool (*virtio_is_big_endian)(CPUState *cpu); + /** * @legacy_vmsd: Legacy state for migration. * Do not use in new targets, use #DeviceClass::vmsd ins= tead. diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index aa68ca281e8..bad7d2cb016 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/core/cpu.h" +#include "hw/core/sysemu-cpu-ops.h" =20 bool cpu_paging_enabled(const CPUState *cpu) { @@ -126,8 +127,8 @@ bool cpu_virtio_is_big_endian(CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->virtio_is_big_endian) { - return cc->virtio_is_big_endian(cpu); + if (cc->sysemu_ops->virtio_is_big_endian) { + return cc->sysemu_ops->virtio_is_big_endian(cpu); } return target_words_bigendian(); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0a104cec633..9100947905a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1944,6 +1944,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian, .legacy_vmsd =3D &vmstate_arm_cpu, }; #endif @@ -1987,7 +1988,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; - cc->virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian; cc->write_elf64_note =3D arm_cpu_write_elf64_note; cc->write_elf32_note =3D arm_cpu_write_elf32_note; cc->sysemu_ops =3D &arm_sysemu_ops; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 9f20cdb569b..73e859ea0d3 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10239,6 +10239,7 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps ppc_sysemu_ops =3D { + .virtio_is_big_endian =3D ppc_cpu_is_big_endian, .legacy_vmsd =3D &vmstate_ppc_cpu, }; #endif @@ -10307,9 +10308,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_core_xml_file =3D "power64-core.xml"; #else cc->gdb_core_xml_file =3D "power-core.xml"; -#endif -#ifndef CONFIG_USER_ONLY - cc->virtio_is_big_endian =3D ppc_cpu_is_big_endian; #endif cc->disas_set_info =3D ppc_disas_set_info; =20 --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) client-ip=209.85.221.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1621248786; cv=none; d=zohomail.com; s=zohoarc; b=O1d/mBgFajfQuyLe8jWRqdPJRGI769VVTGMZDD2za29laLBlCUqvdLRxXaVSXCiT9KHOfZwY+atyS3pWXciBzv2INmTUaiPFrThgclgHsj3A8x8OGr9+WnyH8BdFHLQgyiEv2pBjrP8jEXVd1zZ0xH5XZakX18/clkSOxfSFtlY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[83.51.215.31]) by smtp.gmail.com with ESMTPSA id e3sm6058502wru.48.2021.05.17.03.53.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:53:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mNroUX3BeAka8NdiLyy2HrifOJFWYU+B+TgnTgbcsqY=; b=htA/JO62MIPWqMM8tgAdaw8+n8BDVcJmTO6X9HNgLDImG7fCL54Hsf4Ua24ZjaYeAY eRuOYkPGrbnw4AWxRWP7fUCYAji7KmG8OGKUZIZc/hEnNTZ8r/X23/P1jDFmFPLwkpot Qr8irfpNnCQscmEoiQYLUhXopnmU9sJbFYzcM2wg3x81Rw3syjnvqIVu8cLxu3GlG1xW E6CDvp2YwD/htIBWiGb+FuLkFLUeZu7crgfdmzk0q0h1Q3QZcpVHNdMNhd420CdLkhwY S5//4ebo9obU4cCqW3G6LpBF92MSGet81re/9OvWkMv7r95O8ZnHUsISxlWHfZI4yS6g xzOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=mNroUX3BeAka8NdiLyy2HrifOJFWYU+B+TgnTgbcsqY=; b=lAsQZFjN/Z3XSnhyoemvYpTOpYxGQHWPNmFMgTUyhXXjFvGz0SdLHXBGgtdFxqjbt4 wDCM32xGfOWrwookw8UIV2RINnOfC3T3FoH7hecVoEpU890CMTqpMP9kD1zQST5pBLhU ieqNkKZ7GFuVudXc1Fa0OiecyIh98a2MP/svmm9lhqZAwBIbvJiorg++aTBwSb9bQM/G 5nyJpFJ641IAqJ5EoX3xfsxQ10Ubj6Z1jvEo/4b8JQTvJDApHebYK4Ur/OIqwGCI1dp6 5wEKBYWkYo20XWcLx2q7gq/0Z5m92R+ZMoZWoGt+pLp+MVwPkFu3+xWocpZRWq9mADgJ qSog== X-Gm-Message-State: AOAM5304qbHbHwzr3stzgbyo2Nfz0V616xV/AHvdzyVxEUJpovxc1bpb jNLgoAE44f9c/ztfLuhYaKQ= X-Google-Smtp-Source: ABdhPJy/wkIOO3bdTRTA4r7yyPIY92NFP4/oBAwG1Y9cz+mafUmCu45WXOvC8zg7Wy+/7EgmGsv2MQ== X-Received: by 2002:a5d:52c5:: with SMTP id r5mr73462267wrv.391.1621248785231; Mon, 17 May 2021 03:53:05 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 17/23] cpu: Move CPUClass::get_crash_info to SysemuCPUOps Date: Mon, 17 May 2021 12:51:34 +0200 Message-Id: <20210517105140.1062037-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) cpu_get_crash_info() is called on GUEST_PANICKED events, which only occur in system emulation. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 1 - include/hw/core/sysemu-cpu-ops.h | 5 +++++ hw/core/cpu-sysemu.c | 4 ++-- target/i386/cpu.c | 2 +- target/s390x/cpu.c | 2 +- 5 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 1b7e815c871..6f5e04ae580 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -150,7 +150,6 @@ struct CPUClass { int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); void (*dump_state)(CPUState *cpu, FILE *, int flags); - GuestPanicInformation* (*get_crash_info)(CPUState *cpu); void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); bool (*get_paging_enabled)(const CPUState *cpu); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index ed212085f89..c6ec9b0a7f6 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_crash_info: Callback for reporting guest crash information in + * GUEST_PANICKED events. + */ + GuestPanicInformation* (*get_crash_info)(CPUState *cpu); /** * @virtio_is_big_endian: Callback to return %true if a CPU which supp= orts * runtime configurable endianness is currently big-endian. diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index bad7d2cb016..90b5ac8eb9e 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -138,8 +138,8 @@ GuestPanicInformation *cpu_get_crash_info(CPUState *cpu) CPUClass *cc =3D CPU_GET_CLASS(cpu); GuestPanicInformation *res =3D NULL; =20 - if (cc->get_crash_info) { - res =3D cc->get_crash_info(cpu); + if (cc->sysemu_ops->get_crash_info) { + res =3D cc->sysemu_ops->get_crash_info(cpu); } return res; } diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f8750f6400f..1106dc3fc98 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6716,6 +6716,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .get_crash_info =3D x86_cpu_get_crash_info, .legacy_vmsd =3D &vmstate_x86_cpu, }; #endif @@ -6750,7 +6751,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; - cc->get_crash_info =3D x86_cpu_get_crash_info; cc->write_elf64_note =3D x86_cpu_write_elf64_note; cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; cc->write_elf32_note =3D x86_cpu_write_elf32_note; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index aafe5fa2ef5..470aaeb72e6 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -478,6 +478,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps s390_sysemu_ops =3D { + .get_crash_info =3D s390_cpu_get_crash_info, .legacy_vmsd =3D &vmstate_s390_cpu, }; #endif @@ -522,7 +523,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; - cc->get_crash_info =3D s390_cpu_get_crash_info; cc->write_elf64_note =3D s390_cpu_write_elf64_note; cc->sysemu_ops =3D &s390_sysemu_ops; #endif --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1621248791; cv=none; d=zohomail.com; s=zohoarc; b=J6AXDGWkg8qodSZNq0QSw3e6uOFzZ5SLfOKwIckRUVlPmUroGtmQJ6SmeXWMk/5lZIjn04DEAwGaQOiYkth934JAtCF6WU148AjBNCAb7CWZd5B16qg82w7Qv5SeZq+1fLSzYtzJ0KS7IEs8bFkoHSyn57TZb+kH1GMvWdTXGHk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621248791; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; 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[83.51.215.31]) by smtp.gmail.com with ESMTPSA id r5sm11135324wrw.96.2021.05.17.03.53.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:53:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4ZG0pkj4UWtVe9/4Fh6Wi0BGus1XDQNTQXT8vjTo2FU=; b=hDRrrf4jR9nv3UB5od7RygSuLKh0xnmIRXeIqmy3a/frnSBlWG1eFTyK1uti3d5FRV 9ADQ6Kn7jEZT7wUSoQhrUOPh4G91S2Qae1b4ANV1qDMBA5dA2i471FAp1RzReI/Z+3MP ULQoh/YAPBnsSO4Ap5OsrwrjUyyA8FdWQZTLhNtUg2sXrTLU6woejpmzPdJIKSToNuHD KYwGiqZU8aoRS6g0PvrblkivL0r/U/cfif34hBHTJQpvLgz3Riq5QUX8yp/PW3D1oRro Dg39CGj8arSffctLQyXka4mvZNwMKzd0Fdfp5M52Q7ER/W61Hl6Ll359kEirUu/fZDKJ 5a4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=4ZG0pkj4UWtVe9/4Fh6Wi0BGus1XDQNTQXT8vjTo2FU=; b=LcFTQ3i/R2EZNKPgc8OfbxEzuMEsUPFNV7Ptj0PELIK8kBalNNrU6qQP0Z2m4Jmsu5 Hfyu7CoWzJuOjpHz5aBsxP3OF4z2Y1iwV8sqsQgBNAewfpx1mLqfC4/rVNdh+0bn0IgX +uTfz7zT8pUYQQ/9O/S+QUtfxBlTHrpO9Po5qmGDnS0PQOp+InYppKUQHGqC0W/+/610 +rBSTZMgswtzARpGCNSIJfNlBvV1GaFnNs4IwwXZAIFheFjNpC/U7a7kh4tVsJgca+X+ OfFUKXTPmGqZtxWXwAmnYfRce8ciwKoeaUqrt8ETssnfHDdozSFqsxqJopBP/5DeWySN YdzQ== X-Gm-Message-State: AOAM533ugRRK0cY5oOHHhHE6kNq5nftgP6lxxJZP2RLkeZ5ccZug6oGo iW7FgY/13oyaJjopcJVPHI8= X-Google-Smtp-Source: ABdhPJxZhDi0X1JTY82rI7bQ5kO/AHO15yHSeY1NOQEZAwEItv5gJrXRFgdB6j9EqCuk2A5EGrjZzg== X-Received: by 2002:a5d:5184:: with SMTP id k4mr28144900wrv.84.1621248789949; Mon, 17 May 2021 03:53:09 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 18/23] cpu: Move CPUClass::write_elf* to SysemuCPUOps Date: Mon, 17 May 2021 12:51:35 +0200 Message-Id: <20210517105140.1062037-19-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The write_elf*() handlers are used to dump vmcore images. This feature is only meaningful for system emulation. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 17 ----------------- include/hw/core/sysemu-cpu-ops.h | 24 ++++++++++++++++++++++++ hw/core/cpu-sysemu.c | 16 ++++++++-------- target/arm/cpu.c | 4 ++-- target/i386/cpu.c | 8 ++++---- target/riscv/cpu.c | 4 ++-- target/s390x/cpu.c | 2 +- target/ppc/translate_init.c.inc | 6 ++---- 8 files changed, 43 insertions(+), 38 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 6f5e04ae580..fce9bdc686e 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -112,14 +112,6 @@ struct AccelCPUClass; * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. - * @write_elf64_note: Callback for writing a CPU-specific ELF note to a - * 64-bit VM coredump. - * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF - * note to a 32-bit VM coredump. - * @write_elf32_note: Callback for writing a CPU-specific ELF note to a - * 32-bit VM coredump. - * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF - * note to a 32-bit VM coredump. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to s= top @@ -163,15 +155,6 @@ struct CPUClass { int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 - int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque); - int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque); - int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, - int cpuid, void *opaque); - int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, - void *opaque); - const char *gdb_core_xml_file; gchar * (*gdb_arch_name)(CPUState *cpu); const char * (*gdb_get_dynamic_xml)(CPUState *cpu, const char *xmlname= ); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index c6ec9b0a7f6..19247d330dc 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -21,6 +21,30 @@ typedef struct SysemuCPUOps { * GUEST_PANICKED events. */ GuestPanicInformation* (*get_crash_info)(CPUState *cpu); + /** + * @write_elf32_note: Callback for writing a CPU-specific ELF note to a + * 32-bit VM coredump. + */ + int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque); + /** + * @write_elf64_note: Callback for writing a CPU-specific ELF note to a + * 64-bit VM coredump. + */ + int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, + int cpuid, void *opaque); + /** + * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specifi= c ELF + * note to a 32-bit VM coredump. + */ + int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque); + /** + * @write_elf64_qemunote: Callback for writing a CPU- and QEMU-specifi= c ELF + * note to a 64-bit VM coredump. + */ + int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, + void *opaque); /** * @virtio_is_big_endian: Callback to return %true if a CPU which supp= orts * runtime configurable endianness is currently big-endian. diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index 90b5ac8eb9e..d55ef8d23d1 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -84,10 +84,10 @@ int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, C= PUState *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf32_qemunote) { + if (!cc->sysemu_ops->write_elf32_qemunote) { return 0; } - return (*cc->write_elf32_qemunote)(f, cpu, opaque); + return (*cc->sysemu_ops->write_elf32_qemunote)(f, cpu, opaque); } =20 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, @@ -95,10 +95,10 @@ int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUSt= ate *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf32_note) { + if (!cc->sysemu_ops->write_elf32_note) { return -1; } - return (*cc->write_elf32_note)(f, cpu, cpuid, opaque); + return (*cc->sysemu_ops->write_elf32_note)(f, cpu, cpuid, opaque); } =20 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, @@ -106,10 +106,10 @@ int cpu_write_elf64_qemunote(WriteCoreDumpFunction f,= CPUState *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf64_qemunote) { + if (!cc->sysemu_ops->write_elf64_qemunote) { return 0; } - return (*cc->write_elf64_qemunote)(f, cpu, opaque); + return (*cc->sysemu_ops->write_elf64_qemunote)(f, cpu, opaque); } =20 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, @@ -117,10 +117,10 @@ int cpu_write_elf64_note(WriteCoreDumpFunction f, CPU= State *cpu, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (!cc->write_elf64_note) { + if (!cc->sysemu_ops->write_elf64_note) { return -1; } - return (*cc->write_elf64_note)(f, cpu, cpuid, opaque); + return (*cc->sysemu_ops->write_elf64_note)(f, cpu, cpuid, opaque); } =20 bool cpu_virtio_is_big_endian(CPUState *cpu) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9100947905a..a56de47d1fa 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1944,6 +1944,8 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .write_elf32_note =3D arm_cpu_write_elf32_note, + .write_elf64_note =3D arm_cpu_write_elf64_note, .virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian, .legacy_vmsd =3D &vmstate_arm_cpu, }; @@ -1988,8 +1990,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; - cc->write_elf64_note =3D arm_cpu_write_elf64_note; - cc->write_elf32_note =3D arm_cpu_write_elf32_note; cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1106dc3fc98..44c9546eda2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6717,6 +6717,10 @@ static Property x86_cpu_properties[] =3D { #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { .get_crash_info =3D x86_cpu_get_crash_info, + .write_elf32_note =3D x86_cpu_write_elf32_note, + .write_elf64_note =3D x86_cpu_write_elf64_note, + .write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote, + .write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote, .legacy_vmsd =3D &vmstate_x86_cpu, }; #endif @@ -6751,10 +6755,6 @@ static void x86_cpu_common_class_init(ObjectClass *o= c, void *data) cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; - cc->write_elf64_note =3D x86_cpu_write_elf64_note; - cc->write_elf64_qemunote =3D x86_cpu_write_elf64_qemunote; - cc->write_elf32_note =3D x86_cpu_write_elf32_note; - cc->write_elf32_qemunote =3D x86_cpu_write_elf32_qemunote; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e724c10a2ed..d86e44ca07d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -598,6 +598,8 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *= cs, const char *xmlname) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps riscv_sysemu_ops =3D { + .write_elf64_note =3D riscv_cpu_write_elf64_note, + .write_elf32_note =3D riscv_cpu_write_elf32_note, .legacy_vmsd =3D &vmstate_riscv_cpu, }; #endif @@ -645,8 +647,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; cc->sysemu_ops =3D &riscv_sysemu_ops; - cc->write_elf64_note =3D riscv_cpu_write_elf64_note; - cc->write_elf32_note =3D riscv_cpu_write_elf32_note; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; cc->gdb_get_dynamic_xml =3D riscv_gdb_get_dynamic_xml; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 470aaeb72e6..058ffcef15f 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -479,6 +479,7 @@ static void s390_cpu_reset_full(DeviceState *dev) #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps s390_sysemu_ops =3D { .get_crash_info =3D s390_cpu_get_crash_info, + .write_elf64_note =3D s390_cpu_write_elf64_note, .legacy_vmsd =3D &vmstate_s390_cpu, }; #endif @@ -523,7 +524,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; - cc->write_elf64_note =3D s390_cpu_write_elf64_note; cc->sysemu_ops =3D &s390_sysemu_ops; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 73e859ea0d3..86b11e1356a 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10239,6 +10239,8 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps ppc_sysemu_ops =3D { + .write_elf32_note =3D ppc32_cpu_write_elf32_note, + .write_elf64_note =3D ppc64_cpu_write_elf64_note, .virtio_is_big_endian =3D ppc_cpu_is_big_endian, .legacy_vmsd =3D &vmstate_ppc_cpu, }; @@ -10288,10 +10290,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &ppc_sysemu_ops; #endif -#if defined(CONFIG_SOFTMMU) - cc->write_elf64_note =3D ppc64_cpu_write_elf64_note; - cc->write_elf32_note =3D ppc32_cpu_write_elf32_note; -#endif =20 cc->gdb_num_core_regs =3D 71; #ifndef CONFIG_USER_ONLY --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 3 --- include/hw/core/sysemu-cpu-ops.h | 5 +++++ hw/core/cpu-sysemu.c | 4 ++-- target/arm/cpu.c | 2 +- target/i386/cpu.c | 2 +- 5 files changed, 9 insertions(+), 7 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index fce9bdc686e..cbc43f11376 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -108,8 +108,6 @@ struct AccelCPUClass; * associated memory transaction attributes to use for the access. * CPUs which use memory transaction attributes should implement this * instead of get_phys_page_debug. - * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for - * a memory access with the specified memory transaction attributes. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -151,7 +149,6 @@ struct CPUClass { hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); - int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 19247d330dc..894bb95e4fa 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @asidx_from_attrs: Callback to return the CPU AddressSpace to use f= or + * a memory access with the specified memory transaction attribu= tes. + */ + int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); /** * @get_crash_info: Callback for reporting guest crash information in * GUEST_PANICKED events. diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index d55ef8d23d1..ba53c2eaa85 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -72,8 +72,8 @@ int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) CPUClass *cc =3D CPU_GET_CLASS(cpu); int ret =3D 0; =20 - if (cc->asidx_from_attrs) { - ret =3D cc->asidx_from_attrs(cpu, attrs); + if (cc->sysemu_ops->asidx_from_attrs) { + ret =3D cc->sysemu_ops->asidx_from_attrs(cpu, attrs); assert(ret < cpu->num_ases && ret >=3D 0); } return ret; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a56de47d1fa..f8fc0d01956 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1944,6 +1944,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, .write_elf64_note =3D arm_cpu_write_elf64_note, .virtio_is_big_endian =3D arm_cpu_virtio_is_big_endian, @@ -1989,7 +1990,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; - cc->asidx_from_attrs =3D arm_asidx_from_attrs; cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 44c9546eda2..d050245b502 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6716,6 +6716,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, .write_elf32_note =3D x86_cpu_write_elf32_note, .write_elf64_note =3D x86_cpu_write_elf64_note, @@ -6752,7 +6753,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY - cc->asidx_from_attrs =3D x86_asidx_from_attrs; cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &i386_sysemu_ops; --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 8 -------- include/hw/core/sysemu-cpu-ops.h | 13 +++++++++++++ target/alpha/cpu.h | 2 +- target/arm/cpu.h | 6 +++--- target/cris/cpu.h | 4 ++-- target/hppa/cpu.h | 2 +- target/i386/cpu.h | 6 +++--- target/m68k/cpu.h | 5 ++++- target/microblaze/cpu.h | 5 ++--- target/nios2/cpu.h | 2 +- target/openrisc/cpu.h | 3 ++- target/ppc/cpu.h | 2 +- target/riscv/cpu.h | 2 +- target/rx/cpu.h | 2 ++ target/sh4/cpu.h | 2 +- target/sparc/cpu.h | 2 +- target/tricore/cpu.h | 2 ++ target/xtensa/cpu.h | 2 +- hw/core/cpu-sysemu.c | 6 +++--- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- target/ppc/translate_init.c.inc | 2 +- 38 files changed, 63 insertions(+), 51 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index cbc43f11376..b4d3a21bbf0 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -103,11 +103,6 @@ struct AccelCPUClass; * If the target behaviour here is anything other than "set * the PC register to the value passed in" then the target must * also implement the synchronize_from_tb hook. - * @get_phys_page_debug: Callback for obtaining a physical address. - * @get_phys_page_attrs_debug: Callback for obtaining a physical address a= nd the - * associated memory transaction attributes to use for the access. - * CPUs which use memory transaction attributes should implement this - * instead of get_phys_page_debug. * @gdb_read_register: Callback for letting GDB read a register. * @gdb_write_register: Callback for letting GDB write a register. * @gdb_num_core_regs: Number of core registers accessible to GDB. @@ -146,9 +141,6 @@ struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); - hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 894bb95e4fa..7f8ff641854 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,19 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_phys_page_debug: Callback for obtaining a physical address. + */ + hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); + /** + * @get_phys_page_attrs_debug: Callback for obtaining a physical addre= ss + * and the associated memory transaction attributes to use for t= he + * access. + * CPUs which use memory transaction attributes should implement this + * instead of get_phys_page_debug. + */ + hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); /** * @asidx_from_attrs: Callback to return the CPU AddressSpace to use f= or * a memory access with the specified memory transaction attribu= tes. diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 6541675d9d6..cb3021c1afa 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -275,6 +275,7 @@ struct AlphaCPU { #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_alpha_cpu; =20 +hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); @@ -283,7 +284,6 @@ void alpha_cpu_do_unaligned_access(CPUState *cpu, vaddr= addr, void alpha_cpu_do_interrupt(CPUState *cpu); bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req); void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags); -hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 616b3932534..1129b5ec0cc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1026,15 +1026,15 @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clust= ersz); =20 #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_arm_cpu; + +hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); #endif =20 void arm_cpu_do_interrupt(CPUState *cpu); void arm_v7m_cpu_do_interrupt(CPUState *cpu); bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); =20 -hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); - int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/target/cris/cpu.h b/target/cris/cpu.h index d3b64929096..aac921e221a 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -185,6 +185,8 @@ struct CRISCPU { =20 #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_cris_cpu; + +hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); #endif =20 void cris_cpu_do_interrupt(CPUState *cpu); @@ -193,8 +195,6 @@ bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req= ); =20 void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags); =20 -hwaddr cris_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); - int crisv10_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int cris_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int cris_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 748270bfa31..d125aeac1d3 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -322,7 +322,6 @@ void cpu_hppa_change_prot_id(CPUHPPAState *env); #define cpu_signal_handler cpu_hppa_signal_handler =20 int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); -hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void hppa_cpu_do_interrupt(CPUState *cpu); @@ -332,6 +331,7 @@ bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); #ifndef CONFIG_USER_ONLY +hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, int type, hwaddr *pphys, int *pprot); extern const MemoryRegionOps hppa_io_eir_ops; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 324ef92beb7..27a7214debe 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1800,6 +1800,9 @@ struct X86CPU { =20 #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_x86_cpu; + +hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); #endif =20 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); @@ -1818,9 +1821,6 @@ void x86_cpu_get_memory_mapping(CPUState *cpu, Memory= MappingList *list, =20 void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags); =20 -hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); - int x86_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index cf58fee9ada..7b17f59d40f 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -169,10 +169,13 @@ struct M68kCPU { void m68k_cpu_do_interrupt(CPUState *cpu); bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); void m68k_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int m68k_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 +#if !defined(CONFIG_USER_ONLY) +hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +#endif + void m68k_tcg_init(void); void m68k_cpu_init_gdb(M68kCPU *cpu); /* diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 348540c7640..444dc487456 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -358,8 +358,6 @@ struct MicroBlazeCPU { void mb_cpu_do_interrupt(CPUState *cs); bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, - MemTxAttrs *attrs); int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 @@ -417,7 +415,8 @@ static inline void cpu_get_tb_cpu_state(CPUMBState *env= , target_ulong *pc, } =20 #if !defined(CONFIG_USER_ONLY) - +hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index aa7b5cc9e16..75b0c9924bb 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -196,8 +196,8 @@ void nios2_cpu_do_interrupt(CPUState *cs); int cpu_nios2_signal_handler(int host_signum, void *pinfo, void *puc); void dump_mmu(CPUNios2State *env); void nios2_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); #ifndef CONFIG_USER_ONLY +hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void nios2_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 82cbaeb4f84..33ab91719c2 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -315,7 +315,6 @@ void cpu_openrisc_list(void); void openrisc_cpu_do_interrupt(CPUState *cpu); bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg= ); int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void openrisc_translate_init(void); @@ -331,6 +330,8 @@ int print_insn_or1k(bfd_vma addr, disassemble_info *inf= o); #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_openrisc_cpu; =20 +hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); + /* hw/openrisc_pic.c */ void cpu_openrisc_pic_init(OpenRISCCPU *cpu); =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 733a2168c48..69978fe0d9b 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1261,7 +1261,6 @@ void ppc_cpu_do_interrupt(CPUState *cpu); bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req); void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); void ppc_cpu_dump_statistics(CPUState *cpu, int flags); -hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int ppc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int ppc_cpu_gdb_read_register_apple(CPUState *cpu, GByteArray *buf, int re= g); int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); @@ -1275,6 +1274,7 @@ int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction = f, CPUState *cs, int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, int cpuid, void *opaque); #ifndef CONFIG_USER_ONLY +hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void ppc_cpu_do_system_reset(CPUState *cs); void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector); extern const VMStateDescription vmstate_ppc_cpu; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2dd66401127..6713bf6fb44 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -339,7 +339,6 @@ bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *en= v); void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable); bool riscv_cpu_two_stage_lookup(int mmu_idx); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); -hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); @@ -351,6 +350,7 @@ void riscv_cpu_list(void); #define cpu_mmu_index riscv_cpu_mmu_index =20 #ifndef CONFIG_USER_ONLY +hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 0b4b998c7be..2b7595ff372 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -129,7 +129,9 @@ bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req); void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +#ifndef CONFIG_USER_ONLY hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +#endif =20 void rx_translate_init(void); int cpu_rx_signal_handler(int host_signum, void *pinfo, diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index e41337a101d..64870023e31 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -207,7 +207,6 @@ struct SuperHCPU { void superh_cpu_do_interrupt(CPUState *cpu); bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); void superh_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int superh_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int superh_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 @@ -237,6 +236,7 @@ uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State *s, hwaddr addr); void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr, uint32_t mem_value); +hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void superh_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 60ff6306980..79e28eb2182 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -569,6 +569,7 @@ struct SPARCCPU { #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_sparc_cpu; =20 +hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, @@ -577,7 +578,6 @@ void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUSta= te *cpu, vaddr addr, =20 void sparc_cpu_do_interrupt(CPUState *cpu); void sparc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr sparc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t) QEMU_NORETURN; diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 4b61a2c03f8..0892ae647dc 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -207,7 +207,9 @@ struct TriCoreCPU { }; =20 =20 +#ifndef CONFIG_USER_ONLY hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +#endif void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags); =20 =20 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index d08e60c673e..d40d8b7d863 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -570,7 +570,6 @@ bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, void xtensa_cpu_do_interrupt(CPUState *cpu); bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void xtensa_count_regs(const XtensaConfig *config, unsigned *n_regs, unsigned *n_core_regs); int xtensa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); @@ -668,6 +667,7 @@ static inline int xtensa_get_cring(const CPUXtensaState= *env) } =20 #ifndef CONFIG_USER_ONLY +hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index ba53c2eaa85..b31c33ad2b5 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -52,12 +52,12 @@ hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vad= dr addr, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_phys_page_attrs_debug) { - return cc->get_phys_page_attrs_debug(cpu, addr, attrs); + if (cc->sysemu_ops->get_phys_page_attrs_debug) { + return cc->sysemu_ops->get_phys_page_attrs_debug(cpu, addr, attrs); } /* Fallback for CPUs which don't implement the _attrs_ hook */ *attrs =3D MEMTXATTRS_UNSPECIFIED; - return cc->get_phys_page_debug(cpu, addr); + return cc->sysemu_ops->get_phys_page_debug(cpu, addr); } =20 hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index cd01d34d92f..979a4c0be1e 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -208,6 +208,7 @@ static void alpha_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps alpha_sysemu_ops =3D { + .get_phys_page_debug =3D alpha_cpu_get_phys_page_debug, }; #endif =20 @@ -241,7 +242,6 @@ static void alpha_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D alpha_cpu_gdb_read_register; cc->gdb_write_register =3D alpha_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D alpha_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_alpha_cpu; cc->sysemu_ops =3D &alpha_sysemu_ops; #endif diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f8fc0d01956..f29649ecba7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1944,6 +1944,7 @@ static gchar *arm_gdb_arch_name(CPUState *cs) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps arm_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D arm_asidx_from_attrs, .write_elf32_note =3D arm_cpu_write_elf32_note, .write_elf64_note =3D arm_cpu_write_elf64_note, @@ -1989,7 +1990,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D arm_cpu_gdb_read_register; cc->gdb_write_register =3D arm_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &arm_sysemu_ops; #endif cc->gdb_num_core_regs =3D 26; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 5c8bb9b3fec..a357ff0bffb 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -185,6 +185,7 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, i= nt flags) } =20 static const struct SysemuCPUOps avr_sysemu_ops =3D { + .get_phys_page_debug =3D avr_cpu_get_phys_page_debug, }; =20 #include "hw/core/tcg-cpu-ops.h" @@ -215,7 +216,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *d= ata) cc->dump_state =3D avr_cpu_dump_state; cc->set_pc =3D avr_cpu_set_pc; cc->memory_rw_debug =3D avr_cpu_memory_rw_debug; - cc->get_phys_page_debug =3D avr_cpu_get_phys_page_debug; dc->vmsd =3D &vms_avr_cpu; cc->sysemu_ops =3D &avr_sysemu_ops; cc->disas_set_info =3D avr_cpu_disas_set_info; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 394df655c9f..58193c02cbf 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -195,6 +195,7 @@ static void cris_cpu_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps cris_sysemu_ops =3D { + .get_phys_page_debug =3D cris_cpu_get_phys_page_debug, }; #endif =20 @@ -297,7 +298,6 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D cris_cpu_gdb_read_register; cc->gdb_write_register =3D cris_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D cris_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_cris_cpu; cc->sysemu_ops =3D &cris_sysemu_ops; #endif diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 6605c42e509..0d755b8a880 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -133,6 +133,7 @@ static ObjectClass *hppa_cpu_class_by_name(const char *= cpu_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps hppa_sysemu_ops =3D { + .get_phys_page_debug =3D hppa_cpu_get_phys_page_debug, }; #endif =20 @@ -166,7 +167,6 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D hppa_cpu_gdb_read_register; cc->gdb_write_register =3D hppa_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D hppa_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_hppa_cpu; cc->sysemu_ops =3D &hppa_sysemu_ops; #endif diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d050245b502..1092305cb43 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6716,6 +6716,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, .write_elf32_note =3D x86_cpu_write_elf32_note, @@ -6754,7 +6755,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) =20 #ifndef CONFIG_USER_ONLY cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; - cc->get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 600812d682b..f743a86c7d5 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -505,6 +505,7 @@ static const VMStateDescription vmstate_m68k_cpu =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps m68k_sysemu_ops =3D { + .get_phys_page_debug =3D m68k_cpu_get_phys_page_debug, }; #endif =20 @@ -538,7 +539,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D m68k_cpu_gdb_read_register; cc->gdb_write_register =3D m68k_cpu_gdb_write_register; #if defined(CONFIG_SOFTMMU) - cc->get_phys_page_debug =3D m68k_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_m68k_cpu; cc->sysemu_ops =3D &m68k_sysemu_ops; #endif diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index c6a10b1a52b..8ccac373631 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -354,6 +354,7 @@ static ObjectClass *mb_cpu_class_by_name(const char *cp= u_model) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps mb_sysemu_ops =3D { + .get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug, }; #endif =20 @@ -391,7 +392,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->gdb_write_register =3D mb_cpu_gdb_write_register; =20 #ifndef CONFIG_USER_ONLY - cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; dc->vmsd =3D &vmstate_mb_cpu; cc->sysemu_ops =3D &mb_sysemu_ops; #endif diff --git a/target/mips/cpu.c b/target/mips/cpu.c index a74b7fab318..c65fb4607f6 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -523,6 +523,7 @@ static Property mips_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps mips_sysemu_ops =3D { + .get_phys_page_debug =3D mips_cpu_get_phys_page_debug, .legacy_vmsd =3D &vmstate_mips_cpu, }; #endif @@ -566,7 +567,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) cc->gdb_read_register =3D mips_cpu_gdb_read_register; cc->gdb_write_register =3D mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D mips_cpu_get_phys_page_debug; cc->sysemu_ops =3D &mips_sysemu_ops; #endif cc->disas_set_info =3D mips_cpu_disas_set_info; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 296ccc0ed3c..f3b51732c29 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -209,6 +209,7 @@ static Property nios2_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps nios2_sysemu_ops =3D { + .get_phys_page_debug =3D nios2_cpu_get_phys_page_debug, }; #endif =20 @@ -242,7 +243,6 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) cc->set_pc =3D nios2_cpu_set_pc; cc->disas_set_info =3D nios2_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D nios2_cpu_get_phys_page_debug; cc->sysemu_ops =3D &nios2_sysemu_ops; #endif cc->gdb_read_register =3D nios2_cpu_gdb_read_register; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index cd8e3ae6754..babe637cda6 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -176,6 +176,7 @@ static void openrisc_any_initfn(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps openrisc_sysemu_ops =3D { + .get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug, }; #endif =20 @@ -208,7 +209,6 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) cc->gdb_read_register =3D openrisc_cpu_gdb_read_register; cc->gdb_write_register =3D openrisc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D openrisc_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_openrisc_cpu; cc->sysemu_ops =3D &openrisc_sysemu_ops; #endif diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d86e44ca07d..29b829e9484 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -598,6 +598,7 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *= cs, const char *xmlname) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps riscv_sysemu_ops =3D { + .get_phys_page_debug =3D riscv_cpu_get_phys_page_debug, .write_elf64_note =3D riscv_cpu_write_elf64_note, .write_elf32_note =3D riscv_cpu_write_elf32_note, .legacy_vmsd =3D &vmstate_riscv_cpu, @@ -645,7 +646,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D riscv_cpu_get_phys_page_debug; cc->sysemu_ops =3D &riscv_sysemu_ops; #endif cc->gdb_arch_name =3D riscv_gdb_arch_name; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index bbee1cb913f..e76b7708b89 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -175,6 +175,7 @@ static void rx_cpu_init(Object *obj) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps rx_sysemu_ops =3D { + .get_phys_page_debug =3D rx_cpu_get_phys_page_debug, }; #endif =20 @@ -212,7 +213,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void = *data) #endif cc->gdb_read_register =3D rx_cpu_gdb_read_register; cc->gdb_write_register =3D rx_cpu_gdb_write_register; - cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; cc->disas_set_info =3D rx_cpu_disas_set_info; =20 cc->gdb_num_core_regs =3D 26; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 058ffcef15f..e32265a61eb 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -478,6 +478,7 @@ static void s390_cpu_reset_full(DeviceState *dev) =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps s390_sysemu_ops =3D { + .get_phys_page_debug =3D s390_cpu_get_phys_page_debug, .get_crash_info =3D s390_cpu_get_crash_info, .write_elf64_note =3D s390_cpu_write_elf64_note, .legacy_vmsd =3D &vmstate_s390_cpu, @@ -523,7 +524,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *= data) cc->gdb_read_register =3D s390_cpu_gdb_read_register; cc->gdb_write_register =3D s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D s390_cpu_get_phys_page_debug; cc->sysemu_ops =3D &s390_sysemu_ops; #endif cc->disas_set_info =3D s390_cpu_disas_set_info; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 85e15ec9954..09de295cf91 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -225,6 +225,7 @@ static const VMStateDescription vmstate_sh_cpu =3D { }; =20 static const struct SysemuCPUOps sh4_sysemu_ops =3D { + .get_phys_page_debug =3D superh_cpu_get_phys_page_debug, }; #endif =20 @@ -261,7 +262,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_read_register =3D superh_cpu_gdb_read_register; cc->gdb_write_register =3D superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D superh_cpu_get_phys_page_debug; cc->sysemu_ops =3D &sh4_sysemu_ops; dc->vmsd =3D &vmstate_sh_cpu; #endif diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 543853c24dc..90658ba8e61 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -850,6 +850,7 @@ static Property sparc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps sparc_sysemu_ops =3D { + .get_phys_page_debug =3D sparc_cpu_get_phys_page_debug, .legacy_vmsd =3D &vmstate_sparc_cpu, }; #endif @@ -894,7 +895,6 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) cc->gdb_read_register =3D sparc_cpu_gdb_read_register; cc->gdb_write_register =3D sparc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D sparc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &sparc_sysemu_ops; #endif cc->disas_set_info =3D cpu_sparc_disas_set_info; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 8865fa18fce..4572dde1486 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -143,6 +143,7 @@ static void tc27x_initfn(Object *obj) } =20 static const struct SysemuCPUOps tricore_sysemu_ops =3D { + .get_phys_page_debug =3D tricore_cpu_get_phys_page_debug, }; =20 #include "hw/core/tcg-cpu-ops.h" @@ -173,7 +174,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) =20 cc->dump_state =3D tricore_cpu_dump_state; cc->set_pc =3D tricore_cpu_set_pc; - cc->get_phys_page_debug =3D tricore_cpu_get_phys_page_debug; cc->sysemu_ops =3D &tricore_sysemu_ops; cc->tcg_ops =3D &tricore_tcg_ops; } diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index d0bf06696e4..eb61ee55be4 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -183,6 +183,7 @@ static const VMStateDescription vmstate_xtensa_cpu =3D { }; =20 static const struct SysemuCPUOps xtensa_sysemu_ops =3D { + .get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug, }; #endif =20 @@ -221,7 +222,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) cc->gdb_stop_before_watchpoint =3D true; #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &xtensa_sysemu_ops; - cc->get_phys_page_debug =3D xtensa_cpu_get_phys_page_debug; dc->vmsd =3D &vmstate_xtensa_cpu; #endif cc->disas_set_info =3D xtensa_cpu_disas_set_info; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index 86b11e1356a..fd252ba72c9 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10239,6 +10239,7 @@ static Property ppc_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps ppc_sysemu_ops =3D { + .get_phys_page_debug =3D ppc_cpu_get_phys_page_debug, .write_elf32_note =3D ppc32_cpu_write_elf32_note, .write_elf64_note =3D ppc64_cpu_write_elf64_note, .virtio_is_big_endian =3D ppc_cpu_is_big_endian, @@ -10287,7 +10288,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) cc->gdb_read_register =3D ppc_cpu_gdb_read_register; cc->gdb_write_register =3D ppc_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->get_phys_page_debug =3D ppc_cpu_get_phys_page_debug; cc->sysemu_ops =3D &ppc_sysemu_ops; #endif =20 --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1621248806; cv=none; d=zohomail.com; s=zohoarc; b=NJTxpJm4KHsKsMNXrYn8aI/ezMg+7+U/Oqn2f53EhKGa4XbtzUA1EcIrfhbTll5GT4stGOyuR8cawuUPlZ7RE1lRAv6dbenSl5LiRuCUeOxo6rBAjItu3Tlv964B8qkVlHQcrt2x1Wyq1lpcgBne+B2RgazngCGFxco2dhwn4YY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[83.51.215.31]) by smtp.gmail.com with ESMTPSA id y2sm23430073wmq.45.2021.05.17.03.53.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:53:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Dw1xNt8fMjOUvBAaIK7tDLqLF14cF0ULOaAdWbFvGnU=; b=cc184CW8NKPOOBD44+OcxjcqSvTc7XrVxKwSGpTMOMonDv+ieiKKK7e/gCIPd/r01d sL8XF5B4ooV1N3l3SVYQhDEEvyCLOmgZC+dOwISAcABxLU5nTrlq3+bkcevbWnxVAwOZ 4/AuuWyzFh12j36T16inLj5CMrFFt5kOnKWCRtmcJsKKpaDdwWPKBabgcQMXSKRpyCsT 60lleuL6juUjJ4LlVkoV+lzo+XbOIiz4kEIfFZWXz9rRV89xzi8Qvkeei+8jSAHrSuEy WD1FuLM5HwW1Sx38x/qY3Bo5+QWvhmtWhJqADrqGK3DgtOK72JuLz0A14fJrh72A/iBK IA0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Dw1xNt8fMjOUvBAaIK7tDLqLF14cF0ULOaAdWbFvGnU=; b=NONV8QMfssQaQK3BDwAtS0qxMy5xlP+9RiFTpwDMh+Bs0UQCQqV8x84sNbLcVg+bdF tSLjljYnI6rTJF8gUyDiCxK5T7+xazfvW5O/1gFelPRf7kjbxwMCiLoWtGuuxjlZbDqw qmC2NuvpjvkCXmZjYGJSmYOckU61z9xpmOe63yR8rdCS6C+sQAdox6PxZhyhYQebnLMX r/mfexY2p15VY9NafZR7K+a8zHI1CKHxlFl9cN8AYkdM8Al11oa25pA+j30HKtxKJKGV aQJCji13uzOPFVzFnwLwvayENE/MBeEqQh/9WIDyk2RwstH/xBKr/bzu6/rtEZt61Lqy nPZw== X-Gm-Message-State: AOAM531f9dBFh3c19bvxnq7IAzBUhv/LAO5NKAEayh9WV6zhlBgX6JlZ iSWfmXKa45UW4Q+2Hb1rZgc= X-Google-Smtp-Source: ABdhPJwN1jjEpu8gMO1ImnigmcPr23L9QqbdDOMQNG8pnyw2YkNG0Xo80s4KtLH8Sov2Z/6bA9+CRw== X-Received: by 2002:a05:6000:43:: with SMTP id k3mr29956305wrx.222.1621248804766; Mon, 17 May 2021 03:53:24 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 21/23] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps Date: Mon, 17 May 2021 12:51:38 +0200 Message-Id: <20210517105140.1062037-22-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 3 --- include/hw/core/sysemu-cpu-ops.h | 5 +++++ hw/core/cpu-sysemu.c | 4 ++-- target/i386/cpu.c | 2 +- 4 files changed, 8 insertions(+), 6 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index b4d3a21bbf0..c95fc76064d 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -94,7 +94,6 @@ struct AccelCPUClass; * @dump_statistics: Callback for dumping statistics. * @get_arch_id: Callback for getting architecture-dependent CPU ID. * @get_paging_enabled: Callback for inquiring whether paging is enabled. - * @get_memory_mapping: Callback for obtaining the memory mappings. * @set_pc: Callback for setting the Program Counter register. This * should have the semantics used by the target architecture when * setting the PC from a source such as an ELF file entry point; @@ -138,8 +137,6 @@ struct CPUClass { void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); bool (*get_paging_enabled)(const CPUState *cpu); - void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, - Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 7f8ff641854..959523315ba 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -16,6 +16,11 @@ * struct SysemuCPUOps: System operations specific to a CPU class */ typedef struct SysemuCPUOps { + /** + * @get_memory_mapping: Callback for obtaining the memory mappings. + */ + void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, + Error **errp); /** * @get_phys_page_debug: Callback for obtaining a physical address. */ diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index b31c33ad2b5..3850fcb27f0 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -39,8 +39,8 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingL= ist *list, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_memory_mapping) { - cc->get_memory_mapping(cpu, list, errp); + if (cc->sysemu_ops->get_memory_mapping) { + cc->sysemu_ops->get_memory_mapping(cpu, list, errp); return; } =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1092305cb43..26640d9cacf 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6716,6 +6716,7 @@ static Property x86_cpu_properties[] =3D { =20 #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { + .get_memory_mapping =3D x86_cpu_get_memory_mapping, .get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, @@ -6754,7 +6755,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY - cc->get_memory_mapping =3D x86_cpu_get_memory_mapping; cc->sysemu_ops =3D &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ =20 --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f51.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1621248811; cv=none; d=zohomail.com; s=zohoarc; b=QsDN/jPTR4ywrkkQVDECxWG7dKWAt5e18JB9e2rArxYS+WDF2XGl9CuoyeReqHuHOGs0abf8okyb29DtxfuddqqWJdVArY4fWyVtcnXv8qDaLyYO+b0AaIC0t9xrnPBoqwxXhV6+hUWAIhOQs4Vqgl5nb0+yFBRh6tyQlEHTyXw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621248811; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=R6/9QXNVBtIBcMma+2nqCStG6/fu3uxJQHcr+W0fUdE=; b=FE2fSpIkWPHIqdgePAGJktOE6t0HM5vR9NAc2Yu46ufVRqkeLLvWpy9T+T1UOzQK8u8v/NYk7TySmpX0niQmdSwLtB9T0tVTQZtx/BU1rcPfTFrHLq1HI7hK3f6KoHl0nbQTPEuB5nFIhMqaWctCuMnr31i+tP1SEvdnIwGhOIQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) by mx.zohomail.com with SMTPS id 1621248811548873.5221578557632; Mon, 17 May 2021 03:53:31 -0700 (PDT) Received: by mail-wr1-f51.google.com with SMTP id a4so5907143wrr.2 for ; Mon, 17 May 2021 03:53:30 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (31.red-83-51-215.dynamicip.rima-tde.net. [83.51.215.31]) by smtp.gmail.com with ESMTPSA id q20sm23081179wmq.2.2021.05.17.03.53.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:53:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R6/9QXNVBtIBcMma+2nqCStG6/fu3uxJQHcr+W0fUdE=; b=ZsQiE3adxKjkMl8HQS0AjOQd3J/uyyKqnWzW/XIlOiT1yRvgfrJTtspozLz+cyCQSq Hu9Hppfy7YL7zMN/ZjRsR9snKAP29YZfeK2TXo6F9MDGfNDGpTZJq8/DjnusD3/ZZ1Qn iOtFgsFC4Jz96M1KXd/I5fVJTztvYVN+c3QcUDb6icqyvPSLXLNYZienKlDTlRGiKLhw EXmIc5aJVyt5eSgzhrao8DTyhqVpOc4ZTxUbYthbegZpgO65zMfG0MjCvRyz0s0Fyeqy zxjl9cKX3+v9gM/FGdMF67RuC3LWQUYNyYacoFHZBhb6YrhyMtUVM/ud1BwVgLUXweGL E9MA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=R6/9QXNVBtIBcMma+2nqCStG6/fu3uxJQHcr+W0fUdE=; b=irKy0XNN9f7xVP/xJWtGSo+2yyI7ZjsfdwUxv5EWKrf+EhNbDLLfyAAoGMDIffLSIh UaIRejf37v9zjb6lM1LuYw0UOXrfjPWhsG3O6Cv0dPaz06817cHBB/tROuj9P3pvtfMU UEDW3XG5NSUE58VCc/K+mFHTXG9RrvhgKs4/qf/hQle8MwMOyFb5cT9TkiCvBtsdn1MC sxh44hsdrjDScvIJyhxQTyN++0TSqG6DCCS7puh5Joe3jD2Lh842r/WI9sdFfv8t9VXe CnGnlMOtNqOLlzzGB1V+LC3GjpCu5QLcR6mYP6HF9KMECRCuG+HOnWsFyC7+lBZ3DRZ1 0foA== X-Gm-Message-State: AOAM533IjsStMMjIKmEPHGEcBN/tvgTOvPMxwnZd/BP2/twVuGzoj+RK m0E6h8iEVOC+vI2vWVRwkhQ= X-Google-Smtp-Source: ABdhPJwGjqFRy0Hel78NABTweEgXOFV/zZ5Z+Mw8L6eGW+9PKUr1f/mlk0NafvqVK3dPTsEvts0lyw== X-Received: by 2002:adf:ee44:: with SMTP id w4mr28902496wro.415.1621248809517; Mon, 17 May 2021 03:53:29 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 22/23] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps Date: Mon, 17 May 2021 12:51:39 +0200 Message-Id: <20210517105140.1062037-23-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 2 -- include/hw/core/sysemu-cpu-ops.h | 4 ++++ hw/core/cpu-sysemu.c | 4 ++-- target/i386/cpu.c | 4 +++- 4 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c95fc76064d..45fb543c291 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -93,7 +93,6 @@ struct AccelCPUClass; * @dump_state: Callback for dumping state. * @dump_statistics: Callback for dumping statistics. * @get_arch_id: Callback for getting architecture-dependent CPU ID. - * @get_paging_enabled: Callback for inquiring whether paging is enabled. * @set_pc: Callback for setting the Program Counter register. This * should have the semantics used by the target architecture when * setting the PC from a source such as an ELF file entry point; @@ -136,7 +135,6 @@ struct CPUClass { void (*dump_state)(CPUState *cpu, FILE *, int flags); void (*dump_statistics)(CPUState *cpu, int flags); int64_t (*get_arch_id)(CPUState *cpu); - bool (*get_paging_enabled)(const CPUState *cpu); void (*set_pc)(CPUState *cpu, vaddr value); int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-= ops.h index 959523315ba..554af5bebe9 100644 --- a/include/hw/core/sysemu-cpu-ops.h +++ b/include/hw/core/sysemu-cpu-ops.h @@ -21,6 +21,10 @@ typedef struct SysemuCPUOps { */ void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); + /** + * @get_paging_enabled: Callback for inquiring whether paging is enabl= ed. + */ + bool (*get_paging_enabled)(const CPUState *cpu); /** * @get_phys_page_debug: Callback for obtaining a physical address. */ diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c index 3850fcb27f0..00253f89293 100644 --- a/hw/core/cpu-sysemu.c +++ b/hw/core/cpu-sysemu.c @@ -27,8 +27,8 @@ bool cpu_paging_enabled(const CPUState *cpu) { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->get_paging_enabled) { - return cc->get_paging_enabled(cpu); + if (cc->sysemu_ops->get_paging_enabled) { + return cc->sysemu_ops->get_paging_enabled(cpu); } =20 return false; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 26640d9cacf..839b9d9f8b2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6485,12 +6485,14 @@ static int64_t x86_cpu_get_arch_id(CPUState *cs) return cpu->apic_id; } =20 +#if !defined(CONFIG_USER_ONLY) static bool x86_cpu_get_paging_enabled(const CPUState *cs) { X86CPU *cpu =3D X86_CPU(cs); =20 return cpu->env.cr[0] & CR0_PG_MASK; } +#endif /* !CONFIG_USER_ONLY */ =20 static void x86_cpu_set_pc(CPUState *cs, vaddr value) { @@ -6717,6 +6719,7 @@ static Property x86_cpu_properties[] =3D { #ifndef CONFIG_USER_ONLY static const struct SysemuCPUOps i386_sysemu_ops =3D { .get_memory_mapping =3D x86_cpu_get_memory_mapping, + .get_paging_enabled =3D x86_cpu_get_paging_enabled, .get_phys_page_attrs_debug =3D x86_cpu_get_phys_page_attrs_debug, .asidx_from_attrs =3D x86_asidx_from_attrs, .get_crash_info =3D x86_cpu_get_crash_info, @@ -6752,7 +6755,6 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) cc->gdb_read_register =3D x86_cpu_gdb_read_register; cc->gdb_write_register =3D x86_cpu_gdb_write_register; cc->get_arch_id =3D x86_cpu_get_arch_id; - cc->get_paging_enabled =3D x86_cpu_get_paging_enabled; =20 #ifndef CONFIG_USER_ONLY cc->sysemu_ops =3D &i386_sysemu_ops; --=20 2.26.3 From nobody Fri May 17 07:47:10 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) client-ip=209.85.221.41; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f41.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1621248816; cv=none; d=zohomail.com; s=zohoarc; b=NRB3mqbYIuiwUlQgwKovvw61rLaZyIsQ6B0AWMP2bpbFj+OKoF51v7G19OCu/IXe6E7dI861g5I6D3B0jsclPhcPaDUTE/mPueuQWpMRkYo0/vn4vWO0+aj4x8G5fMcXg2ZluWOJmEjfoT1WbXlX5xB2HWwaPBjICgJ0uqIe3m4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621248816; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Mhuox7xIp0GIglyCZDYTd85KgP4TwSkffnhZhs7gf3c=; b=eLWbvv0764MSYzQ0XjbJJeTX54MiN6bfCXl57sDPzjScniQC830WODgoZWKEC8WFTFfZ6RX6/vk/BkREP8j1JEUvBFFb689hBiDJBE/RGN8XJOywboAwclfC+y4E4im+rICx0zDtC9M5uD6IeHc/gT1aqwpg42pEx6svoEoEzeI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.41 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) by mx.zohomail.com with SMTPS id 1621248816102817.1716023216745; Mon, 17 May 2021 03:53:36 -0700 (PDT) Received: by mail-wr1-f41.google.com with SMTP id c14so4084525wrx.3 for ; Mon, 17 May 2021 03:53:35 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (31.red-83-51-215.dynamicip.rima-tde.net. [83.51.215.31]) by smtp.gmail.com with ESMTPSA id t13sm354487wmi.2.2021.05.17.03.53.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:53:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Mhuox7xIp0GIglyCZDYTd85KgP4TwSkffnhZhs7gf3c=; b=R9NO8LQe30o58Mt3m6NdVuyTPZGbNV4LActhLkKq6JU5IfCDUqDiDcAXuGT902+/1F a19tnCxEi7h7L4KerntHqoxiJtqjbUJdWd3RkysZRr5GaQv65JznWUPOHgVJA1iQGMos 70JlCIeWcJaxF7l52h/VT41U0qwViNYenhPtom3FA8hmqviwEhbuQ4cCm9z8JZHAusT6 GvhvQie85q6n54Spdz2TXlpuTycb5Jzyr+BrbbMOzpdCWDo7zmMgg4aiPavxsrb6GfFk EbJpslzvPtRkrP12XZSh1Ak5KFcZHBHs+n18RDRWbqVBJOxRjQ28dsJlSRzqyFsj6Zcx i4NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Mhuox7xIp0GIglyCZDYTd85KgP4TwSkffnhZhs7gf3c=; b=K+A/2405tVYkPuNTe0NddnNRoDVVjwMyHMq9n+t+th1LdnSY3RQOsba4B/VDtRJ++p O6xjgCh2XMCaM8bW6bWxo1cqJ8wkMkSVACbUyHruJswlpg0Kkw050szZx8W9obp3+lW1 OadIjCG5liM8aK5VosSJz1pBDNNf2RKag0Ps3YYxLTjg6IgjnDAOrMm3TELFOEJfjQBs qH7E+S3fhIudHooNAQPFGq72m+dE2FQro1IFqdvDYLsgglhiFamJofXN6zUgjscKRrJS GoBo5x5BYzRhe/kgzhkGi3av8r0IixvVddYtJBu4Tx5VyR5J5Q9Y/N1MC7SLezMhe89/ L1PQ== X-Gm-Message-State: AOAM530o+5WSdGQHfysNDD+NDbk8rzi3XOE0oJnl/08p21vpLk5rOUVu FivTML7LhQ1vbtuyqZzSwnU= X-Google-Smtp-Source: ABdhPJwyYLueB5+kdo+0wMM8EZ3E4acvl+/XSTDzZs2uX6CHe5UpjCppbFCCs6rzZYjJQItV/P8LJg== X-Received: by 2002:a5d:5301:: with SMTP id e1mr31274420wrv.36.1621248814331; Mon, 17 May 2021 03:53:34 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-arm@nongnu.org, Laurent Vivier , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Claudio Fontana , Taylor Simpson Subject: [PATCH v7 23/23] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c Date: Mon, 17 May 2021 12:51:40 +0200 Message-Id: <20210517105140.1062037-24-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210517105140.1062037-1-f4bug@amsat.org> References: <20210517105140.1062037-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Somehow similar to commit 78271684719 ("cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass"): We cannot in principle make the SysEmu Operations field definitions conditional on CONFIG_SOFTMMU in code that is included by both common_ss and specific_ss modules. Therefore, what we can do safely to restrict the SysEmu fields to system emulation builds, is to move all sysemu operations into a separate header file, which is only included by system-specific code. This leaves just a NULL pointer in the cpu.h for the user-mode builds. Inspired-by: Claudio Fontana Reviewed-by: Taylor Simpson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/core/cpu.h | 3 ++- target/alpha/cpu.h | 3 +++ target/arm/cpu.h | 3 +++ target/avr/cpu.h | 1 + target/cris/cpu.h | 3 +++ target/hexagon/cpu.h | 3 +++ target/hppa/cpu.h | 3 +++ target/i386/cpu.h | 3 +++ target/m68k/cpu.h | 3 +++ target/microblaze/cpu.h | 1 + target/mips/cpu.h | 3 +++ target/nios2/cpu.h | 1 + target/openrisc/cpu.h | 3 +++ target/ppc/cpu.h | 3 +++ target/riscv/cpu.h | 3 +++ target/rx/cpu.h | 3 +++ target/s390x/cpu.h | 3 +++ target/sh4/cpu.h | 3 +++ target/sparc/cpu.h | 3 +++ target/tricore/cpu.h | 3 +++ target/xtensa/cpu.h | 3 +++ cpu.c | 1 + 22 files changed, 57 insertions(+), 1 deletion(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 45fb543c291..e4328de8d41 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -80,7 +80,8 @@ struct TCGCPUOps; /* see accel-cpu.h */ struct AccelCPUClass; =20 -#include "hw/core/sysemu-cpu-ops.h" +/* see sysemu-cpu-ops.h */ +struct SysemuCPUOps; =20 /** * CPUClass: diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index cb3021c1afa..d5c13c7411f 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -22,6 +22,9 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1129b5ec0cc..8c63032d503 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -25,6 +25,9 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) diff --git a/target/avr/cpu.h b/target/avr/cpu.h index d148e8c75a4..e0419649fa7 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -23,6 +23,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "hw/core/sysemu-cpu-ops.h" =20 #ifdef CONFIG_USER_ONLY #error "AVR 8-bit does not support user mode" diff --git a/target/cris/cpu.h b/target/cris/cpu.h index aac921e221a..e258305675e 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -23,6 +23,9 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define EXCP_NMI 1 #define EXCP_GURU 2 diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 2855dd38816..7fb4bcb74f9 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -26,6 +26,9 @@ typedef struct CPUHexagonState CPUHexagonState; #include "qemu-common.h" #include "exec/cpu-defs.h" #include "hex_regs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define NUM_PREGS 4 #define TOTAL_PER_THREAD_REGS 64 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index d125aeac1d3..c5541a5aea9 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -22,6 +22,9 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* PA-RISC 1.x processors have a strong memory model. */ /* ??? While we do not yet implement PA-RISC 2.0, those processors have diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 27a7214debe..38fff85b60f 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -25,6 +25,9 @@ #include "kvm/hyperv-proto.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* The x86 has a strong memory model with some store-after-load re-orderin= g */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 7b17f59d40f..102988799bc 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -23,6 +23,9 @@ =20 #include "exec/cpu-defs.h" #include "cpu-qom.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define OS_BYTE 0 #define OS_WORD 1 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 444dc487456..20a89746104 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -26,6 +26,7 @@ =20 typedef struct CPUMBState CPUMBState; #if !defined(CONFIG_USER_ONLY) +#include "hw/core/sysemu-cpu-ops.h" #include "mmu.h" #endif =20 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 075c24abdad..923ab71f8d7 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -6,6 +6,9 @@ #include "fpu/softfloat-types.h" #include "hw/clock.h" #include "mips-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define TCG_GUEST_DEFAULT_MO (0) =20 diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 75b0c9924bb..16461a17e88 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -27,6 +27,7 @@ =20 typedef struct CPUNios2State CPUNios2State; #if !defined(CONFIG_USER_ONLY) +#include "hw/core/sysemu-cpu-ops.h" #include "mmu.h" #endif =20 diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 33ab91719c2..062a6369d62 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -23,6 +23,9 @@ #include "exec/cpu-defs.h" #include "hw/core/cpu.h" #include "qom/object.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */ struct OpenRISCCPU; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 69978fe0d9b..fa61ef0f8f1 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -24,6 +24,9 @@ #include "exec/cpu-defs.h" #include "cpu-qom.h" #include "qom/object.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define TCG_GUEST_DEFAULT_MO 0 =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6713bf6fb44..78754ce7ae4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -25,6 +25,9 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" #include "qom/object.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define TCG_GUEST_DEFAULT_MO 0 =20 diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 2b7595ff372..0fe4bf586cb 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -25,6 +25,9 @@ #include "cpu-qom.h" =20 #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* PSW define */ REG32(PSW, 0) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 2464d4076c0..8f7233d97c2 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -28,6 +28,9 @@ #include "cpu-qom.h" #include "cpu_models.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #define ELF_MACHINE_UNAME "S390X" =20 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 64870023e31..c93b0461e5f 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -22,6 +22,9 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* CPU Subtypes */ #define SH_CPU_SH7750 (1 << 0) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 79e28eb2182..de048fdf287 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -4,6 +4,9 @@ #include "qemu/bswap.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 #if !defined(TARGET_SPARC64) #define TARGET_DPREGS 16 diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 0892ae647dc..9f4b55731f9 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -23,6 +23,9 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "tricore-defs.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 struct tricore_boot_info; =20 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index d40d8b7d863..cef48f3a7e6 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -31,6 +31,9 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "xtensa-isa.h" +#ifndef CONFIG_USER_ONLY +#include "hw/core/sysemu-cpu-ops.h" +#endif =20 /* Xtensa processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) diff --git a/cpu.c b/cpu.c index 76047fcd4d6..164fefeaa35 100644 --- a/cpu.c +++ b/cpu.c @@ -29,6 +29,7 @@ #ifdef CONFIG_USER_ONLY #include "qemu.h" #else +#include "hw/core/sysemu-cpu-ops.h" #include "exec/address-spaces.h" #endif #include "sysemu/tcg.h" --=20 2.26.3