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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.18; envelope-from=its@irrelevant.dk; helo=wnew4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Gollu Appalanaidu , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Gollu Appalanaidu Currently pci_nvme_err_invalid_lba_range trace is called individually at each nvme_check_bounds() call site. Move the trace event to nvme_check_bounds() and remove the redundant events. Signed-off-by: Gollu Appalanaidu Reviewed-by: Philippe Mathieu-Daud=C3=A9 [k.jensen: commit message fixup] Signed-off-by: Klaus Jensen --- hw/block/nvme.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 5fe082ec34c5..cd594280a7f9 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1426,6 +1426,7 @@ static inline uint16_t nvme_check_bounds(NvmeNamespac= e *ns, uint64_t slba, uint64_t nsze =3D le64_to_cpu(ns->id_ns.nsze); =20 if (unlikely(UINT64_MAX - slba < nlb || slba + nlb > nsze)) { + trace_pci_nvme_err_invalid_lba_range(slba, nlb, nsze); return NVME_LBA_RANGE | NVME_DNR; } =20 @@ -2268,7 +2269,6 @@ static void nvme_copy_in_complete(NvmeRequest *req) =20 status =3D nvme_check_bounds(ns, sdlba, ctx->nlb); if (status) { - trace_pci_nvme_err_invalid_lba_range(sdlba, ctx->nlb, ns->id_ns.ns= ze); goto invalid; } =20 @@ -2530,8 +2530,6 @@ static uint16_t nvme_dsm(NvmeCtrl *n, NvmeRequest *re= q) uint32_t nlb =3D le32_to_cpu(range[i].nlb); =20 if (nvme_check_bounds(ns, slba, nlb)) { - trace_pci_nvme_err_invalid_lba_range(slba, nlb, - ns->id_ns.nsze); continue; } =20 @@ -2604,7 +2602,6 @@ static uint16_t nvme_verify(NvmeCtrl *n, NvmeRequest = *req) =20 status =3D nvme_check_bounds(ns, slba, nlb); if (status) { - trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze); return status; } =20 @@ -2689,7 +2686,6 @@ static uint16_t nvme_copy(NvmeCtrl *n, NvmeRequest *r= eq) =20 status =3D nvme_check_bounds(ns, slba, _nlb); if (status) { - trace_pci_nvme_err_invalid_lba_range(slba, _nlb, ns->id_ns.nsz= e); goto out; } =20 @@ -2818,7 +2814,6 @@ static uint16_t nvme_compare(NvmeCtrl *n, NvmeRequest= *req) =20 status =3D nvme_check_bounds(ns, slba, nlb); if (status) { - trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze); return status; } =20 @@ -2938,7 +2933,6 @@ static uint16_t nvme_read(NvmeCtrl *n, NvmeRequest *r= eq) =20 status =3D nvme_check_bounds(ns, slba, nlb); if (status) { - trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze); goto invalid; } =20 @@ -3018,7 +3012,6 @@ static uint16_t nvme_do_write(NvmeCtrl *n, NvmeReques= t *req, bool append, =20 status =3D nvme_check_bounds(ns, slba, nlb); if (status) { - trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze); goto invalid; } =20 --=20 2.31.1 From nobody Sat May 18 09:48:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1621243726; cv=none; d=zohomail.com; s=zohoarc; b=oItHUk9OK7Ne4G69zzD1v9atgdLyDercyu54hczRIVWN7CNWfWiDwV/vvDR5VAYUwlFjHjg4SEjw5WLhaViSvwqAMuERW6FzxhpBP0rlMAomza2QrwD0NNT9A2Src5xh2tF+FbTekBJcQU19GWS1MU0zRm5LN5jJfdj2AOkmjc8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621243726; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.18; envelope-from=its@irrelevant.dk; helo=wnew4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Gollu Appalanaidu , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Gollu Appalanaidu Align the 'rsvd1' reserved field declaration in NvmeBar with existing style. Signed-off-by: Gollu Appalanaidu [k.jensen: minor commit message fixup] Signed-off-by: Klaus Jensen --- include/block/nvme.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/block/nvme.h b/include/block/nvme.h index 4ac926fbc687..e7fc119adb24 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -7,7 +7,7 @@ typedef struct QEMU_PACKED NvmeBar { uint32_t intms; uint32_t intmc; uint32_t cc; - uint32_t rsvd1; + uint8_t rsvd24[4]; uint32_t csts; uint32_t nssrc; uint32_t aqa; --=20 2.31.1 From nobody Sat May 18 09:48:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1621243377; cv=none; d=zohomail.com; s=zohoarc; b=oDR2Te71AnKqLW9EBhTE+Jm1Q5tfFCdBkBxmBTjmQiBRKrdLpebnh98dLozKjDnMu8iGuuyyURIzUD7uF+TI0KOcY4kokIgy4KBFAlDEFrLlp3dVEFiAg03JdiCyKNn+qdr+iQxrRasbsCDEU1NTrzAgMQstjc8eyl+E/AtXK7Y= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.18; envelope-from=its@irrelevant.dk; helo=wnew4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Gollu Appalanaidu , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Gollu Appalanaidu Currently in compare command metadata aio read blk_aio_preadv return value ignored. Consider it and complete the block accounting. Signed-off-by: Gollu Appalanaidu Fixes: 0a384f923f51 ("hw/block/nvme: add compare command") Signed-off-by: Klaus Jensen --- hw/block/nvme.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index cd594280a7f9..67abc9eb2c24 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -2369,10 +2369,19 @@ static void nvme_compare_mdata_cb(void *opaque, int= ret) uint32_t reftag =3D le32_to_cpu(rw->reftag); struct nvme_compare_ctx *ctx =3D req->opaque; g_autofree uint8_t *buf =3D NULL; + BlockBackend *blk =3D ns->blkconf.blk; + BlockAcctCookie *acct =3D &req->acct; + BlockAcctStats *stats =3D blk_get_stats(blk); uint16_t status =3D NVME_SUCCESS; =20 trace_pci_nvme_compare_mdata_cb(nvme_cid(req)); =20 + if (ret) { + block_acct_failed(stats, acct); + nvme_aio_err(req, ret); + goto out; + } + buf =3D g_malloc(ctx->mdata.iov.size); =20 status =3D nvme_bounce_mdata(n, buf, ctx->mdata.iov.size, @@ -2421,6 +2430,8 @@ static void nvme_compare_mdata_cb(void *opaque, int r= et) goto out; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.18; envelope-from=its@irrelevant.dk; helo=wnew4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Gollu Appalanaidu , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Gollu Appalanaidu Currently IO Command Set Profile feature is supported, but the feature support flag not set. Further, this feature is changable. Fix that. Additionally, remove filling default value of the CQE result with zero, since it will fall back to the default case anyway. Signed-off-by: Gollu Appalanaidu [k.jensen: fix up commit message] Signed-off-by: Klaus Jensen --- hw/block/nvme.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 67abc9eb2c24..14c24f9b0866 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -185,6 +185,7 @@ static const bool nvme_feature_support[NVME_FID_MAX] = =3D { [NVME_WRITE_ATOMICITY] =3D true, [NVME_ASYNCHRONOUS_EVENT_CONF] =3D true, [NVME_TIMESTAMP] =3D true, + [NVME_COMMAND_SET_PROFILE] =3D true, }; =20 static const uint32_t nvme_feature_cap[NVME_FID_MAX] =3D { @@ -194,6 +195,7 @@ static const uint32_t nvme_feature_cap[NVME_FID_MAX] = =3D { [NVME_NUMBER_OF_QUEUES] =3D NVME_FEAT_CAP_CHANGE, [NVME_ASYNCHRONOUS_EVENT_CONF] =3D NVME_FEAT_CAP_CHANGE, [NVME_TIMESTAMP] =3D NVME_FEAT_CAP_CHANGE, + [NVME_COMMAND_SET_PROFILE] =3D NVME_FEAT_CAP_CHANGE, }; =20 static const uint32_t nvme_cse_acs[256] =3D { @@ -4711,9 +4713,6 @@ defaults: result |=3D NVME_INTVC_NOCOALESCING; } break; - case NVME_COMMAND_SET_PROFILE: - result =3D 0; - break; default: result =3D nvme_feature_default[fid]; break; --=20 2.31.1 From nobody Sat May 18 09:48:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1621243750; cv=none; d=zohomail.com; s=zohoarc; b=HqdtFGRTuQIRlUzAifjx0cstKbyXv+4zbWy6kjpLGfG40ueLeDZqGukRCH3Dcg6g3/U/KJ6n/orh0af07ibBq4lq4hTQYftXHef1VI8USDeSwOqDktkvHLSuQsTbg/WDXh5WMAIAObOdvwiic4eSblzFqTitkI3wqpEkSdTTzUA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621243750; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6L1kb0gYXdvfO3EJGF4b/9i9bG4hRwLVbSYaA0XKb4Q=; b=VuIdt36JsWJ8FaVPwg8ZnHuYzwCziJ5bnSU6eV9OlszXy3z0fyuz9/tcnQ8LIQDlNYlc+RIJ79uoAk8gMERIHdmt4m6FbxeWo9PccVChGz6z+HOkFTzrPonmypNVoCs135OKLSZw0D5vD++G9Ccunr0f9cjyAkIxWDr/Ct276uI= ARC-Authentication-Results: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.18; envelope-from=its@irrelevant.dk; helo=wnew4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Gollu Appalanaidu , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Gollu Appalanaidu nvme_map_addr_pmr function arguments not aligned, fix that. Signed-off-by: Gollu Appalanaidu Signed-off-by: Klaus Jensen --- hw/block/nvme.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 14c24f9b0866..79a087a41ce8 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -576,7 +576,7 @@ static uint16_t nvme_map_addr_cmb(NvmeCtrl *n, QEMUIOVe= ctor *iov, hwaddr addr, } =20 static uint16_t nvme_map_addr_pmr(NvmeCtrl *n, QEMUIOVector *iov, hwaddr a= ddr, - size_t len) + size_t len) { if (!len) { return NVME_SUCCESS; --=20 2.31.1 From nobody Sat May 18 09:48:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1621243405; cv=none; d=zohomail.com; s=zohoarc; b=Wbhr611jJwq5u357Z8OOd1e0qeej/fB9ZsZScC2GXN5OY7gxt+krPyZHy3pOO4ZvqRypOrT8iMiZGNsVnbOkYJNObBgXM5rlJqmW202p8Xa4p3c7xByqB0Zv7D1LQMPxDO2hvnfj/v2LXQULjaGsRKcBKkHs4mlegsnAwDzd9+o= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.18; envelope-from=its@irrelevant.dk; helo=wnew4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Gollu Appalanaidu , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Gollu Appalanaidu While QEMU coding style prefers lowercase hexadecimals in constants, the NVMe subsystem uses the format from the NVMe specifications in comments, i.e. 'h' suffix instead of '0x' prefix. Fix this up across the code base. Signed-off-by: Gollu Appalanaidu [k.jensen: updated message; added conversion in a couple of missing comment= s] Signed-off-by: Klaus Jensen --- include/block/nvme.h | 10 +++---- hw/block/nvme-ns.c | 2 +- hw/block/nvme.c | 67 +++++++++++++++++++++++++------------------- 3 files changed, 44 insertions(+), 35 deletions(-) diff --git a/include/block/nvme.h b/include/block/nvme.h index e7fc119adb24..0ff9ce17a99e 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -848,8 +848,8 @@ enum NvmeStatusCodes { NVME_FW_REQ_SUSYSTEM_RESET =3D 0x0110, NVME_NS_ALREADY_ATTACHED =3D 0x0118, NVME_NS_PRIVATE =3D 0x0119, - NVME_NS_NOT_ATTACHED =3D 0x011A, - NVME_NS_CTRL_LIST_INVALID =3D 0x011C, + NVME_NS_NOT_ATTACHED =3D 0x011a, + NVME_NS_CTRL_LIST_INVALID =3D 0x011c, NVME_CONFLICTING_ATTRS =3D 0x0180, NVME_INVALID_PROT_INFO =3D 0x0181, NVME_WRITE_TO_RO =3D 0x0182, @@ -1409,9 +1409,9 @@ typedef enum NvmeZoneState { NVME_ZONE_STATE_IMPLICITLY_OPEN =3D 0x02, NVME_ZONE_STATE_EXPLICITLY_OPEN =3D 0x03, NVME_ZONE_STATE_CLOSED =3D 0x04, - NVME_ZONE_STATE_READ_ONLY =3D 0x0D, - NVME_ZONE_STATE_FULL =3D 0x0E, - NVME_ZONE_STATE_OFFLINE =3D 0x0F, + NVME_ZONE_STATE_READ_ONLY =3D 0x0d, + NVME_ZONE_STATE_FULL =3D 0x0e, + NVME_ZONE_STATE_OFFLINE =3D 0x0f, } NvmeZoneState; =20 static inline void _nvme_check_size(void) diff --git a/hw/block/nvme-ns.c b/hw/block/nvme-ns.c index 7bb618f18209..a0895614d9c3 100644 --- a/hw/block/nvme-ns.c +++ b/hw/block/nvme-ns.c @@ -303,7 +303,7 @@ static void nvme_ns_init_zoned(NvmeNamespace *ns) =20 id_ns_z =3D g_malloc0(sizeof(NvmeIdNsZoned)); =20 - /* MAR/MOR are zeroes-based, 0xffffffff means no limit */ + /* MAR/MOR are zeroes-based, FFFFFFFFFh means no limit */ id_ns_z->mar =3D cpu_to_le32(ns->params.max_active_zones - 1); id_ns_z->mor =3D cpu_to_le32(ns->params.max_open_zones - 1); id_ns_z->zoc =3D 0; diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 79a087a41ce8..baba949660f2 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -12,10 +12,19 @@ * Reference Specs: http://www.nvmexpress.org, 1.4, 1.3, 1.2, 1.1, 1.0e * * https://nvmexpress.org/developers/nvme-specification/ - */ - -/** - * Usage: add options: + * + * + * Notes on coding style + * --------------------- + * While QEMU coding style prefers lowercase hexadecimals in constants, the + * NVMe subsystem use thes format from the NVMe specifications in the comm= ents + * (i.e. 'h' suffix instead of '0x' prefix). + * + * Usage + * ----- + * See docs/system/nvme.rst for extensive documentation. + * + * Add options: * -drive file=3D,if=3Dnone,id=3D * -device nvme-subsys,id=3D,nqn=3D * -device nvme,serial=3D,id=3D, \ @@ -3613,18 +3622,18 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeReques= t *req) =20 /* * In the base NVM command set, Flush may apply to all namespaces - * (indicated by NSID being set to 0xFFFFFFFF). But if that feature is= used + * (indicated by NSID being set to FFFFFFFFh). But if that feature is = used * along with TP 4056 (Namespace Types), it may be pretty screwed up. * - * If NSID is indeed set to 0xFFFFFFFF, we simply cannot associate the + * If NSID is indeed set to FFFFFFFFh, we simply cannot associate the * opcode with a specific command since we cannot determine a unique I= /O - * command set. Opcode 0x0 could have any other meaning than something + * command set. Opcode 0h could have any other meaning than something * equivalent to flushing and say it DOES have completely different - * semantics in some other command set - does an NSID of 0xFFFFFFFF th= en + * semantics in some other command set - does an NSID of FFFFFFFFh then * mean "for all namespaces, apply whatever command set specific comma= nd - * that uses the 0x0 opcode?" Or does it mean "for all namespaces, app= ly - * whatever command that uses the 0x0 opcode if, and only if, it allows - * NSID to be 0xFFFFFFFF"? + * that uses the 0h opcode?" Or does it mean "for all namespaces, apply + * whatever command that uses the 0h opcode if, and only if, it allows= NSID + * to be FFFFFFFFh"? * * Anyway (and luckily), for now, we do not care about this since the * device only supports namespace types that includes the NVM Flush co= mmand @@ -3940,7 +3949,7 @@ static uint16_t nvme_changed_nslist(NvmeCtrl *n, uint= 8_t rae, uint32_t buf_len, NVME_CHANGED_NSID_SIZE) { /* * If more than 1024 namespaces, the first entry in the log page s= hould - * be set to 0xffffffff and the others to 0 as spec. + * be set to FFFFFFFFh and the others to 0 as spec. */ if (i =3D=3D ARRAY_SIZE(nslist)) { memset(nslist, 0x0, sizeof(nslist)); @@ -4338,7 +4347,7 @@ static uint16_t nvme_identify_nslist(NvmeCtrl *n, Nvm= eRequest *req, trace_pci_nvme_identify_nslist(min_nsid); =20 /* - * Both 0xffffffff (NVME_NSID_BROADCAST) and 0xfffffffe are invalid va= lues + * Both FFFFFFFFh (NVME_NSID_BROADCAST) and FFFFFFFFEh are invalid val= ues * since the Active Namespace ID List should return namespaces with ids * *higher* than the NSID specified in the command. This is also speci= fied * in the spec (NVM Express v1.3d, Section 5.15.4). @@ -4385,7 +4394,7 @@ static uint16_t nvme_identify_nslist_csi(NvmeCtrl *n,= NvmeRequest *req, trace_pci_nvme_identify_nslist_csi(min_nsid, c->csi); =20 /* - * Same as in nvme_identify_nslist(), 0xffffffff/0xfffffffe are invali= d. + * Same as in nvme_identify_nslist(), FFFFFFFFh/FFFFFFFFEh are invalid. */ if (min_nsid >=3D NVME_NSID_BROADCAST - 1) { return NVME_INVALID_NSID | NVME_DNR; @@ -4452,7 +4461,7 @@ static uint16_t nvme_identify_ns_descr_list(NvmeCtrl = *n, NvmeRequest *req) =20 /* * Because the NGUID and EUI64 fields are 0 in the Identify Namespace = data - * structure, a Namespace UUID (nidt =3D 0x3) must be reported in the + * structure, a Namespace UUID (nidt =3D 3h) must be reported in the * Namespace Identification Descriptor. Add the namespace UUID here. */ ns_descrs->uuid.hdr.nidt =3D NVME_NIDT_UUID; @@ -4601,7 +4610,7 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeReq= uest *req) /* * The Reservation Notification Mask and Reservation Persisten= ce * features require a status code of Invalid Field in Command = when - * NSID is 0xFFFFFFFF. Since the device does not support those + * NSID is FFFFFFFFh. Since the device does not support those * features we can always return Invalid Namespace or Format a= s we * should do for all other features. */ @@ -4850,15 +4859,15 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeR= equest *req) } =20 /* - * NVMe v1.3, Section 5.21.1.7: 0xffff is not an allowed value for= NCQR + * NVMe v1.3, Section 5.21.1.7: FFFFh is not an allowed value for = NCQR * and NSQR. */ if ((dw11 & 0xffff) =3D=3D 0xffff || ((dw11 >> 16) & 0xffff) =3D= =3D 0xffff) { return NVME_INVALID_FIELD | NVME_DNR; } =20 - trace_pci_nvme_setfeat_numq((dw11 & 0xFFFF) + 1, - ((dw11 >> 16) & 0xFFFF) + 1, + trace_pci_nvme_setfeat_numq((dw11 & 0xffff) + 1, + ((dw11 >> 16) & 0xffff) + 1, n->params.max_ioqpairs, n->params.max_ioqpairs); req->cqe.result =3D cpu_to_le32((n->params.max_ioqpairs - 1) | @@ -5496,7 +5505,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset= , uint64_t data, n->bar.cc =3D data; } break; - case 0x1C: /* CSTS */ + case 0x1c: /* CSTS */ if (data & (1 << 4)) { NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ssreset_w1c_unsupported, "attempted to W1C CSTS.NSSRO" @@ -5508,7 +5517,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset= , uint64_t data, } break; case 0x20: /* NSSR */ - if (data =3D=3D 0x4E564D65) { + if (data =3D=3D 0x4e564d65) { trace_pci_nvme_ub_mmiowr_ssreset_unsupported(); } else { /* The spec says that writes of other values have no effect */ @@ -5578,11 +5587,11 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offs= et, uint64_t data, n->bar.cmbmsc =3D (n->bar.cmbmsc & 0xffffffff) | (data << 32); return; =20 - case 0xE00: /* PMRCAP */ + case 0xe00: /* PMRCAP */ NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrcap_readonly, "invalid write to PMRCAP register, ignored"); return; - case 0xE04: /* PMRCTL */ + case 0xe04: /* PMRCTL */ n->bar.pmrctl =3D data; if (NVME_PMRCTL_EN(data)) { memory_region_set_enabled(&n->pmr.dev->mr, true); @@ -5593,19 +5602,19 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offs= et, uint64_t data, n->pmr.cmse =3D false; } return; - case 0xE08: /* PMRSTS */ + case 0xe08: /* PMRSTS */ NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrsts_readonly, "invalid write to PMRSTS register, ignored"); return; - case 0xE0C: /* PMREBS */ + case 0xe0C: /* PMREBS */ NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrebs_readonly, "invalid write to PMREBS register, ignored"); return; - case 0xE10: /* PMRSWTP */ + case 0xe10: /* PMRSWTP */ NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrswtp_readonly, "invalid write to PMRSWTP register, ignored"); return; - case 0xE14: /* PMRMSCL */ + case 0xe14: /* PMRMSCL */ if (!NVME_CAP_PMRS(n->bar.cap)) { return; } @@ -5625,7 +5634,7 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset= , uint64_t data, } =20 return; - case 0xE18: /* PMRMSCU */ + case 0xe18: /* PMRMSCU */ if (!NVME_CAP_PMRS(n->bar.cap)) { return; } @@ -5667,7 +5676,7 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr a= ddr, unsigned size) * from PMRSTS should ensure prior writes * made it to persistent media */ - if (addr =3D=3D 0xE08 && + if (addr =3D=3D 0xe08 && (NVME_PMRCAP_PMRWBM(n->bar.pmrcap) & 0x02)) { memory_region_msync(&n->pmr.dev->mr, 0, n->pmr.dev->size); } --=20 2.31.1 From nobody Sat May 18 09:48:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.18; envelope-from=its@irrelevant.dk; helo=wnew4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , Thomas Huth , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Get rid of the (reserved) double underscore use. Rename the "generic" zone open function to nvme_zrm_open_flags() and add a generic `int flags` argument instead which allows more flags to be easily added in the future. There is at least one TP under standardization that would add an additional flag. Cc: Philippe Mathieu-Daud=C3=A9 Cc: Thomas Huth Signed-off-by: Klaus Jensen Reviewed-by: Thomas Huth Reviewed-by: Keith Busch --- hw/block/nvme.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index baba949660f2..9e5ab4cacb06 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1694,8 +1694,12 @@ static void nvme_zrm_auto_transition_zone(NvmeNamesp= ace *ns) } } =20 -static uint16_t __nvme_zrm_open(NvmeNamespace *ns, NvmeZone *zone, - bool implicit) +enum { + NVME_ZRM_AUTO =3D 1 << 0, +}; + +static uint16_t nvme_zrm_open_flags(NvmeNamespace *ns, NvmeZone *zone, + int flags) { int act =3D 0; uint16_t status; @@ -1719,7 +1723,7 @@ static uint16_t __nvme_zrm_open(NvmeNamespace *ns, Nv= meZone *zone, =20 nvme_aor_inc_open(ns); =20 - if (implicit) { + if (flags & NVME_ZRM_AUTO) { nvme_assign_zone_state(ns, zone, NVME_ZONE_STATE_IMPLICITLY_OP= EN); return NVME_SUCCESS; } @@ -1727,7 +1731,7 @@ static uint16_t __nvme_zrm_open(NvmeNamespace *ns, Nv= meZone *zone, /* fallthrough */ =20 case NVME_ZONE_STATE_IMPLICITLY_OPEN: - if (implicit) { + if (flags & NVME_ZRM_AUTO) { return NVME_SUCCESS; } =20 @@ -1745,12 +1749,12 @@ static uint16_t __nvme_zrm_open(NvmeNamespace *ns, = NvmeZone *zone, =20 static inline uint16_t nvme_zrm_auto(NvmeNamespace *ns, NvmeZone *zone) { - return __nvme_zrm_open(ns, zone, true); + return nvme_zrm_open_flags(ns, zone, NVME_ZRM_AUTO); } =20 static inline uint16_t nvme_zrm_open(NvmeNamespace *ns, NvmeZone *zone) { - return __nvme_zrm_open(ns, zone, false); + return nvme_zrm_open_flags(ns, zone, 0); } =20 static void __nvme_advance_zone_wp(NvmeNamespace *ns, NvmeZone *zone, --=20 2.31.1 From nobody Sat May 18 09:48:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1621244232; cv=none; d=zohomail.com; s=zohoarc; b=JkwvrFZdw/pEDM7GhHO4RBUQa36QrfYPcnW4J2zuN1JpkvY+IMEh/Vl1MHJTKTJoxFmm4ug+gzPPQufVUvh/pmZs1dVSEG/gHTRwWky4JsoprV2PbDChxm31ccWAK3lPwgLaYZzrV/rfebMmhjs4+TfbIKgjjJBEfC+JjnjUkSU= ARC-Message-Signature: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.18; envelope-from=its@irrelevant.dk; helo=wnew4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , Thomas Huth , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Get rid of the (reserved) double underscore use. Cc: Philippe Mathieu-Daud=C3=A9 Cc: Thomas Huth Signed-off-by: Klaus Jensen Reviewed-by: Thomas Huth Reviewed-by: Keith Busch --- hw/block/nvme.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 9e5ab4cacb06..acbfa3f890dc 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1757,8 +1757,8 @@ static inline uint16_t nvme_zrm_open(NvmeNamespace *n= s, NvmeZone *zone) return nvme_zrm_open_flags(ns, zone, 0); } =20 -static void __nvme_advance_zone_wp(NvmeNamespace *ns, NvmeZone *zone, - uint32_t nlb) +static void nvme_advance_zone_wp(NvmeNamespace *ns, NvmeZone *zone, + uint32_t nlb) { zone->d.wp +=3D nlb; =20 @@ -1778,7 +1778,7 @@ static void nvme_finalize_zoned_write(NvmeNamespace *= ns, NvmeRequest *req) nlb =3D le16_to_cpu(rw->nlb) + 1; zone =3D nvme_get_zone_by_slba(ns, slba); =20 - __nvme_advance_zone_wp(ns, zone, nlb); + nvme_advance_zone_wp(ns, zone, nlb); } =20 static inline bool nvme_is_write(NvmeRequest *req) @@ -2167,7 +2167,7 @@ out: uint64_t sdlba =3D le64_to_cpu(copy->sdlba); NvmeZone *zone =3D nvme_get_zone_by_slba(ns, sdlba); =20 - __nvme_advance_zone_wp(ns, zone, ctx->nlb); + nvme_advance_zone_wp(ns, zone, ctx->nlb); } =20 g_free(ctx->bounce); --=20 2.31.1 From nobody Sat May 18 09:48:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1621243874; cv=none; d=zohomail.com; s=zohoarc; b=Tr5cQXFNjgdH8dpg2J/xudPfrkLNWDLTTevYDXJ6gFciCQwEwjGwR+sWmFF3L30BknbGJPC5AhoytZRsiyTgB+uE31kr9RwJaZORCKnsME3BNMKHTxkkVx+ChMZatHRZ6d9d8nDG7FPXxQNcQCWyeL264x/XEG2NhMVXKlvekjg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621243874; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.18; envelope-from=its@irrelevant.dk; helo=wnew4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , Thomas Huth , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen Get rid of the (reserved) double underscore use. Cc: Philippe Mathieu-Daud=C3=A9 Cc: Thomas Huth Signed-off-by: Klaus Jensen Reviewed-by: Thomas Huth Reviewed-by: Keith Busch --- hw/block/nvme.c | 47 +++++++++++++++++++++++------------------------ 1 file changed, 23 insertions(+), 24 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index acbfa3f890dc..f0cfca869875 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -4928,7 +4928,25 @@ static void nvme_update_dmrsl(NvmeCtrl *n) } } =20 -static void __nvme_select_ns_iocs(NvmeCtrl *n, NvmeNamespace *ns); +static void nvme_select_iocs_ns(NvmeCtrl *n, NvmeNamespace *ns) +{ + ns->iocs =3D nvme_cse_iocs_none; + switch (ns->csi) { + case NVME_CSI_NVM: + if (NVME_CC_CSS(n->bar.cc) !=3D NVME_CC_CSS_ADMIN_ONLY) { + ns->iocs =3D nvme_cse_iocs_nvm; + } + break; + case NVME_CSI_ZONED: + if (NVME_CC_CSS(n->bar.cc) =3D=3D NVME_CC_CSS_CSI) { + ns->iocs =3D nvme_cse_iocs_zoned; + } else if (NVME_CC_CSS(n->bar.cc) =3D=3D NVME_CC_CSS_NVM) { + ns->iocs =3D nvme_cse_iocs_nvm; + } + break; + } +} + static uint16_t nvme_ns_attachment(NvmeCtrl *n, NvmeRequest *req) { NvmeNamespace *ns; @@ -4979,7 +4997,7 @@ static uint16_t nvme_ns_attachment(NvmeCtrl *n, NvmeR= equest *req) } =20 nvme_attach_ns(ctrl, ns); - __nvme_select_ns_iocs(ctrl, ns); + nvme_select_iocs_ns(ctrl, ns); } else { if (!nvme_ns(ctrl, nsid)) { return NVME_NS_NOT_ATTACHED | NVME_DNR; @@ -5280,26 +5298,7 @@ static void nvme_ctrl_shutdown(NvmeCtrl *n) } } =20 -static void __nvme_select_ns_iocs(NvmeCtrl *n, NvmeNamespace *ns) -{ - ns->iocs =3D nvme_cse_iocs_none; - switch (ns->csi) { - case NVME_CSI_NVM: - if (NVME_CC_CSS(n->bar.cc) !=3D NVME_CC_CSS_ADMIN_ONLY) { - ns->iocs =3D nvme_cse_iocs_nvm; - } - break; - case NVME_CSI_ZONED: - if (NVME_CC_CSS(n->bar.cc) =3D=3D NVME_CC_CSS_CSI) { - ns->iocs =3D nvme_cse_iocs_zoned; - } else if (NVME_CC_CSS(n->bar.cc) =3D=3D NVME_CC_CSS_NVM) { - ns->iocs =3D nvme_cse_iocs_nvm; - } - break; - } -} - -static void nvme_select_ns_iocs(NvmeCtrl *n) +static void nvme_select_iocs(NvmeCtrl *n) { NvmeNamespace *ns; int i; @@ -5310,7 +5309,7 @@ static void nvme_select_ns_iocs(NvmeCtrl *n) continue; } =20 - __nvme_select_ns_iocs(n, ns); + nvme_select_iocs_ns(n, ns); } } =20 @@ -5412,7 +5411,7 @@ static int nvme_start_ctrl(NvmeCtrl *n) =20 QTAILQ_INIT(&n->aer_queue); =20 - nvme_select_ns_iocs(n); + nvme_select_iocs(n); =20 return 0; } --=20 2.31.1 From nobody Sat May 18 09:48:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1621243783; cv=none; d=zohomail.com; s=zohoarc; b=Yv+KMap2ZGdBf+E4bVY7z7oTh8y/7KuUxRgRxFd60dtU3r7n5bGzUHUl+bpl8xaeSdfzmlSw9ZECUI26nwmo8iYcn+omak5VVo5m98xc7fUNUsh25WvDqdnRki5Wn2KXqyxNEk4I1zrQ9t4v3mYGOlzx3EJ05nHHixouByg5p7Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621243783; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.24; envelope-from=its@irrelevant.dk; helo=wout1-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen In preparation for moving the nvme device into its own subtree, merge the header files into one. Also add missing copyright notice and add list of authors with substantial contributions. Signed-off-by: Klaus Jensen Reviewed-by: Keith Busch --- hw/block/nvme-dif.h | 63 ------- hw/block/nvme-ns.h | 229 ------------------------ hw/block/nvme-subsys.h | 59 ------- hw/block/nvme.h | 383 +++++++++++++++++++++++++++++++++++++---- hw/block/nvme-dif.c | 1 - hw/block/nvme-ns.c | 1 - hw/block/nvme-subsys.c | 1 - hw/block/nvme.c | 2 - 8 files changed, 348 insertions(+), 391 deletions(-) delete mode 100644 hw/block/nvme-dif.h delete mode 100644 hw/block/nvme-ns.h delete mode 100644 hw/block/nvme-subsys.h diff --git a/hw/block/nvme-dif.h b/hw/block/nvme-dif.h deleted file mode 100644 index 524faffbd7a0..000000000000 --- a/hw/block/nvme-dif.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * QEMU NVM Express End-to-End Data Protection support - * - * Copyright (c) 2021 Samsung Electronics Co., Ltd. - * - * Authors: - * Klaus Jensen - * Gollu Appalanaidu - */ - -#ifndef HW_NVME_DIF_H -#define HW_NVME_DIF_H - -/* from Linux kernel (crypto/crct10dif_common.c) */ -static const uint16_t t10_dif_crc_table[256] =3D { - 0x0000, 0x8BB7, 0x9CD9, 0x176E, 0xB205, 0x39B2, 0x2EDC, 0xA56B, - 0xEFBD, 0x640A, 0x7364, 0xF8D3, 0x5DB8, 0xD60F, 0xC161, 0x4AD6, - 0x54CD, 0xDF7A, 0xC814, 0x43A3, 0xE6C8, 0x6D7F, 0x7A11, 0xF1A6, - 0xBB70, 0x30C7, 0x27A9, 0xAC1E, 0x0975, 0x82C2, 0x95AC, 0x1E1B, - 0xA99A, 0x222D, 0x3543, 0xBEF4, 0x1B9F, 0x9028, 0x8746, 0x0CF1, - 0x4627, 0xCD90, 0xDAFE, 0x5149, 0xF422, 0x7F95, 0x68FB, 0xE34C, - 0xFD57, 0x76E0, 0x618E, 0xEA39, 0x4F52, 0xC4E5, 0xD38B, 0x583C, - 0x12EA, 0x995D, 0x8E33, 0x0584, 0xA0EF, 0x2B58, 0x3C36, 0xB781, - 0xD883, 0x5334, 0x445A, 0xCFED, 0x6A86, 0xE131, 0xF65F, 0x7DE8, - 0x373E, 0xBC89, 0xABE7, 0x2050, 0x853B, 0x0E8C, 0x19E2, 0x9255, - 0x8C4E, 0x07F9, 0x1097, 0x9B20, 0x3E4B, 0xB5FC, 0xA292, 0x2925, - 0x63F3, 0xE844, 0xFF2A, 0x749D, 0xD1F6, 0x5A41, 0x4D2F, 0xC698, - 0x7119, 0xFAAE, 0xEDC0, 0x6677, 0xC31C, 0x48AB, 0x5FC5, 0xD472, - 0x9EA4, 0x1513, 0x027D, 0x89CA, 0x2CA1, 0xA716, 0xB078, 0x3BCF, - 0x25D4, 0xAE63, 0xB90D, 0x32BA, 0x97D1, 0x1C66, 0x0B08, 0x80BF, - 0xCA69, 0x41DE, 0x56B0, 0xDD07, 0x786C, 0xF3DB, 0xE4B5, 0x6F02, - 0x3AB1, 0xB106, 0xA668, 0x2DDF, 0x88B4, 0x0303, 0x146D, 0x9FDA, - 0xD50C, 0x5EBB, 0x49D5, 0xC262, 0x6709, 0xECBE, 0xFBD0, 0x7067, - 0x6E7C, 0xE5CB, 0xF2A5, 0x7912, 0xDC79, 0x57CE, 0x40A0, 0xCB17, - 0x81C1, 0x0A76, 0x1D18, 0x96AF, 0x33C4, 0xB873, 0xAF1D, 0x24AA, - 0x932B, 0x189C, 0x0FF2, 0x8445, 0x212E, 0xAA99, 0xBDF7, 0x3640, - 0x7C96, 0xF721, 0xE04F, 0x6BF8, 0xCE93, 0x4524, 0x524A, 0xD9FD, - 0xC7E6, 0x4C51, 0x5B3F, 0xD088, 0x75E3, 0xFE54, 0xE93A, 0x628D, - 0x285B, 0xA3EC, 0xB482, 0x3F35, 0x9A5E, 0x11E9, 0x0687, 0x8D30, - 0xE232, 0x6985, 0x7EEB, 0xF55C, 0x5037, 0xDB80, 0xCCEE, 0x4759, - 0x0D8F, 0x8638, 0x9156, 0x1AE1, 0xBF8A, 0x343D, 0x2353, 0xA8E4, - 0xB6FF, 0x3D48, 0x2A26, 0xA191, 0x04FA, 0x8F4D, 0x9823, 0x1394, - 0x5942, 0xD2F5, 0xC59B, 0x4E2C, 0xEB47, 0x60F0, 0x779E, 0xFC29, - 0x4BA8, 0xC01F, 0xD771, 0x5CC6, 0xF9AD, 0x721A, 0x6574, 0xEEC3, - 0xA415, 0x2FA2, 0x38CC, 0xB37B, 0x1610, 0x9DA7, 0x8AC9, 0x017E, - 0x1F65, 0x94D2, 0x83BC, 0x080B, 0xAD60, 0x26D7, 0x31B9, 0xBA0E, - 0xF0D8, 0x7B6F, 0x6C01, 0xE7B6, 0x42DD, 0xC96A, 0xDE04, 0x55B3 -}; - -uint16_t nvme_check_prinfo(NvmeNamespace *ns, uint16_t ctrl, uint64_t slba, - uint32_t reftag); -uint16_t nvme_dif_mangle_mdata(NvmeNamespace *ns, uint8_t *mbuf, size_t ml= en, - uint64_t slba); -void nvme_dif_pract_generate_dif(NvmeNamespace *ns, uint8_t *buf, size_t l= en, - uint8_t *mbuf, size_t mlen, uint16_t appt= ag, - uint32_t reftag); -uint16_t nvme_dif_check(NvmeNamespace *ns, uint8_t *buf, size_t len, - uint8_t *mbuf, size_t mlen, uint16_t ctrl, - uint64_t slba, uint16_t apptag, - uint16_t appmask, uint32_t reftag); -uint16_t nvme_dif_rw(NvmeCtrl *n, NvmeRequest *req); - -#endif /* HW_NVME_DIF_H */ diff --git a/hw/block/nvme-ns.h b/hw/block/nvme-ns.h deleted file mode 100644 index fb0a41f912e7..000000000000 --- a/hw/block/nvme-ns.h +++ /dev/null @@ -1,229 +0,0 @@ -/* - * QEMU NVM Express Virtual Namespace - * - * Copyright (c) 2019 CNEX Labs - * Copyright (c) 2020 Samsung Electronics - * - * Authors: - * Klaus Jensen - * - * This work is licensed under the terms of the GNU GPL, version 2. See the - * COPYING file in the top-level directory. - * - */ - -#ifndef NVME_NS_H -#define NVME_NS_H - -#include "qemu/uuid.h" - -#define TYPE_NVME_NS "nvme-ns" -#define NVME_NS(obj) \ - OBJECT_CHECK(NvmeNamespace, (obj), TYPE_NVME_NS) - -typedef struct NvmeZone { - NvmeZoneDescr d; - uint64_t w_ptr; - QTAILQ_ENTRY(NvmeZone) entry; -} NvmeZone; - -typedef struct NvmeNamespaceParams { - bool detached; - bool shared; - uint32_t nsid; - QemuUUID uuid; - - uint16_t ms; - uint8_t mset; - uint8_t pi; - uint8_t pil; - - uint16_t mssrl; - uint32_t mcl; - uint8_t msrc; - - bool zoned; - bool cross_zone_read; - uint64_t zone_size_bs; - uint64_t zone_cap_bs; - uint32_t max_active_zones; - uint32_t max_open_zones; - uint32_t zd_extension_size; -} NvmeNamespaceParams; - -typedef struct NvmeNamespace { - DeviceState parent_obj; - BlockConf blkconf; - int32_t bootindex; - int64_t size; - int64_t mdata_offset; - NvmeIdNs id_ns; - const uint32_t *iocs; - uint8_t csi; - uint16_t status; - int attached; - - QTAILQ_ENTRY(NvmeNamespace) entry; - - NvmeIdNsZoned *id_ns_zoned; - NvmeZone *zone_array; - QTAILQ_HEAD(, NvmeZone) exp_open_zones; - QTAILQ_HEAD(, NvmeZone) imp_open_zones; - QTAILQ_HEAD(, NvmeZone) closed_zones; - QTAILQ_HEAD(, NvmeZone) full_zones; - uint32_t num_zones; - uint64_t zone_size; - uint64_t zone_capacity; - uint32_t zone_size_log2; - uint8_t *zd_extensions; - int32_t nr_open_zones; - int32_t nr_active_zones; - - NvmeNamespaceParams params; - - struct { - uint32_t err_rec; - } features; -} NvmeNamespace; - -static inline uint16_t nvme_ns_status(NvmeNamespace *ns) -{ - return ns->status; -} - -static inline uint32_t nvme_nsid(NvmeNamespace *ns) -{ - if (ns) { - return ns->params.nsid; - } - - return 0; -} - -static inline NvmeLBAF *nvme_ns_lbaf(NvmeNamespace *ns) -{ - NvmeIdNs *id_ns =3D &ns->id_ns; - return &id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(id_ns->flbas)]; -} - -static inline uint8_t nvme_ns_lbads(NvmeNamespace *ns) -{ - return nvme_ns_lbaf(ns)->ds; -} - -/* convert an LBA to the equivalent in bytes */ -static inline size_t nvme_l2b(NvmeNamespace *ns, uint64_t lba) -{ - return lba << nvme_ns_lbads(ns); -} - -static inline size_t nvme_lsize(NvmeNamespace *ns) -{ - return 1 << nvme_ns_lbads(ns); -} - -static inline uint16_t nvme_msize(NvmeNamespace *ns) -{ - return nvme_ns_lbaf(ns)->ms; -} - -static inline size_t nvme_m2b(NvmeNamespace *ns, uint64_t lba) -{ - return nvme_msize(ns) * lba; -} - -static inline bool nvme_ns_ext(NvmeNamespace *ns) -{ - return !!NVME_ID_NS_FLBAS_EXTENDED(ns->id_ns.flbas); -} - -/* calculate the number of LBAs that the namespace can accomodate */ -static inline uint64_t nvme_ns_nlbas(NvmeNamespace *ns) -{ - if (nvme_msize(ns)) { - return ns->size / (nvme_lsize(ns) + nvme_msize(ns)); - } - return ns->size >> nvme_ns_lbads(ns); -} - -typedef struct NvmeCtrl NvmeCtrl; - -static inline NvmeZoneState nvme_get_zone_state(NvmeZone *zone) -{ - return zone->d.zs >> 4; -} - -static inline void nvme_set_zone_state(NvmeZone *zone, NvmeZoneState state) -{ - zone->d.zs =3D state << 4; -} - -static inline uint64_t nvme_zone_rd_boundary(NvmeNamespace *ns, NvmeZone *= zone) -{ - return zone->d.zslba + ns->zone_size; -} - -static inline uint64_t nvme_zone_wr_boundary(NvmeZone *zone) -{ - return zone->d.zslba + zone->d.zcap; -} - -static inline bool nvme_wp_is_valid(NvmeZone *zone) -{ - uint8_t st =3D nvme_get_zone_state(zone); - - return st !=3D NVME_ZONE_STATE_FULL && - st !=3D NVME_ZONE_STATE_READ_ONLY && - st !=3D NVME_ZONE_STATE_OFFLINE; -} - -static inline uint8_t *nvme_get_zd_extension(NvmeNamespace *ns, - uint32_t zone_idx) -{ - return &ns->zd_extensions[zone_idx * ns->params.zd_extension_size]; -} - -static inline void nvme_aor_inc_open(NvmeNamespace *ns) -{ - assert(ns->nr_open_zones >=3D 0); - if (ns->params.max_open_zones) { - ns->nr_open_zones++; - assert(ns->nr_open_zones <=3D ns->params.max_open_zones); - } -} - -static inline void nvme_aor_dec_open(NvmeNamespace *ns) -{ - if (ns->params.max_open_zones) { - assert(ns->nr_open_zones > 0); - ns->nr_open_zones--; - } - assert(ns->nr_open_zones >=3D 0); -} - -static inline void nvme_aor_inc_active(NvmeNamespace *ns) -{ - assert(ns->nr_active_zones >=3D 0); - if (ns->params.max_active_zones) { - ns->nr_active_zones++; - assert(ns->nr_active_zones <=3D ns->params.max_active_zones); - } -} - -static inline void nvme_aor_dec_active(NvmeNamespace *ns) -{ - if (ns->params.max_active_zones) { - assert(ns->nr_active_zones > 0); - ns->nr_active_zones--; - assert(ns->nr_active_zones >=3D ns->nr_open_zones); - } - assert(ns->nr_active_zones >=3D 0); -} - -void nvme_ns_init_format(NvmeNamespace *ns); -int nvme_ns_setup(NvmeCtrl *n, NvmeNamespace *ns, Error **errp); -void nvme_ns_drain(NvmeNamespace *ns); -void nvme_ns_shutdown(NvmeNamespace *ns); -void nvme_ns_cleanup(NvmeNamespace *ns); - -#endif /* NVME_NS_H */ diff --git a/hw/block/nvme-subsys.h b/hw/block/nvme-subsys.h deleted file mode 100644 index 7d7ef5f7f12b..000000000000 --- a/hw/block/nvme-subsys.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * QEMU NVM Express Subsystem: nvme-subsys - * - * Copyright (c) 2021 Minwoo Im - * - * This code is licensed under the GNU GPL v2. Refer COPYING. - */ - -#ifndef NVME_SUBSYS_H -#define NVME_SUBSYS_H - -#define TYPE_NVME_SUBSYS "nvme-subsys" -#define NVME_SUBSYS(obj) \ - OBJECT_CHECK(NvmeSubsystem, (obj), TYPE_NVME_SUBSYS) - -#define NVME_SUBSYS_MAX_CTRLS 32 -#define NVME_MAX_NAMESPACES 256 - -typedef struct NvmeCtrl NvmeCtrl; -typedef struct NvmeNamespace NvmeNamespace; -typedef struct NvmeSubsystem { - DeviceState parent_obj; - uint8_t subnqn[256]; - - NvmeCtrl *ctrls[NVME_SUBSYS_MAX_CTRLS]; - /* Allocated namespaces for this subsystem */ - NvmeNamespace *namespaces[NVME_MAX_NAMESPACES + 1]; - - struct { - char *nqn; - } params; -} NvmeSubsystem; - -int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp); - -static inline NvmeCtrl *nvme_subsys_ctrl(NvmeSubsystem *subsys, - uint32_t cntlid) -{ - if (!subsys || cntlid >=3D NVME_SUBSYS_MAX_CTRLS) { - return NULL; - } - - return subsys->ctrls[cntlid]; -} - -/* - * Return allocated namespace of the specified nsid in the subsystem. - */ -static inline NvmeNamespace *nvme_subsys_ns(NvmeSubsystem *subsys, - uint32_t nsid) -{ - if (!subsys || !nsid || nsid > NVME_MAX_NAMESPACES) { - return NULL; - } - - return subsys->namespaces[nsid]; -} - -#endif /* NVME_SUBSYS_H */ diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 5d05ec368f7a..d9374d3e33e0 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -1,28 +1,281 @@ +/* + * QEMU NVM Express + * + * Copyright (c) 2012 Intel Corporation + * Copyright (c) 2021 Minwoo Im + * Copyright (c) 2021 Samsung Electronics Co., Ltd. + * + * Authors: + * Keith Busch + * Klaus Jensen + * Gollu Appalanaidu + * Dmitry Fomichev + * Minwoo Im + * + * This code is licensed under the GNU GPL v2 or later. + */ + #ifndef HW_NVME_H #define HW_NVME_H =20 -#include "block/nvme.h" +#include "qemu/uuid.h" #include "hw/pci/pci.h" -#include "nvme-subsys.h" -#include "nvme-ns.h" +#include "hw/block/block.h" + +#include "block/nvme.h" =20 #define NVME_DEFAULT_ZONE_SIZE (128 * MiB) #define NVME_DEFAULT_MAX_ZA_SIZE (128 * KiB) +#define NVME_MAX_CONTROLLERS 32 +#define NVME_MAX_NAMESPACES 256 =20 -typedef struct NvmeParams { - char *serial; - uint32_t num_queues; /* deprecated since 5.1 */ - uint32_t max_ioqpairs; - uint16_t msix_qsize; - uint32_t cmb_size_mb; - uint8_t aerl; - uint32_t aer_max_queued; - uint8_t mdts; - uint8_t vsl; - bool use_intel_id; - uint8_t zasl; - bool legacy_cmb; -} NvmeParams; +typedef struct NvmeCtrl NvmeCtrl; +typedef struct NvmeNamespace NvmeNamespace; + +#define TYPE_NVME_SUBSYS "nvme-subsys" +#define NVME_SUBSYS(obj) \ + OBJECT_CHECK(NvmeSubsystem, (obj), TYPE_NVME_SUBSYS) + +typedef struct NvmeSubsystem { + DeviceState parent_obj; + uint8_t subnqn[256]; + + NvmeCtrl *ctrls[NVME_MAX_CONTROLLERS]; + NvmeNamespace *namespaces[NVME_MAX_NAMESPACES + 1]; + + struct { + char *nqn; + } params; +} NvmeSubsystem; + +int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp); + +static inline NvmeCtrl *nvme_subsys_ctrl(NvmeSubsystem *subsys, + uint32_t cntlid) +{ + if (!subsys || cntlid >=3D NVME_MAX_CONTROLLERS) { + return NULL; + } + + return subsys->ctrls[cntlid]; +} + +static inline NvmeNamespace *nvme_subsys_ns(NvmeSubsystem *subsys, + uint32_t nsid) +{ + if (!subsys || !nsid || nsid > NVME_MAX_NAMESPACES) { + return NULL; + } + + return subsys->namespaces[nsid]; +} + +#define TYPE_NVME_NS "nvme-ns" +#define NVME_NS(obj) \ + OBJECT_CHECK(NvmeNamespace, (obj), TYPE_NVME_NS) + +typedef struct NvmeZone { + NvmeZoneDescr d; + uint64_t w_ptr; + QTAILQ_ENTRY(NvmeZone) entry; +} NvmeZone; + +typedef struct NvmeNamespaceParams { + bool detached; + bool shared; + uint32_t nsid; + QemuUUID uuid; + + uint16_t ms; + uint8_t mset; + uint8_t pi; + uint8_t pil; + + uint16_t mssrl; + uint32_t mcl; + uint8_t msrc; + + bool zoned; + bool cross_zone_read; + uint64_t zone_size_bs; + uint64_t zone_cap_bs; + uint32_t max_active_zones; + uint32_t max_open_zones; + uint32_t zd_extension_size; +} NvmeNamespaceParams; + +typedef struct NvmeNamespace { + DeviceState parent_obj; + BlockConf blkconf; + int32_t bootindex; + int64_t size; + int64_t mdata_offset; + NvmeIdNs id_ns; + const uint32_t *iocs; + uint8_t csi; + uint16_t status; + int attached; + + QTAILQ_ENTRY(NvmeNamespace) entry; + + NvmeIdNsZoned *id_ns_zoned; + NvmeZone *zone_array; + QTAILQ_HEAD(, NvmeZone) exp_open_zones; + QTAILQ_HEAD(, NvmeZone) imp_open_zones; + QTAILQ_HEAD(, NvmeZone) closed_zones; + QTAILQ_HEAD(, NvmeZone) full_zones; + uint32_t num_zones; + uint64_t zone_size; + uint64_t zone_capacity; + uint32_t zone_size_log2; + uint8_t *zd_extensions; + int32_t nr_open_zones; + int32_t nr_active_zones; + + NvmeNamespaceParams params; + + struct { + uint32_t err_rec; + } features; +} NvmeNamespace; + +static inline uint16_t nvme_ns_status(NvmeNamespace *ns) +{ + return ns->status; +} + +static inline uint32_t nvme_nsid(NvmeNamespace *ns) +{ + if (ns) { + return ns->params.nsid; + } + + return 0; +} + +static inline NvmeLBAF *nvme_ns_lbaf(NvmeNamespace *ns) +{ + NvmeIdNs *id_ns =3D &ns->id_ns; + return &id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(id_ns->flbas)]; +} + +static inline uint8_t nvme_ns_lbads(NvmeNamespace *ns) +{ + return nvme_ns_lbaf(ns)->ds; +} + +/* convert an LBA to the equivalent in bytes */ +static inline size_t nvme_l2b(NvmeNamespace *ns, uint64_t lba) +{ + return lba << nvme_ns_lbads(ns); +} + +static inline size_t nvme_lsize(NvmeNamespace *ns) +{ + return 1 << nvme_ns_lbads(ns); +} + +static inline uint16_t nvme_msize(NvmeNamespace *ns) +{ + return nvme_ns_lbaf(ns)->ms; +} + +static inline size_t nvme_m2b(NvmeNamespace *ns, uint64_t lba) +{ + return nvme_msize(ns) * lba; +} + +static inline bool nvme_ns_ext(NvmeNamespace *ns) +{ + return !!NVME_ID_NS_FLBAS_EXTENDED(ns->id_ns.flbas); +} + +/* calculate the number of LBAs that the namespace can accomodate */ +static inline uint64_t nvme_ns_nlbas(NvmeNamespace *ns) +{ + if (nvme_msize(ns)) { + return ns->size / (nvme_lsize(ns) + nvme_msize(ns)); + } + return ns->size >> nvme_ns_lbads(ns); +} + +static inline NvmeZoneState nvme_get_zone_state(NvmeZone *zone) +{ + return zone->d.zs >> 4; +} + +static inline void nvme_set_zone_state(NvmeZone *zone, NvmeZoneState state) +{ + zone->d.zs =3D state << 4; +} + +static inline uint64_t nvme_zone_rd_boundary(NvmeNamespace *ns, NvmeZone *= zone) +{ + return zone->d.zslba + ns->zone_size; +} + +static inline uint64_t nvme_zone_wr_boundary(NvmeZone *zone) +{ + return zone->d.zslba + zone->d.zcap; +} + +static inline bool nvme_wp_is_valid(NvmeZone *zone) +{ + uint8_t st =3D nvme_get_zone_state(zone); + + return st !=3D NVME_ZONE_STATE_FULL && + st !=3D NVME_ZONE_STATE_READ_ONLY && + st !=3D NVME_ZONE_STATE_OFFLINE; +} + +static inline uint8_t *nvme_get_zd_extension(NvmeNamespace *ns, + uint32_t zone_idx) +{ + return &ns->zd_extensions[zone_idx * ns->params.zd_extension_size]; +} + +static inline void nvme_aor_inc_open(NvmeNamespace *ns) +{ + assert(ns->nr_open_zones >=3D 0); + if (ns->params.max_open_zones) { + ns->nr_open_zones++; + assert(ns->nr_open_zones <=3D ns->params.max_open_zones); + } +} + +static inline void nvme_aor_dec_open(NvmeNamespace *ns) +{ + if (ns->params.max_open_zones) { + assert(ns->nr_open_zones > 0); + ns->nr_open_zones--; + } + assert(ns->nr_open_zones >=3D 0); +} + +static inline void nvme_aor_inc_active(NvmeNamespace *ns) +{ + assert(ns->nr_active_zones >=3D 0); + if (ns->params.max_active_zones) { + ns->nr_active_zones++; + assert(ns->nr_active_zones <=3D ns->params.max_active_zones); + } +} + +static inline void nvme_aor_dec_active(NvmeNamespace *ns) +{ + if (ns->params.max_active_zones) { + assert(ns->nr_active_zones > 0); + ns->nr_active_zones--; + assert(ns->nr_active_zones >=3D ns->nr_open_zones); + } + assert(ns->nr_active_zones >=3D 0); +} + +void nvme_ns_init_format(NvmeNamespace *ns); +int nvme_ns_setup(NvmeCtrl *n, NvmeNamespace *ns, Error **errp); +void nvme_ns_drain(NvmeNamespace *ns); +void nvme_ns_shutdown(NvmeNamespace *ns); +void nvme_ns_cleanup(NvmeNamespace *ns); =20 typedef struct NvmeAsyncEvent { QTAILQ_ENTRY(NvmeAsyncEvent) entry; @@ -43,6 +296,11 @@ typedef struct NvmeSg { }; } NvmeSg; =20 +typedef enum NvmeTxDirection { + NVME_TX_DIRECTION_TO_DEVICE =3D 0, + NVME_TX_DIRECTION_FROM_DEVICE =3D 1, +} NvmeTxDirection; + typedef struct NvmeRequest { struct NvmeSQueue *sq; struct NvmeNamespace *ns; @@ -143,13 +401,20 @@ typedef struct NvmeBus { #define NVME(obj) \ OBJECT_CHECK(NvmeCtrl, (obj), TYPE_NVME) =20 -typedef struct NvmeFeatureVal { - struct { - uint16_t temp_thresh_hi; - uint16_t temp_thresh_low; - }; - uint32_t async_config; -} NvmeFeatureVal; +typedef struct NvmeParams { + char *serial; + uint32_t num_queues; /* deprecated since 5.1 */ + uint32_t max_ioqpairs; + uint16_t msix_qsize; + uint32_t cmb_size_mb; + uint8_t aerl; + uint32_t aer_max_queued; + uint8_t mdts; + uint8_t vsl; + bool use_intel_id; + uint8_t zasl; + bool legacy_cmb; +} NvmeParams; =20 typedef struct NvmeCtrl { PCIDevice parent_obj; @@ -204,22 +469,25 @@ typedef struct NvmeCtrl { NvmeSubsystem *subsys; =20 NvmeNamespace namespace; - /* - * Attached namespaces to this controller. If subsys is not given, all - * namespaces in this list will always be attached. - */ NvmeNamespace *namespaces[NVME_MAX_NAMESPACES]; NvmeSQueue **sq; NvmeCQueue **cq; NvmeSQueue admin_sq; NvmeCQueue admin_cq; NvmeIdCtrl id_ctrl; - NvmeFeatureVal features; + + struct { + struct { + uint16_t temp_thresh_hi; + uint16_t temp_thresh_low; + }; + uint32_t async_config; + } features; } NvmeCtrl; =20 static inline NvmeNamespace *nvme_ns(NvmeCtrl *n, uint32_t nsid) { - if (!nsid || nsid > n->num_namespaces) { + if (!nsid || nsid > NVME_MAX_NAMESPACES) { return NULL; } =20 @@ -249,11 +517,6 @@ static inline uint16_t nvme_cid(NvmeRequest *req) return le16_to_cpu(req->cqe.cid); } =20 -typedef enum NvmeTxDirection { - NVME_TX_DIRECTION_TO_DEVICE =3D 0, - NVME_TX_DIRECTION_FROM_DEVICE =3D 1, -} NvmeTxDirection; - void nvme_attach_ns(NvmeCtrl *n, NvmeNamespace *ns); uint16_t nvme_bounce_data(NvmeCtrl *n, uint8_t *ptr, uint32_t len, NvmeTxDirection dir, NvmeRequest *req); @@ -263,4 +526,54 @@ void nvme_rw_complete_cb(void *opaque, int ret); uint16_t nvme_map_dptr(NvmeCtrl *n, NvmeSg *sg, size_t len, NvmeCmd *cmd); =20 +/* from Linux kernel (crypto/crct10dif_common.c) */ +static const uint16_t t10_dif_crc_table[256] =3D { + 0x0000, 0x8BB7, 0x9CD9, 0x176E, 0xB205, 0x39B2, 0x2EDC, 0xA56B, + 0xEFBD, 0x640A, 0x7364, 0xF8D3, 0x5DB8, 0xD60F, 0xC161, 0x4AD6, + 0x54CD, 0xDF7A, 0xC814, 0x43A3, 0xE6C8, 0x6D7F, 0x7A11, 0xF1A6, + 0xBB70, 0x30C7, 0x27A9, 0xAC1E, 0x0975, 0x82C2, 0x95AC, 0x1E1B, + 0xA99A, 0x222D, 0x3543, 0xBEF4, 0x1B9F, 0x9028, 0x8746, 0x0CF1, + 0x4627, 0xCD90, 0xDAFE, 0x5149, 0xF422, 0x7F95, 0x68FB, 0xE34C, + 0xFD57, 0x76E0, 0x618E, 0xEA39, 0x4F52, 0xC4E5, 0xD38B, 0x583C, + 0x12EA, 0x995D, 0x8E33, 0x0584, 0xA0EF, 0x2B58, 0x3C36, 0xB781, + 0xD883, 0x5334, 0x445A, 0xCFED, 0x6A86, 0xE131, 0xF65F, 0x7DE8, + 0x373E, 0xBC89, 0xABE7, 0x2050, 0x853B, 0x0E8C, 0x19E2, 0x9255, + 0x8C4E, 0x07F9, 0x1097, 0x9B20, 0x3E4B, 0xB5FC, 0xA292, 0x2925, + 0x63F3, 0xE844, 0xFF2A, 0x749D, 0xD1F6, 0x5A41, 0x4D2F, 0xC698, + 0x7119, 0xFAAE, 0xEDC0, 0x6677, 0xC31C, 0x48AB, 0x5FC5, 0xD472, + 0x9EA4, 0x1513, 0x027D, 0x89CA, 0x2CA1, 0xA716, 0xB078, 0x3BCF, + 0x25D4, 0xAE63, 0xB90D, 0x32BA, 0x97D1, 0x1C66, 0x0B08, 0x80BF, + 0xCA69, 0x41DE, 0x56B0, 0xDD07, 0x786C, 0xF3DB, 0xE4B5, 0x6F02, + 0x3AB1, 0xB106, 0xA668, 0x2DDF, 0x88B4, 0x0303, 0x146D, 0x9FDA, + 0xD50C, 0x5EBB, 0x49D5, 0xC262, 0x6709, 0xECBE, 0xFBD0, 0x7067, + 0x6E7C, 0xE5CB, 0xF2A5, 0x7912, 0xDC79, 0x57CE, 0x40A0, 0xCB17, + 0x81C1, 0x0A76, 0x1D18, 0x96AF, 0x33C4, 0xB873, 0xAF1D, 0x24AA, + 0x932B, 0x189C, 0x0FF2, 0x8445, 0x212E, 0xAA99, 0xBDF7, 0x3640, + 0x7C96, 0xF721, 0xE04F, 0x6BF8, 0xCE93, 0x4524, 0x524A, 0xD9FD, + 0xC7E6, 0x4C51, 0x5B3F, 0xD088, 0x75E3, 0xFE54, 0xE93A, 0x628D, + 0x285B, 0xA3EC, 0xB482, 0x3F35, 0x9A5E, 0x11E9, 0x0687, 0x8D30, + 0xE232, 0x6985, 0x7EEB, 0xF55C, 0x5037, 0xDB80, 0xCCEE, 0x4759, + 0x0D8F, 0x8638, 0x9156, 0x1AE1, 0xBF8A, 0x343D, 0x2353, 0xA8E4, + 0xB6FF, 0x3D48, 0x2A26, 0xA191, 0x04FA, 0x8F4D, 0x9823, 0x1394, + 0x5942, 0xD2F5, 0xC59B, 0x4E2C, 0xEB47, 0x60F0, 0x779E, 0xFC29, + 0x4BA8, 0xC01F, 0xD771, 0x5CC6, 0xF9AD, 0x721A, 0x6574, 0xEEC3, + 0xA415, 0x2FA2, 0x38CC, 0xB37B, 0x1610, 0x9DA7, 0x8AC9, 0x017E, + 0x1F65, 0x94D2, 0x83BC, 0x080B, 0xAD60, 0x26D7, 0x31B9, 0xBA0E, + 0xF0D8, 0x7B6F, 0x6C01, 0xE7B6, 0x42DD, 0xC96A, 0xDE04, 0x55B3 +}; + +uint16_t nvme_check_prinfo(NvmeNamespace *ns, uint16_t ctrl, uint64_t slba, + uint32_t reftag); +uint16_t nvme_dif_mangle_mdata(NvmeNamespace *ns, uint8_t *mbuf, size_t ml= en, + uint64_t slba); +void nvme_dif_pract_generate_dif(NvmeNamespace *ns, uint8_t *buf, size_t l= en, + uint8_t *mbuf, size_t mlen, uint16_t appt= ag, + uint32_t reftag); +uint16_t nvme_dif_check(NvmeNamespace *ns, uint8_t *buf, size_t len, + uint8_t *mbuf, size_t mlen, uint16_t ctrl, + uint64_t slba, uint16_t apptag, + uint16_t appmask, uint32_t reftag); +uint16_t nvme_dif_rw(NvmeCtrl *n, NvmeRequest *req); + + #endif /* HW_NVME_H */ diff --git a/hw/block/nvme-dif.c b/hw/block/nvme-dif.c index 81b0a4cb1382..25e5a90854fa 100644 --- a/hw/block/nvme-dif.c +++ b/hw/block/nvme-dif.c @@ -15,7 +15,6 @@ #include "qapi/error.h" #include "trace.h" #include "nvme.h" -#include "nvme-dif.h" =20 uint16_t nvme_check_prinfo(NvmeNamespace *ns, uint16_t ctrl, uint64_t slba, uint32_t reftag) diff --git a/hw/block/nvme-ns.c b/hw/block/nvme-ns.c index a0895614d9c3..4d7103e78ff8 100644 --- a/hw/block/nvme-ns.c +++ b/hw/block/nvme-ns.c @@ -28,7 +28,6 @@ =20 #include "trace.h" #include "nvme.h" -#include "nvme-ns.h" =20 #define MIN_DISCARD_GRANULARITY (4 * KiB) =20 diff --git a/hw/block/nvme-subsys.c b/hw/block/nvme-subsys.c index 9604c19117de..3c404e3fcb78 100644 --- a/hw/block/nvme-subsys.c +++ b/hw/block/nvme-subsys.c @@ -19,7 +19,6 @@ #include "block/accounting.h" #include "hw/pci/pci.h" #include "nvme.h" -#include "nvme-subsys.h" =20 int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp) { diff --git a/hw/block/nvme.c b/hw/block/nvme.c index f0cfca869875..29f80d543903 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -162,8 +162,6 @@ #include "qemu/cutils.h" #include "trace.h" #include "nvme.h" -#include "nvme-ns.h" -#include "nvme-dif.h" =20 #define NVME_MAX_IOQPAIRS 0xffff #define NVME_DB_SIZE 4 --=20 2.31.1 From nobody Sat May 18 09:48:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.24; envelope-from=its@irrelevant.dk; helo=wout1-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Clean up includes. Signed-off-by: Klaus Jensen Reviewed-by: Keith Busch --- hw/block/nvme-dif.c | 7 +++---- hw/block/nvme-ns.c | 11 ++--------- hw/block/nvme-subsys.c | 11 +---------- hw/block/nvme.c | 22 +++++++++------------- 4 files changed, 15 insertions(+), 36 deletions(-) diff --git a/hw/block/nvme-dif.c b/hw/block/nvme-dif.c index 25e5a90854fa..e269d275ebed 100644 --- a/hw/block/nvme-dif.c +++ b/hw/block/nvme-dif.c @@ -9,12 +9,11 @@ */ =20 #include "qemu/osdep.h" -#include "hw/block/block.h" -#include "sysemu/dma.h" -#include "sysemu/block-backend.h" #include "qapi/error.h" -#include "trace.h" +#include "sysemu/block-backend.h" + #include "nvme.h" +#include "trace.h" =20 uint16_t nvme_check_prinfo(NvmeNamespace *ns, uint16_t ctrl, uint64_t slba, uint32_t reftag) diff --git a/hw/block/nvme-ns.c b/hw/block/nvme-ns.c index 4d7103e78ff8..d91bf7bbbbbb 100644 --- a/hw/block/nvme-ns.c +++ b/hw/block/nvme-ns.c @@ -14,20 +14,13 @@ =20 #include "qemu/osdep.h" #include "qemu/units.h" -#include "qemu/cutils.h" -#include "qemu/log.h" #include "qemu/error-report.h" -#include "hw/block/block.h" -#include "hw/pci/pci.h" +#include "qapi/error.h" #include "sysemu/sysemu.h" #include "sysemu/block-backend.h" -#include "qapi/error.h" =20 -#include "hw/qdev-properties.h" -#include "hw/qdev-core.h" - -#include "trace.h" #include "nvme.h" +#include "trace.h" =20 #define MIN_DISCARD_GRANULARITY (4 * KiB) =20 diff --git a/hw/block/nvme-subsys.c b/hw/block/nvme-subsys.c index 3c404e3fcb78..192223d17ca1 100644 --- a/hw/block/nvme-subsys.c +++ b/hw/block/nvme-subsys.c @@ -6,18 +6,9 @@ * This code is licensed under the GNU GPL v2. Refer COPYING. */ =20 -#include "qemu/units.h" #include "qemu/osdep.h" -#include "qemu/uuid.h" -#include "qemu/iov.h" -#include "qemu/cutils.h" #include "qapi/error.h" -#include "hw/qdev-properties.h" -#include "hw/qdev-core.h" -#include "hw/block/block.h" -#include "block/aio.h" -#include "block/accounting.h" -#include "hw/pci/pci.h" + #include "nvme.h" =20 int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 29f80d543903..e152c61adb76 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -144,24 +144,20 @@ */ =20 #include "qemu/osdep.h" -#include "qemu/units.h" +#include "qemu/cutils.h" #include "qemu/error-report.h" -#include "hw/block/block.h" -#include "hw/pci/msix.h" -#include "hw/pci/pci.h" -#include "hw/qdev-properties.h" -#include "migration/vmstate.h" -#include "sysemu/sysemu.h" +#include "qemu/log.h" +#include "qemu/units.h" #include "qapi/error.h" #include "qapi/visitor.h" -#include "sysemu/hostmem.h" +#include "sysemu/sysemu.h" #include "sysemu/block-backend.h" -#include "exec/memory.h" -#include "qemu/log.h" -#include "qemu/module.h" -#include "qemu/cutils.h" -#include "trace.h" +#include "sysemu/hostmem.h" +#include "hw/pci/msix.h" +#include "migration/vmstate.h" + #include "nvme.h" +#include "trace.h" =20 #define NVME_MAX_IOQPAIRS 0xffff #define NVME_DB_SIZE 4 --=20 2.31.1 From nobody Sat May 18 09:48:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.24; envelope-from=its@irrelevant.dk; helo=wout1-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Remove non-shared defines from the shared header. Signed-off-by: Klaus Jensen Reviewed-by: Keith Busch --- hw/block/nvme.h | 2 -- hw/block/nvme-ns.c | 1 + hw/block/nvme.c | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/block/nvme.h b/hw/block/nvme.h index d9374d3e33e0..2c4e7b90fa54 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -24,8 +24,6 @@ =20 #include "block/nvme.h" =20 -#define NVME_DEFAULT_ZONE_SIZE (128 * MiB) -#define NVME_DEFAULT_MAX_ZA_SIZE (128 * KiB) #define NVME_MAX_CONTROLLERS 32 #define NVME_MAX_NAMESPACES 256 =20 diff --git a/hw/block/nvme-ns.c b/hw/block/nvme-ns.c index d91bf7bbbbbb..93aaf6de02af 100644 --- a/hw/block/nvme-ns.c +++ b/hw/block/nvme-ns.c @@ -23,6 +23,7 @@ #include "trace.h" =20 #define MIN_DISCARD_GRANULARITY (4 * KiB) +#define NVME_DEFAULT_ZONE_SIZE (128 * MiB) =20 void nvme_ns_init_format(NvmeNamespace *ns) { diff --git a/hw/block/nvme.c b/hw/block/nvme.c index e152c61adb76..e7bd22b8b2ed 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -168,6 +168,7 @@ #define NVME_TEMPERATURE_WARNING 0x157 #define NVME_TEMPERATURE_CRITICAL 0x175 #define NVME_NUM_FW_SLOTS 1 +#define NVME_DEFAULT_MAX_ZA_SIZE (128 * KiB) =20 #define NVME_GUEST_ERR(trace, fmt, ...) \ do { \ --=20 2.31.1 From nobody Sat May 18 09:48:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.24; envelope-from=its@irrelevant.dk; helo=wout1-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen The inline nvme_ns_status() helper only has a single call site. Remove it from the header file and inline it for real. Signed-off-by: Klaus Jensen Reviewed-by: Keith Busch --- hw/block/nvme.h | 5 ----- hw/block/nvme.c | 15 ++++++++------- 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 2c4e7b90fa54..d9bee7e5a05c 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -137,11 +137,6 @@ typedef struct NvmeNamespace { } features; } NvmeNamespace; =20 -static inline uint16_t nvme_ns_status(NvmeNamespace *ns) -{ - return ns->status; -} - static inline uint32_t nvme_nsid(NvmeNamespace *ns) { if (ns) { diff --git a/hw/block/nvme.c b/hw/block/nvme.c index e7bd22b8b2ed..710af6a7147c 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -3609,8 +3609,8 @@ static uint16_t nvme_zone_mgmt_recv(NvmeCtrl *n, Nvme= Request *req) =20 static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest *req) { + NvmeNamespace *ns; uint32_t nsid =3D le32_to_cpu(req->cmd.nsid); - uint16_t status; =20 trace_pci_nvme_io_cmd(nvme_cid(req), nsid, nvme_sqid(req), req->cmd.opcode, nvme_io_opc_str(req->cmd.opcode= )); @@ -3642,21 +3642,22 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeReques= t *req) return nvme_flush(n, req); } =20 - req->ns =3D nvme_ns(n, nsid); - if (unlikely(!req->ns)) { + ns =3D nvme_ns(n, nsid); + if (unlikely(!ns)) { return NVME_INVALID_FIELD | NVME_DNR; } =20 - if (!(req->ns->iocs[req->cmd.opcode] & NVME_CMD_EFF_CSUPP)) { + if (!(ns->iocs[req->cmd.opcode] & NVME_CMD_EFF_CSUPP)) { trace_pci_nvme_err_invalid_opc(req->cmd.opcode); return NVME_INVALID_OPCODE | NVME_DNR; } =20 - status =3D nvme_ns_status(req->ns); - if (unlikely(status)) { - return status; + if (ns->status) { + return ns->status; } =20 + req->ns =3D ns; + switch (req->cmd.opcode) { case NVME_CMD_WRITE_ZEROES: return nvme_write_zeroes(n, req); --=20 2.31.1 From nobody Sat May 18 09:48:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.24; envelope-from=its@irrelevant.dk; helo=wout1-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen There is no need to look up the lba size and metadata size in the LBA Format structure everytime we want to use it. And we use it a lot. Cache the values in the NvmeNamespace and update them if the namespace is formatted. Signed-off-by: Klaus Jensen Reviewed-by: Keith Busch --- hw/block/nvme.h | 37 ++++------------------------------- hw/block/nvme-dif.c | 45 ++++++++++++++++++------------------------- hw/block/nvme-ns.c | 26 +++++++++++++------------ hw/block/nvme.c | 47 ++++++++++++++++++--------------------------- 4 files changed, 56 insertions(+), 99 deletions(-) diff --git a/hw/block/nvme.h b/hw/block/nvme.h index d9bee7e5a05c..dc065e57b509 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -109,6 +109,8 @@ typedef struct NvmeNamespace { int64_t size; int64_t mdata_offset; NvmeIdNs id_ns; + NvmeLBAF lbaf; + size_t lbasz; const uint32_t *iocs; uint8_t csi; uint16_t status; @@ -146,36 +148,14 @@ static inline uint32_t nvme_nsid(NvmeNamespace *ns) return 0; } =20 -static inline NvmeLBAF *nvme_ns_lbaf(NvmeNamespace *ns) -{ - NvmeIdNs *id_ns =3D &ns->id_ns; - return &id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(id_ns->flbas)]; -} - -static inline uint8_t nvme_ns_lbads(NvmeNamespace *ns) -{ - return nvme_ns_lbaf(ns)->ds; -} - -/* convert an LBA to the equivalent in bytes */ static inline size_t nvme_l2b(NvmeNamespace *ns, uint64_t lba) { - return lba << nvme_ns_lbads(ns); -} - -static inline size_t nvme_lsize(NvmeNamespace *ns) -{ - return 1 << nvme_ns_lbads(ns); -} - -static inline uint16_t nvme_msize(NvmeNamespace *ns) -{ - return nvme_ns_lbaf(ns)->ms; + return lba << ns->lbaf.ds; } =20 static inline size_t nvme_m2b(NvmeNamespace *ns, uint64_t lba) { - return nvme_msize(ns) * lba; + return ns->lbaf.ms * lba; } =20 static inline bool nvme_ns_ext(NvmeNamespace *ns) @@ -183,15 +163,6 @@ static inline bool nvme_ns_ext(NvmeNamespace *ns) return !!NVME_ID_NS_FLBAS_EXTENDED(ns->id_ns.flbas); } =20 -/* calculate the number of LBAs that the namespace can accomodate */ -static inline uint64_t nvme_ns_nlbas(NvmeNamespace *ns) -{ - if (nvme_msize(ns)) { - return ns->size / (nvme_lsize(ns) + nvme_msize(ns)); - } - return ns->size >> nvme_ns_lbads(ns); -} - static inline NvmeZoneState nvme_get_zone_state(NvmeZone *zone) { return zone->d.zs >> 4; diff --git a/hw/block/nvme-dif.c b/hw/block/nvme-dif.c index e269d275ebed..c72e43195abf 100644 --- a/hw/block/nvme-dif.c +++ b/hw/block/nvme-dif.c @@ -44,20 +44,18 @@ void nvme_dif_pract_generate_dif(NvmeNamespace *ns, uin= t8_t *buf, size_t len, uint32_t reftag) { uint8_t *end =3D buf + len; - size_t lsize =3D nvme_lsize(ns); - size_t msize =3D nvme_msize(ns); int16_t pil =3D 0; =20 if (!(ns->id_ns.dps & NVME_ID_NS_DPS_FIRST_EIGHT)) { - pil =3D nvme_msize(ns) - sizeof(NvmeDifTuple); + pil =3D ns->lbaf.ms - sizeof(NvmeDifTuple); } =20 - trace_pci_nvme_dif_pract_generate_dif(len, lsize, lsize + pil, apptag, - reftag); + trace_pci_nvme_dif_pract_generate_dif(len, ns->lbasz, ns->lbasz + pil, + apptag, reftag); =20 - for (; buf < end; buf +=3D lsize, mbuf +=3D msize) { + for (; buf < end; buf +=3D ns->lbasz, mbuf +=3D ns->lbaf.ms) { NvmeDifTuple *dif =3D (NvmeDifTuple *)(mbuf + pil); - uint16_t crc =3D crc_t10dif(0x0, buf, lsize); + uint16_t crc =3D crc_t10dif(0x0, buf, ns->lbasz); =20 if (pil) { crc =3D crc_t10dif(crc, mbuf, pil); @@ -98,7 +96,7 @@ static uint16_t nvme_dif_prchk(NvmeNamespace *ns, NvmeDif= Tuple *dif, } =20 if (ctrl & NVME_RW_PRINFO_PRCHK_GUARD) { - uint16_t crc =3D crc_t10dif(0x0, buf, nvme_lsize(ns)); + uint16_t crc =3D crc_t10dif(0x0, buf, ns->lbasz); =20 if (pil) { crc =3D crc_t10dif(crc, mbuf, pil); @@ -137,8 +135,6 @@ uint16_t nvme_dif_check(NvmeNamespace *ns, uint8_t *buf= , size_t len, uint16_t appmask, uint32_t reftag) { uint8_t *end =3D buf + len; - size_t lsize =3D nvme_lsize(ns); - size_t msize =3D nvme_msize(ns); int16_t pil =3D 0; uint16_t status; =20 @@ -148,12 +144,12 @@ uint16_t nvme_dif_check(NvmeNamespace *ns, uint8_t *b= uf, size_t len, } =20 if (!(ns->id_ns.dps & NVME_ID_NS_DPS_FIRST_EIGHT)) { - pil =3D nvme_msize(ns) - sizeof(NvmeDifTuple); + pil =3D ns->lbaf.ms - sizeof(NvmeDifTuple); } =20 - trace_pci_nvme_dif_check(NVME_RW_PRINFO(ctrl), lsize + pil); + trace_pci_nvme_dif_check(NVME_RW_PRINFO(ctrl), ns->lbasz + pil); =20 - for (; buf < end; buf +=3D lsize, mbuf +=3D msize) { + for (; buf < end; buf +=3D ns->lbasz, mbuf +=3D ns->lbaf.ms) { NvmeDifTuple *dif =3D (NvmeDifTuple *)(mbuf + pil); =20 status =3D nvme_dif_prchk(ns, dif, buf, mbuf, pil, ctrl, apptag, @@ -176,20 +172,18 @@ uint16_t nvme_dif_mangle_mdata(NvmeNamespace *ns, uin= t8_t *mbuf, size_t mlen, BlockBackend *blk =3D ns->blkconf.blk; BlockDriverState *bs =3D blk_bs(blk); =20 - size_t msize =3D nvme_msize(ns); - size_t lsize =3D nvme_lsize(ns); int64_t moffset =3D 0, offset =3D nvme_l2b(ns, slba); uint8_t *mbufp, *end; bool zeroed; int16_t pil =3D 0; - int64_t bytes =3D (mlen / msize) * lsize; + int64_t bytes =3D (mlen / ns->lbaf.ms) << ns->lbaf.ds; int64_t pnum =3D 0; =20 Error *err =3D NULL; =20 =20 if (!(ns->id_ns.dps & NVME_ID_NS_DPS_FIRST_EIGHT)) { - pil =3D nvme_msize(ns) - sizeof(NvmeDifTuple); + pil =3D ns->lbaf.ms - sizeof(NvmeDifTuple); } =20 do { @@ -211,15 +205,15 @@ uint16_t nvme_dif_mangle_mdata(NvmeNamespace *ns, uin= t8_t *mbuf, size_t mlen, =20 if (zeroed) { mbufp =3D mbuf + moffset; - mlen =3D (pnum / lsize) * msize; + mlen =3D (pnum >> ns->lbaf.ds) * ns->lbaf.ms; end =3D mbufp + mlen; =20 - for (; mbufp < end; mbufp +=3D msize) { + for (; mbufp < end; mbufp +=3D ns->lbaf.ms) { memset(mbufp + pil, 0xff, sizeof(NvmeDifTuple)); } } =20 - moffset +=3D (pnum / lsize) * msize; + moffset +=3D (pnum >> ns->lbaf.ds) * ns->lbaf.ms; offset +=3D pnum; } while (pnum !=3D bytes); =20 @@ -289,7 +283,7 @@ static void nvme_dif_rw_check_cb(void *opaque, int ret) goto out; } =20 - if (ctrl & NVME_RW_PRINFO_PRACT && nvme_msize(ns) =3D=3D 8) { + if (ctrl & NVME_RW_PRINFO_PRACT && ns->lbaf.ms =3D=3D 8) { goto out; } =20 @@ -393,8 +387,7 @@ uint16_t nvme_dif_rw(NvmeCtrl *n, NvmeRequest *req) =20 if (pract) { uint8_t *mbuf, *end; - size_t msize =3D nvme_msize(ns); - int16_t pil =3D msize - sizeof(NvmeDifTuple); + int16_t pil =3D ns->lbaf.ms - sizeof(NvmeDifTuple); =20 status =3D nvme_check_prinfo(ns, ctrl, slba, reftag); if (status) { @@ -415,7 +408,7 @@ uint16_t nvme_dif_rw(NvmeCtrl *n, NvmeRequest *req) pil =3D 0; } =20 - for (; mbuf < end; mbuf +=3D msize) { + for (; mbuf < end; mbuf +=3D ns->lbaf.ms) { NvmeDifTuple *dif =3D (NvmeDifTuple *)(mbuf + pil); =20 dif->apptag =3D cpu_to_be16(apptag); @@ -434,7 +427,7 @@ uint16_t nvme_dif_rw(NvmeCtrl *n, NvmeRequest *req) return NVME_NO_COMPLETE; } =20 - if (nvme_ns_ext(ns) && !(pract && nvme_msize(ns) =3D=3D 8)) { + if (nvme_ns_ext(ns) && !(pract && ns->lbaf.ms =3D=3D 8)) { mapped_len +=3D mlen; } =20 @@ -468,7 +461,7 @@ uint16_t nvme_dif_rw(NvmeCtrl *n, NvmeRequest *req) qemu_iovec_init(&ctx->mdata.iov, 1); qemu_iovec_add(&ctx->mdata.iov, ctx->mdata.bounce, mlen); =20 - if (!(pract && nvme_msize(ns) =3D=3D 8)) { + if (!(pract && ns->lbaf.ms =3D=3D 8)) { status =3D nvme_bounce_mdata(n, ctx->mdata.bounce, ctx->mdata.iov.= size, NVME_TX_DIRECTION_TO_DEVICE, req); if (status) { diff --git a/hw/block/nvme-ns.c b/hw/block/nvme-ns.c index 93aaf6de02af..b9369460b965 100644 --- a/hw/block/nvme-ns.c +++ b/hw/block/nvme-ns.c @@ -31,7 +31,10 @@ void nvme_ns_init_format(NvmeNamespace *ns) BlockDriverInfo bdi; int npdg, nlbas, ret; =20 - nlbas =3D nvme_ns_nlbas(ns); + ns->lbaf =3D id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(id_ns->flbas)]; + ns->lbasz =3D 1 << ns->lbaf.ds; + + nlbas =3D ns->size / (ns->lbasz + ns->lbaf.ms); =20 id_ns->nsze =3D cpu_to_le64(nlbas); =20 @@ -39,13 +42,13 @@ void nvme_ns_init_format(NvmeNamespace *ns) id_ns->ncap =3D id_ns->nsze; id_ns->nuse =3D id_ns->ncap; =20 - ns->mdata_offset =3D nvme_l2b(ns, nlbas); + ns->mdata_offset =3D (int64_t)nlbas << ns->lbaf.ds; =20 - npdg =3D ns->blkconf.discard_granularity / nvme_lsize(ns); + npdg =3D ns->blkconf.discard_granularity / ns->lbasz; =20 ret =3D bdrv_get_info(blk_bs(ns->blkconf.blk), &bdi); if (ret >=3D 0 && bdi.cluster_size > ns->blkconf.discard_granularity) { - npdg =3D bdi.cluster_size / nvme_lsize(ns); + npdg =3D bdi.cluster_size / ns->lbasz; } =20 id_ns->npda =3D id_ns->npdg =3D npdg - 1; @@ -163,7 +166,6 @@ static int nvme_ns_init_blk(NvmeNamespace *ns, Error **= errp) static int nvme_ns_zoned_check_calc_geometry(NvmeNamespace *ns, Error **er= rp) { uint64_t zone_size, zone_cap; - uint32_t lbasz =3D nvme_lsize(ns); =20 /* Make sure that the values of ZNS properties are sane */ if (ns->params.zone_size_bs) { @@ -181,14 +183,14 @@ static int nvme_ns_zoned_check_calc_geometry(NvmeName= space *ns, Error **errp) "zone size %"PRIu64"B", zone_cap, zone_size); return -1; } - if (zone_size < lbasz) { + if (zone_size < ns->lbasz) { error_setg(errp, "zone size %"PRIu64"B too small, " - "must be at least %"PRIu32"B", zone_size, lbasz); + "must be at least %zuB", zone_size, ns->lbasz); return -1; } - if (zone_cap < lbasz) { + if (zone_cap < ns->lbasz) { error_setg(errp, "zone capacity %"PRIu64"B too small, " - "must be at least %"PRIu32"B", zone_cap, lbasz); + "must be at least %zuB", zone_cap, ns->lbasz); return -1; } =20 @@ -196,9 +198,9 @@ static int nvme_ns_zoned_check_calc_geometry(NvmeNamesp= ace *ns, Error **errp) * Save the main zone geometry values to avoid * calculating them later again. */ - ns->zone_size =3D zone_size / lbasz; - ns->zone_capacity =3D zone_cap / lbasz; - ns->num_zones =3D nvme_ns_nlbas(ns) / ns->zone_size; + ns->zone_size =3D zone_size / ns->lbasz; + ns->zone_capacity =3D zone_cap / ns->lbasz; + ns->num_zones =3D le64_to_cpu(ns->id_ns.nsze) / ns->zone_size; =20 /* Do a few more sanity checks of ZNS properties */ if (!ns->num_zones) { diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 710af6a7147c..9153d5d91363 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -517,9 +517,7 @@ static void nvme_sg_split(NvmeSg *sg, NvmeNamespace *ns= , NvmeSg *data, NvmeSg *mdata) { NvmeSg *dst =3D data; - size_t size =3D nvme_lsize(ns); - size_t msize =3D nvme_msize(ns); - uint32_t trans_len, count =3D size; + uint32_t trans_len, count =3D ns->lbasz; uint64_t offset =3D 0; bool dma =3D sg->flags & NVME_SG_DMA; size_t sge_len; @@ -551,7 +549,7 @@ static void nvme_sg_split(NvmeSg *sg, NvmeNamespace *ns= , NvmeSg *data, =20 if (count =3D=3D 0) { dst =3D (dst =3D=3D data) ? mdata : data; - count =3D (dst =3D=3D data) ? size : msize; + count =3D (dst =3D=3D data) ? ns->lbasz : ns->lbaf.ms; } =20 if (sge_len =3D=3D offset) { @@ -1010,7 +1008,7 @@ static uint16_t nvme_map_data(NvmeCtrl *n, uint32_t n= lb, NvmeRequest *req) uint16_t status; =20 if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps) && - (ctrl & NVME_RW_PRINFO_PRACT && nvme_msize(ns) =3D=3D 8)) { + (ctrl & NVME_RW_PRINFO_PRACT && ns->lbaf.ms =3D=3D 8)) { goto out; } =20 @@ -1193,12 +1191,9 @@ uint16_t nvme_bounce_data(NvmeCtrl *n, uint8_t *ptr,= uint32_t len, uint16_t ctrl =3D le16_to_cpu(rw->control); =20 if (nvme_ns_ext(ns) && - !(ctrl & NVME_RW_PRINFO_PRACT && nvme_msize(ns) =3D=3D 8)) { - size_t lsize =3D nvme_lsize(ns); - size_t msize =3D nvme_msize(ns); - - return nvme_tx_interleaved(n, &req->sg, ptr, len, lsize, msize, 0, - dir); + !(ctrl & NVME_RW_PRINFO_PRACT && ns->lbaf.ms =3D=3D 8)) { + return nvme_tx_interleaved(n, &req->sg, ptr, len, ns->lbasz, + ns->lbaf.ms, 0, dir); } =20 return nvme_tx(n, &req->sg, ptr, len, dir); @@ -1211,11 +1206,8 @@ uint16_t nvme_bounce_mdata(NvmeCtrl *n, uint8_t *ptr= , uint32_t len, uint16_t status; =20 if (nvme_ns_ext(ns)) { - size_t lsize =3D nvme_lsize(ns); - size_t msize =3D nvme_msize(ns); - - return nvme_tx_interleaved(n, &req->sg, ptr, len, msize, lsize, ls= ize, - dir); + return nvme_tx_interleaved(n, &req->sg, ptr, len, ns->lbaf.ms, + ns->lbasz, ns->lbasz, dir); } =20 nvme_sg_unmap(&req->sg); @@ -1843,7 +1835,7 @@ static void nvme_rw_cb(void *opaque, int ret) goto out; } =20 - if (nvme_msize(ns)) { + if (ns->lbaf.ms) { NvmeRwCmd *rw =3D (NvmeRwCmd *)&req->cmd; uint64_t slba =3D le64_to_cpu(rw->slba); uint32_t nlb =3D (uint32_t)le16_to_cpu(rw->nlb) + 1; @@ -2115,7 +2107,7 @@ static void nvme_aio_zone_reset_cb(void *opaque, int = ret) goto out; } =20 - if (nvme_msize(ns)) { + if (ns->lbaf.ms) { int64_t offset =3D ns->mdata_offset + nvme_m2b(ns, zone->d.zslba); =20 blk_aio_pwrite_zeroes(ns->blkconf.blk, offset, @@ -2184,7 +2176,7 @@ static void nvme_copy_cb(void *opaque, int ret) goto out; } =20 - if (nvme_msize(ns)) { + if (ns->lbaf.ms) { NvmeCopyCmd *copy =3D (NvmeCopyCmd *)&req->cmd; uint64_t sdlba =3D le64_to_cpu(copy->sdlba); int64_t offset =3D ns->mdata_offset + nvme_m2b(ns, sdlba); @@ -2406,7 +2398,6 @@ static void nvme_compare_mdata_cb(void *opaque, int r= et) uint8_t *bufp; uint8_t *mbufp =3D ctx->mdata.bounce; uint8_t *end =3D mbufp + ctx->mdata.iov.size; - size_t msize =3D nvme_msize(ns); int16_t pil =3D 0; =20 status =3D nvme_dif_check(ns, ctx->data.bounce, ctx->data.iov.size, @@ -2422,11 +2413,11 @@ static void nvme_compare_mdata_cb(void *opaque, int= ret) * tuple. */ if (!(ns->id_ns.dps & NVME_ID_NS_DPS_FIRST_EIGHT)) { - pil =3D nvme_msize(ns) - sizeof(NvmeDifTuple); + pil =3D ns->lbaf.ms - sizeof(NvmeDifTuple); } =20 - for (bufp =3D buf; mbufp < end; bufp +=3D msize, mbufp +=3D msize)= { - if (memcmp(bufp + pil, mbufp + pil, msize - pil)) { + for (bufp =3D buf; mbufp < end; bufp +=3D ns->lbaf.ms, mbufp +=3D = ns->lbaf.ms) { + if (memcmp(bufp + pil, mbufp + pil, ns->lbaf.ms - pil)) { req->status =3D NVME_CMP_FAILURE; goto out; } @@ -2489,7 +2480,7 @@ static void nvme_compare_data_cb(void *opaque, int re= t) goto out; } =20 - if (nvme_msize(ns)) { + if (ns->lbaf.ms) { NvmeRwCmd *rw =3D (NvmeRwCmd *)&req->cmd; uint64_t slba =3D le64_to_cpu(rw->slba); uint32_t nlb =3D le16_to_cpu(rw->nlb) + 1; @@ -2733,7 +2724,7 @@ static uint16_t nvme_copy(NvmeCtrl *n, NvmeRequest *r= eq) } =20 bounce =3D bouncep =3D g_malloc(nvme_l2b(ns, nlb)); - if (nvme_msize(ns)) { + if (ns->lbaf.ms) { mbounce =3D mbouncep =3D g_malloc(nvme_m2b(ns, nlb)); } =20 @@ -2769,7 +2760,7 @@ static uint16_t nvme_copy(NvmeCtrl *n, NvmeRequest *r= eq) =20 bouncep +=3D len; =20 - if (nvme_msize(ns)) { + if (ns->lbaf.ms) { len =3D nvme_m2b(ns, nlb); offset =3D ns->mdata_offset + nvme_m2b(ns, slba); =20 @@ -2939,7 +2930,7 @@ static uint16_t nvme_read(NvmeCtrl *n, NvmeRequest *r= eq) if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) { bool pract =3D ctrl & NVME_RW_PRINFO_PRACT; =20 - if (pract && nvme_msize(ns) =3D=3D 8) { + if (pract && ns->lbaf.ms =3D=3D 8) { mapped_size =3D data_size; } } @@ -3015,7 +3006,7 @@ static uint16_t nvme_do_write(NvmeCtrl *n, NvmeReques= t *req, bool append, if (NVME_ID_NS_DPS_TYPE(ns->id_ns.dps)) { bool pract =3D ctrl & NVME_RW_PRINFO_PRACT; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=66.111.4.28; envelope-from=its@irrelevant.dk; helo=out4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Add an nvme_moff() helper. Signed-off-by: Klaus Jensen Reviewed-by: Keith Busch --- hw/block/nvme.h | 7 ++++++- hw/block/nvme-dif.c | 4 ++-- hw/block/nvme-ns.c | 2 +- hw/block/nvme.c | 12 ++++++------ 4 files changed, 15 insertions(+), 10 deletions(-) diff --git a/hw/block/nvme.h b/hw/block/nvme.h index dc065e57b509..9349d1c33ad7 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -107,7 +107,7 @@ typedef struct NvmeNamespace { BlockConf blkconf; int32_t bootindex; int64_t size; - int64_t mdata_offset; + int64_t moff; NvmeIdNs id_ns; NvmeLBAF lbaf; size_t lbasz; @@ -158,6 +158,11 @@ static inline size_t nvme_m2b(NvmeNamespace *ns, uint6= 4_t lba) return ns->lbaf.ms * lba; } =20 +static inline int64_t nvme_moff(NvmeNamespace *ns, uint64_t lba) +{ + return ns->moff + nvme_m2b(ns, lba); +} + static inline bool nvme_ns_ext(NvmeNamespace *ns) { return !!NVME_ID_NS_FLBAS_EXTENDED(ns->id_ns.flbas); diff --git a/hw/block/nvme-dif.c b/hw/block/nvme-dif.c index c72e43195abf..88efcbe9bd60 100644 --- a/hw/block/nvme-dif.c +++ b/hw/block/nvme-dif.c @@ -306,7 +306,7 @@ static void nvme_dif_rw_mdata_in_cb(void *opaque, int r= et) uint64_t slba =3D le64_to_cpu(rw->slba); uint32_t nlb =3D le16_to_cpu(rw->nlb) + 1; size_t mlen =3D nvme_m2b(ns, nlb); - uint64_t offset =3D ns->mdata_offset + nvme_m2b(ns, slba); + uint64_t offset =3D nvme_moff(ns, slba); BlockBackend *blk =3D ns->blkconf.blk; =20 trace_pci_nvme_dif_rw_mdata_in_cb(nvme_cid(req), blk_name(blk)); @@ -335,7 +335,7 @@ static void nvme_dif_rw_mdata_out_cb(void *opaque, int = ret) NvmeNamespace *ns =3D req->ns; NvmeRwCmd *rw =3D (NvmeRwCmd *)&req->cmd; uint64_t slba =3D le64_to_cpu(rw->slba); - uint64_t offset =3D ns->mdata_offset + nvme_m2b(ns, slba); + uint64_t offset =3D nvme_moff(ns, slba); BlockBackend *blk =3D ns->blkconf.blk; =20 trace_pci_nvme_dif_rw_mdata_out_cb(nvme_cid(req), blk_name(blk)); diff --git a/hw/block/nvme-ns.c b/hw/block/nvme-ns.c index b9369460b965..b25838ac4fd4 100644 --- a/hw/block/nvme-ns.c +++ b/hw/block/nvme-ns.c @@ -42,7 +42,7 @@ void nvme_ns_init_format(NvmeNamespace *ns) id_ns->ncap =3D id_ns->nsze; id_ns->nuse =3D id_ns->ncap; =20 - ns->mdata_offset =3D (int64_t)nlbas << ns->lbaf.ds; + ns->moff =3D (int64_t)nlbas << ns->lbaf.ds; =20 npdg =3D ns->blkconf.discard_granularity / ns->lbasz; =20 diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 9153d5d91363..1db9a603f5c4 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1839,7 +1839,7 @@ static void nvme_rw_cb(void *opaque, int ret) NvmeRwCmd *rw =3D (NvmeRwCmd *)&req->cmd; uint64_t slba =3D le64_to_cpu(rw->slba); uint32_t nlb =3D (uint32_t)le16_to_cpu(rw->nlb) + 1; - uint64_t offset =3D ns->mdata_offset + nvme_m2b(ns, slba); + uint64_t offset =3D nvme_moff(ns, slba); =20 if (req->cmd.opcode =3D=3D NVME_CMD_WRITE_ZEROES) { size_t mlen =3D nvme_m2b(ns, nlb); @@ -2005,7 +2005,7 @@ static void nvme_verify_mdata_in_cb(void *opaque, int= ret) uint64_t slba =3D le64_to_cpu(rw->slba); uint32_t nlb =3D le16_to_cpu(rw->nlb) + 1; size_t mlen =3D nvme_m2b(ns, nlb); - uint64_t offset =3D ns->mdata_offset + nvme_m2b(ns, slba); + uint64_t offset =3D nvme_moff(ns, slba); BlockBackend *blk =3D ns->blkconf.blk; =20 trace_pci_nvme_verify_mdata_in_cb(nvme_cid(req), blk_name(blk)); @@ -2108,7 +2108,7 @@ static void nvme_aio_zone_reset_cb(void *opaque, int = ret) } =20 if (ns->lbaf.ms) { - int64_t offset =3D ns->mdata_offset + nvme_m2b(ns, zone->d.zslba); + int64_t offset =3D nvme_moff(ns, zone->d.zslba); =20 blk_aio_pwrite_zeroes(ns->blkconf.blk, offset, nvme_m2b(ns, ns->zone_size), BDRV_REQ_MAY_UN= MAP, @@ -2179,7 +2179,7 @@ static void nvme_copy_cb(void *opaque, int ret) if (ns->lbaf.ms) { NvmeCopyCmd *copy =3D (NvmeCopyCmd *)&req->cmd; uint64_t sdlba =3D le64_to_cpu(copy->sdlba); - int64_t offset =3D ns->mdata_offset + nvme_m2b(ns, sdlba); + int64_t offset =3D nvme_moff(ns, sdlba); =20 qemu_iovec_reset(&req->sg.iov); qemu_iovec_add(&req->sg.iov, ctx->mbounce, nvme_m2b(ns, ctx->nlb)); @@ -2485,7 +2485,7 @@ static void nvme_compare_data_cb(void *opaque, int re= t) uint64_t slba =3D le64_to_cpu(rw->slba); uint32_t nlb =3D le16_to_cpu(rw->nlb) + 1; size_t mlen =3D nvme_m2b(ns, nlb); - uint64_t offset =3D ns->mdata_offset + nvme_m2b(ns, slba); + uint64_t offset =3D nvme_moff(ns, slba); =20 ctx->mdata.bounce =3D g_malloc(mlen); =20 @@ -2762,7 +2762,7 @@ static uint16_t nvme_copy(NvmeCtrl *n, NvmeRequest *r= eq) =20 if (ns->lbaf.ms) { len =3D nvme_m2b(ns, nlb); - offset =3D ns->mdata_offset + nvme_m2b(ns, slba); + offset =3D nvme_moff(ns, slba); =20 in_ctx =3D g_new(struct nvme_copy_in_ctx, 1); in_ctx->req =3D req; --=20 2.31.1 From nobody Sat May 18 09:48:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1621244477; cv=none; d=zohomail.com; s=zohoarc; b=aI7oS5WA0ebziw1IHZfF5yxVqcxhhJT3QSJ5iSN6zzdkESuG6RCkfjPh7Bt0+26QZEab/KmhmJV3Sgm6Rz7+J+y3H7gmiGQ3oJsKbSai9ywv3HKAvMzHl4ihEFH6xlZDkvYPeyTuMvGxNWJHlrqKd9/s8kOCN7kdRFi3PCyGjPQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621244477; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.24; envelope-from=its@irrelevant.dk; helo=wout1-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Streamline namespace array indexing such that both the subsystem and controller namespaces arrays are 1-indexed. Signed-off-by: Klaus Jensen Reviewed-by: Keith Busch --- hw/block/nvme.h | 4 ++-- hw/block/nvme.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 9349d1c33ad7..ac3f0a886735 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -438,7 +438,7 @@ typedef struct NvmeCtrl { NvmeSubsystem *subsys; =20 NvmeNamespace namespace; - NvmeNamespace *namespaces[NVME_MAX_NAMESPACES]; + NvmeNamespace *namespaces[NVME_MAX_NAMESPACES + 1]; NvmeSQueue **sq; NvmeCQueue **cq; NvmeSQueue admin_sq; @@ -460,7 +460,7 @@ static inline NvmeNamespace *nvme_ns(NvmeCtrl *n, uint3= 2_t nsid) return NULL; } =20 - return n->namespaces[nsid - 1]; + return n->namespaces[nsid]; } =20 static inline NvmeCQueue *nvme_cq(NvmeRequest *req) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 1db9a603f5c4..baf7b6714544 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -4990,7 +4990,7 @@ static uint16_t nvme_ns_attachment(NvmeCtrl *n, NvmeR= equest *req) return NVME_NS_NOT_ATTACHED | NVME_DNR; } =20 - ctrl->namespaces[nsid - 1] =3D NULL; + ctrl->namespaces[nsid] =3D NULL; ns->attached--; =20 nvme_update_dmrsl(ctrl); @@ -6163,7 +6163,7 @@ void nvme_attach_ns(NvmeCtrl *n, NvmeNamespace *ns) uint32_t nsid =3D ns->params.nsid; assert(nsid && nsid <=3D NVME_MAX_NAMESPACES); =20 - n->namespaces[nsid - 1] =3D ns; + n->namespaces[nsid] =3D ns; ns->attached++; =20 n->dmrsl =3D MIN_NON_ZERO(n->dmrsl, --=20 2.31.1 From nobody Sat May 18 09:48:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1621246393; cv=none; d=zohomail.com; s=zohoarc; b=Aue2uk2d5Yolr8kzGUZK4AG6Lm07u/pjv8nKk/ulRVK1I52SWDdGRWS3oxPiHvZQIH6VfRtUW2LUIPF7Tkjz1yk8H6zEKcDuoC16DZz9/besc0xSBK2o9Gn7hXdXBdpVq4JgRfNgicRxSWCBj009YjYt10THEjGdMGfmvMLYOoQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.24; envelope-from=its@irrelevant.dk; helo=wout1-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen The NvmeCtrl num_namespaces member is just an indirection for the NVME_MAX_NAMESPACES constant. Remove the indirection. Signed-off-by: Klaus Jensen Reviewed-by: Keith Busch --- hw/block/nvme.h | 1 - hw/block/nvme.c | 30 +++++++++++++++--------------- 2 files changed, 15 insertions(+), 16 deletions(-) diff --git a/hw/block/nvme.h b/hw/block/nvme.h index ac3f0a886735..fb028d81d16f 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -401,7 +401,6 @@ typedef struct NvmeCtrl { uint16_t cqe_size; uint16_t sqe_size; uint32_t reg_size; - uint32_t num_namespaces; uint32_t max_q_ents; uint8_t outstanding_aers; uint32_t irq_status; diff --git a/hw/block/nvme.c b/hw/block/nvme.c index baf7b6714544..0bcaf7192f99 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -393,7 +393,8 @@ static int nvme_addr_write(NvmeCtrl *n, hwaddr addr, vo= id *buf, int size) =20 static bool nvme_nsid_valid(NvmeCtrl *n, uint32_t nsid) { - return nsid && (nsid =3D=3D NVME_NSID_BROADCAST || nsid <=3D n->num_na= mespaces); + return nsid && + (nsid =3D=3D NVME_NSID_BROADCAST || nsid <=3D NVME_MAX_NAMESPACES); } =20 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid) @@ -2882,7 +2883,7 @@ static uint16_t nvme_flush(NvmeCtrl *n, NvmeRequest *= req) /* 1-initialize; see comment in nvme_dsm */ *num_flushes =3D 1; =20 - for (int i =3D 1; i <=3D n->num_namespaces; i++) { + for (int i =3D 1; i <=3D NVME_MAX_NAMESPACES; i++) { ns =3D nvme_ns(n, i); if (!ns) { continue; @@ -3850,7 +3851,7 @@ static uint16_t nvme_smart_info(NvmeCtrl *n, uint8_t = rae, uint32_t buf_len, } else { int i; =20 - for (i =3D 1; i <=3D n->num_namespaces; i++) { + for (i =3D 1; i <=3D NVME_MAX_NAMESPACES; i++) { ns =3D nvme_ns(n, i); if (!ns) { continue; @@ -4347,7 +4348,7 @@ static uint16_t nvme_identify_nslist(NvmeCtrl *n, Nvm= eRequest *req, return NVME_INVALID_NSID | NVME_DNR; } =20 - for (i =3D 1; i <=3D n->num_namespaces; i++) { + for (i =3D 1; i <=3D NVME_MAX_NAMESPACES; i++) { ns =3D nvme_ns(n, i); if (!ns) { if (!active) { @@ -4395,7 +4396,7 @@ static uint16_t nvme_identify_nslist_csi(NvmeCtrl *n,= NvmeRequest *req, return NVME_INVALID_FIELD | NVME_DNR; } =20 - for (i =3D 1; i <=3D n->num_namespaces; i++) { + for (i =3D 1; i <=3D NVME_MAX_NAMESPACES; i++) { ns =3D nvme_ns(n, i); if (!ns) { if (!active) { @@ -4661,7 +4662,7 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeReq= uest *req) goto out; case NVME_VOLATILE_WRITE_CACHE: result =3D 0; - for (i =3D 1; i <=3D n->num_namespaces; i++) { + for (i =3D 1; i <=3D NVME_MAX_NAMESPACES; i++) { ns =3D nvme_ns(n, i); if (!ns) { continue; @@ -4808,7 +4809,7 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeReq= uest *req) break; case NVME_ERROR_RECOVERY: if (nsid =3D=3D NVME_NSID_BROADCAST) { - for (i =3D 1; i <=3D n->num_namespaces; i++) { + for (i =3D 1; i <=3D NVME_MAX_NAMESPACES; i++) { ns =3D nvme_ns(n, i); =20 if (!ns) { @@ -4829,7 +4830,7 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeReq= uest *req) } break; case NVME_VOLATILE_WRITE_CACHE: - for (i =3D 1; i <=3D n->num_namespaces; i++) { + for (i =3D 1; i <=3D NVME_MAX_NAMESPACES; i++) { ns =3D nvme_ns(n, i); if (!ns) { continue; @@ -5122,7 +5123,7 @@ static uint16_t nvme_format(NvmeCtrl *n, NvmeRequest = *req) req->status =3D status; } } else { - for (i =3D 1; i <=3D n->num_namespaces; i++) { + for (i =3D 1; i <=3D NVME_MAX_NAMESPACES; i++) { ns =3D nvme_ns(n, i); if (!ns) { continue; @@ -5233,7 +5234,7 @@ static void nvme_ctrl_reset(NvmeCtrl *n) NvmeNamespace *ns; int i; =20 - for (i =3D 1; i <=3D n->num_namespaces; i++) { + for (i =3D 1; i <=3D NVME_MAX_NAMESPACES; i++) { ns =3D nvme_ns(n, i); if (!ns) { continue; @@ -5275,7 +5276,7 @@ static void nvme_ctrl_shutdown(NvmeCtrl *n) memory_region_msync(&n->pmr.dev->mr, 0, n->pmr.dev->size); } =20 - for (i =3D 1; i <=3D n->num_namespaces; i++) { + for (i =3D 1; i <=3D NVME_MAX_NAMESPACES; i++) { ns =3D nvme_ns(n, i); if (!ns) { continue; @@ -5290,7 +5291,7 @@ static void nvme_select_iocs(NvmeCtrl *n) NvmeNamespace *ns; int i; =20 - for (i =3D 1; i <=3D n->num_namespaces; i++) { + for (i =3D 1; i <=3D NVME_MAX_NAMESPACES; i++) { ns =3D nvme_ns(n, i); if (!ns) { continue; @@ -5917,7 +5918,6 @@ static void nvme_check_constraints(NvmeCtrl *n, Error= **errp) =20 static void nvme_init_state(NvmeCtrl *n) { - n->num_namespaces =3D NVME_MAX_NAMESPACES; /* add one to max_ioqpairs to account for the admin queue pair */ n->reg_size =3D pow2ceil(sizeof(NvmeBar) + 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE= ); @@ -6098,7 +6098,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pc= i_dev) =20 id->sqes =3D (0x6 << 4) | 0x6; id->cqes =3D (0x4 << 4) | 0x4; - id->nn =3D cpu_to_le32(n->num_namespaces); + id->nn =3D cpu_to_le32(NVME_MAX_NAMESPACES); id->oncs =3D cpu_to_le16(NVME_ONCS_WRITE_ZEROES | NVME_ONCS_TIMESTAMP | NVME_ONCS_FEATURES | NVME_ONCS_DSM | NVME_ONCS_COMPARE | NVME_ONCS_COPY); @@ -6217,7 +6217,7 @@ static void nvme_exit(PCIDevice *pci_dev) =20 nvme_ctrl_reset(n); =20 - for (i =3D 1; i <=3D n->num_namespaces; i++) { + for (i =3D 1; i <=3D NVME_MAX_NAMESPACES; i++) { ns =3D nvme_ns(n, i); if (!ns) { continue; --=20 2.31.1 From nobody Sat May 18 09:48:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Mon, 17 May 2021 05:18:36 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irrelevant.dk; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=7OmYgoJTlIydJ GN2Pi3EGX9pMYR+k1maUIL5Jxiw1fc=; b=jpuwCCcvWDDzKs429J+80ezvmV35W QKaZob3y0ygw8uEV+LMtcHEsM6T/YF3e6bsNN6ayDLhWblyjqM5OvEttBg3IDz/T kyPoRvjGYivJEDoYXJRxhbMt6VMlXQZpDF7cHqLDl+d9MePrH43dXMx8d6DpIXfg MngFI5cU8AuKmQi5ls5fSzv2BUbcUTTMXGfrEctnZTnrxGSw2G0Sqohrqoz8+NTp NtdMTWJ5OD6C2yPFega4SAftlc5CTUW16TY8BcoHdWZLzhETaajkdWAYbJfGe+05 SUCX7QHrQT0q1jhqXoAjoEIRv8jq1qe+NsPzUKsuO5UUtC6naH0Qv/2aw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=7OmYgoJTlIydJGN2Pi3EGX9pMYR+k1maUIL5Jxiw1fc=; b=QxPjayUe jat8TZJ9jM4eg0iVjgbu2VR1wFfUnvhBzGhOH8ryr/Elz+vJfbjaoXT/ytYujKCf 7801VNwZv4NY/QSsHBrpYO3HjrLTaB2pRUHqQNpbPR2OADb6c9LOFxK4UY8M4gR7 0YmLVxRTxog4QEYG9Zp7xP0+3wv3uXgIMBvqSzr0+ZnGxsMcjYeYxY/RJtYL4OrG tRULq8qdE+HKsHC0oVz2HKCO4VGvKBqNHIbwQP39fvRQERRzkPgeKu3UPpmcNKKB F+wO4yhVjC/0J+vdwy7twKjvQapS8IVDYZZaeq8iHdItQQslcJcscmSVtL3ybfia 1JNRXq1w5fMZtA== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduledrvdeihedgudegucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefmlhgruhhs ucflvghnshgvnhcuoehithhssehirhhrvghlvghvrghnthdrughkqeenucggtffrrghtth gvrhhnpeeuleetgeeiuefhgfekfefgveejiefgteekiedtgfdtieefhfdthfefueffvefg keenucfkphepkedtrdduieejrdelkedrudeltdenucevlhhushhtvghrufhiiigvpeegne curfgrrhgrmhepmhgrihhlfhhrohhmpehithhssehirhhrvghlvghvrghnthdrughk X-ME-Proxy: From: Klaus Jensen To: Peter Maydell , qemu-devel@nongnu.org Subject: [PULL 18/20] hw/block/nvme: remove irrelevant zone resource checks Date: Mon, 17 May 2021 11:17:35 +0200 Message-Id: <20210517091737.841787-19-its@irrelevant.dk> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517091737.841787-1-its@irrelevant.dk> References: <20210517091737.841787-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.24; envelope-from=its@irrelevant.dk; helo=wout1-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen It is not an error to report more active/open zones supported than the number of zones in the namespace. Signed-off-by: Klaus Jensen Reviewed-by: Keith Busch --- hw/block/nvme-ns.c | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/hw/block/nvme-ns.c b/hw/block/nvme-ns.c index b25838ac4fd4..008deb5e87d1 100644 --- a/hw/block/nvme-ns.c +++ b/hw/block/nvme-ns.c @@ -210,19 +210,6 @@ static int nvme_ns_zoned_check_calc_geometry(NvmeNames= pace *ns, Error **errp) return -1; } =20 - if (ns->params.max_open_zones > ns->num_zones) { - error_setg(errp, - "max_open_zones value %u exceeds the number of zones %u= ", - ns->params.max_open_zones, ns->num_zones); - return -1; - } - if (ns->params.max_active_zones > ns->num_zones) { - error_setg(errp, - "max_active_zones value %u exceeds the number of zones = %u", - ns->params.max_active_zones, ns->num_zones); - return -1; - } - if (ns->params.max_active_zones) { if (ns->params.max_open_zones > ns->params.max_active_zones) { error_setg(errp, "max_open_zones (%u) exceeds max_active_zones= (%u)", --=20 2.31.1 From nobody Sat May 18 09:48:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 17 May 2021 05:18:39 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irrelevant.dk; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm3; bh=OjjOCTGGyGxca i3HzvKQum9is7s3hqHrEO3Us4Ph/bc=; b=ZsFgvcJJsf0spVLVC72JzbtlVklxm vDMXvbHw5rl2PCJdqvUdq4ytg9WWp+ceb+7lBBhkLp20dSjevZMUTHQSi+h004oi dFrOfEQ+AHwrWvWDhS0qQj7rrLiiFUtppCuedo/OuaGEeLlczoWE48ADyssvE12K qvn6HqVravLPzurYqb8V1D8iI4lxYVNA8DyP13y7s0MpVOQ4Gnj77H+l4RXuJ6X0 pI2HAPia12Yb0jJt0MBizfL9fH09PJn8eFUc6CmBbEB8wKx0F0G31fwpIrB5eojr 9iynBahivBHHkB44fxCBtiBxq9+EL+068g6vAlc/QzV+Vy5TmteatKSbQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; bh=OjjOCTGGyGxcai3HzvKQum9is7s3hqHrEO3Us4Ph/bc=; b=W2KdLe1o DI6vk17KN62Egr7QBUQjMptE51/vil8sd75tmDb1n4PzZow5Kl+V1BkF4nq82RPs hYQQ+/LXPqR0q717YxYFxDEPdXairV992C+fFci51N1WWJFRd7LPy9L/QVnJ+pg6 /kPznoP7vFQlqbJEd4PdgFnTR37jkC+gBwUQLVC7WdGmIvYgl4Nd31vrhF0ZKHqC RcQ48VPHubucDO6ScVl1r0gxeVfUAf+6BH/BVffNSmNt+kc3Y8Uan3Xt6TlzmcuE eF7nYcRuU+WQhOvK/SgoJmdz/1dhpC3iMQImMnOqsVpoSf1Zrz76bSb+i1spawPf BG5qpt909oq03g== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduledrvdeihedgudegucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefmlhgruhhs ucflvghnshgvnhcuoehithhssehirhhrvghlvghvrghnthdrughkqeenucggtffrrghtth gvrhhnpeeuleetgeeiuefhgfekfefgveejiefgteekiedtgfdtieefhfdthfefueffvefg keenucfkphepkedtrdduieejrdelkedrudeltdenucevlhhushhtvghrufhiiigvpedune curfgrrhgrmhepmhgrihhlfhhrohhmpehithhssehirhhrvghlvghvrghnthdrughk X-ME-Proxy: From: Klaus Jensen To: Peter Maydell , qemu-devel@nongnu.org Subject: [PULL 19/20] hw/block/nvme: move zoned constraints checks Date: Mon, 17 May 2021 11:17:36 +0200 Message-Id: <20210517091737.841787-20-its@irrelevant.dk> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517091737.841787-1-its@irrelevant.dk> References: <20210517091737.841787-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=66.111.4.28; envelope-from=its@irrelevant.dk; helo=out4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Validation of the max_active and max_open zoned parameters are independent of any other state, so move them to the early nvme_ns_check_constraints parameter checks. Signed-off-by: Klaus Jensen Reviewed-by: Keith Busch --- hw/block/nvme-ns.c | 52 +++++++++++++++++++++++++--------------------- 1 file changed, 28 insertions(+), 24 deletions(-) diff --git a/hw/block/nvme-ns.c b/hw/block/nvme-ns.c index 008deb5e87d1..992e5a13f538 100644 --- a/hw/block/nvme-ns.c +++ b/hw/block/nvme-ns.c @@ -210,30 +210,6 @@ static int nvme_ns_zoned_check_calc_geometry(NvmeNames= pace *ns, Error **errp) return -1; } =20 - if (ns->params.max_active_zones) { - if (ns->params.max_open_zones > ns->params.max_active_zones) { - error_setg(errp, "max_open_zones (%u) exceeds max_active_zones= (%u)", - ns->params.max_open_zones, ns->params.max_active_zo= nes); - return -1; - } - - if (!ns->params.max_open_zones) { - ns->params.max_open_zones =3D ns->params.max_active_zones; - } - } - - if (ns->params.zd_extension_size) { - if (ns->params.zd_extension_size & 0x3f) { - error_setg(errp, - "zone descriptor extension size must be a multiple of 64B"= ); - return -1; - } - if ((ns->params.zd_extension_size >> 6) > 0xff) { - error_setg(errp, "zone descriptor extension size is too large"= ); - return -1; - } - } - return 0; } =20 @@ -403,6 +379,34 @@ static int nvme_ns_check_constraints(NvmeCtrl *n, Nvme= Namespace *ns, } } =20 + if (ns->params.zoned) { + if (ns->params.max_active_zones) { + if (ns->params.max_open_zones > ns->params.max_active_zones) { + error_setg(errp, "max_open_zones (%u) exceeds " + "max_active_zones (%u)", ns->params.max_open_zo= nes, + ns->params.max_active_zones); + return -1; + } + + if (!ns->params.max_open_zones) { + ns->params.max_open_zones =3D ns->params.max_active_zones; + } + } + + if (ns->params.zd_extension_size) { + if (ns->params.zd_extension_size & 0x3f) { + error_setg(errp, "zone descriptor extension size must be a= " + "multiple of 64B"); + return -1; + } + if ((ns->params.zd_extension_size >> 6) > 0xff) { + error_setg(errp, + "zone descriptor extension size is too large"); + return -1; + } + } + } + return 0; } =20 --=20 2.31.1 From nobody Sat May 18 09:48:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Mon, 17 May 2021 05:18:42 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=irrelevant.dk; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-type:content-transfer-encoding; s=fm3; bh= vIdqWNwfpspIlxuEcLsiOuEZ3kAAeweEOeQZhepWk04=; b=L/xFeXqA2n7dQNvE vdF/LiLNCgRbiF6FV2bNqGJUQd6SAnd0vEz0nD+g3SkBlQpouzVRKqoxAYnYeuR1 EAA6vdSFHF1GJetd0AHJxZwdue956vIqt7n7OSrstLDPwIP+SrdvPJNIJhlJmwB3 zMPTrP2cgjZKzt3lLjHm7emF+Umqe+t86oSN0M+AZnFHd9jDOGaQUHORNtylsLKU EWjJMvYQhS6gjiqeKi4elebgbpJ43pKH/owtSIHqGmW80SF1MenbsLR0z7jwR1Ff SvyLZ8zoyg7b1HPOmPSLC2uIsVCIJIkA4oZSaZC5s+MdAgbyJuKzCn8cvpcYIWK3 N6e7Pw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm2; bh=vIdqWNwfpspIlxuEcLsiOuEZ3kAAeweEOeQZhepWk 04=; b=tqQwoNtUli79m+OILqXLOQnbHlwDJ2/H39yKiBGJIJAqf8jW4jDreXaTR jCrf3X8yt9LPvISOM+w5F5FqrKzi/IlRxrLDw7HBhmH1S5lbMx/0npxHQtCB6UiK zD3BwhVlCQYl3psP7rCE+h8JpmJAppK23ruRTUzV3jRewK85z0HgkaKsvE2e+6uL cWMzfqYL/UJbhyCF1YzMBD8P0636NMrEuXj+Asf4YJFWe1Goqq0NzFHInjL32gUp AAZTZK2TXsMMMNGUaCeqncwjABYKAO0W6ikRbpnpBj6zaZxLEzYKh5+VH6Pp7XLc MJ/kn618WFVWcC8MXJNr6864oAKHA== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeduledrvdeihedgudehucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepmfhlrghu shculfgvnhhsvghnuceoihhtshesihhrrhgvlhgvvhgrnhhtrdgukheqnecuggftrfgrth htvghrnhepteevuedugeevieehgeeileeufeetvddtkeetfeelgeehudfhjeeuledvhfff tdegnecukfhppeektddrudeijedrleekrdduledtnecuvehluhhsthgvrhfuihiivgeptd enucfrrghrrghmpehmrghilhhfrhhomhepihhtshesihhrrhgvlhgvvhgrnhhtrdgukh X-ME-Proxy: From: Klaus Jensen To: Peter Maydell , qemu-devel@nongnu.org Subject: [PULL 20/20] hw/nvme: move nvme emulation out of hw/block Date: Mon, 17 May 2021 11:17:37 +0200 Message-Id: <20210517091737.841787-21-its@irrelevant.dk> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210517091737.841787-1-its@irrelevant.dk> References: <20210517091737.841787-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=64.147.123.18; envelope-from=its@irrelevant.dk; helo=wnew4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Kevin Wolf , qemu-block@nongnu.org, Klaus Jensen , Max Reitz , Keith Busch , Stefan Hajnoczi , Klaus Jensen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" From: Klaus Jensen With the introduction of the nvme-subsystem device we are really cluttering up the hw/block directory. As suggested by Philippe previously, move the nvme emulation to hw/nvme. Suggested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Klaus Jensen Reviewed-by: Keith Busch --- meson.build | 1 + hw/{block =3D> nvme}/nvme.h | 6 +- hw/nvme/trace.h | 1 + hw/{block/nvme.c =3D> nvme/ctrl.c} | 0 hw/{block/nvme-dif.c =3D> nvme/dif.c} | 0 hw/{block/nvme-ns.c =3D> nvme/ns.c} | 0 hw/{block/nvme-subsys.c =3D> nvme/subsys.c} | 0 MAINTAINERS | 2 +- hw/Kconfig | 1 + hw/block/Kconfig | 5 - hw/block/meson.build | 1 - hw/block/trace-events | 206 ---------------------- hw/meson.build | 1 + hw/nvme/Kconfig | 4 + hw/nvme/meson.build | 1 + hw/nvme/trace-events | 204 +++++++++++++++++++++ 16 files changed, 217 insertions(+), 216 deletions(-) rename hw/{block =3D> nvme}/nvme.h (99%) create mode 100644 hw/nvme/trace.h rename hw/{block/nvme.c =3D> nvme/ctrl.c} (100%) rename hw/{block/nvme-dif.c =3D> nvme/dif.c} (100%) rename hw/{block/nvme-ns.c =3D> nvme/ns.c} (100%) rename hw/{block/nvme-subsys.c =3D> nvme/subsys.c} (100%) create mode 100644 hw/nvme/Kconfig create mode 100644 hw/nvme/meson.build create mode 100644 hw/nvme/trace-events diff --git a/meson.build b/meson.build index 8e16e05c2ade..1559e8d873a7 100644 --- a/meson.build +++ b/meson.build @@ -1822,6 +1822,7 @@ if have_system 'hw/misc/macio', 'hw/net', 'hw/net/can', + 'hw/nvme', 'hw/nvram', 'hw/pci', 'hw/pci-host', diff --git a/hw/block/nvme.h b/hw/nvme/nvme.h similarity index 99% rename from hw/block/nvme.h rename to hw/nvme/nvme.h index fb028d81d16f..81a35cda142b 100644 --- a/hw/block/nvme.h +++ b/hw/nvme/nvme.h @@ -15,8 +15,8 @@ * This code is licensed under the GNU GPL v2 or later. */ =20 -#ifndef HW_NVME_H -#define HW_NVME_H +#ifndef HW_NVME_INTERNAL_H +#define HW_NVME_INTERNAL_H =20 #include "qemu/uuid.h" #include "hw/pci/pci.h" @@ -544,4 +544,4 @@ uint16_t nvme_dif_check(NvmeNamespace *ns, uint8_t *buf= , size_t len, uint16_t nvme_dif_rw(NvmeCtrl *n, NvmeRequest *req); =20 =20 -#endif /* HW_NVME_H */ +#endif /* HW_NVME_INTERNAL_H */ diff --git a/hw/nvme/trace.h b/hw/nvme/trace.h new file mode 100644 index 000000000000..b398ea107f59 --- /dev/null +++ b/hw/nvme/trace.h @@ -0,0 +1 @@ +#include "trace/trace-hw_nvme.h" diff --git a/hw/block/nvme.c b/hw/nvme/ctrl.c similarity index 100% rename from hw/block/nvme.c rename to hw/nvme/ctrl.c diff --git a/hw/block/nvme-dif.c b/hw/nvme/dif.c similarity index 100% rename from hw/block/nvme-dif.c rename to hw/nvme/dif.c diff --git a/hw/block/nvme-ns.c b/hw/nvme/ns.c similarity index 100% rename from hw/block/nvme-ns.c rename to hw/nvme/ns.c diff --git a/hw/block/nvme-subsys.c b/hw/nvme/subsys.c similarity index 100% rename from hw/block/nvme-subsys.c rename to hw/nvme/subsys.c diff --git a/MAINTAINERS b/MAINTAINERS index 78561a223f92..e3c2866393e2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1956,7 +1956,7 @@ M: Keith Busch M: Klaus Jensen L: qemu-block@nongnu.org S: Supported -F: hw/block/nvme* +F: hw/nvme/* F: include/block/nvme.h F: tests/qtest/nvme-test.c F: docs/system/nvme.rst diff --git a/hw/Kconfig b/hw/Kconfig index aa10357adff2..805860f56451 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -21,6 +21,7 @@ source mem/Kconfig source misc/Kconfig source net/Kconfig source nubus/Kconfig +source nvme/Kconfig source nvram/Kconfig source pci-bridge/Kconfig source pci-host/Kconfig diff --git a/hw/block/Kconfig b/hw/block/Kconfig index 4fcd15216684..295441e64ab4 100644 --- a/hw/block/Kconfig +++ b/hw/block/Kconfig @@ -25,11 +25,6 @@ config ONENAND config TC58128 bool =20 -config NVME_PCI - bool - default y if PCI_DEVICES - depends on PCI - config VIRTIO_BLK bool default y diff --git a/hw/block/meson.build b/hw/block/meson.build index 5b4a7699f98f..8b0de54db1fc 100644 --- a/hw/block/meson.build +++ b/hw/block/meson.build @@ -13,7 +13,6 @@ softmmu_ss.add(when: 'CONFIG_SSI_M25P80', if_true: files(= 'm25p80.c')) softmmu_ss.add(when: 'CONFIG_SWIM', if_true: files('swim.c')) softmmu_ss.add(when: 'CONFIG_XEN', if_true: files('xen-block.c')) softmmu_ss.add(when: 'CONFIG_TC58128', if_true: files('tc58128.c')) -softmmu_ss.add(when: 'CONFIG_NVME_PCI', if_true: files('nvme.c', 'nvme-ns.= c', 'nvme-subsys.c', 'nvme-dif.c')) =20 specific_ss.add(when: 'CONFIG_VIRTIO_BLK', if_true: files('virtio-blk.c')) specific_ss.add(when: 'CONFIG_VHOST_USER_BLK', if_true: files('vhost-user-= blk.c')) diff --git a/hw/block/trace-events b/hw/block/trace-events index fa12e3a67a75..646917d045f7 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -49,212 +49,6 @@ virtio_blk_submit_multireq(void *vdev, void *mrb, int s= tart, int num_reqs, uint6 hd_geometry_lchs_guess(void *blk, int cyls, int heads, int secs) "blk %p L= CHS %d %d %d" hd_geometry_guess(void *blk, uint32_t cyls, uint32_t heads, uint32_t secs,= int trans) "blk %p CHS %u %u %u trans %d" =20 -# nvme.c -# nvme traces for successful events -pci_nvme_irq_msix(uint32_t vector) "raising MSI-X IRQ vector %u" -pci_nvme_irq_pin(void) "pulsing IRQ pin" -pci_nvme_irq_masked(void) "IRQ is masked" -pci_nvme_dma_read(uint64_t prp1, uint64_t prp2) "DMA read, prp1=3D0x%"PRIx= 64" prp2=3D0x%"PRIx64"" -pci_nvme_map_addr(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %"PRI= u64"" -pci_nvme_map_addr_cmb(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %= "PRIu64"" -pci_nvme_map_prp(uint64_t trans_len, uint32_t len, uint64_t prp1, uint64_t= prp2, int num_prps) "trans_len %"PRIu64" len %"PRIu32" prp1 0x%"PRIx64" pr= p2 0x%"PRIx64" num_prps %d" -pci_nvme_map_sgl(uint8_t typ, uint64_t len) "type 0x%"PRIx8" len %"PRIu64"" -pci_nvme_io_cmd(uint16_t cid, uint32_t nsid, uint16_t sqid, uint8_t opcode= , const char *opname) "cid %"PRIu16" nsid %"PRIu32" sqid %"PRIu16" opc 0x%"= PRIx8" opname '%s'" -pci_nvme_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t opcode, const char= *opname) "cid %"PRIu16" sqid %"PRIu16" opc 0x%"PRIx8" opname '%s'" -pci_nvme_flush(uint16_t cid, uint32_t nsid) "cid %"PRIu16" nsid %"PRIu32"" -pci_nvme_format(uint16_t cid, uint32_t nsid, uint8_t lbaf, uint8_t mset, u= int8_t pi, uint8_t pil) "cid %"PRIu16" nsid %"PRIu32" lbaf %"PRIu8" mset %"= PRIu8" pi %"PRIu8" pil %"PRIu8"" -pci_nvme_format_ns(uint16_t cid, uint32_t nsid, uint8_t lbaf, uint8_t mset= , uint8_t pi, uint8_t pil) "cid %"PRIu16" nsid %"PRIu32" lbaf %"PRIu8" mset= %"PRIu8" pi %"PRIu8" pil %"PRIu8"" -pci_nvme_format_cb(uint16_t cid, uint32_t nsid) "cid %"PRIu16" nsid %"PRIu= 32"" -pci_nvme_read(uint16_t cid, uint32_t nsid, uint32_t nlb, uint64_t count, u= int64_t lba) "cid %"PRIu16" nsid %"PRIu32" nlb %"PRIu32" count %"PRIu64" lb= a 0x%"PRIx64"" -pci_nvme_write(uint16_t cid, const char *verb, uint32_t nsid, uint32_t nlb= , uint64_t count, uint64_t lba) "cid %"PRIu16" opname '%s' nsid %"PRIu32" n= lb %"PRIu32" count %"PRIu64" lba 0x%"PRIx64"" -pci_nvme_rw_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'" -pci_nvme_misc_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s= '" -pci_nvme_dif_rw(uint8_t pract, uint8_t prinfo) "pract 0x%"PRIx8" prinfo 0x= %"PRIx8"" -pci_nvme_dif_rw_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '= %s'" -pci_nvme_dif_rw_mdata_in_cb(uint16_t cid, const char *blkname) "cid %"PRIu= 16" blk '%s'" -pci_nvme_dif_rw_mdata_out_cb(uint16_t cid, const char *blkname) "cid %"PRI= u16" blk '%s'" -pci_nvme_dif_rw_check_cb(uint16_t cid, uint8_t prinfo, uint16_t apptag, ui= nt16_t appmask, uint32_t reftag) "cid %"PRIu16" prinfo 0x%"PRIx8" apptag 0x= %"PRIx16" appmask 0x%"PRIx16" reftag 0x%"PRIx32"" -pci_nvme_dif_pract_generate_dif(size_t len, size_t lba_size, size_t chksum= _len, uint16_t apptag, uint32_t reftag) "len %zu lba_size %zu chksum_len %z= u apptag 0x%"PRIx16" reftag 0x%"PRIx32"" -pci_nvme_dif_check(uint8_t prinfo, uint16_t chksum_len) "prinfo 0x%"PRIx8"= chksum_len %"PRIu16"" -pci_nvme_dif_prchk_disabled(uint16_t apptag, uint32_t reftag) "apptag 0x%"= PRIx16" reftag 0x%"PRIx32"" -pci_nvme_dif_prchk_guard(uint16_t guard, uint16_t crc) "guard 0x%"PRIx16" = crc 0x%"PRIx16"" -pci_nvme_dif_prchk_apptag(uint16_t apptag, uint16_t elbat, uint16_t elbatm= ) "apptag 0x%"PRIx16" elbat 0x%"PRIx16" elbatm 0x%"PRIx16"" -pci_nvme_dif_prchk_reftag(uint32_t reftag, uint32_t elbrt) "reftag 0x%"PRI= x32" elbrt 0x%"PRIx32"" -pci_nvme_copy(uint16_t cid, uint32_t nsid, uint16_t nr, uint8_t format) "c= id %"PRIu16" nsid %"PRIu32" nr %"PRIu16" format 0x%"PRIx8"" -pci_nvme_copy_source_range(uint64_t slba, uint32_t nlb) "slba 0x%"PRIx64" = nlb %"PRIu32"" -pci_nvme_copy_in_complete(uint16_t cid) "cid %"PRIu16"" -pci_nvme_copy_cb(uint16_t cid) "cid %"PRIu16"" -pci_nvme_verify(uint16_t cid, uint32_t nsid, uint64_t slba, uint32_t nlb) = "cid %"PRIu16" nsid %"PRIu32" slba 0x%"PRIx64" nlb %"PRIu32"" -pci_nvme_verify_mdata_in_cb(uint16_t cid, const char *blkname) "cid %"PRIu= 16" blk '%s'" -pci_nvme_verify_cb(uint16_t cid, uint8_t prinfo, uint16_t apptag, uint16_t= appmask, uint32_t reftag) "cid %"PRIu16" prinfo 0x%"PRIx8" apptag 0x%"PRIx= 16" appmask 0x%"PRIx16" reftag 0x%"PRIx32"" -pci_nvme_rw_complete_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" = blk '%s'" -pci_nvme_block_status(int64_t offset, int64_t bytes, int64_t pnum, int ret= , bool zeroed) "offset %"PRId64" bytes %"PRId64" pnum %"PRId64" ret 0x%x ze= roed %d" -pci_nvme_dsm(uint16_t cid, uint32_t nsid, uint32_t nr, uint32_t attr) "cid= %"PRIu16" nsid %"PRIu32" nr %"PRIu32" attr 0x%"PRIx32"" -pci_nvme_dsm_deallocate(uint16_t cid, uint32_t nsid, uint64_t slba, uint32= _t nlb) "cid %"PRIu16" nsid %"PRIu32" slba %"PRIu64" nlb %"PRIu32"" -pci_nvme_dsm_single_range_limit_exceeded(uint32_t nlb, uint32_t dmrsl) "nl= b %"PRIu32" dmrsl %"PRIu32"" -pci_nvme_compare(uint16_t cid, uint32_t nsid, uint64_t slba, uint32_t nlb)= "cid %"PRIu16" nsid %"PRIu32" slba 0x%"PRIx64" nlb %"PRIu32"" -pci_nvme_compare_data_cb(uint16_t cid) "cid %"PRIu16"" -pci_nvme_compare_mdata_cb(uint16_t cid) "cid %"PRIu16"" -pci_nvme_aio_discard_cb(uint16_t cid) "cid %"PRIu16"" -pci_nvme_aio_copy_in_cb(uint16_t cid) "cid %"PRIu16"" -pci_nvme_aio_zone_reset_cb(uint16_t cid, uint64_t zslba) "cid %"PRIu16" zs= lba 0x%"PRIx64"" -pci_nvme_aio_flush_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" bl= k '%s'" -pci_nvme_create_sq(uint64_t addr, uint16_t sqid, uint16_t cqid, uint16_t q= size, uint16_t qflags) "create submission queue, addr=3D0x%"PRIx64", sqid= =3D%"PRIu16", cqid=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRIu16"" -pci_nvme_create_cq(uint64_t addr, uint16_t cqid, uint16_t vector, uint16_t= size, uint16_t qflags, int ien) "create completion queue, addr=3D0x%"PRIx6= 4", cqid=3D%"PRIu16", vector=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRI= u16", ien=3D%d" -pci_nvme_del_sq(uint16_t qid) "deleting submission queue sqid=3D%"PRIu16"" -pci_nvme_del_cq(uint16_t cqid) "deleted completion queue, cqid=3D%"PRIu16"" -pci_nvme_identify(uint16_t cid, uint8_t cns, uint16_t ctrlid, uint8_t csi)= "cid %"PRIu16" cns 0x%"PRIx8" ctrlid %"PRIu16" csi 0x%"PRIx8"" -pci_nvme_identify_ctrl(void) "identify controller" -pci_nvme_identify_ctrl_csi(uint8_t csi) "identify controller, csi=3D0x%"PR= Ix8"" -pci_nvme_identify_ns(uint32_t ns) "nsid %"PRIu32"" -pci_nvme_identify_ns_attached_list(uint16_t cntid) "cntid=3D%"PRIu16"" -pci_nvme_identify_ns_csi(uint32_t ns, uint8_t csi) "nsid=3D%"PRIu32", csi= =3D0x%"PRIx8"" -pci_nvme_identify_nslist(uint32_t ns) "nsid %"PRIu32"" -pci_nvme_identify_nslist_csi(uint16_t ns, uint8_t csi) "nsid=3D%"PRIu16", = csi=3D0x%"PRIx8"" -pci_nvme_identify_cmd_set(void) "identify i/o command set" -pci_nvme_identify_ns_descr_list(uint32_t ns) "nsid %"PRIu32"" -pci_nvme_get_log(uint16_t cid, uint8_t lid, uint8_t lsp, uint8_t rae, uint= 32_t len, uint64_t off) "cid %"PRIu16" lid 0x%"PRIx8" lsp 0x%"PRIx8" rae 0x= %"PRIx8" len %"PRIu32" off %"PRIu64"" -pci_nvme_getfeat(uint16_t cid, uint32_t nsid, uint8_t fid, uint8_t sel, ui= nt32_t cdw11) "cid %"PRIu16" nsid 0x%"PRIx32" fid 0x%"PRIx8" sel 0x%"PRIx8"= cdw11 0x%"PRIx32"" -pci_nvme_setfeat(uint16_t cid, uint32_t nsid, uint8_t fid, uint8_t save, u= int32_t cdw11) "cid %"PRIu16" nsid 0x%"PRIx32" fid 0x%"PRIx8" save 0x%"PRIx= 8" cdw11 0x%"PRIx32"" -pci_nvme_getfeat_vwcache(const char* result) "get feature volatile write c= ache, result=3D%s" -pci_nvme_getfeat_numq(int result) "get feature number of queues, result=3D= %d" -pci_nvme_setfeat_numq(int reqcq, int reqsq, int gotcq, int gotsq) "request= ed cq_count=3D%d sq_count=3D%d, responding with cq_count=3D%d sq_count=3D%d" -pci_nvme_setfeat_timestamp(uint64_t ts) "set feature timestamp =3D 0x%"PRI= x64"" -pci_nvme_getfeat_timestamp(uint64_t ts) "get feature timestamp =3D 0x%"PRI= x64"" -pci_nvme_process_aers(int queued) "queued %d" -pci_nvme_aer(uint16_t cid) "cid %"PRIu16"" -pci_nvme_aer_aerl_exceeded(void) "aerl exceeded" -pci_nvme_aer_masked(uint8_t type, uint8_t mask) "type 0x%"PRIx8" mask 0x%"= PRIx8"" -pci_nvme_aer_post_cqe(uint8_t typ, uint8_t info, uint8_t log_page) "type 0= x%"PRIx8" info 0x%"PRIx8" lid 0x%"PRIx8"" -pci_nvme_ns_attachment(uint16_t cid, uint8_t sel) "cid %"PRIu16", sel=3D0x= %"PRIx8"" -pci_nvme_ns_attachment_attach(uint16_t cntlid, uint32_t nsid) "cntlid=3D0x= %"PRIx16", nsid=3D0x%"PRIx32"" -pci_nvme_enqueue_event(uint8_t typ, uint8_t info, uint8_t log_page) "type = 0x%"PRIx8" info 0x%"PRIx8" lid 0x%"PRIx8"" -pci_nvme_enqueue_event_noqueue(int queued) "queued %d" -pci_nvme_enqueue_event_masked(uint8_t typ) "type 0x%"PRIx8"" -pci_nvme_no_outstanding_aers(void) "ignoring event; no outstanding AERs" -pci_nvme_enqueue_req_completion(uint16_t cid, uint16_t cqid, uint16_t stat= us) "cid %"PRIu16" cqid %"PRIu16" status 0x%"PRIx16"" -pci_nvme_mmio_read(uint64_t addr, unsigned size) "addr 0x%"PRIx64" size %d" -pci_nvme_mmio_write(uint64_t addr, uint64_t data, unsigned size) "addr 0x%= "PRIx64" data 0x%"PRIx64" size %d" -pci_nvme_mmio_doorbell_cq(uint16_t cqid, uint16_t new_head) "cqid %"PRIu16= " new_head %"PRIu16"" -pci_nvme_mmio_doorbell_sq(uint16_t sqid, uint16_t new_tail) "sqid %"PRIu16= " new_tail %"PRIu16"" -pci_nvme_mmio_intm_set(uint64_t data, uint64_t new_mask) "wrote MMIO, inte= rrupt mask set, data=3D0x%"PRIx64", new_mask=3D0x%"PRIx64"" -pci_nvme_mmio_intm_clr(uint64_t data, uint64_t new_mask) "wrote MMIO, inte= rrupt mask clr, data=3D0x%"PRIx64", new_mask=3D0x%"PRIx64"" -pci_nvme_mmio_cfg(uint64_t data) "wrote MMIO, config controller config=3D0= x%"PRIx64"" -pci_nvme_mmio_aqattr(uint64_t data) "wrote MMIO, admin queue attributes=3D= 0x%"PRIx64"" -pci_nvme_mmio_asqaddr(uint64_t data) "wrote MMIO, admin submission queue a= ddress=3D0x%"PRIx64"" -pci_nvme_mmio_acqaddr(uint64_t data) "wrote MMIO, admin completion queue a= ddress=3D0x%"PRIx64"" -pci_nvme_mmio_asqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, ad= min submission queue high half=3D0x%"PRIx64", new_address=3D0x%"PRIx64"" -pci_nvme_mmio_acqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, ad= min completion queue high half=3D0x%"PRIx64", new_address=3D0x%"PRIx64"" -pci_nvme_mmio_start_success(void) "setting controller enable bit succeeded" -pci_nvme_mmio_stopped(void) "cleared controller enable bit" -pci_nvme_mmio_shutdown_set(void) "shutdown bit set" -pci_nvme_mmio_shutdown_cleared(void) "shutdown bit cleared" -pci_nvme_open_zone(uint64_t slba, uint32_t zone_idx, int all) "open zone, = slba=3D%"PRIu64", idx=3D%"PRIu32", all=3D%"PRIi32"" -pci_nvme_close_zone(uint64_t slba, uint32_t zone_idx, int all) "close zone= , slba=3D%"PRIu64", idx=3D%"PRIu32", all=3D%"PRIi32"" -pci_nvme_finish_zone(uint64_t slba, uint32_t zone_idx, int all) "finish zo= ne, slba=3D%"PRIu64", idx=3D%"PRIu32", all=3D%"PRIi32"" -pci_nvme_reset_zone(uint64_t slba, uint32_t zone_idx, int all) "reset zone= , slba=3D%"PRIu64", idx=3D%"PRIu32", all=3D%"PRIi32"" -pci_nvme_offline_zone(uint64_t slba, uint32_t zone_idx, int all) "offline = zone, slba=3D%"PRIu64", idx=3D%"PRIu32", all=3D%"PRIi32"" -pci_nvme_set_descriptor_extension(uint64_t slba, uint32_t zone_idx) "set z= one descriptor extension, slba=3D%"PRIu64", idx=3D%"PRIu32"" -pci_nvme_zd_extension_set(uint32_t zone_idx) "set descriptor extension for= zone_idx=3D%"PRIu32"" -pci_nvme_clear_ns_close(uint32_t state, uint64_t slba) "zone state=3D%"PRI= u32", slba=3D%"PRIu64" transitioned to Closed state" -pci_nvme_clear_ns_reset(uint32_t state, uint64_t slba) "zone state=3D%"PRI= u32", slba=3D%"PRIu64" transitioned to Empty state" - -# nvme traces for error conditions -pci_nvme_err_mdts(size_t len) "len %zu" -pci_nvme_err_zasl(size_t len) "len %zu" -pci_nvme_err_req_status(uint16_t cid, uint32_t nsid, uint16_t status, uint= 8_t opc) "cid %"PRIu16" nsid %"PRIu32" status 0x%"PRIx16" opc 0x%"PRIx8"" -pci_nvme_err_addr_read(uint64_t addr) "addr 0x%"PRIx64"" -pci_nvme_err_addr_write(uint64_t addr) "addr 0x%"PRIx64"" -pci_nvme_err_cfs(void) "controller fatal status" -pci_nvme_err_aio(uint16_t cid, const char *errname, uint16_t status) "cid = %"PRIu16" err '%s' status 0x%"PRIx16"" -pci_nvme_err_copy_invalid_format(uint8_t format) "format 0x%"PRIx8"" -pci_nvme_err_invalid_sgld(uint16_t cid, uint8_t typ) "cid %"PRIu16" type 0= x%"PRIx8"" -pci_nvme_err_invalid_num_sgld(uint16_t cid, uint8_t typ) "cid %"PRIu16" ty= pe 0x%"PRIx8"" -pci_nvme_err_invalid_sgl_excess_length(uint32_t residual) "residual %"PRIu= 32"" -pci_nvme_err_invalid_dma(void) "PRP/SGL is too small for transfer size" -pci_nvme_err_invalid_prplist_ent(uint64_t prplist) "PRP list entry is not = page aligned: 0x%"PRIx64"" -pci_nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is not page aligned: = 0x%"PRIx64"" -pci_nvme_err_invalid_opc(uint8_t opc) "invalid opcode 0x%"PRIx8"" -pci_nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin opcode 0x%"PRIx= 8"" -pci_nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limi= t) "Invalid LBA start=3D%"PRIu64" len=3D%"PRIu64" limit=3D%"PRIu64"" -pci_nvme_err_invalid_log_page_offset(uint64_t ofs, uint64_t size) "must be= <=3D %"PRIu64", got %"PRIu64"" -pci_nvme_err_cmb_invalid_cba(uint64_t cmbmsc) "cmbmsc 0x%"PRIx64"" -pci_nvme_err_cmb_not_enabled(uint64_t cmbmsc) "cmbmsc 0x%"PRIx64"" -pci_nvme_err_unaligned_zone_cmd(uint8_t action, uint64_t slba, uint64_t zs= lba) "unaligned zone op 0x%"PRIx32", got slba=3D%"PRIu64", zslba=3D%"PRIu64= "" -pci_nvme_err_invalid_zone_state_transition(uint8_t action, uint64_t slba, = uint8_t attrs) "action=3D0x%"PRIx8", slba=3D%"PRIu64", attrs=3D0x%"PRIx32"" -pci_nvme_err_write_not_at_wp(uint64_t slba, uint64_t zone, uint64_t wp) "w= riting at slba=3D%"PRIu64", zone=3D%"PRIu64", but wp=3D%"PRIu64"" -pci_nvme_err_append_not_at_start(uint64_t slba, uint64_t zone) "appending = at slba=3D%"PRIu64", but zone=3D%"PRIu64"" -pci_nvme_err_zone_is_full(uint64_t zslba) "zslba 0x%"PRIx64"" -pci_nvme_err_zone_is_read_only(uint64_t zslba) "zslba 0x%"PRIx64"" -pci_nvme_err_zone_is_offline(uint64_t zslba) "zslba 0x%"PRIx64"" -pci_nvme_err_zone_boundary(uint64_t slba, uint32_t nlb, uint64_t zcap) "lb= a 0x%"PRIx64" nlb %"PRIu32" zcap 0x%"PRIx64"" -pci_nvme_err_zone_invalid_write(uint64_t slba, uint64_t wp) "lba 0x%"PRIx6= 4" wp 0x%"PRIx64"" -pci_nvme_err_zone_write_not_ok(uint64_t slba, uint32_t nlb, uint16_t statu= s) "slba=3D%"PRIu64", nlb=3D%"PRIu32", status=3D0x%"PRIx16"" -pci_nvme_err_zone_read_not_ok(uint64_t slba, uint32_t nlb, uint16_t status= ) "slba=3D%"PRIu64", nlb=3D%"PRIu32", status=3D0x%"PRIx16"" -pci_nvme_err_insuff_active_res(uint32_t max_active) "max_active=3D%"PRIu32= " zone limit exceeded" -pci_nvme_err_insuff_open_res(uint32_t max_open) "max_open=3D%"PRIu32" zone= limit exceeded" -pci_nvme_err_zd_extension_map_error(uint32_t zone_idx) "can't map descript= or extension for zone_idx=3D%"PRIu32"" -pci_nvme_err_invalid_iocsci(uint32_t idx) "unsupported command set combina= tion index %"PRIu32"" -pci_nvme_err_invalid_del_sq(uint16_t qid) "invalid submission queue deleti= on, sid=3D%"PRIu16"" -pci_nvme_err_invalid_create_sq_cqid(uint16_t cqid) "failed creating submis= sion queue, invalid cqid=3D%"PRIu16"" -pci_nvme_err_invalid_create_sq_sqid(uint16_t sqid) "failed creating submis= sion queue, invalid sqid=3D%"PRIu16"" -pci_nvme_err_invalid_create_sq_size(uint16_t qsize) "failed creating submi= ssion queue, invalid qsize=3D%"PRIu16"" -pci_nvme_err_invalid_create_sq_addr(uint64_t addr) "failed creating submis= sion queue, addr=3D0x%"PRIx64"" -pci_nvme_err_invalid_create_sq_qflags(uint16_t qflags) "failed creating su= bmission queue, qflags=3D%"PRIu16"" -pci_nvme_err_invalid_del_cq_cqid(uint16_t cqid) "failed deleting completio= n queue, cqid=3D%"PRIu16"" -pci_nvme_err_invalid_del_cq_notempty(uint16_t cqid) "failed deleting compl= etion queue, it is not empty, cqid=3D%"PRIu16"" -pci_nvme_err_invalid_create_cq_cqid(uint16_t cqid) "failed creating comple= tion queue, cqid=3D%"PRIu16"" -pci_nvme_err_invalid_create_cq_size(uint16_t size) "failed creating comple= tion queue, size=3D%"PRIu16"" -pci_nvme_err_invalid_create_cq_addr(uint64_t addr) "failed creating comple= tion queue, addr=3D0x%"PRIx64"" -pci_nvme_err_invalid_create_cq_vector(uint16_t vector) "failed creating co= mpletion queue, vector=3D%"PRIu16"" -pci_nvme_err_invalid_create_cq_qflags(uint16_t qflags) "failed creating co= mpletion queue, qflags=3D%"PRIu16"" -pci_nvme_err_invalid_identify_cns(uint16_t cns) "identify, invalid cns=3D0= x%"PRIx16"" -pci_nvme_err_invalid_getfeat(int dw10) "invalid get features, dw10=3D0x%"P= RIx32"" -pci_nvme_err_invalid_setfeat(uint32_t dw10) "invalid set features, dw10=3D= 0x%"PRIx32"" -pci_nvme_err_invalid_log_page(uint16_t cid, uint16_t lid) "cid %"PRIu16" l= id 0x%"PRIx16"" -pci_nvme_err_startfail_cq(void) "nvme_start_ctrl failed because there are = non-admin completion queues" -pci_nvme_err_startfail_sq(void) "nvme_start_ctrl failed because there are = non-admin submission queues" -pci_nvme_err_startfail_nbarasq(void) "nvme_start_ctrl failed because the a= dmin submission queue address is null" -pci_nvme_err_startfail_nbaracq(void) "nvme_start_ctrl failed because the a= dmin completion queue address is null" -pci_nvme_err_startfail_asq_misaligned(uint64_t addr) "nvme_start_ctrl fail= ed because the admin submission queue address is misaligned: 0x%"PRIx64"" -pci_nvme_err_startfail_acq_misaligned(uint64_t addr) "nvme_start_ctrl fail= ed because the admin completion queue address is misaligned: 0x%"PRIx64"" -pci_nvme_err_startfail_page_too_small(uint8_t log2ps, uint8_t maxlog2ps) "= nvme_start_ctrl failed because the page size is too small: log2size=3D%u, m= in=3D%u" -pci_nvme_err_startfail_page_too_large(uint8_t log2ps, uint8_t maxlog2ps) "= nvme_start_ctrl failed because the page size is too large: log2size=3D%u, m= ax=3D%u" -pci_nvme_err_startfail_cqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the completion queue entry size is too smal= l: log2size=3D%u, min=3D%u" -pci_nvme_err_startfail_cqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the completion queue entry size is too larg= e: log2size=3D%u, max=3D%u" -pci_nvme_err_startfail_sqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the submission queue entry size is too smal= l: log2size=3D%u, min=3D%u" -pci_nvme_err_startfail_sqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the submission queue entry size is too larg= e: log2size=3D%u, max=3D%u" -pci_nvme_err_startfail_css(uint8_t css) "nvme_start_ctrl failed because in= valid command set selected:%u" -pci_nvme_err_startfail_asqent_sz_zero(void) "nvme_start_ctrl failed becaus= e the admin submission queue size is zero" -pci_nvme_err_startfail_acqent_sz_zero(void) "nvme_start_ctrl failed becaus= e the admin completion queue size is zero" -pci_nvme_err_startfail_zasl_too_small(uint32_t zasl, uint32_t pagesz) "nvm= e_start_ctrl failed because zone append size limit %"PRIu32" is too small, = needs to be >=3D %"PRIu32"" -pci_nvme_err_startfail(void) "setting controller enable bit failed" -pci_nvme_err_invalid_mgmt_action(uint8_t action) "action=3D0x%"PRIx8"" - -# Traces for undefined behavior -pci_nvme_ub_mmiowr_misaligned32(uint64_t offset) "MMIO write not 32-bit al= igned, offset=3D0x%"PRIx64"" -pci_nvme_ub_mmiowr_toosmall(uint64_t offset, unsigned size) "MMIO write sm= aller than 32 bits, offset=3D0x%"PRIx64", size=3D%u" -pci_nvme_ub_mmiowr_intmask_with_msix(void) "undefined access to interrupt = mask set when MSI-X is enabled" -pci_nvme_ub_mmiowr_ro_csts(void) "attempted to set a read only bit of cont= roller status" -pci_nvme_ub_mmiowr_ssreset_w1c_unsupported(void) "attempted to W1C CSTS.NS= SRO but CAP.NSSRS is zero (not supported)" -pci_nvme_ub_mmiowr_ssreset_unsupported(void) "attempted NVM subsystem rese= t but CAP.NSSRS is zero (not supported)" -pci_nvme_ub_mmiowr_cmbloc_reserved(void) "invalid write to reserved CMBLOC= when CMBSZ is zero, ignored" -pci_nvme_ub_mmiowr_cmbsz_readonly(void) "invalid write to read only CMBSZ,= ignored" -pci_nvme_ub_mmiowr_pmrcap_readonly(void) "invalid write to read only PMRCA= P, ignored" -pci_nvme_ub_mmiowr_pmrsts_readonly(void) "invalid write to read only PMRST= S, ignored" -pci_nvme_ub_mmiowr_pmrebs_readonly(void) "invalid write to read only PMREB= S, ignored" -pci_nvme_ub_mmiowr_pmrswtp_readonly(void) "invalid write to read only PMRS= WTP, ignored" -pci_nvme_ub_mmiowr_invalid(uint64_t offset, uint64_t data) "invalid MMIO w= rite, offset=3D0x%"PRIx64", data=3D0x%"PRIx64"" -pci_nvme_ub_mmiord_misaligned32(uint64_t offset) "MMIO read not 32-bit ali= gned, offset=3D0x%"PRIx64"" -pci_nvme_ub_mmiord_toosmall(uint64_t offset) "MMIO read smaller than 32-bi= ts, offset=3D0x%"PRIx64"" -pci_nvme_ub_mmiord_invalid_ofs(uint64_t offset) "MMIO read beyond last reg= ister, offset=3D0x%"PRIx64", returning 0" -pci_nvme_ub_db_wr_misaligned(uint64_t offset) "doorbell write not 32-bit a= ligned, offset=3D0x%"PRIx64", ignoring" -pci_nvme_ub_db_wr_invalid_cq(uint32_t qid) "completion queue doorbell writ= e for nonexistent queue, cqid=3D%"PRIu32", ignoring" -pci_nvme_ub_db_wr_invalid_cqhead(uint32_t qid, uint16_t new_head) "complet= ion queue doorbell write value beyond queue size, cqid=3D%"PRIu32", new_hea= d=3D%"PRIu16", ignoring" -pci_nvme_ub_db_wr_invalid_sq(uint32_t qid) "submission queue doorbell writ= e for nonexistent queue, sqid=3D%"PRIu32", ignoring" -pci_nvme_ub_db_wr_invalid_sqtail(uint32_t qid, uint16_t new_tail) "submiss= ion queue doorbell write value beyond queue size, sqid=3D%"PRIu32", new_hea= d=3D%"PRIu16", ignoring" -pci_nvme_ub_unknown_css_value(void) "unknown value in cc.css field" - # xen-block.c xen_block_realize(const char *type, uint32_t disk, uint32_t partition) "%s= d%up%u" xen_block_connect(const char *type, uint32_t disk, uint32_t partition) "%s= d%up%u" diff --git a/hw/meson.build b/hw/meson.build index 6bdbae0e810a..ba0601e36edf 100644 --- a/hw/meson.build +++ b/hw/meson.build @@ -21,6 +21,7 @@ subdir('mem') subdir('misc') subdir('net') subdir('nubus') +subdir('nvme') subdir('nvram') subdir('pci') subdir('pci-bridge') diff --git a/hw/nvme/Kconfig b/hw/nvme/Kconfig new file mode 100644 index 000000000000..8ac90942e55e --- /dev/null +++ b/hw/nvme/Kconfig @@ -0,0 +1,4 @@ +config NVME_PCI + bool + default y if PCI_DEVICES + depends on PCI diff --git a/hw/nvme/meson.build b/hw/nvme/meson.build new file mode 100644 index 000000000000..3cf40046eea9 --- /dev/null +++ b/hw/nvme/meson.build @@ -0,0 +1 @@ +softmmu_ss.add(when: 'CONFIG_NVME_PCI', if_true: files('ctrl.c', 'dif.c', = 'ns.c', 'subsys.c')) diff --git a/hw/nvme/trace-events b/hw/nvme/trace-events new file mode 100644 index 000000000000..ea33d0ccc383 --- /dev/null +++ b/hw/nvme/trace-events @@ -0,0 +1,204 @@ +# successful events +pci_nvme_irq_msix(uint32_t vector) "raising MSI-X IRQ vector %u" +pci_nvme_irq_pin(void) "pulsing IRQ pin" +pci_nvme_irq_masked(void) "IRQ is masked" +pci_nvme_dma_read(uint64_t prp1, uint64_t prp2) "DMA read, prp1=3D0x%"PRIx= 64" prp2=3D0x%"PRIx64"" +pci_nvme_map_addr(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %"PRI= u64"" +pci_nvme_map_addr_cmb(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %= "PRIu64"" +pci_nvme_map_prp(uint64_t trans_len, uint32_t len, uint64_t prp1, uint64_t= prp2, int num_prps) "trans_len %"PRIu64" len %"PRIu32" prp1 0x%"PRIx64" pr= p2 0x%"PRIx64" num_prps %d" +pci_nvme_map_sgl(uint8_t typ, uint64_t len) "type 0x%"PRIx8" len %"PRIu64"" +pci_nvme_io_cmd(uint16_t cid, uint32_t nsid, uint16_t sqid, uint8_t opcode= , const char *opname) "cid %"PRIu16" nsid %"PRIu32" sqid %"PRIu16" opc 0x%"= PRIx8" opname '%s'" +pci_nvme_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t opcode, const char= *opname) "cid %"PRIu16" sqid %"PRIu16" opc 0x%"PRIx8" opname '%s'" +pci_nvme_flush(uint16_t cid, uint32_t nsid) "cid %"PRIu16" nsid %"PRIu32"" +pci_nvme_format(uint16_t cid, uint32_t nsid, uint8_t lbaf, uint8_t mset, u= int8_t pi, uint8_t pil) "cid %"PRIu16" nsid %"PRIu32" lbaf %"PRIu8" mset %"= PRIu8" pi %"PRIu8" pil %"PRIu8"" +pci_nvme_format_ns(uint16_t cid, uint32_t nsid, uint8_t lbaf, uint8_t mset= , uint8_t pi, uint8_t pil) "cid %"PRIu16" nsid %"PRIu32" lbaf %"PRIu8" mset= %"PRIu8" pi %"PRIu8" pil %"PRIu8"" +pci_nvme_format_cb(uint16_t cid, uint32_t nsid) "cid %"PRIu16" nsid %"PRIu= 32"" +pci_nvme_read(uint16_t cid, uint32_t nsid, uint32_t nlb, uint64_t count, u= int64_t lba) "cid %"PRIu16" nsid %"PRIu32" nlb %"PRIu32" count %"PRIu64" lb= a 0x%"PRIx64"" +pci_nvme_write(uint16_t cid, const char *verb, uint32_t nsid, uint32_t nlb= , uint64_t count, uint64_t lba) "cid %"PRIu16" opname '%s' nsid %"PRIu32" n= lb %"PRIu32" count %"PRIu64" lba 0x%"PRIx64"" +pci_nvme_rw_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'" +pci_nvme_misc_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s= '" +pci_nvme_dif_rw(uint8_t pract, uint8_t prinfo) "pract 0x%"PRIx8" prinfo 0x= %"PRIx8"" +pci_nvme_dif_rw_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '= %s'" +pci_nvme_dif_rw_mdata_in_cb(uint16_t cid, const char *blkname) "cid %"PRIu= 16" blk '%s'" +pci_nvme_dif_rw_mdata_out_cb(uint16_t cid, const char *blkname) "cid %"PRI= u16" blk '%s'" +pci_nvme_dif_rw_check_cb(uint16_t cid, uint8_t prinfo, uint16_t apptag, ui= nt16_t appmask, uint32_t reftag) "cid %"PRIu16" prinfo 0x%"PRIx8" apptag 0x= %"PRIx16" appmask 0x%"PRIx16" reftag 0x%"PRIx32"" +pci_nvme_dif_pract_generate_dif(size_t len, size_t lba_size, size_t chksum= _len, uint16_t apptag, uint32_t reftag) "len %zu lba_size %zu chksum_len %z= u apptag 0x%"PRIx16" reftag 0x%"PRIx32"" +pci_nvme_dif_check(uint8_t prinfo, uint16_t chksum_len) "prinfo 0x%"PRIx8"= chksum_len %"PRIu16"" +pci_nvme_dif_prchk_disabled(uint16_t apptag, uint32_t reftag) "apptag 0x%"= PRIx16" reftag 0x%"PRIx32"" +pci_nvme_dif_prchk_guard(uint16_t guard, uint16_t crc) "guard 0x%"PRIx16" = crc 0x%"PRIx16"" +pci_nvme_dif_prchk_apptag(uint16_t apptag, uint16_t elbat, uint16_t elbatm= ) "apptag 0x%"PRIx16" elbat 0x%"PRIx16" elbatm 0x%"PRIx16"" +pci_nvme_dif_prchk_reftag(uint32_t reftag, uint32_t elbrt) "reftag 0x%"PRI= x32" elbrt 0x%"PRIx32"" +pci_nvme_copy(uint16_t cid, uint32_t nsid, uint16_t nr, uint8_t format) "c= id %"PRIu16" nsid %"PRIu32" nr %"PRIu16" format 0x%"PRIx8"" +pci_nvme_copy_source_range(uint64_t slba, uint32_t nlb) "slba 0x%"PRIx64" = nlb %"PRIu32"" +pci_nvme_copy_in_complete(uint16_t cid) "cid %"PRIu16"" +pci_nvme_copy_cb(uint16_t cid) "cid %"PRIu16"" +pci_nvme_verify(uint16_t cid, uint32_t nsid, uint64_t slba, uint32_t nlb) = "cid %"PRIu16" nsid %"PRIu32" slba 0x%"PRIx64" nlb %"PRIu32"" +pci_nvme_verify_mdata_in_cb(uint16_t cid, const char *blkname) "cid %"PRIu= 16" blk '%s'" +pci_nvme_verify_cb(uint16_t cid, uint8_t prinfo, uint16_t apptag, uint16_t= appmask, uint32_t reftag) "cid %"PRIu16" prinfo 0x%"PRIx8" apptag 0x%"PRIx= 16" appmask 0x%"PRIx16" reftag 0x%"PRIx32"" +pci_nvme_rw_complete_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" = blk '%s'" +pci_nvme_block_status(int64_t offset, int64_t bytes, int64_t pnum, int ret= , bool zeroed) "offset %"PRId64" bytes %"PRId64" pnum %"PRId64" ret 0x%x ze= roed %d" +pci_nvme_dsm(uint16_t cid, uint32_t nsid, uint32_t nr, uint32_t attr) "cid= %"PRIu16" nsid %"PRIu32" nr %"PRIu32" attr 0x%"PRIx32"" +pci_nvme_dsm_deallocate(uint16_t cid, uint32_t nsid, uint64_t slba, uint32= _t nlb) "cid %"PRIu16" nsid %"PRIu32" slba %"PRIu64" nlb %"PRIu32"" +pci_nvme_dsm_single_range_limit_exceeded(uint32_t nlb, uint32_t dmrsl) "nl= b %"PRIu32" dmrsl %"PRIu32"" +pci_nvme_compare(uint16_t cid, uint32_t nsid, uint64_t slba, uint32_t nlb)= "cid %"PRIu16" nsid %"PRIu32" slba 0x%"PRIx64" nlb %"PRIu32"" +pci_nvme_compare_data_cb(uint16_t cid) "cid %"PRIu16"" +pci_nvme_compare_mdata_cb(uint16_t cid) "cid %"PRIu16"" +pci_nvme_aio_discard_cb(uint16_t cid) "cid %"PRIu16"" +pci_nvme_aio_copy_in_cb(uint16_t cid) "cid %"PRIu16"" +pci_nvme_aio_zone_reset_cb(uint16_t cid, uint64_t zslba) "cid %"PRIu16" zs= lba 0x%"PRIx64"" +pci_nvme_aio_flush_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" bl= k '%s'" +pci_nvme_create_sq(uint64_t addr, uint16_t sqid, uint16_t cqid, uint16_t q= size, uint16_t qflags) "create submission queue, addr=3D0x%"PRIx64", sqid= =3D%"PRIu16", cqid=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRIu16"" +pci_nvme_create_cq(uint64_t addr, uint16_t cqid, uint16_t vector, uint16_t= size, uint16_t qflags, int ien) "create completion queue, addr=3D0x%"PRIx6= 4", cqid=3D%"PRIu16", vector=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRI= u16", ien=3D%d" +pci_nvme_del_sq(uint16_t qid) "deleting submission queue sqid=3D%"PRIu16"" +pci_nvme_del_cq(uint16_t cqid) "deleted completion queue, cqid=3D%"PRIu16"" +pci_nvme_identify(uint16_t cid, uint8_t cns, uint16_t ctrlid, uint8_t csi)= "cid %"PRIu16" cns 0x%"PRIx8" ctrlid %"PRIu16" csi 0x%"PRIx8"" +pci_nvme_identify_ctrl(void) "identify controller" +pci_nvme_identify_ctrl_csi(uint8_t csi) "identify controller, csi=3D0x%"PR= Ix8"" +pci_nvme_identify_ns(uint32_t ns) "nsid %"PRIu32"" +pci_nvme_identify_ns_attached_list(uint16_t cntid) "cntid=3D%"PRIu16"" +pci_nvme_identify_ns_csi(uint32_t ns, uint8_t csi) "nsid=3D%"PRIu32", csi= =3D0x%"PRIx8"" +pci_nvme_identify_nslist(uint32_t ns) "nsid %"PRIu32"" +pci_nvme_identify_nslist_csi(uint16_t ns, uint8_t csi) "nsid=3D%"PRIu16", = csi=3D0x%"PRIx8"" +pci_nvme_identify_cmd_set(void) "identify i/o command set" +pci_nvme_identify_ns_descr_list(uint32_t ns) "nsid %"PRIu32"" +pci_nvme_get_log(uint16_t cid, uint8_t lid, uint8_t lsp, uint8_t rae, uint= 32_t len, uint64_t off) "cid %"PRIu16" lid 0x%"PRIx8" lsp 0x%"PRIx8" rae 0x= %"PRIx8" len %"PRIu32" off %"PRIu64"" +pci_nvme_getfeat(uint16_t cid, uint32_t nsid, uint8_t fid, uint8_t sel, ui= nt32_t cdw11) "cid %"PRIu16" nsid 0x%"PRIx32" fid 0x%"PRIx8" sel 0x%"PRIx8"= cdw11 0x%"PRIx32"" +pci_nvme_setfeat(uint16_t cid, uint32_t nsid, uint8_t fid, uint8_t save, u= int32_t cdw11) "cid %"PRIu16" nsid 0x%"PRIx32" fid 0x%"PRIx8" save 0x%"PRIx= 8" cdw11 0x%"PRIx32"" +pci_nvme_getfeat_vwcache(const char* result) "get feature volatile write c= ache, result=3D%s" +pci_nvme_getfeat_numq(int result) "get feature number of queues, result=3D= %d" +pci_nvme_setfeat_numq(int reqcq, int reqsq, int gotcq, int gotsq) "request= ed cq_count=3D%d sq_count=3D%d, responding with cq_count=3D%d sq_count=3D%d" +pci_nvme_setfeat_timestamp(uint64_t ts) "set feature timestamp =3D 0x%"PRI= x64"" +pci_nvme_getfeat_timestamp(uint64_t ts) "get feature timestamp =3D 0x%"PRI= x64"" +pci_nvme_process_aers(int queued) "queued %d" +pci_nvme_aer(uint16_t cid) "cid %"PRIu16"" +pci_nvme_aer_aerl_exceeded(void) "aerl exceeded" +pci_nvme_aer_masked(uint8_t type, uint8_t mask) "type 0x%"PRIx8" mask 0x%"= PRIx8"" +pci_nvme_aer_post_cqe(uint8_t typ, uint8_t info, uint8_t log_page) "type 0= x%"PRIx8" info 0x%"PRIx8" lid 0x%"PRIx8"" +pci_nvme_ns_attachment(uint16_t cid, uint8_t sel) "cid %"PRIu16", sel=3D0x= %"PRIx8"" +pci_nvme_ns_attachment_attach(uint16_t cntlid, uint32_t nsid) "cntlid=3D0x= %"PRIx16", nsid=3D0x%"PRIx32"" +pci_nvme_enqueue_event(uint8_t typ, uint8_t info, uint8_t log_page) "type = 0x%"PRIx8" info 0x%"PRIx8" lid 0x%"PRIx8"" +pci_nvme_enqueue_event_noqueue(int queued) "queued %d" +pci_nvme_enqueue_event_masked(uint8_t typ) "type 0x%"PRIx8"" +pci_nvme_no_outstanding_aers(void) "ignoring event; no outstanding AERs" +pci_nvme_enqueue_req_completion(uint16_t cid, uint16_t cqid, uint16_t stat= us) "cid %"PRIu16" cqid %"PRIu16" status 0x%"PRIx16"" +pci_nvme_mmio_read(uint64_t addr, unsigned size) "addr 0x%"PRIx64" size %d" +pci_nvme_mmio_write(uint64_t addr, uint64_t data, unsigned size) "addr 0x%= "PRIx64" data 0x%"PRIx64" size %d" +pci_nvme_mmio_doorbell_cq(uint16_t cqid, uint16_t new_head) "cqid %"PRIu16= " new_head %"PRIu16"" +pci_nvme_mmio_doorbell_sq(uint16_t sqid, uint16_t new_tail) "sqid %"PRIu16= " new_tail %"PRIu16"" +pci_nvme_mmio_intm_set(uint64_t data, uint64_t new_mask) "wrote MMIO, inte= rrupt mask set, data=3D0x%"PRIx64", new_mask=3D0x%"PRIx64"" +pci_nvme_mmio_intm_clr(uint64_t data, uint64_t new_mask) "wrote MMIO, inte= rrupt mask clr, data=3D0x%"PRIx64", new_mask=3D0x%"PRIx64"" +pci_nvme_mmio_cfg(uint64_t data) "wrote MMIO, config controller config=3D0= x%"PRIx64"" +pci_nvme_mmio_aqattr(uint64_t data) "wrote MMIO, admin queue attributes=3D= 0x%"PRIx64"" +pci_nvme_mmio_asqaddr(uint64_t data) "wrote MMIO, admin submission queue a= ddress=3D0x%"PRIx64"" +pci_nvme_mmio_acqaddr(uint64_t data) "wrote MMIO, admin completion queue a= ddress=3D0x%"PRIx64"" +pci_nvme_mmio_asqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, ad= min submission queue high half=3D0x%"PRIx64", new_address=3D0x%"PRIx64"" +pci_nvme_mmio_acqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, ad= min completion queue high half=3D0x%"PRIx64", new_address=3D0x%"PRIx64"" +pci_nvme_mmio_start_success(void) "setting controller enable bit succeeded" +pci_nvme_mmio_stopped(void) "cleared controller enable bit" +pci_nvme_mmio_shutdown_set(void) "shutdown bit set" +pci_nvme_mmio_shutdown_cleared(void) "shutdown bit cleared" +pci_nvme_open_zone(uint64_t slba, uint32_t zone_idx, int all) "open zone, = slba=3D%"PRIu64", idx=3D%"PRIu32", all=3D%"PRIi32"" +pci_nvme_close_zone(uint64_t slba, uint32_t zone_idx, int all) "close zone= , slba=3D%"PRIu64", idx=3D%"PRIu32", all=3D%"PRIi32"" +pci_nvme_finish_zone(uint64_t slba, uint32_t zone_idx, int all) "finish zo= ne, slba=3D%"PRIu64", idx=3D%"PRIu32", all=3D%"PRIi32"" +pci_nvme_reset_zone(uint64_t slba, uint32_t zone_idx, int all) "reset zone= , slba=3D%"PRIu64", idx=3D%"PRIu32", all=3D%"PRIi32"" +pci_nvme_offline_zone(uint64_t slba, uint32_t zone_idx, int all) "offline = zone, slba=3D%"PRIu64", idx=3D%"PRIu32", all=3D%"PRIi32"" +pci_nvme_set_descriptor_extension(uint64_t slba, uint32_t zone_idx) "set z= one descriptor extension, slba=3D%"PRIu64", idx=3D%"PRIu32"" +pci_nvme_zd_extension_set(uint32_t zone_idx) "set descriptor extension for= zone_idx=3D%"PRIu32"" +pci_nvme_clear_ns_close(uint32_t state, uint64_t slba) "zone state=3D%"PRI= u32", slba=3D%"PRIu64" transitioned to Closed state" +pci_nvme_clear_ns_reset(uint32_t state, uint64_t slba) "zone state=3D%"PRI= u32", slba=3D%"PRIu64" transitioned to Empty state" + +# error conditions +pci_nvme_err_mdts(size_t len) "len %zu" +pci_nvme_err_zasl(size_t len) "len %zu" +pci_nvme_err_req_status(uint16_t cid, uint32_t nsid, uint16_t status, uint= 8_t opc) "cid %"PRIu16" nsid %"PRIu32" status 0x%"PRIx16" opc 0x%"PRIx8"" +pci_nvme_err_addr_read(uint64_t addr) "addr 0x%"PRIx64"" +pci_nvme_err_addr_write(uint64_t addr) "addr 0x%"PRIx64"" +pci_nvme_err_cfs(void) "controller fatal status" +pci_nvme_err_aio(uint16_t cid, const char *errname, uint16_t status) "cid = %"PRIu16" err '%s' status 0x%"PRIx16"" +pci_nvme_err_copy_invalid_format(uint8_t format) "format 0x%"PRIx8"" +pci_nvme_err_invalid_sgld(uint16_t cid, uint8_t typ) "cid %"PRIu16" type 0= x%"PRIx8"" +pci_nvme_err_invalid_num_sgld(uint16_t cid, uint8_t typ) "cid %"PRIu16" ty= pe 0x%"PRIx8"" +pci_nvme_err_invalid_sgl_excess_length(uint32_t residual) "residual %"PRIu= 32"" +pci_nvme_err_invalid_dma(void) "PRP/SGL is too small for transfer size" +pci_nvme_err_invalid_prplist_ent(uint64_t prplist) "PRP list entry is not = page aligned: 0x%"PRIx64"" +pci_nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is not page aligned: = 0x%"PRIx64"" +pci_nvme_err_invalid_opc(uint8_t opc) "invalid opcode 0x%"PRIx8"" +pci_nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin opcode 0x%"PRIx= 8"" +pci_nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limi= t) "Invalid LBA start=3D%"PRIu64" len=3D%"PRIu64" limit=3D%"PRIu64"" +pci_nvme_err_invalid_log_page_offset(uint64_t ofs, uint64_t size) "must be= <=3D %"PRIu64", got %"PRIu64"" +pci_nvme_err_cmb_invalid_cba(uint64_t cmbmsc) "cmbmsc 0x%"PRIx64"" +pci_nvme_err_cmb_not_enabled(uint64_t cmbmsc) "cmbmsc 0x%"PRIx64"" +pci_nvme_err_unaligned_zone_cmd(uint8_t action, uint64_t slba, uint64_t zs= lba) "unaligned zone op 0x%"PRIx32", got slba=3D%"PRIu64", zslba=3D%"PRIu64= "" +pci_nvme_err_invalid_zone_state_transition(uint8_t action, uint64_t slba, = uint8_t attrs) "action=3D0x%"PRIx8", slba=3D%"PRIu64", attrs=3D0x%"PRIx32"" +pci_nvme_err_write_not_at_wp(uint64_t slba, uint64_t zone, uint64_t wp) "w= riting at slba=3D%"PRIu64", zone=3D%"PRIu64", but wp=3D%"PRIu64"" +pci_nvme_err_append_not_at_start(uint64_t slba, uint64_t zone) "appending = at slba=3D%"PRIu64", but zone=3D%"PRIu64"" +pci_nvme_err_zone_is_full(uint64_t zslba) "zslba 0x%"PRIx64"" +pci_nvme_err_zone_is_read_only(uint64_t zslba) "zslba 0x%"PRIx64"" +pci_nvme_err_zone_is_offline(uint64_t zslba) "zslba 0x%"PRIx64"" +pci_nvme_err_zone_boundary(uint64_t slba, uint32_t nlb, uint64_t zcap) "lb= a 0x%"PRIx64" nlb %"PRIu32" zcap 0x%"PRIx64"" +pci_nvme_err_zone_invalid_write(uint64_t slba, uint64_t wp) "lba 0x%"PRIx6= 4" wp 0x%"PRIx64"" +pci_nvme_err_zone_write_not_ok(uint64_t slba, uint32_t nlb, uint16_t statu= s) "slba=3D%"PRIu64", nlb=3D%"PRIu32", status=3D0x%"PRIx16"" +pci_nvme_err_zone_read_not_ok(uint64_t slba, uint32_t nlb, uint16_t status= ) "slba=3D%"PRIu64", nlb=3D%"PRIu32", status=3D0x%"PRIx16"" +pci_nvme_err_insuff_active_res(uint32_t max_active) "max_active=3D%"PRIu32= " zone limit exceeded" +pci_nvme_err_insuff_open_res(uint32_t max_open) "max_open=3D%"PRIu32" zone= limit exceeded" +pci_nvme_err_zd_extension_map_error(uint32_t zone_idx) "can't map descript= or extension for zone_idx=3D%"PRIu32"" +pci_nvme_err_invalid_iocsci(uint32_t idx) "unsupported command set combina= tion index %"PRIu32"" +pci_nvme_err_invalid_del_sq(uint16_t qid) "invalid submission queue deleti= on, sid=3D%"PRIu16"" +pci_nvme_err_invalid_create_sq_cqid(uint16_t cqid) "failed creating submis= sion queue, invalid cqid=3D%"PRIu16"" +pci_nvme_err_invalid_create_sq_sqid(uint16_t sqid) "failed creating submis= sion queue, invalid sqid=3D%"PRIu16"" +pci_nvme_err_invalid_create_sq_size(uint16_t qsize) "failed creating submi= ssion queue, invalid qsize=3D%"PRIu16"" +pci_nvme_err_invalid_create_sq_addr(uint64_t addr) "failed creating submis= sion queue, addr=3D0x%"PRIx64"" +pci_nvme_err_invalid_create_sq_qflags(uint16_t qflags) "failed creating su= bmission queue, qflags=3D%"PRIu16"" +pci_nvme_err_invalid_del_cq_cqid(uint16_t cqid) "failed deleting completio= n queue, cqid=3D%"PRIu16"" +pci_nvme_err_invalid_del_cq_notempty(uint16_t cqid) "failed deleting compl= etion queue, it is not empty, cqid=3D%"PRIu16"" +pci_nvme_err_invalid_create_cq_cqid(uint16_t cqid) "failed creating comple= tion queue, cqid=3D%"PRIu16"" +pci_nvme_err_invalid_create_cq_size(uint16_t size) "failed creating comple= tion queue, size=3D%"PRIu16"" +pci_nvme_err_invalid_create_cq_addr(uint64_t addr) "failed creating comple= tion queue, addr=3D0x%"PRIx64"" +pci_nvme_err_invalid_create_cq_vector(uint16_t vector) "failed creating co= mpletion queue, vector=3D%"PRIu16"" +pci_nvme_err_invalid_create_cq_qflags(uint16_t qflags) "failed creating co= mpletion queue, qflags=3D%"PRIu16"" +pci_nvme_err_invalid_identify_cns(uint16_t cns) "identify, invalid cns=3D0= x%"PRIx16"" +pci_nvme_err_invalid_getfeat(int dw10) "invalid get features, dw10=3D0x%"P= RIx32"" +pci_nvme_err_invalid_setfeat(uint32_t dw10) "invalid set features, dw10=3D= 0x%"PRIx32"" +pci_nvme_err_invalid_log_page(uint16_t cid, uint16_t lid) "cid %"PRIu16" l= id 0x%"PRIx16"" +pci_nvme_err_startfail_cq(void) "nvme_start_ctrl failed because there are = non-admin completion queues" +pci_nvme_err_startfail_sq(void) "nvme_start_ctrl failed because there are = non-admin submission queues" +pci_nvme_err_startfail_nbarasq(void) "nvme_start_ctrl failed because the a= dmin submission queue address is null" +pci_nvme_err_startfail_nbaracq(void) "nvme_start_ctrl failed because the a= dmin completion queue address is null" +pci_nvme_err_startfail_asq_misaligned(uint64_t addr) "nvme_start_ctrl fail= ed because the admin submission queue address is misaligned: 0x%"PRIx64"" +pci_nvme_err_startfail_acq_misaligned(uint64_t addr) "nvme_start_ctrl fail= ed because the admin completion queue address is misaligned: 0x%"PRIx64"" +pci_nvme_err_startfail_page_too_small(uint8_t log2ps, uint8_t maxlog2ps) "= nvme_start_ctrl failed because the page size is too small: log2size=3D%u, m= in=3D%u" +pci_nvme_err_startfail_page_too_large(uint8_t log2ps, uint8_t maxlog2ps) "= nvme_start_ctrl failed because the page size is too large: log2size=3D%u, m= ax=3D%u" +pci_nvme_err_startfail_cqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the completion queue entry size is too smal= l: log2size=3D%u, min=3D%u" +pci_nvme_err_startfail_cqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the completion queue entry size is too larg= e: log2size=3D%u, max=3D%u" +pci_nvme_err_startfail_sqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the submission queue entry size is too smal= l: log2size=3D%u, min=3D%u" +pci_nvme_err_startfail_sqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the submission queue entry size is too larg= e: log2size=3D%u, max=3D%u" +pci_nvme_err_startfail_css(uint8_t css) "nvme_start_ctrl failed because in= valid command set selected:%u" +pci_nvme_err_startfail_asqent_sz_zero(void) "nvme_start_ctrl failed becaus= e the admin submission queue size is zero" +pci_nvme_err_startfail_acqent_sz_zero(void) "nvme_start_ctrl failed becaus= e the admin completion queue size is zero" +pci_nvme_err_startfail_zasl_too_small(uint32_t zasl, uint32_t pagesz) "nvm= e_start_ctrl failed because zone append size limit %"PRIu32" is too small, = needs to be >=3D %"PRIu32"" +pci_nvme_err_startfail(void) "setting controller enable bit failed" +pci_nvme_err_invalid_mgmt_action(uint8_t action) "action=3D0x%"PRIx8"" + +# undefined behavior +pci_nvme_ub_mmiowr_misaligned32(uint64_t offset) "MMIO write not 32-bit al= igned, offset=3D0x%"PRIx64"" +pci_nvme_ub_mmiowr_toosmall(uint64_t offset, unsigned size) "MMIO write sm= aller than 32 bits, offset=3D0x%"PRIx64", size=3D%u" +pci_nvme_ub_mmiowr_intmask_with_msix(void) "undefined access to interrupt = mask set when MSI-X is enabled" +pci_nvme_ub_mmiowr_ro_csts(void) "attempted to set a read only bit of cont= roller status" +pci_nvme_ub_mmiowr_ssreset_w1c_unsupported(void) "attempted to W1C CSTS.NS= SRO but CAP.NSSRS is zero (not supported)" +pci_nvme_ub_mmiowr_ssreset_unsupported(void) "attempted NVM subsystem rese= t but CAP.NSSRS is zero (not supported)" +pci_nvme_ub_mmiowr_cmbloc_reserved(void) "invalid write to reserved CMBLOC= when CMBSZ is zero, ignored" +pci_nvme_ub_mmiowr_cmbsz_readonly(void) "invalid write to read only CMBSZ,= ignored" +pci_nvme_ub_mmiowr_pmrcap_readonly(void) "invalid write to read only PMRCA= P, ignored" +pci_nvme_ub_mmiowr_pmrsts_readonly(void) "invalid write to read only PMRST= S, ignored" +pci_nvme_ub_mmiowr_pmrebs_readonly(void) "invalid write to read only PMREB= S, ignored" +pci_nvme_ub_mmiowr_pmrswtp_readonly(void) "invalid write to read only PMRS= WTP, ignored" +pci_nvme_ub_mmiowr_invalid(uint64_t offset, uint64_t data) "invalid MMIO w= rite, offset=3D0x%"PRIx64", data=3D0x%"PRIx64"" +pci_nvme_ub_mmiord_misaligned32(uint64_t offset) "MMIO read not 32-bit ali= gned, offset=3D0x%"PRIx64"" +pci_nvme_ub_mmiord_toosmall(uint64_t offset) "MMIO read smaller than 32-bi= ts, offset=3D0x%"PRIx64"" +pci_nvme_ub_mmiord_invalid_ofs(uint64_t offset) "MMIO read beyond last reg= ister, offset=3D0x%"PRIx64", returning 0" +pci_nvme_ub_db_wr_misaligned(uint64_t offset) "doorbell write not 32-bit a= ligned, offset=3D0x%"PRIx64", ignoring" +pci_nvme_ub_db_wr_invalid_cq(uint32_t qid) "completion queue doorbell writ= e for nonexistent queue, cqid=3D%"PRIu32", ignoring" +pci_nvme_ub_db_wr_invalid_cqhead(uint32_t qid, uint16_t new_head) "complet= ion queue doorbell write value beyond queue size, cqid=3D%"PRIu32", new_hea= d=3D%"PRIu16", ignoring" +pci_nvme_ub_db_wr_invalid_sq(uint32_t qid) "submission queue doorbell writ= e for nonexistent queue, sqid=3D%"PRIu32", ignoring" +pci_nvme_ub_db_wr_invalid_sqtail(uint32_t qid, uint16_t new_tail) "submiss= ion queue doorbell write value beyond queue size, sqid=3D%"PRIu32", new_hea= d=3D%"PRIu16", ignoring" +pci_nvme_ub_unknown_css_value(void) "unknown value in cc.css field" --=20 2.31.1